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PIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x168 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x0 Bytes (0x0)
size : 0x168 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x0 Bytes (0x0)
size : 0x168 byte (0x0)
mem_usage : registers
protection :

Registers

PIO_PER

PER

PIO_OER

OER

PIO_SCHMITT

SCHMITT

PIO_DRIVER

DRIVER

PIO_ODR

ODR

PIO_PCMR

PCMR

PIO_PCIER

PCIER

PIO_PCIDR

PCIDR

PIO_PCIMR

PCIMR

PIO_PCISR

PCISR

PIO_PCRHR

PCRHR

PIO_OSR

OSR

PIO_IFER

IFER

PIO_IFDR

IFDR

PIO_IFSR

IFSR

PIO_SODR

SODR

PIO_CODR

CODR

PIO_ODSR

ODSR

PIO_PDSR

PDSR

PIO_PDR

PDR

PIO_IER

IER

PIO_IDR

IDR

PIO_IMR

IMR

PIO_ISR

ISR

PIO_MDER

MDER

PIO_MDDR

MDDR

PIO_MDSR

MDSR

PIO_PUDR

PUDR

PIO_PUER

PUER

PIO_PUSR

PUSR

PIO_ABCDSR0

ABCDSR0

PIO_ABCDSR1

ABCDSR1

PIO_PSR

PSR

PIO_IFSCDR

IFSCDR

PIO_IFSCER

IFSCER

PIO_IFSCSR

IFSCSR

PIO_SCDR

SCDR

PIO_PPDDR

PPDDR

PIO_PPDER

PPDER

PIO_PPDSR

PPDSR

PIO_OWER

OWER

PIO_OWDR

OWDR

PIO_OWSR

OWSR

PIO_AIMER

AIMER

PIO_AIMDR

AIMDR

PIO_AIMMR

AIMMR

PIO_ESR

ESR

PIO_LSR

LSR

PIO_ELSR

ELSR

PIO_FELLSR

FELLSR

PIO_REHLSR

REHLSR

PIO_FRLHSR

FRLHSR

PIO_LOCKSR

LOCKSR

PIO_WPMR

WPMR

PIO_WPSR

WPSR

VERSION


PIO_PER

PIO Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_PER PIO_PER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : PIO Enable
bits : 0 - 0 (1 bit)

P1 : PIO Enable
bits : 1 - 1 (1 bit)

P2 : PIO Enable
bits : 2 - 2 (1 bit)

P3 : PIO Enable
bits : 3 - 3 (1 bit)

P4 : PIO Enable
bits : 4 - 4 (1 bit)

P5 : PIO Enable
bits : 5 - 5 (1 bit)

P6 : PIO Enable
bits : 6 - 6 (1 bit)

P7 : PIO Enable
bits : 7 - 7 (1 bit)

P8 : PIO Enable
bits : 8 - 8 (1 bit)

P9 : PIO Enable
bits : 9 - 9 (1 bit)

P10 : PIO Enable
bits : 10 - 10 (1 bit)

P11 : PIO Enable
bits : 11 - 11 (1 bit)

P12 : PIO Enable
bits : 12 - 12 (1 bit)

P13 : PIO Enable
bits : 13 - 13 (1 bit)

P14 : PIO Enable
bits : 14 - 14 (1 bit)

P15 : PIO Enable
bits : 15 - 15 (1 bit)

P16 : PIO Enable
bits : 16 - 16 (1 bit)

P17 : PIO Enable
bits : 17 - 17 (1 bit)

P18 : PIO Enable
bits : 18 - 18 (1 bit)

P19 : PIO Enable
bits : 19 - 19 (1 bit)

P20 : PIO Enable
bits : 20 - 20 (1 bit)

P21 : PIO Enable
bits : 21 - 21 (1 bit)

P22 : PIO Enable
bits : 22 - 22 (1 bit)

P23 : PIO Enable
bits : 23 - 23 (1 bit)

P24 : PIO Enable
bits : 24 - 24 (1 bit)

P25 : PIO Enable
bits : 25 - 25 (1 bit)

P26 : PIO Enable
bits : 26 - 26 (1 bit)

P27 : PIO Enable
bits : 27 - 27 (1 bit)

P28 : PIO Enable
bits : 28 - 28 (1 bit)

P29 : PIO Enable
bits : 29 - 29 (1 bit)

P30 : PIO Enable
bits : 30 - 30 (1 bit)

P31 : PIO Enable
bits : 31 - 31 (1 bit)


PER

PIO Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PER PER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : PIO Enable
bits : 0 - 0 (1 bit)
access : write-only

P1 : PIO Enable
bits : 1 - 1 (1 bit)
access : write-only

P2 : PIO Enable
bits : 2 - 2 (1 bit)
access : write-only

P3 : PIO Enable
bits : 3 - 3 (1 bit)
access : write-only

P4 : PIO Enable
bits : 4 - 4 (1 bit)
access : write-only

P5 : PIO Enable
bits : 5 - 5 (1 bit)
access : write-only

P6 : PIO Enable
bits : 6 - 6 (1 bit)
access : write-only

P7 : PIO Enable
bits : 7 - 7 (1 bit)
access : write-only

P8 : PIO Enable
bits : 8 - 8 (1 bit)
access : write-only

P9 : PIO Enable
bits : 9 - 9 (1 bit)
access : write-only

P10 : PIO Enable
bits : 10 - 10 (1 bit)
access : write-only

P11 : PIO Enable
bits : 11 - 11 (1 bit)
access : write-only

P12 : PIO Enable
bits : 12 - 12 (1 bit)
access : write-only

P13 : PIO Enable
bits : 13 - 13 (1 bit)
access : write-only

P14 : PIO Enable
bits : 14 - 14 (1 bit)
access : write-only

P15 : PIO Enable
bits : 15 - 15 (1 bit)
access : write-only

P16 : PIO Enable
bits : 16 - 16 (1 bit)
access : write-only

P17 : PIO Enable
bits : 17 - 17 (1 bit)
access : write-only

P18 : PIO Enable
bits : 18 - 18 (1 bit)
access : write-only

P19 : PIO Enable
bits : 19 - 19 (1 bit)
access : write-only

P20 : PIO Enable
bits : 20 - 20 (1 bit)
access : write-only

P21 : PIO Enable
bits : 21 - 21 (1 bit)
access : write-only

P22 : PIO Enable
bits : 22 - 22 (1 bit)
access : write-only

P23 : PIO Enable
bits : 23 - 23 (1 bit)
access : write-only

P24 : PIO Enable
bits : 24 - 24 (1 bit)
access : write-only

P25 : PIO Enable
bits : 25 - 25 (1 bit)
access : write-only

P26 : PIO Enable
bits : 26 - 26 (1 bit)
access : write-only

P27 : PIO Enable
bits : 27 - 27 (1 bit)
access : write-only

P28 : PIO Enable
bits : 28 - 28 (1 bit)
access : write-only

P29 : PIO Enable
bits : 29 - 29 (1 bit)
access : write-only

P30 : PIO Enable
bits : 30 - 30 (1 bit)
access : write-only

P31 : PIO Enable
bits : 31 - 31 (1 bit)
access : write-only


PIO_OER

Output Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_OER PIO_OER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Output Enable
bits : 0 - 0 (1 bit)

P1 : Output Enable
bits : 1 - 1 (1 bit)

P2 : Output Enable
bits : 2 - 2 (1 bit)

P3 : Output Enable
bits : 3 - 3 (1 bit)

P4 : Output Enable
bits : 4 - 4 (1 bit)

P5 : Output Enable
bits : 5 - 5 (1 bit)

P6 : Output Enable
bits : 6 - 6 (1 bit)

P7 : Output Enable
bits : 7 - 7 (1 bit)

P8 : Output Enable
bits : 8 - 8 (1 bit)

P9 : Output Enable
bits : 9 - 9 (1 bit)

P10 : Output Enable
bits : 10 - 10 (1 bit)

P11 : Output Enable
bits : 11 - 11 (1 bit)

P12 : Output Enable
bits : 12 - 12 (1 bit)

P13 : Output Enable
bits : 13 - 13 (1 bit)

P14 : Output Enable
bits : 14 - 14 (1 bit)

P15 : Output Enable
bits : 15 - 15 (1 bit)

P16 : Output Enable
bits : 16 - 16 (1 bit)

P17 : Output Enable
bits : 17 - 17 (1 bit)

P18 : Output Enable
bits : 18 - 18 (1 bit)

P19 : Output Enable
bits : 19 - 19 (1 bit)

P20 : Output Enable
bits : 20 - 20 (1 bit)

P21 : Output Enable
bits : 21 - 21 (1 bit)

P22 : Output Enable
bits : 22 - 22 (1 bit)

P23 : Output Enable
bits : 23 - 23 (1 bit)

P24 : Output Enable
bits : 24 - 24 (1 bit)

P25 : Output Enable
bits : 25 - 25 (1 bit)

P26 : Output Enable
bits : 26 - 26 (1 bit)

P27 : Output Enable
bits : 27 - 27 (1 bit)

P28 : Output Enable
bits : 28 - 28 (1 bit)

P29 : Output Enable
bits : 29 - 29 (1 bit)

P30 : Output Enable
bits : 30 - 30 (1 bit)

P31 : Output Enable
bits : 31 - 31 (1 bit)


OER

Output Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OER OER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Output Enable
bits : 0 - 0 (1 bit)
access : write-only

P1 : Output Enable
bits : 1 - 1 (1 bit)
access : write-only

P2 : Output Enable
bits : 2 - 2 (1 bit)
access : write-only

P3 : Output Enable
bits : 3 - 3 (1 bit)
access : write-only

P4 : Output Enable
bits : 4 - 4 (1 bit)
access : write-only

P5 : Output Enable
bits : 5 - 5 (1 bit)
access : write-only

P6 : Output Enable
bits : 6 - 6 (1 bit)
access : write-only

P7 : Output Enable
bits : 7 - 7 (1 bit)
access : write-only

P8 : Output Enable
bits : 8 - 8 (1 bit)
access : write-only

P9 : Output Enable
bits : 9 - 9 (1 bit)
access : write-only

P10 : Output Enable
bits : 10 - 10 (1 bit)
access : write-only

P11 : Output Enable
bits : 11 - 11 (1 bit)
access : write-only

P12 : Output Enable
bits : 12 - 12 (1 bit)
access : write-only

P13 : Output Enable
bits : 13 - 13 (1 bit)
access : write-only

P14 : Output Enable
bits : 14 - 14 (1 bit)
access : write-only

P15 : Output Enable
bits : 15 - 15 (1 bit)
access : write-only

P16 : Output Enable
bits : 16 - 16 (1 bit)
access : write-only

P17 : Output Enable
bits : 17 - 17 (1 bit)
access : write-only

P18 : Output Enable
bits : 18 - 18 (1 bit)
access : write-only

P19 : Output Enable
bits : 19 - 19 (1 bit)
access : write-only

P20 : Output Enable
bits : 20 - 20 (1 bit)
access : write-only

P21 : Output Enable
bits : 21 - 21 (1 bit)
access : write-only

P22 : Output Enable
bits : 22 - 22 (1 bit)
access : write-only

P23 : Output Enable
bits : 23 - 23 (1 bit)
access : write-only

P24 : Output Enable
bits : 24 - 24 (1 bit)
access : write-only

P25 : Output Enable
bits : 25 - 25 (1 bit)
access : write-only

P26 : Output Enable
bits : 26 - 26 (1 bit)
access : write-only

P27 : Output Enable
bits : 27 - 27 (1 bit)
access : write-only

P28 : Output Enable
bits : 28 - 28 (1 bit)
access : write-only

P29 : Output Enable
bits : 29 - 29 (1 bit)
access : write-only

P30 : Output Enable
bits : 30 - 30 (1 bit)
access : write-only

P31 : Output Enable
bits : 31 - 31 (1 bit)
access : write-only


PIO_SCHMITT

Schmitt Trigger Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO_SCHMITT PIO_SCHMITT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCHMITT0 SCHMITT1 SCHMITT2 SCHMITT3 SCHMITT4 SCHMITT5 SCHMITT6 SCHMITT7 SCHMITT8 SCHMITT9 SCHMITT10 SCHMITT11 SCHMITT12 SCHMITT13 SCHMITT14 SCHMITT15 SCHMITT16 SCHMITT17 SCHMITT18 SCHMITT19 SCHMITT20 SCHMITT21 SCHMITT22 SCHMITT23 SCHMITT24 SCHMITT25 SCHMITT26 SCHMITT27 SCHMITT28 SCHMITT29 SCHMITT30 SCHMITT31

SCHMITT0 : Schmitt Trigger Control
bits : 0 - 0 (1 bit)

SCHMITT1 : Schmitt Trigger Control
bits : 1 - 1 (1 bit)

SCHMITT2 : Schmitt Trigger Control
bits : 2 - 2 (1 bit)

SCHMITT3 : Schmitt Trigger Control
bits : 3 - 3 (1 bit)

SCHMITT4 : Schmitt Trigger Control
bits : 4 - 4 (1 bit)

SCHMITT5 : Schmitt Trigger Control
bits : 5 - 5 (1 bit)

SCHMITT6 : Schmitt Trigger Control
bits : 6 - 6 (1 bit)

SCHMITT7 : Schmitt Trigger Control
bits : 7 - 7 (1 bit)

SCHMITT8 : Schmitt Trigger Control
bits : 8 - 8 (1 bit)

SCHMITT9 : Schmitt Trigger Control
bits : 9 - 9 (1 bit)

SCHMITT10 : Schmitt Trigger Control
bits : 10 - 10 (1 bit)

SCHMITT11 : Schmitt Trigger Control
bits : 11 - 11 (1 bit)

SCHMITT12 : Schmitt Trigger Control
bits : 12 - 12 (1 bit)

SCHMITT13 : Schmitt Trigger Control
bits : 13 - 13 (1 bit)

SCHMITT14 : Schmitt Trigger Control
bits : 14 - 14 (1 bit)

SCHMITT15 : Schmitt Trigger Control
bits : 15 - 15 (1 bit)

SCHMITT16 : Schmitt Trigger Control
bits : 16 - 16 (1 bit)

SCHMITT17 : Schmitt Trigger Control
bits : 17 - 17 (1 bit)

SCHMITT18 : Schmitt Trigger Control
bits : 18 - 18 (1 bit)

SCHMITT19 : Schmitt Trigger Control
bits : 19 - 19 (1 bit)

SCHMITT20 : Schmitt Trigger Control
bits : 20 - 20 (1 bit)

SCHMITT21 : Schmitt Trigger Control
bits : 21 - 21 (1 bit)

SCHMITT22 : Schmitt Trigger Control
bits : 22 - 22 (1 bit)

SCHMITT23 : Schmitt Trigger Control
bits : 23 - 23 (1 bit)

SCHMITT24 : Schmitt Trigger Control
bits : 24 - 24 (1 bit)

SCHMITT25 : Schmitt Trigger Control
bits : 25 - 25 (1 bit)

SCHMITT26 : Schmitt Trigger Control
bits : 26 - 26 (1 bit)

SCHMITT27 : Schmitt Trigger Control
bits : 27 - 27 (1 bit)

SCHMITT28 : Schmitt Trigger Control
bits : 28 - 28 (1 bit)

SCHMITT29 : Schmitt Trigger Control
bits : 29 - 29 (1 bit)

SCHMITT30 : Schmitt Trigger Control
bits : 30 - 30 (1 bit)

SCHMITT31 : Schmitt Trigger Control
bits : 31 - 31 (1 bit)


SCHMITT

Schmitt Trigger Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCHMITT SCHMITT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCHMITT0 SCHMITT1 SCHMITT2 SCHMITT3 SCHMITT4 SCHMITT5 SCHMITT6 SCHMITT7 SCHMITT8 SCHMITT9 SCHMITT10 SCHMITT11 SCHMITT12 SCHMITT13 SCHMITT14 SCHMITT15 SCHMITT16 SCHMITT17 SCHMITT18 SCHMITT19 SCHMITT20 SCHMITT21 SCHMITT22 SCHMITT23 SCHMITT24 SCHMITT25 SCHMITT26 SCHMITT27 SCHMITT28 SCHMITT29 SCHMITT30 SCHMITT31

SCHMITT0 : Schmitt Trigger Control
bits : 0 - 0 (1 bit)
access : read-write

SCHMITT1 : Schmitt Trigger Control
bits : 1 - 1 (1 bit)
access : read-write

SCHMITT2 : Schmitt Trigger Control
bits : 2 - 2 (1 bit)
access : read-write

SCHMITT3 : Schmitt Trigger Control
bits : 3 - 3 (1 bit)
access : read-write

SCHMITT4 : Schmitt Trigger Control
bits : 4 - 4 (1 bit)
access : read-write

SCHMITT5 : Schmitt Trigger Control
bits : 5 - 5 (1 bit)
access : read-write

SCHMITT6 : Schmitt Trigger Control
bits : 6 - 6 (1 bit)
access : read-write

SCHMITT7 : Schmitt Trigger Control
bits : 7 - 7 (1 bit)
access : read-write

SCHMITT8 : Schmitt Trigger Control
bits : 8 - 8 (1 bit)
access : read-write

SCHMITT9 : Schmitt Trigger Control
bits : 9 - 9 (1 bit)
access : read-write

SCHMITT10 : Schmitt Trigger Control
bits : 10 - 10 (1 bit)
access : read-write

SCHMITT11 : Schmitt Trigger Control
bits : 11 - 11 (1 bit)
access : read-write

SCHMITT12 : Schmitt Trigger Control
bits : 12 - 12 (1 bit)
access : read-write

SCHMITT13 : Schmitt Trigger Control
bits : 13 - 13 (1 bit)
access : read-write

SCHMITT14 : Schmitt Trigger Control
bits : 14 - 14 (1 bit)
access : read-write

SCHMITT15 : Schmitt Trigger Control
bits : 15 - 15 (1 bit)
access : read-write

SCHMITT16 : Schmitt Trigger Control
bits : 16 - 16 (1 bit)
access : read-write

SCHMITT17 : Schmitt Trigger Control
bits : 17 - 17 (1 bit)
access : read-write

SCHMITT18 : Schmitt Trigger Control
bits : 18 - 18 (1 bit)
access : read-write

SCHMITT19 : Schmitt Trigger Control
bits : 19 - 19 (1 bit)
access : read-write

SCHMITT20 : Schmitt Trigger Control
bits : 20 - 20 (1 bit)
access : read-write

SCHMITT21 : Schmitt Trigger Control
bits : 21 - 21 (1 bit)
access : read-write

SCHMITT22 : Schmitt Trigger Control
bits : 22 - 22 (1 bit)
access : read-write

SCHMITT23 : Schmitt Trigger Control
bits : 23 - 23 (1 bit)
access : read-write

SCHMITT24 : Schmitt Trigger Control
bits : 24 - 24 (1 bit)
access : read-write

SCHMITT25 : Schmitt Trigger Control
bits : 25 - 25 (1 bit)
access : read-write

SCHMITT26 : Schmitt Trigger Control
bits : 26 - 26 (1 bit)
access : read-write

SCHMITT27 : Schmitt Trigger Control
bits : 27 - 27 (1 bit)
access : read-write

SCHMITT28 : Schmitt Trigger Control
bits : 28 - 28 (1 bit)
access : read-write

SCHMITT29 : Schmitt Trigger Control
bits : 29 - 29 (1 bit)
access : read-write

SCHMITT30 : Schmitt Trigger Control
bits : 30 - 30 (1 bit)
access : read-write

SCHMITT31 : Schmitt Trigger Control
bits : 31 - 31 (1 bit)
access : read-write


PIO_DRIVER

I/O Drive Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO_DRIVER PIO_DRIVER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINE0 LINE1 LINE2 LINE3 LINE4 LINE5 LINE6 LINE7 LINE8 LINE9 LINE10 LINE11 LINE12 LINE13 LINE14 LINE15 LINE16 LINE17 LINE18 LINE19 LINE20 LINE21 LINE22 LINE23 LINE24 LINE25 LINE26 LINE27 LINE28 LINE29 LINE30 LINE31

LINE0 : Drive of PIO Line 0
bits : 0 - 0 (1 bit)

Enumeration: LINE0Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE1 : Drive of PIO Line 1
bits : 1 - 1 (1 bit)

Enumeration: LINE1Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE2 : Drive of PIO Line 2
bits : 2 - 2 (1 bit)

Enumeration: LINE2Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE3 : Drive of PIO Line 3
bits : 3 - 3 (1 bit)

Enumeration: LINE3Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE4 : Drive of PIO Line 4
bits : 4 - 4 (1 bit)

Enumeration: LINE4Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE5 : Drive of PIO Line 5
bits : 5 - 5 (1 bit)

Enumeration: LINE5Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE6 : Drive of PIO Line 6
bits : 6 - 6 (1 bit)

Enumeration: LINE6Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE7 : Drive of PIO Line 7
bits : 7 - 7 (1 bit)

Enumeration: LINE7Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE8 : Drive of PIO Line 8
bits : 8 - 8 (1 bit)

Enumeration: LINE8Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE9 : Drive of PIO Line 9
bits : 9 - 9 (1 bit)

Enumeration: LINE9Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE10 : Drive of PIO Line 10
bits : 10 - 10 (1 bit)

Enumeration: LINE10Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE11 : Drive of PIO Line 11
bits : 11 - 11 (1 bit)

Enumeration: LINE11Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE12 : Drive of PIO Line 12
bits : 12 - 12 (1 bit)

Enumeration: LINE12Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE13 : Drive of PIO Line 13
bits : 13 - 13 (1 bit)

Enumeration: LINE13Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE14 : Drive of PIO Line 14
bits : 14 - 14 (1 bit)

Enumeration: LINE14Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE15 : Drive of PIO Line 15
bits : 15 - 15 (1 bit)

Enumeration: LINE15Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE16 : Drive of PIO Line 16
bits : 16 - 16 (1 bit)

Enumeration: LINE16Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE17 : Drive of PIO Line 17
bits : 17 - 17 (1 bit)

Enumeration: LINE17Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE18 : Drive of PIO Line 18
bits : 18 - 18 (1 bit)

Enumeration: LINE18Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE19 : Drive of PIO Line 19
bits : 19 - 19 (1 bit)

Enumeration: LINE19Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE20 : Drive of PIO Line 20
bits : 20 - 20 (1 bit)

Enumeration: LINE20Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE21 : Drive of PIO Line 21
bits : 21 - 21 (1 bit)

Enumeration: LINE21Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE22 : Drive of PIO Line 22
bits : 22 - 22 (1 bit)

Enumeration: LINE22Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE23 : Drive of PIO Line 23
bits : 23 - 23 (1 bit)

Enumeration: LINE23Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE24 : Drive of PIO Line 24
bits : 24 - 24 (1 bit)

Enumeration: LINE24Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE25 : Drive of PIO Line 25
bits : 25 - 25 (1 bit)

Enumeration: LINE25Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE26 : Drive of PIO Line 26
bits : 26 - 26 (1 bit)

Enumeration: LINE26Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE27 : Drive of PIO Line 27
bits : 27 - 27 (1 bit)

Enumeration: LINE27Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE28 : Drive of PIO Line 28
bits : 28 - 28 (1 bit)

Enumeration: LINE28Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE29 : Drive of PIO Line 29
bits : 29 - 29 (1 bit)

Enumeration: LINE29Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE30 : Drive of PIO Line 30
bits : 30 - 30 (1 bit)

Enumeration: LINE30Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE31 : Drive of PIO Line 31
bits : 31 - 31 (1 bit)

Enumeration: LINE31Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.


DRIVER

I/O Drive Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRIVER DRIVER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINE0 LINE1 LINE2 LINE3 LINE4 LINE5 LINE6 LINE7 LINE8 LINE9 LINE10 LINE11 LINE12 LINE13 LINE14 LINE15 LINE16 LINE17 LINE18 LINE19 LINE20 LINE21 LINE22 LINE23 LINE24 LINE25 LINE26 LINE27 LINE28 LINE29 LINE30 LINE31

LINE0 : Drive of PIO Line 0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration: LINE0Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE1 : Drive of PIO Line 1
bits : 1 - 1 (1 bit)
access : read-write

Enumeration: LINE1Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE2 : Drive of PIO Line 2
bits : 2 - 2 (1 bit)
access : read-write

Enumeration: LINE2Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE3 : Drive of PIO Line 3
bits : 3 - 3 (1 bit)
access : read-write

Enumeration: LINE3Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE4 : Drive of PIO Line 4
bits : 4 - 4 (1 bit)
access : read-write

Enumeration: LINE4Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE5 : Drive of PIO Line 5
bits : 5 - 5 (1 bit)
access : read-write

Enumeration: LINE5Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE6 : Drive of PIO Line 6
bits : 6 - 6 (1 bit)
access : read-write

Enumeration: LINE6Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE7 : Drive of PIO Line 7
bits : 7 - 7 (1 bit)
access : read-write

Enumeration: LINE7Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE8 : Drive of PIO Line 8
bits : 8 - 8 (1 bit)
access : read-write

Enumeration: LINE8Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE9 : Drive of PIO Line 9
bits : 9 - 9 (1 bit)
access : read-write

Enumeration: LINE9Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE10 : Drive of PIO Line 10
bits : 10 - 10 (1 bit)
access : read-write

Enumeration: LINE10Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE11 : Drive of PIO Line 11
bits : 11 - 11 (1 bit)
access : read-write

Enumeration: LINE11Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE12 : Drive of PIO Line 12
bits : 12 - 12 (1 bit)
access : read-write

Enumeration: LINE12Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE13 : Drive of PIO Line 13
bits : 13 - 13 (1 bit)
access : read-write

Enumeration: LINE13Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE14 : Drive of PIO Line 14
bits : 14 - 14 (1 bit)
access : read-write

Enumeration: LINE14Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE15 : Drive of PIO Line 15
bits : 15 - 15 (1 bit)
access : read-write

Enumeration: LINE15Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE16 : Drive of PIO Line 16
bits : 16 - 16 (1 bit)
access : read-write

Enumeration: LINE16Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE17 : Drive of PIO Line 17
bits : 17 - 17 (1 bit)
access : read-write

Enumeration: LINE17Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE18 : Drive of PIO Line 18
bits : 18 - 18 (1 bit)
access : read-write

Enumeration: LINE18Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE19 : Drive of PIO Line 19
bits : 19 - 19 (1 bit)
access : read-write

Enumeration: LINE19Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE20 : Drive of PIO Line 20
bits : 20 - 20 (1 bit)
access : read-write

Enumeration: LINE20Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE21 : Drive of PIO Line 21
bits : 21 - 21 (1 bit)
access : read-write

Enumeration: LINE21Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE22 : Drive of PIO Line 22
bits : 22 - 22 (1 bit)
access : read-write

Enumeration: LINE22Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE23 : Drive of PIO Line 23
bits : 23 - 23 (1 bit)
access : read-write

Enumeration: LINE23Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE24 : Drive of PIO Line 24
bits : 24 - 24 (1 bit)
access : read-write

Enumeration: LINE24Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE25 : Drive of PIO Line 25
bits : 25 - 25 (1 bit)
access : read-write

Enumeration: LINE25Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE26 : Drive of PIO Line 26
bits : 26 - 26 (1 bit)
access : read-write

Enumeration: LINE26Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE27 : Drive of PIO Line 27
bits : 27 - 27 (1 bit)
access : read-write

Enumeration: LINE27Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE28 : Drive of PIO Line 28
bits : 28 - 28 (1 bit)
access : read-write

Enumeration: LINE28Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE29 : Drive of PIO Line 29
bits : 29 - 29 (1 bit)
access : read-write

Enumeration: LINE29Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE30 : Drive of PIO Line 30
bits : 30 - 30 (1 bit)
access : read-write

Enumeration: LINE30Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.

LINE31 : Drive of PIO Line 31
bits : 31 - 31 (1 bit)
access : read-write

Enumeration: LINE31Select

0 : LOW_DRIVE

Lowest drive

1 : HIGH_DRIVE

Highest drive

End of enumeration elements list.


PIO_ODR

Output Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_ODR PIO_ODR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Output Disable
bits : 0 - 0 (1 bit)

P1 : Output Disable
bits : 1 - 1 (1 bit)

P2 : Output Disable
bits : 2 - 2 (1 bit)

P3 : Output Disable
bits : 3 - 3 (1 bit)

P4 : Output Disable
bits : 4 - 4 (1 bit)

P5 : Output Disable
bits : 5 - 5 (1 bit)

P6 : Output Disable
bits : 6 - 6 (1 bit)

P7 : Output Disable
bits : 7 - 7 (1 bit)

P8 : Output Disable
bits : 8 - 8 (1 bit)

P9 : Output Disable
bits : 9 - 9 (1 bit)

P10 : Output Disable
bits : 10 - 10 (1 bit)

P11 : Output Disable
bits : 11 - 11 (1 bit)

P12 : Output Disable
bits : 12 - 12 (1 bit)

P13 : Output Disable
bits : 13 - 13 (1 bit)

P14 : Output Disable
bits : 14 - 14 (1 bit)

P15 : Output Disable
bits : 15 - 15 (1 bit)

P16 : Output Disable
bits : 16 - 16 (1 bit)

P17 : Output Disable
bits : 17 - 17 (1 bit)

P18 : Output Disable
bits : 18 - 18 (1 bit)

P19 : Output Disable
bits : 19 - 19 (1 bit)

P20 : Output Disable
bits : 20 - 20 (1 bit)

P21 : Output Disable
bits : 21 - 21 (1 bit)

P22 : Output Disable
bits : 22 - 22 (1 bit)

P23 : Output Disable
bits : 23 - 23 (1 bit)

P24 : Output Disable
bits : 24 - 24 (1 bit)

P25 : Output Disable
bits : 25 - 25 (1 bit)

P26 : Output Disable
bits : 26 - 26 (1 bit)

P27 : Output Disable
bits : 27 - 27 (1 bit)

P28 : Output Disable
bits : 28 - 28 (1 bit)

P29 : Output Disable
bits : 29 - 29 (1 bit)

P30 : Output Disable
bits : 30 - 30 (1 bit)

P31 : Output Disable
bits : 31 - 31 (1 bit)


ODR

Output Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ODR ODR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Output Disable
bits : 0 - 0 (1 bit)
access : write-only

P1 : Output Disable
bits : 1 - 1 (1 bit)
access : write-only

P2 : Output Disable
bits : 2 - 2 (1 bit)
access : write-only

P3 : Output Disable
bits : 3 - 3 (1 bit)
access : write-only

P4 : Output Disable
bits : 4 - 4 (1 bit)
access : write-only

P5 : Output Disable
bits : 5 - 5 (1 bit)
access : write-only

P6 : Output Disable
bits : 6 - 6 (1 bit)
access : write-only

P7 : Output Disable
bits : 7 - 7 (1 bit)
access : write-only

P8 : Output Disable
bits : 8 - 8 (1 bit)
access : write-only

P9 : Output Disable
bits : 9 - 9 (1 bit)
access : write-only

P10 : Output Disable
bits : 10 - 10 (1 bit)
access : write-only

P11 : Output Disable
bits : 11 - 11 (1 bit)
access : write-only

P12 : Output Disable
bits : 12 - 12 (1 bit)
access : write-only

P13 : Output Disable
bits : 13 - 13 (1 bit)
access : write-only

P14 : Output Disable
bits : 14 - 14 (1 bit)
access : write-only

P15 : Output Disable
bits : 15 - 15 (1 bit)
access : write-only

P16 : Output Disable
bits : 16 - 16 (1 bit)
access : write-only

P17 : Output Disable
bits : 17 - 17 (1 bit)
access : write-only

P18 : Output Disable
bits : 18 - 18 (1 bit)
access : write-only

P19 : Output Disable
bits : 19 - 19 (1 bit)
access : write-only

P20 : Output Disable
bits : 20 - 20 (1 bit)
access : write-only

P21 : Output Disable
bits : 21 - 21 (1 bit)
access : write-only

P22 : Output Disable
bits : 22 - 22 (1 bit)
access : write-only

P23 : Output Disable
bits : 23 - 23 (1 bit)
access : write-only

P24 : Output Disable
bits : 24 - 24 (1 bit)
access : write-only

P25 : Output Disable
bits : 25 - 25 (1 bit)
access : write-only

P26 : Output Disable
bits : 26 - 26 (1 bit)
access : write-only

P27 : Output Disable
bits : 27 - 27 (1 bit)
access : write-only

P28 : Output Disable
bits : 28 - 28 (1 bit)
access : write-only

P29 : Output Disable
bits : 29 - 29 (1 bit)
access : write-only

P30 : Output Disable
bits : 30 - 30 (1 bit)
access : write-only

P31 : Output Disable
bits : 31 - 31 (1 bit)
access : write-only


PIO_PCMR

Parallel Capture Mode Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO_PCMR PIO_PCMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCEN DSIZE ALWYS HALFS FRSTS

PCEN : Parallel Capture Mode Enable
bits : 0 - 0 (1 bit)

DSIZE : Parallel Capture Mode Data Size
bits : 4 - 5 (2 bit)

Enumeration: DSIZESelect

0x0 : BYTE

The reception data in the PIO_PCRHR is a byte (8-bit)

0x1 : HALFWORD

The reception data in the PIO_PCRHR is a half-word (16-bit)

0x2 : WORD

The reception data in the PIO_PCRHR is a word (32-bit)

End of enumeration elements list.

ALWYS : Parallel Capture Mode Always Sampling
bits : 9 - 9 (1 bit)

HALFS : Parallel Capture Mode Half Sampling
bits : 10 - 10 (1 bit)

FRSTS : Parallel Capture Mode First Sample
bits : 11 - 11 (1 bit)


PCMR

Parallel Capture Mode Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCMR PCMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCEN DSIZE ALWYS HALFS FRSTS

PCEN : Parallel Capture Mode Enable
bits : 0 - 0 (1 bit)
access : read-write

DSIZE : Parallel Capture Mode Data Size
bits : 4 - 5 (2 bit)
access : read-write

Enumeration: DSIZESelect

0x0 : BYTE

The reception data in the PIO_PCRHR is a byte (8-bit)

0x1 : HALFWORD

The reception data in the PIO_PCRHR is a half-word (16-bit)

0x2 : WORD

The reception data in the PIO_PCRHR is a word (32-bit)

End of enumeration elements list.

ALWYS : Parallel Capture Mode Always Sampling
bits : 9 - 9 (1 bit)
access : read-write

HALFS : Parallel Capture Mode Half Sampling
bits : 10 - 10 (1 bit)
access : read-write

FRSTS : Parallel Capture Mode First Sample
bits : 11 - 11 (1 bit)
access : read-write


PIO_PCIER

Parallel Capture Interrupt Enable Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_PCIER PIO_PCIER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRDY OVRE ENDRX RXBUFF

DRDY : Parallel Capture Mode Data Ready Interrupt Enable
bits : 0 - 0 (1 bit)

OVRE : Parallel Capture Mode Overrun Error Interrupt Enable
bits : 1 - 1 (1 bit)

ENDRX : End of Reception Transfer Interrupt Enable
bits : 2 - 2 (1 bit)

RXBUFF : Reception Buffer Full Interrupt Enable
bits : 3 - 3 (1 bit)


PCIER

Parallel Capture Interrupt Enable Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PCIER PCIER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRDY OVRE ENDRX RXBUFF

DRDY : Parallel Capture Mode Data Ready Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

OVRE : Parallel Capture Mode Overrun Error Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

ENDRX : End of Reception Transfer Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

RXBUFF : Reception Buffer Full Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only


PIO_PCIDR

Parallel Capture Interrupt Disable Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_PCIDR PIO_PCIDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRDY OVRE ENDRX RXBUFF

DRDY : Parallel Capture Mode Data Ready Interrupt Disable
bits : 0 - 0 (1 bit)

OVRE : Parallel Capture Mode Overrun Error Interrupt Disable
bits : 1 - 1 (1 bit)

ENDRX : End of Reception Transfer Interrupt Disable
bits : 2 - 2 (1 bit)

RXBUFF : Reception Buffer Full Interrupt Disable
bits : 3 - 3 (1 bit)


PCIDR

Parallel Capture Interrupt Disable Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PCIDR PCIDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRDY OVRE ENDRX RXBUFF

DRDY : Parallel Capture Mode Data Ready Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

OVRE : Parallel Capture Mode Overrun Error Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

ENDRX : End of Reception Transfer Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

RXBUFF : Reception Buffer Full Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only


PIO_PCIMR

Parallel Capture Interrupt Mask Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_PCIMR PIO_PCIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRDY OVRE ENDRX RXBUFF

DRDY : Parallel Capture Mode Data Ready Interrupt Mask
bits : 0 - 0 (1 bit)

OVRE : Parallel Capture Mode Overrun Error Interrupt Mask
bits : 1 - 1 (1 bit)

ENDRX : End of Reception Transfer Interrupt Mask
bits : 2 - 2 (1 bit)

RXBUFF : Reception Buffer Full Interrupt Mask
bits : 3 - 3 (1 bit)


PCIMR

Parallel Capture Interrupt Mask Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PCIMR PCIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRDY OVRE ENDRX RXBUFF

DRDY : Parallel Capture Mode Data Ready Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

OVRE : Parallel Capture Mode Overrun Error Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

ENDRX : End of Reception Transfer Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

RXBUFF : Reception Buffer Full Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only


PIO_PCISR

Parallel Capture Interrupt Status Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_PCISR PIO_PCISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRDY OVRE

DRDY : Parallel Capture Mode Data Ready
bits : 0 - 0 (1 bit)

OVRE : Parallel Capture Mode Overrun Error
bits : 1 - 1 (1 bit)


PCISR

Parallel Capture Interrupt Status Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PCISR PCISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRDY OVRE

DRDY : Parallel Capture Mode Data Ready
bits : 0 - 0 (1 bit)
access : read-only

OVRE : Parallel Capture Mode Overrun Error
bits : 1 - 1 (1 bit)
access : read-only


PIO_PCRHR

Parallel Capture Reception Holding Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_PCRHR PIO_PCRHR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA

RDATA : Parallel Capture Mode Reception Data
bits : 0 - 31 (32 bit)


PCRHR

Parallel Capture Reception Holding Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PCRHR PCRHR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA

RDATA : Parallel Capture Mode Reception Data
bits : 0 - 31 (32 bit)
access : read-only


PIO_OSR

Output Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_OSR PIO_OSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Output Status
bits : 0 - 0 (1 bit)

P1 : Output Status
bits : 1 - 1 (1 bit)

P2 : Output Status
bits : 2 - 2 (1 bit)

P3 : Output Status
bits : 3 - 3 (1 bit)

P4 : Output Status
bits : 4 - 4 (1 bit)

P5 : Output Status
bits : 5 - 5 (1 bit)

P6 : Output Status
bits : 6 - 6 (1 bit)

P7 : Output Status
bits : 7 - 7 (1 bit)

P8 : Output Status
bits : 8 - 8 (1 bit)

P9 : Output Status
bits : 9 - 9 (1 bit)

P10 : Output Status
bits : 10 - 10 (1 bit)

P11 : Output Status
bits : 11 - 11 (1 bit)

P12 : Output Status
bits : 12 - 12 (1 bit)

P13 : Output Status
bits : 13 - 13 (1 bit)

P14 : Output Status
bits : 14 - 14 (1 bit)

P15 : Output Status
bits : 15 - 15 (1 bit)

P16 : Output Status
bits : 16 - 16 (1 bit)

P17 : Output Status
bits : 17 - 17 (1 bit)

P18 : Output Status
bits : 18 - 18 (1 bit)

P19 : Output Status
bits : 19 - 19 (1 bit)

P20 : Output Status
bits : 20 - 20 (1 bit)

P21 : Output Status
bits : 21 - 21 (1 bit)

P22 : Output Status
bits : 22 - 22 (1 bit)

P23 : Output Status
bits : 23 - 23 (1 bit)

P24 : Output Status
bits : 24 - 24 (1 bit)

P25 : Output Status
bits : 25 - 25 (1 bit)

P26 : Output Status
bits : 26 - 26 (1 bit)

P27 : Output Status
bits : 27 - 27 (1 bit)

P28 : Output Status
bits : 28 - 28 (1 bit)

P29 : Output Status
bits : 29 - 29 (1 bit)

P30 : Output Status
bits : 30 - 30 (1 bit)

P31 : Output Status
bits : 31 - 31 (1 bit)


OSR

Output Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OSR OSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Output Status
bits : 0 - 0 (1 bit)
access : read-only

P1 : Output Status
bits : 1 - 1 (1 bit)
access : read-only

P2 : Output Status
bits : 2 - 2 (1 bit)
access : read-only

P3 : Output Status
bits : 3 - 3 (1 bit)
access : read-only

P4 : Output Status
bits : 4 - 4 (1 bit)
access : read-only

P5 : Output Status
bits : 5 - 5 (1 bit)
access : read-only

P6 : Output Status
bits : 6 - 6 (1 bit)
access : read-only

P7 : Output Status
bits : 7 - 7 (1 bit)
access : read-only

P8 : Output Status
bits : 8 - 8 (1 bit)
access : read-only

P9 : Output Status
bits : 9 - 9 (1 bit)
access : read-only

P10 : Output Status
bits : 10 - 10 (1 bit)
access : read-only

P11 : Output Status
bits : 11 - 11 (1 bit)
access : read-only

P12 : Output Status
bits : 12 - 12 (1 bit)
access : read-only

P13 : Output Status
bits : 13 - 13 (1 bit)
access : read-only

P14 : Output Status
bits : 14 - 14 (1 bit)
access : read-only

P15 : Output Status
bits : 15 - 15 (1 bit)
access : read-only

P16 : Output Status
bits : 16 - 16 (1 bit)
access : read-only

P17 : Output Status
bits : 17 - 17 (1 bit)
access : read-only

P18 : Output Status
bits : 18 - 18 (1 bit)
access : read-only

P19 : Output Status
bits : 19 - 19 (1 bit)
access : read-only

P20 : Output Status
bits : 20 - 20 (1 bit)
access : read-only

P21 : Output Status
bits : 21 - 21 (1 bit)
access : read-only

P22 : Output Status
bits : 22 - 22 (1 bit)
access : read-only

P23 : Output Status
bits : 23 - 23 (1 bit)
access : read-only

P24 : Output Status
bits : 24 - 24 (1 bit)
access : read-only

P25 : Output Status
bits : 25 - 25 (1 bit)
access : read-only

P26 : Output Status
bits : 26 - 26 (1 bit)
access : read-only

P27 : Output Status
bits : 27 - 27 (1 bit)
access : read-only

P28 : Output Status
bits : 28 - 28 (1 bit)
access : read-only

P29 : Output Status
bits : 29 - 29 (1 bit)
access : read-only

P30 : Output Status
bits : 30 - 30 (1 bit)
access : read-only

P31 : Output Status
bits : 31 - 31 (1 bit)
access : read-only


PIO_IFER

Glitch Input Filter Enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_IFER PIO_IFER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Input Filter Enable
bits : 0 - 0 (1 bit)

P1 : Input Filter Enable
bits : 1 - 1 (1 bit)

P2 : Input Filter Enable
bits : 2 - 2 (1 bit)

P3 : Input Filter Enable
bits : 3 - 3 (1 bit)

P4 : Input Filter Enable
bits : 4 - 4 (1 bit)

P5 : Input Filter Enable
bits : 5 - 5 (1 bit)

P6 : Input Filter Enable
bits : 6 - 6 (1 bit)

P7 : Input Filter Enable
bits : 7 - 7 (1 bit)

P8 : Input Filter Enable
bits : 8 - 8 (1 bit)

P9 : Input Filter Enable
bits : 9 - 9 (1 bit)

P10 : Input Filter Enable
bits : 10 - 10 (1 bit)

P11 : Input Filter Enable
bits : 11 - 11 (1 bit)

P12 : Input Filter Enable
bits : 12 - 12 (1 bit)

P13 : Input Filter Enable
bits : 13 - 13 (1 bit)

P14 : Input Filter Enable
bits : 14 - 14 (1 bit)

P15 : Input Filter Enable
bits : 15 - 15 (1 bit)

P16 : Input Filter Enable
bits : 16 - 16 (1 bit)

P17 : Input Filter Enable
bits : 17 - 17 (1 bit)

P18 : Input Filter Enable
bits : 18 - 18 (1 bit)

P19 : Input Filter Enable
bits : 19 - 19 (1 bit)

P20 : Input Filter Enable
bits : 20 - 20 (1 bit)

P21 : Input Filter Enable
bits : 21 - 21 (1 bit)

P22 : Input Filter Enable
bits : 22 - 22 (1 bit)

P23 : Input Filter Enable
bits : 23 - 23 (1 bit)

P24 : Input Filter Enable
bits : 24 - 24 (1 bit)

P25 : Input Filter Enable
bits : 25 - 25 (1 bit)

P26 : Input Filter Enable
bits : 26 - 26 (1 bit)

P27 : Input Filter Enable
bits : 27 - 27 (1 bit)

P28 : Input Filter Enable
bits : 28 - 28 (1 bit)

P29 : Input Filter Enable
bits : 29 - 29 (1 bit)

P30 : Input Filter Enable
bits : 30 - 30 (1 bit)

P31 : Input Filter Enable
bits : 31 - 31 (1 bit)


IFER

Glitch Input Filter Enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFER IFER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Input Filter Enable
bits : 0 - 0 (1 bit)
access : write-only

P1 : Input Filter Enable
bits : 1 - 1 (1 bit)
access : write-only

P2 : Input Filter Enable
bits : 2 - 2 (1 bit)
access : write-only

P3 : Input Filter Enable
bits : 3 - 3 (1 bit)
access : write-only

P4 : Input Filter Enable
bits : 4 - 4 (1 bit)
access : write-only

P5 : Input Filter Enable
bits : 5 - 5 (1 bit)
access : write-only

P6 : Input Filter Enable
bits : 6 - 6 (1 bit)
access : write-only

P7 : Input Filter Enable
bits : 7 - 7 (1 bit)
access : write-only

P8 : Input Filter Enable
bits : 8 - 8 (1 bit)
access : write-only

P9 : Input Filter Enable
bits : 9 - 9 (1 bit)
access : write-only

P10 : Input Filter Enable
bits : 10 - 10 (1 bit)
access : write-only

P11 : Input Filter Enable
bits : 11 - 11 (1 bit)
access : write-only

P12 : Input Filter Enable
bits : 12 - 12 (1 bit)
access : write-only

P13 : Input Filter Enable
bits : 13 - 13 (1 bit)
access : write-only

P14 : Input Filter Enable
bits : 14 - 14 (1 bit)
access : write-only

P15 : Input Filter Enable
bits : 15 - 15 (1 bit)
access : write-only

P16 : Input Filter Enable
bits : 16 - 16 (1 bit)
access : write-only

P17 : Input Filter Enable
bits : 17 - 17 (1 bit)
access : write-only

P18 : Input Filter Enable
bits : 18 - 18 (1 bit)
access : write-only

P19 : Input Filter Enable
bits : 19 - 19 (1 bit)
access : write-only

P20 : Input Filter Enable
bits : 20 - 20 (1 bit)
access : write-only

P21 : Input Filter Enable
bits : 21 - 21 (1 bit)
access : write-only

P22 : Input Filter Enable
bits : 22 - 22 (1 bit)
access : write-only

P23 : Input Filter Enable
bits : 23 - 23 (1 bit)
access : write-only

P24 : Input Filter Enable
bits : 24 - 24 (1 bit)
access : write-only

P25 : Input Filter Enable
bits : 25 - 25 (1 bit)
access : write-only

P26 : Input Filter Enable
bits : 26 - 26 (1 bit)
access : write-only

P27 : Input Filter Enable
bits : 27 - 27 (1 bit)
access : write-only

P28 : Input Filter Enable
bits : 28 - 28 (1 bit)
access : write-only

P29 : Input Filter Enable
bits : 29 - 29 (1 bit)
access : write-only

P30 : Input Filter Enable
bits : 30 - 30 (1 bit)
access : write-only

P31 : Input Filter Enable
bits : 31 - 31 (1 bit)
access : write-only


PIO_IFDR

Glitch Input Filter Disable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_IFDR PIO_IFDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Input Filter Disable
bits : 0 - 0 (1 bit)

P1 : Input Filter Disable
bits : 1 - 1 (1 bit)

P2 : Input Filter Disable
bits : 2 - 2 (1 bit)

P3 : Input Filter Disable
bits : 3 - 3 (1 bit)

P4 : Input Filter Disable
bits : 4 - 4 (1 bit)

P5 : Input Filter Disable
bits : 5 - 5 (1 bit)

P6 : Input Filter Disable
bits : 6 - 6 (1 bit)

P7 : Input Filter Disable
bits : 7 - 7 (1 bit)

P8 : Input Filter Disable
bits : 8 - 8 (1 bit)

P9 : Input Filter Disable
bits : 9 - 9 (1 bit)

P10 : Input Filter Disable
bits : 10 - 10 (1 bit)

P11 : Input Filter Disable
bits : 11 - 11 (1 bit)

P12 : Input Filter Disable
bits : 12 - 12 (1 bit)

P13 : Input Filter Disable
bits : 13 - 13 (1 bit)

P14 : Input Filter Disable
bits : 14 - 14 (1 bit)

P15 : Input Filter Disable
bits : 15 - 15 (1 bit)

P16 : Input Filter Disable
bits : 16 - 16 (1 bit)

P17 : Input Filter Disable
bits : 17 - 17 (1 bit)

P18 : Input Filter Disable
bits : 18 - 18 (1 bit)

P19 : Input Filter Disable
bits : 19 - 19 (1 bit)

P20 : Input Filter Disable
bits : 20 - 20 (1 bit)

P21 : Input Filter Disable
bits : 21 - 21 (1 bit)

P22 : Input Filter Disable
bits : 22 - 22 (1 bit)

P23 : Input Filter Disable
bits : 23 - 23 (1 bit)

P24 : Input Filter Disable
bits : 24 - 24 (1 bit)

P25 : Input Filter Disable
bits : 25 - 25 (1 bit)

P26 : Input Filter Disable
bits : 26 - 26 (1 bit)

P27 : Input Filter Disable
bits : 27 - 27 (1 bit)

P28 : Input Filter Disable
bits : 28 - 28 (1 bit)

P29 : Input Filter Disable
bits : 29 - 29 (1 bit)

P30 : Input Filter Disable
bits : 30 - 30 (1 bit)

P31 : Input Filter Disable
bits : 31 - 31 (1 bit)


IFDR

Glitch Input Filter Disable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFDR IFDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Input Filter Disable
bits : 0 - 0 (1 bit)
access : write-only

P1 : Input Filter Disable
bits : 1 - 1 (1 bit)
access : write-only

P2 : Input Filter Disable
bits : 2 - 2 (1 bit)
access : write-only

P3 : Input Filter Disable
bits : 3 - 3 (1 bit)
access : write-only

P4 : Input Filter Disable
bits : 4 - 4 (1 bit)
access : write-only

P5 : Input Filter Disable
bits : 5 - 5 (1 bit)
access : write-only

P6 : Input Filter Disable
bits : 6 - 6 (1 bit)
access : write-only

P7 : Input Filter Disable
bits : 7 - 7 (1 bit)
access : write-only

P8 : Input Filter Disable
bits : 8 - 8 (1 bit)
access : write-only

P9 : Input Filter Disable
bits : 9 - 9 (1 bit)
access : write-only

P10 : Input Filter Disable
bits : 10 - 10 (1 bit)
access : write-only

P11 : Input Filter Disable
bits : 11 - 11 (1 bit)
access : write-only

P12 : Input Filter Disable
bits : 12 - 12 (1 bit)
access : write-only

P13 : Input Filter Disable
bits : 13 - 13 (1 bit)
access : write-only

P14 : Input Filter Disable
bits : 14 - 14 (1 bit)
access : write-only

P15 : Input Filter Disable
bits : 15 - 15 (1 bit)
access : write-only

P16 : Input Filter Disable
bits : 16 - 16 (1 bit)
access : write-only

P17 : Input Filter Disable
bits : 17 - 17 (1 bit)
access : write-only

P18 : Input Filter Disable
bits : 18 - 18 (1 bit)
access : write-only

P19 : Input Filter Disable
bits : 19 - 19 (1 bit)
access : write-only

P20 : Input Filter Disable
bits : 20 - 20 (1 bit)
access : write-only

P21 : Input Filter Disable
bits : 21 - 21 (1 bit)
access : write-only

P22 : Input Filter Disable
bits : 22 - 22 (1 bit)
access : write-only

P23 : Input Filter Disable
bits : 23 - 23 (1 bit)
access : write-only

P24 : Input Filter Disable
bits : 24 - 24 (1 bit)
access : write-only

P25 : Input Filter Disable
bits : 25 - 25 (1 bit)
access : write-only

P26 : Input Filter Disable
bits : 26 - 26 (1 bit)
access : write-only

P27 : Input Filter Disable
bits : 27 - 27 (1 bit)
access : write-only

P28 : Input Filter Disable
bits : 28 - 28 (1 bit)
access : write-only

P29 : Input Filter Disable
bits : 29 - 29 (1 bit)
access : write-only

P30 : Input Filter Disable
bits : 30 - 30 (1 bit)
access : write-only

P31 : Input Filter Disable
bits : 31 - 31 (1 bit)
access : write-only


PIO_IFSR

Glitch Input Filter Status Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_IFSR PIO_IFSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Input Filter Status
bits : 0 - 0 (1 bit)

P1 : Input Filter Status
bits : 1 - 1 (1 bit)

P2 : Input Filter Status
bits : 2 - 2 (1 bit)

P3 : Input Filter Status
bits : 3 - 3 (1 bit)

P4 : Input Filter Status
bits : 4 - 4 (1 bit)

P5 : Input Filter Status
bits : 5 - 5 (1 bit)

P6 : Input Filter Status
bits : 6 - 6 (1 bit)

P7 : Input Filter Status
bits : 7 - 7 (1 bit)

P8 : Input Filter Status
bits : 8 - 8 (1 bit)

P9 : Input Filter Status
bits : 9 - 9 (1 bit)

P10 : Input Filter Status
bits : 10 - 10 (1 bit)

P11 : Input Filter Status
bits : 11 - 11 (1 bit)

P12 : Input Filter Status
bits : 12 - 12 (1 bit)

P13 : Input Filter Status
bits : 13 - 13 (1 bit)

P14 : Input Filter Status
bits : 14 - 14 (1 bit)

P15 : Input Filter Status
bits : 15 - 15 (1 bit)

P16 : Input Filter Status
bits : 16 - 16 (1 bit)

P17 : Input Filter Status
bits : 17 - 17 (1 bit)

P18 : Input Filter Status
bits : 18 - 18 (1 bit)

P19 : Input Filter Status
bits : 19 - 19 (1 bit)

P20 : Input Filter Status
bits : 20 - 20 (1 bit)

P21 : Input Filter Status
bits : 21 - 21 (1 bit)

P22 : Input Filter Status
bits : 22 - 22 (1 bit)

P23 : Input Filter Status
bits : 23 - 23 (1 bit)

P24 : Input Filter Status
bits : 24 - 24 (1 bit)

P25 : Input Filter Status
bits : 25 - 25 (1 bit)

P26 : Input Filter Status
bits : 26 - 26 (1 bit)

P27 : Input Filter Status
bits : 27 - 27 (1 bit)

P28 : Input Filter Status
bits : 28 - 28 (1 bit)

P29 : Input Filter Status
bits : 29 - 29 (1 bit)

P30 : Input Filter Status
bits : 30 - 30 (1 bit)

P31 : Input Filter Status
bits : 31 - 31 (1 bit)


IFSR

Glitch Input Filter Status Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IFSR IFSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Input Filter Status
bits : 0 - 0 (1 bit)
access : read-only

P1 : Input Filter Status
bits : 1 - 1 (1 bit)
access : read-only

P2 : Input Filter Status
bits : 2 - 2 (1 bit)
access : read-only

P3 : Input Filter Status
bits : 3 - 3 (1 bit)
access : read-only

P4 : Input Filter Status
bits : 4 - 4 (1 bit)
access : read-only

P5 : Input Filter Status
bits : 5 - 5 (1 bit)
access : read-only

P6 : Input Filter Status
bits : 6 - 6 (1 bit)
access : read-only

P7 : Input Filter Status
bits : 7 - 7 (1 bit)
access : read-only

P8 : Input Filter Status
bits : 8 - 8 (1 bit)
access : read-only

P9 : Input Filter Status
bits : 9 - 9 (1 bit)
access : read-only

P10 : Input Filter Status
bits : 10 - 10 (1 bit)
access : read-only

P11 : Input Filter Status
bits : 11 - 11 (1 bit)
access : read-only

P12 : Input Filter Status
bits : 12 - 12 (1 bit)
access : read-only

P13 : Input Filter Status
bits : 13 - 13 (1 bit)
access : read-only

P14 : Input Filter Status
bits : 14 - 14 (1 bit)
access : read-only

P15 : Input Filter Status
bits : 15 - 15 (1 bit)
access : read-only

P16 : Input Filter Status
bits : 16 - 16 (1 bit)
access : read-only

P17 : Input Filter Status
bits : 17 - 17 (1 bit)
access : read-only

P18 : Input Filter Status
bits : 18 - 18 (1 bit)
access : read-only

P19 : Input Filter Status
bits : 19 - 19 (1 bit)
access : read-only

P20 : Input Filter Status
bits : 20 - 20 (1 bit)
access : read-only

P21 : Input Filter Status
bits : 21 - 21 (1 bit)
access : read-only

P22 : Input Filter Status
bits : 22 - 22 (1 bit)
access : read-only

P23 : Input Filter Status
bits : 23 - 23 (1 bit)
access : read-only

P24 : Input Filter Status
bits : 24 - 24 (1 bit)
access : read-only

P25 : Input Filter Status
bits : 25 - 25 (1 bit)
access : read-only

P26 : Input Filter Status
bits : 26 - 26 (1 bit)
access : read-only

P27 : Input Filter Status
bits : 27 - 27 (1 bit)
access : read-only

P28 : Input Filter Status
bits : 28 - 28 (1 bit)
access : read-only

P29 : Input Filter Status
bits : 29 - 29 (1 bit)
access : read-only

P30 : Input Filter Status
bits : 30 - 30 (1 bit)
access : read-only

P31 : Input Filter Status
bits : 31 - 31 (1 bit)
access : read-only


PIO_SODR

Set Output Data Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_SODR PIO_SODR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Set Output Data
bits : 0 - 0 (1 bit)

P1 : Set Output Data
bits : 1 - 1 (1 bit)

P2 : Set Output Data
bits : 2 - 2 (1 bit)

P3 : Set Output Data
bits : 3 - 3 (1 bit)

P4 : Set Output Data
bits : 4 - 4 (1 bit)

P5 : Set Output Data
bits : 5 - 5 (1 bit)

P6 : Set Output Data
bits : 6 - 6 (1 bit)

P7 : Set Output Data
bits : 7 - 7 (1 bit)

P8 : Set Output Data
bits : 8 - 8 (1 bit)

P9 : Set Output Data
bits : 9 - 9 (1 bit)

P10 : Set Output Data
bits : 10 - 10 (1 bit)

P11 : Set Output Data
bits : 11 - 11 (1 bit)

P12 : Set Output Data
bits : 12 - 12 (1 bit)

P13 : Set Output Data
bits : 13 - 13 (1 bit)

P14 : Set Output Data
bits : 14 - 14 (1 bit)

P15 : Set Output Data
bits : 15 - 15 (1 bit)

P16 : Set Output Data
bits : 16 - 16 (1 bit)

P17 : Set Output Data
bits : 17 - 17 (1 bit)

P18 : Set Output Data
bits : 18 - 18 (1 bit)

P19 : Set Output Data
bits : 19 - 19 (1 bit)

P20 : Set Output Data
bits : 20 - 20 (1 bit)

P21 : Set Output Data
bits : 21 - 21 (1 bit)

P22 : Set Output Data
bits : 22 - 22 (1 bit)

P23 : Set Output Data
bits : 23 - 23 (1 bit)

P24 : Set Output Data
bits : 24 - 24 (1 bit)

P25 : Set Output Data
bits : 25 - 25 (1 bit)

P26 : Set Output Data
bits : 26 - 26 (1 bit)

P27 : Set Output Data
bits : 27 - 27 (1 bit)

P28 : Set Output Data
bits : 28 - 28 (1 bit)

P29 : Set Output Data
bits : 29 - 29 (1 bit)

P30 : Set Output Data
bits : 30 - 30 (1 bit)

P31 : Set Output Data
bits : 31 - 31 (1 bit)


SODR

Set Output Data Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SODR SODR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Set Output Data
bits : 0 - 0 (1 bit)
access : write-only

P1 : Set Output Data
bits : 1 - 1 (1 bit)
access : write-only

P2 : Set Output Data
bits : 2 - 2 (1 bit)
access : write-only

P3 : Set Output Data
bits : 3 - 3 (1 bit)
access : write-only

P4 : Set Output Data
bits : 4 - 4 (1 bit)
access : write-only

P5 : Set Output Data
bits : 5 - 5 (1 bit)
access : write-only

P6 : Set Output Data
bits : 6 - 6 (1 bit)
access : write-only

P7 : Set Output Data
bits : 7 - 7 (1 bit)
access : write-only

P8 : Set Output Data
bits : 8 - 8 (1 bit)
access : write-only

P9 : Set Output Data
bits : 9 - 9 (1 bit)
access : write-only

P10 : Set Output Data
bits : 10 - 10 (1 bit)
access : write-only

P11 : Set Output Data
bits : 11 - 11 (1 bit)
access : write-only

P12 : Set Output Data
bits : 12 - 12 (1 bit)
access : write-only

P13 : Set Output Data
bits : 13 - 13 (1 bit)
access : write-only

P14 : Set Output Data
bits : 14 - 14 (1 bit)
access : write-only

P15 : Set Output Data
bits : 15 - 15 (1 bit)
access : write-only

P16 : Set Output Data
bits : 16 - 16 (1 bit)
access : write-only

P17 : Set Output Data
bits : 17 - 17 (1 bit)
access : write-only

P18 : Set Output Data
bits : 18 - 18 (1 bit)
access : write-only

P19 : Set Output Data
bits : 19 - 19 (1 bit)
access : write-only

P20 : Set Output Data
bits : 20 - 20 (1 bit)
access : write-only

P21 : Set Output Data
bits : 21 - 21 (1 bit)
access : write-only

P22 : Set Output Data
bits : 22 - 22 (1 bit)
access : write-only

P23 : Set Output Data
bits : 23 - 23 (1 bit)
access : write-only

P24 : Set Output Data
bits : 24 - 24 (1 bit)
access : write-only

P25 : Set Output Data
bits : 25 - 25 (1 bit)
access : write-only

P26 : Set Output Data
bits : 26 - 26 (1 bit)
access : write-only

P27 : Set Output Data
bits : 27 - 27 (1 bit)
access : write-only

P28 : Set Output Data
bits : 28 - 28 (1 bit)
access : write-only

P29 : Set Output Data
bits : 29 - 29 (1 bit)
access : write-only

P30 : Set Output Data
bits : 30 - 30 (1 bit)
access : write-only

P31 : Set Output Data
bits : 31 - 31 (1 bit)
access : write-only


PIO_CODR

Clear Output Data Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_CODR PIO_CODR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Clear Output Data
bits : 0 - 0 (1 bit)

P1 : Clear Output Data
bits : 1 - 1 (1 bit)

P2 : Clear Output Data
bits : 2 - 2 (1 bit)

P3 : Clear Output Data
bits : 3 - 3 (1 bit)

P4 : Clear Output Data
bits : 4 - 4 (1 bit)

P5 : Clear Output Data
bits : 5 - 5 (1 bit)

P6 : Clear Output Data
bits : 6 - 6 (1 bit)

P7 : Clear Output Data
bits : 7 - 7 (1 bit)

P8 : Clear Output Data
bits : 8 - 8 (1 bit)

P9 : Clear Output Data
bits : 9 - 9 (1 bit)

P10 : Clear Output Data
bits : 10 - 10 (1 bit)

P11 : Clear Output Data
bits : 11 - 11 (1 bit)

P12 : Clear Output Data
bits : 12 - 12 (1 bit)

P13 : Clear Output Data
bits : 13 - 13 (1 bit)

P14 : Clear Output Data
bits : 14 - 14 (1 bit)

P15 : Clear Output Data
bits : 15 - 15 (1 bit)

P16 : Clear Output Data
bits : 16 - 16 (1 bit)

P17 : Clear Output Data
bits : 17 - 17 (1 bit)

P18 : Clear Output Data
bits : 18 - 18 (1 bit)

P19 : Clear Output Data
bits : 19 - 19 (1 bit)

P20 : Clear Output Data
bits : 20 - 20 (1 bit)

P21 : Clear Output Data
bits : 21 - 21 (1 bit)

P22 : Clear Output Data
bits : 22 - 22 (1 bit)

P23 : Clear Output Data
bits : 23 - 23 (1 bit)

P24 : Clear Output Data
bits : 24 - 24 (1 bit)

P25 : Clear Output Data
bits : 25 - 25 (1 bit)

P26 : Clear Output Data
bits : 26 - 26 (1 bit)

P27 : Clear Output Data
bits : 27 - 27 (1 bit)

P28 : Clear Output Data
bits : 28 - 28 (1 bit)

P29 : Clear Output Data
bits : 29 - 29 (1 bit)

P30 : Clear Output Data
bits : 30 - 30 (1 bit)

P31 : Clear Output Data
bits : 31 - 31 (1 bit)


CODR

Clear Output Data Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CODR CODR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Clear Output Data
bits : 0 - 0 (1 bit)
access : write-only

P1 : Clear Output Data
bits : 1 - 1 (1 bit)
access : write-only

P2 : Clear Output Data
bits : 2 - 2 (1 bit)
access : write-only

P3 : Clear Output Data
bits : 3 - 3 (1 bit)
access : write-only

P4 : Clear Output Data
bits : 4 - 4 (1 bit)
access : write-only

P5 : Clear Output Data
bits : 5 - 5 (1 bit)
access : write-only

P6 : Clear Output Data
bits : 6 - 6 (1 bit)
access : write-only

P7 : Clear Output Data
bits : 7 - 7 (1 bit)
access : write-only

P8 : Clear Output Data
bits : 8 - 8 (1 bit)
access : write-only

P9 : Clear Output Data
bits : 9 - 9 (1 bit)
access : write-only

P10 : Clear Output Data
bits : 10 - 10 (1 bit)
access : write-only

P11 : Clear Output Data
bits : 11 - 11 (1 bit)
access : write-only

P12 : Clear Output Data
bits : 12 - 12 (1 bit)
access : write-only

P13 : Clear Output Data
bits : 13 - 13 (1 bit)
access : write-only

P14 : Clear Output Data
bits : 14 - 14 (1 bit)
access : write-only

P15 : Clear Output Data
bits : 15 - 15 (1 bit)
access : write-only

P16 : Clear Output Data
bits : 16 - 16 (1 bit)
access : write-only

P17 : Clear Output Data
bits : 17 - 17 (1 bit)
access : write-only

P18 : Clear Output Data
bits : 18 - 18 (1 bit)
access : write-only

P19 : Clear Output Data
bits : 19 - 19 (1 bit)
access : write-only

P20 : Clear Output Data
bits : 20 - 20 (1 bit)
access : write-only

P21 : Clear Output Data
bits : 21 - 21 (1 bit)
access : write-only

P22 : Clear Output Data
bits : 22 - 22 (1 bit)
access : write-only

P23 : Clear Output Data
bits : 23 - 23 (1 bit)
access : write-only

P24 : Clear Output Data
bits : 24 - 24 (1 bit)
access : write-only

P25 : Clear Output Data
bits : 25 - 25 (1 bit)
access : write-only

P26 : Clear Output Data
bits : 26 - 26 (1 bit)
access : write-only

P27 : Clear Output Data
bits : 27 - 27 (1 bit)
access : write-only

P28 : Clear Output Data
bits : 28 - 28 (1 bit)
access : write-only

P29 : Clear Output Data
bits : 29 - 29 (1 bit)
access : write-only

P30 : Clear Output Data
bits : 30 - 30 (1 bit)
access : write-only

P31 : Clear Output Data
bits : 31 - 31 (1 bit)
access : write-only


PIO_ODSR

Output Data Status Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO_ODSR PIO_ODSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Output Data Status
bits : 0 - 0 (1 bit)

P1 : Output Data Status
bits : 1 - 1 (1 bit)

P2 : Output Data Status
bits : 2 - 2 (1 bit)

P3 : Output Data Status
bits : 3 - 3 (1 bit)

P4 : Output Data Status
bits : 4 - 4 (1 bit)

P5 : Output Data Status
bits : 5 - 5 (1 bit)

P6 : Output Data Status
bits : 6 - 6 (1 bit)

P7 : Output Data Status
bits : 7 - 7 (1 bit)

P8 : Output Data Status
bits : 8 - 8 (1 bit)

P9 : Output Data Status
bits : 9 - 9 (1 bit)

P10 : Output Data Status
bits : 10 - 10 (1 bit)

P11 : Output Data Status
bits : 11 - 11 (1 bit)

P12 : Output Data Status
bits : 12 - 12 (1 bit)

P13 : Output Data Status
bits : 13 - 13 (1 bit)

P14 : Output Data Status
bits : 14 - 14 (1 bit)

P15 : Output Data Status
bits : 15 - 15 (1 bit)

P16 : Output Data Status
bits : 16 - 16 (1 bit)

P17 : Output Data Status
bits : 17 - 17 (1 bit)

P18 : Output Data Status
bits : 18 - 18 (1 bit)

P19 : Output Data Status
bits : 19 - 19 (1 bit)

P20 : Output Data Status
bits : 20 - 20 (1 bit)

P21 : Output Data Status
bits : 21 - 21 (1 bit)

P22 : Output Data Status
bits : 22 - 22 (1 bit)

P23 : Output Data Status
bits : 23 - 23 (1 bit)

P24 : Output Data Status
bits : 24 - 24 (1 bit)

P25 : Output Data Status
bits : 25 - 25 (1 bit)

P26 : Output Data Status
bits : 26 - 26 (1 bit)

P27 : Output Data Status
bits : 27 - 27 (1 bit)

P28 : Output Data Status
bits : 28 - 28 (1 bit)

P29 : Output Data Status
bits : 29 - 29 (1 bit)

P30 : Output Data Status
bits : 30 - 30 (1 bit)

P31 : Output Data Status
bits : 31 - 31 (1 bit)


ODSR

Output Data Status Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ODSR ODSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Output Data Status
bits : 0 - 0 (1 bit)
access : read-write

P1 : Output Data Status
bits : 1 - 1 (1 bit)
access : read-write

P2 : Output Data Status
bits : 2 - 2 (1 bit)
access : read-write

P3 : Output Data Status
bits : 3 - 3 (1 bit)
access : read-write

P4 : Output Data Status
bits : 4 - 4 (1 bit)
access : read-write

P5 : Output Data Status
bits : 5 - 5 (1 bit)
access : read-write

P6 : Output Data Status
bits : 6 - 6 (1 bit)
access : read-write

P7 : Output Data Status
bits : 7 - 7 (1 bit)
access : read-write

P8 : Output Data Status
bits : 8 - 8 (1 bit)
access : read-write

P9 : Output Data Status
bits : 9 - 9 (1 bit)
access : read-write

P10 : Output Data Status
bits : 10 - 10 (1 bit)
access : read-write

P11 : Output Data Status
bits : 11 - 11 (1 bit)
access : read-write

P12 : Output Data Status
bits : 12 - 12 (1 bit)
access : read-write

P13 : Output Data Status
bits : 13 - 13 (1 bit)
access : read-write

P14 : Output Data Status
bits : 14 - 14 (1 bit)
access : read-write

P15 : Output Data Status
bits : 15 - 15 (1 bit)
access : read-write

P16 : Output Data Status
bits : 16 - 16 (1 bit)
access : read-write

P17 : Output Data Status
bits : 17 - 17 (1 bit)
access : read-write

P18 : Output Data Status
bits : 18 - 18 (1 bit)
access : read-write

P19 : Output Data Status
bits : 19 - 19 (1 bit)
access : read-write

P20 : Output Data Status
bits : 20 - 20 (1 bit)
access : read-write

P21 : Output Data Status
bits : 21 - 21 (1 bit)
access : read-write

P22 : Output Data Status
bits : 22 - 22 (1 bit)
access : read-write

P23 : Output Data Status
bits : 23 - 23 (1 bit)
access : read-write

P24 : Output Data Status
bits : 24 - 24 (1 bit)
access : read-write

P25 : Output Data Status
bits : 25 - 25 (1 bit)
access : read-write

P26 : Output Data Status
bits : 26 - 26 (1 bit)
access : read-write

P27 : Output Data Status
bits : 27 - 27 (1 bit)
access : read-write

P28 : Output Data Status
bits : 28 - 28 (1 bit)
access : read-write

P29 : Output Data Status
bits : 29 - 29 (1 bit)
access : read-write

P30 : Output Data Status
bits : 30 - 30 (1 bit)
access : read-write

P31 : Output Data Status
bits : 31 - 31 (1 bit)
access : read-write


PIO_PDSR

Pin Data Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_PDSR PIO_PDSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Output Data Status
bits : 0 - 0 (1 bit)

P1 : Output Data Status
bits : 1 - 1 (1 bit)

P2 : Output Data Status
bits : 2 - 2 (1 bit)

P3 : Output Data Status
bits : 3 - 3 (1 bit)

P4 : Output Data Status
bits : 4 - 4 (1 bit)

P5 : Output Data Status
bits : 5 - 5 (1 bit)

P6 : Output Data Status
bits : 6 - 6 (1 bit)

P7 : Output Data Status
bits : 7 - 7 (1 bit)

P8 : Output Data Status
bits : 8 - 8 (1 bit)

P9 : Output Data Status
bits : 9 - 9 (1 bit)

P10 : Output Data Status
bits : 10 - 10 (1 bit)

P11 : Output Data Status
bits : 11 - 11 (1 bit)

P12 : Output Data Status
bits : 12 - 12 (1 bit)

P13 : Output Data Status
bits : 13 - 13 (1 bit)

P14 : Output Data Status
bits : 14 - 14 (1 bit)

P15 : Output Data Status
bits : 15 - 15 (1 bit)

P16 : Output Data Status
bits : 16 - 16 (1 bit)

P17 : Output Data Status
bits : 17 - 17 (1 bit)

P18 : Output Data Status
bits : 18 - 18 (1 bit)

P19 : Output Data Status
bits : 19 - 19 (1 bit)

P20 : Output Data Status
bits : 20 - 20 (1 bit)

P21 : Output Data Status
bits : 21 - 21 (1 bit)

P22 : Output Data Status
bits : 22 - 22 (1 bit)

P23 : Output Data Status
bits : 23 - 23 (1 bit)

P24 : Output Data Status
bits : 24 - 24 (1 bit)

P25 : Output Data Status
bits : 25 - 25 (1 bit)

P26 : Output Data Status
bits : 26 - 26 (1 bit)

P27 : Output Data Status
bits : 27 - 27 (1 bit)

P28 : Output Data Status
bits : 28 - 28 (1 bit)

P29 : Output Data Status
bits : 29 - 29 (1 bit)

P30 : Output Data Status
bits : 30 - 30 (1 bit)

P31 : Output Data Status
bits : 31 - 31 (1 bit)


PDSR

Pin Data Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDSR PDSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Output Data Status
bits : 0 - 0 (1 bit)
access : read-only

P1 : Output Data Status
bits : 1 - 1 (1 bit)
access : read-only

P2 : Output Data Status
bits : 2 - 2 (1 bit)
access : read-only

P3 : Output Data Status
bits : 3 - 3 (1 bit)
access : read-only

P4 : Output Data Status
bits : 4 - 4 (1 bit)
access : read-only

P5 : Output Data Status
bits : 5 - 5 (1 bit)
access : read-only

P6 : Output Data Status
bits : 6 - 6 (1 bit)
access : read-only

P7 : Output Data Status
bits : 7 - 7 (1 bit)
access : read-only

P8 : Output Data Status
bits : 8 - 8 (1 bit)
access : read-only

P9 : Output Data Status
bits : 9 - 9 (1 bit)
access : read-only

P10 : Output Data Status
bits : 10 - 10 (1 bit)
access : read-only

P11 : Output Data Status
bits : 11 - 11 (1 bit)
access : read-only

P12 : Output Data Status
bits : 12 - 12 (1 bit)
access : read-only

P13 : Output Data Status
bits : 13 - 13 (1 bit)
access : read-only

P14 : Output Data Status
bits : 14 - 14 (1 bit)
access : read-only

P15 : Output Data Status
bits : 15 - 15 (1 bit)
access : read-only

P16 : Output Data Status
bits : 16 - 16 (1 bit)
access : read-only

P17 : Output Data Status
bits : 17 - 17 (1 bit)
access : read-only

P18 : Output Data Status
bits : 18 - 18 (1 bit)
access : read-only

P19 : Output Data Status
bits : 19 - 19 (1 bit)
access : read-only

P20 : Output Data Status
bits : 20 - 20 (1 bit)
access : read-only

P21 : Output Data Status
bits : 21 - 21 (1 bit)
access : read-only

P22 : Output Data Status
bits : 22 - 22 (1 bit)
access : read-only

P23 : Output Data Status
bits : 23 - 23 (1 bit)
access : read-only

P24 : Output Data Status
bits : 24 - 24 (1 bit)
access : read-only

P25 : Output Data Status
bits : 25 - 25 (1 bit)
access : read-only

P26 : Output Data Status
bits : 26 - 26 (1 bit)
access : read-only

P27 : Output Data Status
bits : 27 - 27 (1 bit)
access : read-only

P28 : Output Data Status
bits : 28 - 28 (1 bit)
access : read-only

P29 : Output Data Status
bits : 29 - 29 (1 bit)
access : read-only

P30 : Output Data Status
bits : 30 - 30 (1 bit)
access : read-only

P31 : Output Data Status
bits : 31 - 31 (1 bit)
access : read-only


PIO_PDR

PIO Disable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_PDR PIO_PDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : PIO Disable
bits : 0 - 0 (1 bit)

P1 : PIO Disable
bits : 1 - 1 (1 bit)

P2 : PIO Disable
bits : 2 - 2 (1 bit)

P3 : PIO Disable
bits : 3 - 3 (1 bit)

P4 : PIO Disable
bits : 4 - 4 (1 bit)

P5 : PIO Disable
bits : 5 - 5 (1 bit)

P6 : PIO Disable
bits : 6 - 6 (1 bit)

P7 : PIO Disable
bits : 7 - 7 (1 bit)

P8 : PIO Disable
bits : 8 - 8 (1 bit)

P9 : PIO Disable
bits : 9 - 9 (1 bit)

P10 : PIO Disable
bits : 10 - 10 (1 bit)

P11 : PIO Disable
bits : 11 - 11 (1 bit)

P12 : PIO Disable
bits : 12 - 12 (1 bit)

P13 : PIO Disable
bits : 13 - 13 (1 bit)

P14 : PIO Disable
bits : 14 - 14 (1 bit)

P15 : PIO Disable
bits : 15 - 15 (1 bit)

P16 : PIO Disable
bits : 16 - 16 (1 bit)

P17 : PIO Disable
bits : 17 - 17 (1 bit)

P18 : PIO Disable
bits : 18 - 18 (1 bit)

P19 : PIO Disable
bits : 19 - 19 (1 bit)

P20 : PIO Disable
bits : 20 - 20 (1 bit)

P21 : PIO Disable
bits : 21 - 21 (1 bit)

P22 : PIO Disable
bits : 22 - 22 (1 bit)

P23 : PIO Disable
bits : 23 - 23 (1 bit)

P24 : PIO Disable
bits : 24 - 24 (1 bit)

P25 : PIO Disable
bits : 25 - 25 (1 bit)

P26 : PIO Disable
bits : 26 - 26 (1 bit)

P27 : PIO Disable
bits : 27 - 27 (1 bit)

P28 : PIO Disable
bits : 28 - 28 (1 bit)

P29 : PIO Disable
bits : 29 - 29 (1 bit)

P30 : PIO Disable
bits : 30 - 30 (1 bit)

P31 : PIO Disable
bits : 31 - 31 (1 bit)


PDR

PIO Disable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PDR PDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : PIO Disable
bits : 0 - 0 (1 bit)
access : write-only

P1 : PIO Disable
bits : 1 - 1 (1 bit)
access : write-only

P2 : PIO Disable
bits : 2 - 2 (1 bit)
access : write-only

P3 : PIO Disable
bits : 3 - 3 (1 bit)
access : write-only

P4 : PIO Disable
bits : 4 - 4 (1 bit)
access : write-only

P5 : PIO Disable
bits : 5 - 5 (1 bit)
access : write-only

P6 : PIO Disable
bits : 6 - 6 (1 bit)
access : write-only

P7 : PIO Disable
bits : 7 - 7 (1 bit)
access : write-only

P8 : PIO Disable
bits : 8 - 8 (1 bit)
access : write-only

P9 : PIO Disable
bits : 9 - 9 (1 bit)
access : write-only

P10 : PIO Disable
bits : 10 - 10 (1 bit)
access : write-only

P11 : PIO Disable
bits : 11 - 11 (1 bit)
access : write-only

P12 : PIO Disable
bits : 12 - 12 (1 bit)
access : write-only

P13 : PIO Disable
bits : 13 - 13 (1 bit)
access : write-only

P14 : PIO Disable
bits : 14 - 14 (1 bit)
access : write-only

P15 : PIO Disable
bits : 15 - 15 (1 bit)
access : write-only

P16 : PIO Disable
bits : 16 - 16 (1 bit)
access : write-only

P17 : PIO Disable
bits : 17 - 17 (1 bit)
access : write-only

P18 : PIO Disable
bits : 18 - 18 (1 bit)
access : write-only

P19 : PIO Disable
bits : 19 - 19 (1 bit)
access : write-only

P20 : PIO Disable
bits : 20 - 20 (1 bit)
access : write-only

P21 : PIO Disable
bits : 21 - 21 (1 bit)
access : write-only

P22 : PIO Disable
bits : 22 - 22 (1 bit)
access : write-only

P23 : PIO Disable
bits : 23 - 23 (1 bit)
access : write-only

P24 : PIO Disable
bits : 24 - 24 (1 bit)
access : write-only

P25 : PIO Disable
bits : 25 - 25 (1 bit)
access : write-only

P26 : PIO Disable
bits : 26 - 26 (1 bit)
access : write-only

P27 : PIO Disable
bits : 27 - 27 (1 bit)
access : write-only

P28 : PIO Disable
bits : 28 - 28 (1 bit)
access : write-only

P29 : PIO Disable
bits : 29 - 29 (1 bit)
access : write-only

P30 : PIO Disable
bits : 30 - 30 (1 bit)
access : write-only

P31 : PIO Disable
bits : 31 - 31 (1 bit)
access : write-only


PIO_IER

Interrupt Enable Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_IER PIO_IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Input Change Interrupt Enable
bits : 0 - 0 (1 bit)

P1 : Input Change Interrupt Enable
bits : 1 - 1 (1 bit)

P2 : Input Change Interrupt Enable
bits : 2 - 2 (1 bit)

P3 : Input Change Interrupt Enable
bits : 3 - 3 (1 bit)

P4 : Input Change Interrupt Enable
bits : 4 - 4 (1 bit)

P5 : Input Change Interrupt Enable
bits : 5 - 5 (1 bit)

P6 : Input Change Interrupt Enable
bits : 6 - 6 (1 bit)

P7 : Input Change Interrupt Enable
bits : 7 - 7 (1 bit)

P8 : Input Change Interrupt Enable
bits : 8 - 8 (1 bit)

P9 : Input Change Interrupt Enable
bits : 9 - 9 (1 bit)

P10 : Input Change Interrupt Enable
bits : 10 - 10 (1 bit)

P11 : Input Change Interrupt Enable
bits : 11 - 11 (1 bit)

P12 : Input Change Interrupt Enable
bits : 12 - 12 (1 bit)

P13 : Input Change Interrupt Enable
bits : 13 - 13 (1 bit)

P14 : Input Change Interrupt Enable
bits : 14 - 14 (1 bit)

P15 : Input Change Interrupt Enable
bits : 15 - 15 (1 bit)

P16 : Input Change Interrupt Enable
bits : 16 - 16 (1 bit)

P17 : Input Change Interrupt Enable
bits : 17 - 17 (1 bit)

P18 : Input Change Interrupt Enable
bits : 18 - 18 (1 bit)

P19 : Input Change Interrupt Enable
bits : 19 - 19 (1 bit)

P20 : Input Change Interrupt Enable
bits : 20 - 20 (1 bit)

P21 : Input Change Interrupt Enable
bits : 21 - 21 (1 bit)

P22 : Input Change Interrupt Enable
bits : 22 - 22 (1 bit)

P23 : Input Change Interrupt Enable
bits : 23 - 23 (1 bit)

P24 : Input Change Interrupt Enable
bits : 24 - 24 (1 bit)

P25 : Input Change Interrupt Enable
bits : 25 - 25 (1 bit)

P26 : Input Change Interrupt Enable
bits : 26 - 26 (1 bit)

P27 : Input Change Interrupt Enable
bits : 27 - 27 (1 bit)

P28 : Input Change Interrupt Enable
bits : 28 - 28 (1 bit)

P29 : Input Change Interrupt Enable
bits : 29 - 29 (1 bit)

P30 : Input Change Interrupt Enable
bits : 30 - 30 (1 bit)

P31 : Input Change Interrupt Enable
bits : 31 - 31 (1 bit)


IER

Interrupt Enable Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Input Change Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

P1 : Input Change Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

P2 : Input Change Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

P3 : Input Change Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

P4 : Input Change Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

P5 : Input Change Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

P6 : Input Change Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

P7 : Input Change Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

P8 : Input Change Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

P9 : Input Change Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

P10 : Input Change Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

P11 : Input Change Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

P12 : Input Change Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

P13 : Input Change Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

P14 : Input Change Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

P15 : Input Change Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only

P16 : Input Change Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only

P17 : Input Change Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only

P18 : Input Change Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

P19 : Input Change Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only

P20 : Input Change Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only

P21 : Input Change Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only

P22 : Input Change Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only

P23 : Input Change Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only

P24 : Input Change Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only

P25 : Input Change Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only

P26 : Input Change Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only

P27 : Input Change Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only

P28 : Input Change Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only

P29 : Input Change Interrupt Enable
bits : 29 - 29 (1 bit)
access : write-only

P30 : Input Change Interrupt Enable
bits : 30 - 30 (1 bit)
access : write-only

P31 : Input Change Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only


PIO_IDR

Interrupt Disable Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_IDR PIO_IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Input Change Interrupt Disable
bits : 0 - 0 (1 bit)

P1 : Input Change Interrupt Disable
bits : 1 - 1 (1 bit)

P2 : Input Change Interrupt Disable
bits : 2 - 2 (1 bit)

P3 : Input Change Interrupt Disable
bits : 3 - 3 (1 bit)

P4 : Input Change Interrupt Disable
bits : 4 - 4 (1 bit)

P5 : Input Change Interrupt Disable
bits : 5 - 5 (1 bit)

P6 : Input Change Interrupt Disable
bits : 6 - 6 (1 bit)

P7 : Input Change Interrupt Disable
bits : 7 - 7 (1 bit)

P8 : Input Change Interrupt Disable
bits : 8 - 8 (1 bit)

P9 : Input Change Interrupt Disable
bits : 9 - 9 (1 bit)

P10 : Input Change Interrupt Disable
bits : 10 - 10 (1 bit)

P11 : Input Change Interrupt Disable
bits : 11 - 11 (1 bit)

P12 : Input Change Interrupt Disable
bits : 12 - 12 (1 bit)

P13 : Input Change Interrupt Disable
bits : 13 - 13 (1 bit)

P14 : Input Change Interrupt Disable
bits : 14 - 14 (1 bit)

P15 : Input Change Interrupt Disable
bits : 15 - 15 (1 bit)

P16 : Input Change Interrupt Disable
bits : 16 - 16 (1 bit)

P17 : Input Change Interrupt Disable
bits : 17 - 17 (1 bit)

P18 : Input Change Interrupt Disable
bits : 18 - 18 (1 bit)

P19 : Input Change Interrupt Disable
bits : 19 - 19 (1 bit)

P20 : Input Change Interrupt Disable
bits : 20 - 20 (1 bit)

P21 : Input Change Interrupt Disable
bits : 21 - 21 (1 bit)

P22 : Input Change Interrupt Disable
bits : 22 - 22 (1 bit)

P23 : Input Change Interrupt Disable
bits : 23 - 23 (1 bit)

P24 : Input Change Interrupt Disable
bits : 24 - 24 (1 bit)

P25 : Input Change Interrupt Disable
bits : 25 - 25 (1 bit)

P26 : Input Change Interrupt Disable
bits : 26 - 26 (1 bit)

P27 : Input Change Interrupt Disable
bits : 27 - 27 (1 bit)

P28 : Input Change Interrupt Disable
bits : 28 - 28 (1 bit)

P29 : Input Change Interrupt Disable
bits : 29 - 29 (1 bit)

P30 : Input Change Interrupt Disable
bits : 30 - 30 (1 bit)

P31 : Input Change Interrupt Disable
bits : 31 - 31 (1 bit)


IDR

Interrupt Disable Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Input Change Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

P1 : Input Change Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

P2 : Input Change Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

P3 : Input Change Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

P4 : Input Change Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

P5 : Input Change Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

P6 : Input Change Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

P7 : Input Change Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

P8 : Input Change Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

P9 : Input Change Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

P10 : Input Change Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

P11 : Input Change Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

P12 : Input Change Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

P13 : Input Change Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

P14 : Input Change Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

P15 : Input Change Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only

P16 : Input Change Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only

P17 : Input Change Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only

P18 : Input Change Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

P19 : Input Change Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only

P20 : Input Change Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only

P21 : Input Change Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only

P22 : Input Change Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only

P23 : Input Change Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only

P24 : Input Change Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only

P25 : Input Change Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only

P26 : Input Change Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only

P27 : Input Change Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only

P28 : Input Change Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only

P29 : Input Change Interrupt Disable
bits : 29 - 29 (1 bit)
access : write-only

P30 : Input Change Interrupt Disable
bits : 30 - 30 (1 bit)
access : write-only

P31 : Input Change Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only


PIO_IMR

Interrupt Mask Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_IMR PIO_IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Input Change Interrupt Mask
bits : 0 - 0 (1 bit)

P1 : Input Change Interrupt Mask
bits : 1 - 1 (1 bit)

P2 : Input Change Interrupt Mask
bits : 2 - 2 (1 bit)

P3 : Input Change Interrupt Mask
bits : 3 - 3 (1 bit)

P4 : Input Change Interrupt Mask
bits : 4 - 4 (1 bit)

P5 : Input Change Interrupt Mask
bits : 5 - 5 (1 bit)

P6 : Input Change Interrupt Mask
bits : 6 - 6 (1 bit)

P7 : Input Change Interrupt Mask
bits : 7 - 7 (1 bit)

P8 : Input Change Interrupt Mask
bits : 8 - 8 (1 bit)

P9 : Input Change Interrupt Mask
bits : 9 - 9 (1 bit)

P10 : Input Change Interrupt Mask
bits : 10 - 10 (1 bit)

P11 : Input Change Interrupt Mask
bits : 11 - 11 (1 bit)

P12 : Input Change Interrupt Mask
bits : 12 - 12 (1 bit)

P13 : Input Change Interrupt Mask
bits : 13 - 13 (1 bit)

P14 : Input Change Interrupt Mask
bits : 14 - 14 (1 bit)

P15 : Input Change Interrupt Mask
bits : 15 - 15 (1 bit)

P16 : Input Change Interrupt Mask
bits : 16 - 16 (1 bit)

P17 : Input Change Interrupt Mask
bits : 17 - 17 (1 bit)

P18 : Input Change Interrupt Mask
bits : 18 - 18 (1 bit)

P19 : Input Change Interrupt Mask
bits : 19 - 19 (1 bit)

P20 : Input Change Interrupt Mask
bits : 20 - 20 (1 bit)

P21 : Input Change Interrupt Mask
bits : 21 - 21 (1 bit)

P22 : Input Change Interrupt Mask
bits : 22 - 22 (1 bit)

P23 : Input Change Interrupt Mask
bits : 23 - 23 (1 bit)

P24 : Input Change Interrupt Mask
bits : 24 - 24 (1 bit)

P25 : Input Change Interrupt Mask
bits : 25 - 25 (1 bit)

P26 : Input Change Interrupt Mask
bits : 26 - 26 (1 bit)

P27 : Input Change Interrupt Mask
bits : 27 - 27 (1 bit)

P28 : Input Change Interrupt Mask
bits : 28 - 28 (1 bit)

P29 : Input Change Interrupt Mask
bits : 29 - 29 (1 bit)

P30 : Input Change Interrupt Mask
bits : 30 - 30 (1 bit)

P31 : Input Change Interrupt Mask
bits : 31 - 31 (1 bit)


IMR

Interrupt Mask Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Input Change Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

P1 : Input Change Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

P2 : Input Change Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

P3 : Input Change Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only

P4 : Input Change Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only

P5 : Input Change Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only

P6 : Input Change Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only

P7 : Input Change Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only

P8 : Input Change Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only

P9 : Input Change Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only

P10 : Input Change Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only

P11 : Input Change Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only

P12 : Input Change Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only

P13 : Input Change Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only

P14 : Input Change Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only

P15 : Input Change Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only

P16 : Input Change Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only

P17 : Input Change Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only

P18 : Input Change Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only

P19 : Input Change Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only

P20 : Input Change Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only

P21 : Input Change Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only

P22 : Input Change Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only

P23 : Input Change Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only

P24 : Input Change Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only

P25 : Input Change Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only

P26 : Input Change Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only

P27 : Input Change Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only

P28 : Input Change Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only

P29 : Input Change Interrupt Mask
bits : 29 - 29 (1 bit)
access : read-only

P30 : Input Change Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-only

P31 : Input Change Interrupt Mask
bits : 31 - 31 (1 bit)
access : read-only


PIO_ISR

Interrupt Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_ISR PIO_ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Input Change Interrupt Status
bits : 0 - 0 (1 bit)

P1 : Input Change Interrupt Status
bits : 1 - 1 (1 bit)

P2 : Input Change Interrupt Status
bits : 2 - 2 (1 bit)

P3 : Input Change Interrupt Status
bits : 3 - 3 (1 bit)

P4 : Input Change Interrupt Status
bits : 4 - 4 (1 bit)

P5 : Input Change Interrupt Status
bits : 5 - 5 (1 bit)

P6 : Input Change Interrupt Status
bits : 6 - 6 (1 bit)

P7 : Input Change Interrupt Status
bits : 7 - 7 (1 bit)

P8 : Input Change Interrupt Status
bits : 8 - 8 (1 bit)

P9 : Input Change Interrupt Status
bits : 9 - 9 (1 bit)

P10 : Input Change Interrupt Status
bits : 10 - 10 (1 bit)

P11 : Input Change Interrupt Status
bits : 11 - 11 (1 bit)

P12 : Input Change Interrupt Status
bits : 12 - 12 (1 bit)

P13 : Input Change Interrupt Status
bits : 13 - 13 (1 bit)

P14 : Input Change Interrupt Status
bits : 14 - 14 (1 bit)

P15 : Input Change Interrupt Status
bits : 15 - 15 (1 bit)

P16 : Input Change Interrupt Status
bits : 16 - 16 (1 bit)

P17 : Input Change Interrupt Status
bits : 17 - 17 (1 bit)

P18 : Input Change Interrupt Status
bits : 18 - 18 (1 bit)

P19 : Input Change Interrupt Status
bits : 19 - 19 (1 bit)

P20 : Input Change Interrupt Status
bits : 20 - 20 (1 bit)

P21 : Input Change Interrupt Status
bits : 21 - 21 (1 bit)

P22 : Input Change Interrupt Status
bits : 22 - 22 (1 bit)

P23 : Input Change Interrupt Status
bits : 23 - 23 (1 bit)

P24 : Input Change Interrupt Status
bits : 24 - 24 (1 bit)

P25 : Input Change Interrupt Status
bits : 25 - 25 (1 bit)

P26 : Input Change Interrupt Status
bits : 26 - 26 (1 bit)

P27 : Input Change Interrupt Status
bits : 27 - 27 (1 bit)

P28 : Input Change Interrupt Status
bits : 28 - 28 (1 bit)

P29 : Input Change Interrupt Status
bits : 29 - 29 (1 bit)

P30 : Input Change Interrupt Status
bits : 30 - 30 (1 bit)

P31 : Input Change Interrupt Status
bits : 31 - 31 (1 bit)


ISR

Interrupt Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Input Change Interrupt Status
bits : 0 - 0 (1 bit)
access : read-only

P1 : Input Change Interrupt Status
bits : 1 - 1 (1 bit)
access : read-only

P2 : Input Change Interrupt Status
bits : 2 - 2 (1 bit)
access : read-only

P3 : Input Change Interrupt Status
bits : 3 - 3 (1 bit)
access : read-only

P4 : Input Change Interrupt Status
bits : 4 - 4 (1 bit)
access : read-only

P5 : Input Change Interrupt Status
bits : 5 - 5 (1 bit)
access : read-only

P6 : Input Change Interrupt Status
bits : 6 - 6 (1 bit)
access : read-only

P7 : Input Change Interrupt Status
bits : 7 - 7 (1 bit)
access : read-only

P8 : Input Change Interrupt Status
bits : 8 - 8 (1 bit)
access : read-only

P9 : Input Change Interrupt Status
bits : 9 - 9 (1 bit)
access : read-only

P10 : Input Change Interrupt Status
bits : 10 - 10 (1 bit)
access : read-only

P11 : Input Change Interrupt Status
bits : 11 - 11 (1 bit)
access : read-only

P12 : Input Change Interrupt Status
bits : 12 - 12 (1 bit)
access : read-only

P13 : Input Change Interrupt Status
bits : 13 - 13 (1 bit)
access : read-only

P14 : Input Change Interrupt Status
bits : 14 - 14 (1 bit)
access : read-only

P15 : Input Change Interrupt Status
bits : 15 - 15 (1 bit)
access : read-only

P16 : Input Change Interrupt Status
bits : 16 - 16 (1 bit)
access : read-only

P17 : Input Change Interrupt Status
bits : 17 - 17 (1 bit)
access : read-only

P18 : Input Change Interrupt Status
bits : 18 - 18 (1 bit)
access : read-only

P19 : Input Change Interrupt Status
bits : 19 - 19 (1 bit)
access : read-only

P20 : Input Change Interrupt Status
bits : 20 - 20 (1 bit)
access : read-only

P21 : Input Change Interrupt Status
bits : 21 - 21 (1 bit)
access : read-only

P22 : Input Change Interrupt Status
bits : 22 - 22 (1 bit)
access : read-only

P23 : Input Change Interrupt Status
bits : 23 - 23 (1 bit)
access : read-only

P24 : Input Change Interrupt Status
bits : 24 - 24 (1 bit)
access : read-only

P25 : Input Change Interrupt Status
bits : 25 - 25 (1 bit)
access : read-only

P26 : Input Change Interrupt Status
bits : 26 - 26 (1 bit)
access : read-only

P27 : Input Change Interrupt Status
bits : 27 - 27 (1 bit)
access : read-only

P28 : Input Change Interrupt Status
bits : 28 - 28 (1 bit)
access : read-only

P29 : Input Change Interrupt Status
bits : 29 - 29 (1 bit)
access : read-only

P30 : Input Change Interrupt Status
bits : 30 - 30 (1 bit)
access : read-only

P31 : Input Change Interrupt Status
bits : 31 - 31 (1 bit)
access : read-only


PIO_MDER

Multi-driver Enable Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_MDER PIO_MDER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Multi-drive Enable
bits : 0 - 0 (1 bit)

P1 : Multi-drive Enable
bits : 1 - 1 (1 bit)

P2 : Multi-drive Enable
bits : 2 - 2 (1 bit)

P3 : Multi-drive Enable
bits : 3 - 3 (1 bit)

P4 : Multi-drive Enable
bits : 4 - 4 (1 bit)

P5 : Multi-drive Enable
bits : 5 - 5 (1 bit)

P6 : Multi-drive Enable
bits : 6 - 6 (1 bit)

P7 : Multi-drive Enable
bits : 7 - 7 (1 bit)

P8 : Multi-drive Enable
bits : 8 - 8 (1 bit)

P9 : Multi-drive Enable
bits : 9 - 9 (1 bit)

P10 : Multi-drive Enable
bits : 10 - 10 (1 bit)

P11 : Multi-drive Enable
bits : 11 - 11 (1 bit)

P12 : Multi-drive Enable
bits : 12 - 12 (1 bit)

P13 : Multi-drive Enable
bits : 13 - 13 (1 bit)

P14 : Multi-drive Enable
bits : 14 - 14 (1 bit)

P15 : Multi-drive Enable
bits : 15 - 15 (1 bit)

P16 : Multi-drive Enable
bits : 16 - 16 (1 bit)

P17 : Multi-drive Enable
bits : 17 - 17 (1 bit)

P18 : Multi-drive Enable
bits : 18 - 18 (1 bit)

P19 : Multi-drive Enable
bits : 19 - 19 (1 bit)

P20 : Multi-drive Enable
bits : 20 - 20 (1 bit)

P21 : Multi-drive Enable
bits : 21 - 21 (1 bit)

P22 : Multi-drive Enable
bits : 22 - 22 (1 bit)

P23 : Multi-drive Enable
bits : 23 - 23 (1 bit)

P24 : Multi-drive Enable
bits : 24 - 24 (1 bit)

P25 : Multi-drive Enable
bits : 25 - 25 (1 bit)

P26 : Multi-drive Enable
bits : 26 - 26 (1 bit)

P27 : Multi-drive Enable
bits : 27 - 27 (1 bit)

P28 : Multi-drive Enable
bits : 28 - 28 (1 bit)

P29 : Multi-drive Enable
bits : 29 - 29 (1 bit)

P30 : Multi-drive Enable
bits : 30 - 30 (1 bit)

P31 : Multi-drive Enable
bits : 31 - 31 (1 bit)


MDER

Multi-driver Enable Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MDER MDER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Multi-drive Enable
bits : 0 - 0 (1 bit)
access : write-only

P1 : Multi-drive Enable
bits : 1 - 1 (1 bit)
access : write-only

P2 : Multi-drive Enable
bits : 2 - 2 (1 bit)
access : write-only

P3 : Multi-drive Enable
bits : 3 - 3 (1 bit)
access : write-only

P4 : Multi-drive Enable
bits : 4 - 4 (1 bit)
access : write-only

P5 : Multi-drive Enable
bits : 5 - 5 (1 bit)
access : write-only

P6 : Multi-drive Enable
bits : 6 - 6 (1 bit)
access : write-only

P7 : Multi-drive Enable
bits : 7 - 7 (1 bit)
access : write-only

P8 : Multi-drive Enable
bits : 8 - 8 (1 bit)
access : write-only

P9 : Multi-drive Enable
bits : 9 - 9 (1 bit)
access : write-only

P10 : Multi-drive Enable
bits : 10 - 10 (1 bit)
access : write-only

P11 : Multi-drive Enable
bits : 11 - 11 (1 bit)
access : write-only

P12 : Multi-drive Enable
bits : 12 - 12 (1 bit)
access : write-only

P13 : Multi-drive Enable
bits : 13 - 13 (1 bit)
access : write-only

P14 : Multi-drive Enable
bits : 14 - 14 (1 bit)
access : write-only

P15 : Multi-drive Enable
bits : 15 - 15 (1 bit)
access : write-only

P16 : Multi-drive Enable
bits : 16 - 16 (1 bit)
access : write-only

P17 : Multi-drive Enable
bits : 17 - 17 (1 bit)
access : write-only

P18 : Multi-drive Enable
bits : 18 - 18 (1 bit)
access : write-only

P19 : Multi-drive Enable
bits : 19 - 19 (1 bit)
access : write-only

P20 : Multi-drive Enable
bits : 20 - 20 (1 bit)
access : write-only

P21 : Multi-drive Enable
bits : 21 - 21 (1 bit)
access : write-only

P22 : Multi-drive Enable
bits : 22 - 22 (1 bit)
access : write-only

P23 : Multi-drive Enable
bits : 23 - 23 (1 bit)
access : write-only

P24 : Multi-drive Enable
bits : 24 - 24 (1 bit)
access : write-only

P25 : Multi-drive Enable
bits : 25 - 25 (1 bit)
access : write-only

P26 : Multi-drive Enable
bits : 26 - 26 (1 bit)
access : write-only

P27 : Multi-drive Enable
bits : 27 - 27 (1 bit)
access : write-only

P28 : Multi-drive Enable
bits : 28 - 28 (1 bit)
access : write-only

P29 : Multi-drive Enable
bits : 29 - 29 (1 bit)
access : write-only

P30 : Multi-drive Enable
bits : 30 - 30 (1 bit)
access : write-only

P31 : Multi-drive Enable
bits : 31 - 31 (1 bit)
access : write-only


PIO_MDDR

Multi-driver Disable Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_MDDR PIO_MDDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Multi-drive Disable
bits : 0 - 0 (1 bit)

P1 : Multi-drive Disable
bits : 1 - 1 (1 bit)

P2 : Multi-drive Disable
bits : 2 - 2 (1 bit)

P3 : Multi-drive Disable
bits : 3 - 3 (1 bit)

P4 : Multi-drive Disable
bits : 4 - 4 (1 bit)

P5 : Multi-drive Disable
bits : 5 - 5 (1 bit)

P6 : Multi-drive Disable
bits : 6 - 6 (1 bit)

P7 : Multi-drive Disable
bits : 7 - 7 (1 bit)

P8 : Multi-drive Disable
bits : 8 - 8 (1 bit)

P9 : Multi-drive Disable
bits : 9 - 9 (1 bit)

P10 : Multi-drive Disable
bits : 10 - 10 (1 bit)

P11 : Multi-drive Disable
bits : 11 - 11 (1 bit)

P12 : Multi-drive Disable
bits : 12 - 12 (1 bit)

P13 : Multi-drive Disable
bits : 13 - 13 (1 bit)

P14 : Multi-drive Disable
bits : 14 - 14 (1 bit)

P15 : Multi-drive Disable
bits : 15 - 15 (1 bit)

P16 : Multi-drive Disable
bits : 16 - 16 (1 bit)

P17 : Multi-drive Disable
bits : 17 - 17 (1 bit)

P18 : Multi-drive Disable
bits : 18 - 18 (1 bit)

P19 : Multi-drive Disable
bits : 19 - 19 (1 bit)

P20 : Multi-drive Disable
bits : 20 - 20 (1 bit)

P21 : Multi-drive Disable
bits : 21 - 21 (1 bit)

P22 : Multi-drive Disable
bits : 22 - 22 (1 bit)

P23 : Multi-drive Disable
bits : 23 - 23 (1 bit)

P24 : Multi-drive Disable
bits : 24 - 24 (1 bit)

P25 : Multi-drive Disable
bits : 25 - 25 (1 bit)

P26 : Multi-drive Disable
bits : 26 - 26 (1 bit)

P27 : Multi-drive Disable
bits : 27 - 27 (1 bit)

P28 : Multi-drive Disable
bits : 28 - 28 (1 bit)

P29 : Multi-drive Disable
bits : 29 - 29 (1 bit)

P30 : Multi-drive Disable
bits : 30 - 30 (1 bit)

P31 : Multi-drive Disable
bits : 31 - 31 (1 bit)


MDDR

Multi-driver Disable Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MDDR MDDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Multi-drive Disable
bits : 0 - 0 (1 bit)
access : write-only

P1 : Multi-drive Disable
bits : 1 - 1 (1 bit)
access : write-only

P2 : Multi-drive Disable
bits : 2 - 2 (1 bit)
access : write-only

P3 : Multi-drive Disable
bits : 3 - 3 (1 bit)
access : write-only

P4 : Multi-drive Disable
bits : 4 - 4 (1 bit)
access : write-only

P5 : Multi-drive Disable
bits : 5 - 5 (1 bit)
access : write-only

P6 : Multi-drive Disable
bits : 6 - 6 (1 bit)
access : write-only

P7 : Multi-drive Disable
bits : 7 - 7 (1 bit)
access : write-only

P8 : Multi-drive Disable
bits : 8 - 8 (1 bit)
access : write-only

P9 : Multi-drive Disable
bits : 9 - 9 (1 bit)
access : write-only

P10 : Multi-drive Disable
bits : 10 - 10 (1 bit)
access : write-only

P11 : Multi-drive Disable
bits : 11 - 11 (1 bit)
access : write-only

P12 : Multi-drive Disable
bits : 12 - 12 (1 bit)
access : write-only

P13 : Multi-drive Disable
bits : 13 - 13 (1 bit)
access : write-only

P14 : Multi-drive Disable
bits : 14 - 14 (1 bit)
access : write-only

P15 : Multi-drive Disable
bits : 15 - 15 (1 bit)
access : write-only

P16 : Multi-drive Disable
bits : 16 - 16 (1 bit)
access : write-only

P17 : Multi-drive Disable
bits : 17 - 17 (1 bit)
access : write-only

P18 : Multi-drive Disable
bits : 18 - 18 (1 bit)
access : write-only

P19 : Multi-drive Disable
bits : 19 - 19 (1 bit)
access : write-only

P20 : Multi-drive Disable
bits : 20 - 20 (1 bit)
access : write-only

P21 : Multi-drive Disable
bits : 21 - 21 (1 bit)
access : write-only

P22 : Multi-drive Disable
bits : 22 - 22 (1 bit)
access : write-only

P23 : Multi-drive Disable
bits : 23 - 23 (1 bit)
access : write-only

P24 : Multi-drive Disable
bits : 24 - 24 (1 bit)
access : write-only

P25 : Multi-drive Disable
bits : 25 - 25 (1 bit)
access : write-only

P26 : Multi-drive Disable
bits : 26 - 26 (1 bit)
access : write-only

P27 : Multi-drive Disable
bits : 27 - 27 (1 bit)
access : write-only

P28 : Multi-drive Disable
bits : 28 - 28 (1 bit)
access : write-only

P29 : Multi-drive Disable
bits : 29 - 29 (1 bit)
access : write-only

P30 : Multi-drive Disable
bits : 30 - 30 (1 bit)
access : write-only

P31 : Multi-drive Disable
bits : 31 - 31 (1 bit)
access : write-only


PIO_MDSR

Multi-driver Status Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_MDSR PIO_MDSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Multi-drive Status
bits : 0 - 0 (1 bit)

P1 : Multi-drive Status
bits : 1 - 1 (1 bit)

P2 : Multi-drive Status
bits : 2 - 2 (1 bit)

P3 : Multi-drive Status
bits : 3 - 3 (1 bit)

P4 : Multi-drive Status
bits : 4 - 4 (1 bit)

P5 : Multi-drive Status
bits : 5 - 5 (1 bit)

P6 : Multi-drive Status
bits : 6 - 6 (1 bit)

P7 : Multi-drive Status
bits : 7 - 7 (1 bit)

P8 : Multi-drive Status
bits : 8 - 8 (1 bit)

P9 : Multi-drive Status
bits : 9 - 9 (1 bit)

P10 : Multi-drive Status
bits : 10 - 10 (1 bit)

P11 : Multi-drive Status
bits : 11 - 11 (1 bit)

P12 : Multi-drive Status
bits : 12 - 12 (1 bit)

P13 : Multi-drive Status
bits : 13 - 13 (1 bit)

P14 : Multi-drive Status
bits : 14 - 14 (1 bit)

P15 : Multi-drive Status
bits : 15 - 15 (1 bit)

P16 : Multi-drive Status
bits : 16 - 16 (1 bit)

P17 : Multi-drive Status
bits : 17 - 17 (1 bit)

P18 : Multi-drive Status
bits : 18 - 18 (1 bit)

P19 : Multi-drive Status
bits : 19 - 19 (1 bit)

P20 : Multi-drive Status
bits : 20 - 20 (1 bit)

P21 : Multi-drive Status
bits : 21 - 21 (1 bit)

P22 : Multi-drive Status
bits : 22 - 22 (1 bit)

P23 : Multi-drive Status
bits : 23 - 23 (1 bit)

P24 : Multi-drive Status
bits : 24 - 24 (1 bit)

P25 : Multi-drive Status
bits : 25 - 25 (1 bit)

P26 : Multi-drive Status
bits : 26 - 26 (1 bit)

P27 : Multi-drive Status
bits : 27 - 27 (1 bit)

P28 : Multi-drive Status
bits : 28 - 28 (1 bit)

P29 : Multi-drive Status
bits : 29 - 29 (1 bit)

P30 : Multi-drive Status
bits : 30 - 30 (1 bit)

P31 : Multi-drive Status
bits : 31 - 31 (1 bit)


MDSR

Multi-driver Status Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MDSR MDSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Multi-drive Status
bits : 0 - 0 (1 bit)
access : read-only

P1 : Multi-drive Status
bits : 1 - 1 (1 bit)
access : read-only

P2 : Multi-drive Status
bits : 2 - 2 (1 bit)
access : read-only

P3 : Multi-drive Status
bits : 3 - 3 (1 bit)
access : read-only

P4 : Multi-drive Status
bits : 4 - 4 (1 bit)
access : read-only

P5 : Multi-drive Status
bits : 5 - 5 (1 bit)
access : read-only

P6 : Multi-drive Status
bits : 6 - 6 (1 bit)
access : read-only

P7 : Multi-drive Status
bits : 7 - 7 (1 bit)
access : read-only

P8 : Multi-drive Status
bits : 8 - 8 (1 bit)
access : read-only

P9 : Multi-drive Status
bits : 9 - 9 (1 bit)
access : read-only

P10 : Multi-drive Status
bits : 10 - 10 (1 bit)
access : read-only

P11 : Multi-drive Status
bits : 11 - 11 (1 bit)
access : read-only

P12 : Multi-drive Status
bits : 12 - 12 (1 bit)
access : read-only

P13 : Multi-drive Status
bits : 13 - 13 (1 bit)
access : read-only

P14 : Multi-drive Status
bits : 14 - 14 (1 bit)
access : read-only

P15 : Multi-drive Status
bits : 15 - 15 (1 bit)
access : read-only

P16 : Multi-drive Status
bits : 16 - 16 (1 bit)
access : read-only

P17 : Multi-drive Status
bits : 17 - 17 (1 bit)
access : read-only

P18 : Multi-drive Status
bits : 18 - 18 (1 bit)
access : read-only

P19 : Multi-drive Status
bits : 19 - 19 (1 bit)
access : read-only

P20 : Multi-drive Status
bits : 20 - 20 (1 bit)
access : read-only

P21 : Multi-drive Status
bits : 21 - 21 (1 bit)
access : read-only

P22 : Multi-drive Status
bits : 22 - 22 (1 bit)
access : read-only

P23 : Multi-drive Status
bits : 23 - 23 (1 bit)
access : read-only

P24 : Multi-drive Status
bits : 24 - 24 (1 bit)
access : read-only

P25 : Multi-drive Status
bits : 25 - 25 (1 bit)
access : read-only

P26 : Multi-drive Status
bits : 26 - 26 (1 bit)
access : read-only

P27 : Multi-drive Status
bits : 27 - 27 (1 bit)
access : read-only

P28 : Multi-drive Status
bits : 28 - 28 (1 bit)
access : read-only

P29 : Multi-drive Status
bits : 29 - 29 (1 bit)
access : read-only

P30 : Multi-drive Status
bits : 30 - 30 (1 bit)
access : read-only

P31 : Multi-drive Status
bits : 31 - 31 (1 bit)
access : read-only


PIO_PUDR

Pull-up Disable Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_PUDR PIO_PUDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Pull-Up Disable
bits : 0 - 0 (1 bit)

P1 : Pull-Up Disable
bits : 1 - 1 (1 bit)

P2 : Pull-Up Disable
bits : 2 - 2 (1 bit)

P3 : Pull-Up Disable
bits : 3 - 3 (1 bit)

P4 : Pull-Up Disable
bits : 4 - 4 (1 bit)

P5 : Pull-Up Disable
bits : 5 - 5 (1 bit)

P6 : Pull-Up Disable
bits : 6 - 6 (1 bit)

P7 : Pull-Up Disable
bits : 7 - 7 (1 bit)

P8 : Pull-Up Disable
bits : 8 - 8 (1 bit)

P9 : Pull-Up Disable
bits : 9 - 9 (1 bit)

P10 : Pull-Up Disable
bits : 10 - 10 (1 bit)

P11 : Pull-Up Disable
bits : 11 - 11 (1 bit)

P12 : Pull-Up Disable
bits : 12 - 12 (1 bit)

P13 : Pull-Up Disable
bits : 13 - 13 (1 bit)

P14 : Pull-Up Disable
bits : 14 - 14 (1 bit)

P15 : Pull-Up Disable
bits : 15 - 15 (1 bit)

P16 : Pull-Up Disable
bits : 16 - 16 (1 bit)

P17 : Pull-Up Disable
bits : 17 - 17 (1 bit)

P18 : Pull-Up Disable
bits : 18 - 18 (1 bit)

P19 : Pull-Up Disable
bits : 19 - 19 (1 bit)

P20 : Pull-Up Disable
bits : 20 - 20 (1 bit)

P21 : Pull-Up Disable
bits : 21 - 21 (1 bit)

P22 : Pull-Up Disable
bits : 22 - 22 (1 bit)

P23 : Pull-Up Disable
bits : 23 - 23 (1 bit)

P24 : Pull-Up Disable
bits : 24 - 24 (1 bit)

P25 : Pull-Up Disable
bits : 25 - 25 (1 bit)

P26 : Pull-Up Disable
bits : 26 - 26 (1 bit)

P27 : Pull-Up Disable
bits : 27 - 27 (1 bit)

P28 : Pull-Up Disable
bits : 28 - 28 (1 bit)

P29 : Pull-Up Disable
bits : 29 - 29 (1 bit)

P30 : Pull-Up Disable
bits : 30 - 30 (1 bit)

P31 : Pull-Up Disable
bits : 31 - 31 (1 bit)


PUDR

Pull-up Disable Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PUDR PUDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Pull-Up Disable
bits : 0 - 0 (1 bit)
access : write-only

P1 : Pull-Up Disable
bits : 1 - 1 (1 bit)
access : write-only

P2 : Pull-Up Disable
bits : 2 - 2 (1 bit)
access : write-only

P3 : Pull-Up Disable
bits : 3 - 3 (1 bit)
access : write-only

P4 : Pull-Up Disable
bits : 4 - 4 (1 bit)
access : write-only

P5 : Pull-Up Disable
bits : 5 - 5 (1 bit)
access : write-only

P6 : Pull-Up Disable
bits : 6 - 6 (1 bit)
access : write-only

P7 : Pull-Up Disable
bits : 7 - 7 (1 bit)
access : write-only

P8 : Pull-Up Disable
bits : 8 - 8 (1 bit)
access : write-only

P9 : Pull-Up Disable
bits : 9 - 9 (1 bit)
access : write-only

P10 : Pull-Up Disable
bits : 10 - 10 (1 bit)
access : write-only

P11 : Pull-Up Disable
bits : 11 - 11 (1 bit)
access : write-only

P12 : Pull-Up Disable
bits : 12 - 12 (1 bit)
access : write-only

P13 : Pull-Up Disable
bits : 13 - 13 (1 bit)
access : write-only

P14 : Pull-Up Disable
bits : 14 - 14 (1 bit)
access : write-only

P15 : Pull-Up Disable
bits : 15 - 15 (1 bit)
access : write-only

P16 : Pull-Up Disable
bits : 16 - 16 (1 bit)
access : write-only

P17 : Pull-Up Disable
bits : 17 - 17 (1 bit)
access : write-only

P18 : Pull-Up Disable
bits : 18 - 18 (1 bit)
access : write-only

P19 : Pull-Up Disable
bits : 19 - 19 (1 bit)
access : write-only

P20 : Pull-Up Disable
bits : 20 - 20 (1 bit)
access : write-only

P21 : Pull-Up Disable
bits : 21 - 21 (1 bit)
access : write-only

P22 : Pull-Up Disable
bits : 22 - 22 (1 bit)
access : write-only

P23 : Pull-Up Disable
bits : 23 - 23 (1 bit)
access : write-only

P24 : Pull-Up Disable
bits : 24 - 24 (1 bit)
access : write-only

P25 : Pull-Up Disable
bits : 25 - 25 (1 bit)
access : write-only

P26 : Pull-Up Disable
bits : 26 - 26 (1 bit)
access : write-only

P27 : Pull-Up Disable
bits : 27 - 27 (1 bit)
access : write-only

P28 : Pull-Up Disable
bits : 28 - 28 (1 bit)
access : write-only

P29 : Pull-Up Disable
bits : 29 - 29 (1 bit)
access : write-only

P30 : Pull-Up Disable
bits : 30 - 30 (1 bit)
access : write-only

P31 : Pull-Up Disable
bits : 31 - 31 (1 bit)
access : write-only


PIO_PUER

Pull-up Enable Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_PUER PIO_PUER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Pull-Up Enable
bits : 0 - 0 (1 bit)

P1 : Pull-Up Enable
bits : 1 - 1 (1 bit)

P2 : Pull-Up Enable
bits : 2 - 2 (1 bit)

P3 : Pull-Up Enable
bits : 3 - 3 (1 bit)

P4 : Pull-Up Enable
bits : 4 - 4 (1 bit)

P5 : Pull-Up Enable
bits : 5 - 5 (1 bit)

P6 : Pull-Up Enable
bits : 6 - 6 (1 bit)

P7 : Pull-Up Enable
bits : 7 - 7 (1 bit)

P8 : Pull-Up Enable
bits : 8 - 8 (1 bit)

P9 : Pull-Up Enable
bits : 9 - 9 (1 bit)

P10 : Pull-Up Enable
bits : 10 - 10 (1 bit)

P11 : Pull-Up Enable
bits : 11 - 11 (1 bit)

P12 : Pull-Up Enable
bits : 12 - 12 (1 bit)

P13 : Pull-Up Enable
bits : 13 - 13 (1 bit)

P14 : Pull-Up Enable
bits : 14 - 14 (1 bit)

P15 : Pull-Up Enable
bits : 15 - 15 (1 bit)

P16 : Pull-Up Enable
bits : 16 - 16 (1 bit)

P17 : Pull-Up Enable
bits : 17 - 17 (1 bit)

P18 : Pull-Up Enable
bits : 18 - 18 (1 bit)

P19 : Pull-Up Enable
bits : 19 - 19 (1 bit)

P20 : Pull-Up Enable
bits : 20 - 20 (1 bit)

P21 : Pull-Up Enable
bits : 21 - 21 (1 bit)

P22 : Pull-Up Enable
bits : 22 - 22 (1 bit)

P23 : Pull-Up Enable
bits : 23 - 23 (1 bit)

P24 : Pull-Up Enable
bits : 24 - 24 (1 bit)

P25 : Pull-Up Enable
bits : 25 - 25 (1 bit)

P26 : Pull-Up Enable
bits : 26 - 26 (1 bit)

P27 : Pull-Up Enable
bits : 27 - 27 (1 bit)

P28 : Pull-Up Enable
bits : 28 - 28 (1 bit)

P29 : Pull-Up Enable
bits : 29 - 29 (1 bit)

P30 : Pull-Up Enable
bits : 30 - 30 (1 bit)

P31 : Pull-Up Enable
bits : 31 - 31 (1 bit)


PUER

Pull-up Enable Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PUER PUER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Pull-Up Enable
bits : 0 - 0 (1 bit)
access : write-only

P1 : Pull-Up Enable
bits : 1 - 1 (1 bit)
access : write-only

P2 : Pull-Up Enable
bits : 2 - 2 (1 bit)
access : write-only

P3 : Pull-Up Enable
bits : 3 - 3 (1 bit)
access : write-only

P4 : Pull-Up Enable
bits : 4 - 4 (1 bit)
access : write-only

P5 : Pull-Up Enable
bits : 5 - 5 (1 bit)
access : write-only

P6 : Pull-Up Enable
bits : 6 - 6 (1 bit)
access : write-only

P7 : Pull-Up Enable
bits : 7 - 7 (1 bit)
access : write-only

P8 : Pull-Up Enable
bits : 8 - 8 (1 bit)
access : write-only

P9 : Pull-Up Enable
bits : 9 - 9 (1 bit)
access : write-only

P10 : Pull-Up Enable
bits : 10 - 10 (1 bit)
access : write-only

P11 : Pull-Up Enable
bits : 11 - 11 (1 bit)
access : write-only

P12 : Pull-Up Enable
bits : 12 - 12 (1 bit)
access : write-only

P13 : Pull-Up Enable
bits : 13 - 13 (1 bit)
access : write-only

P14 : Pull-Up Enable
bits : 14 - 14 (1 bit)
access : write-only

P15 : Pull-Up Enable
bits : 15 - 15 (1 bit)
access : write-only

P16 : Pull-Up Enable
bits : 16 - 16 (1 bit)
access : write-only

P17 : Pull-Up Enable
bits : 17 - 17 (1 bit)
access : write-only

P18 : Pull-Up Enable
bits : 18 - 18 (1 bit)
access : write-only

P19 : Pull-Up Enable
bits : 19 - 19 (1 bit)
access : write-only

P20 : Pull-Up Enable
bits : 20 - 20 (1 bit)
access : write-only

P21 : Pull-Up Enable
bits : 21 - 21 (1 bit)
access : write-only

P22 : Pull-Up Enable
bits : 22 - 22 (1 bit)
access : write-only

P23 : Pull-Up Enable
bits : 23 - 23 (1 bit)
access : write-only

P24 : Pull-Up Enable
bits : 24 - 24 (1 bit)
access : write-only

P25 : Pull-Up Enable
bits : 25 - 25 (1 bit)
access : write-only

P26 : Pull-Up Enable
bits : 26 - 26 (1 bit)
access : write-only

P27 : Pull-Up Enable
bits : 27 - 27 (1 bit)
access : write-only

P28 : Pull-Up Enable
bits : 28 - 28 (1 bit)
access : write-only

P29 : Pull-Up Enable
bits : 29 - 29 (1 bit)
access : write-only

P30 : Pull-Up Enable
bits : 30 - 30 (1 bit)
access : write-only

P31 : Pull-Up Enable
bits : 31 - 31 (1 bit)
access : write-only


PIO_PUSR

Pad Pull-up Status Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_PUSR PIO_PUSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Pull-Up Status
bits : 0 - 0 (1 bit)

P1 : Pull-Up Status
bits : 1 - 1 (1 bit)

P2 : Pull-Up Status
bits : 2 - 2 (1 bit)

P3 : Pull-Up Status
bits : 3 - 3 (1 bit)

P4 : Pull-Up Status
bits : 4 - 4 (1 bit)

P5 : Pull-Up Status
bits : 5 - 5 (1 bit)

P6 : Pull-Up Status
bits : 6 - 6 (1 bit)

P7 : Pull-Up Status
bits : 7 - 7 (1 bit)

P8 : Pull-Up Status
bits : 8 - 8 (1 bit)

P9 : Pull-Up Status
bits : 9 - 9 (1 bit)

P10 : Pull-Up Status
bits : 10 - 10 (1 bit)

P11 : Pull-Up Status
bits : 11 - 11 (1 bit)

P12 : Pull-Up Status
bits : 12 - 12 (1 bit)

P13 : Pull-Up Status
bits : 13 - 13 (1 bit)

P14 : Pull-Up Status
bits : 14 - 14 (1 bit)

P15 : Pull-Up Status
bits : 15 - 15 (1 bit)

P16 : Pull-Up Status
bits : 16 - 16 (1 bit)

P17 : Pull-Up Status
bits : 17 - 17 (1 bit)

P18 : Pull-Up Status
bits : 18 - 18 (1 bit)

P19 : Pull-Up Status
bits : 19 - 19 (1 bit)

P20 : Pull-Up Status
bits : 20 - 20 (1 bit)

P21 : Pull-Up Status
bits : 21 - 21 (1 bit)

P22 : Pull-Up Status
bits : 22 - 22 (1 bit)

P23 : Pull-Up Status
bits : 23 - 23 (1 bit)

P24 : Pull-Up Status
bits : 24 - 24 (1 bit)

P25 : Pull-Up Status
bits : 25 - 25 (1 bit)

P26 : Pull-Up Status
bits : 26 - 26 (1 bit)

P27 : Pull-Up Status
bits : 27 - 27 (1 bit)

P28 : Pull-Up Status
bits : 28 - 28 (1 bit)

P29 : Pull-Up Status
bits : 29 - 29 (1 bit)

P30 : Pull-Up Status
bits : 30 - 30 (1 bit)

P31 : Pull-Up Status
bits : 31 - 31 (1 bit)


PUSR

Pad Pull-up Status Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PUSR PUSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Pull-Up Status
bits : 0 - 0 (1 bit)
access : read-only

P1 : Pull-Up Status
bits : 1 - 1 (1 bit)
access : read-only

P2 : Pull-Up Status
bits : 2 - 2 (1 bit)
access : read-only

P3 : Pull-Up Status
bits : 3 - 3 (1 bit)
access : read-only

P4 : Pull-Up Status
bits : 4 - 4 (1 bit)
access : read-only

P5 : Pull-Up Status
bits : 5 - 5 (1 bit)
access : read-only

P6 : Pull-Up Status
bits : 6 - 6 (1 bit)
access : read-only

P7 : Pull-Up Status
bits : 7 - 7 (1 bit)
access : read-only

P8 : Pull-Up Status
bits : 8 - 8 (1 bit)
access : read-only

P9 : Pull-Up Status
bits : 9 - 9 (1 bit)
access : read-only

P10 : Pull-Up Status
bits : 10 - 10 (1 bit)
access : read-only

P11 : Pull-Up Status
bits : 11 - 11 (1 bit)
access : read-only

P12 : Pull-Up Status
bits : 12 - 12 (1 bit)
access : read-only

P13 : Pull-Up Status
bits : 13 - 13 (1 bit)
access : read-only

P14 : Pull-Up Status
bits : 14 - 14 (1 bit)
access : read-only

P15 : Pull-Up Status
bits : 15 - 15 (1 bit)
access : read-only

P16 : Pull-Up Status
bits : 16 - 16 (1 bit)
access : read-only

P17 : Pull-Up Status
bits : 17 - 17 (1 bit)
access : read-only

P18 : Pull-Up Status
bits : 18 - 18 (1 bit)
access : read-only

P19 : Pull-Up Status
bits : 19 - 19 (1 bit)
access : read-only

P20 : Pull-Up Status
bits : 20 - 20 (1 bit)
access : read-only

P21 : Pull-Up Status
bits : 21 - 21 (1 bit)
access : read-only

P22 : Pull-Up Status
bits : 22 - 22 (1 bit)
access : read-only

P23 : Pull-Up Status
bits : 23 - 23 (1 bit)
access : read-only

P24 : Pull-Up Status
bits : 24 - 24 (1 bit)
access : read-only

P25 : Pull-Up Status
bits : 25 - 25 (1 bit)
access : read-only

P26 : Pull-Up Status
bits : 26 - 26 (1 bit)
access : read-only

P27 : Pull-Up Status
bits : 27 - 27 (1 bit)
access : read-only

P28 : Pull-Up Status
bits : 28 - 28 (1 bit)
access : read-only

P29 : Pull-Up Status
bits : 29 - 29 (1 bit)
access : read-only

P30 : Pull-Up Status
bits : 30 - 30 (1 bit)
access : read-only

P31 : Pull-Up Status
bits : 31 - 31 (1 bit)
access : read-only


PIO_ABCDSR0

Peripheral ABCD Select Register 0
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO_ABCDSR0 PIO_ABCDSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Peripheral Select
bits : 0 - 0 (1 bit)

P1 : Peripheral Select
bits : 1 - 1 (1 bit)

P2 : Peripheral Select
bits : 2 - 2 (1 bit)

P3 : Peripheral Select
bits : 3 - 3 (1 bit)

P4 : Peripheral Select
bits : 4 - 4 (1 bit)

P5 : Peripheral Select
bits : 5 - 5 (1 bit)

P6 : Peripheral Select
bits : 6 - 6 (1 bit)

P7 : Peripheral Select
bits : 7 - 7 (1 bit)

P8 : Peripheral Select
bits : 8 - 8 (1 bit)

P9 : Peripheral Select
bits : 9 - 9 (1 bit)

P10 : Peripheral Select
bits : 10 - 10 (1 bit)

P11 : Peripheral Select
bits : 11 - 11 (1 bit)

P12 : Peripheral Select
bits : 12 - 12 (1 bit)

P13 : Peripheral Select
bits : 13 - 13 (1 bit)

P14 : Peripheral Select
bits : 14 - 14 (1 bit)

P15 : Peripheral Select
bits : 15 - 15 (1 bit)

P16 : Peripheral Select
bits : 16 - 16 (1 bit)

P17 : Peripheral Select
bits : 17 - 17 (1 bit)

P18 : Peripheral Select
bits : 18 - 18 (1 bit)

P19 : Peripheral Select
bits : 19 - 19 (1 bit)

P20 : Peripheral Select
bits : 20 - 20 (1 bit)

P21 : Peripheral Select
bits : 21 - 21 (1 bit)

P22 : Peripheral Select
bits : 22 - 22 (1 bit)

P23 : Peripheral Select
bits : 23 - 23 (1 bit)

P24 : Peripheral Select
bits : 24 - 24 (1 bit)

P25 : Peripheral Select
bits : 25 - 25 (1 bit)

P26 : Peripheral Select
bits : 26 - 26 (1 bit)

P27 : Peripheral Select
bits : 27 - 27 (1 bit)

P28 : Peripheral Select
bits : 28 - 28 (1 bit)

P29 : Peripheral Select
bits : 29 - 29 (1 bit)

P30 : Peripheral Select
bits : 30 - 30 (1 bit)

P31 : Peripheral Select
bits : 31 - 31 (1 bit)


ABCDSR0

Peripheral ABCD Select Register 0
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ABCDSR0 ABCDSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Peripheral Select
bits : 0 - 0 (1 bit)
access : read-write

P1 : Peripheral Select
bits : 1 - 1 (1 bit)
access : read-write

P2 : Peripheral Select
bits : 2 - 2 (1 bit)
access : read-write

P3 : Peripheral Select
bits : 3 - 3 (1 bit)
access : read-write

P4 : Peripheral Select
bits : 4 - 4 (1 bit)
access : read-write

P5 : Peripheral Select
bits : 5 - 5 (1 bit)
access : read-write

P6 : Peripheral Select
bits : 6 - 6 (1 bit)
access : read-write

P7 : Peripheral Select
bits : 7 - 7 (1 bit)
access : read-write

P8 : Peripheral Select
bits : 8 - 8 (1 bit)
access : read-write

P9 : Peripheral Select
bits : 9 - 9 (1 bit)
access : read-write

P10 : Peripheral Select
bits : 10 - 10 (1 bit)
access : read-write

P11 : Peripheral Select
bits : 11 - 11 (1 bit)
access : read-write

P12 : Peripheral Select
bits : 12 - 12 (1 bit)
access : read-write

P13 : Peripheral Select
bits : 13 - 13 (1 bit)
access : read-write

P14 : Peripheral Select
bits : 14 - 14 (1 bit)
access : read-write

P15 : Peripheral Select
bits : 15 - 15 (1 bit)
access : read-write

P16 : Peripheral Select
bits : 16 - 16 (1 bit)
access : read-write

P17 : Peripheral Select
bits : 17 - 17 (1 bit)
access : read-write

P18 : Peripheral Select
bits : 18 - 18 (1 bit)
access : read-write

P19 : Peripheral Select
bits : 19 - 19 (1 bit)
access : read-write

P20 : Peripheral Select
bits : 20 - 20 (1 bit)
access : read-write

P21 : Peripheral Select
bits : 21 - 21 (1 bit)
access : read-write

P22 : Peripheral Select
bits : 22 - 22 (1 bit)
access : read-write

P23 : Peripheral Select
bits : 23 - 23 (1 bit)
access : read-write

P24 : Peripheral Select
bits : 24 - 24 (1 bit)
access : read-write

P25 : Peripheral Select
bits : 25 - 25 (1 bit)
access : read-write

P26 : Peripheral Select
bits : 26 - 26 (1 bit)
access : read-write

P27 : Peripheral Select
bits : 27 - 27 (1 bit)
access : read-write

P28 : Peripheral Select
bits : 28 - 28 (1 bit)
access : read-write

P29 : Peripheral Select
bits : 29 - 29 (1 bit)
access : read-write

P30 : Peripheral Select
bits : 30 - 30 (1 bit)
access : read-write

P31 : Peripheral Select
bits : 31 - 31 (1 bit)
access : read-write


PIO_ABCDSR1

Peripheral ABCD Select Register 0
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO_ABCDSR1 PIO_ABCDSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Peripheral Select
bits : 0 - 0 (1 bit)

P1 : Peripheral Select
bits : 1 - 1 (1 bit)

P2 : Peripheral Select
bits : 2 - 2 (1 bit)

P3 : Peripheral Select
bits : 3 - 3 (1 bit)

P4 : Peripheral Select
bits : 4 - 4 (1 bit)

P5 : Peripheral Select
bits : 5 - 5 (1 bit)

P6 : Peripheral Select
bits : 6 - 6 (1 bit)

P7 : Peripheral Select
bits : 7 - 7 (1 bit)

P8 : Peripheral Select
bits : 8 - 8 (1 bit)

P9 : Peripheral Select
bits : 9 - 9 (1 bit)

P10 : Peripheral Select
bits : 10 - 10 (1 bit)

P11 : Peripheral Select
bits : 11 - 11 (1 bit)

P12 : Peripheral Select
bits : 12 - 12 (1 bit)

P13 : Peripheral Select
bits : 13 - 13 (1 bit)

P14 : Peripheral Select
bits : 14 - 14 (1 bit)

P15 : Peripheral Select
bits : 15 - 15 (1 bit)

P16 : Peripheral Select
bits : 16 - 16 (1 bit)

P17 : Peripheral Select
bits : 17 - 17 (1 bit)

P18 : Peripheral Select
bits : 18 - 18 (1 bit)

P19 : Peripheral Select
bits : 19 - 19 (1 bit)

P20 : Peripheral Select
bits : 20 - 20 (1 bit)

P21 : Peripheral Select
bits : 21 - 21 (1 bit)

P22 : Peripheral Select
bits : 22 - 22 (1 bit)

P23 : Peripheral Select
bits : 23 - 23 (1 bit)

P24 : Peripheral Select
bits : 24 - 24 (1 bit)

P25 : Peripheral Select
bits : 25 - 25 (1 bit)

P26 : Peripheral Select
bits : 26 - 26 (1 bit)

P27 : Peripheral Select
bits : 27 - 27 (1 bit)

P28 : Peripheral Select
bits : 28 - 28 (1 bit)

P29 : Peripheral Select
bits : 29 - 29 (1 bit)

P30 : Peripheral Select
bits : 30 - 30 (1 bit)

P31 : Peripheral Select
bits : 31 - 31 (1 bit)


ABCDSR1

Peripheral ABCD Select Register 0
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ABCDSR1 ABCDSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Peripheral Select
bits : 0 - 0 (1 bit)
access : read-write

P1 : Peripheral Select
bits : 1 - 1 (1 bit)
access : read-write

P2 : Peripheral Select
bits : 2 - 2 (1 bit)
access : read-write

P3 : Peripheral Select
bits : 3 - 3 (1 bit)
access : read-write

P4 : Peripheral Select
bits : 4 - 4 (1 bit)
access : read-write

P5 : Peripheral Select
bits : 5 - 5 (1 bit)
access : read-write

P6 : Peripheral Select
bits : 6 - 6 (1 bit)
access : read-write

P7 : Peripheral Select
bits : 7 - 7 (1 bit)
access : read-write

P8 : Peripheral Select
bits : 8 - 8 (1 bit)
access : read-write

P9 : Peripheral Select
bits : 9 - 9 (1 bit)
access : read-write

P10 : Peripheral Select
bits : 10 - 10 (1 bit)
access : read-write

P11 : Peripheral Select
bits : 11 - 11 (1 bit)
access : read-write

P12 : Peripheral Select
bits : 12 - 12 (1 bit)
access : read-write

P13 : Peripheral Select
bits : 13 - 13 (1 bit)
access : read-write

P14 : Peripheral Select
bits : 14 - 14 (1 bit)
access : read-write

P15 : Peripheral Select
bits : 15 - 15 (1 bit)
access : read-write

P16 : Peripheral Select
bits : 16 - 16 (1 bit)
access : read-write

P17 : Peripheral Select
bits : 17 - 17 (1 bit)
access : read-write

P18 : Peripheral Select
bits : 18 - 18 (1 bit)
access : read-write

P19 : Peripheral Select
bits : 19 - 19 (1 bit)
access : read-write

P20 : Peripheral Select
bits : 20 - 20 (1 bit)
access : read-write

P21 : Peripheral Select
bits : 21 - 21 (1 bit)
access : read-write

P22 : Peripheral Select
bits : 22 - 22 (1 bit)
access : read-write

P23 : Peripheral Select
bits : 23 - 23 (1 bit)
access : read-write

P24 : Peripheral Select
bits : 24 - 24 (1 bit)
access : read-write

P25 : Peripheral Select
bits : 25 - 25 (1 bit)
access : read-write

P26 : Peripheral Select
bits : 26 - 26 (1 bit)
access : read-write

P27 : Peripheral Select
bits : 27 - 27 (1 bit)
access : read-write

P28 : Peripheral Select
bits : 28 - 28 (1 bit)
access : read-write

P29 : Peripheral Select
bits : 29 - 29 (1 bit)
access : read-write

P30 : Peripheral Select
bits : 30 - 30 (1 bit)
access : read-write

P31 : Peripheral Select
bits : 31 - 31 (1 bit)
access : read-write


PIO_PSR

PIO Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_PSR PIO_PSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : PIO Status
bits : 0 - 0 (1 bit)

P1 : PIO Status
bits : 1 - 1 (1 bit)

P2 : PIO Status
bits : 2 - 2 (1 bit)

P3 : PIO Status
bits : 3 - 3 (1 bit)

P4 : PIO Status
bits : 4 - 4 (1 bit)

P5 : PIO Status
bits : 5 - 5 (1 bit)

P6 : PIO Status
bits : 6 - 6 (1 bit)

P7 : PIO Status
bits : 7 - 7 (1 bit)

P8 : PIO Status
bits : 8 - 8 (1 bit)

P9 : PIO Status
bits : 9 - 9 (1 bit)

P10 : PIO Status
bits : 10 - 10 (1 bit)

P11 : PIO Status
bits : 11 - 11 (1 bit)

P12 : PIO Status
bits : 12 - 12 (1 bit)

P13 : PIO Status
bits : 13 - 13 (1 bit)

P14 : PIO Status
bits : 14 - 14 (1 bit)

P15 : PIO Status
bits : 15 - 15 (1 bit)

P16 : PIO Status
bits : 16 - 16 (1 bit)

P17 : PIO Status
bits : 17 - 17 (1 bit)

P18 : PIO Status
bits : 18 - 18 (1 bit)

P19 : PIO Status
bits : 19 - 19 (1 bit)

P20 : PIO Status
bits : 20 - 20 (1 bit)

P21 : PIO Status
bits : 21 - 21 (1 bit)

P22 : PIO Status
bits : 22 - 22 (1 bit)

P23 : PIO Status
bits : 23 - 23 (1 bit)

P24 : PIO Status
bits : 24 - 24 (1 bit)

P25 : PIO Status
bits : 25 - 25 (1 bit)

P26 : PIO Status
bits : 26 - 26 (1 bit)

P27 : PIO Status
bits : 27 - 27 (1 bit)

P28 : PIO Status
bits : 28 - 28 (1 bit)

P29 : PIO Status
bits : 29 - 29 (1 bit)

P30 : PIO Status
bits : 30 - 30 (1 bit)

P31 : PIO Status
bits : 31 - 31 (1 bit)


PSR

PIO Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PSR PSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : PIO Status
bits : 0 - 0 (1 bit)
access : read-only

P1 : PIO Status
bits : 1 - 1 (1 bit)
access : read-only

P2 : PIO Status
bits : 2 - 2 (1 bit)
access : read-only

P3 : PIO Status
bits : 3 - 3 (1 bit)
access : read-only

P4 : PIO Status
bits : 4 - 4 (1 bit)
access : read-only

P5 : PIO Status
bits : 5 - 5 (1 bit)
access : read-only

P6 : PIO Status
bits : 6 - 6 (1 bit)
access : read-only

P7 : PIO Status
bits : 7 - 7 (1 bit)
access : read-only

P8 : PIO Status
bits : 8 - 8 (1 bit)
access : read-only

P9 : PIO Status
bits : 9 - 9 (1 bit)
access : read-only

P10 : PIO Status
bits : 10 - 10 (1 bit)
access : read-only

P11 : PIO Status
bits : 11 - 11 (1 bit)
access : read-only

P12 : PIO Status
bits : 12 - 12 (1 bit)
access : read-only

P13 : PIO Status
bits : 13 - 13 (1 bit)
access : read-only

P14 : PIO Status
bits : 14 - 14 (1 bit)
access : read-only

P15 : PIO Status
bits : 15 - 15 (1 bit)
access : read-only

P16 : PIO Status
bits : 16 - 16 (1 bit)
access : read-only

P17 : PIO Status
bits : 17 - 17 (1 bit)
access : read-only

P18 : PIO Status
bits : 18 - 18 (1 bit)
access : read-only

P19 : PIO Status
bits : 19 - 19 (1 bit)
access : read-only

P20 : PIO Status
bits : 20 - 20 (1 bit)
access : read-only

P21 : PIO Status
bits : 21 - 21 (1 bit)
access : read-only

P22 : PIO Status
bits : 22 - 22 (1 bit)
access : read-only

P23 : PIO Status
bits : 23 - 23 (1 bit)
access : read-only

P24 : PIO Status
bits : 24 - 24 (1 bit)
access : read-only

P25 : PIO Status
bits : 25 - 25 (1 bit)
access : read-only

P26 : PIO Status
bits : 26 - 26 (1 bit)
access : read-only

P27 : PIO Status
bits : 27 - 27 (1 bit)
access : read-only

P28 : PIO Status
bits : 28 - 28 (1 bit)
access : read-only

P29 : PIO Status
bits : 29 - 29 (1 bit)
access : read-only

P30 : PIO Status
bits : 30 - 30 (1 bit)
access : read-only

P31 : PIO Status
bits : 31 - 31 (1 bit)
access : read-only


PIO_IFSCDR

Input Filter Slow Clock Disable Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_IFSCDR PIO_IFSCDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Peripheral Clock Glitch Filtering Select
bits : 0 - 0 (1 bit)

P1 : Peripheral Clock Glitch Filtering Select
bits : 1 - 1 (1 bit)

P2 : Peripheral Clock Glitch Filtering Select
bits : 2 - 2 (1 bit)

P3 : Peripheral Clock Glitch Filtering Select
bits : 3 - 3 (1 bit)

P4 : Peripheral Clock Glitch Filtering Select
bits : 4 - 4 (1 bit)

P5 : Peripheral Clock Glitch Filtering Select
bits : 5 - 5 (1 bit)

P6 : Peripheral Clock Glitch Filtering Select
bits : 6 - 6 (1 bit)

P7 : Peripheral Clock Glitch Filtering Select
bits : 7 - 7 (1 bit)

P8 : Peripheral Clock Glitch Filtering Select
bits : 8 - 8 (1 bit)

P9 : Peripheral Clock Glitch Filtering Select
bits : 9 - 9 (1 bit)

P10 : Peripheral Clock Glitch Filtering Select
bits : 10 - 10 (1 bit)

P11 : Peripheral Clock Glitch Filtering Select
bits : 11 - 11 (1 bit)

P12 : Peripheral Clock Glitch Filtering Select
bits : 12 - 12 (1 bit)

P13 : Peripheral Clock Glitch Filtering Select
bits : 13 - 13 (1 bit)

P14 : Peripheral Clock Glitch Filtering Select
bits : 14 - 14 (1 bit)

P15 : Peripheral Clock Glitch Filtering Select
bits : 15 - 15 (1 bit)

P16 : Peripheral Clock Glitch Filtering Select
bits : 16 - 16 (1 bit)

P17 : Peripheral Clock Glitch Filtering Select
bits : 17 - 17 (1 bit)

P18 : Peripheral Clock Glitch Filtering Select
bits : 18 - 18 (1 bit)

P19 : Peripheral Clock Glitch Filtering Select
bits : 19 - 19 (1 bit)

P20 : Peripheral Clock Glitch Filtering Select
bits : 20 - 20 (1 bit)

P21 : Peripheral Clock Glitch Filtering Select
bits : 21 - 21 (1 bit)

P22 : Peripheral Clock Glitch Filtering Select
bits : 22 - 22 (1 bit)

P23 : Peripheral Clock Glitch Filtering Select
bits : 23 - 23 (1 bit)

P24 : Peripheral Clock Glitch Filtering Select
bits : 24 - 24 (1 bit)

P25 : Peripheral Clock Glitch Filtering Select
bits : 25 - 25 (1 bit)

P26 : Peripheral Clock Glitch Filtering Select
bits : 26 - 26 (1 bit)

P27 : Peripheral Clock Glitch Filtering Select
bits : 27 - 27 (1 bit)

P28 : Peripheral Clock Glitch Filtering Select
bits : 28 - 28 (1 bit)

P29 : Peripheral Clock Glitch Filtering Select
bits : 29 - 29 (1 bit)

P30 : Peripheral Clock Glitch Filtering Select
bits : 30 - 30 (1 bit)

P31 : Peripheral Clock Glitch Filtering Select
bits : 31 - 31 (1 bit)


IFSCDR

Input Filter Slow Clock Disable Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFSCDR IFSCDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Peripheral Clock Glitch Filtering Select
bits : 0 - 0 (1 bit)
access : write-only

P1 : Peripheral Clock Glitch Filtering Select
bits : 1 - 1 (1 bit)
access : write-only

P2 : Peripheral Clock Glitch Filtering Select
bits : 2 - 2 (1 bit)
access : write-only

P3 : Peripheral Clock Glitch Filtering Select
bits : 3 - 3 (1 bit)
access : write-only

P4 : Peripheral Clock Glitch Filtering Select
bits : 4 - 4 (1 bit)
access : write-only

P5 : Peripheral Clock Glitch Filtering Select
bits : 5 - 5 (1 bit)
access : write-only

P6 : Peripheral Clock Glitch Filtering Select
bits : 6 - 6 (1 bit)
access : write-only

P7 : Peripheral Clock Glitch Filtering Select
bits : 7 - 7 (1 bit)
access : write-only

P8 : Peripheral Clock Glitch Filtering Select
bits : 8 - 8 (1 bit)
access : write-only

P9 : Peripheral Clock Glitch Filtering Select
bits : 9 - 9 (1 bit)
access : write-only

P10 : Peripheral Clock Glitch Filtering Select
bits : 10 - 10 (1 bit)
access : write-only

P11 : Peripheral Clock Glitch Filtering Select
bits : 11 - 11 (1 bit)
access : write-only

P12 : Peripheral Clock Glitch Filtering Select
bits : 12 - 12 (1 bit)
access : write-only

P13 : Peripheral Clock Glitch Filtering Select
bits : 13 - 13 (1 bit)
access : write-only

P14 : Peripheral Clock Glitch Filtering Select
bits : 14 - 14 (1 bit)
access : write-only

P15 : Peripheral Clock Glitch Filtering Select
bits : 15 - 15 (1 bit)
access : write-only

P16 : Peripheral Clock Glitch Filtering Select
bits : 16 - 16 (1 bit)
access : write-only

P17 : Peripheral Clock Glitch Filtering Select
bits : 17 - 17 (1 bit)
access : write-only

P18 : Peripheral Clock Glitch Filtering Select
bits : 18 - 18 (1 bit)
access : write-only

P19 : Peripheral Clock Glitch Filtering Select
bits : 19 - 19 (1 bit)
access : write-only

P20 : Peripheral Clock Glitch Filtering Select
bits : 20 - 20 (1 bit)
access : write-only

P21 : Peripheral Clock Glitch Filtering Select
bits : 21 - 21 (1 bit)
access : write-only

P22 : Peripheral Clock Glitch Filtering Select
bits : 22 - 22 (1 bit)
access : write-only

P23 : Peripheral Clock Glitch Filtering Select
bits : 23 - 23 (1 bit)
access : write-only

P24 : Peripheral Clock Glitch Filtering Select
bits : 24 - 24 (1 bit)
access : write-only

P25 : Peripheral Clock Glitch Filtering Select
bits : 25 - 25 (1 bit)
access : write-only

P26 : Peripheral Clock Glitch Filtering Select
bits : 26 - 26 (1 bit)
access : write-only

P27 : Peripheral Clock Glitch Filtering Select
bits : 27 - 27 (1 bit)
access : write-only

P28 : Peripheral Clock Glitch Filtering Select
bits : 28 - 28 (1 bit)
access : write-only

P29 : Peripheral Clock Glitch Filtering Select
bits : 29 - 29 (1 bit)
access : write-only

P30 : Peripheral Clock Glitch Filtering Select
bits : 30 - 30 (1 bit)
access : write-only

P31 : Peripheral Clock Glitch Filtering Select
bits : 31 - 31 (1 bit)
access : write-only


PIO_IFSCER

Input Filter Slow Clock Enable Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_IFSCER PIO_IFSCER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Slow Clock Debouncing Filtering Select
bits : 0 - 0 (1 bit)

P1 : Slow Clock Debouncing Filtering Select
bits : 1 - 1 (1 bit)

P2 : Slow Clock Debouncing Filtering Select
bits : 2 - 2 (1 bit)

P3 : Slow Clock Debouncing Filtering Select
bits : 3 - 3 (1 bit)

P4 : Slow Clock Debouncing Filtering Select
bits : 4 - 4 (1 bit)

P5 : Slow Clock Debouncing Filtering Select
bits : 5 - 5 (1 bit)

P6 : Slow Clock Debouncing Filtering Select
bits : 6 - 6 (1 bit)

P7 : Slow Clock Debouncing Filtering Select
bits : 7 - 7 (1 bit)

P8 : Slow Clock Debouncing Filtering Select
bits : 8 - 8 (1 bit)

P9 : Slow Clock Debouncing Filtering Select
bits : 9 - 9 (1 bit)

P10 : Slow Clock Debouncing Filtering Select
bits : 10 - 10 (1 bit)

P11 : Slow Clock Debouncing Filtering Select
bits : 11 - 11 (1 bit)

P12 : Slow Clock Debouncing Filtering Select
bits : 12 - 12 (1 bit)

P13 : Slow Clock Debouncing Filtering Select
bits : 13 - 13 (1 bit)

P14 : Slow Clock Debouncing Filtering Select
bits : 14 - 14 (1 bit)

P15 : Slow Clock Debouncing Filtering Select
bits : 15 - 15 (1 bit)

P16 : Slow Clock Debouncing Filtering Select
bits : 16 - 16 (1 bit)

P17 : Slow Clock Debouncing Filtering Select
bits : 17 - 17 (1 bit)

P18 : Slow Clock Debouncing Filtering Select
bits : 18 - 18 (1 bit)

P19 : Slow Clock Debouncing Filtering Select
bits : 19 - 19 (1 bit)

P20 : Slow Clock Debouncing Filtering Select
bits : 20 - 20 (1 bit)

P21 : Slow Clock Debouncing Filtering Select
bits : 21 - 21 (1 bit)

P22 : Slow Clock Debouncing Filtering Select
bits : 22 - 22 (1 bit)

P23 : Slow Clock Debouncing Filtering Select
bits : 23 - 23 (1 bit)

P24 : Slow Clock Debouncing Filtering Select
bits : 24 - 24 (1 bit)

P25 : Slow Clock Debouncing Filtering Select
bits : 25 - 25 (1 bit)

P26 : Slow Clock Debouncing Filtering Select
bits : 26 - 26 (1 bit)

P27 : Slow Clock Debouncing Filtering Select
bits : 27 - 27 (1 bit)

P28 : Slow Clock Debouncing Filtering Select
bits : 28 - 28 (1 bit)

P29 : Slow Clock Debouncing Filtering Select
bits : 29 - 29 (1 bit)

P30 : Slow Clock Debouncing Filtering Select
bits : 30 - 30 (1 bit)

P31 : Slow Clock Debouncing Filtering Select
bits : 31 - 31 (1 bit)


IFSCER

Input Filter Slow Clock Enable Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFSCER IFSCER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Slow Clock Debouncing Filtering Select
bits : 0 - 0 (1 bit)
access : write-only

P1 : Slow Clock Debouncing Filtering Select
bits : 1 - 1 (1 bit)
access : write-only

P2 : Slow Clock Debouncing Filtering Select
bits : 2 - 2 (1 bit)
access : write-only

P3 : Slow Clock Debouncing Filtering Select
bits : 3 - 3 (1 bit)
access : write-only

P4 : Slow Clock Debouncing Filtering Select
bits : 4 - 4 (1 bit)
access : write-only

P5 : Slow Clock Debouncing Filtering Select
bits : 5 - 5 (1 bit)
access : write-only

P6 : Slow Clock Debouncing Filtering Select
bits : 6 - 6 (1 bit)
access : write-only

P7 : Slow Clock Debouncing Filtering Select
bits : 7 - 7 (1 bit)
access : write-only

P8 : Slow Clock Debouncing Filtering Select
bits : 8 - 8 (1 bit)
access : write-only

P9 : Slow Clock Debouncing Filtering Select
bits : 9 - 9 (1 bit)
access : write-only

P10 : Slow Clock Debouncing Filtering Select
bits : 10 - 10 (1 bit)
access : write-only

P11 : Slow Clock Debouncing Filtering Select
bits : 11 - 11 (1 bit)
access : write-only

P12 : Slow Clock Debouncing Filtering Select
bits : 12 - 12 (1 bit)
access : write-only

P13 : Slow Clock Debouncing Filtering Select
bits : 13 - 13 (1 bit)
access : write-only

P14 : Slow Clock Debouncing Filtering Select
bits : 14 - 14 (1 bit)
access : write-only

P15 : Slow Clock Debouncing Filtering Select
bits : 15 - 15 (1 bit)
access : write-only

P16 : Slow Clock Debouncing Filtering Select
bits : 16 - 16 (1 bit)
access : write-only

P17 : Slow Clock Debouncing Filtering Select
bits : 17 - 17 (1 bit)
access : write-only

P18 : Slow Clock Debouncing Filtering Select
bits : 18 - 18 (1 bit)
access : write-only

P19 : Slow Clock Debouncing Filtering Select
bits : 19 - 19 (1 bit)
access : write-only

P20 : Slow Clock Debouncing Filtering Select
bits : 20 - 20 (1 bit)
access : write-only

P21 : Slow Clock Debouncing Filtering Select
bits : 21 - 21 (1 bit)
access : write-only

P22 : Slow Clock Debouncing Filtering Select
bits : 22 - 22 (1 bit)
access : write-only

P23 : Slow Clock Debouncing Filtering Select
bits : 23 - 23 (1 bit)
access : write-only

P24 : Slow Clock Debouncing Filtering Select
bits : 24 - 24 (1 bit)
access : write-only

P25 : Slow Clock Debouncing Filtering Select
bits : 25 - 25 (1 bit)
access : write-only

P26 : Slow Clock Debouncing Filtering Select
bits : 26 - 26 (1 bit)
access : write-only

P27 : Slow Clock Debouncing Filtering Select
bits : 27 - 27 (1 bit)
access : write-only

P28 : Slow Clock Debouncing Filtering Select
bits : 28 - 28 (1 bit)
access : write-only

P29 : Slow Clock Debouncing Filtering Select
bits : 29 - 29 (1 bit)
access : write-only

P30 : Slow Clock Debouncing Filtering Select
bits : 30 - 30 (1 bit)
access : write-only

P31 : Slow Clock Debouncing Filtering Select
bits : 31 - 31 (1 bit)
access : write-only


PIO_IFSCSR

Input Filter Slow Clock Status Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_IFSCSR PIO_IFSCSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Glitch or Debouncing Filter Selection Status
bits : 0 - 0 (1 bit)

P1 : Glitch or Debouncing Filter Selection Status
bits : 1 - 1 (1 bit)

P2 : Glitch or Debouncing Filter Selection Status
bits : 2 - 2 (1 bit)

P3 : Glitch or Debouncing Filter Selection Status
bits : 3 - 3 (1 bit)

P4 : Glitch or Debouncing Filter Selection Status
bits : 4 - 4 (1 bit)

P5 : Glitch or Debouncing Filter Selection Status
bits : 5 - 5 (1 bit)

P6 : Glitch or Debouncing Filter Selection Status
bits : 6 - 6 (1 bit)

P7 : Glitch or Debouncing Filter Selection Status
bits : 7 - 7 (1 bit)

P8 : Glitch or Debouncing Filter Selection Status
bits : 8 - 8 (1 bit)

P9 : Glitch or Debouncing Filter Selection Status
bits : 9 - 9 (1 bit)

P10 : Glitch or Debouncing Filter Selection Status
bits : 10 - 10 (1 bit)

P11 : Glitch or Debouncing Filter Selection Status
bits : 11 - 11 (1 bit)

P12 : Glitch or Debouncing Filter Selection Status
bits : 12 - 12 (1 bit)

P13 : Glitch or Debouncing Filter Selection Status
bits : 13 - 13 (1 bit)

P14 : Glitch or Debouncing Filter Selection Status
bits : 14 - 14 (1 bit)

P15 : Glitch or Debouncing Filter Selection Status
bits : 15 - 15 (1 bit)

P16 : Glitch or Debouncing Filter Selection Status
bits : 16 - 16 (1 bit)

P17 : Glitch or Debouncing Filter Selection Status
bits : 17 - 17 (1 bit)

P18 : Glitch or Debouncing Filter Selection Status
bits : 18 - 18 (1 bit)

P19 : Glitch or Debouncing Filter Selection Status
bits : 19 - 19 (1 bit)

P20 : Glitch or Debouncing Filter Selection Status
bits : 20 - 20 (1 bit)

P21 : Glitch or Debouncing Filter Selection Status
bits : 21 - 21 (1 bit)

P22 : Glitch or Debouncing Filter Selection Status
bits : 22 - 22 (1 bit)

P23 : Glitch or Debouncing Filter Selection Status
bits : 23 - 23 (1 bit)

P24 : Glitch or Debouncing Filter Selection Status
bits : 24 - 24 (1 bit)

P25 : Glitch or Debouncing Filter Selection Status
bits : 25 - 25 (1 bit)

P26 : Glitch or Debouncing Filter Selection Status
bits : 26 - 26 (1 bit)

P27 : Glitch or Debouncing Filter Selection Status
bits : 27 - 27 (1 bit)

P28 : Glitch or Debouncing Filter Selection Status
bits : 28 - 28 (1 bit)

P29 : Glitch or Debouncing Filter Selection Status
bits : 29 - 29 (1 bit)

P30 : Glitch or Debouncing Filter Selection Status
bits : 30 - 30 (1 bit)

P31 : Glitch or Debouncing Filter Selection Status
bits : 31 - 31 (1 bit)


IFSCSR

Input Filter Slow Clock Status Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IFSCSR IFSCSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Glitch or Debouncing Filter Selection Status
bits : 0 - 0 (1 bit)
access : read-only

P1 : Glitch or Debouncing Filter Selection Status
bits : 1 - 1 (1 bit)
access : read-only

P2 : Glitch or Debouncing Filter Selection Status
bits : 2 - 2 (1 bit)
access : read-only

P3 : Glitch or Debouncing Filter Selection Status
bits : 3 - 3 (1 bit)
access : read-only

P4 : Glitch or Debouncing Filter Selection Status
bits : 4 - 4 (1 bit)
access : read-only

P5 : Glitch or Debouncing Filter Selection Status
bits : 5 - 5 (1 bit)
access : read-only

P6 : Glitch or Debouncing Filter Selection Status
bits : 6 - 6 (1 bit)
access : read-only

P7 : Glitch or Debouncing Filter Selection Status
bits : 7 - 7 (1 bit)
access : read-only

P8 : Glitch or Debouncing Filter Selection Status
bits : 8 - 8 (1 bit)
access : read-only

P9 : Glitch or Debouncing Filter Selection Status
bits : 9 - 9 (1 bit)
access : read-only

P10 : Glitch or Debouncing Filter Selection Status
bits : 10 - 10 (1 bit)
access : read-only

P11 : Glitch or Debouncing Filter Selection Status
bits : 11 - 11 (1 bit)
access : read-only

P12 : Glitch or Debouncing Filter Selection Status
bits : 12 - 12 (1 bit)
access : read-only

P13 : Glitch or Debouncing Filter Selection Status
bits : 13 - 13 (1 bit)
access : read-only

P14 : Glitch or Debouncing Filter Selection Status
bits : 14 - 14 (1 bit)
access : read-only

P15 : Glitch or Debouncing Filter Selection Status
bits : 15 - 15 (1 bit)
access : read-only

P16 : Glitch or Debouncing Filter Selection Status
bits : 16 - 16 (1 bit)
access : read-only

P17 : Glitch or Debouncing Filter Selection Status
bits : 17 - 17 (1 bit)
access : read-only

P18 : Glitch or Debouncing Filter Selection Status
bits : 18 - 18 (1 bit)
access : read-only

P19 : Glitch or Debouncing Filter Selection Status
bits : 19 - 19 (1 bit)
access : read-only

P20 : Glitch or Debouncing Filter Selection Status
bits : 20 - 20 (1 bit)
access : read-only

P21 : Glitch or Debouncing Filter Selection Status
bits : 21 - 21 (1 bit)
access : read-only

P22 : Glitch or Debouncing Filter Selection Status
bits : 22 - 22 (1 bit)
access : read-only

P23 : Glitch or Debouncing Filter Selection Status
bits : 23 - 23 (1 bit)
access : read-only

P24 : Glitch or Debouncing Filter Selection Status
bits : 24 - 24 (1 bit)
access : read-only

P25 : Glitch or Debouncing Filter Selection Status
bits : 25 - 25 (1 bit)
access : read-only

P26 : Glitch or Debouncing Filter Selection Status
bits : 26 - 26 (1 bit)
access : read-only

P27 : Glitch or Debouncing Filter Selection Status
bits : 27 - 27 (1 bit)
access : read-only

P28 : Glitch or Debouncing Filter Selection Status
bits : 28 - 28 (1 bit)
access : read-only

P29 : Glitch or Debouncing Filter Selection Status
bits : 29 - 29 (1 bit)
access : read-only

P30 : Glitch or Debouncing Filter Selection Status
bits : 30 - 30 (1 bit)
access : read-only

P31 : Glitch or Debouncing Filter Selection Status
bits : 31 - 31 (1 bit)
access : read-only


PIO_SCDR

Slow Clock Divider Debouncing Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO_SCDR PIO_SCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Slow Clock Divider Selection for Debouncing
bits : 0 - 13 (14 bit)


SCDR

Slow Clock Divider Debouncing Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCDR SCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Slow Clock Divider Selection for Debouncing
bits : 0 - 13 (14 bit)
access : read-write


PIO_PPDDR

Pad Pull-down Disable Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_PPDDR PIO_PPDDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Pull-Down Disable
bits : 0 - 0 (1 bit)

P1 : Pull-Down Disable
bits : 1 - 1 (1 bit)

P2 : Pull-Down Disable
bits : 2 - 2 (1 bit)

P3 : Pull-Down Disable
bits : 3 - 3 (1 bit)

P4 : Pull-Down Disable
bits : 4 - 4 (1 bit)

P5 : Pull-Down Disable
bits : 5 - 5 (1 bit)

P6 : Pull-Down Disable
bits : 6 - 6 (1 bit)

P7 : Pull-Down Disable
bits : 7 - 7 (1 bit)

P8 : Pull-Down Disable
bits : 8 - 8 (1 bit)

P9 : Pull-Down Disable
bits : 9 - 9 (1 bit)

P10 : Pull-Down Disable
bits : 10 - 10 (1 bit)

P11 : Pull-Down Disable
bits : 11 - 11 (1 bit)

P12 : Pull-Down Disable
bits : 12 - 12 (1 bit)

P13 : Pull-Down Disable
bits : 13 - 13 (1 bit)

P14 : Pull-Down Disable
bits : 14 - 14 (1 bit)

P15 : Pull-Down Disable
bits : 15 - 15 (1 bit)

P16 : Pull-Down Disable
bits : 16 - 16 (1 bit)

P17 : Pull-Down Disable
bits : 17 - 17 (1 bit)

P18 : Pull-Down Disable
bits : 18 - 18 (1 bit)

P19 : Pull-Down Disable
bits : 19 - 19 (1 bit)

P20 : Pull-Down Disable
bits : 20 - 20 (1 bit)

P21 : Pull-Down Disable
bits : 21 - 21 (1 bit)

P22 : Pull-Down Disable
bits : 22 - 22 (1 bit)

P23 : Pull-Down Disable
bits : 23 - 23 (1 bit)

P24 : Pull-Down Disable
bits : 24 - 24 (1 bit)

P25 : Pull-Down Disable
bits : 25 - 25 (1 bit)

P26 : Pull-Down Disable
bits : 26 - 26 (1 bit)

P27 : Pull-Down Disable
bits : 27 - 27 (1 bit)

P28 : Pull-Down Disable
bits : 28 - 28 (1 bit)

P29 : Pull-Down Disable
bits : 29 - 29 (1 bit)

P30 : Pull-Down Disable
bits : 30 - 30 (1 bit)

P31 : Pull-Down Disable
bits : 31 - 31 (1 bit)


PPDDR

Pad Pull-down Disable Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PPDDR PPDDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Pull-Down Disable
bits : 0 - 0 (1 bit)
access : write-only

P1 : Pull-Down Disable
bits : 1 - 1 (1 bit)
access : write-only

P2 : Pull-Down Disable
bits : 2 - 2 (1 bit)
access : write-only

P3 : Pull-Down Disable
bits : 3 - 3 (1 bit)
access : write-only

P4 : Pull-Down Disable
bits : 4 - 4 (1 bit)
access : write-only

P5 : Pull-Down Disable
bits : 5 - 5 (1 bit)
access : write-only

P6 : Pull-Down Disable
bits : 6 - 6 (1 bit)
access : write-only

P7 : Pull-Down Disable
bits : 7 - 7 (1 bit)
access : write-only

P8 : Pull-Down Disable
bits : 8 - 8 (1 bit)
access : write-only

P9 : Pull-Down Disable
bits : 9 - 9 (1 bit)
access : write-only

P10 : Pull-Down Disable
bits : 10 - 10 (1 bit)
access : write-only

P11 : Pull-Down Disable
bits : 11 - 11 (1 bit)
access : write-only

P12 : Pull-Down Disable
bits : 12 - 12 (1 bit)
access : write-only

P13 : Pull-Down Disable
bits : 13 - 13 (1 bit)
access : write-only

P14 : Pull-Down Disable
bits : 14 - 14 (1 bit)
access : write-only

P15 : Pull-Down Disable
bits : 15 - 15 (1 bit)
access : write-only

P16 : Pull-Down Disable
bits : 16 - 16 (1 bit)
access : write-only

P17 : Pull-Down Disable
bits : 17 - 17 (1 bit)
access : write-only

P18 : Pull-Down Disable
bits : 18 - 18 (1 bit)
access : write-only

P19 : Pull-Down Disable
bits : 19 - 19 (1 bit)
access : write-only

P20 : Pull-Down Disable
bits : 20 - 20 (1 bit)
access : write-only

P21 : Pull-Down Disable
bits : 21 - 21 (1 bit)
access : write-only

P22 : Pull-Down Disable
bits : 22 - 22 (1 bit)
access : write-only

P23 : Pull-Down Disable
bits : 23 - 23 (1 bit)
access : write-only

P24 : Pull-Down Disable
bits : 24 - 24 (1 bit)
access : write-only

P25 : Pull-Down Disable
bits : 25 - 25 (1 bit)
access : write-only

P26 : Pull-Down Disable
bits : 26 - 26 (1 bit)
access : write-only

P27 : Pull-Down Disable
bits : 27 - 27 (1 bit)
access : write-only

P28 : Pull-Down Disable
bits : 28 - 28 (1 bit)
access : write-only

P29 : Pull-Down Disable
bits : 29 - 29 (1 bit)
access : write-only

P30 : Pull-Down Disable
bits : 30 - 30 (1 bit)
access : write-only

P31 : Pull-Down Disable
bits : 31 - 31 (1 bit)
access : write-only


PIO_PPDER

Pad Pull-down Enable Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_PPDER PIO_PPDER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Pull-Down Enable
bits : 0 - 0 (1 bit)

P1 : Pull-Down Enable
bits : 1 - 1 (1 bit)

P2 : Pull-Down Enable
bits : 2 - 2 (1 bit)

P3 : Pull-Down Enable
bits : 3 - 3 (1 bit)

P4 : Pull-Down Enable
bits : 4 - 4 (1 bit)

P5 : Pull-Down Enable
bits : 5 - 5 (1 bit)

P6 : Pull-Down Enable
bits : 6 - 6 (1 bit)

P7 : Pull-Down Enable
bits : 7 - 7 (1 bit)

P8 : Pull-Down Enable
bits : 8 - 8 (1 bit)

P9 : Pull-Down Enable
bits : 9 - 9 (1 bit)

P10 : Pull-Down Enable
bits : 10 - 10 (1 bit)

P11 : Pull-Down Enable
bits : 11 - 11 (1 bit)

P12 : Pull-Down Enable
bits : 12 - 12 (1 bit)

P13 : Pull-Down Enable
bits : 13 - 13 (1 bit)

P14 : Pull-Down Enable
bits : 14 - 14 (1 bit)

P15 : Pull-Down Enable
bits : 15 - 15 (1 bit)

P16 : Pull-Down Enable
bits : 16 - 16 (1 bit)

P17 : Pull-Down Enable
bits : 17 - 17 (1 bit)

P18 : Pull-Down Enable
bits : 18 - 18 (1 bit)

P19 : Pull-Down Enable
bits : 19 - 19 (1 bit)

P20 : Pull-Down Enable
bits : 20 - 20 (1 bit)

P21 : Pull-Down Enable
bits : 21 - 21 (1 bit)

P22 : Pull-Down Enable
bits : 22 - 22 (1 bit)

P23 : Pull-Down Enable
bits : 23 - 23 (1 bit)

P24 : Pull-Down Enable
bits : 24 - 24 (1 bit)

P25 : Pull-Down Enable
bits : 25 - 25 (1 bit)

P26 : Pull-Down Enable
bits : 26 - 26 (1 bit)

P27 : Pull-Down Enable
bits : 27 - 27 (1 bit)

P28 : Pull-Down Enable
bits : 28 - 28 (1 bit)

P29 : Pull-Down Enable
bits : 29 - 29 (1 bit)

P30 : Pull-Down Enable
bits : 30 - 30 (1 bit)

P31 : Pull-Down Enable
bits : 31 - 31 (1 bit)


PPDER

Pad Pull-down Enable Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PPDER PPDER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Pull-Down Enable
bits : 0 - 0 (1 bit)
access : write-only

P1 : Pull-Down Enable
bits : 1 - 1 (1 bit)
access : write-only

P2 : Pull-Down Enable
bits : 2 - 2 (1 bit)
access : write-only

P3 : Pull-Down Enable
bits : 3 - 3 (1 bit)
access : write-only

P4 : Pull-Down Enable
bits : 4 - 4 (1 bit)
access : write-only

P5 : Pull-Down Enable
bits : 5 - 5 (1 bit)
access : write-only

P6 : Pull-Down Enable
bits : 6 - 6 (1 bit)
access : write-only

P7 : Pull-Down Enable
bits : 7 - 7 (1 bit)
access : write-only

P8 : Pull-Down Enable
bits : 8 - 8 (1 bit)
access : write-only

P9 : Pull-Down Enable
bits : 9 - 9 (1 bit)
access : write-only

P10 : Pull-Down Enable
bits : 10 - 10 (1 bit)
access : write-only

P11 : Pull-Down Enable
bits : 11 - 11 (1 bit)
access : write-only

P12 : Pull-Down Enable
bits : 12 - 12 (1 bit)
access : write-only

P13 : Pull-Down Enable
bits : 13 - 13 (1 bit)
access : write-only

P14 : Pull-Down Enable
bits : 14 - 14 (1 bit)
access : write-only

P15 : Pull-Down Enable
bits : 15 - 15 (1 bit)
access : write-only

P16 : Pull-Down Enable
bits : 16 - 16 (1 bit)
access : write-only

P17 : Pull-Down Enable
bits : 17 - 17 (1 bit)
access : write-only

P18 : Pull-Down Enable
bits : 18 - 18 (1 bit)
access : write-only

P19 : Pull-Down Enable
bits : 19 - 19 (1 bit)
access : write-only

P20 : Pull-Down Enable
bits : 20 - 20 (1 bit)
access : write-only

P21 : Pull-Down Enable
bits : 21 - 21 (1 bit)
access : write-only

P22 : Pull-Down Enable
bits : 22 - 22 (1 bit)
access : write-only

P23 : Pull-Down Enable
bits : 23 - 23 (1 bit)
access : write-only

P24 : Pull-Down Enable
bits : 24 - 24 (1 bit)
access : write-only

P25 : Pull-Down Enable
bits : 25 - 25 (1 bit)
access : write-only

P26 : Pull-Down Enable
bits : 26 - 26 (1 bit)
access : write-only

P27 : Pull-Down Enable
bits : 27 - 27 (1 bit)
access : write-only

P28 : Pull-Down Enable
bits : 28 - 28 (1 bit)
access : write-only

P29 : Pull-Down Enable
bits : 29 - 29 (1 bit)
access : write-only

P30 : Pull-Down Enable
bits : 30 - 30 (1 bit)
access : write-only

P31 : Pull-Down Enable
bits : 31 - 31 (1 bit)
access : write-only


PIO_PPDSR

Pad Pull-down Status Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_PPDSR PIO_PPDSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Pull-Down Status
bits : 0 - 0 (1 bit)

P1 : Pull-Down Status
bits : 1 - 1 (1 bit)

P2 : Pull-Down Status
bits : 2 - 2 (1 bit)

P3 : Pull-Down Status
bits : 3 - 3 (1 bit)

P4 : Pull-Down Status
bits : 4 - 4 (1 bit)

P5 : Pull-Down Status
bits : 5 - 5 (1 bit)

P6 : Pull-Down Status
bits : 6 - 6 (1 bit)

P7 : Pull-Down Status
bits : 7 - 7 (1 bit)

P8 : Pull-Down Status
bits : 8 - 8 (1 bit)

P9 : Pull-Down Status
bits : 9 - 9 (1 bit)

P10 : Pull-Down Status
bits : 10 - 10 (1 bit)

P11 : Pull-Down Status
bits : 11 - 11 (1 bit)

P12 : Pull-Down Status
bits : 12 - 12 (1 bit)

P13 : Pull-Down Status
bits : 13 - 13 (1 bit)

P14 : Pull-Down Status
bits : 14 - 14 (1 bit)

P15 : Pull-Down Status
bits : 15 - 15 (1 bit)

P16 : Pull-Down Status
bits : 16 - 16 (1 bit)

P17 : Pull-Down Status
bits : 17 - 17 (1 bit)

P18 : Pull-Down Status
bits : 18 - 18 (1 bit)

P19 : Pull-Down Status
bits : 19 - 19 (1 bit)

P20 : Pull-Down Status
bits : 20 - 20 (1 bit)

P21 : Pull-Down Status
bits : 21 - 21 (1 bit)

P22 : Pull-Down Status
bits : 22 - 22 (1 bit)

P23 : Pull-Down Status
bits : 23 - 23 (1 bit)

P24 : Pull-Down Status
bits : 24 - 24 (1 bit)

P25 : Pull-Down Status
bits : 25 - 25 (1 bit)

P26 : Pull-Down Status
bits : 26 - 26 (1 bit)

P27 : Pull-Down Status
bits : 27 - 27 (1 bit)

P28 : Pull-Down Status
bits : 28 - 28 (1 bit)

P29 : Pull-Down Status
bits : 29 - 29 (1 bit)

P30 : Pull-Down Status
bits : 30 - 30 (1 bit)

P31 : Pull-Down Status
bits : 31 - 31 (1 bit)


PPDSR

Pad Pull-down Status Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PPDSR PPDSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Pull-Down Status
bits : 0 - 0 (1 bit)
access : read-only

P1 : Pull-Down Status
bits : 1 - 1 (1 bit)
access : read-only

P2 : Pull-Down Status
bits : 2 - 2 (1 bit)
access : read-only

P3 : Pull-Down Status
bits : 3 - 3 (1 bit)
access : read-only

P4 : Pull-Down Status
bits : 4 - 4 (1 bit)
access : read-only

P5 : Pull-Down Status
bits : 5 - 5 (1 bit)
access : read-only

P6 : Pull-Down Status
bits : 6 - 6 (1 bit)
access : read-only

P7 : Pull-Down Status
bits : 7 - 7 (1 bit)
access : read-only

P8 : Pull-Down Status
bits : 8 - 8 (1 bit)
access : read-only

P9 : Pull-Down Status
bits : 9 - 9 (1 bit)
access : read-only

P10 : Pull-Down Status
bits : 10 - 10 (1 bit)
access : read-only

P11 : Pull-Down Status
bits : 11 - 11 (1 bit)
access : read-only

P12 : Pull-Down Status
bits : 12 - 12 (1 bit)
access : read-only

P13 : Pull-Down Status
bits : 13 - 13 (1 bit)
access : read-only

P14 : Pull-Down Status
bits : 14 - 14 (1 bit)
access : read-only

P15 : Pull-Down Status
bits : 15 - 15 (1 bit)
access : read-only

P16 : Pull-Down Status
bits : 16 - 16 (1 bit)
access : read-only

P17 : Pull-Down Status
bits : 17 - 17 (1 bit)
access : read-only

P18 : Pull-Down Status
bits : 18 - 18 (1 bit)
access : read-only

P19 : Pull-Down Status
bits : 19 - 19 (1 bit)
access : read-only

P20 : Pull-Down Status
bits : 20 - 20 (1 bit)
access : read-only

P21 : Pull-Down Status
bits : 21 - 21 (1 bit)
access : read-only

P22 : Pull-Down Status
bits : 22 - 22 (1 bit)
access : read-only

P23 : Pull-Down Status
bits : 23 - 23 (1 bit)
access : read-only

P24 : Pull-Down Status
bits : 24 - 24 (1 bit)
access : read-only

P25 : Pull-Down Status
bits : 25 - 25 (1 bit)
access : read-only

P26 : Pull-Down Status
bits : 26 - 26 (1 bit)
access : read-only

P27 : Pull-Down Status
bits : 27 - 27 (1 bit)
access : read-only

P28 : Pull-Down Status
bits : 28 - 28 (1 bit)
access : read-only

P29 : Pull-Down Status
bits : 29 - 29 (1 bit)
access : read-only

P30 : Pull-Down Status
bits : 30 - 30 (1 bit)
access : read-only

P31 : Pull-Down Status
bits : 31 - 31 (1 bit)
access : read-only


PIO_OWER

Output Write Enable
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_OWER PIO_OWER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Output Write Enable
bits : 0 - 0 (1 bit)

P1 : Output Write Enable
bits : 1 - 1 (1 bit)

P2 : Output Write Enable
bits : 2 - 2 (1 bit)

P3 : Output Write Enable
bits : 3 - 3 (1 bit)

P4 : Output Write Enable
bits : 4 - 4 (1 bit)

P5 : Output Write Enable
bits : 5 - 5 (1 bit)

P6 : Output Write Enable
bits : 6 - 6 (1 bit)

P7 : Output Write Enable
bits : 7 - 7 (1 bit)

P8 : Output Write Enable
bits : 8 - 8 (1 bit)

P9 : Output Write Enable
bits : 9 - 9 (1 bit)

P10 : Output Write Enable
bits : 10 - 10 (1 bit)

P11 : Output Write Enable
bits : 11 - 11 (1 bit)

P12 : Output Write Enable
bits : 12 - 12 (1 bit)

P13 : Output Write Enable
bits : 13 - 13 (1 bit)

P14 : Output Write Enable
bits : 14 - 14 (1 bit)

P15 : Output Write Enable
bits : 15 - 15 (1 bit)

P16 : Output Write Enable
bits : 16 - 16 (1 bit)

P17 : Output Write Enable
bits : 17 - 17 (1 bit)

P18 : Output Write Enable
bits : 18 - 18 (1 bit)

P19 : Output Write Enable
bits : 19 - 19 (1 bit)

P20 : Output Write Enable
bits : 20 - 20 (1 bit)

P21 : Output Write Enable
bits : 21 - 21 (1 bit)

P22 : Output Write Enable
bits : 22 - 22 (1 bit)

P23 : Output Write Enable
bits : 23 - 23 (1 bit)

P24 : Output Write Enable
bits : 24 - 24 (1 bit)

P25 : Output Write Enable
bits : 25 - 25 (1 bit)

P26 : Output Write Enable
bits : 26 - 26 (1 bit)

P27 : Output Write Enable
bits : 27 - 27 (1 bit)

P28 : Output Write Enable
bits : 28 - 28 (1 bit)

P29 : Output Write Enable
bits : 29 - 29 (1 bit)

P30 : Output Write Enable
bits : 30 - 30 (1 bit)

P31 : Output Write Enable
bits : 31 - 31 (1 bit)


OWER

Output Write Enable
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OWER OWER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Output Write Enable
bits : 0 - 0 (1 bit)
access : write-only

P1 : Output Write Enable
bits : 1 - 1 (1 bit)
access : write-only

P2 : Output Write Enable
bits : 2 - 2 (1 bit)
access : write-only

P3 : Output Write Enable
bits : 3 - 3 (1 bit)
access : write-only

P4 : Output Write Enable
bits : 4 - 4 (1 bit)
access : write-only

P5 : Output Write Enable
bits : 5 - 5 (1 bit)
access : write-only

P6 : Output Write Enable
bits : 6 - 6 (1 bit)
access : write-only

P7 : Output Write Enable
bits : 7 - 7 (1 bit)
access : write-only

P8 : Output Write Enable
bits : 8 - 8 (1 bit)
access : write-only

P9 : Output Write Enable
bits : 9 - 9 (1 bit)
access : write-only

P10 : Output Write Enable
bits : 10 - 10 (1 bit)
access : write-only

P11 : Output Write Enable
bits : 11 - 11 (1 bit)
access : write-only

P12 : Output Write Enable
bits : 12 - 12 (1 bit)
access : write-only

P13 : Output Write Enable
bits : 13 - 13 (1 bit)
access : write-only

P14 : Output Write Enable
bits : 14 - 14 (1 bit)
access : write-only

P15 : Output Write Enable
bits : 15 - 15 (1 bit)
access : write-only

P16 : Output Write Enable
bits : 16 - 16 (1 bit)
access : write-only

P17 : Output Write Enable
bits : 17 - 17 (1 bit)
access : write-only

P18 : Output Write Enable
bits : 18 - 18 (1 bit)
access : write-only

P19 : Output Write Enable
bits : 19 - 19 (1 bit)
access : write-only

P20 : Output Write Enable
bits : 20 - 20 (1 bit)
access : write-only

P21 : Output Write Enable
bits : 21 - 21 (1 bit)
access : write-only

P22 : Output Write Enable
bits : 22 - 22 (1 bit)
access : write-only

P23 : Output Write Enable
bits : 23 - 23 (1 bit)
access : write-only

P24 : Output Write Enable
bits : 24 - 24 (1 bit)
access : write-only

P25 : Output Write Enable
bits : 25 - 25 (1 bit)
access : write-only

P26 : Output Write Enable
bits : 26 - 26 (1 bit)
access : write-only

P27 : Output Write Enable
bits : 27 - 27 (1 bit)
access : write-only

P28 : Output Write Enable
bits : 28 - 28 (1 bit)
access : write-only

P29 : Output Write Enable
bits : 29 - 29 (1 bit)
access : write-only

P30 : Output Write Enable
bits : 30 - 30 (1 bit)
access : write-only

P31 : Output Write Enable
bits : 31 - 31 (1 bit)
access : write-only


PIO_OWDR

Output Write Disable
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_OWDR PIO_OWDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Output Write Disable
bits : 0 - 0 (1 bit)

P1 : Output Write Disable
bits : 1 - 1 (1 bit)

P2 : Output Write Disable
bits : 2 - 2 (1 bit)

P3 : Output Write Disable
bits : 3 - 3 (1 bit)

P4 : Output Write Disable
bits : 4 - 4 (1 bit)

P5 : Output Write Disable
bits : 5 - 5 (1 bit)

P6 : Output Write Disable
bits : 6 - 6 (1 bit)

P7 : Output Write Disable
bits : 7 - 7 (1 bit)

P8 : Output Write Disable
bits : 8 - 8 (1 bit)

P9 : Output Write Disable
bits : 9 - 9 (1 bit)

P10 : Output Write Disable
bits : 10 - 10 (1 bit)

P11 : Output Write Disable
bits : 11 - 11 (1 bit)

P12 : Output Write Disable
bits : 12 - 12 (1 bit)

P13 : Output Write Disable
bits : 13 - 13 (1 bit)

P14 : Output Write Disable
bits : 14 - 14 (1 bit)

P15 : Output Write Disable
bits : 15 - 15 (1 bit)

P16 : Output Write Disable
bits : 16 - 16 (1 bit)

P17 : Output Write Disable
bits : 17 - 17 (1 bit)

P18 : Output Write Disable
bits : 18 - 18 (1 bit)

P19 : Output Write Disable
bits : 19 - 19 (1 bit)

P20 : Output Write Disable
bits : 20 - 20 (1 bit)

P21 : Output Write Disable
bits : 21 - 21 (1 bit)

P22 : Output Write Disable
bits : 22 - 22 (1 bit)

P23 : Output Write Disable
bits : 23 - 23 (1 bit)

P24 : Output Write Disable
bits : 24 - 24 (1 bit)

P25 : Output Write Disable
bits : 25 - 25 (1 bit)

P26 : Output Write Disable
bits : 26 - 26 (1 bit)

P27 : Output Write Disable
bits : 27 - 27 (1 bit)

P28 : Output Write Disable
bits : 28 - 28 (1 bit)

P29 : Output Write Disable
bits : 29 - 29 (1 bit)

P30 : Output Write Disable
bits : 30 - 30 (1 bit)

P31 : Output Write Disable
bits : 31 - 31 (1 bit)


OWDR

Output Write Disable
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OWDR OWDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Output Write Disable
bits : 0 - 0 (1 bit)
access : write-only

P1 : Output Write Disable
bits : 1 - 1 (1 bit)
access : write-only

P2 : Output Write Disable
bits : 2 - 2 (1 bit)
access : write-only

P3 : Output Write Disable
bits : 3 - 3 (1 bit)
access : write-only

P4 : Output Write Disable
bits : 4 - 4 (1 bit)
access : write-only

P5 : Output Write Disable
bits : 5 - 5 (1 bit)
access : write-only

P6 : Output Write Disable
bits : 6 - 6 (1 bit)
access : write-only

P7 : Output Write Disable
bits : 7 - 7 (1 bit)
access : write-only

P8 : Output Write Disable
bits : 8 - 8 (1 bit)
access : write-only

P9 : Output Write Disable
bits : 9 - 9 (1 bit)
access : write-only

P10 : Output Write Disable
bits : 10 - 10 (1 bit)
access : write-only

P11 : Output Write Disable
bits : 11 - 11 (1 bit)
access : write-only

P12 : Output Write Disable
bits : 12 - 12 (1 bit)
access : write-only

P13 : Output Write Disable
bits : 13 - 13 (1 bit)
access : write-only

P14 : Output Write Disable
bits : 14 - 14 (1 bit)
access : write-only

P15 : Output Write Disable
bits : 15 - 15 (1 bit)
access : write-only

P16 : Output Write Disable
bits : 16 - 16 (1 bit)
access : write-only

P17 : Output Write Disable
bits : 17 - 17 (1 bit)
access : write-only

P18 : Output Write Disable
bits : 18 - 18 (1 bit)
access : write-only

P19 : Output Write Disable
bits : 19 - 19 (1 bit)
access : write-only

P20 : Output Write Disable
bits : 20 - 20 (1 bit)
access : write-only

P21 : Output Write Disable
bits : 21 - 21 (1 bit)
access : write-only

P22 : Output Write Disable
bits : 22 - 22 (1 bit)
access : write-only

P23 : Output Write Disable
bits : 23 - 23 (1 bit)
access : write-only

P24 : Output Write Disable
bits : 24 - 24 (1 bit)
access : write-only

P25 : Output Write Disable
bits : 25 - 25 (1 bit)
access : write-only

P26 : Output Write Disable
bits : 26 - 26 (1 bit)
access : write-only

P27 : Output Write Disable
bits : 27 - 27 (1 bit)
access : write-only

P28 : Output Write Disable
bits : 28 - 28 (1 bit)
access : write-only

P29 : Output Write Disable
bits : 29 - 29 (1 bit)
access : write-only

P30 : Output Write Disable
bits : 30 - 30 (1 bit)
access : write-only

P31 : Output Write Disable
bits : 31 - 31 (1 bit)
access : write-only


PIO_OWSR

Output Write Status Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_OWSR PIO_OWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Output Write Status
bits : 0 - 0 (1 bit)

P1 : Output Write Status
bits : 1 - 1 (1 bit)

P2 : Output Write Status
bits : 2 - 2 (1 bit)

P3 : Output Write Status
bits : 3 - 3 (1 bit)

P4 : Output Write Status
bits : 4 - 4 (1 bit)

P5 : Output Write Status
bits : 5 - 5 (1 bit)

P6 : Output Write Status
bits : 6 - 6 (1 bit)

P7 : Output Write Status
bits : 7 - 7 (1 bit)

P8 : Output Write Status
bits : 8 - 8 (1 bit)

P9 : Output Write Status
bits : 9 - 9 (1 bit)

P10 : Output Write Status
bits : 10 - 10 (1 bit)

P11 : Output Write Status
bits : 11 - 11 (1 bit)

P12 : Output Write Status
bits : 12 - 12 (1 bit)

P13 : Output Write Status
bits : 13 - 13 (1 bit)

P14 : Output Write Status
bits : 14 - 14 (1 bit)

P15 : Output Write Status
bits : 15 - 15 (1 bit)

P16 : Output Write Status
bits : 16 - 16 (1 bit)

P17 : Output Write Status
bits : 17 - 17 (1 bit)

P18 : Output Write Status
bits : 18 - 18 (1 bit)

P19 : Output Write Status
bits : 19 - 19 (1 bit)

P20 : Output Write Status
bits : 20 - 20 (1 bit)

P21 : Output Write Status
bits : 21 - 21 (1 bit)

P22 : Output Write Status
bits : 22 - 22 (1 bit)

P23 : Output Write Status
bits : 23 - 23 (1 bit)

P24 : Output Write Status
bits : 24 - 24 (1 bit)

P25 : Output Write Status
bits : 25 - 25 (1 bit)

P26 : Output Write Status
bits : 26 - 26 (1 bit)

P27 : Output Write Status
bits : 27 - 27 (1 bit)

P28 : Output Write Status
bits : 28 - 28 (1 bit)

P29 : Output Write Status
bits : 29 - 29 (1 bit)

P30 : Output Write Status
bits : 30 - 30 (1 bit)

P31 : Output Write Status
bits : 31 - 31 (1 bit)


OWSR

Output Write Status Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OWSR OWSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Output Write Status
bits : 0 - 0 (1 bit)
access : read-only

P1 : Output Write Status
bits : 1 - 1 (1 bit)
access : read-only

P2 : Output Write Status
bits : 2 - 2 (1 bit)
access : read-only

P3 : Output Write Status
bits : 3 - 3 (1 bit)
access : read-only

P4 : Output Write Status
bits : 4 - 4 (1 bit)
access : read-only

P5 : Output Write Status
bits : 5 - 5 (1 bit)
access : read-only

P6 : Output Write Status
bits : 6 - 6 (1 bit)
access : read-only

P7 : Output Write Status
bits : 7 - 7 (1 bit)
access : read-only

P8 : Output Write Status
bits : 8 - 8 (1 bit)
access : read-only

P9 : Output Write Status
bits : 9 - 9 (1 bit)
access : read-only

P10 : Output Write Status
bits : 10 - 10 (1 bit)
access : read-only

P11 : Output Write Status
bits : 11 - 11 (1 bit)
access : read-only

P12 : Output Write Status
bits : 12 - 12 (1 bit)
access : read-only

P13 : Output Write Status
bits : 13 - 13 (1 bit)
access : read-only

P14 : Output Write Status
bits : 14 - 14 (1 bit)
access : read-only

P15 : Output Write Status
bits : 15 - 15 (1 bit)
access : read-only

P16 : Output Write Status
bits : 16 - 16 (1 bit)
access : read-only

P17 : Output Write Status
bits : 17 - 17 (1 bit)
access : read-only

P18 : Output Write Status
bits : 18 - 18 (1 bit)
access : read-only

P19 : Output Write Status
bits : 19 - 19 (1 bit)
access : read-only

P20 : Output Write Status
bits : 20 - 20 (1 bit)
access : read-only

P21 : Output Write Status
bits : 21 - 21 (1 bit)
access : read-only

P22 : Output Write Status
bits : 22 - 22 (1 bit)
access : read-only

P23 : Output Write Status
bits : 23 - 23 (1 bit)
access : read-only

P24 : Output Write Status
bits : 24 - 24 (1 bit)
access : read-only

P25 : Output Write Status
bits : 25 - 25 (1 bit)
access : read-only

P26 : Output Write Status
bits : 26 - 26 (1 bit)
access : read-only

P27 : Output Write Status
bits : 27 - 27 (1 bit)
access : read-only

P28 : Output Write Status
bits : 28 - 28 (1 bit)
access : read-only

P29 : Output Write Status
bits : 29 - 29 (1 bit)
access : read-only

P30 : Output Write Status
bits : 30 - 30 (1 bit)
access : read-only

P31 : Output Write Status
bits : 31 - 31 (1 bit)
access : read-only


PIO_AIMER

Additional Interrupt Modes Enable Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_AIMER PIO_AIMER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Additional Interrupt Modes Enable
bits : 0 - 0 (1 bit)

P1 : Additional Interrupt Modes Enable
bits : 1 - 1 (1 bit)

P2 : Additional Interrupt Modes Enable
bits : 2 - 2 (1 bit)

P3 : Additional Interrupt Modes Enable
bits : 3 - 3 (1 bit)

P4 : Additional Interrupt Modes Enable
bits : 4 - 4 (1 bit)

P5 : Additional Interrupt Modes Enable
bits : 5 - 5 (1 bit)

P6 : Additional Interrupt Modes Enable
bits : 6 - 6 (1 bit)

P7 : Additional Interrupt Modes Enable
bits : 7 - 7 (1 bit)

P8 : Additional Interrupt Modes Enable
bits : 8 - 8 (1 bit)

P9 : Additional Interrupt Modes Enable
bits : 9 - 9 (1 bit)

P10 : Additional Interrupt Modes Enable
bits : 10 - 10 (1 bit)

P11 : Additional Interrupt Modes Enable
bits : 11 - 11 (1 bit)

P12 : Additional Interrupt Modes Enable
bits : 12 - 12 (1 bit)

P13 : Additional Interrupt Modes Enable
bits : 13 - 13 (1 bit)

P14 : Additional Interrupt Modes Enable
bits : 14 - 14 (1 bit)

P15 : Additional Interrupt Modes Enable
bits : 15 - 15 (1 bit)

P16 : Additional Interrupt Modes Enable
bits : 16 - 16 (1 bit)

P17 : Additional Interrupt Modes Enable
bits : 17 - 17 (1 bit)

P18 : Additional Interrupt Modes Enable
bits : 18 - 18 (1 bit)

P19 : Additional Interrupt Modes Enable
bits : 19 - 19 (1 bit)

P20 : Additional Interrupt Modes Enable
bits : 20 - 20 (1 bit)

P21 : Additional Interrupt Modes Enable
bits : 21 - 21 (1 bit)

P22 : Additional Interrupt Modes Enable
bits : 22 - 22 (1 bit)

P23 : Additional Interrupt Modes Enable
bits : 23 - 23 (1 bit)

P24 : Additional Interrupt Modes Enable
bits : 24 - 24 (1 bit)

P25 : Additional Interrupt Modes Enable
bits : 25 - 25 (1 bit)

P26 : Additional Interrupt Modes Enable
bits : 26 - 26 (1 bit)

P27 : Additional Interrupt Modes Enable
bits : 27 - 27 (1 bit)

P28 : Additional Interrupt Modes Enable
bits : 28 - 28 (1 bit)

P29 : Additional Interrupt Modes Enable
bits : 29 - 29 (1 bit)

P30 : Additional Interrupt Modes Enable
bits : 30 - 30 (1 bit)

P31 : Additional Interrupt Modes Enable
bits : 31 - 31 (1 bit)


AIMER

Additional Interrupt Modes Enable Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AIMER AIMER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Additional Interrupt Modes Enable
bits : 0 - 0 (1 bit)
access : write-only

P1 : Additional Interrupt Modes Enable
bits : 1 - 1 (1 bit)
access : write-only

P2 : Additional Interrupt Modes Enable
bits : 2 - 2 (1 bit)
access : write-only

P3 : Additional Interrupt Modes Enable
bits : 3 - 3 (1 bit)
access : write-only

P4 : Additional Interrupt Modes Enable
bits : 4 - 4 (1 bit)
access : write-only

P5 : Additional Interrupt Modes Enable
bits : 5 - 5 (1 bit)
access : write-only

P6 : Additional Interrupt Modes Enable
bits : 6 - 6 (1 bit)
access : write-only

P7 : Additional Interrupt Modes Enable
bits : 7 - 7 (1 bit)
access : write-only

P8 : Additional Interrupt Modes Enable
bits : 8 - 8 (1 bit)
access : write-only

P9 : Additional Interrupt Modes Enable
bits : 9 - 9 (1 bit)
access : write-only

P10 : Additional Interrupt Modes Enable
bits : 10 - 10 (1 bit)
access : write-only

P11 : Additional Interrupt Modes Enable
bits : 11 - 11 (1 bit)
access : write-only

P12 : Additional Interrupt Modes Enable
bits : 12 - 12 (1 bit)
access : write-only

P13 : Additional Interrupt Modes Enable
bits : 13 - 13 (1 bit)
access : write-only

P14 : Additional Interrupt Modes Enable
bits : 14 - 14 (1 bit)
access : write-only

P15 : Additional Interrupt Modes Enable
bits : 15 - 15 (1 bit)
access : write-only

P16 : Additional Interrupt Modes Enable
bits : 16 - 16 (1 bit)
access : write-only

P17 : Additional Interrupt Modes Enable
bits : 17 - 17 (1 bit)
access : write-only

P18 : Additional Interrupt Modes Enable
bits : 18 - 18 (1 bit)
access : write-only

P19 : Additional Interrupt Modes Enable
bits : 19 - 19 (1 bit)
access : write-only

P20 : Additional Interrupt Modes Enable
bits : 20 - 20 (1 bit)
access : write-only

P21 : Additional Interrupt Modes Enable
bits : 21 - 21 (1 bit)
access : write-only

P22 : Additional Interrupt Modes Enable
bits : 22 - 22 (1 bit)
access : write-only

P23 : Additional Interrupt Modes Enable
bits : 23 - 23 (1 bit)
access : write-only

P24 : Additional Interrupt Modes Enable
bits : 24 - 24 (1 bit)
access : write-only

P25 : Additional Interrupt Modes Enable
bits : 25 - 25 (1 bit)
access : write-only

P26 : Additional Interrupt Modes Enable
bits : 26 - 26 (1 bit)
access : write-only

P27 : Additional Interrupt Modes Enable
bits : 27 - 27 (1 bit)
access : write-only

P28 : Additional Interrupt Modes Enable
bits : 28 - 28 (1 bit)
access : write-only

P29 : Additional Interrupt Modes Enable
bits : 29 - 29 (1 bit)
access : write-only

P30 : Additional Interrupt Modes Enable
bits : 30 - 30 (1 bit)
access : write-only

P31 : Additional Interrupt Modes Enable
bits : 31 - 31 (1 bit)
access : write-only


PIO_AIMDR

Additional Interrupt Modes Disable Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_AIMDR PIO_AIMDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Additional Interrupt Modes Disable
bits : 0 - 0 (1 bit)

P1 : Additional Interrupt Modes Disable
bits : 1 - 1 (1 bit)

P2 : Additional Interrupt Modes Disable
bits : 2 - 2 (1 bit)

P3 : Additional Interrupt Modes Disable
bits : 3 - 3 (1 bit)

P4 : Additional Interrupt Modes Disable
bits : 4 - 4 (1 bit)

P5 : Additional Interrupt Modes Disable
bits : 5 - 5 (1 bit)

P6 : Additional Interrupt Modes Disable
bits : 6 - 6 (1 bit)

P7 : Additional Interrupt Modes Disable
bits : 7 - 7 (1 bit)

P8 : Additional Interrupt Modes Disable
bits : 8 - 8 (1 bit)

P9 : Additional Interrupt Modes Disable
bits : 9 - 9 (1 bit)

P10 : Additional Interrupt Modes Disable
bits : 10 - 10 (1 bit)

P11 : Additional Interrupt Modes Disable
bits : 11 - 11 (1 bit)

P12 : Additional Interrupt Modes Disable
bits : 12 - 12 (1 bit)

P13 : Additional Interrupt Modes Disable
bits : 13 - 13 (1 bit)

P14 : Additional Interrupt Modes Disable
bits : 14 - 14 (1 bit)

P15 : Additional Interrupt Modes Disable
bits : 15 - 15 (1 bit)

P16 : Additional Interrupt Modes Disable
bits : 16 - 16 (1 bit)

P17 : Additional Interrupt Modes Disable
bits : 17 - 17 (1 bit)

P18 : Additional Interrupt Modes Disable
bits : 18 - 18 (1 bit)

P19 : Additional Interrupt Modes Disable
bits : 19 - 19 (1 bit)

P20 : Additional Interrupt Modes Disable
bits : 20 - 20 (1 bit)

P21 : Additional Interrupt Modes Disable
bits : 21 - 21 (1 bit)

P22 : Additional Interrupt Modes Disable
bits : 22 - 22 (1 bit)

P23 : Additional Interrupt Modes Disable
bits : 23 - 23 (1 bit)

P24 : Additional Interrupt Modes Disable
bits : 24 - 24 (1 bit)

P25 : Additional Interrupt Modes Disable
bits : 25 - 25 (1 bit)

P26 : Additional Interrupt Modes Disable
bits : 26 - 26 (1 bit)

P27 : Additional Interrupt Modes Disable
bits : 27 - 27 (1 bit)

P28 : Additional Interrupt Modes Disable
bits : 28 - 28 (1 bit)

P29 : Additional Interrupt Modes Disable
bits : 29 - 29 (1 bit)

P30 : Additional Interrupt Modes Disable
bits : 30 - 30 (1 bit)

P31 : Additional Interrupt Modes Disable
bits : 31 - 31 (1 bit)


AIMDR

Additional Interrupt Modes Disable Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AIMDR AIMDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Additional Interrupt Modes Disable
bits : 0 - 0 (1 bit)
access : write-only

P1 : Additional Interrupt Modes Disable
bits : 1 - 1 (1 bit)
access : write-only

P2 : Additional Interrupt Modes Disable
bits : 2 - 2 (1 bit)
access : write-only

P3 : Additional Interrupt Modes Disable
bits : 3 - 3 (1 bit)
access : write-only

P4 : Additional Interrupt Modes Disable
bits : 4 - 4 (1 bit)
access : write-only

P5 : Additional Interrupt Modes Disable
bits : 5 - 5 (1 bit)
access : write-only

P6 : Additional Interrupt Modes Disable
bits : 6 - 6 (1 bit)
access : write-only

P7 : Additional Interrupt Modes Disable
bits : 7 - 7 (1 bit)
access : write-only

P8 : Additional Interrupt Modes Disable
bits : 8 - 8 (1 bit)
access : write-only

P9 : Additional Interrupt Modes Disable
bits : 9 - 9 (1 bit)
access : write-only

P10 : Additional Interrupt Modes Disable
bits : 10 - 10 (1 bit)
access : write-only

P11 : Additional Interrupt Modes Disable
bits : 11 - 11 (1 bit)
access : write-only

P12 : Additional Interrupt Modes Disable
bits : 12 - 12 (1 bit)
access : write-only

P13 : Additional Interrupt Modes Disable
bits : 13 - 13 (1 bit)
access : write-only

P14 : Additional Interrupt Modes Disable
bits : 14 - 14 (1 bit)
access : write-only

P15 : Additional Interrupt Modes Disable
bits : 15 - 15 (1 bit)
access : write-only

P16 : Additional Interrupt Modes Disable
bits : 16 - 16 (1 bit)
access : write-only

P17 : Additional Interrupt Modes Disable
bits : 17 - 17 (1 bit)
access : write-only

P18 : Additional Interrupt Modes Disable
bits : 18 - 18 (1 bit)
access : write-only

P19 : Additional Interrupt Modes Disable
bits : 19 - 19 (1 bit)
access : write-only

P20 : Additional Interrupt Modes Disable
bits : 20 - 20 (1 bit)
access : write-only

P21 : Additional Interrupt Modes Disable
bits : 21 - 21 (1 bit)
access : write-only

P22 : Additional Interrupt Modes Disable
bits : 22 - 22 (1 bit)
access : write-only

P23 : Additional Interrupt Modes Disable
bits : 23 - 23 (1 bit)
access : write-only

P24 : Additional Interrupt Modes Disable
bits : 24 - 24 (1 bit)
access : write-only

P25 : Additional Interrupt Modes Disable
bits : 25 - 25 (1 bit)
access : write-only

P26 : Additional Interrupt Modes Disable
bits : 26 - 26 (1 bit)
access : write-only

P27 : Additional Interrupt Modes Disable
bits : 27 - 27 (1 bit)
access : write-only

P28 : Additional Interrupt Modes Disable
bits : 28 - 28 (1 bit)
access : write-only

P29 : Additional Interrupt Modes Disable
bits : 29 - 29 (1 bit)
access : write-only

P30 : Additional Interrupt Modes Disable
bits : 30 - 30 (1 bit)
access : write-only

P31 : Additional Interrupt Modes Disable
bits : 31 - 31 (1 bit)
access : write-only


PIO_AIMMR

Additional Interrupt Modes Mask Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_AIMMR PIO_AIMMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : IO Line Index
bits : 0 - 0 (1 bit)

P1 : IO Line Index
bits : 1 - 1 (1 bit)

P2 : IO Line Index
bits : 2 - 2 (1 bit)

P3 : IO Line Index
bits : 3 - 3 (1 bit)

P4 : IO Line Index
bits : 4 - 4 (1 bit)

P5 : IO Line Index
bits : 5 - 5 (1 bit)

P6 : IO Line Index
bits : 6 - 6 (1 bit)

P7 : IO Line Index
bits : 7 - 7 (1 bit)

P8 : IO Line Index
bits : 8 - 8 (1 bit)

P9 : IO Line Index
bits : 9 - 9 (1 bit)

P10 : IO Line Index
bits : 10 - 10 (1 bit)

P11 : IO Line Index
bits : 11 - 11 (1 bit)

P12 : IO Line Index
bits : 12 - 12 (1 bit)

P13 : IO Line Index
bits : 13 - 13 (1 bit)

P14 : IO Line Index
bits : 14 - 14 (1 bit)

P15 : IO Line Index
bits : 15 - 15 (1 bit)

P16 : IO Line Index
bits : 16 - 16 (1 bit)

P17 : IO Line Index
bits : 17 - 17 (1 bit)

P18 : IO Line Index
bits : 18 - 18 (1 bit)

P19 : IO Line Index
bits : 19 - 19 (1 bit)

P20 : IO Line Index
bits : 20 - 20 (1 bit)

P21 : IO Line Index
bits : 21 - 21 (1 bit)

P22 : IO Line Index
bits : 22 - 22 (1 bit)

P23 : IO Line Index
bits : 23 - 23 (1 bit)

P24 : IO Line Index
bits : 24 - 24 (1 bit)

P25 : IO Line Index
bits : 25 - 25 (1 bit)

P26 : IO Line Index
bits : 26 - 26 (1 bit)

P27 : IO Line Index
bits : 27 - 27 (1 bit)

P28 : IO Line Index
bits : 28 - 28 (1 bit)

P29 : IO Line Index
bits : 29 - 29 (1 bit)

P30 : IO Line Index
bits : 30 - 30 (1 bit)

P31 : IO Line Index
bits : 31 - 31 (1 bit)


AIMMR

Additional Interrupt Modes Mask Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AIMMR AIMMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : IO Line Index
bits : 0 - 0 (1 bit)
access : read-only

P1 : IO Line Index
bits : 1 - 1 (1 bit)
access : read-only

P2 : IO Line Index
bits : 2 - 2 (1 bit)
access : read-only

P3 : IO Line Index
bits : 3 - 3 (1 bit)
access : read-only

P4 : IO Line Index
bits : 4 - 4 (1 bit)
access : read-only

P5 : IO Line Index
bits : 5 - 5 (1 bit)
access : read-only

P6 : IO Line Index
bits : 6 - 6 (1 bit)
access : read-only

P7 : IO Line Index
bits : 7 - 7 (1 bit)
access : read-only

P8 : IO Line Index
bits : 8 - 8 (1 bit)
access : read-only

P9 : IO Line Index
bits : 9 - 9 (1 bit)
access : read-only

P10 : IO Line Index
bits : 10 - 10 (1 bit)
access : read-only

P11 : IO Line Index
bits : 11 - 11 (1 bit)
access : read-only

P12 : IO Line Index
bits : 12 - 12 (1 bit)
access : read-only

P13 : IO Line Index
bits : 13 - 13 (1 bit)
access : read-only

P14 : IO Line Index
bits : 14 - 14 (1 bit)
access : read-only

P15 : IO Line Index
bits : 15 - 15 (1 bit)
access : read-only

P16 : IO Line Index
bits : 16 - 16 (1 bit)
access : read-only

P17 : IO Line Index
bits : 17 - 17 (1 bit)
access : read-only

P18 : IO Line Index
bits : 18 - 18 (1 bit)
access : read-only

P19 : IO Line Index
bits : 19 - 19 (1 bit)
access : read-only

P20 : IO Line Index
bits : 20 - 20 (1 bit)
access : read-only

P21 : IO Line Index
bits : 21 - 21 (1 bit)
access : read-only

P22 : IO Line Index
bits : 22 - 22 (1 bit)
access : read-only

P23 : IO Line Index
bits : 23 - 23 (1 bit)
access : read-only

P24 : IO Line Index
bits : 24 - 24 (1 bit)
access : read-only

P25 : IO Line Index
bits : 25 - 25 (1 bit)
access : read-only

P26 : IO Line Index
bits : 26 - 26 (1 bit)
access : read-only

P27 : IO Line Index
bits : 27 - 27 (1 bit)
access : read-only

P28 : IO Line Index
bits : 28 - 28 (1 bit)
access : read-only

P29 : IO Line Index
bits : 29 - 29 (1 bit)
access : read-only

P30 : IO Line Index
bits : 30 - 30 (1 bit)
access : read-only

P31 : IO Line Index
bits : 31 - 31 (1 bit)
access : read-only


PIO_ESR

Edge Select Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_ESR PIO_ESR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Edge Interrupt Selection
bits : 0 - 0 (1 bit)

P1 : Edge Interrupt Selection
bits : 1 - 1 (1 bit)

P2 : Edge Interrupt Selection
bits : 2 - 2 (1 bit)

P3 : Edge Interrupt Selection
bits : 3 - 3 (1 bit)

P4 : Edge Interrupt Selection
bits : 4 - 4 (1 bit)

P5 : Edge Interrupt Selection
bits : 5 - 5 (1 bit)

P6 : Edge Interrupt Selection
bits : 6 - 6 (1 bit)

P7 : Edge Interrupt Selection
bits : 7 - 7 (1 bit)

P8 : Edge Interrupt Selection
bits : 8 - 8 (1 bit)

P9 : Edge Interrupt Selection
bits : 9 - 9 (1 bit)

P10 : Edge Interrupt Selection
bits : 10 - 10 (1 bit)

P11 : Edge Interrupt Selection
bits : 11 - 11 (1 bit)

P12 : Edge Interrupt Selection
bits : 12 - 12 (1 bit)

P13 : Edge Interrupt Selection
bits : 13 - 13 (1 bit)

P14 : Edge Interrupt Selection
bits : 14 - 14 (1 bit)

P15 : Edge Interrupt Selection
bits : 15 - 15 (1 bit)

P16 : Edge Interrupt Selection
bits : 16 - 16 (1 bit)

P17 : Edge Interrupt Selection
bits : 17 - 17 (1 bit)

P18 : Edge Interrupt Selection
bits : 18 - 18 (1 bit)

P19 : Edge Interrupt Selection
bits : 19 - 19 (1 bit)

P20 : Edge Interrupt Selection
bits : 20 - 20 (1 bit)

P21 : Edge Interrupt Selection
bits : 21 - 21 (1 bit)

P22 : Edge Interrupt Selection
bits : 22 - 22 (1 bit)

P23 : Edge Interrupt Selection
bits : 23 - 23 (1 bit)

P24 : Edge Interrupt Selection
bits : 24 - 24 (1 bit)

P25 : Edge Interrupt Selection
bits : 25 - 25 (1 bit)

P26 : Edge Interrupt Selection
bits : 26 - 26 (1 bit)

P27 : Edge Interrupt Selection
bits : 27 - 27 (1 bit)

P28 : Edge Interrupt Selection
bits : 28 - 28 (1 bit)

P29 : Edge Interrupt Selection
bits : 29 - 29 (1 bit)

P30 : Edge Interrupt Selection
bits : 30 - 30 (1 bit)

P31 : Edge Interrupt Selection
bits : 31 - 31 (1 bit)


ESR

Edge Select Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ESR ESR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Edge Interrupt Selection
bits : 0 - 0 (1 bit)
access : write-only

P1 : Edge Interrupt Selection
bits : 1 - 1 (1 bit)
access : write-only

P2 : Edge Interrupt Selection
bits : 2 - 2 (1 bit)
access : write-only

P3 : Edge Interrupt Selection
bits : 3 - 3 (1 bit)
access : write-only

P4 : Edge Interrupt Selection
bits : 4 - 4 (1 bit)
access : write-only

P5 : Edge Interrupt Selection
bits : 5 - 5 (1 bit)
access : write-only

P6 : Edge Interrupt Selection
bits : 6 - 6 (1 bit)
access : write-only

P7 : Edge Interrupt Selection
bits : 7 - 7 (1 bit)
access : write-only

P8 : Edge Interrupt Selection
bits : 8 - 8 (1 bit)
access : write-only

P9 : Edge Interrupt Selection
bits : 9 - 9 (1 bit)
access : write-only

P10 : Edge Interrupt Selection
bits : 10 - 10 (1 bit)
access : write-only

P11 : Edge Interrupt Selection
bits : 11 - 11 (1 bit)
access : write-only

P12 : Edge Interrupt Selection
bits : 12 - 12 (1 bit)
access : write-only

P13 : Edge Interrupt Selection
bits : 13 - 13 (1 bit)
access : write-only

P14 : Edge Interrupt Selection
bits : 14 - 14 (1 bit)
access : write-only

P15 : Edge Interrupt Selection
bits : 15 - 15 (1 bit)
access : write-only

P16 : Edge Interrupt Selection
bits : 16 - 16 (1 bit)
access : write-only

P17 : Edge Interrupt Selection
bits : 17 - 17 (1 bit)
access : write-only

P18 : Edge Interrupt Selection
bits : 18 - 18 (1 bit)
access : write-only

P19 : Edge Interrupt Selection
bits : 19 - 19 (1 bit)
access : write-only

P20 : Edge Interrupt Selection
bits : 20 - 20 (1 bit)
access : write-only

P21 : Edge Interrupt Selection
bits : 21 - 21 (1 bit)
access : write-only

P22 : Edge Interrupt Selection
bits : 22 - 22 (1 bit)
access : write-only

P23 : Edge Interrupt Selection
bits : 23 - 23 (1 bit)
access : write-only

P24 : Edge Interrupt Selection
bits : 24 - 24 (1 bit)
access : write-only

P25 : Edge Interrupt Selection
bits : 25 - 25 (1 bit)
access : write-only

P26 : Edge Interrupt Selection
bits : 26 - 26 (1 bit)
access : write-only

P27 : Edge Interrupt Selection
bits : 27 - 27 (1 bit)
access : write-only

P28 : Edge Interrupt Selection
bits : 28 - 28 (1 bit)
access : write-only

P29 : Edge Interrupt Selection
bits : 29 - 29 (1 bit)
access : write-only

P30 : Edge Interrupt Selection
bits : 30 - 30 (1 bit)
access : write-only

P31 : Edge Interrupt Selection
bits : 31 - 31 (1 bit)
access : write-only


PIO_LSR

Level Select Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_LSR PIO_LSR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Level Interrupt Selection
bits : 0 - 0 (1 bit)

P1 : Level Interrupt Selection
bits : 1 - 1 (1 bit)

P2 : Level Interrupt Selection
bits : 2 - 2 (1 bit)

P3 : Level Interrupt Selection
bits : 3 - 3 (1 bit)

P4 : Level Interrupt Selection
bits : 4 - 4 (1 bit)

P5 : Level Interrupt Selection
bits : 5 - 5 (1 bit)

P6 : Level Interrupt Selection
bits : 6 - 6 (1 bit)

P7 : Level Interrupt Selection
bits : 7 - 7 (1 bit)

P8 : Level Interrupt Selection
bits : 8 - 8 (1 bit)

P9 : Level Interrupt Selection
bits : 9 - 9 (1 bit)

P10 : Level Interrupt Selection
bits : 10 - 10 (1 bit)

P11 : Level Interrupt Selection
bits : 11 - 11 (1 bit)

P12 : Level Interrupt Selection
bits : 12 - 12 (1 bit)

P13 : Level Interrupt Selection
bits : 13 - 13 (1 bit)

P14 : Level Interrupt Selection
bits : 14 - 14 (1 bit)

P15 : Level Interrupt Selection
bits : 15 - 15 (1 bit)

P16 : Level Interrupt Selection
bits : 16 - 16 (1 bit)

P17 : Level Interrupt Selection
bits : 17 - 17 (1 bit)

P18 : Level Interrupt Selection
bits : 18 - 18 (1 bit)

P19 : Level Interrupt Selection
bits : 19 - 19 (1 bit)

P20 : Level Interrupt Selection
bits : 20 - 20 (1 bit)

P21 : Level Interrupt Selection
bits : 21 - 21 (1 bit)

P22 : Level Interrupt Selection
bits : 22 - 22 (1 bit)

P23 : Level Interrupt Selection
bits : 23 - 23 (1 bit)

P24 : Level Interrupt Selection
bits : 24 - 24 (1 bit)

P25 : Level Interrupt Selection
bits : 25 - 25 (1 bit)

P26 : Level Interrupt Selection
bits : 26 - 26 (1 bit)

P27 : Level Interrupt Selection
bits : 27 - 27 (1 bit)

P28 : Level Interrupt Selection
bits : 28 - 28 (1 bit)

P29 : Level Interrupt Selection
bits : 29 - 29 (1 bit)

P30 : Level Interrupt Selection
bits : 30 - 30 (1 bit)

P31 : Level Interrupt Selection
bits : 31 - 31 (1 bit)


LSR

Level Select Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LSR LSR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Level Interrupt Selection
bits : 0 - 0 (1 bit)
access : write-only

P1 : Level Interrupt Selection
bits : 1 - 1 (1 bit)
access : write-only

P2 : Level Interrupt Selection
bits : 2 - 2 (1 bit)
access : write-only

P3 : Level Interrupt Selection
bits : 3 - 3 (1 bit)
access : write-only

P4 : Level Interrupt Selection
bits : 4 - 4 (1 bit)
access : write-only

P5 : Level Interrupt Selection
bits : 5 - 5 (1 bit)
access : write-only

P6 : Level Interrupt Selection
bits : 6 - 6 (1 bit)
access : write-only

P7 : Level Interrupt Selection
bits : 7 - 7 (1 bit)
access : write-only

P8 : Level Interrupt Selection
bits : 8 - 8 (1 bit)
access : write-only

P9 : Level Interrupt Selection
bits : 9 - 9 (1 bit)
access : write-only

P10 : Level Interrupt Selection
bits : 10 - 10 (1 bit)
access : write-only

P11 : Level Interrupt Selection
bits : 11 - 11 (1 bit)
access : write-only

P12 : Level Interrupt Selection
bits : 12 - 12 (1 bit)
access : write-only

P13 : Level Interrupt Selection
bits : 13 - 13 (1 bit)
access : write-only

P14 : Level Interrupt Selection
bits : 14 - 14 (1 bit)
access : write-only

P15 : Level Interrupt Selection
bits : 15 - 15 (1 bit)
access : write-only

P16 : Level Interrupt Selection
bits : 16 - 16 (1 bit)
access : write-only

P17 : Level Interrupt Selection
bits : 17 - 17 (1 bit)
access : write-only

P18 : Level Interrupt Selection
bits : 18 - 18 (1 bit)
access : write-only

P19 : Level Interrupt Selection
bits : 19 - 19 (1 bit)
access : write-only

P20 : Level Interrupt Selection
bits : 20 - 20 (1 bit)
access : write-only

P21 : Level Interrupt Selection
bits : 21 - 21 (1 bit)
access : write-only

P22 : Level Interrupt Selection
bits : 22 - 22 (1 bit)
access : write-only

P23 : Level Interrupt Selection
bits : 23 - 23 (1 bit)
access : write-only

P24 : Level Interrupt Selection
bits : 24 - 24 (1 bit)
access : write-only

P25 : Level Interrupt Selection
bits : 25 - 25 (1 bit)
access : write-only

P26 : Level Interrupt Selection
bits : 26 - 26 (1 bit)
access : write-only

P27 : Level Interrupt Selection
bits : 27 - 27 (1 bit)
access : write-only

P28 : Level Interrupt Selection
bits : 28 - 28 (1 bit)
access : write-only

P29 : Level Interrupt Selection
bits : 29 - 29 (1 bit)
access : write-only

P30 : Level Interrupt Selection
bits : 30 - 30 (1 bit)
access : write-only

P31 : Level Interrupt Selection
bits : 31 - 31 (1 bit)
access : write-only


PIO_ELSR

Edge/Level Status Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_ELSR PIO_ELSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Edge/Level Interrupt Source Selection
bits : 0 - 0 (1 bit)

P1 : Edge/Level Interrupt Source Selection
bits : 1 - 1 (1 bit)

P2 : Edge/Level Interrupt Source Selection
bits : 2 - 2 (1 bit)

P3 : Edge/Level Interrupt Source Selection
bits : 3 - 3 (1 bit)

P4 : Edge/Level Interrupt Source Selection
bits : 4 - 4 (1 bit)

P5 : Edge/Level Interrupt Source Selection
bits : 5 - 5 (1 bit)

P6 : Edge/Level Interrupt Source Selection
bits : 6 - 6 (1 bit)

P7 : Edge/Level Interrupt Source Selection
bits : 7 - 7 (1 bit)

P8 : Edge/Level Interrupt Source Selection
bits : 8 - 8 (1 bit)

P9 : Edge/Level Interrupt Source Selection
bits : 9 - 9 (1 bit)

P10 : Edge/Level Interrupt Source Selection
bits : 10 - 10 (1 bit)

P11 : Edge/Level Interrupt Source Selection
bits : 11 - 11 (1 bit)

P12 : Edge/Level Interrupt Source Selection
bits : 12 - 12 (1 bit)

P13 : Edge/Level Interrupt Source Selection
bits : 13 - 13 (1 bit)

P14 : Edge/Level Interrupt Source Selection
bits : 14 - 14 (1 bit)

P15 : Edge/Level Interrupt Source Selection
bits : 15 - 15 (1 bit)

P16 : Edge/Level Interrupt Source Selection
bits : 16 - 16 (1 bit)

P17 : Edge/Level Interrupt Source Selection
bits : 17 - 17 (1 bit)

P18 : Edge/Level Interrupt Source Selection
bits : 18 - 18 (1 bit)

P19 : Edge/Level Interrupt Source Selection
bits : 19 - 19 (1 bit)

P20 : Edge/Level Interrupt Source Selection
bits : 20 - 20 (1 bit)

P21 : Edge/Level Interrupt Source Selection
bits : 21 - 21 (1 bit)

P22 : Edge/Level Interrupt Source Selection
bits : 22 - 22 (1 bit)

P23 : Edge/Level Interrupt Source Selection
bits : 23 - 23 (1 bit)

P24 : Edge/Level Interrupt Source Selection
bits : 24 - 24 (1 bit)

P25 : Edge/Level Interrupt Source Selection
bits : 25 - 25 (1 bit)

P26 : Edge/Level Interrupt Source Selection
bits : 26 - 26 (1 bit)

P27 : Edge/Level Interrupt Source Selection
bits : 27 - 27 (1 bit)

P28 : Edge/Level Interrupt Source Selection
bits : 28 - 28 (1 bit)

P29 : Edge/Level Interrupt Source Selection
bits : 29 - 29 (1 bit)

P30 : Edge/Level Interrupt Source Selection
bits : 30 - 30 (1 bit)

P31 : Edge/Level Interrupt Source Selection
bits : 31 - 31 (1 bit)


ELSR

Edge/Level Status Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ELSR ELSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Edge/Level Interrupt Source Selection
bits : 0 - 0 (1 bit)
access : read-only

P1 : Edge/Level Interrupt Source Selection
bits : 1 - 1 (1 bit)
access : read-only

P2 : Edge/Level Interrupt Source Selection
bits : 2 - 2 (1 bit)
access : read-only

P3 : Edge/Level Interrupt Source Selection
bits : 3 - 3 (1 bit)
access : read-only

P4 : Edge/Level Interrupt Source Selection
bits : 4 - 4 (1 bit)
access : read-only

P5 : Edge/Level Interrupt Source Selection
bits : 5 - 5 (1 bit)
access : read-only

P6 : Edge/Level Interrupt Source Selection
bits : 6 - 6 (1 bit)
access : read-only

P7 : Edge/Level Interrupt Source Selection
bits : 7 - 7 (1 bit)
access : read-only

P8 : Edge/Level Interrupt Source Selection
bits : 8 - 8 (1 bit)
access : read-only

P9 : Edge/Level Interrupt Source Selection
bits : 9 - 9 (1 bit)
access : read-only

P10 : Edge/Level Interrupt Source Selection
bits : 10 - 10 (1 bit)
access : read-only

P11 : Edge/Level Interrupt Source Selection
bits : 11 - 11 (1 bit)
access : read-only

P12 : Edge/Level Interrupt Source Selection
bits : 12 - 12 (1 bit)
access : read-only

P13 : Edge/Level Interrupt Source Selection
bits : 13 - 13 (1 bit)
access : read-only

P14 : Edge/Level Interrupt Source Selection
bits : 14 - 14 (1 bit)
access : read-only

P15 : Edge/Level Interrupt Source Selection
bits : 15 - 15 (1 bit)
access : read-only

P16 : Edge/Level Interrupt Source Selection
bits : 16 - 16 (1 bit)
access : read-only

P17 : Edge/Level Interrupt Source Selection
bits : 17 - 17 (1 bit)
access : read-only

P18 : Edge/Level Interrupt Source Selection
bits : 18 - 18 (1 bit)
access : read-only

P19 : Edge/Level Interrupt Source Selection
bits : 19 - 19 (1 bit)
access : read-only

P20 : Edge/Level Interrupt Source Selection
bits : 20 - 20 (1 bit)
access : read-only

P21 : Edge/Level Interrupt Source Selection
bits : 21 - 21 (1 bit)
access : read-only

P22 : Edge/Level Interrupt Source Selection
bits : 22 - 22 (1 bit)
access : read-only

P23 : Edge/Level Interrupt Source Selection
bits : 23 - 23 (1 bit)
access : read-only

P24 : Edge/Level Interrupt Source Selection
bits : 24 - 24 (1 bit)
access : read-only

P25 : Edge/Level Interrupt Source Selection
bits : 25 - 25 (1 bit)
access : read-only

P26 : Edge/Level Interrupt Source Selection
bits : 26 - 26 (1 bit)
access : read-only

P27 : Edge/Level Interrupt Source Selection
bits : 27 - 27 (1 bit)
access : read-only

P28 : Edge/Level Interrupt Source Selection
bits : 28 - 28 (1 bit)
access : read-only

P29 : Edge/Level Interrupt Source Selection
bits : 29 - 29 (1 bit)
access : read-only

P30 : Edge/Level Interrupt Source Selection
bits : 30 - 30 (1 bit)
access : read-only

P31 : Edge/Level Interrupt Source Selection
bits : 31 - 31 (1 bit)
access : read-only


PIO_FELLSR

Falling Edge/Low-Level Select Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_FELLSR PIO_FELLSR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Falling Edge/Low-Level Interrupt Selection
bits : 0 - 0 (1 bit)

P1 : Falling Edge/Low-Level Interrupt Selection
bits : 1 - 1 (1 bit)

P2 : Falling Edge/Low-Level Interrupt Selection
bits : 2 - 2 (1 bit)

P3 : Falling Edge/Low-Level Interrupt Selection
bits : 3 - 3 (1 bit)

P4 : Falling Edge/Low-Level Interrupt Selection
bits : 4 - 4 (1 bit)

P5 : Falling Edge/Low-Level Interrupt Selection
bits : 5 - 5 (1 bit)

P6 : Falling Edge/Low-Level Interrupt Selection
bits : 6 - 6 (1 bit)

P7 : Falling Edge/Low-Level Interrupt Selection
bits : 7 - 7 (1 bit)

P8 : Falling Edge/Low-Level Interrupt Selection
bits : 8 - 8 (1 bit)

P9 : Falling Edge/Low-Level Interrupt Selection
bits : 9 - 9 (1 bit)

P10 : Falling Edge/Low-Level Interrupt Selection
bits : 10 - 10 (1 bit)

P11 : Falling Edge/Low-Level Interrupt Selection
bits : 11 - 11 (1 bit)

P12 : Falling Edge/Low-Level Interrupt Selection
bits : 12 - 12 (1 bit)

P13 : Falling Edge/Low-Level Interrupt Selection
bits : 13 - 13 (1 bit)

P14 : Falling Edge/Low-Level Interrupt Selection
bits : 14 - 14 (1 bit)

P15 : Falling Edge/Low-Level Interrupt Selection
bits : 15 - 15 (1 bit)

P16 : Falling Edge/Low-Level Interrupt Selection
bits : 16 - 16 (1 bit)

P17 : Falling Edge/Low-Level Interrupt Selection
bits : 17 - 17 (1 bit)

P18 : Falling Edge/Low-Level Interrupt Selection
bits : 18 - 18 (1 bit)

P19 : Falling Edge/Low-Level Interrupt Selection
bits : 19 - 19 (1 bit)

P20 : Falling Edge/Low-Level Interrupt Selection
bits : 20 - 20 (1 bit)

P21 : Falling Edge/Low-Level Interrupt Selection
bits : 21 - 21 (1 bit)

P22 : Falling Edge/Low-Level Interrupt Selection
bits : 22 - 22 (1 bit)

P23 : Falling Edge/Low-Level Interrupt Selection
bits : 23 - 23 (1 bit)

P24 : Falling Edge/Low-Level Interrupt Selection
bits : 24 - 24 (1 bit)

P25 : Falling Edge/Low-Level Interrupt Selection
bits : 25 - 25 (1 bit)

P26 : Falling Edge/Low-Level Interrupt Selection
bits : 26 - 26 (1 bit)

P27 : Falling Edge/Low-Level Interrupt Selection
bits : 27 - 27 (1 bit)

P28 : Falling Edge/Low-Level Interrupt Selection
bits : 28 - 28 (1 bit)

P29 : Falling Edge/Low-Level Interrupt Selection
bits : 29 - 29 (1 bit)

P30 : Falling Edge/Low-Level Interrupt Selection
bits : 30 - 30 (1 bit)

P31 : Falling Edge/Low-Level Interrupt Selection
bits : 31 - 31 (1 bit)


FELLSR

Falling Edge/Low-Level Select Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FELLSR FELLSR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Falling Edge/Low-Level Interrupt Selection
bits : 0 - 0 (1 bit)
access : write-only

P1 : Falling Edge/Low-Level Interrupt Selection
bits : 1 - 1 (1 bit)
access : write-only

P2 : Falling Edge/Low-Level Interrupt Selection
bits : 2 - 2 (1 bit)
access : write-only

P3 : Falling Edge/Low-Level Interrupt Selection
bits : 3 - 3 (1 bit)
access : write-only

P4 : Falling Edge/Low-Level Interrupt Selection
bits : 4 - 4 (1 bit)
access : write-only

P5 : Falling Edge/Low-Level Interrupt Selection
bits : 5 - 5 (1 bit)
access : write-only

P6 : Falling Edge/Low-Level Interrupt Selection
bits : 6 - 6 (1 bit)
access : write-only

P7 : Falling Edge/Low-Level Interrupt Selection
bits : 7 - 7 (1 bit)
access : write-only

P8 : Falling Edge/Low-Level Interrupt Selection
bits : 8 - 8 (1 bit)
access : write-only

P9 : Falling Edge/Low-Level Interrupt Selection
bits : 9 - 9 (1 bit)
access : write-only

P10 : Falling Edge/Low-Level Interrupt Selection
bits : 10 - 10 (1 bit)
access : write-only

P11 : Falling Edge/Low-Level Interrupt Selection
bits : 11 - 11 (1 bit)
access : write-only

P12 : Falling Edge/Low-Level Interrupt Selection
bits : 12 - 12 (1 bit)
access : write-only

P13 : Falling Edge/Low-Level Interrupt Selection
bits : 13 - 13 (1 bit)
access : write-only

P14 : Falling Edge/Low-Level Interrupt Selection
bits : 14 - 14 (1 bit)
access : write-only

P15 : Falling Edge/Low-Level Interrupt Selection
bits : 15 - 15 (1 bit)
access : write-only

P16 : Falling Edge/Low-Level Interrupt Selection
bits : 16 - 16 (1 bit)
access : write-only

P17 : Falling Edge/Low-Level Interrupt Selection
bits : 17 - 17 (1 bit)
access : write-only

P18 : Falling Edge/Low-Level Interrupt Selection
bits : 18 - 18 (1 bit)
access : write-only

P19 : Falling Edge/Low-Level Interrupt Selection
bits : 19 - 19 (1 bit)
access : write-only

P20 : Falling Edge/Low-Level Interrupt Selection
bits : 20 - 20 (1 bit)
access : write-only

P21 : Falling Edge/Low-Level Interrupt Selection
bits : 21 - 21 (1 bit)
access : write-only

P22 : Falling Edge/Low-Level Interrupt Selection
bits : 22 - 22 (1 bit)
access : write-only

P23 : Falling Edge/Low-Level Interrupt Selection
bits : 23 - 23 (1 bit)
access : write-only

P24 : Falling Edge/Low-Level Interrupt Selection
bits : 24 - 24 (1 bit)
access : write-only

P25 : Falling Edge/Low-Level Interrupt Selection
bits : 25 - 25 (1 bit)
access : write-only

P26 : Falling Edge/Low-Level Interrupt Selection
bits : 26 - 26 (1 bit)
access : write-only

P27 : Falling Edge/Low-Level Interrupt Selection
bits : 27 - 27 (1 bit)
access : write-only

P28 : Falling Edge/Low-Level Interrupt Selection
bits : 28 - 28 (1 bit)
access : write-only

P29 : Falling Edge/Low-Level Interrupt Selection
bits : 29 - 29 (1 bit)
access : write-only

P30 : Falling Edge/Low-Level Interrupt Selection
bits : 30 - 30 (1 bit)
access : write-only

P31 : Falling Edge/Low-Level Interrupt Selection
bits : 31 - 31 (1 bit)
access : write-only


PIO_REHLSR

Rising Edge/High-Level Select Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PIO_REHLSR PIO_REHLSR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Rising Edge/High-Level Interrupt Selection
bits : 0 - 0 (1 bit)

P1 : Rising Edge/High-Level Interrupt Selection
bits : 1 - 1 (1 bit)

P2 : Rising Edge/High-Level Interrupt Selection
bits : 2 - 2 (1 bit)

P3 : Rising Edge/High-Level Interrupt Selection
bits : 3 - 3 (1 bit)

P4 : Rising Edge/High-Level Interrupt Selection
bits : 4 - 4 (1 bit)

P5 : Rising Edge/High-Level Interrupt Selection
bits : 5 - 5 (1 bit)

P6 : Rising Edge/High-Level Interrupt Selection
bits : 6 - 6 (1 bit)

P7 : Rising Edge/High-Level Interrupt Selection
bits : 7 - 7 (1 bit)

P8 : Rising Edge/High-Level Interrupt Selection
bits : 8 - 8 (1 bit)

P9 : Rising Edge/High-Level Interrupt Selection
bits : 9 - 9 (1 bit)

P10 : Rising Edge/High-Level Interrupt Selection
bits : 10 - 10 (1 bit)

P11 : Rising Edge/High-Level Interrupt Selection
bits : 11 - 11 (1 bit)

P12 : Rising Edge/High-Level Interrupt Selection
bits : 12 - 12 (1 bit)

P13 : Rising Edge/High-Level Interrupt Selection
bits : 13 - 13 (1 bit)

P14 : Rising Edge/High-Level Interrupt Selection
bits : 14 - 14 (1 bit)

P15 : Rising Edge/High-Level Interrupt Selection
bits : 15 - 15 (1 bit)

P16 : Rising Edge/High-Level Interrupt Selection
bits : 16 - 16 (1 bit)

P17 : Rising Edge/High-Level Interrupt Selection
bits : 17 - 17 (1 bit)

P18 : Rising Edge/High-Level Interrupt Selection
bits : 18 - 18 (1 bit)

P19 : Rising Edge/High-Level Interrupt Selection
bits : 19 - 19 (1 bit)

P20 : Rising Edge/High-Level Interrupt Selection
bits : 20 - 20 (1 bit)

P21 : Rising Edge/High-Level Interrupt Selection
bits : 21 - 21 (1 bit)

P22 : Rising Edge/High-Level Interrupt Selection
bits : 22 - 22 (1 bit)

P23 : Rising Edge/High-Level Interrupt Selection
bits : 23 - 23 (1 bit)

P24 : Rising Edge/High-Level Interrupt Selection
bits : 24 - 24 (1 bit)

P25 : Rising Edge/High-Level Interrupt Selection
bits : 25 - 25 (1 bit)

P26 : Rising Edge/High-Level Interrupt Selection
bits : 26 - 26 (1 bit)

P27 : Rising Edge/High-Level Interrupt Selection
bits : 27 - 27 (1 bit)

P28 : Rising Edge/High-Level Interrupt Selection
bits : 28 - 28 (1 bit)

P29 : Rising Edge/High-Level Interrupt Selection
bits : 29 - 29 (1 bit)

P30 : Rising Edge/High-Level Interrupt Selection
bits : 30 - 30 (1 bit)

P31 : Rising Edge/High-Level Interrupt Selection
bits : 31 - 31 (1 bit)


REHLSR

Rising Edge/High-Level Select Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

REHLSR REHLSR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Rising Edge/High-Level Interrupt Selection
bits : 0 - 0 (1 bit)
access : write-only

P1 : Rising Edge/High-Level Interrupt Selection
bits : 1 - 1 (1 bit)
access : write-only

P2 : Rising Edge/High-Level Interrupt Selection
bits : 2 - 2 (1 bit)
access : write-only

P3 : Rising Edge/High-Level Interrupt Selection
bits : 3 - 3 (1 bit)
access : write-only

P4 : Rising Edge/High-Level Interrupt Selection
bits : 4 - 4 (1 bit)
access : write-only

P5 : Rising Edge/High-Level Interrupt Selection
bits : 5 - 5 (1 bit)
access : write-only

P6 : Rising Edge/High-Level Interrupt Selection
bits : 6 - 6 (1 bit)
access : write-only

P7 : Rising Edge/High-Level Interrupt Selection
bits : 7 - 7 (1 bit)
access : write-only

P8 : Rising Edge/High-Level Interrupt Selection
bits : 8 - 8 (1 bit)
access : write-only

P9 : Rising Edge/High-Level Interrupt Selection
bits : 9 - 9 (1 bit)
access : write-only

P10 : Rising Edge/High-Level Interrupt Selection
bits : 10 - 10 (1 bit)
access : write-only

P11 : Rising Edge/High-Level Interrupt Selection
bits : 11 - 11 (1 bit)
access : write-only

P12 : Rising Edge/High-Level Interrupt Selection
bits : 12 - 12 (1 bit)
access : write-only

P13 : Rising Edge/High-Level Interrupt Selection
bits : 13 - 13 (1 bit)
access : write-only

P14 : Rising Edge/High-Level Interrupt Selection
bits : 14 - 14 (1 bit)
access : write-only

P15 : Rising Edge/High-Level Interrupt Selection
bits : 15 - 15 (1 bit)
access : write-only

P16 : Rising Edge/High-Level Interrupt Selection
bits : 16 - 16 (1 bit)
access : write-only

P17 : Rising Edge/High-Level Interrupt Selection
bits : 17 - 17 (1 bit)
access : write-only

P18 : Rising Edge/High-Level Interrupt Selection
bits : 18 - 18 (1 bit)
access : write-only

P19 : Rising Edge/High-Level Interrupt Selection
bits : 19 - 19 (1 bit)
access : write-only

P20 : Rising Edge/High-Level Interrupt Selection
bits : 20 - 20 (1 bit)
access : write-only

P21 : Rising Edge/High-Level Interrupt Selection
bits : 21 - 21 (1 bit)
access : write-only

P22 : Rising Edge/High-Level Interrupt Selection
bits : 22 - 22 (1 bit)
access : write-only

P23 : Rising Edge/High-Level Interrupt Selection
bits : 23 - 23 (1 bit)
access : write-only

P24 : Rising Edge/High-Level Interrupt Selection
bits : 24 - 24 (1 bit)
access : write-only

P25 : Rising Edge/High-Level Interrupt Selection
bits : 25 - 25 (1 bit)
access : write-only

P26 : Rising Edge/High-Level Interrupt Selection
bits : 26 - 26 (1 bit)
access : write-only

P27 : Rising Edge/High-Level Interrupt Selection
bits : 27 - 27 (1 bit)
access : write-only

P28 : Rising Edge/High-Level Interrupt Selection
bits : 28 - 28 (1 bit)
access : write-only

P29 : Rising Edge/High-Level Interrupt Selection
bits : 29 - 29 (1 bit)
access : write-only

P30 : Rising Edge/High-Level Interrupt Selection
bits : 30 - 30 (1 bit)
access : write-only

P31 : Rising Edge/High-Level Interrupt Selection
bits : 31 - 31 (1 bit)
access : write-only


PIO_FRLHSR

Fall/Rise - Low/High Status Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_FRLHSR PIO_FRLHSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Edge/Level Interrupt Source Selection
bits : 0 - 0 (1 bit)

P1 : Edge/Level Interrupt Source Selection
bits : 1 - 1 (1 bit)

P2 : Edge/Level Interrupt Source Selection
bits : 2 - 2 (1 bit)

P3 : Edge/Level Interrupt Source Selection
bits : 3 - 3 (1 bit)

P4 : Edge/Level Interrupt Source Selection
bits : 4 - 4 (1 bit)

P5 : Edge/Level Interrupt Source Selection
bits : 5 - 5 (1 bit)

P6 : Edge/Level Interrupt Source Selection
bits : 6 - 6 (1 bit)

P7 : Edge/Level Interrupt Source Selection
bits : 7 - 7 (1 bit)

P8 : Edge/Level Interrupt Source Selection
bits : 8 - 8 (1 bit)

P9 : Edge/Level Interrupt Source Selection
bits : 9 - 9 (1 bit)

P10 : Edge/Level Interrupt Source Selection
bits : 10 - 10 (1 bit)

P11 : Edge/Level Interrupt Source Selection
bits : 11 - 11 (1 bit)

P12 : Edge/Level Interrupt Source Selection
bits : 12 - 12 (1 bit)

P13 : Edge/Level Interrupt Source Selection
bits : 13 - 13 (1 bit)

P14 : Edge/Level Interrupt Source Selection
bits : 14 - 14 (1 bit)

P15 : Edge/Level Interrupt Source Selection
bits : 15 - 15 (1 bit)

P16 : Edge/Level Interrupt Source Selection
bits : 16 - 16 (1 bit)

P17 : Edge/Level Interrupt Source Selection
bits : 17 - 17 (1 bit)

P18 : Edge/Level Interrupt Source Selection
bits : 18 - 18 (1 bit)

P19 : Edge/Level Interrupt Source Selection
bits : 19 - 19 (1 bit)

P20 : Edge/Level Interrupt Source Selection
bits : 20 - 20 (1 bit)

P21 : Edge/Level Interrupt Source Selection
bits : 21 - 21 (1 bit)

P22 : Edge/Level Interrupt Source Selection
bits : 22 - 22 (1 bit)

P23 : Edge/Level Interrupt Source Selection
bits : 23 - 23 (1 bit)

P24 : Edge/Level Interrupt Source Selection
bits : 24 - 24 (1 bit)

P25 : Edge/Level Interrupt Source Selection
bits : 25 - 25 (1 bit)

P26 : Edge/Level Interrupt Source Selection
bits : 26 - 26 (1 bit)

P27 : Edge/Level Interrupt Source Selection
bits : 27 - 27 (1 bit)

P28 : Edge/Level Interrupt Source Selection
bits : 28 - 28 (1 bit)

P29 : Edge/Level Interrupt Source Selection
bits : 29 - 29 (1 bit)

P30 : Edge/Level Interrupt Source Selection
bits : 30 - 30 (1 bit)

P31 : Edge/Level Interrupt Source Selection
bits : 31 - 31 (1 bit)


FRLHSR

Fall/Rise - Low/High Status Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FRLHSR FRLHSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Edge/Level Interrupt Source Selection
bits : 0 - 0 (1 bit)
access : read-only

P1 : Edge/Level Interrupt Source Selection
bits : 1 - 1 (1 bit)
access : read-only

P2 : Edge/Level Interrupt Source Selection
bits : 2 - 2 (1 bit)
access : read-only

P3 : Edge/Level Interrupt Source Selection
bits : 3 - 3 (1 bit)
access : read-only

P4 : Edge/Level Interrupt Source Selection
bits : 4 - 4 (1 bit)
access : read-only

P5 : Edge/Level Interrupt Source Selection
bits : 5 - 5 (1 bit)
access : read-only

P6 : Edge/Level Interrupt Source Selection
bits : 6 - 6 (1 bit)
access : read-only

P7 : Edge/Level Interrupt Source Selection
bits : 7 - 7 (1 bit)
access : read-only

P8 : Edge/Level Interrupt Source Selection
bits : 8 - 8 (1 bit)
access : read-only

P9 : Edge/Level Interrupt Source Selection
bits : 9 - 9 (1 bit)
access : read-only

P10 : Edge/Level Interrupt Source Selection
bits : 10 - 10 (1 bit)
access : read-only

P11 : Edge/Level Interrupt Source Selection
bits : 11 - 11 (1 bit)
access : read-only

P12 : Edge/Level Interrupt Source Selection
bits : 12 - 12 (1 bit)
access : read-only

P13 : Edge/Level Interrupt Source Selection
bits : 13 - 13 (1 bit)
access : read-only

P14 : Edge/Level Interrupt Source Selection
bits : 14 - 14 (1 bit)
access : read-only

P15 : Edge/Level Interrupt Source Selection
bits : 15 - 15 (1 bit)
access : read-only

P16 : Edge/Level Interrupt Source Selection
bits : 16 - 16 (1 bit)
access : read-only

P17 : Edge/Level Interrupt Source Selection
bits : 17 - 17 (1 bit)
access : read-only

P18 : Edge/Level Interrupt Source Selection
bits : 18 - 18 (1 bit)
access : read-only

P19 : Edge/Level Interrupt Source Selection
bits : 19 - 19 (1 bit)
access : read-only

P20 : Edge/Level Interrupt Source Selection
bits : 20 - 20 (1 bit)
access : read-only

P21 : Edge/Level Interrupt Source Selection
bits : 21 - 21 (1 bit)
access : read-only

P22 : Edge/Level Interrupt Source Selection
bits : 22 - 22 (1 bit)
access : read-only

P23 : Edge/Level Interrupt Source Selection
bits : 23 - 23 (1 bit)
access : read-only

P24 : Edge/Level Interrupt Source Selection
bits : 24 - 24 (1 bit)
access : read-only

P25 : Edge/Level Interrupt Source Selection
bits : 25 - 25 (1 bit)
access : read-only

P26 : Edge/Level Interrupt Source Selection
bits : 26 - 26 (1 bit)
access : read-only

P27 : Edge/Level Interrupt Source Selection
bits : 27 - 27 (1 bit)
access : read-only

P28 : Edge/Level Interrupt Source Selection
bits : 28 - 28 (1 bit)
access : read-only

P29 : Edge/Level Interrupt Source Selection
bits : 29 - 29 (1 bit)
access : read-only

P30 : Edge/Level Interrupt Source Selection
bits : 30 - 30 (1 bit)
access : read-only

P31 : Edge/Level Interrupt Source Selection
bits : 31 - 31 (1 bit)
access : read-only


PIO_LOCKSR

Lock Status
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_LOCKSR PIO_LOCKSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Lock Status
bits : 0 - 0 (1 bit)

P1 : Lock Status
bits : 1 - 1 (1 bit)

P2 : Lock Status
bits : 2 - 2 (1 bit)

P3 : Lock Status
bits : 3 - 3 (1 bit)

P4 : Lock Status
bits : 4 - 4 (1 bit)

P5 : Lock Status
bits : 5 - 5 (1 bit)

P6 : Lock Status
bits : 6 - 6 (1 bit)

P7 : Lock Status
bits : 7 - 7 (1 bit)

P8 : Lock Status
bits : 8 - 8 (1 bit)

P9 : Lock Status
bits : 9 - 9 (1 bit)

P10 : Lock Status
bits : 10 - 10 (1 bit)

P11 : Lock Status
bits : 11 - 11 (1 bit)

P12 : Lock Status
bits : 12 - 12 (1 bit)

P13 : Lock Status
bits : 13 - 13 (1 bit)

P14 : Lock Status
bits : 14 - 14 (1 bit)

P15 : Lock Status
bits : 15 - 15 (1 bit)

P16 : Lock Status
bits : 16 - 16 (1 bit)

P17 : Lock Status
bits : 17 - 17 (1 bit)

P18 : Lock Status
bits : 18 - 18 (1 bit)

P19 : Lock Status
bits : 19 - 19 (1 bit)

P20 : Lock Status
bits : 20 - 20 (1 bit)

P21 : Lock Status
bits : 21 - 21 (1 bit)

P22 : Lock Status
bits : 22 - 22 (1 bit)

P23 : Lock Status
bits : 23 - 23 (1 bit)

P24 : Lock Status
bits : 24 - 24 (1 bit)

P25 : Lock Status
bits : 25 - 25 (1 bit)

P26 : Lock Status
bits : 26 - 26 (1 bit)

P27 : Lock Status
bits : 27 - 27 (1 bit)

P28 : Lock Status
bits : 28 - 28 (1 bit)

P29 : Lock Status
bits : 29 - 29 (1 bit)

P30 : Lock Status
bits : 30 - 30 (1 bit)

P31 : Lock Status
bits : 31 - 31 (1 bit)


LOCKSR

Lock Status
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LOCKSR LOCKSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31

P0 : Lock Status
bits : 0 - 0 (1 bit)
access : read-only

P1 : Lock Status
bits : 1 - 1 (1 bit)
access : read-only

P2 : Lock Status
bits : 2 - 2 (1 bit)
access : read-only

P3 : Lock Status
bits : 3 - 3 (1 bit)
access : read-only

P4 : Lock Status
bits : 4 - 4 (1 bit)
access : read-only

P5 : Lock Status
bits : 5 - 5 (1 bit)
access : read-only

P6 : Lock Status
bits : 6 - 6 (1 bit)
access : read-only

P7 : Lock Status
bits : 7 - 7 (1 bit)
access : read-only

P8 : Lock Status
bits : 8 - 8 (1 bit)
access : read-only

P9 : Lock Status
bits : 9 - 9 (1 bit)
access : read-only

P10 : Lock Status
bits : 10 - 10 (1 bit)
access : read-only

P11 : Lock Status
bits : 11 - 11 (1 bit)
access : read-only

P12 : Lock Status
bits : 12 - 12 (1 bit)
access : read-only

P13 : Lock Status
bits : 13 - 13 (1 bit)
access : read-only

P14 : Lock Status
bits : 14 - 14 (1 bit)
access : read-only

P15 : Lock Status
bits : 15 - 15 (1 bit)
access : read-only

P16 : Lock Status
bits : 16 - 16 (1 bit)
access : read-only

P17 : Lock Status
bits : 17 - 17 (1 bit)
access : read-only

P18 : Lock Status
bits : 18 - 18 (1 bit)
access : read-only

P19 : Lock Status
bits : 19 - 19 (1 bit)
access : read-only

P20 : Lock Status
bits : 20 - 20 (1 bit)
access : read-only

P21 : Lock Status
bits : 21 - 21 (1 bit)
access : read-only

P22 : Lock Status
bits : 22 - 22 (1 bit)
access : read-only

P23 : Lock Status
bits : 23 - 23 (1 bit)
access : read-only

P24 : Lock Status
bits : 24 - 24 (1 bit)
access : read-only

P25 : Lock Status
bits : 25 - 25 (1 bit)
access : read-only

P26 : Lock Status
bits : 26 - 26 (1 bit)
access : read-only

P27 : Lock Status
bits : 27 - 27 (1 bit)
access : read-only

P28 : Lock Status
bits : 28 - 28 (1 bit)
access : read-only

P29 : Lock Status
bits : 29 - 29 (1 bit)
access : read-only

P30 : Lock Status
bits : 30 - 30 (1 bit)
access : read-only

P31 : Lock Status
bits : 31 - 31 (1 bit)
access : read-only


PIO_WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIO_WPMR PIO_WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)

Enumeration: WPKEYSelect

0x50494F : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

End of enumeration elements list.


WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write

Enumeration: WPKEYSelect

0x50494F : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

End of enumeration elements list.


PIO_WPSR

Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIO_WPSR PIO_WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)

WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)


WPSR

Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only


VERSION

Version Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION MFN

VERSION : Hardware Module Version
bits : 0 - 11 (12 bit)
access : read-only

MFN : Metal Fix Number
bits : 16 - 18 (3 bit)
access : read-only



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