\n
address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
Interrupt Controller Type Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTLINESNUM : Total number of interrupt lines supported by an implementation, defined in groups of 32
bits : 0 - 3 (4 bit)
Auxiliary Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISFOLD : Disables folding of IT instructions
bits : 2 - 2 (1 bit)
FPEXCODIS : Disables FPU exception outputs
bits : 10 - 10 (1 bit)
DISRAMODE : Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions
bits : 11 - 11 (1 bit)
DISITMATBFLUSH : Disables ITM and DWT ATB flush
bits : 12 - 12 (1 bit)
DISBTACREAD :
bits : 13 - 13 (1 bit)
DISBTACALLOC :
bits : 14 - 14 (1 bit)
DISCRITAXIRUR :
bits : 15 - 15 (1 bit)
DISDI :
bits : 16 - 20 (5 bit)
DISISSCH1 :
bits : 21 - 25 (5 bit)
DISDYNADD : Disables dynamic allocation of ADD and SUB instructions
bits : 26 - 26 (1 bit)
DISCRITAXIRUW : Disable critical AXI read-under-write
bits : 27 - 27 (1 bit)
DISFPUISSOPT : Disables dynamic allocation of ADD and SUB instructions
bits : 28 - 28 (1 bit)
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