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address_offset : 0x0 Bytes (0x0)
size : 0x2D byte (0x0)
mem_usage : registers
protection : not protected
Control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE : Peripheral enable
bits : 0 - 0 (1 bit)
TXIE : TXIE
bits : 1 - 1 (1 bit)
RXIE : RXIE
bits : 2 - 2 (1 bit)
ADDRE : ADDRE
bits : 3 - 3 (1 bit)
NACKIE : NACKIE
bits : 4 - 4 (1 bit)
STOPIE : STOPIE
bits : 5 - 5 (1 bit)
TCIE : TCIE
bits : 6 - 6 (1 bit)
ERRIE : ERRIE
bits : 7 - 7 (1 bit)
DNF : DNF
bits : 8 - 11 (4 bit)
ANFOFF : ANFOFF
bits : 12 - 12 (1 bit)
TCDMAEN : TCDMAEN
bits : 14 - 14 (1 bit)
RXDMAEN : RXDMAEN
bits : 15 - 15 (1 bit)
SBC : SBC
bits : 16 - 16 (1 bit)
NOSTRETCH : NOSTRETCH
bits : 17 - 17 (1 bit)
GCEN : GCEN
bits : 19 - 19 (1 bit)
SMBHEN : SMBHEN
bits : 20 - 20 (1 bit)
SMBDEN : SMBDEN
bits : 21 - 21 (1 bit)
ALERTEN : ALERTEN
bits : 22 - 22 (1 bit)
PECEN : PECEN
bits : 23 - 23 (1 bit)
Timing register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCLL : SCLL
bits : 0 - 7 (8 bit)
SCLH : SCLH
bits : 8 - 15 (8 bit)
SDADEL : SDADEL
bits : 16 - 19 (4 bit)
SCLDEL : SCLDEL
bits : 20 - 23 (4 bit)
PRESC : PRESC
bits : 28 - 31 (4 bit)
Timeout register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUTA : TIMEOUTA
bits : 0 - 11 (12 bit)
TIDLE : TIDLE
bits : 12 - 12 (1 bit)
TIMOUTEN : TIMOUTEN
bits : 15 - 15 (1 bit)
TIMEOUTB : TIMEOUTB
bits : 16 - 27 (12 bit)
TEXTEN : TEXTEN
bits : 31 - 31 (1 bit)
Interrupt and Status register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXE : TXE
bits : 0 - 0 (1 bit)
access : read-write
TXIS : TXIS
bits : 1 - 1 (1 bit)
access : read-write
RXNE : RXNE
bits : 2 - 2 (1 bit)
access : read-only
ADDR : ADDR
bits : 3 - 3 (1 bit)
access : read-only
NACKF : NACKF
bits : 4 - 4 (1 bit)
access : read-only
STOPF : STOPF
bits : 5 - 5 (1 bit)
access : read-only
TC : TC
bits : 6 - 6 (1 bit)
access : read-only
TCR : TCR
bits : 7 - 7 (1 bit)
access : read-only
BERR : BERR
bits : 8 - 8 (1 bit)
access : read-only
ARLO : ARLO
bits : 9 - 9 (1 bit)
access : read-only
OVR : OVR
bits : 10 - 10 (1 bit)
access : read-only
PECERR : PECERR
bits : 11 - 11 (1 bit)
access : read-only
TIMEOUT : TIMEOUT
bits : 12 - 12 (1 bit)
access : read-only
ALERT : ALERT
bits : 13 - 13 (1 bit)
access : read-only
BUSY : BUSY
bits : 15 - 15 (1 bit)
access : read-only
DIR : DIR
bits : 16 - 16 (1 bit)
access : read-only
ADDCODE : ADDCODE
bits : 17 - 23 (7 bit)
access : read-only
Interrupt clear register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ADDRCF : Address matched flag clear
bits : 3 - 3 (1 bit)
NACKCF : Not Acknowledge flag clear
bits : 4 - 4 (1 bit)
STOPCF : Stop detection flag clear
bits : 5 - 5 (1 bit)
BERRCF : Bus error flag clear
bits : 8 - 8 (1 bit)
ARLOCF : Arbitration Lost flag clear
bits : 9 - 9 (1 bit)
OVRCF : Overrun/Underrun flag clear
bits : 10 - 10 (1 bit)
PECCF : PEC Error flag clear
bits : 11 - 11 (1 bit)
TIMOUTCF : Timeout detection flag clear
bits : 12 - 12 (1 bit)
ALERTCF : Alert flag clear
bits : 13 - 13 (1 bit)
PEC register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PEC : PEC
bits : 0 - 7 (8 bit)
Receive data register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RXDATA
bits : 0 - 7 (8 bit)
Transmit data register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TXDATA
bits : 0 - 7 (8 bit)
Control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADD0 : Slave address bit 0
bits : 0 - 0 (1 bit)
SADD1_7 : Slave address bit 7_1
bits : 1 - 7 (7 bit)
SADD8_9 : Slave address bit 8_9
bits : 8 - 9 (2 bit)
RD_WRN : Transfer direction
bits : 10 - 10 (1 bit)
ADD10 : 10-bit addressing mode
bits : 11 - 11 (1 bit)
HEAD10R : 10-bit address header only read direction
bits : 12 - 12 (1 bit)
START : Start generation
bits : 13 - 13 (1 bit)
STOP : Stop generation
bits : 14 - 14 (1 bit)
NACK : NACK generation
bits : 15 - 15 (1 bit)
NBYTES : Number of bytes
bits : 16 - 23 (8 bit)
RELOAD : NBYTES reload mode
bits : 24 - 24 (1 bit)
AUTOEND : Automatic end mode
bits : 25 - 25 (1 bit)
PECBYTE : Packet error checking byte
bits : 26 - 26 (1 bit)
Own address register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA1 : OA1
bits : 0 - 0 (1 bit)
OA11_7 : OA11_7
bits : 1 - 7 (7 bit)
OA18_9 : OA18_9
bits : 8 - 9 (2 bit)
OA1MODE : OA1MODE
bits : 10 - 10 (1 bit)
OA1EN : OA1EN
bits : 15 - 15 (1 bit)
Own address register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OA21_7 : OA21_7
bits : 1 - 7 (7 bit)
OA2MSK : OA2MSK
bits : 8 - 10 (3 bit)
OA2EN : OA2EN
bits : 15 - 15 (1 bit)
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