\n

FPU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

FPSCR


FPSCR

Floating-point Status and Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPSCR FPSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOC DZC OFC UFC IXC IDC RMode FZ DN AHP V C Z N

IOC : Invalid Operation cumulative exception bit
bits : 0 - 0 (1 bit)

DZC : Division by Zero cumulative exception bit
bits : 1 - 1 (1 bit)

OFC : Overflow cumulative exception bit
bits : 2 - 2 (1 bit)

UFC : Underflow cumulative exception bit
bits : 3 - 3 (1 bit)

IXC : Inexact cumulative exception bit
bits : 4 - 4 (1 bit)

IDC : Input Denormal cumulative exception bit
bits : 7 - 7 (1 bit)

RMode : Rounding Mode control field.
bits : 22 - 23 (2 bit)

FZ : Flush-to-zero mode control bit
bits : 24 - 24 (1 bit)

DN : Default NaN mode control bit
bits : 25 - 25 (1 bit)

AHP : Alternative half-precision control bit
bits : 26 - 26 (1 bit)

V : Overflow condition code flag
bits : 28 - 28 (1 bit)

C : Carry condition code flag
bits : 29 - 29 (1 bit)

Z : Zero condition code flag
bits : 30 - 30 (1 bit)

N : Negative condition code flag
bits : 31 - 31 (1 bit)



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