\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
OTG_HS host configuration register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSLSPCS : FS/LS PHY clock select
bits : 0 - 1 (2 bit)
access : read-write
FSLSS : FS- and LS-only support
bits : 2 - 2 (1 bit)
access : read-only
OTG_HS_Host periodic transmit FIFO/queue status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTXFSAVL : Periodic transmit data FIFO space available
bits : 0 - 15 (16 bit)
access : read-write
PTXQSAV : Periodic transmit request queue space available
bits : 16 - 23 (8 bit)
access : read-only
PTXQTOP : Top of the periodic transmit request queue
bits : 24 - 31 (8 bit)
access : read-only
OTG_HS host channel-0 characteristics register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSDEV : Low-speed device
bits : 17 - 17 (1 bit)
EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)
DAD : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CHDIS : Channel disable
bits : 30 - 30 (1 bit)
CHENA : Channel enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-0 split control register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTADDR : Port address
bits : 0 - 6 (7 bit)
HUBADDR : Hub address
bits : 7 - 13 (7 bit)
XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)
COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)
SPLITEN : Split enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-11 interrupt register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : Transfer completed
bits : 0 - 0 (1 bit)
CHH : Channel halted
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERR : Transaction error
bits : 7 - 7 (1 bit)
BBERR : Babble error
bits : 8 - 8 (1 bit)
FRMOR : Frame overrun
bits : 9 - 9 (1 bit)
DTERR : Data toggle error
bits : 10 - 10 (1 bit)
OTG_HS host channel-11 interrupt mask register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)
CHHM : Channel halted mask
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)
NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)
ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)
NYET : response received interrupt mask
bits : 6 - 6 (1 bit)
TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)
BBERRM : Babble error mask
bits : 8 - 8 (1 bit)
FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)
DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)
OTG_HS host channel-11 transfer size register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)
PKTCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
OTG_HS host channel-0 DMA address register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
OTG_HS host channel-1 characteristics register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSDEV : Low-speed device
bits : 17 - 17 (1 bit)
EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)
DAD : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CHDIS : Channel disable
bits : 30 - 30 (1 bit)
CHENA : Channel enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-1 split control register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTADDR : Port address
bits : 0 - 6 (7 bit)
HUBADDR : Hub address
bits : 7 - 13 (7 bit)
XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)
COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)
SPLITEN : Split enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-1 interrupt register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : Transfer completed
bits : 0 - 0 (1 bit)
CHH : Channel halted
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERR : Transaction error
bits : 7 - 7 (1 bit)
BBERR : Babble error
bits : 8 - 8 (1 bit)
FRMOR : Frame overrun
bits : 9 - 9 (1 bit)
DTERR : Data toggle error
bits : 10 - 10 (1 bit)
OTG_HS host channel-1 interrupt mask register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)
CHHM : Channel halted mask
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)
NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)
ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)
NYET : response received interrupt mask
bits : 6 - 6 (1 bit)
TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)
BBERRM : Babble error mask
bits : 8 - 8 (1 bit)
FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)
DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)
OTG_HS host channel-1 transfer size register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)
PKTCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
OTG_HS host channel-1 DMA address register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
OTG_HS Host all channels interrupt register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HAINT : Channel interrupts
bits : 0 - 15 (16 bit)
OTG_HS host channel-2 characteristics register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSDEV : Low-speed device
bits : 17 - 17 (1 bit)
EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)
DAD : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CHDIS : Channel disable
bits : 30 - 30 (1 bit)
CHENA : Channel enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-2 split control register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTADDR : Port address
bits : 0 - 6 (7 bit)
HUBADDR : Hub address
bits : 7 - 13 (7 bit)
XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)
COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)
SPLITEN : Split enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-2 interrupt register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : Transfer completed
bits : 0 - 0 (1 bit)
CHH : Channel halted
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERR : Transaction error
bits : 7 - 7 (1 bit)
BBERR : Babble error
bits : 8 - 8 (1 bit)
FRMOR : Frame overrun
bits : 9 - 9 (1 bit)
DTERR : Data toggle error
bits : 10 - 10 (1 bit)
OTG_HS host channel-2 interrupt mask register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)
CHHM : Channel halted mask
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)
NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)
ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)
NYET : response received interrupt mask
bits : 6 - 6 (1 bit)
TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)
BBERRM : Babble error mask
bits : 8 - 8 (1 bit)
FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)
DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)
OTG_HS host channel-2 transfer size register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)
PKTCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
OTG_HS host channel-2 DMA address register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
OTG_HS host channel-3 characteristics register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSDEV : Low-speed device
bits : 17 - 17 (1 bit)
EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)
DAD : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CHDIS : Channel disable
bits : 30 - 30 (1 bit)
CHENA : Channel enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-3 split control register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTADDR : Port address
bits : 0 - 6 (7 bit)
HUBADDR : Hub address
bits : 7 - 13 (7 bit)
XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)
COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)
SPLITEN : Split enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-3 interrupt register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : Transfer completed
bits : 0 - 0 (1 bit)
CHH : Channel halted
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERR : Transaction error
bits : 7 - 7 (1 bit)
BBERR : Babble error
bits : 8 - 8 (1 bit)
FRMOR : Frame overrun
bits : 9 - 9 (1 bit)
DTERR : Data toggle error
bits : 10 - 10 (1 bit)
OTG_HS host channel-3 interrupt mask register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)
CHHM : Channel halted mask
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)
NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)
ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)
NYET : response received interrupt mask
bits : 6 - 6 (1 bit)
TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)
BBERRM : Babble error mask
bits : 8 - 8 (1 bit)
FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)
DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)
OTG_HS host channel-3 transfer size register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)
PKTCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
OTG_HS host channel-3 DMA address register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
OTG_HS host all channels interrupt mask register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HAINTM : Channel interrupt mask
bits : 0 - 15 (16 bit)
OTG_HS host channel-4 characteristics register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSDEV : Low-speed device
bits : 17 - 17 (1 bit)
EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)
DAD : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CHDIS : Channel disable
bits : 30 - 30 (1 bit)
CHENA : Channel enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-4 split control register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTADDR : Port address
bits : 0 - 6 (7 bit)
HUBADDR : Hub address
bits : 7 - 13 (7 bit)
XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)
COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)
SPLITEN : Split enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-4 interrupt register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : Transfer completed
bits : 0 - 0 (1 bit)
CHH : Channel halted
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERR : Transaction error
bits : 7 - 7 (1 bit)
BBERR : Babble error
bits : 8 - 8 (1 bit)
FRMOR : Frame overrun
bits : 9 - 9 (1 bit)
DTERR : Data toggle error
bits : 10 - 10 (1 bit)
OTG_HS host channel-4 interrupt mask register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)
CHHM : Channel halted mask
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)
NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)
ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)
NYET : response received interrupt mask
bits : 6 - 6 (1 bit)
TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)
BBERRM : Babble error mask
bits : 8 - 8 (1 bit)
FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)
DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)
OTG_HS host channel-4 transfer size register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)
PKTCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
OTG_HS host channel-4 DMA address register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
OTG_HS host channel-5 characteristics register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSDEV : Low-speed device
bits : 17 - 17 (1 bit)
EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)
DAD : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CHDIS : Channel disable
bits : 30 - 30 (1 bit)
CHENA : Channel enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-5 split control register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTADDR : Port address
bits : 0 - 6 (7 bit)
HUBADDR : Hub address
bits : 7 - 13 (7 bit)
XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)
COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)
SPLITEN : Split enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-5 interrupt register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : Transfer completed
bits : 0 - 0 (1 bit)
CHH : Channel halted
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERR : Transaction error
bits : 7 - 7 (1 bit)
BBERR : Babble error
bits : 8 - 8 (1 bit)
FRMOR : Frame overrun
bits : 9 - 9 (1 bit)
DTERR : Data toggle error
bits : 10 - 10 (1 bit)
OTG_HS host channel-5 interrupt mask register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)
CHHM : Channel halted mask
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)
NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)
ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)
NYET : response received interrupt mask
bits : 6 - 6 (1 bit)
TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)
BBERRM : Babble error mask
bits : 8 - 8 (1 bit)
FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)
DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)
OTG_HS host channel-5 transfer size register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)
PKTCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
OTG_HS host channel-5 DMA address register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
OTG_HS host channel-6 characteristics register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSDEV : Low-speed device
bits : 17 - 17 (1 bit)
EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)
DAD : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CHDIS : Channel disable
bits : 30 - 30 (1 bit)
CHENA : Channel enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-6 split control register
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTADDR : Port address
bits : 0 - 6 (7 bit)
HUBADDR : Hub address
bits : 7 - 13 (7 bit)
XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)
COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)
SPLITEN : Split enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-6 interrupt register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : Transfer completed
bits : 0 - 0 (1 bit)
CHH : Channel halted
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERR : Transaction error
bits : 7 - 7 (1 bit)
BBERR : Babble error
bits : 8 - 8 (1 bit)
FRMOR : Frame overrun
bits : 9 - 9 (1 bit)
DTERR : Data toggle error
bits : 10 - 10 (1 bit)
OTG_HS host channel-6 interrupt mask register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)
CHHM : Channel halted mask
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)
NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)
ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)
NYET : response received interrupt mask
bits : 6 - 6 (1 bit)
TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)
BBERRM : Babble error mask
bits : 8 - 8 (1 bit)
FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)
DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)
OTG_HS host channel-6 transfer size register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)
PKTCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
OTG_HS host channel-6 DMA address register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
OTG_HS host channel-7 characteristics register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSDEV : Low-speed device
bits : 17 - 17 (1 bit)
EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)
DAD : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CHDIS : Channel disable
bits : 30 - 30 (1 bit)
CHENA : Channel enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-7 split control register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTADDR : Port address
bits : 0 - 6 (7 bit)
HUBADDR : Hub address
bits : 7 - 13 (7 bit)
XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)
COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)
SPLITEN : Split enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-7 interrupt register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : Transfer completed
bits : 0 - 0 (1 bit)
CHH : Channel halted
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERR : Transaction error
bits : 7 - 7 (1 bit)
BBERR : Babble error
bits : 8 - 8 (1 bit)
FRMOR : Frame overrun
bits : 9 - 9 (1 bit)
DTERR : Data toggle error
bits : 10 - 10 (1 bit)
OTG_HS host channel-7 interrupt mask register
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)
CHHM : Channel halted mask
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)
NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)
ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)
NYET : response received interrupt mask
bits : 6 - 6 (1 bit)
TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)
BBERRM : Babble error mask
bits : 8 - 8 (1 bit)
FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)
DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)
OTG_HS host channel-7 transfer size register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)
PKTCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
OTG_HS host channel-7 DMA address register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
OTG_HS host channel-8 characteristics register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSDEV : Low-speed device
bits : 17 - 17 (1 bit)
EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)
DAD : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CHDIS : Channel disable
bits : 30 - 30 (1 bit)
CHENA : Channel enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-8 split control register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTADDR : Port address
bits : 0 - 6 (7 bit)
HUBADDR : Hub address
bits : 7 - 13 (7 bit)
XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)
COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)
SPLITEN : Split enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-8 interrupt register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : Transfer completed
bits : 0 - 0 (1 bit)
CHH : Channel halted
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERR : Transaction error
bits : 7 - 7 (1 bit)
BBERR : Babble error
bits : 8 - 8 (1 bit)
FRMOR : Frame overrun
bits : 9 - 9 (1 bit)
DTERR : Data toggle error
bits : 10 - 10 (1 bit)
OTG_HS host channel-8 interrupt mask register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)
CHHM : Channel halted mask
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)
NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)
ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)
NYET : response received interrupt mask
bits : 6 - 6 (1 bit)
TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)
BBERRM : Babble error mask
bits : 8 - 8 (1 bit)
FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)
DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)
OTG_HS host channel-8 transfer size register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)
PKTCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
OTG_HS host channel-8 DMA address register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
OTG_HS host channel-9 characteristics register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSDEV : Low-speed device
bits : 17 - 17 (1 bit)
EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)
DAD : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CHDIS : Channel disable
bits : 30 - 30 (1 bit)
CHENA : Channel enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-9 split control register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTADDR : Port address
bits : 0 - 6 (7 bit)
HUBADDR : Hub address
bits : 7 - 13 (7 bit)
XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)
COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)
SPLITEN : Split enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-9 interrupt register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : Transfer completed
bits : 0 - 0 (1 bit)
CHH : Channel halted
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERR : Transaction error
bits : 7 - 7 (1 bit)
BBERR : Babble error
bits : 8 - 8 (1 bit)
FRMOR : Frame overrun
bits : 9 - 9 (1 bit)
DTERR : Data toggle error
bits : 10 - 10 (1 bit)
OTG_HS host channel-9 interrupt mask register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)
CHHM : Channel halted mask
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)
NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)
ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)
NYET : response received interrupt mask
bits : 6 - 6 (1 bit)
TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)
BBERRM : Babble error mask
bits : 8 - 8 (1 bit)
FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)
DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)
OTG_HS host channel-9 transfer size register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)
PKTCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
OTG_HS host channel-9 DMA address register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
OTG_HS host channel-10 characteristics register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSDEV : Low-speed device
bits : 17 - 17 (1 bit)
EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)
DAD : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CHDIS : Channel disable
bits : 30 - 30 (1 bit)
CHENA : Channel enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-10 split control register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTADDR : Port address
bits : 0 - 6 (7 bit)
HUBADDR : Hub address
bits : 7 - 13 (7 bit)
XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)
COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)
SPLITEN : Split enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-10 interrupt register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : Transfer completed
bits : 0 - 0 (1 bit)
CHH : Channel halted
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERR : Transaction error
bits : 7 - 7 (1 bit)
BBERR : Babble error
bits : 8 - 8 (1 bit)
FRMOR : Frame overrun
bits : 9 - 9 (1 bit)
DTERR : Data toggle error
bits : 10 - 10 (1 bit)
OTG_HS host channel-10 interrupt mask register
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)
CHHM : Channel halted mask
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)
NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)
ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)
NYET : response received interrupt mask
bits : 6 - 6 (1 bit)
TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)
BBERRM : Babble error mask
bits : 8 - 8 (1 bit)
FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)
DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)
OTG_HS host channel-10 transfer size register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)
PKTCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
OTG_HS host channel-10 DMA address register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
OTG_HS host channel-11 characteristics register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSDEV : Low-speed device
bits : 17 - 17 (1 bit)
EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)
DAD : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CHDIS : Channel disable
bits : 30 - 30 (1 bit)
CHENA : Channel enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-11 split control register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTADDR : Port address
bits : 0 - 6 (7 bit)
HUBADDR : Hub address
bits : 7 - 13 (7 bit)
XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)
COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)
SPLITEN : Split enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-11 interrupt register
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : Transfer completed
bits : 0 - 0 (1 bit)
CHH : Channel halted
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERR : Transaction error
bits : 7 - 7 (1 bit)
BBERR : Babble error
bits : 8 - 8 (1 bit)
FRMOR : Frame overrun
bits : 9 - 9 (1 bit)
DTERR : Data toggle error
bits : 10 - 10 (1 bit)
OTG_HS host channel-11 interrupt mask register
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)
CHHM : Channel halted mask
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)
NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)
ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)
NYET : response received interrupt mask
bits : 6 - 6 (1 bit)
TXERRM : Transaction error mask
bits : 7 - 7 (1 bit)
BBERRM : Babble error mask
bits : 8 - 8 (1 bit)
FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)
DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)
OTG_HS host channel-11 transfer size register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)
PKTCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
OTG_HS host channel-11 DMA address register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
OTG_HS host channel-12 characteristics register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSDEV : Low-speed device
bits : 17 - 17 (1 bit)
EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)
DAD : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CHDIS : Channel disable
bits : 30 - 30 (1 bit)
CHENA : Channel enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-12 split control register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTADDR : Port address
bits : 0 - 6 (7 bit)
HUBADDR : Hub address
bits : 7 - 13 (7 bit)
XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)
COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)
SPLITEN : Split enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-12 interrupt register
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : Transfer completed
bits : 0 - 0 (1 bit)
CHH : Channel halted
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERR : Transaction error
bits : 7 - 7 (1 bit)
BBERR : Babble error
bits : 8 - 8 (1 bit)
FRMOR : Frame overrun
bits : 9 - 9 (1 bit)
DTERR : Data toggle error
bits : 10 - 10 (1 bit)
OTG_HS host channel-12 interrupt mask register
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)
CHHM : Channel halted mask
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)
NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)
ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERRM : Transaction error
bits : 7 - 7 (1 bit)
BBERRM : Babble error
bits : 8 - 8 (1 bit)
FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)
DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)
OTG_HS host channel-12 transfer size register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)
PKTCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
OTG_HS host channel-12 DMA address register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
OTG_HS host channel-13 characteristics register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSDEV : Low-speed device
bits : 17 - 17 (1 bit)
EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)
DAD : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CHDIS : Channel disable
bits : 30 - 30 (1 bit)
CHENA : Channel enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-13 split control register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTADDR : Port address
bits : 0 - 6 (7 bit)
HUBADDR : Hub address
bits : 7 - 13 (7 bit)
XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)
COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)
SPLITEN : Split enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-13 interrupt register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : Transfer completed
bits : 0 - 0 (1 bit)
CHH : Channel halted
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERR : Transaction error
bits : 7 - 7 (1 bit)
BBERR : Babble error
bits : 8 - 8 (1 bit)
FRMOR : Frame overrun
bits : 9 - 9 (1 bit)
DTERR : Data toggle error
bits : 10 - 10 (1 bit)
OTG_HS host channel-13 interrupt mask register
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)
CHHM : Channel halted mask
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALLM : STALLM response received interrupt mask
bits : 3 - 3 (1 bit)
NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)
ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERRM : Transaction error
bits : 7 - 7 (1 bit)
BBERRM : Babble error
bits : 8 - 8 (1 bit)
FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)
DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)
OTG_HS host channel-13 transfer size register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)
PKTCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
OTG_HS host channel-13 DMA address register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
OTG_HS host channel-14 characteristics register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSDEV : Low-speed device
bits : 17 - 17 (1 bit)
EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)
DAD : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CHDIS : Channel disable
bits : 30 - 30 (1 bit)
CHENA : Channel enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-14 split control register
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTADDR : Port address
bits : 0 - 6 (7 bit)
HUBADDR : Hub address
bits : 7 - 13 (7 bit)
XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)
COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)
SPLITEN : Split enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-14 interrupt register
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : Transfer completed
bits : 0 - 0 (1 bit)
CHH : Channel halted
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERR : Transaction error
bits : 7 - 7 (1 bit)
BBERR : Babble error
bits : 8 - 8 (1 bit)
FRMOR : Frame overrun
bits : 9 - 9 (1 bit)
DTERR : Data toggle error
bits : 10 - 10 (1 bit)
OTG_HS host channel-14 interrupt mask register
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)
CHHM : Channel halted mask
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALLM : STALL response received interrupt mask
bits : 3 - 3 (1 bit)
NAKM : NAKM response received interrupt mask
bits : 4 - 4 (1 bit)
ACKM : ACKM response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERRM : Transaction error
bits : 7 - 7 (1 bit)
BBERRM : Babble error
bits : 8 - 8 (1 bit)
FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)
DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)
OTG_HS host channel-14 transfer size register
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)
PKTCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
OTG_HS host channel-14 DMA address register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
OTG_HS host channel-15 characteristics register
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPSIZ : Maximum packet size
bits : 0 - 10 (11 bit)
EPNUM : Endpoint number
bits : 11 - 14 (4 bit)
EPDIR : Endpoint direction
bits : 15 - 15 (1 bit)
LSDEV : Low-speed device
bits : 17 - 17 (1 bit)
EPTYP : Endpoint type
bits : 18 - 19 (2 bit)
MC : Multi Count (MC) / Error Count (EC)
bits : 20 - 21 (2 bit)
DAD : Device address
bits : 22 - 28 (7 bit)
ODDFRM : Odd frame
bits : 29 - 29 (1 bit)
CHDIS : Channel disable
bits : 30 - 30 (1 bit)
CHENA : Channel enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-15 split control register
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTADDR : Port address
bits : 0 - 6 (7 bit)
HUBADDR : Hub address
bits : 7 - 13 (7 bit)
XACTPOS : XACTPOS
bits : 14 - 15 (2 bit)
COMPLSPLT : Do complete split
bits : 16 - 16 (1 bit)
SPLITEN : Split enable
bits : 31 - 31 (1 bit)
OTG_HS host channel-15 interrupt register
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRC : Transfer completed
bits : 0 - 0 (1 bit)
CHH : Channel halted
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt
bits : 3 - 3 (1 bit)
NAK : NAK response received interrupt
bits : 4 - 4 (1 bit)
ACK : ACK response received/transmitted interrupt
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERR : Transaction error
bits : 7 - 7 (1 bit)
BBERR : Babble error
bits : 8 - 8 (1 bit)
FRMOR : Frame overrun
bits : 9 - 9 (1 bit)
DTERR : Data toggle error
bits : 10 - 10 (1 bit)
OTG_HS host channel-15 interrupt mask register
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRCM : Transfer completed mask
bits : 0 - 0 (1 bit)
CHHM : Channel halted mask
bits : 1 - 1 (1 bit)
AHBERR : AHB error
bits : 2 - 2 (1 bit)
STALL : STALL response received interrupt mask
bits : 3 - 3 (1 bit)
NAKM : NAK response received interrupt mask
bits : 4 - 4 (1 bit)
ACKM : ACK response received/transmitted interrupt mask
bits : 5 - 5 (1 bit)
NYET : Response received interrupt
bits : 6 - 6 (1 bit)
TXERRM : Transaction error
bits : 7 - 7 (1 bit)
BBERRM : Babble error
bits : 8 - 8 (1 bit)
FRMORM : Frame overrun mask
bits : 9 - 9 (1 bit)
DTERRM : Data toggle error mask
bits : 10 - 10 (1 bit)
OTG_HS host channel-15 transfer size register
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFRSIZ : Transfer size
bits : 0 - 18 (19 bit)
PKTCNT : Packet count
bits : 19 - 28 (10 bit)
DPID : Data PID
bits : 29 - 30 (2 bit)
OTG_HS host channel-15 DMA address register
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA address
bits : 0 - 31 (32 bit)
OTG_HS Host frame interval register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRIVL : Frame interval
bits : 0 - 15 (16 bit)
OTG_HS host port control and status register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCSTS : Port connect status
bits : 0 - 0 (1 bit)
access : read-only
PCDET : Port connect detected
bits : 1 - 1 (1 bit)
access : read-write
PENA : Port enable
bits : 2 - 2 (1 bit)
access : read-write
PENCHNG : Port enable/disable change
bits : 3 - 3 (1 bit)
access : read-write
POCA : Port overcurrent active
bits : 4 - 4 (1 bit)
access : read-only
POCCHNG : Port overcurrent change
bits : 5 - 5 (1 bit)
access : read-write
PRES : Port resume
bits : 6 - 6 (1 bit)
access : read-write
PSUSP : Port suspend
bits : 7 - 7 (1 bit)
access : read-write
PRST : Port reset
bits : 8 - 8 (1 bit)
access : read-write
PLSTS : Port line status
bits : 10 - 11 (2 bit)
access : read-only
PPWR : Port power
bits : 12 - 12 (1 bit)
access : read-write
PTCTL : Port test control
bits : 13 - 16 (4 bit)
access : read-write
PSPD : Port speed
bits : 17 - 18 (2 bit)
access : read-only
OTG_HS host frame number/frame time remaining register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRNUM : Frame number
bits : 0 - 15 (16 bit)
FTREM : Frame time remaining
bits : 16 - 31 (16 bit)
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