CR

AHB1RSTR

AHB2RSTR

AHB3RSTR

APB1RSTR

APB2RSTR

AHB1ENR

AHB2ENR

AHB3ENR

PLLCFGR

APB1ENR

APB2ENR

AHB1LPENR

AHB2LPENR

AHB3LPENR

APB1LPENR

APB2LPENR

BDCR

CSR

CFGR

SSCGR

PLLI2SCFGR

DCKCFGR

CKGATENR

DCKCFGR2

CIR

HSION : Internal high-speed clock enable
bits : 0 - 0 (1 bit)

HSIRDY : Internal high-speed clock ready flag
bits : 1 - 1 (1 bit)

HSITRIM : Internal high-speed clock trimming
bits : 3 - 7 (5 bit)

HSICAL : Internal high-speed clock calibration
bits : 8 - 15 (8 bit)

HSEON : HSE clock enable
bits : 16 - 16 (1 bit)

HSERDY : HSE clock ready flag
bits : 17 - 17 (1 bit)

HSEBYP : HSE clock bypass
bits : 18 - 18 (1 bit)

CSSON : Clock security system enable
bits : 19 - 19 (1 bit)

PLLON : Main PLL (PLL) enable
bits : 24 - 24 (1 bit)

PLLRDY : Main PLL (PLL) clock ready flag
bits : 25 - 25 (1 bit)

PLLI2SON : PLLI2S enable
bits : 26 - 26 (1 bit)

PLLI2SRDY : PLLI2S clock ready flag
bits : 27 - 27 (1 bit)

GPIOARST : IO port A reset
bits : 0 - 0 (1 bit)

GPIOBRST : IO port B reset
bits : 1 - 1 (1 bit)

GPIOCRST : IO port C reset
bits : 2 - 2 (1 bit)

GPIODRST : IO port D reset
bits : 3 - 3 (1 bit)

GPIOERST : IO port E reset
bits : 4 - 4 (1 bit)

GPIOFRST : IO port F reset
bits : 5 - 5 (1 bit)

GPIOGRST : IO port G reset
bits : 6 - 6 (1 bit)

GPIOHRST : IO port H reset
bits : 7 - 7 (1 bit)

CRCRST : CRC reset
bits : 12 - 12 (1 bit)

DMA1RST : DMA2 reset
bits : 21 - 21 (1 bit)

DMA2RST : DMA2 reset
bits : 22 - 22 (1 bit)

CRYPRST : CRYP module reset
bits : 4 - 4 (1 bit)

RNGRST : RNGRST
bits : 6 - 6 (1 bit)

OTGFSRST : USB OTG FS module reset
bits : 7 - 7 (1 bit)

FSMCRST : Flexible memory controller module reset
bits : 0 - 0 (1 bit)

QSPIRST : QUADSPI module reset
bits : 1 - 1 (1 bit)

TIM2RST : TIM2 reset
bits : 0 - 0 (1 bit)

TIM3RST : TIM3 reset
bits : 1 - 1 (1 bit)

TIM4RST : TIM4 reset
bits : 2 - 2 (1 bit)

TIM5RST : TIM5 reset
bits : 3 - 3 (1 bit)

TIM6RST : TIM6RST
bits : 4 - 4 (1 bit)

TIM7RST : TIM7RST
bits : 5 - 5 (1 bit)

TIM12RST : TIM12RST
bits : 6 - 6 (1 bit)

TIM13RST : TIM13RST
bits : 7 - 7 (1 bit)

TIM14RST : TIM14RST
bits : 8 - 8 (1 bit)

LPTIMER1RST : LPTimer1 reset
bits : 9 - 9 (1 bit)

WWDGRST : Window watchdog reset
bits : 11 - 11 (1 bit)

SPI2RST : SPI 2 reset
bits : 14 - 14 (1 bit)

SPI3RST : SPI 3 reset
bits : 15 - 15 (1 bit)

UART2RST : USART 2 reset
bits : 17 - 17 (1 bit)

USART3RST : USART3RST
bits : 18 - 18 (1 bit)

USART4RST : USART4 reset
bits : 19 - 19 (1 bit)

USART5RST : USART5 reset
bits : 20 - 20 (1 bit)

I2C1RST : I2C 1 reset
bits : 21 - 21 (1 bit)

I2C2RST : I2C 2 reset
bits : 22 - 22 (1 bit)

I2C3RST : I2C3 reset
bits : 23 - 23 (1 bit)

I2C4RST : I2C4RST
bits : 24 - 24 (1 bit)

CAN1RST : CAN1RST
bits : 25 - 25 (1 bit)

CAN2RST : CAN2RST
bits : 26 - 26 (1 bit)

CAN3RST : CAN 3 reset
bits : 27 - 27 (1 bit)

PWRRST : Power interface reset
bits : 28 - 28 (1 bit)

DACRST : DAC reset
bits : 29 - 29 (1 bit)

UART7RST : UART 7 reset
bits : 30 - 30 (1 bit)

UART8RST : UART 8 reset
bits : 31 - 31 (1 bit)

TIM1RST : TIM1 reset
bits : 0 - 0 (1 bit)

TIM8RST : TIM8RST
bits : 1 - 1 (1 bit)

USART1RST : USART1 reset
bits : 4 - 4 (1 bit)

USART6RST : USART6 reset
bits : 5 - 5 (1 bit)

USART9RST : USART9 reset
bits : 6 - 6 (1 bit)

SART10RST : USART10 reset
bits : 7 - 7 (1 bit)

ADCRST : ADC interface reset (common to all ADCs)
bits : 8 - 8 (1 bit)

SDIORST : SDIO reset
bits : 11 - 11 (1 bit)

SPI1RST : SPI 1 reset
bits : 12 - 12 (1 bit)

SPI4RST : SPI4 reset
bits : 13 - 13 (1 bit)

SYSCFGRST : System configuration controller reset
bits : 14 - 14 (1 bit)

TIM9RST : TIM9 reset
bits : 16 - 16 (1 bit)

TIM10RST : TIM10 reset
bits : 17 - 17 (1 bit)

TIM11RST : TIM11 reset
bits : 18 - 18 (1 bit)

SPI5RST : SPI5RST
bits : 20 - 20 (1 bit)

SAI1RST : SAI1 reset
bits : 22 - 22 (1 bit)

DFSDMRST : DFSDMRST
bits : 24 - 24 (1 bit)

DFSDM2RST : DFSDM2 reset
bits : 25 - 25 (1 bit)

GPIOAEN : IO port A clock enable
bits : 0 - 0 (1 bit)

GPIOBEN : IO port B clock enable
bits : 1 - 1 (1 bit)

GPIOCEN : IO port C clock enable
bits : 2 - 2 (1 bit)

GPIODEN : IO port D clock enable
bits : 3 - 3 (1 bit)

GPIOEEN : IO port E clock enable
bits : 4 - 4 (1 bit)

GPIOFEN : IO port F clock enable
bits : 5 - 5 (1 bit)

GPIOGEN : IO port G clock enable
bits : 6 - 6 (1 bit)

GPIOHEN : IO port H clock enable
bits : 7 - 7 (1 bit)

CRCEN : CRC clock enable
bits : 12 - 12 (1 bit)

DMA1EN : DMA1 clock enable
bits : 21 - 21 (1 bit)

DMA2EN : DMA2 clock enable
bits : 22 - 22 (1 bit)

CRYPEN : CRYP clock enable
bits : 4 - 4 (1 bit)

RNGEN : RNGEN
bits : 6 - 6 (1 bit)

OTGFSEN : USB OTG FS clock enable
bits : 7 - 7 (1 bit)

FSMCEN : Flexible memory controller module clock enable
bits : 0 - 0 (1 bit)

QSPIEN : QUADSPI memory controller module clock enable
bits : 1 - 1 (1 bit)

PLLM0 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 0 - 0 (1 bit)

PLLM1 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 1 - 1 (1 bit)

PLLM2 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 2 - 2 (1 bit)

PLLM3 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 3 - 3 (1 bit)

PLLM4 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 4 - 4 (1 bit)

PLLM5 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 5 - 5 (1 bit)

PLLN0 : Main PLL (PLL) multiplication factor for VCO
bits : 6 - 6 (1 bit)

PLLN1 : Main PLL (PLL) multiplication factor for VCO
bits : 7 - 7 (1 bit)

PLLN2 : Main PLL (PLL) multiplication factor for VCO
bits : 8 - 8 (1 bit)

PLLN3 : Main PLL (PLL) multiplication factor for VCO
bits : 9 - 9 (1 bit)

PLLN4 : Main PLL (PLL) multiplication factor for VCO
bits : 10 - 10 (1 bit)

PLLN5 : Main PLL (PLL) multiplication factor for VCO
bits : 11 - 11 (1 bit)

PLLN6 : Main PLL (PLL) multiplication factor for VCO
bits : 12 - 12 (1 bit)

PLLN7 : Main PLL (PLL) multiplication factor for VCO
bits : 13 - 13 (1 bit)

PLLN8 : Main PLL (PLL) multiplication factor for VCO
bits : 14 - 14 (1 bit)

PLLP0 : Main PLL (PLL) division factor for main system clock
bits : 16 - 16 (1 bit)

PLLP1 : Main PLL (PLL) division factor for main system clock
bits : 17 - 17 (1 bit)

PLLSRC : Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
bits : 22 - 22 (1 bit)

PLLQ0 : Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
bits : 24 - 24 (1 bit)

PLLQ1 : Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
bits : 25 - 25 (1 bit)

PLLQ2 : Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
bits : 26 - 26 (1 bit)

PLLQ3 : Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
bits : 27 - 27 (1 bit)

PLLR : Main PLL (PLL) division factor for I2S, DFSDM clocks
bits : 28 - 30 (3 bit)

TIM2EN : TIM2 clock enable
bits : 0 - 0 (1 bit)

TIM3EN : TIM3 clock enable
bits : 1 - 1 (1 bit)

TIM4EN : TIM4 clock enable
bits : 2 - 2 (1 bit)

TIM5EN : TIM5 clock enable
bits : 3 - 3 (1 bit)

TIM6EN : TIM6EN
bits : 4 - 4 (1 bit)

TIM7EN : TIM7EN
bits : 5 - 5 (1 bit)

TIM12EN : TIM12EN
bits : 6 - 6 (1 bit)

TIM13EN : TIM13EN
bits : 7 - 7 (1 bit)

TIM14EN : TIM14EN
bits : 8 - 8 (1 bit)

LPTIMER1EN : LPTimer 1 clock enable
bits : 9 - 9 (1 bit)

RTCAPB : clock enable
bits : 10 - 10 (1 bit)

WWDGEN : Window watchdog clock enable
bits : 11 - 11 (1 bit)

SPI2EN : SPI2 clock enable
bits : 14 - 14 (1 bit)

SPI3EN : SPI3 clock enable
bits : 15 - 15 (1 bit)

USART2EN : USART 2 clock enable
bits : 17 - 17 (1 bit)

USART3EN : USART3EN
bits : 18 - 18 (1 bit)

UART4EN : UART 4 clock enable
bits : 19 - 19 (1 bit)

UART5EN : UART 5 clock enable
bits : 20 - 20 (1 bit)

I2C1EN : I2C1 clock enable
bits : 21 - 21 (1 bit)

I2C2EN : I2C2 clock enable
bits : 22 - 22 (1 bit)

I2C3EN : I2C3 clock enable
bits : 23 - 23 (1 bit)

I2C4EN : I2C4EN
bits : 24 - 24 (1 bit)

CAN1EN : CAN1EN
bits : 25 - 25 (1 bit)

CAN2EN : CAN2EN
bits : 26 - 26 (1 bit)

CAN3EN : CAN 3 clock enable
bits : 27 - 27 (1 bit)

PWREN : Power interface clock enable
bits : 28 - 28 (1 bit)

DACEN : DAC clock enable
bits : 29 - 29 (1 bit)

UART7EN : UART7 clock enable
bits : 30 - 30 (1 bit)

UART8EN : UART8 clock enable
bits : 31 - 31 (1 bit)

TIM1EN : TIM1 clock enable
bits : 0 - 0 (1 bit)

TIM8EN : TIM8EN
bits : 1 - 1 (1 bit)

USART1EN : USART1 clock enable
bits : 4 - 4 (1 bit)

USART6EN : USART6 clock enable
bits : 5 - 5 (1 bit)

ADC1EN : ADC1 clock enable
bits : 8 - 8 (1 bit)

SDIOEN : SDIO clock enable
bits : 11 - 11 (1 bit)

SPI1EN : SPI1 clock enable
bits : 12 - 12 (1 bit)

SPI4EN : SPI4 clock enable
bits : 13 - 13 (1 bit)

SYSCFGEN : System configuration controller clock enable
bits : 14 - 14 (1 bit)

TIM9EN : TIM9 clock enable
bits : 16 - 16 (1 bit)

TIM10EN : TIM10 clock enable
bits : 17 - 17 (1 bit)

TIM11EN : TIM11 clock enable
bits : 18 - 18 (1 bit)

SPI5EN : SPI5 clock enable
bits : 20 - 20 (1 bit)

SAI1EN : SAI 1 clock enable
bits : 22 - 22 (1 bit)

DFSDMEN : DFSDMEN
bits : 24 - 24 (1 bit)

DFSDM2EN : DFSDM2 clock enable
bits : 25 - 25 (1 bit)

GPIOALPEN : IO port A clock enable during sleep mode
bits : 0 - 0 (1 bit)

GPIOBLPEN : IO port B clock enable during Sleep mode
bits : 1 - 1 (1 bit)

GPIOCLPEN : IO port C clock enable during Sleep mode
bits : 2 - 2 (1 bit)

GPIODLPEN : IO port D clock enable during Sleep mode
bits : 3 - 3 (1 bit)

GPIOELPEN : IO port E clock enable during Sleep mode
bits : 4 - 4 (1 bit)

GPIOFLPEN : IO port F clock enable during sleep mode
bits : 5 - 5 (1 bit)

GPIOGLPEN : IO port G clock enable during sleep mode
bits : 6 - 6 (1 bit)

GPIOHLPEN : IO port H clock enable during Sleep mode
bits : 7 - 7 (1 bit)

CRCLPEN : CRC clock enable during Sleep mode
bits : 12 - 12 (1 bit)

FLITFLPEN : Flash interface clock enable during Sleep mode
bits : 15 - 15 (1 bit)

SRAM1LPEN : SRAM 1interface clock enable during Sleep mode
bits : 16 - 16 (1 bit)

SRAM2LPEN : SRAM2interface clock enable during Sleep mode
bits : 17 - 17 (1 bit)

DMA1LPEN : DMA1 clock enable during Sleep mode
bits : 21 - 21 (1 bit)

DMA2LPEN : DMA2 clock enable during Sleep mode
bits : 22 - 22 (1 bit)

FSMCLPEN : Flexible memory controller module clock enable during Sleep mode
bits : 0 - 0 (1 bit)

QSPILPEN : QUADSPI memory controller module clock enable during Sleep mode
bits : 1 - 1 (1 bit)

RNGLPEN : RNGLPEN
bits : 6 - 6 (1 bit)

OTGFSLPEN : USB OTG FS clock enable during Sleep mode
bits : 7 - 7 (1 bit)

FSMCLPEN : Flexible memory controller module clock enable during Sleep mode
bits : 0 - 0 (1 bit)

QSPILPEN : QUADSPI memory controller module clock enable during Sleep mode
bits : 1 - 1 (1 bit)

TIM2LPEN : TIM2 clock enable during Sleep mode
bits : 0 - 0 (1 bit)

TIM3LPEN : TIM3 clock enable during Sleep mode
bits : 1 - 1 (1 bit)

TIM4LPEN : TIM4 clock enable during Sleep mode
bits : 2 - 2 (1 bit)

TIM5LPEN : TIM5 clock enable during Sleep mode
bits : 3 - 3 (1 bit)

TIM6LPEN : TIM6LPEN
bits : 4 - 4 (1 bit)

TIM7LPEN : TIM7LPEN
bits : 5 - 5 (1 bit)

TIM12LPEN : TIM12LPEN
bits : 6 - 6 (1 bit)

TIM13LPEN : TIM13LPEN
bits : 7 - 7 (1 bit)

TIM14LPEN : TIM14LPEN
bits : 8 - 8 (1 bit)

LPTIMER1LPEN : TIM14 clock enable during Sleep mode
bits : 9 - 9 (1 bit)

RTCAPBEN : RTC APB clock enable during Sleep mode
bits : 10 - 10 (1 bit)

WWDGLPEN : Window watchdog clock enable during Sleep mode
bits : 11 - 11 (1 bit)

SPI2LPEN : SPI2 clock enable during Sleep mode
bits : 14 - 14 (1 bit)

SPI3LPEN : SPI3 clock enable during Sleep mode
bits : 15 - 15 (1 bit)

USART2LPEN : USART2 clock enable during Sleep mode
bits : 17 - 17 (1 bit)

USART3LPEN : USART3LPEN
bits : 18 - 18 (1 bit)

USART4LPEN : USART4 clock enable during Sleep mode
bits : 19 - 19 (1 bit)

USART5LPEN : USART5 clock enable during Sleep mode
bits : 20 - 20 (1 bit)

I2C1LPEN : I2C1 clock enable during Sleep mode
bits : 21 - 21 (1 bit)

I2C2LPEN : I2C2 clock enable during Sleep mode
bits : 22 - 22 (1 bit)

I2C3LPEN : I2C3 clock enable during Sleep mode
bits : 23 - 23 (1 bit)

I2C4LPEN : I2C4LPEN
bits : 24 - 24 (1 bit)

CAN1LPEN : CAN1LPEN
bits : 25 - 25 (1 bit)

CAN2LPEN : CAN2LPEN
bits : 26 - 26 (1 bit)

CAN3LPEN : CAN3 clock enable during Sleep mode
bits : 27 - 27 (1 bit)

PWRLPEN : Power interface clock enable during Sleep mode
bits : 28 - 28 (1 bit)

DACLPEN : DAC clock enable during Sleep mode
bits : 29 - 29 (1 bit)

UART7LPEN : UART7 clock enable during Sleep mode
bits : 30 - 30 (1 bit)

UART8LPEN : UART8 clock enable during Sleep mode
bits : 31 - 31 (1 bit)

TIM1LPEN : TIM1 clock enable during Sleep mode
bits : 0 - 0 (1 bit)

TIM8LPEN : TIM8LPEN
bits : 1 - 1 (1 bit)

USART1LPEN : USART1 clock enable during Sleep mode
bits : 4 - 4 (1 bit)

USART6LPEN : USART6 clock enable during Sleep mode
bits : 5 - 5 (1 bit)

USART9LPEN : USART9 clock enable during Sleep mode
bits : 6 - 6 (1 bit)

USART10LPEN : USART10 clock enable during Sleep mode
bits : 7 - 7 (1 bit)

ADC1LPEN : ADC1 clock enable during Sleep mode
bits : 8 - 8 (1 bit)

SDIOLPEN : SDIO clock enable during Sleep mode
bits : 11 - 11 (1 bit)

SPI1LPEN : SPI 1 clock enable during Sleep mode
bits : 12 - 12 (1 bit)

SPI4LPEN : SPI4 clock enable during Sleep mode
bits : 13 - 13 (1 bit)

SYSCFGLPEN : System configuration controller clock enable during Sleep mode
bits : 14 - 14 (1 bit)

EXTITEN : EXTIT APB and SYSCTRL PFREE clock enable during Sleep mode
bits : 15 - 15 (1 bit)

TIM9LPEN : TIM9 clock enable during sleep mode
bits : 16 - 16 (1 bit)

TIM10LPEN : TIM10 clock enable during Sleep mode
bits : 17 - 17 (1 bit)

TIM11LPEN : TIM11 clock enable during Sleep mode
bits : 18 - 18 (1 bit)

SPI5LPEN : SPI5 clock enable during Sleep mode
bits : 20 - 20 (1 bit)

SAI1LPEN : SAI1 clock enable during Sleep mode
bits : 22 - 22 (1 bit)

DFSDMLPEN : DFSDMLPEN
bits : 24 - 24 (1 bit)

DFSDM2LPEN : DFSDM2 clock enable during Sleep mode
bits : 25 - 25 (1 bit)

LSEON : External low-speed oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSERDY : External low-speed oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

LSEBYP : External low-speed oscillator bypass
bits : 2 - 2 (1 bit)
access : read-write

LSEMOD : External low-speed oscillator bypass
bits : 3 - 3 (1 bit)
access : read-write

RTCSEL0 : RTC clock source selection
bits : 8 - 8 (1 bit)
access : read-write

RTCSEL1 : RTC clock source selection
bits : 9 - 9 (1 bit)
access : read-write

RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write

BDRST : Backup domain software reset
bits : 16 - 16 (1 bit)
access : read-write

LSION : Internal low-speed oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSIRDY : Internal low-speed oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

RMVF : Remove reset flag
bits : 24 - 24 (1 bit)
access : read-write

BORRSTF : BOR reset flag
bits : 25 - 25 (1 bit)
access : read-write

PADRSTF : PIN reset flag
bits : 26 - 26 (1 bit)
access : read-write

PORRSTF : POR/PDR reset flag
bits : 27 - 27 (1 bit)
access : read-write

SFTRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-write

WDGRSTF : Independent watchdog reset flag
bits : 29 - 29 (1 bit)
access : read-write

WWDGRSTF : Window watchdog reset flag
bits : 30 - 30 (1 bit)
access : read-write

LPWRRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-write

SW0 : System clock switch
bits : 0 - 0 (1 bit)
access : read-write

SW1 : System clock switch
bits : 1 - 1 (1 bit)
access : read-write

SWS0 : System clock switch status
bits : 2 - 2 (1 bit)
access : read-only

SWS1 : System clock switch status
bits : 3 - 3 (1 bit)
access : read-only

HPRE : AHB prescaler
bits : 4 - 7 (4 bit)
access : read-write

PPRE1 : APB Low speed prescaler (APB1)
bits : 10 - 12 (3 bit)
access : read-write

PPRE2 : APB high-speed prescaler (APB2)
bits : 13 - 15 (3 bit)
access : read-write

RTCPRE : HSE division factor for RTC clock
bits : 16 - 20 (5 bit)
access : read-write

MCO1 : Microcontroller clock output 1
bits : 21 - 22 (2 bit)
access : read-write

MCO1PRE : MCO1 prescaler
bits : 24 - 26 (3 bit)
access : read-write

MCO2PRE : MCO2 prescaler
bits : 27 - 29 (3 bit)
access : read-write

MCO2 : Microcontroller clock output 2
bits : 30 - 31 (2 bit)
access : read-write

MODPER : Modulation period
bits : 0 - 12 (13 bit)

INCSTEP : Incrementation step
bits : 13 - 27 (15 bit)

SPREADSEL : Spread Select
bits : 30 - 30 (1 bit)

SSCGEN : Spread spectrum modulation enable
bits : 31 - 31 (1 bit)

PLLI2SM : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 0 - 5 (6 bit)

PLLI2SN : PLLI2S multiplication factor for VCO
bits : 6 - 14 (9 bit)

PLLI2SSRC : PLLI2S entry clock source
bits : 22 - 22 (1 bit)

PLLI2SQ : PLLI2S division factor for USB OTG FS/SDIO/RNG clock
bits : 24 - 27 (4 bit)

PLLI2SR : PLLI2S division factor for I2S clocks
bits : 28 - 30 (3 bit)

CKDFSDM1ASEL : DFSDM1 audio clock selection.
bits : 15 - 15 (1 bit)

TIMPRE : Timers clocks prescalers selection
bits : 24 - 24 (1 bit)

I2S1SRC : I2S APB1 clocks source selection (I2S2/3)
bits : 25 - 26 (2 bit)

I2S2SRC : I2S APB2 clocks source selection (I2S1/4/5)
bits : 27 - 28 (2 bit)

LPTIMER1SEL : LPTIMER1 kernel clock selection.
bits : 30 - 31 (2 bit)

AHB2APB1_CKEN : AHB to APB1 Bridge clock enable
bits : 0 - 0 (1 bit)

AHB2APB2_CKEN : AHB to APB2 Bridge clock enable
bits : 1 - 1 (1 bit)

CM4DBG_CKEN : Cortex M4 ETM clock enable
bits : 2 - 2 (1 bit)

SPARE_CKEN : Spare clock enable
bits : 3 - 3 (1 bit)

SRAM_CKEN : SRQAM controller clock enable
bits : 4 - 4 (1 bit)

FLITF_CKEN : Flash Interface clock enable
bits : 5 - 5 (1 bit)

RCC_CKEN : RCC clock enable
bits : 6 - 6 (1 bit)

EVTCL_CKEN : EVTCL_CKEN
bits : 7 - 7 (1 bit)

I2CFMP1SEL : I2CFMP1 kernel clock source selection
bits : 22 - 22 (1 bit)

CK48MSEL : SDIO/USBFS clock selection.
bits : 27 - 27 (1 bit)

CKSDIOSEL : SDIO clock selection.
bits : 28 - 28 (1 bit)

LSIRDYF : LSI ready interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

LSERDYF : LSE ready interrupt flag
bits : 1 - 1 (1 bit)
access : read-only

HSIRDYF : HSI ready interrupt flag
bits : 2 - 2 (1 bit)
access : read-only

HSERDYF : HSE ready interrupt flag
bits : 3 - 3 (1 bit)
access : read-only

PLLRDYF : Main PLL (PLL) ready interrupt flag
bits : 4 - 4 (1 bit)
access : read-only

PLLI2SRDYF : PLLI2S ready interrupt flag
bits : 5 - 5 (1 bit)
access : read-only

CSSF : Clock security system interrupt flag
bits : 7 - 7 (1 bit)
access : read-only

LSIRDYIE : LSI ready interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

LSERDYIE : LSE ready interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

HSIRDYIE : HSI ready interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

HSERDYIE : HSE ready interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

PLLRDYIE : Main PLL (PLL) ready interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

PLLI2SRDYIE : PLLI2S ready interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

LSIRDYC : LSI ready interrupt clear
bits : 16 - 16 (1 bit)
access : write-only

LSERDYC : LSE ready interrupt clear
bits : 17 - 17 (1 bit)
access : write-only

HSIRDYC : HSI ready interrupt clear
bits : 18 - 18 (1 bit)
access : write-only

HSERDYC : HSE ready interrupt clear
bits : 19 - 19 (1 bit)
access : write-only

PLLRDYC : Main PLL(PLL) ready interrupt clear
bits : 20 - 20 (1 bit)
access : write-only

PLLI2SRDYC : PLLI2S ready interrupt clear
bits : 21 - 21 (1 bit)
access : write-only

CSSC : Clock security system interrupt clear
bits : 23 - 23 (1 bit)
access : write-only