APEXMIC APM32F00x 2024.04.26 APM32F00x SVD APM32F00x ARM 32-bit Cortex-M0 Microcontroller based device CM0+ r0p0 little 4 false 8 32 ADC Analog to digital converter ADC 0x0 0x0 0x400 registers n ADC ADC global interrupt 22 AWDEN0 AWDEN0 Watchdog Control low register 0xBC 32 read-write n 0x0 0x0 AWDEN Watchdog Control egister 0 8 AWDEN1 AWDEN1 Watchdog Control high register 0xB8 32 read-write n 0x0 0x0 AWDEN Watchdog Control egister 0 2 AWDHT0 AWDHT0 watchdog higher threshold register low 0xA4 32 read-write n 0x0 0x0 THRESHOLD Analog watchdog higher threshold low 0 8 AWDHT1 AWDHT1 watchdog higher threshold register high 0xA0 32 read-write n 0x0 0x0 THRESHOLD Analog watchdog higher threshold high 0 8 AWDLT0 AWDLT0 watchdog lower threshold register low 0xAC 32 read-write n 0x0 0x0 THRESHOLD Analog watchdog lower threshold low 0 8 AWDLT1 AWDLT1 watchdog lower threshold register high 0xA8 32 read-write n 0x0 0x0 LT Analog watchdog lower threshold high 0 8 AWDS0 AWDS0 Watchdog status low register 0xB4 32 read-write n 0x0 0x0 AWDS Watchdog status register 0 8 AWDS1 AWDS1 Watchdog status high register 0xB0 32 read-write n 0x0 0x0 AWDS Watchdog status register 0 2 CSTS CSTS control/status register 0x80 32 read-write n 0x0 0x0 AWDF Analog watchdog flag 6 1 AWDIE AWDIE 4 1 CCF Regular channel end of conversion 7 1 CCIE CCIE 5 1 CHSEL CHSEL 0 4 CTRL1 CTRL1 control register 1 0x84 32 read-write n 0x0 0x0 ADCON ADCON 0 1 CCM CCM 1 1 DIVSEL DIVSEL 4 3 CTRL2 CTRL2 control register 2 0x88 32 read-write n 0x0 0x0 DAM DAM 3 1 ETEN ETEN 6 1 ETS ETS 4 2 SMEN SMEN 1 1 CTRL3 CTRL3 control register 3 0x8C 32 read-write n 0x0 0x0 DBEN DBEN 7 1 OVRF OVRF 6 1 CTRL4 CTRL4 Control register 4 0xC0 32 read-write n 0x0 0x0 DFS DFS 2 1 DISH DISH 0 1 GCMP GCMP 1 1 DATA0 DATA0 low-regular data register 0x94 32 read-only n 0x0 0x0 DATA Regular data 0 8 DATA1 DATA1 high-regular data register 0x90 32 read-only n 0x0 0x0 DATA Regular data 0 8 DATABUF0 DATABUF Data buffer 0 0x0 32 read-only n 0x0 0x0 DATABUF0 Regular data 0 0 8 DATABUF1 DATABUF Data buffer 0 0x4 32 read-only n 0x0 0x0 DATABUF1 Regular data 1 0 8 DATABUF10 DATABUF Data buffer 0 0x28 32 read-only n 0x0 0x0 DATABUF10 Regular data 10 0 8 DATABUF11 DATABUF Data buffer 0 0x2C 32 read-only n 0x0 0x0 DATABUF11 Regular data 11 0 8 DATABUF12 DATABUF Data buffer 0 0x30 32 read-only n 0x0 0x0 DATABUF12 Regular data 12 0 8 DATABUF13 DATABUF Data buffer 0 0x34 32 read-only n 0x0 0x0 DATABUF13 Regular data 13 0 8 DATABUF14 DATABUF Data buffer 0 0x38 32 read-only n 0x0 0x0 DATABUF14 Regular data 14 0 8 DATABUF15 DATABUF Data buffer 0 0x3C 32 read-only n 0x0 0x0 DATABUF15 Regular data 15 0 8 DATABUF16 DATABUF Data buffer 0 0x40 32 read-only n 0x0 0x0 DATABUF16 Regular data 16 0 8 DATABUF17 DATABUF Data buffer 0 0x44 32 read-only n 0x0 0x0 DATABUF17 Regular data 17 0 8 DATABUF18 DATABUF Data buffer 0 0x48 32 read-only n 0x0 0x0 DATABUF18 Regular data 18 0 8 DATABUF19 DATABUF Data buffer 0 0x4C 32 read-only n 0x0 0x0 DATABUF19 Regular data 19 0 8 DATABUF2 DATABUF Data buffer 0 0x8 32 read-only n 0x0 0x0 DATABUF2 Regular data 2 0 8 DATABUF3 DATABUF Data buffer 0 0xC 32 read-only n 0x0 0x0 DATABUF3 Regular data 3 0 8 DATABUF4 DATABUF Data buffer 0 0x10 32 read-only n 0x0 0x0 DATABUF4 Regular data 4 0 8 DATABUF5 DATABUF Data buffer 0 0x14 32 read-only n 0x0 0x0 DATABUF5 Regular data 5 0 8 DATABUF6 DATABUF Data buffer 0 0x18 32 read-only n 0x0 0x0 DATABUF6 Regular data 6 0 8 DATABUF7 DATABUF Data buffer 0 0x1C 32 read-only n 0x0 0x0 DATABUF7 Regular data 7 0 8 DATABUF8 DATABUF Data buffer 0 0x20 32 read-only n 0x0 0x0 DATABUF8 Regular data 8 0 8 DATABUF9 DATABUF Data buffer 0 0x24 32 read-only n 0x0 0x0 DATABUF9 Regular data 9 0 8 OFFSET OFFSET Offset register 0xC4 32 read-write n 0x0 0x0 OFFSET OFFSET 0 8 STD0 STD0 Schmitt trigger disable register low 0x9C 32 read-write n 0x0 0x0 STD Schmitt trigger prohibit low 0 8 STD1 STD1 Schmitt trigger disable register high 0x98 32 read-write n 0x0 0x0 STD Schmitt trigger prohibit high 0 8 BBEP Beeper BBEP 0x0 0x0 0x400 registers n CSTS CSTS External Interrupt Control Register for PORTA to PORTD 0x0 32 read-write n 0x0 0x0 BOFS Beeper frequency selection mask 6 2 BUZEN Beeper enable mask 5 1 DIV Beeper Divider prescalar mask 0 5 EINT External interrupt control EINT 0x0 0x0 0x400 registers n CLR CLR External interrupt clear register 0x8 32 write-only n 0x0 0x0 PAIC PAIC 0 1 PBIC PBIC 1 1 PCIC PCIC 2 1 PDIC PDIC 3 1 TLIC TLIC 6 1 CTRL1 CTRL1 External Interrupt Control Register for PORTA to PORTD 0x0 32 read-write n 0x0 0x0 PAIT PORTA external interrupt sensitivity bits mask 0 2 PBIT PORTB external interrupt sensitivity bits mask 2 2 PCIT PORTC external interrupt sensitivity bits mask 4 2 PDIT PORTD external interrupt sensitivity bits mask 6 2 CTRL2 CTRL2 External Interrupt Control Register for PORTE and TLI 0x4 32 read-write n 0x0 0x0 TLIT TLIT 2 1 FMC Flash Interface FMC 0x0 0x0 0x400 registers n FLASH Flash interrupt 24 ADDR ADDR Flash address register 0x14 32 write-only n 0x0 0x0 ADDR Flash Address 0 32 CTRL1 CTRL1 Flash access control register 0x0 32 read-write n 0x0 0x0 HCAEN Flash half cycle access enable 3 1 read-write LATENCY Latency 0 3 read-write PBEN Prefetch buffer enable 4 1 read-write PBSF Prefetch buffer status 5 1 read-only CTRL2 CTRL2 Control register 0x10 32 read-write n 0x0 0x0 ERRIE Error interrupt enable 10 1 LOCK Lock 7 1 MASSERA Mass Erase 2 1 OBE Option byte erase 5 1 OBP Option byte programming 4 1 OBWEN Option bytes write enable 9 1 OCIE End of operation interrupt enable 12 1 PAGEERA Page Erase 1 1 PG Programming 0 1 STA Start 6 1 KEY KEY Flash key register 0x4 32 write-only n 0x0 0x0 KEY FPEC key 0 32 LPM LPM Low power mode register 0x24 32 read-write n 0x0 0x0 AHALT Power-down in Halt mode 1 1 HALT Power-down in Active-Halt mode 0 1 OBCS OBCS Option byte register 0x1C 32 read-only n 0x0 0x0 DATA0 DATA0 10 8 DATA1 DATA1 18 8 HIRCTRIM HIRCTRIM 6 1 IWDTSW IWDTSW 4 1 LIRCEN LIRCEN 5 1 NOTUSED NOTUSED 7 3 OBE OBE 0 1 READPROT READPROT 1 1 WWDTRST WWDTRST 3 1 WWDTSW WWDTSW 2 1 OBKEY OBKEY Flash option key register 0x8 32 write-only n 0x0 0x0 OBEYR Option byte key 0 32 STS STS Status register 0xC 32 read-write n 0x0 0x0 BUSYF BUSYF 0 1 read-only OCF End of operation 5 1 read-write PEF Programming error 2 1 read-write WPEF Write protection error 4 1 read-write TPO TPO tpower_on register 0x28 32 read-write n 0x0 0x0 TPO TPO 0 8 WRTPROT WRTPROT Write protection register 0x20 32 read-only n 0x0 0x0 WP Write protect 0 32 GPIOA General purpose I/O GPIO 0x0 0x0 0x400 registers n EINTA Popt A external interrupts 3 CTRL1 CTRL1 Port configuration register 1 (GPIOn_CTRL1) 0xC 32 read-write n 0x0 0x0 CR0 Port configuration 0 1 CR1 Port configuration 1 1 CR2 Port configuration 2 1 CR3 Port configuration 3 1 CR4 Port configuration 4 1 CR5 Port configuration 5 1 CR6 Port configuration 6 1 CR7 Port configuration 7 1 CTRL2 CTRL2 Port configuration register 2 (GPIOn_CTRL2) 0x10 32 read-write n 0x0 0x0 CR0 Port configuration 0 1 CR1 Port configuration 1 1 CR2 Port configuration 2 1 CR3 Port configuration 3 1 CR4 Port configuration 4 1 CR5 Port configuration 5 1 CR6 Port configuration 6 1 CR7 Port configuration 7 1 DIN DIN Port input data register (GPIOn_DIN) 0x4 32 read-only n 0x0 0x0 DIN0 Port input data 0 0 1 DIN1 Port input data 1 1 1 DIN2 Port input data 2 2 1 DIN3 Port input data 3 3 1 DIN4 Port input data 4 4 1 DIN5 Port input data 5 5 1 DIN6 Port input data 6 6 1 DIN7 Port input data 7 7 1 DOUT DOUT Port output data register (GPIOn_DOUT) 0x0 32 read-write n 0x0 0x0 DOUT0 Port output data 0 0 1 DOUT1 Port output data 1 1 1 DOUT2 Port output data 2 2 1 DOUT3 Port output data 3 3 1 DOUT4 Port output data 4 4 1 DOUT5 Port output data 5 5 1 DOUT6 Port output data 6 6 1 DOUT7 Port output data 7 7 1 MODE MODE Port data data register (GPIOnMODE) 0x8 32 read-write n 0x0 0x0 MODE0 ouput mode 0 0 1 MODE1 ouput mode 1 1 1 MODE2 ouput mode 2 2 1 MODE3 ouput mode 3 3 1 MODE4 ouput mode 4 4 1 MODE5 ouput mode 5 5 1 MODE6 ouput mode 6 6 1 MODE7 ouput mode 7 7 1 GPIOB General purpose I/O GPIO 0x0 0x0 0x400 registers n EINTB Popt B external interrupts 4 CTRL1 CTRL1 Port configuration register 1 (GPIOn_CTRL1) 0xC 32 read-write n 0x0 0x0 CR0 Port configuration 0 1 CR1 Port configuration 1 1 CR2 Port configuration 2 1 CR3 Port configuration 3 1 CR4 Port configuration 4 1 CR5 Port configuration 5 1 CR6 Port configuration 6 1 CR7 Port configuration 7 1 CTRL2 CTRL2 Port configuration register 2 (GPIOn_CTRL2) 0x10 32 read-write n 0x0 0x0 CR0 Port configuration 0 1 CR1 Port configuration 1 1 CR2 Port configuration 2 1 CR3 Port configuration 3 1 CR4 Port configuration 4 1 CR5 Port configuration 5 1 CR6 Port configuration 6 1 CR7 Port configuration 7 1 DIN DIN Port input data register (GPIOn_DIN) 0x4 32 read-only n 0x0 0x0 DIN0 Port input data 0 0 1 DIN1 Port input data 1 1 1 DIN2 Port input data 2 2 1 DIN3 Port input data 3 3 1 DIN4 Port input data 4 4 1 DIN5 Port input data 5 5 1 DIN6 Port input data 6 6 1 DIN7 Port input data 7 7 1 DOUT DOUT Port output data register (GPIOn_DOUT) 0x0 32 read-write n 0x0 0x0 DOUT0 Port output data 0 0 1 DOUT1 Port output data 1 1 1 DOUT2 Port output data 2 2 1 DOUT3 Port output data 3 3 1 DOUT4 Port output data 4 4 1 DOUT5 Port output data 5 5 1 DOUT6 Port output data 6 6 1 DOUT7 Port output data 7 7 1 MODE MODE Port data data register (GPIOnMODE) 0x8 32 read-write n 0x0 0x0 MODE0 ouput mode 0 0 1 MODE1 ouput mode 1 1 1 MODE2 ouput mode 2 2 1 MODE3 ouput mode 3 3 1 MODE4 ouput mode 4 4 1 MODE5 ouput mode 5 5 1 MODE6 ouput mode 6 6 1 MODE7 ouput mode 7 7 1 GPIOC General purpose I/O GPIO 0x0 0x0 0x400 registers n EINTC Popt C external interrupts 5 CTRL1 CTRL1 Port configuration register 1 (GPIOn_CTRL1) 0xC 32 read-write n 0x0 0x0 CR0 Port configuration 0 1 CR1 Port configuration 1 1 CR2 Port configuration 2 1 CR3 Port configuration 3 1 CR4 Port configuration 4 1 CR5 Port configuration 5 1 CR6 Port configuration 6 1 CR7 Port configuration 7 1 CTRL2 CTRL2 Port configuration register 2 (GPIOn_CTRL2) 0x10 32 read-write n 0x0 0x0 CR0 Port configuration 0 1 CR1 Port configuration 1 1 CR2 Port configuration 2 1 CR3 Port configuration 3 1 CR4 Port configuration 4 1 CR5 Port configuration 5 1 CR6 Port configuration 6 1 CR7 Port configuration 7 1 DIN DIN Port input data register (GPIOn_DIN) 0x4 32 read-only n 0x0 0x0 DIN0 Port input data 0 0 1 DIN1 Port input data 1 1 1 DIN2 Port input data 2 2 1 DIN3 Port input data 3 3 1 DIN4 Port input data 4 4 1 DIN5 Port input data 5 5 1 DIN6 Port input data 6 6 1 DIN7 Port input data 7 7 1 DOUT DOUT Port output data register (GPIOn_DOUT) 0x0 32 read-write n 0x0 0x0 DOUT0 Port output data 0 0 1 DOUT1 Port output data 1 1 1 DOUT2 Port output data 2 2 1 DOUT3 Port output data 3 3 1 DOUT4 Port output data 4 4 1 DOUT5 Port output data 5 5 1 DOUT6 Port output data 6 6 1 DOUT7 Port output data 7 7 1 MODE MODE Port data data register (GPIOnMODE) 0x8 32 read-write n 0x0 0x0 MODE0 ouput mode 0 0 1 MODE1 ouput mode 1 1 1 MODE2 ouput mode 2 2 1 MODE3 ouput mode 3 3 1 MODE4 ouput mode 4 4 1 MODE5 ouput mode 5 5 1 MODE6 ouput mode 6 6 1 MODE7 ouput mode 7 7 1 GPIOD General purpose I/O GPIO 0x0 0x0 0x400 registers n EINTD Popt D external interrupts 6 CTRL1 CTRL1 Port configuration register 1 (GPIOn_CTRL1) 0xC 32 read-write n 0x0 0x0 CR0 Port configuration 0 1 CR1 Port configuration 1 1 CR2 Port configuration 2 1 CR3 Port configuration 3 1 CR4 Port configuration 4 1 CR5 Port configuration 5 1 CR6 Port configuration 6 1 CR7 Port configuration 7 1 CTRL2 CTRL2 Port configuration register 2 (GPIOn_CTRL2) 0x10 32 read-write n 0x0 0x0 CR0 Port configuration 0 1 CR1 Port configuration 1 1 CR2 Port configuration 2 1 CR3 Port configuration 3 1 CR4 Port configuration 4 1 CR5 Port configuration 5 1 CR6 Port configuration 6 1 CR7 Port configuration 7 1 DIN DIN Port input data register (GPIOn_DIN) 0x4 32 read-only n 0x0 0x0 DIN0 Port input data 0 0 1 DIN1 Port input data 1 1 1 DIN2 Port input data 2 2 1 DIN3 Port input data 3 3 1 DIN4 Port input data 4 4 1 DIN5 Port input data 5 5 1 DIN6 Port input data 6 6 1 DIN7 Port input data 7 7 1 DOUT DOUT Port output data register (GPIOn_DOUT) 0x0 32 read-write n 0x0 0x0 DOUT0 Port output data 0 0 1 DOUT1 Port output data 1 1 1 DOUT2 Port output data 2 2 1 DOUT3 Port output data 3 3 1 DOUT4 Port output data 4 4 1 DOUT5 Port output data 5 5 1 DOUT6 Port output data 6 6 1 DOUT7 Port output data 7 7 1 MODE MODE Port data data register (GPIOnMODE) 0x8 32 read-write n 0x0 0x0 MODE0 ouput mode 0 0 1 MODE1 ouput mode 1 1 1 MODE2 ouput mode 2 2 1 MODE3 ouput mode 3 3 1 MODE4 ouput mode 4 4 1 MODE5 ouput mode 5 5 1 MODE6 ouput mode 6 6 1 MODE7 ouput mode 7 7 1 I2C Inter-integrated circuit interface I2C 0x0 0x0 0x400 registers n IIC I2C Interrupt 19 ADDR0 ADDR0 Slave address register 0 0xC 32 read-write n 0x0 0x0 ADDR0 ADDR0 0 8 ADDR1 ADDR1 Slave address register 1 0x10 32 read-write n 0x0 0x0 ADDR ADDR 1 2 ADDRCFG ADDRCFG 6 1 ADDRMODE ADDRMODE 7 1 CLKCTRL1 CLKCTRL1 Clock control register 1 0x2C 32 read-write n 0x0 0x0 CLKCTRL CLKCTRL 0 8 CLKCTRL2 CLKCTRL2 Clock control register 2 0x30 32 read-write n 0x0 0x0 CLKCTRL CLKCTRL 0 4 FASTMODE FASTMODE 7 1 FMDC FMDC 6 1 CLKFREQ CLKFREQ Frequency Control register 0x8 32 read-write n 0x0 0x0 FREQ FREQ 0 6 CTRL1 CTRL1 Control register 1 0x0 32 read-write n 0x0 0x0 BCEN BCEN 6 1 I2CEN I2CEN 0 1 STRDIS STRDIS 7 1 CTRL2 CTRL2 Control register 2 0x4 32 read-write n 0x0 0x0 ACKEN ACKEN 2 1 ACKPOS ACKPOS 3 1 STA STA 0 1 STOP STOP 1 1 SWRST SWRST 7 1 DATA DATA Data register 0x18 32 read-write n 0x0 0x0 DATA DATA 0 8 INTCTRL INTCTRL Interrupt control register 0x28 32 read-write n 0x0 0x0 BUFIE BUFIE 2 1 ERRIE ERRIE 0 1 EVTIE EVTIE 1 1 MRT MRT Max Rise time register 0x34 32 read-write n 0x0 0x0 MRT MRT 0 6 STS1 STS1 Status register 1 0x1C 32 read-only n 0x0 0x0 ADDR10F ADDR10F 3 1 ADDRF ADDRF 1 1 BTCF BTCF 2 1 RXBNEF RXBNEF 7 1 SBDF SBDF 4 1 SBTCF SBTCF 0 1 TXBEF TXBEF 8 1 STS2 STS2 Status register 2 0x20 32 read-only n 0x0 0x0 AEF AEF 2 1 ALF ALF 1 1 BEF BEF 0 1 OUF OUF 3 1 WFHF WFHF 5 1 STS3 STS3 Status register 3 0x24 32 read-only n 0x0 0x0 BUSYF BUSYF 1 1 MMF MMF 0 1 RGF RGF 4 1 RWMF RWMF 2 1 IWDT Independent Watchdog IWDT 0x0 0x0 0x400 registers n CNTRLD CNTRLD Reload Register 0x8 32 write-only n 0x0 0x0 CNTRLD Reload Register 0 8 DIV DIV Prescaler Register 0x4 32 read-write n 0x0 0x0 DIV Prescaler Register 0 3 KEYWORD KEYWORD Key Register 0x0 32 write-only n 0x0 0x0 KEY Key Register 0 8 OB Option Bytes Registers OB 0x0 0x0 0x400 registers n AFR AFR AFR 0x10 16 read-write n 0x0 0x0 AFR AFR 0 16 CLKOPT CLKOPT CLKOPT 0x16 16 read-write n 0x0 0x0 EXTCLK EXTCLK 3 1 nCLKOPT nCLKOPT 8 8 NOTUSED NOTUSED 4 4 WUPTCS WUPTCS 2 1 WUPTDIV WUPTDIV 0 2 DATA0 DATA0 DATA0 0x4 16 write-only n 0x0 0x0 DATA0 DATA0 0 16 DATA1 DATA1 DATA1 0x6 16 write-only n 0x0 0x0 DATA1 DATA1 0 16 HXTCNT HXTCNT HXTCNT 0x14 16 read-write n 0x0 0x0 HXTCNT HXTCNT 0 16 USER USER USER 0x2 16 read-write n 0x0 0x0 HIRCTRIM HIRCTRIM 4 1 IWDTSW IWDTSW 2 1 LIRCEN LIRCEN 3 1 NOTUSED NOTUSED 5 3 nUSER nUSER 8 8 WWDTRST WWDTRST 1 1 WWDTSW WWDTSW 0 1 WRTPROT0 WRTPROT0 WRTPROT0 0x8 16 read-write n 0x0 0x0 WRTPROT0 WRTPROT0 0 16 WRTPROT1 WRTPROT1 WRTPROT1 0xA 16 read-write n 0x0 0x0 WRTPROT1 WRTPROT1 0 16 WRTPROT2 WRTPROT2 WRTPROT2 0xC 16 read-write n 0x0 0x0 WRTPROT2 WRTPROT2 0 16 WRTPROT3 WRTPROT3 WRTPROT3 0xE 16 read-write n 0x0 0x0 WRTPROT3 WRTPROT3 0 16 RCM Reset and Clock Management RCM 0x0 0x0 0x400 registers n RCM Clock controller interrupt 2 APBEN1 APBEN1 APB peripheral clock enable register1 0x1C 32 read-write n 0x0 0x0 I2CCEN I2C clock enable 0 1 SPICEN SPI clock enable 1 1 TMR1CEN Timer 1 clock enable 7 1 TMR2CEN Timer 2 clock enable 5 1 TMR4CEN Timer 4 clock enable 4 1 UART1CEN UART1 clock enabl 3 1 APBEN2 APBEN2 APB peripheral clock enable register2 0x28 32 read-write n 0x0 0x0 ADCCEN ADC clock enable 3 1 WUPTCEN AWU clock enable 2 1 APBEN3 APBEN3 APB peripheral clock enable register3 0x3C 32 read-write n 0x0 0x0 TMR1ACEN TMR1 clock enable 0 1 UART2CEN UART2 clock enable 1 1 UART3CEN UART3 clock enable 4 1 CLKDIV CLKDIV Clock Divider Register 0x18 32 read-write n 0x0 0x0 CPUDIV High speed internal clock prescaler 0 3 HDS HDS 5 1 HIRCDIV CPU clock prescaler 3 2 COC COC clock output control register 0x24 32 read-write n 0x0 0x0 COBF Configurable clock output busy 6 1 read-only COEN Configurable clock output enable 0 1 read-write CORF Configurable clock output ready 5 1 read-only COS Configurable clock output selection 1 4 read-write CSC CSC Switch Control Register 0x14 32 read-write n 0x0 0x0 CSBF Switch busy flag 0 1 CSEN Switch start/stop 1 1 CSIE Clock switch interrupt enable 2 1 CSIF Clock switch interrupt flag 3 1 CSS CSS Clock security system register 0x20 32 read-write n 0x0 0x0 BCEN Auxiliary oscillator connected to master clock 1 1 read-only CSSEN Clock security system enable 0 1 read-write CSSFDIE Clock security system detection interrupt enable 2 1 read-write CSSFDIF Clock security system detection 3 1 read-write ECC ECC External Interrupt Control Register for PORTE and TLI 0x4 8 read-write n 0x0 0x0 HXTEN High speed external crystal oscillator enable 0 1 read-write HXTRF High speed external crystal oscillator ready 1 1 read-only HIRCTRIM HIRCTRIM HIRC clock calibration trimming register 0x30 32 read-write n 0x0 0x0 TRIM High speed internal oscillator trimmer 0 4 ICC ICC Internal Clocks Control Register 0x0 8 read-write n 0x0 0x0 FWFHEN Fast Wake-up from Active Halt/Halt mode 2 1 read-write HIRCEN High speed internal RC oscillator enable 0 1 read-write HIRCRF High speed internal RC oscillator ready 1 1 read-only LIRCEN Low speed internal RC oscillator enable 3 1 read-write LIRCRF Low speed internal oscillator ready 4 1 read-only RPOEN Slow Wake-up from Active Halt/Halt modes 5 1 read-write MCC MCC Clock Master Switch Register 0x10 32 read-write n 0x0 0x0 MCC Clock master selection bits 0 8 MCS MCS Clock Master Status Register 0xC 32 read-only n 0x0 0x0 MCS Clock master status bits 0 8 RSTSTS RSTSTS Reset status register 0x38 32 read-write n 0x0 0x0 EMCRF EMC reset flag bit mask 4 1 IWDTRF IWDG reset flag bit mask 1 1 WWDTRF WWDG reset flag bit mask 0 1 SPI Serial peripheral interface SPI 0x0 0x0 0x400 registers n SPI SPI Interrupt 10 CRCPOLY CRCPOLY CRC polynomial register 0x14 32 read-write n 0x0 0x0 polynomial polynomial 0 8 CTRL1 CTRL1 Control register 1 0x0 32 read-write n 0x0 0x0 BRC BRC 3 3 CLKPHA CLKPHA 0 1 CLKPOL CLKPOL 1 1 LSBF LSBF 7 1 MSTMODE MSTMODE 2 1 SPIEN SPIEN 6 1 CTRL2 CTRL2 Control register 2 0x4 32 read-write n 0x0 0x0 BMEN BMEN 7 1 BMTX BMTX 6 1 CRCEN CRCEN 5 1 CRCNXT CRCNXT 3 1 ISS ISS 0 1 SSC SSC 1 1 UMRXO UMRXO 2 1 DATA DATA Data register 0x10 32 read-write n 0x0 0x0 DATA DATA 0 8 INTCTRL INTCTRL Interrupt control register 0x8 32 read-write n 0x0 0x0 ERRIE ERRIE 5 1 RXBNEIE RXBNEIE 6 1 TXBEIE TXBEIE 7 1 WUPIE WUPIE 4 1 RXCRC RXCRC Rx CRC register 0x18 32 read-only n 0x0 0x0 CRC CRC 0 8 STS STS Status register 0xC 32 read-write n 0x0 0x0 BUSYF BUSYF 7 1 CRCEF CRCEF 4 1 MMEF MMEF 5 1 RXBNEF RXBNEF 0 1 RXOF RXOF 6 1 TXBEF TXBEF 1 1 WUPF WUPF 2 1 TXCRC TXCRC Tx CRC register 0x20 32 read-only n 0x0 0x0 CRC CRC 0 8 TMR1 16-bit timer with complementary PWM outputs TMR 0x0 0x0 0x400 registers n TMR1_UT TIM1 update/overflow/underflow/trigger/break interrupt 11 TMR1_CC TIM1 capture/compare interrupt 12 AUTORLD0 AUTORLD0 auto-reload register low 0x4C 32 read-write n 0x0 0x0 RELOAD Autoreload Value (LSB) mask. 0 8 AUTORLD1 AUTORLD1 auto-reload register high 0x48 32 read-write n 0x0 0x0 RELOAD Autoreload Value (MSB) mask. 0 8 BRKCTRL BRKCTRL Break Register 0x74 32 read-write n 0x0 0x0 AOEN Automatic Output Enable mask. 6 1 BRKEN Break Enable mask. 4 1 BRKPOL Break Polarity mask. 5 1 IMOS Off-State Selection for Idle mode mask. 2 1 PROTCFG Lock Configuration mask. 0 2 RMOS Off-State Selection for Run mode mask. 3 1 WOEN Main Output Enable mask. 7 1 CH1CC0 CH1CC0 capture/compare register 1 low 0x58 32 read-write n 0x0 0x0 CC Capture/Compare 1 Value (LSB) mask. 0 8 CH1CC1 CH1CC1 capture/compare register 1 high 0x54 32 read-write n 0x0 0x0 CC Capture/Compare 1 Value (MSB) mask. 0 8 CH1IC CH1IC IC mode register 1 CH1OC 0x20 32 read-write n 0x0 0x0 ICD ICD 2 2 ICFC ICFC 4 4 MODESEL Capture/Compare 1 Selection mask. 0 2 CH1OC CH1OC CC mode register 1 0x20 32 read-write n 0x0 0x0 MODESEL Capture/Compare 1 Selection mask. 0 2 OCBEN Output Compare 1 Preload Enable mask. 3 1 OCCEN Input Capture 1 Filter mask. 7 1 OCFEN Output Compare 1 Fast Enable mask. 2 1 OCMS Output Compare 1 Mode mask. 4 3 CH2CC0 CH2CC0 capture/compare register 2 low 0x60 32 read-write n 0x0 0x0 CC Capture/Compare 2 Value (LSB) mask. 0 8 CH2CC1 CH2CC1 capture/compare register 2 high 0x5C 32 read-write n 0x0 0x0 CC Capture/Compare 2 Value (MSB) mask. 0 8 CH2IC CH2IC IC mode register 2 CH2OC 0x24 32 read-write n 0x0 0x0 ICD ICD 2 2 ICFC ICFC 4 4 MODESEL Capture/Compare 1 Selection mask. 0 2 CH2OC CH2OC CC mode register 2 0x24 32 read-write n 0x0 0x0 MODESEL Capture/Compare 2 Selection mask. 0 2 OCBEN Output Compare 2 Preload Enable mask. 3 1 OCCEN Input Capture 2 Filter mask. 7 1 OCFEN Output Compare 2 Fast Enable mask. 2 1 OCMS Output Compare 2 Mode mask. 4 3 CH3CC0 CH3CC0 capture/compare register 3 low 0x68 32 read-write n 0x0 0x0 CC Capture/Compare 3 Value (LSB) mask. 0 8 CH3CC1 CH3CC1 capture/compare register 3 high 0x64 32 read-write n 0x0 0x0 CC Capture/Compare 3 Value (MSB) mask. 0 8 CH3IC CH3IC IC mode register 3 CH3OC 0x28 32 read-write n 0x0 0x0 ICD ICD 2 2 ICFC ICFC 4 4 MODESEL Capture/Compare 1 Selection mask. 0 2 CH3OC CH3OC CC mode register 3 0x28 32 read-write n 0x0 0x0 MODESEL Capture/Compare 3 Selection mask. 0 2 OCBEN Output Compare 3 Preload Enable mask. 3 1 OCCEN Input Capture 3 Filter mask. 7 1 OCFEN Output Compare 3 Fast Enable mask. 2 1 OCMS Output Compare 3 Mode mask. 4 3 CH4CC0 CH4CC0 capture/compare register 4 low 0x70 32 read-write n 0x0 0x0 CC Capture/Compare 4 Value (LSB) mask. 0 8 CH4CC1 CH4CC1 capture/compare register 4 high 0x6C 32 read-write n 0x0 0x0 CC Capture/Compare 4 Value (MSB) mask. 0 8 CH4IC CH4IC IC mode register 4 CH4OC 0x2C 32 read-write n 0x0 0x0 ICD ICD 2 2 ICFC ICFC 4 4 MODESEL Capture/Compare 1 Selection mask. 0 2 CH4OC CH4OC CC mode register 4 0x2C 32 read-write n 0x0 0x0 MODESEL Capture/Compare 4 Selection mask. 0 2 OCBEN Output Compare 4 Preload Enable mask. 3 1 OCCEN Input Capture 4 Filter mask. 7 1 OCFEN Output Compare 4 Fast Enable mask. 2 1 OCMS Output Compare 4 Mode mask. 4 3 CHCTRL1 CHCTRL1 CC enable register 1 0x30 32 read-write n 0x0 0x0 CH1CCEN Capture/Compare 1 output enable mask. 0 1 CH1CCP Capture/Compare 1 output Polarity mask. 1 1 CH1OCNEN Capture/Compare 1 Complementary output enable mask. 2 1 CH1OCNP Capture/Compare 1 Complementary output Polarity mask. 3 1 CH2CCEN Capture/Compare 2 output enable mask. 4 1 CH2CCP Capture/Compare 2 output Polarity mask. 5 1 CH2OCNEN Capture/Compare 2 Complementary output enable mask. 6 1 CH2OCNP Capture/Compare 2 Complementary output Polarity mask. 7 1 CHCTRL2 CHCTRL2 CC enable register 2 0x34 32 read-write n 0x0 0x0 CH3CCEN Capture/Compare 3 output enable mask. 0 1 CH3CCP Capture/Compare 3 output Polarity mask. 1 1 CH4CCEN Capture/Compare 3 Complementary output enable mask. 2 1 CH4CCP Capture/Compare 3 Complementary output Polarity mask. 3 1 CHEN CHEN Timer1A Channel enable register 0x84 32 read-write n 0x0 0x0 CH1 CH1 0 1 CH2 CH2 1 1 CH3 CH3 2 1 CH4 CH4 3 1 CNT0 CNT0 counter low 0x3C 32 read-write n 0x0 0x0 CNT Counter Value (LSB) mask. 0 8 CNT1 CNT1 counter high 0x38 32 read-write n 0x0 0x0 CNT Counter Value (MSB) mask. 0 8 CTRL1 CTRL1 control register 1 0x0 32 read-write n 0x0 0x0 ARBEN Auto-Reload Preload Enable mask. 7 1 CNTDIR Direction mask. 4 1 CNTEN Counter Enable mask. 0 1 CNTMODE Center-aligned Mode Selection mask. 5 2 NGUE Update DIsable mask. 1 1 SPMEN One Pulse Mode mask. 3 1 UES Update Request Source mask. 2 1 CTRL2 CTRL2 control register 2 0x4 32 read-write n 0x0 0x0 CCBEN MMS Selection mask. 0 1 CCUS Capture/Compare Control Update Selection mask. 2 1 MMFC Capture/Compare Preloaded Control mask. 4 3 DIV0 DIV0 prescaler low 0x44 32 read-write n 0x0 0x0 DIV Prescaler Value (LSB) mask. 0 8 DIV1 DIV1 prescaler high 0x40 32 read-write n 0x0 0x0 DIV Prescaler Value (MSB) mask. 0 8 DTS DTS dead-time register 0x78 32 read-write n 0x0 0x0 DT Dead-Time Generator set-up mask. 0 8 ETC ETC external trigger register 0xC 32 read-write n 0x0 0x0 ECM2EN External Clock mask. 6 1 ETDC External Trigger Prescaler mask. 4 2 ETFC External Trigger Filter mask. 0 4 ETPC External Trigger Polarity mask. 7 1 INTCTRL INTCTRL interrupt enable register 0x10 32 read-write n 0x0 0x0 BRKIE Break Interrupt Enable mask. 7 1 CCUIE Commutation Interrupt Enable mask. 5 1 CH1CCIE Capture/Compare 1 Interrupt Enable mask. 1 1 CH2CCIE Capture/Compare 2 Interrupt Enable mask. 2 1 CH3CCIE Capture/Compare 3 Interrupt Enable mask. 3 1 CH4CCIE Capture/Compare 4 Interrupt Enable mask. 4 1 TRGIE Trigger Interrupt Enable mask. 6 1 UDIE Update Interrupt Enable mask. 0 1 ISO ISO Output idle register 0x7C 32 read-write n 0x0 0x0 CH1ISO Output Idle state 1 (OC1 output) mask. 0 1 CH1NISO Output Idle state 1 (OC1N output) mask. 1 1 CH2ISO Output Idle state 2 (OC2 output) mask. 2 1 CH2NISO Output Idle state 2 (OC2N output) mask. 3 1 CH3ISO Output Idle state 3 (OC3 output) mask. 4 1 CH3NISO Output Idle state 3 (OC3N output) mask. 5 1 CH4ISO Output Idle state 4 (OC4 output) mask. 6 1 CH4NISO Output Idle state 4 (OC4N output) mask. 7 1 REPCNT REPCNT Repetition Counter register 0x50 32 read-write n 0x0 0x0 REPCNT Repetition Counter Value mask. 0 8 SCEG SCEG event generation register 0x1C 32 read-write n 0x0 0x0 BEG Break Generation mask. 7 1 CCUEG Capture/Compare Control Update Generation mask. 5 1 CH1CCG Capture/Compare 1 Generation mask. 1 1 CH2CCG Capture/Compare 2 Generation mask. 2 1 CH3CCG Capture/Compare 3 Generation mask. 3 1 CH4CCG Capture/Compare 4 Generation mask. 4 1 TEG Trigger Generation mask. 6 1 UEG Update Generation mask. 0 1 SMC SMC Synchro mode control register 0x8 32 read-write n 0x0 0x0 ITC Trigger Selection mask. 4 3 MSMEN Slave Mode Selection mask. 7 1 SMFC Master/Slave Mode mask. 0 3 STS1 STS1 status register 1 0x14 32 read-write n 0x0 0x0 BRKIF Break Interrupt Flag mask. 7 1 CCUIF Commutation Interrupt Flag mask. 5 1 CH1CCIF Capture/Compare 1 Interrupt Flag mask. 1 1 CH2CCIF Capture/Compare 2 Interrupt Flag mask. 2 1 CH3CCIF Capture/Compare 3 Interrupt Flag mask. 3 1 CH4CCIF Capture/Compare 4 Interrupt Flag mask. 4 1 TRGIF Trigger Interrupt Flag mask. 6 1 UDIF Update Interrupt Flag mask. 0 1 STS2 STS2 status register 2 0x18 32 read-write n 0x0 0x0 CH1RCF Capture/Compare 1 Overcapture Flag mask. 1 1 CH2RCF Capture/Compare 2 Overcapture Flag mask. 2 1 CH3RCF Capture/Compare 3 Overcapture Flag mask. 3 1 CH4RCF Capture/Compare 4 Overcapture Flag mask. 4 1 TMR1A 16-bit timer with complementary PWM outputs TMR 0x0 0x0 0x400 registers n TMR1A_UT TIM1 update/overflow/underflow/trigger/break interrupt 29 TMR1A_CC TIM1 capture/compare interrupt 30 AUTORLD0 AUTORLD0 auto-reload register low 0x4C 32 read-write n 0x0 0x0 RELOAD Autoreload Value (LSB) mask. 0 8 AUTORLD1 AUTORLD1 auto-reload register high 0x48 32 read-write n 0x0 0x0 RELOAD Autoreload Value (MSB) mask. 0 8 BRKCTRL BRKCTRL Break Register 0x74 32 read-write n 0x0 0x0 AOEN Automatic Output Enable mask. 6 1 BRKEN Break Enable mask. 4 1 BRKPOL Break Polarity mask. 5 1 IMOS Off-State Selection for Idle mode mask. 2 1 PROTCFG Lock Configuration mask. 0 2 RMOS Off-State Selection for Run mode mask. 3 1 WOEN Main Output Enable mask. 7 1 CH1CC0 CH1CC0 capture/compare register 1 low 0x58 32 read-write n 0x0 0x0 CC Capture/Compare 1 Value (LSB) mask. 0 8 CH1CC1 CH1CC1 capture/compare register 1 high 0x54 32 read-write n 0x0 0x0 CC Capture/Compare 1 Value (MSB) mask. 0 8 CH1IC CH1IC IC mode register 1 CH1OC 0x20 32 read-write n 0x0 0x0 ICD ICD 2 2 ICFC ICFC 4 4 MODESEL Capture/Compare 1 Selection mask. 0 2 CH1OC CH1OC CC mode register 1 0x20 32 read-write n 0x0 0x0 MODESEL Capture/Compare 1 Selection mask. 0 2 OCBEN Output Compare 1 Preload Enable mask. 3 1 OCCEN Input Capture 1 Filter mask. 7 1 OCFEN Output Compare 1 Fast Enable mask. 2 1 OCMS Output Compare 1 Mode mask. 4 3 CH2CC0 CH2CC0 capture/compare register 2 low 0x60 32 read-write n 0x0 0x0 CC Capture/Compare 2 Value (LSB) mask. 0 8 CH2CC1 CH2CC1 capture/compare register 2 high 0x5C 32 read-write n 0x0 0x0 CC Capture/Compare 2 Value (MSB) mask. 0 8 CH2IC CH2IC IC mode register 2 CH2OC 0x24 32 read-write n 0x0 0x0 ICD ICD 2 2 ICFC ICFC 4 4 MODESEL Capture/Compare 1 Selection mask. 0 2 CH2OC CH2OC CC mode register 2 0x24 32 read-write n 0x0 0x0 MODESEL Capture/Compare 2 Selection mask. 0 2 OCBEN Output Compare 2 Preload Enable mask. 3 1 OCCEN Input Capture 2 Filter mask. 7 1 OCFEN Output Compare 2 Fast Enable mask. 2 1 OCMS Output Compare 2 Mode mask. 4 3 CH3CC0 CH3CC0 capture/compare register 3 low 0x68 32 read-write n 0x0 0x0 CC Capture/Compare 3 Value (LSB) mask. 0 8 CH3CC1 CH3CC1 capture/compare register 3 high 0x64 32 read-write n 0x0 0x0 CC Capture/Compare 3 Value (MSB) mask. 0 8 CH3IC CH3IC IC mode register 3 CH3OC 0x28 32 read-write n 0x0 0x0 ICD ICD 2 2 ICFC ICFC 4 4 MODESEL Capture/Compare 1 Selection mask. 0 2 CH3OC CH3OC CC mode register 3 0x28 32 read-write n 0x0 0x0 MODESEL Capture/Compare 3 Selection mask. 0 2 OCBEN Output Compare 3 Preload Enable mask. 3 1 OCCEN Input Capture 3 Filter mask. 7 1 OCFEN Output Compare 3 Fast Enable mask. 2 1 OCMS Output Compare 3 Mode mask. 4 3 CH4CC0 CH4CC0 capture/compare register 4 low 0x70 32 read-write n 0x0 0x0 CC Capture/Compare 4 Value (LSB) mask. 0 8 CH4CC1 CH4CC1 capture/compare register 4 high 0x6C 32 read-write n 0x0 0x0 CC Capture/Compare 4 Value (MSB) mask. 0 8 CH4IC CH4IC IC mode register 4 CH4OC 0x2C 32 read-write n 0x0 0x0 ICD ICD 2 2 ICFC ICFC 4 4 MODESEL Capture/Compare 1 Selection mask. 0 2 CH4OC CH4OC CC mode register 4 0x2C 32 read-write n 0x0 0x0 MODESEL Capture/Compare 4 Selection mask. 0 2 OCBEN Output Compare 4 Preload Enable mask. 3 1 OCCEN Input Capture 4 Filter mask. 7 1 OCFEN Output Compare 4 Fast Enable mask. 2 1 OCMS Output Compare 4 Mode mask. 4 3 CHCTRL1 CHCTRL1 CC enable register 1 0x30 32 read-write n 0x0 0x0 CH1CCEN Capture/Compare 1 output enable mask. 0 1 CH1CCP Capture/Compare 1 output Polarity mask. 1 1 CH1OCNEN Capture/Compare 1 Complementary output enable mask. 2 1 CH1OCNP Capture/Compare 1 Complementary output Polarity mask. 3 1 CH2CCEN Capture/Compare 2 output enable mask. 4 1 CH2CCP Capture/Compare 2 output Polarity mask. 5 1 CH2OCNEN Capture/Compare 2 Complementary output enable mask. 6 1 CH2OCNP Capture/Compare 2 Complementary output Polarity mask. 7 1 CHCTRL2 CHCTRL2 CC enable register 2 0x34 32 read-write n 0x0 0x0 CH3CCEN Capture/Compare 3 output enable mask. 0 1 CH3CCP Capture/Compare 3 output Polarity mask. 1 1 CH4CCEN Capture/Compare 3 Complementary output enable mask. 2 1 CH4CCP Capture/Compare 3 Complementary output Polarity mask. 3 1 CHEN CHEN Timer1A Channel enable register 0x84 32 read-write n 0x0 0x0 CH1 CH1 0 1 CH2 CH2 1 1 CH3 CH3 2 1 CH4 CH4 3 1 CNT0 CNT0 counter low 0x3C 32 read-write n 0x0 0x0 CNT Counter Value (LSB) mask. 0 8 CNT1 CNT1 counter high 0x38 32 read-write n 0x0 0x0 CNT Counter Value (MSB) mask. 0 8 CTRL1 CTRL1 control register 1 0x0 32 read-write n 0x0 0x0 ARBEN Auto-Reload Preload Enable mask. 7 1 CNTDIR Direction mask. 4 1 CNTEN Counter Enable mask. 0 1 CNTMODE Center-aligned Mode Selection mask. 5 2 NGUE Update DIsable mask. 1 1 SPMEN One Pulse Mode mask. 3 1 UES Update Request Source mask. 2 1 CTRL2 CTRL2 control register 2 0x4 32 read-write n 0x0 0x0 CCBEN MMS Selection mask. 0 1 CCUS Capture/Compare Control Update Selection mask. 2 1 MMFC Capture/Compare Preloaded Control mask. 4 3 DIV0 DIV0 prescaler low 0x44 32 read-write n 0x0 0x0 DIV Prescaler Value (LSB) mask. 0 8 DIV1 DIV1 prescaler high 0x40 32 read-write n 0x0 0x0 DIV Prescaler Value (MSB) mask. 0 8 DTS DTS dead-time register 0x78 32 read-write n 0x0 0x0 DT Dead-Time Generator set-up mask. 0 8 ETC ETC external trigger register 0xC 32 read-write n 0x0 0x0 ECM2EN External Clock mask. 6 1 ETDC External Trigger Prescaler mask. 4 2 ETFC External Trigger Filter mask. 0 4 ETPC External Trigger Polarity mask. 7 1 INTCTRL INTCTRL interrupt enable register 0x10 32 read-write n 0x0 0x0 BRKIE Break Interrupt Enable mask. 7 1 CCUIE Commutation Interrupt Enable mask. 5 1 CH1CCIE Capture/Compare 1 Interrupt Enable mask. 1 1 CH2CCIE Capture/Compare 2 Interrupt Enable mask. 2 1 CH3CCIE Capture/Compare 3 Interrupt Enable mask. 3 1 CH4CCIE Capture/Compare 4 Interrupt Enable mask. 4 1 TRGIE Trigger Interrupt Enable mask. 6 1 UDIE Update Interrupt Enable mask. 0 1 ISO ISO Output idle register 0x7C 32 read-write n 0x0 0x0 CH1ISO Output Idle state 1 (OC1 output) mask. 0 1 CH1NISO Output Idle state 1 (OC1N output) mask. 1 1 CH2ISO Output Idle state 2 (OC2 output) mask. 2 1 CH2NISO Output Idle state 2 (OC2N output) mask. 3 1 CH3ISO Output Idle state 3 (OC3 output) mask. 4 1 CH3NISO Output Idle state 3 (OC3N output) mask. 5 1 CH4ISO Output Idle state 4 (OC4 output) mask. 6 1 CH4NISO Output Idle state 4 (OC4N output) mask. 7 1 REPCNT REPCNT Repetition Counter register 0x50 32 read-write n 0x0 0x0 REPCNT Repetition Counter Value mask. 0 8 SCEG SCEG event generation register 0x1C 32 read-write n 0x0 0x0 BEG Break Generation mask. 7 1 CCUEG Capture/Compare Control Update Generation mask. 5 1 CH1CCG Capture/Compare 1 Generation mask. 1 1 CH2CCG Capture/Compare 2 Generation mask. 2 1 CH3CCG Capture/Compare 3 Generation mask. 3 1 CH4CCG Capture/Compare 4 Generation mask. 4 1 TEG Trigger Generation mask. 6 1 UEG Update Generation mask. 0 1 SMC SMC Synchro mode control register 0x8 32 read-write n 0x0 0x0 ITC Trigger Selection mask. 4 3 MSMEN Slave Mode Selection mask. 7 1 SMFC Master/Slave Mode mask. 0 3 STS1 STS1 status register 1 0x14 32 read-write n 0x0 0x0 BRKIF Break Interrupt Flag mask. 7 1 CCUIF Commutation Interrupt Flag mask. 5 1 CH1CCIF Capture/Compare 1 Interrupt Flag mask. 1 1 CH2CCIF Capture/Compare 2 Interrupt Flag mask. 2 1 CH3CCIF Capture/Compare 3 Interrupt Flag mask. 3 1 CH4CCIF Capture/Compare 4 Interrupt Flag mask. 4 1 TRGIF Trigger Interrupt Flag mask. 6 1 UDIF Update Interrupt Flag mask. 0 1 STS2 STS2 status register 2 0x18 32 read-write n 0x0 0x0 CH1RCF Capture/Compare 1 Overcapture Flag mask. 1 1 CH2RCF Capture/Compare 2 Overcapture Flag mask. 2 1 CH3RCF Capture/Compare 3 Overcapture Flag mask. 3 1 CH4RCF Capture/Compare 4 Overcapture Flag mask. 4 1 TMR2 16-bit timer TMR 0x0 0x0 0x400 registers n TMR2_UO TIM2 update /overflow interrupt 13 TMR2_CC TIM2 capture/compare interrupt 14 AUTORLD0 AUTORLD0 Auto reload register 0 0x40 32 read-write n 0x0 0x0 ARR Autoreload Value (LSB) mask. 0 8 AUTORLD1 AUTORLD1 Auto reload register 1 0x3C 32 read-write n 0x0 0x0 RELOAD Autoreload Value (MSB) mask. 0 8 CH1CC0 CH1CC0 channel 1 compare/capture register 0 0x48 32 read-write n 0x0 0x0 CC Capture/Compare 1 Value (LSB) mask. 0 8 CH1CC1 CH1CC1 channel 1 compare/capture register 1 0x44 32 read-write n 0x0 0x0 CC Capture/Compare 1 Value (MSB) mask. 0 8 CH1IC CH1CCM capture/compare mode register 1 (input mode) CH1OC 0x1C 32 read-write n 0x0 0x0 ICD Input capture 1 prescaler 2 2 ICFC Input capture 1 filter 4 4 MODESEL Capture/Compare 1 Selection mask. 0 2 CH1OC CH1CCM capture/compare mode register 1 (output mode) 0x1C 32 read-write n 0x0 0x0 MODESEL Capture/Compare 1 Selection mask. 0 2 OCBEN Output Compare 1 Preload Enable mask. 3 1 OCMS Output Compare 1 Mode mask. 4 3 CH2CC0 CH2CC0 channel 2 compare/capture register 0 0x50 32 read-write n 0x0 0x0 CC Capture/Compare 2 Value (LSB) mask. 0 8 CH2CC1 CH2CC1 channel 2 compare/capture register 1 0x4C 32 read-write n 0x0 0x0 CC Capture/Compare 2 Value (MSB) mask. 0 8 CH2IC CH2CCM capture/compare mode register 2 (input mode) CH2OC 0x20 32 read-write n 0x0 0x0 ICD Input capture 2 prescaler 2 2 ICFC Input capture 2 filter 4 4 MODESEL Capture/Compare 2 Selection mask. 0 2 CH2OC CH2CCM capture/compare mode register 2 (output mode) 0x20 32 read-write n 0x0 0x0 MODESEL Capture/Compare 2 Selection mask. 0 2 OCBEN Output Compare 2 Preload Enable mask. 3 1 OCMS Output Compare 2 Mode mask. 4 3 CH3CC0 CH3CC0 channel 3 compare/capture register 0 0x58 32 read-write n 0x0 0x0 CC Capture/Compare 3 Value (LSB) mask. 0 8 CH3CC1 CH3CC1 channel 3 compare/capture register 1 0x54 32 read-write n 0x0 0x0 CC Capture/Compare 3 Value (MSB) mask. 0 8 CH3IC CH3CCM capture/compare mode register 3 (input mode) CH3OC 0x24 32 read-write n 0x0 0x0 ICD Input capture 3 prescaler 2 2 ICFC Input capture 3 filter 4 4 MODESEL Capture/Compare 3 Selection mask. 0 2 CH3OC CH3CCM capture/compare mode register 3 (output mode) 0x24 32 read-write n 0x0 0x0 MODESEL Capture/Compare 3 Selection mask. 0 2 OCBEN Output Compare 3 Preload Enable mask. 3 1 OCMS Output Compare 3 Mode mask. 4 3 CHCTRL1 CHCTRL1 Channel control register 1 0x28 32 read-write n 0x0 0x0 CH1CCEN Capture/Compare 1 output enable mask. 0 1 CH1CCP Capture/Compare 1 output Polarity mask. 1 1 CH2CCEN Capture/Compare 2 output enable mask. 4 1 CH2CCP Capture/Compare 2 output Polarity mask. 5 1 CHCTRL2 CHCTRL2 Channel control register 2 0x2C 32 read-write n 0x0 0x0 CH3CCEN Capture/Compare 3 output enable mask. 0 1 CH3CCP Capture/Compare 3 output Polarity mask. 1 1 CNT0 CNT0 Count register 0 0x34 32 read-write n 0x0 0x0 CNT Counter Value (LSB) mask. 0 8 CNT1 CNT1 Count register 1 0x30 32 read-write n 0x0 0x0 CNT Counter Value (MSB) mask. 0 8 CTRL1 CTRL1 control register 1 0x0 32 read-write n 0x0 0x0 ARBEN Auto-Reload Preload Enable mask. 7 1 CNTEN Counter Enable mask. 0 1 NGUE Update DIsable mask. 1 1 SPMEN One Pulse Mode mask. 3 1 UES Update Request Source mask. 2 1 CTRL2 CTRL2 control register 2 0x4 32 read-write n 0x0 0x0 MMFC Capture/Compare Preloaded Control mask. 4 3 DIV DIV divider register 0x38 32 read-write n 0x0 0x0 DIV Prescaler Value mask. 0 4 INTCTRL INTCTRL interrupt enable register 0xC 32 read-write n 0x0 0x0 CH1CCIE Capture/Compare 1 Interrupt Enable mask. 1 1 CH2CCIE Capture/Compare 2 Interrupt Enable mask. 2 1 CH3CCIE Capture/Compare 3 Interrupt Enable mask. 3 1 TRGIE Trigger Interrupt Enable mask. 6 1 UDIE Update Interrupt Enable mask. 0 1 SCEG SCEG event generation register 0x18 32 write-only n 0x0 0x0 CH1CCG Capture/Compare 1 Generation mask. 1 1 CH2CCG Capture/Compare 2 Generation mask. 2 1 CH3CCG Capture/Compare 3 Generation mask. 3 1 TEG Trigger Generation mask. 6 1 UEG Update Generation mask. 0 1 SMC SMC Synchro mode control register 0x8 32 read-write n 0x0 0x0 ITC Trigger Selection mask. 4 3 MSMEN Slave Mode Selection mask. 7 1 SMFC Master/Slave Mode mask. 0 3 STS1 STS1 status register 1 0x10 32 read-write n 0x0 0x0 CH1CCIF Capture/Compare 1 Interrupt Flag mask. 1 1 CH2CCIF Capture/Compare 2 Interrupt Flag mask. 2 1 CH3CCIF Capture/Compare 3 Interrupt Flag mask. 3 1 TRGIF Trigger Interrupt Flag mask. 6 1 UDIF Update Interrupt Flag mask. 0 1 STS2 STS2 status register 2 0x14 32 read-write n 0x0 0x0 CH1RCF Capture/Compare 1 Overcapture Flag mask. 1 1 CH2RCF Capture/Compare 2 Overcapture Flag mask. 2 1 CH3RCF Capture/Compare 3 Overcapture Flag mask. 3 1 TMR4 8-bit timer TMR 0x0 0x0 0x400 registers n TMR4 TIM4 update /overflow interrupt 23 AUTORLD AUTORLD auto-reload register 0x20 32 read-write n 0x0 0x0 RELOAD Autoreload Value mask. 0 8 CNT CNT counter 0x18 32 read-write n 0x0 0x0 CNT Counter Value mask. 0 8 CTRL1 CTRL1 control register 1 0x0 32 read-write n 0x0 0x0 ARBEN Auto-Reload Preload Enable mask. 7 1 CNTEN Counter Enable mask. 0 1 NGUE Update DIsable mask. 1 1 SPMEN One Pulse Mode mask. 3 1 UES Update Request Source mask. 2 1 CTRL2 CTRL2 control register 2 0x4 32 read-write n 0x0 0x0 MMFC Capture/Compare Preloaded Control mask. 4 3 DIV DIV divider register 0x1C 32 read-write n 0x0 0x0 DIV Prescaler Value mask. 0 3 INTCTRL INTCTRL interrupt enable register 0xC 32 read-write n 0x0 0x0 TRGIE Trigger Interrupt Enable mask. 6 1 UDIE Update Interrupt Enable mask. 0 1 SCEG SCEG event generation register 0x14 32 write-only n 0x0 0x0 TEG Trigger Generation mask. 6 1 UEG Update Generation mask. 0 1 SMC SMC Synchro mode control register 0x8 32 read-write n 0x0 0x0 ITC Trigger Selection mask. 4 3 MSMEN Slave Mode Selection mask. 7 1 SMFC Master/Slave Mode mask. 0 3 STS STS status register 1 0x10 32 write-only n 0x0 0x0 TRGIF Trigger Interrupt Flag mask. 6 1 UDIF Update Interrupt Flag mask. 0 1 UART1 Universal asynchronous receiver transmitter UART 0x0 0x0 0x400 registers n USART1_TX USART1 TX interrupt 17 USART1_RX USART1 RX interrupt 18 BR0 BR0 Baud rate register 2 0xC 32 read-write n 0x0 0x0 DIV15_12 MSB mantissa of UARTxDIV [15:12] mask 4 4 DIV3_0 Fraction bits of UARTxDIV [3:0] mask 0 4 BR1 BR1 Baud rate register 1 0x8 32 read-write n 0x0 0x0 DIV11_4 LSB mantissa of UARTxDIV [7:0] mask 0 8 CTRL1 CTRL1 Control register 1 0x10 32 read-write n 0x0 0x0 DBL Word length mask 4 1 PEN Parity Control Enable mask 2 1 PIE UARTx Parity Interrupt Enable mask 0 1 PSEL UARTx Parity Selection 1 1 RDB8 Receive Data bit 8 7 1 TDB8 Transmit data bit 8 6 1 UARTDIS UARTx Disable (for low power consumption) 5 1 WMS Wake-up method mask 3 1 CTRL2 CTRL2 Control register 2 0x14 32 read-write n 0x0 0x0 IDLEIE IDLEIE 4 1 RMM RMM 1 1 RXEN RXEN 2 1 RXIE RXIE 5 1 TXBRK TXBRK 0 1 TXCIE TXCIE 6 1 TXEN TXEN 3 1 TXIE TXIE 7 1 CTRL3 CTRL3 Control register 3 0x18 32 read-write n 0x0 0x0 CLKEN CLKEN 3 1 CLKPHA CLKPHA 1 1 CLKPOL CLKPOL 2 1 LBCP LBCP 0 1 LINEN LINEN 5 1 SBS SBS 4 1 CTRL4 CTRL4 Control register 4 0x1C 32 read-write n 0x0 0x0 ADDR ADDR 0 1 LMBDF LMBDF 1 1 LMBDIE LMBDIE 3 1 LMBDL LMBDL 2 1 CTRL5 CTRL5 Control register 5 0x20 32 read-write n 0x0 0x0 HDMEN HDMEN 3 1 ILPM ILPM 2 1 IRDAEN IRDAEN 1 1 NACKEN NACKEN 4 1 SMEN SMEN 5 1 DATA DATA Data register 0x4 32 read-write n 0x0 0x0 DATA Data value 0 9 DIV DIV UART1 prescaler register 0x28 32 read-write n 0x0 0x0 DIV DIV 8 8 GTS GTS Guard time and register 0x24 32 read-write n 0x0 0x0 GTS GTS 8 8 IOSW2 IOSW2 UART3 IO switch register 0x30 32 read-write n 0x0 0x0 SW SW 0 1 STS STS Status register 0x0 32 read-write n 0x0 0x0 FEF Framing error 1 1 read-only IDLEF IDLE line detected 4 1 read-only NEF Noise error flag 2 1 read-only OEF Overrun error 3 1 read-only PEF Parity error 0 1 read-only RXBNEF Read data register not empty 5 1 read-write TXBEF Transmit data register empty 7 1 read-only TXCF Transmission complete 6 1 read-write SW SW UART2/USART3 switch register 0x2C 32 read-write n 0x0 0x0 SW SW 0 1 UART2 Universal asynchronous receiver transmitter UART 0x0 0x0 0x400 registers n USART2_TX USART2 TX interrupt 27 USART2_RX USART2 RX interrupt 28 BR0 BR0 Baud rate register 2 0xC 32 read-write n 0x0 0x0 DIV15_12 MSB mantissa of UARTxDIV [15:12] mask 4 4 DIV3_0 Fraction bits of UARTxDIV [3:0] mask 0 4 BR1 BR1 Baud rate register 1 0x8 32 read-write n 0x0 0x0 DIV11_4 LSB mantissa of UARTxDIV [7:0] mask 0 8 CTRL1 CTRL1 Control register 1 0x10 32 read-write n 0x0 0x0 DBL Word length mask 4 1 PEN Parity Control Enable mask 2 1 PIE UARTx Parity Interrupt Enable mask 0 1 PSEL UARTx Parity Selection 1 1 RDB8 Receive Data bit 8 7 1 TDB8 Transmit data bit 8 6 1 UARTDIS UARTx Disable (for low power consumption) 5 1 WMS Wake-up method mask 3 1 CTRL2 CTRL2 Control register 2 0x14 32 read-write n 0x0 0x0 IDLEIE IDLEIE 4 1 RMM RMM 1 1 RXEN RXEN 2 1 RXIE RXIE 5 1 TXBRK TXBRK 0 1 TXCIE TXCIE 6 1 TXEN TXEN 3 1 TXIE TXIE 7 1 CTRL3 CTRL3 Control register 3 0x18 32 read-write n 0x0 0x0 CLKEN CLKEN 3 1 CLKPHA CLKPHA 1 1 CLKPOL CLKPOL 2 1 LBCP LBCP 0 1 LINEN LINEN 5 1 SBS SBS 4 1 CTRL4 CTRL4 Control register 4 0x1C 32 read-write n 0x0 0x0 ADDR ADDR 0 1 LMBDF LMBDF 1 1 LMBDIE LMBDIE 3 1 LMBDL LMBDL 2 1 CTRL5 CTRL5 Control register 5 0x20 32 read-write n 0x0 0x0 HDMEN HDMEN 3 1 ILPM ILPM 2 1 IRDAEN IRDAEN 1 1 NACKEN NACKEN 4 1 SMEN SMEN 5 1 DATA DATA Data register 0x4 32 read-write n 0x0 0x0 DATA Data value 0 9 DIV DIV UART1 prescaler register 0x28 32 read-write n 0x0 0x0 DIV DIV 8 8 GTS GTS Guard time and register 0x24 32 read-write n 0x0 0x0 GTS GTS 8 8 IOSW2 IOSW2 UART3 IO switch register 0x30 32 read-write n 0x0 0x0 SW SW 0 1 STS STS Status register 0x0 32 read-write n 0x0 0x0 FEF Framing error 1 1 read-only IDLEF IDLE line detected 4 1 read-only NEF Noise error flag 2 1 read-only OEF Overrun error 3 1 read-only PEF Parity error 0 1 read-only RXBNEF Read data register not empty 5 1 read-write TXBEF Transmit data register empty 7 1 read-only TXCF Transmission complete 6 1 read-write SW SW UART2/USART3 switch register 0x2C 32 read-write n 0x0 0x0 SW SW 0 1 UART3 Universal asynchronous receiver transmitter UART 0x0 0x0 0x400 registers n USART3_TX USART3 TX interrupt 25 USART3_RX USART3 RX interrupt 26 BR0 BR0 Baud rate register 2 0xC 32 read-write n 0x0 0x0 DIV15_12 MSB mantissa of UARTxDIV [15:12] mask 4 4 DIV3_0 Fraction bits of UARTxDIV [3:0] mask 0 4 BR1 BR1 Baud rate register 1 0x8 32 read-write n 0x0 0x0 DIV11_4 LSB mantissa of UARTxDIV [7:0] mask 0 8 CTRL1 CTRL1 Control register 1 0x10 32 read-write n 0x0 0x0 DBL Word length mask 4 1 PEN Parity Control Enable mask 2 1 PIE UARTx Parity Interrupt Enable mask 0 1 PSEL UARTx Parity Selection 1 1 RDB8 Receive Data bit 8 7 1 TDB8 Transmit data bit 8 6 1 UARTDIS UARTx Disable (for low power consumption) 5 1 WMS Wake-up method mask 3 1 CTRL2 CTRL2 Control register 2 0x14 32 read-write n 0x0 0x0 IDLEIE IDLEIE 4 1 RMM RMM 1 1 RXEN RXEN 2 1 RXIE RXIE 5 1 TXBRK TXBRK 0 1 TXCIE TXCIE 6 1 TXEN TXEN 3 1 TXIE TXIE 7 1 CTRL3 CTRL3 Control register 3 0x18 32 read-write n 0x0 0x0 CLKEN CLKEN 3 1 CLKPHA CLKPHA 1 1 CLKPOL CLKPOL 2 1 LBCP LBCP 0 1 LINEN LINEN 5 1 SBS SBS 4 1 CTRL4 CTRL4 Control register 4 0x1C 32 read-write n 0x0 0x0 ADDR ADDR 0 1 LMBDF LMBDF 1 1 LMBDIE LMBDIE 3 1 LMBDL LMBDL 2 1 CTRL5 CTRL5 Control register 5 0x20 32 read-write n 0x0 0x0 HDMEN HDMEN 3 1 ILPM ILPM 2 1 IRDAEN IRDAEN 1 1 NACKEN NACKEN 4 1 SMEN SMEN 5 1 DATA DATA Data register 0x4 32 read-write n 0x0 0x0 DATA Data value 0 9 DIV DIV UART1 prescaler register 0x28 32 read-write n 0x0 0x0 DIV DIV 8 8 GTS GTS Guard time and register 0x24 32 read-write n 0x0 0x0 GTS GTS 8 8 IOSW2 IOSW2 UART3 IO switch register 0x30 32 read-write n 0x0 0x0 SW SW 0 1 STS STS Status register 0x0 32 read-write n 0x0 0x0 FEF Framing error 1 1 read-only IDLEF IDLE line detected 4 1 read-only NEF Noise error flag 2 1 read-only OEF Overrun error 3 1 read-only PEF Parity error 0 1 read-only RXBNEF Read data register not empty 5 1 read-write TXBEF Transmit data register empty 7 1 read-only TXCF Transmission complete 6 1 read-write SW SW UART2/USART3 switch register 0x2C 32 read-write n 0x0 0x0 SW SW 0 1 WUPT Auto wake up WUPT 0x0 0x0 0x400 registers n WUPT Auto wake up from halt interrupt 1 CSTS CSTS WUPT Control status register 0x0 32 read-write n 0x0 0x0 CFMEN LSI Measurement enable mask 0 1 WUPIF Interrupt flag mask 5 1 WUPTEN Auto Wake-up enable mask 4 1 DIV DIV WUPT Asynchronous prescaler buffer 0x4 32 read-write n 0x0 0x0 DIV Asynchronous Prescaler divider mask 0 6 TBC TBC WUPT Time base selection register 0x8 32 write-only n 0x0 0x0 TBC Timebase selection mask 0 4 WWDT Window Watchdog WWDT 0x0 0x0 0x400 registers n CTRL CTRL Control Register 0x0 32 read-write n 0x0 0x0 CNT CNT 0 7 WWDTEN WWDTEN 7 1 WDDATA WDDATA Window Register 0x4 32 read-write n 0x0 0x0 WINCNT WINCNT 0 7 WWDTEN WWDTEN 7 1