APEXMIC
APM32F103xx
2024.04.19
APM32F103xx SVD test APM32F10xxx ARM 32-bit Cortex-M3 Microcontroller based device
CM3
r2p1
little
true
4
false
8
32
ADC1
Analog to digital converter
ADC
0x0
0x0
0x400
registers
n
ADC1_2
ADC1 global interrupt
18
AWDHT
AWDHT
watchdog higher threshold register
0x24
32
read-write
n
0x0
0x0
AWDHT
Analog watchdog higher threshold
0
12
AWDLT
AWDLT
watchdog lower threshold register
0x28
32
read-write
n
0x0
0x0
AWDLT
Analog watchdog lower threshold
0
12
CTRL1
CTRL1
control register 1
0x4
32
read-write
n
0x0
0x0
AWDCS
Analog watchdog channel select bits
0
5
AWDIEN
Analog watchdog interrupt enable
6
1
AWDSC
Enable the watchdog on a single channel in scan mode
9
1
DMCC
Discontinuous mode channel count
13
3
DMS
Dual mode selection
16
4
EOCIEN
Interrupt enable for EOC
5
1
IJAEN
Automatic injected group conversion
10
1
IJAWDEN
Analog watchdog enable on injected channels
22
1
IJDMEN
Discontinuous mode on injected channels
12
1
IJEOCIEN
Interrupt enable for injected channels
7
1
RGAWDEN
Analog watchdog enable on regular channels
23
1
RGDMEN
Discontinuous mode on regular channels
11
1
SMEN
Scan mode
8
1
CTRL2
CTRL2
control register 2
0x8
32
read-write
n
0x0
0x0
ADCON
A/D converter ON / OFF
0
1
CALRST
Reset calibration
3
1
CALSTR
A/D calibration
2
1
CCM
Continuous conversion
1
1
DAM
Data alignment
11
1
DMAEN
Direct memory access mode
8
1
IJEXTGEN
External trigger conversion mode for injected channels
15
1
IJEXTSEL
External event select for injected group
12
3
IJSWSTR
Start conversion of injected channels
21
1
RGEXTGEN
External trigger conversion mode for regular channels
20
1
RGEXTSEL
External event select for regular group
17
3
RGSWSTR
Start conversion of regular channels
22
1
TVEN
Temperature sensor and VREFINT enable
23
1
IJD1
IJD1
injected data register x
0x3C
32
read-only
n
0x0
0x0
IJD
Injected data
0
16
IJD2
IJD2
injected data register x
0x40
32
read-only
n
0x0
0x0
IJD
Injected data
0
16
IJD3
IJD3
injected data register x
0x44
32
read-only
n
0x0
0x0
IJD
Injected data
0
16
IJD4
IJD4
injected data register x
0x48
32
read-only
n
0x0
0x0
IJD
Injected data
0
16
IJOF1
IJOF1
injected channel data offset register x
0x14
32
read-write
n
0x0
0x0
OFFSET1
Data offset for injected channel x
0
12
IJOF2
IJOF2
injected channel data offset register x
0x18
32
read-write
n
0x0
0x0
OFFSET2
Data offset for injected channel x
0
12
IJOF3
IJOF3
injected channel data offset register x
0x1C
32
read-write
n
0x0
0x0
OFFSET3
Data offset for injected channel x
0
12
IJOF4
IJOF4
injected channel data offset register x
0x20
32
read-write
n
0x0
0x0
OFFSET4
Data offset for injected channel x
0
12
IJSQ
IJSQ
injected sequence register
0x38
32
read-write
n
0x0
0x0
IJSL
Injected sequence length
20
2
IJSQ1
1st conversion in injected sequence
0
5
IJSQ2
2nd conversion in injected sequence
5
5
IJSQ3
3rd conversion in injected sequence
10
5
IJSQ4
4th conversion in injected sequence
15
5
RDG
RDG
regular data register
0x4C
32
read-only
n
0x0
0x0
ADC2DATA
ADC2 data
16
16
RDATA
Regular data
0
16
RGSQ1
RGSQ1
regular sequence register 1
0x2C
32
read-write
n
0x0
0x0
RGSL
Regular channel sequence length
20
4
RGSQ13
13th conversion in regular sequence
0
5
RGSQ14
14th conversion in regular sequence
5
5
RGSQ15
15th conversion in regular sequence
10
5
RGSQ16
16th conversion in regular sequence
15
5
RGSQ2
RGSQ2
regular sequence register 2
0x30
32
read-write
n
0x0
0x0
RGSQ10
10th conversion in regular sequence
15
5
RGSQ11
11th conversion in regular sequence
20
5
RGSQ12
12th conversion in regular sequence
25
5
RGSQ7
7th conversion in regular sequence
0
5
RGSQ8
8th conversion in regular sequence
5
5
RGSQ9
9th conversion in regular sequence
10
5
RGSQ3
RGSQ3
regular sequence register 3
0x34
32
read-write
n
0x0
0x0
RGSQ1
1st conversion in regular sequence
0
5
RGSQ2
2nd conversion in regular sequence
5
5
RGSQ3
3rd conversion in regular sequence
10
5
RGSQ4
4th conversion in regular sequence
15
5
RGSQ5
5th conversion in regular sequence
20
5
RGSQ6
6th conversion in regular sequence
25
5
SMPT1
SMPT1
sample time register 1
0xC
32
read-write
n
0x0
0x0
SMPT10
Channel 10 sample time selection
0
3
SMPT11
Channel 11 sample time selection
3
3
SMPT12
Channel 12 sample time selection
6
3
SMPT13
Channel 13 sample time selection
9
3
SMPT14
Channel 14 sample time selection
12
3
SMPT15
Channel 15 sample time selection
15
3
SMPT16
Channel 16 sample time selection
18
3
SMPT17
Channel 17 sample time selection
21
3
SMPT2
SMPT2
sample time register 2
0x10
32
read-write
n
0x0
0x0
SMPT0
Channel 0 sample time selection
0
3
SMPT1
Channel 1 sample time selection
3
3
SMPT2
Channel 2 sample time selection
6
3
SMPT3
Channel 3 sample time selection
9
3
SMPT4
Channel 4 sample time selection
12
3
SMPT5
Channel 5 sample time selection
15
3
SMPT6
Channel 6 sample time selection
18
3
SMPT7
Channel 7 sample time selection
21
3
SMPT8
Channel 8 sample time selection
24
3
SMPT9
Channel 9 sample time selection
27
3
STS
STS
status register
0x0
32
read-write
n
0x0
0x0
AWDF
Analog watchdog flag
0
1
CCF
Regular channel end of conversion
1
1
IJEOCF
Injected channel end of conversion
2
1
IJSTRF
Injected channel start flag
3
1
STRT
Regular channel start flag
4
1
ADC2
Analog to digital converter
ADC
0x0
0x0
0x400
registers
n
ADC1_2
ADC2 global interrupt
18
AWDHT
AWDHT
watchdog higher threshold register
0x24
32
read-write
n
0x0
0x0
AWDHT
Analog watchdog higher threshold
0
12
AWDLT
AWDLT
watchdog lower threshold register
0x28
32
read-write
n
0x0
0x0
AWDLT
Analog watchdog lower threshold
0
12
CTRL1
CTRL1
control register 1
0x4
32
read-write
n
0x0
0x0
AWDCS
Analog watchdog channel select bits
0
5
AWDIEN
Analog watchdog interrupt enable
6
1
AWDSC
Enable the watchdog on a single channel in scan mode
9
1
DMCC
Discontinuous mode channel count
13
3
DMS
Dual mode selection
16
4
EOCIEN
Interrupt enable for EOC
5
1
IJAEN
Automatic injected group conversion
10
1
IJAWDEN
Analog watchdog enable on injected channels
22
1
IJDMEN
Discontinuous mode on injected channels
12
1
IJEOCIEN
Interrupt enable for injected channels
7
1
RGAWDEN
Analog watchdog enable on regular channels
23
1
RGDMEN
Discontinuous mode on regular channels
11
1
SMEN
Scan mode
8
1
CTRL2
CTRL2
control register 2
0x8
32
read-write
n
0x0
0x0
ADCON
A/D converter ON / OFF
0
1
CALRST
Reset calibration
3
1
CALSTR
A/D calibration
2
1
CCM
Continuous conversion
1
1
DAM
Data alignment
11
1
DMAEN
Direct memory access mode
8
1
IJEXTGEN
External trigger conversion mode for injected channels
15
1
IJEXTSEL
External event select for injected group
12
3
IJSWSTR
Start conversion of injected channels
21
1
RGEXTGEN
External trigger conversion mode for regular channels
20
1
RGEXTSEL
External event select for regular group
17
3
RGSWSTR
Start conversion of regular channels
22
1
TVEN
Temperature sensor and VREFINT enable
23
1
IJD1
IJD1
injected data register x
0x3C
32
read-only
n
0x0
0x0
IJD
Injected data
0
16
IJD2
IJD2
injected data register x
0x40
32
read-only
n
0x0
0x0
IJD
Injected data
0
16
IJD3
IJD3
injected data register x
0x44
32
read-only
n
0x0
0x0
IJD
Injected data
0
16
IJD4
IJD4
injected data register x
0x48
32
read-only
n
0x0
0x0
IJD
Injected data
0
16
IJOF1
IJOF1
injected channel data offset register x
0x14
32
read-write
n
0x0
0x0
OFFSET1
Data offset for injected channel x
0
12
IJOF2
IJOF2
injected channel data offset register x
0x18
32
read-write
n
0x0
0x0
OFFSET2
Data offset for injected channel x
0
12
IJOF3
IJOF3
injected channel data offset register x
0x1C
32
read-write
n
0x0
0x0
OFFSET3
Data offset for injected channel x
0
12
IJOF4
IJOF4
injected channel data offset register x
0x20
32
read-write
n
0x0
0x0
OFFSET4
Data offset for injected channel x
0
12
IJSQ
IJSQ
injected sequence register
0x38
32
read-write
n
0x0
0x0
IJSL
Injected sequence length
20
2
IJSQ1
1st conversion in injected sequence
0
5
IJSQ2
2nd conversion in injected sequence
5
5
IJSQ3
3rd conversion in injected sequence
10
5
IJSQ4
4th conversion in injected sequence
15
5
RDG
RDG
regular data register
0x4C
32
read-only
n
0x0
0x0
ADC2DATA
ADC2 data
16
16
RDATA
Regular data
0
16
RGSQ1
RGSQ1
regular sequence register 1
0x2C
32
read-write
n
0x0
0x0
RGSL
Regular channel sequence length
20
4
RGSQ13
13th conversion in regular sequence
0
5
RGSQ14
14th conversion in regular sequence
5
5
RGSQ15
15th conversion in regular sequence
10
5
RGSQ16
16th conversion in regular sequence
15
5
RGSQ2
RGSQ2
regular sequence register 2
0x30
32
read-write
n
0x0
0x0
RGSQ10
10th conversion in regular sequence
15
5
RGSQ11
11th conversion in regular sequence
20
5
RGSQ12
12th conversion in regular sequence
25
5
RGSQ7
7th conversion in regular sequence
0
5
RGSQ8
8th conversion in regular sequence
5
5
RGSQ9
9th conversion in regular sequence
10
5
RGSQ3
RGSQ3
regular sequence register 3
0x34
32
read-write
n
0x0
0x0
RGSQ1
1st conversion in regular sequence
0
5
RGSQ2
2nd conversion in regular sequence
5
5
RGSQ3
3rd conversion in regular sequence
10
5
RGSQ4
4th conversion in regular sequence
15
5
RGSQ5
5th conversion in regular sequence
20
5
RGSQ6
6th conversion in regular sequence
25
5
SMPT1
SMPT1
sample time register 1
0xC
32
read-write
n
0x0
0x0
SMPT10
Channel 10 sample time selection
0
3
SMPT11
Channel 11 sample time selection
3
3
SMPT12
Channel 12 sample time selection
6
3
SMPT13
Channel 13 sample time selection
9
3
SMPT14
Channel 14 sample time selection
12
3
SMPT15
Channel 15 sample time selection
15
3
SMPT16
Channel 16 sample time selection
18
3
SMPT17
Channel 17 sample time selection
21
3
SMPT2
SMPT2
sample time register 2
0x10
32
read-write
n
0x0
0x0
SMPT0
Channel 0 sample time selection
0
3
SMPT1
Channel 1 sample time selection
3
3
SMPT2
Channel 2 sample time selection
6
3
SMPT3
Channel 3 sample time selection
9
3
SMPT4
Channel 4 sample time selection
12
3
SMPT5
Channel 5 sample time selection
15
3
SMPT6
Channel 6 sample time selection
18
3
SMPT7
Channel 7 sample time selection
21
3
SMPT8
Channel 8 sample time selection
24
3
SMPT9
Channel 9 sample time selection
27
3
STS
STS
status register
0x0
32
read-write
n
0x0
0x0
AWDF
Analog watchdog flag
0
1
CCF
Regular channel end of conversion
1
1
IJEOCF
Injected channel end of conversion
2
1
IJSTRF
Injected channel start flag
3
1
STRT
Regular channel start flag
4
1
AFIO
Alternate function I/O
AFIO
0x0
0x0
0x400
registers
n
EINTCFG1
EINTCFG1
External interrupt configuration register1 (AFIO_EINTCFG1)
0x8
32
read-write
n
0x0
0x0
EINT0
EINT 0 configuration
0
4
EINT1
EINT 1 configuration
4
4
EINT2
EINT 2 configuration
8
4
EINT3
EINT 3 configuration
12
4
EINTCFG2
EINTCFG2
External interrupt configuration register2 (AFIO_EINTCFG2)
0xC
32
read-write
n
0x0
0x0
EINT4
EINT 4 configuration
0
4
EINT5
EINT 5 configuration
4
4
EINT6
EINT 6 configuration
8
4
EINT7
EINT 7 configuration
12
4
EINTCFG3
EINTCFG3
External interrupt configuration register3 (AFIO_EINTCFG3)
0x10
32
read-write
n
0x0
0x0
EINT10
EINT 10 configuration
8
4
EINT11
EINT 11 configuration
12
4
EINT8
EINT 8 configuration
0
4
EINT9
EINT 9 configuration
4
4
EINTCFG4
EINTCFG4
External interrupt configuration register4 (AFIO_EINTCFG4)
0x14
32
read-write
n
0x0
0x0
EINT12
EINT 12 configuration
0
4
EINT13
EINT 13 configuration
4
4
EINT14
EINT 14 configuration
8
4
EINT15
EINT 15 configuration
12
4
EVCTRL
EVCTRL
Event control register (AFIO_EVCTRL)
0x0
32
read-write
n
0x0
0x0
EVOEN
EVOEN
7
1
PINSEL
PINSEL
0
4
PORTSEL
PORTSEL
4
3
REMAP
REMAP
Alternate function IO remap and Serial wire JTAG configuration register (AFIO_REMAP)
0x4
32
read-write
n
0x0
0x0
ADC1_ETI_REMAP
ADC 1 External trigger injected conversion remapping
17
1
ADC1_ETR_REMAP
ADC 1 external trigger regular conversion remapping
18
1
ADC2_ETI_REMAP
ADC 2 external trigger injected conversion remapping
19
1
ADC2_ETR_REMAP
ADC 2 external trigger regular conversion remapping
20
1
CAN_REMAP
CAN alternate function remapping
13
2
I2C1_REMAP
I2C1 remapping
1
1
PD01_REMAP
Port D0/Port D1 mapping on OSC_IN/OSC_OUT
15
1
SPI1_REMAP
SPI1 remapping
0
1
SWJ_CFG
Serial wire JTAG configuration
24
3
TMR1_REMAP
TMR1 remapping
6
2
TMR2_REMAP
TMR2 remapping
8
2
TMR3_REMAP
TMR3 remapping
10
2
TMR4_REMAP
TMR4 remapping
12
1
TMR5_CH4_REMAP
TMR5 channel4 internal remap
16
1
USART1_REMAP
USART1 remapping
2
1
USART2_REMAP
USART2 remapping
3
1
USART3_REMAP
USART3 remapping
4
2
REMAP2
REMAP2
Alternate function IO remap register2 (AFIO_REMAP2)
0x18
32
read-write
n
0x0
0x0
EMMC_NADV
NADV connect/disconnect
10
1
TMR10_REMAP
TMR10 remapping
6
1
TMR11_REMAP
TMR11 remapping
7
1
TMR13_REMAP
TMR13 remapping
8
1
TMR14_REMAP
TMR14 remapping
9
1
TMR9_REMAP
TMR9 remapping
5
1
BAKR
Bakr registers
BAKR
0x0
0x0
0x400
registers
n
CTRL
CTRL
Bakr control register (BAKR_CTRL_B)
0x30
32
read-write
n
0x0
0x0
TPEN
Tamper pin enable
0
1
TPTM
Tamper pin active level
1
1
CTRLF
CTRLF
BAKR_CSR control/status register (BAKR_CTRLF)
0x34
32
read-write
n
0x0
0x0
RTPEF
Clear Tamper event
0
1
write-only
RTPIF
Clear Tamper Interrupt
1
1
write-only
TPEF
Tamper Event Flag
8
1
read-only
TPIEN
Tamper Pin interrupt enable
2
1
read-write
TPIF
Tamper Interrupt Flag
9
1
read-only
DATA1
DATA1
Bakr data register (BAKR_DATA)
0x4
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA10
DATA10
Bakr data register (BAKR_DATA)
0x28
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA11
DATA11
Bakr data register (BAKR_DATA)
0x40
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA12
DATA12
Bakr data register (BAKR_DATA)
0x44
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA13
DATA13
Bakr data register (BAKR_DATA)
0x48
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA14
DATA14
Bakr data register (BAKR_DATA)
0x4C
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA15
DATA15
Bakr data register (BAKR_DATA)
0x50
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA16
DATA16
Bakr data register (BAKR_DATA)
0x54
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA17
DATA17
Bakr data register (BAKR_DATA)
0x58
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA18
DATA18
Bakr data register (BAKR_DATA)
0x5C
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA19
DATA19
Bakr data register (BAKR_DATA)
0x60
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA2
DATA2
Bakr data register (BAKR_DATA)
0x8
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA20
DATA20
Bakr data register (BAKR_DATA)
0x64
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA21
DATA21
Bakr data register (BAKR_DATA)
0x68
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA22
DATA22
Bakr data register (BAKR_DATA)
0x6C
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA23
DATA23
Bakr data register (BAKR_DATA)
0x70
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA24
DATA24
Bakr data register (BAKR_DATA)
0x74
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA25
DATA25
Bakr data register (BAKR_DATA)
0x78
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA26
DATA26
Bakr data register (BAKR_DATA)
0x7C
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA27
DATA27
Bakr data register (BAKR_DATA)
0x80
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA28
DATA28
Bakr data register (BAKR_DATA)
0x84
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA29
DATA29
Bakr data register (BAKR_DATA)
0x88
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA3
DATA3
Bakr data register (BAKR_DATA)
0xC
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA30
DATA30
Bakr data register (BAKR_DATA)
0x8C
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA31
DATA31
Bakr data register (BAKR_DATA)
0x90
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA32
DATA32
Bakr data register (BAKR_DATA)
0x94
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA33
DATA33
Bakr data register (BAKR_DATA)
0x98
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA34
DATA34
Bakr data register (BAKR_DATA)
0x9C
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA35
DATA35
Bakr data register (BAKR_DATA)
0xA0
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA36
DATA36
Bakr data register (BAKR_DATA)
0xA4
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA37
DATA37
Bakr data register (BAKR_DATA)
0xA8
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA38
DATA38
Bakr data register (BAKR_DATA)
0xAC
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA39
DATA39
Bakr data register (BAKR_DATA)
0xB0
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA4
DATA4
Bakr data register (BAKR_DATA)
0x10
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA40
DATA40
Bakr data register (BAKR_DATA)
0xB4
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA41
DATA41
Bakr data register (BAKR_DATA)
0xB8
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA42
DATA42
Bakr data register (BAKR_DATA)
0xBC
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA5
DATA5
Bakr data register (BAKR_DATA)
0x14
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA6
DATA6
Bakr data register (BAKR_DATA)
0x18
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA7
DATA7
Bakr data register (BAKR_DATA)
0x1C
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA8
DATA8
Bakr data register (BAKR_DATA)
0x20
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
DATA9
DATA9
Bakr data register (BAKR_DATA)
0x24
32
read-write
n
0x0
0x0
DATA
Bakr data
0
16
RTCCTRL
RTCCTRL
RTC clock calibration register (BAKR_RTCCTRL)
0x2C
32
read-write
n
0x0
0x0
ASOC
Alarm or second output selection
9
1
ASOEN
Alarm or second output enable
8
1
CALP
Calibration value
0
7
RTCO
Calibration Clock Output
7
1
CAN
Controller area network
CAN
0x0
0x0
0x400
registers
n
USB_HP_CAN1_TX
SB HP and CAN1 TX interrupts
19
USB_LP_CAN1_RX0
USB LP and CAN1 RX0 interrupts
20
CAN1_RX1
CAN1 RX1 interrupt
21
CAN1_SCE
CAN1 SCE interrupt
22
BT
BT
CAN Bit Time register
0x1C
32
read-write
n
0x0
0x0
BRD
BRD
0
10
LBM
LBM
30
1
RSJW
RSJW
24
2
SILM
SILM
31
1
TS1
TS1
16
4
TS2
TS2
20
3
ESTS
ESTS
CAN Error States register
0x18
32
read-write
n
0x0
0x0
BOF
BOF
2
1
read-only
EPF
EPF
1
1
read-only
EWF
EWF
0
1
read-only
LEC
LEC
4
3
read-write
RXEC
RXEC
24
8
read-only
TXEC
TXEC
16
8
read-only
F01
F01
Filter bank 0 register 1
0x240
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F02
F02
Filter bank 0 register 2
0x244
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F101
F101
Filter bank 10 register 1
0x290
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F102
F102
Filter bank 10 register 2
0x294
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F11
F11
Filter bank 1 register 1
0x248
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F111
F111
Filter bank 11 register 1
0x298
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F112
F112
Filter bank 11 register 2
0x29C
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F12
F12
Filter bank 1 register 2
0x24C
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F121
F121
Filter bank 4 register 1
0x2A0
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F122
F122
Filter bank 12 register 2
0x2A4
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F131
F131
Filter bank 13 register 1
0x2A8
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F132
F132
Filter bank 13 register 2
0x2AC
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F21
F21
Filter bank 2 register 1
0x250
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F22
F22
Filter bank 2 register 2
0x254
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F31
F31
Filter bank 3 register 1
0x258
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F32
F32
Filter bank 3 register 2
0x25C
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F41
F41
Filter bank 4 register 1
0x260
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F42
F42
Filter bank 4 register 2
0x264
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F51
F51
Filter bank 5 register 1
0x268
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F52
F52
Filter bank 5 register 2
0x26C
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F61
F61
Filter bank 6 register 1
0x270
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F62
F62
Filter bank 6 register 2
0x274
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F71
F71
Filter bank 7 register 1
0x278
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F72
F72
Filter bank 7 register 2
0x27C
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F81
F81
Filter bank 8 register 1
0x280
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F82
F82
Filter bank 8 register 2
0x284
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F91
F91
Filter bank 9 register 1
0x288
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
F92
F92
Filter bank 9 register 2
0x28C
32
read-write
n
0x0
0x0
FB1
Filter bits
0
1
FB10
Filter bits
9
1
FB11
Filter bits
10
1
FB12
Filter bits
11
1
FB13
Filter bits
12
1
FB14
Filter bits
13
1
FB15
Filter bits
14
1
FB16
Filter bits
15
1
FB17
Filter bits
16
1
FB18
Filter bits
17
1
FB19
Filter bits
18
1
FB2
Filter bits
1
1
FB20
Filter bits
19
1
FB21
Filter bits
20
1
FB22
Filter bits
21
1
FB23
Filter bits
22
1
FB24
Filter bits
23
1
FB25
Filter bits
24
1
FB26
Filter bits
25
1
FB27
Filter bits
26
1
FB28
Filter bits
27
1
FB29
Filter bits
28
1
FB3
Filter bits
2
1
FB30
Filter bits
29
1
FB31
Filter bits
30
1
FB32
Filter bits
31
1
FB4
Filter bits
3
1
FB5
Filter bits
4
1
FB6
Filter bits
5
1
FB7
Filter bits
6
1
FB8
Filter bits
7
1
FB9
Filter bits
8
1
FBW
FBW
CAN Filter bit width register
0x20C
32
read-write
n
0x0
0x0
BW1
Filter bit
0
1
BW10
Filter bit
9
1
BW11
Filter bit
10
1
BW12
Filter bit
11
1
BW13
Filter bit
12
1
BW14
Filter bit
13
1
BW15
Filter bit
14
1
BW16
Filter bit
15
1
BW17
Filter bit
16
1
BW18
Filter bit
17
1
BW19
Filter bit
18
1
BW2
Filter bit
1
1
BW20
Filter bit
19
1
BW21
Filter bit
20
1
BW22
Filter bit
21
1
BW23
Filter bit
23
1
BW24
Filter bit
24
1
BW25
Filter bit
25
1
BW26
Filter bit
26
1
BW27
Filter bit
27
1
BW28
Filter bit
28
1
BW3
Filter bit
2
1
BW4
Filter bit
3
1
BW5
Filter bit
4
1
BW6
Filter bit
5
1
BW7
Filter bit
6
1
BW8
Filter bit
7
1
BW9
Filter bit
8
1
FEN
FEN
CAN Filter activation register
0x21C
32
read-write
n
0x0
0x0
FEN1
Filter active
0
1
FEN10
Filter active
9
1
FEN11
Filter active
10
1
FEN12
Filter active
11
1
FEN13
Filter active
12
1
FEN14
Filter active
13
1
FEN15
Filter active
14
1
FEN16
Filter active
15
1
FEN17
Filter active
16
1
FEN18
Filter active
17
1
FEN19
Filter active
18
1
FEN2
Filter active
1
1
FEN20
Filter active
19
1
FEN21
Filter active
20
1
FEN22
Filter active
21
1
FEN23
Filter active
23
1
FEN24
Filter active
24
1
FEN25
Filter active
25
1
FEN26
Filter active
26
1
FEN27
Filter active
27
1
FEN28
Filter active
28
1
FEN3
Filter active
2
1
FEN4
Filter active
3
1
FEN5
Filter active
4
1
FEN6
Filter active
5
1
FEN7
Filter active
6
1
FEN8
Filter active
7
1
FEN9
Filter active
8
1
FFA
FFA
CAN Filter FIFO associated registers
0x214
32
read-write
n
0x0
0x0
FFA1
Filter FIFO assignment for filter
0
1
FFA10
Filter FIFO assignment for filter
9
1
FFA11
Filter FIFO assignment for filter
10
1
FFA12
Filter FIFO assignment for filter
11
1
FFA13
Filter FIFO assignment for filter
12
1
FFA14
Filter FIFO assignment for filter
13
1
FFA15
Filter FIFO assignment for filter
14
1
FFA16
Filter FIFO assignment for filter
15
1
FFA17
Filter FIFO assignment for filter
16
1
FFA18
Filter FIFO assignment for filter
17
1
FFA19
Filter FIFO assignment for filter
18
1
FFA2
Filter FIFO assignment for filter
1
1
FFA20
Filter FIFO assignment for filter
19
1
FFA21
Filter FIFO assignment for filter
20
1
FFA22
Filter FIFO assignment for filter
21
1
FFA23
Filter FIFO assignment for filter
23
1
FFA24
Filter FIFO assignment for filter
24
1
FFA25
Filter FIFO assignment for filter
25
1
FFA26
Filter FIFO assignment for filter
26
1
FFA27
Filter FIFO assignment for filter
27
1
FFA28
Filter FIFO assignment for filter
28
1
FFA3
Filter FIFO assignment for filter
2
1
FFA4
Filter FIFO assignment for filter
3
1
FFA5
Filter FIFO assignment for filter
4
1
FFA6
Filter FIFO assignment for filter
5
1
FFA7
Filter FIFO assignment for filter
6
1
FFA8
Filter FIFO assignment for filter
7
1
FFA9
Filter FIFO assignment for filter
8
1
FM
FM
CAN Filter register
0x204
32
read-write
n
0x0
0x0
FBM1
Filter mode
0
1
FBM10
Filter mode
9
1
FBM11
Filter mode
10
1
FBM12
Filter mode
11
1
FBM13
Filter mode
12
1
FBM14
Filter mode
13
1
FBM15
Filter mode
14
1
FBM16
Filter mode
15
1
FBM17
Filter mode
16
1
FBM18
Filter mode
17
1
FBM19
Filter mode
18
1
FBM2
Filter mode
1
1
FBM20
Filter mode
19
1
FBM21
Filter mode
20
1
FBM22
Filter mode
21
1
FBM23
Filter mode
23
1
FBM24
Filter mode
24
1
FBM25
Filter mode
25
1
FBM26
Filter mode
26
1
FBM27
Filter mode
27
1
FBM28
Filter mode
28
1
FBM3
Filter mode
2
1
FBM4
Filter mode
3
1
FBM5
Filter mode
4
1
FBM6
Filter mode
5
1
FBM7
Filter mode
6
1
FBM8
Filter mode
7
1
FBM9
Filter mode
8
1
FMCTRL
FMCTRL
CAN Filter the master control register
0x200
32
read-write
n
0x0
0x0
FINIT
FINIT
0
1
IEN
IEN
CAN Interrupts register
0x14
32
read-write
n
0x0
0x0
BOFIEN
BOFIEN
10
1
EORMIEN
EORMIEN
0
1
EPVIEN
EPVIEN
9
1
ERRIEN
ERRIEN
15
1
EWGIEN
EWGIEN
8
1
FFIEN1
FFIEN1
2
1
FFIEN2
FFIEN2
5
1
FMNPIEN1
FMNPIEN1
1
1
FMNPIEN2
FMNPIEN2
4
1
FOFIEN1
FOFIEN1
3
1
FOFIEN2
FOFIEN2
6
1
LECIEN
LECIEN
11
1
SLPIEN
SLPIEN
17
1
WUPIEN
WUPIEN
16
1
MCTRL
MCTRL
CAN Master control register
0x0
32
read-write
n
0x0
0x0
ABOM
ABOM
6
1
ARTDIS
ARTDIS
4
1
AWUPM
AWUPM
5
1
DBF
DBF
16
1
INIT
INIT
0
1
RESET
RESET
15
1
RFLOCK
RFLOCK
3
1
SLEEP
SLEEP
1
1
TTCM
TTCM
7
1
TX_PS
TX_PS
2
1
MSTS
MSTS
CAN Master States register
0x4
32
read-write
n
0x0
0x0
ERRIF
ERRIF
2
1
read-write
INITF
INITF
0
1
read-only
LST_SAMP
LST_SAMP
10
1
read-only
RX
RX
9
1
read-only
RX_L
RX_L
11
1
read-only
SLAK
SLAK
1
1
read-only
SLPIF
SLPIF
4
1
read-write
TX
TX
8
1
read-only
WUPIF
WUPIF
3
1
read-write
RF1
RF1
CAN Receive FIFO1 register
0xC
32
read-write
n
0x0
0x0
FMNP1
FMNP1
0
2
read-only
FOF1
FOF1
4
1
read-write
FULL1
FULL1
3
1
read-write
RFOM1
RFOM1
5
1
read-write
RF2
RF2
CAN Receive FIFO2 register
0x10
32
read-write
n
0x0
0x0
FMNP2
FMNP2
0
2
read-only
FOF2
FOF2
4
1
read-write
FULL2
FULL2
3
1
read-write
RFOM2
RFOM2
5
1
read-write
RXDH0
RXDH0
CAN receive mailbox High byte data register 0
0x1BC
32
read-only
n
0x0
0x0
DATA5
DATA5
0
8
DATA6
DATA6
8
8
DATA7
DATA7
16
8
DATA8
DATA8
24
8
RXDH1
RXDH1
CAN receive mailbox High byte data register 1
0x1CC
32
read-only
n
0x0
0x0
DATA5
DATA5
0
8
DATA6
DATA6
8
8
DATA7
DATA7
16
8
DATA8
DATA8
24
8
RXDL0
RXDL0
CAN receive mailbox low byte data register 0
0x1B8
32
read-only
n
0x0
0x0
DATA1
DATA1
0
8
DATA2
DATA2
8
8
DATA3
DATA3
16
8
DATA4
DATA4
24
8
RXDL1
RXDL1
CAN receive mailbox low byte data register 1
0x1C8
32
read-only
n
0x0
0x0
DATA1
DATA1
0
8
DATA2
DATA2
8
8
DATA3
DATA3
16
8
DATA4
DATA4
24
8
RXDLT0
RXDLT0
CAN receive the mailbox data length and timestamp register 0
0x1B4
32
read-only
n
0x0
0x0
FMI
FMI
8
8
MTS
MTS
16
16
RXDL
RXDL
0
4
RXDLT1
RXDLT1
CAN receive the mailbox data length and timestamp register 1
0x1C4
32
read-only
n
0x0
0x0
FMI
FMI
8
8
MTS
MTS
16
16
RXDL
RXDL
0
4
RXI0
RXI0
CAN Each mailbox contains the receive mailbox identifier register 0
0x1B0
32
read-only
n
0x0
0x0
EXID
EXID
3
18
EXIDEN
EXIDEN
2
1
RTR
RTR
1
1
STID
STID
21
11
RXI1
RXI1
CAN Each mailbox contains the receive mailbox identifier register 1
0x1C0
32
read-only
n
0x0
0x0
EXID
EXID
3
18
EXIDEN
EXIDEN
2
1
RTR
RTR
1
1
STID
STID
21
11
TXDH0
TXDH0
CAN Send mailbox High byte data register 0
0x18C
32
read-write
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
TXDH1
TXDH1
CAN Send mailbox High byte data register1
0x19C
32
read-write
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
TXDH2
TXDH2
CAN Send mailbox High byte data register2
0x1AC
32
read-write
n
0x0
0x0
DATA4
DATA4
0
8
DATA5
DATA5
8
8
DATA6
DATA6
16
8
DATA7
DATA7
24
8
TXDL0
TXDL0
CAN Send mailbox low byte data register 0
0x188
32
read-write
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
TXDL1
TXDL1
CAN Send mailbox low byte data register 1
0x198
32
read-write
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
TXDL2
TXDL2
CAN Send mailbox low byte data register 2
0x1A8
32
read-write
n
0x0
0x0
DATA0
DATA0
0
8
DATA1
DATA1
8
8
DATA2
DATA2
16
8
DATA3
DATA3
24
8
TXDLT0
TXDLT0
CAN Send the mailbox data length and timestamp register 0
0x184
32
read-write
n
0x0
0x0
MTS
MTS
16
16
TXDL
TXDL
0
4
TXTS
TXTS
8
1
TXDLT1
TXDLT1
CAN Send the mailbox data length and timestamp register 1
0x194
32
read-write
n
0x0
0x0
MTS
MTS
16
16
TXDL
TXDL
0
4
TXTS
TXTS
8
1
TXDLT2
TXDLT2
CAN Send the mailbox data length and timestamp register 2
0x1A4
32
read-write
n
0x0
0x0
MTS
MTS
16
16
TXDL
TXDL
0
4
TXTS
TXTS
8
1
TXI0
TXI0
CAN Each mailbox contains the sending mailbox identifier register 0
0x180
32
read-write
n
0x0
0x0
EXID
EXID
3
18
EXIDEN
EXIDEN
2
1
RTR
RTR
1
1
STID
STID
21
11
TXRQ
TXRQ
0
1
TXI1
TXI1
CAN Each mailbox contains the sending mailbox identifier register 1
0x190
32
read-write
n
0x0
0x0
EXID
EXID
3
18
EXIDEN
EXIDEN
2
1
RTR
RTR
1
1
STID
STID
21
11
TXRQ
TXRQ
0
1
TXI2
TXI2
CAN Each mailbox contains the sending mailbox identifier register 2
0x1A0
32
read-write
n
0x0
0x0
EXID
EXID
3
18
EXIDEN
EXIDEN
2
1
RTR
RTR
1
1
STID
STID
21
11
TXRQ
TXRQ
0
1
TXSTS
TXSTS
CAN Send States register
0x8
32
read-write
n
0x0
0x0
ALSTM1
ALSTM1
2
1
read-write
ALSTM2
ALSTM2
8
1
read-write
ALSTM3
ALSTM3
14
1
read-write
ATRM1
ATRM1
5
1
read-write
ATRM2
ATRM3
11
1
read-write
ATRM3
ATRM3
17
1
read-write
EMN
EMN
18
2
read-only
EORM1
EORM1
0
1
read-write
EORM2
EORM2
6
1
read-write
EORM3
EORM3
12
1
read-write
FOTM1
FOTM1
3
1
read-write
FOTM2
FOTM2
9
1
read-write
FOTM3
FOTM3
15
1
read-write
LOWMF1
LOWMF1
23
1
read-only
LOWMF2
LOWMF2
24
1
read-only
LOWMF3
LOWMF3
25
1
read-only
TCM1
TCM1
1
1
read-write
TCM2
TCM2
7
1
read-write
TCM3
TCM3
13
1
read-write
TXME1
TXME1
20
1
read-only
TXME2
TXME2
21
1
read-only
TXME3
TXME3
22
1
read-only
CRC
CRC calculation unit
CRC
0x0
0x0
0x400
registers
n
CTRL
CTRL
Control register
0x8
32
write-only
n
0x0
0x0
CTRL
Reset bit
0
1
DATA
DATA
Data register
0x0
32
read-write
n
0x0
0x0
DATA
Data Register
0
32
DB
DB
Independent Data register
0x4
32
read-write
n
0x0
0x0
DB
Independent Data register
0
8
DBG
Debug support
DBG
0x0
0x0
0x400
registers
n
CR
CR
DBGMCU_CR
0x4
32
read-write
n
0x0
0x0
DBG_CAN1_STOP
DBG_CAN1_STOP
14
1
DBG_CAN2_STOP
DBG_CAN2_STOP
21
1
DBG_I2C1_SMBUS_TIMEOUT
DBG_I2C1_SMBUS_TIMEOUT
15
1
DBG_I2C2_SMBUS_TIMEOUT
DBG_I2C2_SMBUS_TIMEOUT
16
1
DBG_IWDT_STOP
DBG_IWDT_STOP
8
1
DBG_SLEEP
DBG_SLEEP
0
1
DBG_STANDBY
DBG_STANDBY
2
1
DBG_STOP
DBG_STOP
1
1
DBG_TMR1_STOP
DBG_TMR1_STOP
10
1
DBG_TMR2_STOP
DBG_TMR2_STOP
11
1
DBG_TMR3_STOP
DBG_TMR3_STOP
12
1
DBG_TMR4_STOP
DBG_TMR4_STOP
13
1
DBG_TMR5_STOP
DBG_TMR5_STOP
18
1
DBG_TMR6_STOP
DBG_TMR6_STOP
19
1
DBG_TMR7_STOP
DBG_TMR7_STOP
20
1
DBG_TMR8_STOP
DBG_TMR8_STOP
17
1
DBG_WWDT_STOP
DBG_WWDT_STOP
9
1
TRACE_IOEN
TRACE_IOEN
5
1
TRACE_MODE
TRACE_MODE
6
2
IDCODE
IDCODE
DBGMCU_IDCODE
0x0
32
read-only
n
0x0
0x0
DEV_ID
DEV_ID
0
12
REV_ID
REV_ID
16
16
DMA
DMA controller
DMA
0x0
0x0
0x400
registers
n
DMA1_Channel1
DMA1 Channel1 global interrupt
11
DMA1_Channel2
DMA1 Channel2 global interrupt
12
DMA1_Channel3
DMA1 Channel3 global interrupt
13
DMA1_Channel4
DMA1 Channel4 global interrupt
14
DMA1_Channel5
DMA1 Channel5 global interrupt
15
DMA1_Channel6
DMA1 Channel6 global interrupt
16
DMA1_Channel7
DMA1 Channel7 global interrupt
17
CNTTC1
CNTTC1
DMA channel 1 number of data register
0xC
32
read-write
n
0x0
0x0
CNTTC
Number of data to transfer
0
16
CNTTC2
CNTTC2
DMA channel 2 number of data register
0x20
32
read-write
n
0x0
0x0
CNTTC
Number of data to transfer
0
16
CNTTC3
CNTTC3
DMA channel 3 number of data register
0x34
32
read-write
n
0x0
0x0
CNTTC
Number of data to transfer
0
16
CNTTC4
CNTTC4
DMA channel 4 number of data register
0x48
32
read-write
n
0x0
0x0
CNTTC
Number of data to transfer
0
16
CNTTC5
CNTTC5
DMA channel 5 number of data register
0x5C
32
read-write
n
0x0
0x0
CNTTC
Number of data to transfer
0
16
CNTTC6
CNTTC6
DMA channel 6 number of data register
0x70
32
read-write
n
0x0
0x0
CNTTC
Number of data to transfer
0
16
CNTTC7
CNTTC7
DMA channel 7 number of data register
0x84
32
read-write
n
0x0
0x0
CNTTC
Number of data to transfer
0
16
IF
IF
DMA Interrupt status register (DMA_IF)
0x0
32
read-only
n
0x0
0x0
EOTTFC1
Channel 1 Transfer Complete flag
1
1
EOTTFC2
Channel 2 Transfer Complete flag
5
1
EOTTFC3
Channel 3 Transfer Complete flag
9
1
EOTTFC4
Channel 4 Transfer Complete flag
13
1
EOTTFC5
Channel 5 Transfer Complete flag
17
1
EOTTFC6
Channel 6 Transfer Complete flag
21
1
EOTTFC7
Channel 7 Transfer Complete flag
25
1
FOTIFC1
Channel 1 Transfer Error flag
3
1
FOTIFC2
Channel 2 Transfer Error flag
7
1
FOTIFC3
Channel 3 Transfer Error flag
11
1
FOTIFC4
Channel 4 Transfer Error flag
15
1
FOTIFC5
Channel 5 Transfer Error flag
19
1
FOTIFC6
Channel 6 Transfer Error flag
23
1
FOTIFC7
Channel 7 Transfer Error flag
27
1
GIFC1
Channel 1 Global interrupt flag
0
1
GIFC2
Channel 2 Global interrupt flag
4
1
GIFC3
Channel 3 Global interrupt flag
8
1
GIFC4
Channel 4 Global interrupt flag
12
1
GIFC5
Channel 5 Global interrupt flag
16
1
GIFC6
Channel 6 Global interrupt flag
20
1
GIFC7
Channel 7 Global interrupt flag
24
1
MOTIFC1
Channel 1 Half Transfer Complete flag
2
1
MOTIFC2
Channel 2 Half Transfer Complete flag
6
1
MOTIFC3
Channel 3 Half Transfer Complete flag
10
1
MOTIFC4
Channel 4 Half Transfer Complete flag
14
1
MOTIFC5
Channel 5 Half Transfer Complete flag
18
1
MOTIFC6
Channel 6 Half Transfer Complete flag
22
1
MOTIFC7
Channel 7 Half Transfer Complete flag
26
1
IFR
IFR
DMA Interrupt reset register (DMA_IFR)
0x4
32
write-only
n
0x0
0x0
REOTIFC1
Channel 1 Transfer Complete reset
1
1
REOTIFC2
Channel 2 Transfer Complete reset
5
1
REOTIFC3
Channel 3 Transfer Complete reset
9
1
REOTIFC4
Channel 4 Transfer Complete reset
13
1
REOTIFC5
Channel 5 Transfer Complete reset
17
1
REOTIFC6
Channel 6 Transfer Complete reset
21
1
REOTIFC7
Channel 7 Transfer Complete reset
25
1
RFOTIFC1
Channel 1 Transfer Error reset
3
1
RFOTIFC2
Channel 2 Transfer Error reset
7
1
RFOTIFC3
Channel 3 Transfer Error reset
11
1
RFOTIFC4
Channel 4 Transfer Error reset
15
1
RFOTIFC5
Channel 5 Transfer Error reset
19
1
RFOTIFC6
Channel 6 Transfer Error reset
23
1
RFOTIFC7
Channel 7 Transfer Error reset
27
1
RGIFC1
Channel 1 Global interrupt resetr
0
1
RGIFC2
Channel 2 Global interrupt reset
4
1
RGIFC3
Channel 3 Global interrupt reset
8
1
RGIFC4
Channel 4 Global interrupt reset
12
1
RGIFC5
Channel 5 Global interrupt reset
16
1
RGIFC6
Channel 6 Global interrupt reset
20
1
RGIFC7
Channel 7 Global interrupt reset
24
1
RMOTIFC1
Channel 1 Half Transfer reset
2
1
RMOTIFC2
Channel 2 Half Transfer reset
6
1
RMOTIFC3
Channel 3 Half Transfer reset
10
1
RMOTIFC4
Channel 4 Half Transfer reset
14
1
RMOTIFC5
Channel 5 Half Transfer reset
18
1
RMOTIFC6
Channel 6 Half Transfer reset
22
1
RMOTIFC7
Channel 7 Half Transfer reset
26
1
MAC1
MAC1
DMA channel 1 memory address register
0x14
32
read-write
n
0x0
0x0
MAC
Memory address
0
32
MAC2
MAC2
DMA channel 2 memory address register
0x28
32
read-write
n
0x0
0x0
MAC
Memory address
0
32
MAC3
MAC3
DMA channel 3 memory address register
0x3C
32
read-write
n
0x0
0x0
MAC
Memory address
0
32
MAC4
MAC4
DMA channel 4 memory address register
0x50
32
read-write
n
0x0
0x0
MAC
Memory address
0
32
MAC5
MAC5
DMA channel 5 memory address register
0x64
32
read-write
n
0x0
0x0
MAC
Memory address
0
32
MAC6
MAC6
DMA channel 6 memory address register
0x78
32
read-write
n
0x0
0x0
MAC
Memory address
0
32
MAC7
MAC7
DMA channel 7 memory address register
0x8C
32
read-write
n
0x0
0x0
MAC
Memory address
0
32
PAC1
PAC1
DMA channel 1 peripheral address register
0x10
32
read-write
n
0x0
0x0
PAC
Peripheral address
0
32
PAC2
PAC2
DMA channel 2 peripheral address register
0x24
32
read-write
n
0x0
0x0
PAC
Peripheral address
0
32
PAC3
PAC3
DMA channel 3 peripheral address register
0x38
32
read-write
n
0x0
0x0
PAC
Peripheral address
0
32
PAC4
PAC4
DMA channel 4 peripheral address register
0x4C
32
read-write
n
0x0
0x0
PAC
Peripheral address
0
32
PAC5
PAC5
DMA channel 5 peripheral address register
0x60
32
read-write
n
0x0
0x0
PAC
Peripheral address
0
32
PAC6
PAC6
DMA channel 6 peripheral address register
0x74
32
read-write
n
0x0
0x0
PAC
Peripheral address
0
32
PAC7
PAC7
DMA channel 7 peripheral address register
0x88
32
read-write
n
0x0
0x0
PAC
Peripheral address
0
32
SRC1
SRC1
DMA channel 1 configuration register
0x8
32
read-write
n
0x0
0x0
DOT
Data transfer direction
4
1
EN
Channel enable
0
1
EOTIEN
Transfer complete interrupt enable
1
1
FOTIEN
Transfer error interrupt enable
3
1
LOOP
Circular mode
5
1
M2MEN
Memory to memory mode
14
1
MLOOP
Memory increment mode
7
1
MOTIEN
Half Transfer interrupt enable
2
1
MWID
Memory size
10
2
PL
Channel Priority level
12
2
PLOOP
Peripheral increment mode
6
1
PWID
Peripheral size
8
2
SRC2
SRC2
DMA channel 2 configuration register
0x1C
32
read-write
n
0x0
0x0
DOT
Data transfer direction
4
1
EN
Channel enable
0
1
EOTIEN
Transfer complete interrupt enable
1
1
FOTIEN
Transfer error interrupt enable
3
1
LOOP
Circular mode
5
1
M2MEN
Memory to memory mode
14
1
MLOOP
Memory increment mode
7
1
MOTIEN
Half Transfer interrupt enable
2
1
MWID
Memory size
10
2
PL
Channel Priority level
12
2
PLOOP
Peripheral increment mode
6
1
PWID
Peripheral size
8
2
SRC3
SRC3
DMA channel 3 configuration register
0x30
32
read-write
n
0x0
0x0
DOT
Data transfer direction
4
1
EN
Channel enable
0
1
EOTIEN
Transfer complete interrupt enable
1
1
FOTIEN
Transfer error interrupt enable
3
1
LOOP
Circular mode
5
1
M2MEN
Memory to memory mode
14
1
MLOOP
Memory increment mode
7
1
MOTIEN
Half Transfer interrupt enable
2
1
MWID
Memory size
10
2
PL
Channel Priority level
12
2
PLOOP
Peripheral increment mode
6
1
PWID
Peripheral size
8
2
SRC4
SRC4
DMA channel 4 configuration register
0x44
32
read-write
n
0x0
0x0
DOT
Data transfer direction
4
1
EN
Channel enable
0
1
EOTIEN
Transfer complete interrupt enable
1
1
FOTIEN
Transfer error interrupt enable
3
1
LOOP
Circular mode
5
1
M2MEN
Memory to memory mode
14
1
MLOOP
Memory increment mode
7
1
MOTIEN
Half Transfer interrupt enable
2
1
MWID
Memory size
10
2
PL
Channel Priority level
12
2
PLOOP
Peripheral increment mode
6
1
PWID
Peripheral size
8
2
SRC5
SRC5
DMA channel 5 configuration register
0x58
32
read-write
n
0x0
0x0
DOT
Data transfer direction
4
1
EN
Channel enable
0
1
EOTIEN
Transfer complete interrupt enable
1
1
FOTIEN
Transfer error interrupt enable
3
1
LOOP
Circular mode
5
1
M2MEN
Memory to memory mode
14
1
MLOOP
Memory increment mode
7
1
MOTIEN
Half Transfer interrupt enable
2
1
MWID
Memory size
10
2
PL
Channel Priority level
12
2
PLOOP
Peripheral increment mode
6
1
PWID
Peripheral size
8
2
SRC6
SRC6
DMA channel 6 configuration register
0x6C
32
read-write
n
0x0
0x0
DOT
Data transfer direction
4
1
EN
Channel enable
0
1
EOTIEN
Transfer complete interrupt enable
1
1
FOTIEN
Transfer error interrupt enable
3
1
LOOP
Circular mode
5
1
M2MEN
Memory to memory mode
14
1
MLOOP
Memory increment mode
7
1
MOTIEN
Half Transfer interrupt enable
2
1
MWID
Memory size
10
2
PL
Channel Priority level
12
2
PLOOP
Peripheral increment mode
6
1
PWID
Peripheral size
8
2
SRC7
SRC7
DMA channel 7 configuration register
0x80
32
read-write
n
0x0
0x0
DOT
Data transfer direction
4
1
EN
Channel enable
0
1
EOTIEN
Transfer complete interrupt enable
1
1
FOTIEN
Transfer error interrupt enable
3
1
LOOP
Circular mode
5
1
M2MEN
Memory to memory mode
14
1
MLOOP
Memory increment mode
7
1
MOTIEN
Half Transfer interrupt enable
2
1
MWID
Memory size
10
2
PL
Channel Priority level
12
2
PLOOP
Peripheral increment mode
6
1
PWID
Peripheral size
8
2
EINT
External Interrupt
EINT
0x0
0x0
0x400
registers
n
TAMPER
Tamper interrupt
2
EINT0
EINT Line0 interrupt
6
EINT1
EINT Line1 interrupt
7
EINT2
EINT Line2 interrupt
8
EINT3
EINT Line3 interrupt
9
EINT4
EINT Line4 interrupt
10
EINT9_5
EINT Line[9:5] interrupts
23
EINT15_10
EINT Line[15:10] interrupts
40
EEN
EEN
Event mask register (EXTI_EMR)
0x4
32
read-write
n
0x0
0x0
EEN0
Event Mask on line 0
0
1
EEN1
Event Mask on line 1
1
1
EEN10
Event Mask on line 10
10
1
EEN11
Event Mask on line 11
11
1
EEN12
Event Mask on line 12
12
1
EEN13
Event Mask on line 13
13
1
EEN14
Event Mask on line 14
14
1
EEN15
Event Mask on line 15
15
1
EEN16
Event Mask on line 16
16
1
EEN17
Event Mask on line 17
17
1
EEN18
Event Mask on line 18
18
1
EEN19
Event Mask on line 19
19
1
EEN2
Event Mask on line 2
2
1
EEN3
Event Mask on line 3
3
1
EEN4
Event Mask on line 4
4
1
EEN5
Event Mask on line 5
5
1
EEN6
Event Mask on line 6
6
1
EEN7
Event Mask on line 7
7
1
EEN8
Event Mask on line 8
8
1
EEN9
Event Mask on line 9
9
1
FTEN
FTEN
Falling Trigger selection register (EXTI_FTSR)
0xC
32
read-write
n
0x0
0x0
FT0
Falling trigger event configuration of line 0
0
1
FT1
Falling trigger event configuration of line 1
1
1
FT10
Falling trigger event configuration of line 10
10
1
FT11
Falling trigger event configuration of line 11
11
1
FT12
Falling trigger event configuration of line 12
12
1
FT13
Falling trigger event configuration of line 13
13
1
FT14
Falling trigger event configuration of line 14
14
1
FT15
Falling trigger event configuration of line 15
15
1
FT16
Falling trigger event configuration of line 16
16
1
FT17
Falling trigger event configuration of line 17
17
1
FT18
Falling trigger event configuration of line 18
18
1
FT19
Falling trigger event configuration of line 19
19
1
FT2
Falling trigger event configuration of line 2
2
1
FT3
Falling trigger event configuration of line 3
3
1
FT4
Falling trigger event configuration of line 4
4
1
FT5
Falling trigger event configuration of line 5
5
1
FT6
Falling trigger event configuration of line 6
6
1
FT7
Falling trigger event configuration of line 7
7
1
FT8
Falling trigger event configuration of line 8
8
1
FT9
Falling trigger event configuration of line 9
9
1
IEN
IEN
Interrupt mask register (EXTI_IMR)
0x0
32
read-write
n
0x0
0x0
IEN0
Interrupt Mask on line 0
0
1
IEN1
Interrupt Mask on line 1
1
1
IEN10
Interrupt Mask on line 10
10
1
IEN11
Interrupt Mask on line 11
11
1
IEN12
Interrupt Mask on line 12
12
1
IEN13
Interrupt Mask on line 13
13
1
IEN14
Interrupt Mask on line 14
14
1
IEN15
Interrupt Mask on line 15
15
1
IEN16
Interrupt Mask on line 16
16
1
IEN17
Interrupt Mask on line 17
17
1
IEN18
Interrupt Mask on line 18
18
1
IEN19
Interrupt Mask on line 19
19
1
IEN2
Interrupt Mask on line 2
2
1
IEN3
Interrupt Mask on line 3
3
1
IEN4
Interrupt Mask on line 4
4
1
IEN5
Interrupt Mask on line 5
5
1
IEN6
Interrupt Mask on line 6
6
1
IEN7
Interrupt Mask on line 7
7
1
IEN8
Interrupt Mask on line 8
8
1
IEN9
Interrupt Mask on line 9
9
1
IF
IF
Interrupt Flag Enable register (EXTI_IF)
0x14
32
read-write
n
0x0
0x0
IF0
Pending bit 0
0
1
IF1
Pending bit 1
1
1
IF10
Pending bit 10
10
1
IF11
Pending bit 11
11
1
IF12
Pending bit 12
12
1
IF13
Pending bit 13
13
1
IF14
Pending bit 14
14
1
IF15
Pending bit 15
15
1
IF16
Pending bit 16
16
1
IF17
Pending bit 17
17
1
IF18
Pending bit 18
18
1
IF19
Pending bit 19
19
1
IF2
Pending bit 2
2
1
IF3
Pending bit 3
3
1
IF4
Pending bit 4
4
1
IF5
Pending bit 5
5
1
IF6
Pending bit 6
6
1
IF7
Pending bit 7
7
1
IF8
Pending bit 8
8
1
IF9
Pending bit 9
9
1
RTEN
RTEN
Rising Trigger selection register (EXTI_RTSR)
0x8
32
read-write
n
0x0
0x0
RT0
Rising trigger event configuration of line 0
0
1
RT1
Rising trigger event configuration of line 1
1
1
RT10
Rising trigger event configuration of line 10
10
1
RT11
Rising trigger event configuration of line 11
11
1
RT12
Rising trigger event configuration of line 12
12
1
RT13
Rising trigger event configuration of line 13
13
1
RT14
Rising trigger event configuration of line 14
14
1
RT15
Rising trigger event configuration of line 15
15
1
RT16
Rising trigger event configuration of line 16
16
1
RT17
Rising trigger event configuration of line 17
17
1
RT18
Rising trigger event configuration of line 18
18
1
RT19
Rising trigger event configuration of line 19
19
1
RT2
Rising trigger event configuration of line 2
2
1
RT3
Rising trigger event configuration of line 3
3
1
RT4
Rising trigger event configuration of line 4
4
1
RT5
Rising trigger event configuration of line 5
5
1
RT6
Rising trigger event configuration of line 6
6
1
RT7
Rising trigger event configuration of line 7
7
1
RT8
Rising trigger event configuration of line 8
8
1
RT9
Rising trigger event configuration of line 9
9
1
SWIEN
SWIEN
Software interrupt event register (EXTI_SWIER)
0x10
32
read-write
n
0x0
0x0
SWIEN0
Software Interrupt on line 0
0
1
SWIEN1
Software Interrupt on line 1
1
1
SWIEN10
Software Interrupt on line 10
10
1
SWIEN11
Software Interrupt on line 11
11
1
SWIEN12
Software Interrupt on line 12
12
1
SWIEN13
Software Interrupt on line 13
13
1
SWIEN14
Software Interrupt on line 14
14
1
SWIEN15
Software Interrupt on line 15
15
1
SWIEN16
Software Interrupt on line 16
16
1
SWIEN17
Software Interrupt on line 17
17
1
SWIEN18
Software Interrupt on line 18
18
1
SWIEN19
Software Interrupt on line 19
19
1
SWIEN2
Software Interrupt on line 2
2
1
SWIEN3
Software Interrupt on line 3
3
1
SWIEN4
Software Interrupt on line 4
4
1
SWIEN5
Software Interrupt on line 5
5
1
SWIEN6
Software Interrupt on line 6
6
1
SWIEN7
Software Interrupt on line 7
7
1
SWIEN8
Software Interrupt on line 8
8
1
SWIEN9
Software Interrupt on line 9
9
1
FMC
Flash memory controller
FMC
0x0
0x0
0x400
registers
n
FMC
Flash global interrupt
4
ADD
ADD
Flash address register
0x14
32
write-only
n
0x0
0x0
ADD
Flash Address
0
32
CTRL1
CTRL1
Flash access control register
0x0
32
read-write
n
0x0
0x0
HCAEN
Flash half cycle access enable
3
1
read-write
LATENCY
Latency
0
3
read-write
PBEN
Prefetch buffer enable
4
1
read-write
PBSF
Prefetch buffer status
5
1
read-only
CTRL2
CTRL2
Control register
0x10
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
10
1
LOCK
Lock
7
1
MASSERA
Mass Erase
2
1
OBE
Option byte erase
5
1
OBP
Option byte programming
4
1
OBWEN
Option bytes write enable
9
1
OCIE
End of operation interrupt enable
12
1
PAGEERA
Page Erase
1
1
PG
Programming
0
1
STA
Start
6
1
KEY
KEY
key register
0x4
32
write-only
n
0x0
0x0
KEY
FPEC key
0
32
OBCS
OBCS
Option byte register
0x1C
32
read-only
n
0x0
0x0
DATA0
Data1
13
8
Data1
Data1
21
8
NOTUSED
5
8
OBE
Option byte error
0
1
READPORT
Read protection
1
1
STDBYRST
nRST_STDBY
4
1
STOPRST
nRST_STOP
3
1
WDT
WDG_SW
2
1
OBKEY
OBKEY
option byte key register
0x8
32
write-only
n
0x0
0x0
KEY
Option byte key
0
32
STS
STS
status register
0xC
32
read-write
n
0x0
0x0
BUSYF
Busy
0
1
read-only
OCF
End of operation
5
1
read-write
PEF
Programming error
2
1
read-write
WPEF
Write protection error
4
1
read-write
WRTPORT
WRTPORT
Write protection register
0x20
32
read-only
n
0x0
0x0
WRTPORT
Write protect
0
32
GPIOA
General purpose I/O
GPIO
0x0
0x0
0x400
registers
n
BC
BC
Port bit clear register (GPIOn_BC)
0x14
32
write-only
n
0x0
0x0
BC0
Clear bit 0
0
1
BC1
Clear bit 1
1
1
BC10
Clear bit 10
10
1
BC11
Clear bit 11
11
1
BC12
Clear bit 12
12
1
BC13
Clear bit 13
13
1
BC14
Clear bit 14
14
1
BC15
Clear bit 15
15
1
BC2
Clear bit 1
2
1
BC3
Clear bit 3
3
1
BC4
Clear bit 4
4
1
BC5
Clear bit 5
5
1
BC6
Clear bit 6
6
1
BC7
Clear bit 7
7
1
BC8
Clear bit 8
8
1
BC9
Clear bit 9
9
1
BSC
BSC
Port bit set/reset register (GPIOn_BSC)
0x10
32
write-only
n
0x0
0x0
BC0
Clear bit 0
16
1
BC1
Clear bit 1
17
1
BC10
Clear bit 10
26
1
BC11
Clear bit 11
27
1
BC12
Clear bit 12
28
1
BC13
Clear bit 13
29
1
BC14
Clear bit 14
30
1
BC15
Clear bit 15
31
1
BC2
Clear bit 2
18
1
BC3
Clear bit 3
19
1
BC4
Clear bit 4
20
1
BC5
Clear bit 5
21
1
BC6
Clear bit 6
22
1
BC7
Clear bit 7
23
1
BC8
Clear bit 8
24
1
BC9
Clear bit 9
25
1
BS0
Set bit 0
0
1
BS1
Set bit 1
1
1
BS10
Set bit 10
10
1
BS11
Set bit 11
11
1
BS12
Set bit 12
12
1
BS13
Set bit 13
13
1
BS14
Set bit 14
14
1
BS15
Set bit 15
15
1
BS2
Set bit 1
2
1
BS3
Set bit 3
3
1
BS4
Set bit 4
4
1
BS5
Set bit 5
5
1
BS6
Set bit 6
6
1
BS7
Set bit 7
7
1
BS8
Set bit 8
8
1
BS9
Set bit 9
9
1
CTRL0
CTRL0
Port configuration register 0 (GPIOn_CTRL0)
0x0
32
read-write
n
0x0
0x0
CFG0
Port n.0 configuration bits
2
2
CFG1
Port n.1 configuration bits
6
2
CFG2
Port n.2 configuration bits
10
2
CFG3
Port n.3 configuration bits
14
2
CFG4
Port n.4 configuration bits
18
2
CFG5
Port n.5 configuration bits
22
2
CFG6
Port n.6 configuration bits
26
2
CFG7
Port n.7 configuration bits
30
2
MOD0
Port n.0 mode bits
0
2
MOD1
Port n.1 mode bits
4
2
MOD2
Port n.2 mode bits
8
2
MOD3
Port n.3 mode bits
12
2
MOD4
Port n.4 mode bits
16
2
MOD5
Port n.5 mode bits
20
2
MOD6
Port n.6 mode bits
24
2
MOD7
Port n.7 mode bits
28
2
CTRL1
CTRL1
Port configuration register 1 (GPIOn_CTRL1)
0x4
32
read-write
n
0x0
0x0
CFG10
Port n.10 configuration bits
10
2
CFG11
Port n.11 configuration bits
14
2
CFG12
Port n.12 configuration bits
18
2
CFG13
Port n.13 configuration bits
22
2
CFG14
Port n.14 configuration bits
26
2
CFG15
Port n.15 configuration bits
30
2
CFG8
Port n.8 configuration bits
2
2
CFG9
Port n.9 configuration bits
6
2
MOD10
Port n.10 mode bits
8
2
MOD11
Port n.11 mode bits
12
2
MOD12
Port n.12 mode bits
16
2
MOD13
Port n.13 mode bits
20
2
MOD14
Port n.14 mode bits
24
2
MOD15
Port n.15 mode bits
28
2
MOD8
Port n.8 mode bits
0
2
MOD9
Port n.9 mode bits
4
2
DIN
DIN
Port input data register (GPIOn_DIN)
0x8
32
read-only
n
0x0
0x0
DIN0
Port input data
0
1
DIN1
Port input data
1
1
DIN10
Port input data
10
1
DIN11
Port input data
11
1
DIN12
Port input data
12
1
DIN13
Port input data
13
1
DIN14
Port input data
14
1
DIN15
Port input data
15
1
DIN2
Port input data
2
1
DIN3
Port input data
3
1
DIN4
Port input data
4
1
DIN5
Port input data
5
1
DIN6
Port input data
6
1
DIN7
Port input data
7
1
DIN8
Port input data
8
1
DIN9
Port input data
9
1
DOUT
DOUT
Port output data register (GPIOn_DOUT)
0xC
32
read-write
n
0x0
0x0
DOUT0
Port output data
0
1
DOUT1
Port output data
1
1
DOUT10
Port output data
10
1
DOUT11
Port output data
11
1
DOUT12
Port output data
12
1
DOUT13
Port output data
13
1
DOUT14
Port output data
14
1
DOUT15
Port output data
15
1
DOUT2
Port output data
2
1
DOUT3
Port output data
3
1
DOUT4
Port output data
4
1
DOUT5
Port output data
5
1
DOUT6
Port output data
6
1
DOUT7
Port output data
7
1
DOUT8
Port output data
8
1
DOUT9
Port output data
9
1
LOCK
LOCK
Port configuration lock register (GPIOn_LOCK)
0x18
32
read-write
n
0x0
0x0
LCK0
Port A Lock bit 0
0
1
LCK1
Port A Lock bit 1
1
1
LCK10
Port A Lock bit 10
10
1
LCK11
Port A Lock bit 11
11
1
LCK12
Port A Lock bit 12
12
1
LCK13
Port A Lock bit 13
13
1
LCK14
Port A Lock bit 14
14
1
LCK15
Port A Lock bit 15
15
1
LCK2
Port A Lock bit 2
2
1
LCK3
Port A Lock bit 3
3
1
LCK4
Port A Lock bit 4
4
1
LCK5
Port A Lock bit 5
5
1
LCK6
Port A Lock bit 6
6
1
LCK7
Port A Lock bit 7
7
1
LCK8
Port A Lock bit 8
8
1
LCK9
Port A Lock bit 9
9
1
LCKK
Lock key
16
1
GPIOB
General purpose I/O
GPIO
0x0
0x0
0x400
registers
n
BC
BC
Port bit clear register (GPIOn_BC)
0x14
32
write-only
n
0x0
0x0
BC0
Clear bit 0
0
1
BC1
Clear bit 1
1
1
BC10
Clear bit 10
10
1
BC11
Clear bit 11
11
1
BC12
Clear bit 12
12
1
BC13
Clear bit 13
13
1
BC14
Clear bit 14
14
1
BC15
Clear bit 15
15
1
BC2
Clear bit 1
2
1
BC3
Clear bit 3
3
1
BC4
Clear bit 4
4
1
BC5
Clear bit 5
5
1
BC6
Clear bit 6
6
1
BC7
Clear bit 7
7
1
BC8
Clear bit 8
8
1
BC9
Clear bit 9
9
1
BSC
BSC
Port bit set/reset register (GPIOn_BSC)
0x10
32
write-only
n
0x0
0x0
BC0
Clear bit 0
16
1
BC1
Clear bit 1
17
1
BC10
Clear bit 10
26
1
BC11
Clear bit 11
27
1
BC12
Clear bit 12
28
1
BC13
Clear bit 13
29
1
BC14
Clear bit 14
30
1
BC15
Clear bit 15
31
1
BC2
Clear bit 2
18
1
BC3
Clear bit 3
19
1
BC4
Clear bit 4
20
1
BC5
Clear bit 5
21
1
BC6
Clear bit 6
22
1
BC7
Clear bit 7
23
1
BC8
Clear bit 8
24
1
BC9
Clear bit 9
25
1
BS0
Set bit 0
0
1
BS1
Set bit 1
1
1
BS10
Set bit 10
10
1
BS11
Set bit 11
11
1
BS12
Set bit 12
12
1
BS13
Set bit 13
13
1
BS14
Set bit 14
14
1
BS15
Set bit 15
15
1
BS2
Set bit 1
2
1
BS3
Set bit 3
3
1
BS4
Set bit 4
4
1
BS5
Set bit 5
5
1
BS6
Set bit 6
6
1
BS7
Set bit 7
7
1
BS8
Set bit 8
8
1
BS9
Set bit 9
9
1
CTRL0
CTRL0
Port configuration register 0 (GPIOn_CTRL0)
0x0
32
read-write
n
0x0
0x0
CFG0
Port n.0 configuration bits
2
2
CFG1
Port n.1 configuration bits
6
2
CFG2
Port n.2 configuration bits
10
2
CFG3
Port n.3 configuration bits
14
2
CFG4
Port n.4 configuration bits
18
2
CFG5
Port n.5 configuration bits
22
2
CFG6
Port n.6 configuration bits
26
2
CFG7
Port n.7 configuration bits
30
2
MOD0
Port n.0 mode bits
0
2
MOD1
Port n.1 mode bits
4
2
MOD2
Port n.2 mode bits
8
2
MOD3
Port n.3 mode bits
12
2
MOD4
Port n.4 mode bits
16
2
MOD5
Port n.5 mode bits
20
2
MOD6
Port n.6 mode bits
24
2
MOD7
Port n.7 mode bits
28
2
CTRL1
CTRL1
Port configuration register 1 (GPIOn_CTRL1)
0x4
32
read-write
n
0x0
0x0
CFG10
Port n.10 configuration bits
10
2
CFG11
Port n.11 configuration bits
14
2
CFG12
Port n.12 configuration bits
18
2
CFG13
Port n.13 configuration bits
22
2
CFG14
Port n.14 configuration bits
26
2
CFG15
Port n.15 configuration bits
30
2
CFG8
Port n.8 configuration bits
2
2
CFG9
Port n.9 configuration bits
6
2
MOD10
Port n.10 mode bits
8
2
MOD11
Port n.11 mode bits
12
2
MOD12
Port n.12 mode bits
16
2
MOD13
Port n.13 mode bits
20
2
MOD14
Port n.14 mode bits
24
2
MOD15
Port n.15 mode bits
28
2
MOD8
Port n.8 mode bits
0
2
MOD9
Port n.9 mode bits
4
2
DIN
DIN
Port input data register (GPIOn_DIN)
0x8
32
read-only
n
0x0
0x0
DIN0
Port input data
0
1
DIN1
Port input data
1
1
DIN10
Port input data
10
1
DIN11
Port input data
11
1
DIN12
Port input data
12
1
DIN13
Port input data
13
1
DIN14
Port input data
14
1
DIN15
Port input data
15
1
DIN2
Port input data
2
1
DIN3
Port input data
3
1
DIN4
Port input data
4
1
DIN5
Port input data
5
1
DIN6
Port input data
6
1
DIN7
Port input data
7
1
DIN8
Port input data
8
1
DIN9
Port input data
9
1
DOUT
DOUT
Port output data register (GPIOn_DOUT)
0xC
32
read-write
n
0x0
0x0
DOUT0
Port output data
0
1
DOUT1
Port output data
1
1
DOUT10
Port output data
10
1
DOUT11
Port output data
11
1
DOUT12
Port output data
12
1
DOUT13
Port output data
13
1
DOUT14
Port output data
14
1
DOUT15
Port output data
15
1
DOUT2
Port output data
2
1
DOUT3
Port output data
3
1
DOUT4
Port output data
4
1
DOUT5
Port output data
5
1
DOUT6
Port output data
6
1
DOUT7
Port output data
7
1
DOUT8
Port output data
8
1
DOUT9
Port output data
9
1
LOCK
LOCK
Port configuration lock register (GPIOn_LOCK)
0x18
32
read-write
n
0x0
0x0
LCK0
Port A Lock bit 0
0
1
LCK1
Port A Lock bit 1
1
1
LCK10
Port A Lock bit 10
10
1
LCK11
Port A Lock bit 11
11
1
LCK12
Port A Lock bit 12
12
1
LCK13
Port A Lock bit 13
13
1
LCK14
Port A Lock bit 14
14
1
LCK15
Port A Lock bit 15
15
1
LCK2
Port A Lock bit 2
2
1
LCK3
Port A Lock bit 3
3
1
LCK4
Port A Lock bit 4
4
1
LCK5
Port A Lock bit 5
5
1
LCK6
Port A Lock bit 6
6
1
LCK7
Port A Lock bit 7
7
1
LCK8
Port A Lock bit 8
8
1
LCK9
Port A Lock bit 9
9
1
LCKK
Lock key
16
1
GPIOC
General purpose I/O
GPIO
0x0
0x0
0x400
registers
n
BC
BC
Port bit clear register (GPIOn_BC)
0x14
32
write-only
n
0x0
0x0
BC0
Clear bit 0
0
1
BC1
Clear bit 1
1
1
BC10
Clear bit 10
10
1
BC11
Clear bit 11
11
1
BC12
Clear bit 12
12
1
BC13
Clear bit 13
13
1
BC14
Clear bit 14
14
1
BC15
Clear bit 15
15
1
BC2
Clear bit 1
2
1
BC3
Clear bit 3
3
1
BC4
Clear bit 4
4
1
BC5
Clear bit 5
5
1
BC6
Clear bit 6
6
1
BC7
Clear bit 7
7
1
BC8
Clear bit 8
8
1
BC9
Clear bit 9
9
1
BSC
BSC
Port bit set/reset register (GPIOn_BSC)
0x10
32
write-only
n
0x0
0x0
BC0
Clear bit 0
16
1
BC1
Clear bit 1
17
1
BC10
Clear bit 10
26
1
BC11
Clear bit 11
27
1
BC12
Clear bit 12
28
1
BC13
Clear bit 13
29
1
BC14
Clear bit 14
30
1
BC15
Clear bit 15
31
1
BC2
Clear bit 2
18
1
BC3
Clear bit 3
19
1
BC4
Clear bit 4
20
1
BC5
Clear bit 5
21
1
BC6
Clear bit 6
22
1
BC7
Clear bit 7
23
1
BC8
Clear bit 8
24
1
BC9
Clear bit 9
25
1
BS0
Set bit 0
0
1
BS1
Set bit 1
1
1
BS10
Set bit 10
10
1
BS11
Set bit 11
11
1
BS12
Set bit 12
12
1
BS13
Set bit 13
13
1
BS14
Set bit 14
14
1
BS15
Set bit 15
15
1
BS2
Set bit 1
2
1
BS3
Set bit 3
3
1
BS4
Set bit 4
4
1
BS5
Set bit 5
5
1
BS6
Set bit 6
6
1
BS7
Set bit 7
7
1
BS8
Set bit 8
8
1
BS9
Set bit 9
9
1
CTRL0
CTRL0
Port configuration register 0 (GPIOn_CTRL0)
0x0
32
read-write
n
0x0
0x0
CFG0
Port n.0 configuration bits
2
2
CFG1
Port n.1 configuration bits
6
2
CFG2
Port n.2 configuration bits
10
2
CFG3
Port n.3 configuration bits
14
2
CFG4
Port n.4 configuration bits
18
2
CFG5
Port n.5 configuration bits
22
2
CFG6
Port n.6 configuration bits
26
2
CFG7
Port n.7 configuration bits
30
2
MOD0
Port n.0 mode bits
0
2
MOD1
Port n.1 mode bits
4
2
MOD2
Port n.2 mode bits
8
2
MOD3
Port n.3 mode bits
12
2
MOD4
Port n.4 mode bits
16
2
MOD5
Port n.5 mode bits
20
2
MOD6
Port n.6 mode bits
24
2
MOD7
Port n.7 mode bits
28
2
CTRL1
CTRL1
Port configuration register 1 (GPIOn_CTRL1)
0x4
32
read-write
n
0x0
0x0
CFG10
Port n.10 configuration bits
10
2
CFG11
Port n.11 configuration bits
14
2
CFG12
Port n.12 configuration bits
18
2
CFG13
Port n.13 configuration bits
22
2
CFG14
Port n.14 configuration bits
26
2
CFG15
Port n.15 configuration bits
30
2
CFG8
Port n.8 configuration bits
2
2
CFG9
Port n.9 configuration bits
6
2
MOD10
Port n.10 mode bits
8
2
MOD11
Port n.11 mode bits
12
2
MOD12
Port n.12 mode bits
16
2
MOD13
Port n.13 mode bits
20
2
MOD14
Port n.14 mode bits
24
2
MOD15
Port n.15 mode bits
28
2
MOD8
Port n.8 mode bits
0
2
MOD9
Port n.9 mode bits
4
2
DIN
DIN
Port input data register (GPIOn_DIN)
0x8
32
read-only
n
0x0
0x0
DIN0
Port input data
0
1
DIN1
Port input data
1
1
DIN10
Port input data
10
1
DIN11
Port input data
11
1
DIN12
Port input data
12
1
DIN13
Port input data
13
1
DIN14
Port input data
14
1
DIN15
Port input data
15
1
DIN2
Port input data
2
1
DIN3
Port input data
3
1
DIN4
Port input data
4
1
DIN5
Port input data
5
1
DIN6
Port input data
6
1
DIN7
Port input data
7
1
DIN8
Port input data
8
1
DIN9
Port input data
9
1
DOUT
DOUT
Port output data register (GPIOn_DOUT)
0xC
32
read-write
n
0x0
0x0
DOUT0
Port output data
0
1
DOUT1
Port output data
1
1
DOUT10
Port output data
10
1
DOUT11
Port output data
11
1
DOUT12
Port output data
12
1
DOUT13
Port output data
13
1
DOUT14
Port output data
14
1
DOUT15
Port output data
15
1
DOUT2
Port output data
2
1
DOUT3
Port output data
3
1
DOUT4
Port output data
4
1
DOUT5
Port output data
5
1
DOUT6
Port output data
6
1
DOUT7
Port output data
7
1
DOUT8
Port output data
8
1
DOUT9
Port output data
9
1
LOCK
LOCK
Port configuration lock register (GPIOn_LOCK)
0x18
32
read-write
n
0x0
0x0
LCK0
Port A Lock bit 0
0
1
LCK1
Port A Lock bit 1
1
1
LCK10
Port A Lock bit 10
10
1
LCK11
Port A Lock bit 11
11
1
LCK12
Port A Lock bit 12
12
1
LCK13
Port A Lock bit 13
13
1
LCK14
Port A Lock bit 14
14
1
LCK15
Port A Lock bit 15
15
1
LCK2
Port A Lock bit 2
2
1
LCK3
Port A Lock bit 3
3
1
LCK4
Port A Lock bit 4
4
1
LCK5
Port A Lock bit 5
5
1
LCK6
Port A Lock bit 6
6
1
LCK7
Port A Lock bit 7
7
1
LCK8
Port A Lock bit 8
8
1
LCK9
Port A Lock bit 9
9
1
LCKK
Lock key
16
1
GPIOD
General purpose I/O
GPIO
0x0
0x0
0x400
registers
n
BC
BC
Port bit clear register (GPIOn_BC)
0x14
32
write-only
n
0x0
0x0
BC0
Clear bit 0
0
1
BC1
Clear bit 1
1
1
BC10
Clear bit 10
10
1
BC11
Clear bit 11
11
1
BC12
Clear bit 12
12
1
BC13
Clear bit 13
13
1
BC14
Clear bit 14
14
1
BC15
Clear bit 15
15
1
BC2
Clear bit 1
2
1
BC3
Clear bit 3
3
1
BC4
Clear bit 4
4
1
BC5
Clear bit 5
5
1
BC6
Clear bit 6
6
1
BC7
Clear bit 7
7
1
BC8
Clear bit 8
8
1
BC9
Clear bit 9
9
1
BSC
BSC
Port bit set/reset register (GPIOn_BSC)
0x10
32
write-only
n
0x0
0x0
BC0
Clear bit 0
16
1
BC1
Clear bit 1
17
1
BC10
Clear bit 10
26
1
BC11
Clear bit 11
27
1
BC12
Clear bit 12
28
1
BC13
Clear bit 13
29
1
BC14
Clear bit 14
30
1
BC15
Clear bit 15
31
1
BC2
Clear bit 2
18
1
BC3
Clear bit 3
19
1
BC4
Clear bit 4
20
1
BC5
Clear bit 5
21
1
BC6
Clear bit 6
22
1
BC7
Clear bit 7
23
1
BC8
Clear bit 8
24
1
BC9
Clear bit 9
25
1
BS0
Set bit 0
0
1
BS1
Set bit 1
1
1
BS10
Set bit 10
10
1
BS11
Set bit 11
11
1
BS12
Set bit 12
12
1
BS13
Set bit 13
13
1
BS14
Set bit 14
14
1
BS15
Set bit 15
15
1
BS2
Set bit 1
2
1
BS3
Set bit 3
3
1
BS4
Set bit 4
4
1
BS5
Set bit 5
5
1
BS6
Set bit 6
6
1
BS7
Set bit 7
7
1
BS8
Set bit 8
8
1
BS9
Set bit 9
9
1
CTRL0
CTRL0
Port configuration register 0 (GPIOn_CTRL0)
0x0
32
read-write
n
0x0
0x0
CFG0
Port n.0 configuration bits
2
2
CFG1
Port n.1 configuration bits
6
2
CFG2
Port n.2 configuration bits
10
2
CFG3
Port n.3 configuration bits
14
2
CFG4
Port n.4 configuration bits
18
2
CFG5
Port n.5 configuration bits
22
2
CFG6
Port n.6 configuration bits
26
2
CFG7
Port n.7 configuration bits
30
2
MOD0
Port n.0 mode bits
0
2
MOD1
Port n.1 mode bits
4
2
MOD2
Port n.2 mode bits
8
2
MOD3
Port n.3 mode bits
12
2
MOD4
Port n.4 mode bits
16
2
MOD5
Port n.5 mode bits
20
2
MOD6
Port n.6 mode bits
24
2
MOD7
Port n.7 mode bits
28
2
CTRL1
CTRL1
Port configuration register 1 (GPIOn_CTRL1)
0x4
32
read-write
n
0x0
0x0
CFG10
Port n.10 configuration bits
10
2
CFG11
Port n.11 configuration bits
14
2
CFG12
Port n.12 configuration bits
18
2
CFG13
Port n.13 configuration bits
22
2
CFG14
Port n.14 configuration bits
26
2
CFG15
Port n.15 configuration bits
30
2
CFG8
Port n.8 configuration bits
2
2
CFG9
Port n.9 configuration bits
6
2
MOD10
Port n.10 mode bits
8
2
MOD11
Port n.11 mode bits
12
2
MOD12
Port n.12 mode bits
16
2
MOD13
Port n.13 mode bits
20
2
MOD14
Port n.14 mode bits
24
2
MOD15
Port n.15 mode bits
28
2
MOD8
Port n.8 mode bits
0
2
MOD9
Port n.9 mode bits
4
2
DIN
DIN
Port input data register (GPIOn_DIN)
0x8
32
read-only
n
0x0
0x0
DIN0
Port input data
0
1
DIN1
Port input data
1
1
DIN10
Port input data
10
1
DIN11
Port input data
11
1
DIN12
Port input data
12
1
DIN13
Port input data
13
1
DIN14
Port input data
14
1
DIN15
Port input data
15
1
DIN2
Port input data
2
1
DIN3
Port input data
3
1
DIN4
Port input data
4
1
DIN5
Port input data
5
1
DIN6
Port input data
6
1
DIN7
Port input data
7
1
DIN8
Port input data
8
1
DIN9
Port input data
9
1
DOUT
DOUT
Port output data register (GPIOn_DOUT)
0xC
32
read-write
n
0x0
0x0
DOUT0
Port output data
0
1
DOUT1
Port output data
1
1
DOUT10
Port output data
10
1
DOUT11
Port output data
11
1
DOUT12
Port output data
12
1
DOUT13
Port output data
13
1
DOUT14
Port output data
14
1
DOUT15
Port output data
15
1
DOUT2
Port output data
2
1
DOUT3
Port output data
3
1
DOUT4
Port output data
4
1
DOUT5
Port output data
5
1
DOUT6
Port output data
6
1
DOUT7
Port output data
7
1
DOUT8
Port output data
8
1
DOUT9
Port output data
9
1
LOCK
LOCK
Port configuration lock register (GPIOn_LOCK)
0x18
32
read-write
n
0x0
0x0
LCK0
Port A Lock bit 0
0
1
LCK1
Port A Lock bit 1
1
1
LCK10
Port A Lock bit 10
10
1
LCK11
Port A Lock bit 11
11
1
LCK12
Port A Lock bit 12
12
1
LCK13
Port A Lock bit 13
13
1
LCK14
Port A Lock bit 14
14
1
LCK15
Port A Lock bit 15
15
1
LCK2
Port A Lock bit 2
2
1
LCK3
Port A Lock bit 3
3
1
LCK4
Port A Lock bit 4
4
1
LCK5
Port A Lock bit 5
5
1
LCK6
Port A Lock bit 6
6
1
LCK7
Port A Lock bit 7
7
1
LCK8
Port A Lock bit 8
8
1
LCK9
Port A Lock bit 9
9
1
LCKK
Lock key
16
1
GPIOE
General purpose I/O
GPIO
0x0
0x0
0x400
registers
n
BC
BC
Port bit clear register (GPIOn_BC)
0x14
32
write-only
n
0x0
0x0
BC0
Clear bit 0
0
1
BC1
Clear bit 1
1
1
BC10
Clear bit 10
10
1
BC11
Clear bit 11
11
1
BC12
Clear bit 12
12
1
BC13
Clear bit 13
13
1
BC14
Clear bit 14
14
1
BC15
Clear bit 15
15
1
BC2
Clear bit 1
2
1
BC3
Clear bit 3
3
1
BC4
Clear bit 4
4
1
BC5
Clear bit 5
5
1
BC6
Clear bit 6
6
1
BC7
Clear bit 7
7
1
BC8
Clear bit 8
8
1
BC9
Clear bit 9
9
1
BSC
BSC
Port bit set/reset register (GPIOn_BSC)
0x10
32
write-only
n
0x0
0x0
BC0
Clear bit 0
16
1
BC1
Clear bit 1
17
1
BC10
Clear bit 10
26
1
BC11
Clear bit 11
27
1
BC12
Clear bit 12
28
1
BC13
Clear bit 13
29
1
BC14
Clear bit 14
30
1
BC15
Clear bit 15
31
1
BC2
Clear bit 2
18
1
BC3
Clear bit 3
19
1
BC4
Clear bit 4
20
1
BC5
Clear bit 5
21
1
BC6
Clear bit 6
22
1
BC7
Clear bit 7
23
1
BC8
Clear bit 8
24
1
BC9
Clear bit 9
25
1
BS0
Set bit 0
0
1
BS1
Set bit 1
1
1
BS10
Set bit 10
10
1
BS11
Set bit 11
11
1
BS12
Set bit 12
12
1
BS13
Set bit 13
13
1
BS14
Set bit 14
14
1
BS15
Set bit 15
15
1
BS2
Set bit 1
2
1
BS3
Set bit 3
3
1
BS4
Set bit 4
4
1
BS5
Set bit 5
5
1
BS6
Set bit 6
6
1
BS7
Set bit 7
7
1
BS8
Set bit 8
8
1
BS9
Set bit 9
9
1
CTRL0
CTRL0
Port configuration register 0 (GPIOn_CTRL0)
0x0
32
read-write
n
0x0
0x0
CFG0
Port n.0 configuration bits
2
2
CFG1
Port n.1 configuration bits
6
2
CFG2
Port n.2 configuration bits
10
2
CFG3
Port n.3 configuration bits
14
2
CFG4
Port n.4 configuration bits
18
2
CFG5
Port n.5 configuration bits
22
2
CFG6
Port n.6 configuration bits
26
2
CFG7
Port n.7 configuration bits
30
2
MOD0
Port n.0 mode bits
0
2
MOD1
Port n.1 mode bits
4
2
MOD2
Port n.2 mode bits
8
2
MOD3
Port n.3 mode bits
12
2
MOD4
Port n.4 mode bits
16
2
MOD5
Port n.5 mode bits
20
2
MOD6
Port n.6 mode bits
24
2
MOD7
Port n.7 mode bits
28
2
CTRL1
CTRL1
Port configuration register 1 (GPIOn_CTRL1)
0x4
32
read-write
n
0x0
0x0
CFG10
Port n.10 configuration bits
10
2
CFG11
Port n.11 configuration bits
14
2
CFG12
Port n.12 configuration bits
18
2
CFG13
Port n.13 configuration bits
22
2
CFG14
Port n.14 configuration bits
26
2
CFG15
Port n.15 configuration bits
30
2
CFG8
Port n.8 configuration bits
2
2
CFG9
Port n.9 configuration bits
6
2
MOD10
Port n.10 mode bits
8
2
MOD11
Port n.11 mode bits
12
2
MOD12
Port n.12 mode bits
16
2
MOD13
Port n.13 mode bits
20
2
MOD14
Port n.14 mode bits
24
2
MOD15
Port n.15 mode bits
28
2
MOD8
Port n.8 mode bits
0
2
MOD9
Port n.9 mode bits
4
2
DIN
DIN
Port input data register (GPIOn_DIN)
0x8
32
read-only
n
0x0
0x0
DIN0
Port input data
0
1
DIN1
Port input data
1
1
DIN10
Port input data
10
1
DIN11
Port input data
11
1
DIN12
Port input data
12
1
DIN13
Port input data
13
1
DIN14
Port input data
14
1
DIN15
Port input data
15
1
DIN2
Port input data
2
1
DIN3
Port input data
3
1
DIN4
Port input data
4
1
DIN5
Port input data
5
1
DIN6
Port input data
6
1
DIN7
Port input data
7
1
DIN8
Port input data
8
1
DIN9
Port input data
9
1
DOUT
DOUT
Port output data register (GPIOn_DOUT)
0xC
32
read-write
n
0x0
0x0
DOUT0
Port output data
0
1
DOUT1
Port output data
1
1
DOUT10
Port output data
10
1
DOUT11
Port output data
11
1
DOUT12
Port output data
12
1
DOUT13
Port output data
13
1
DOUT14
Port output data
14
1
DOUT15
Port output data
15
1
DOUT2
Port output data
2
1
DOUT3
Port output data
3
1
DOUT4
Port output data
4
1
DOUT5
Port output data
5
1
DOUT6
Port output data
6
1
DOUT7
Port output data
7
1
DOUT8
Port output data
8
1
DOUT9
Port output data
9
1
LOCK
LOCK
Port configuration lock register (GPIOn_LOCK)
0x18
32
read-write
n
0x0
0x0
LCK0
Port A Lock bit 0
0
1
LCK1
Port A Lock bit 1
1
1
LCK10
Port A Lock bit 10
10
1
LCK11
Port A Lock bit 11
11
1
LCK12
Port A Lock bit 12
12
1
LCK13
Port A Lock bit 13
13
1
LCK14
Port A Lock bit 14
14
1
LCK15
Port A Lock bit 15
15
1
LCK2
Port A Lock bit 2
2
1
LCK3
Port A Lock bit 3
3
1
LCK4
Port A Lock bit 4
4
1
LCK5
Port A Lock bit 5
5
1
LCK6
Port A Lock bit 6
6
1
LCK7
Port A Lock bit 7
7
1
LCK8
Port A Lock bit 8
8
1
LCK9
Port A Lock bit 9
9
1
LCKK
Lock key
16
1
GPIOF
General purpose I/O
GPIO
0x0
0x0
0x400
registers
n
BC
BC
Port bit clear register (GPIOn_BC)
0x14
32
write-only
n
0x0
0x0
BC0
Clear bit 0
0
1
BC1
Clear bit 1
1
1
BC10
Clear bit 10
10
1
BC11
Clear bit 11
11
1
BC12
Clear bit 12
12
1
BC13
Clear bit 13
13
1
BC14
Clear bit 14
14
1
BC15
Clear bit 15
15
1
BC2
Clear bit 1
2
1
BC3
Clear bit 3
3
1
BC4
Clear bit 4
4
1
BC5
Clear bit 5
5
1
BC6
Clear bit 6
6
1
BC7
Clear bit 7
7
1
BC8
Clear bit 8
8
1
BC9
Clear bit 9
9
1
BSC
BSC
Port bit set/reset register (GPIOn_BSC)
0x10
32
write-only
n
0x0
0x0
BC0
Clear bit 0
16
1
BC1
Clear bit 1
17
1
BC10
Clear bit 10
26
1
BC11
Clear bit 11
27
1
BC12
Clear bit 12
28
1
BC13
Clear bit 13
29
1
BC14
Clear bit 14
30
1
BC15
Clear bit 15
31
1
BC2
Clear bit 2
18
1
BC3
Clear bit 3
19
1
BC4
Clear bit 4
20
1
BC5
Clear bit 5
21
1
BC6
Clear bit 6
22
1
BC7
Clear bit 7
23
1
BC8
Clear bit 8
24
1
BC9
Clear bit 9
25
1
BS0
Set bit 0
0
1
BS1
Set bit 1
1
1
BS10
Set bit 10
10
1
BS11
Set bit 11
11
1
BS12
Set bit 12
12
1
BS13
Set bit 13
13
1
BS14
Set bit 14
14
1
BS15
Set bit 15
15
1
BS2
Set bit 1
2
1
BS3
Set bit 3
3
1
BS4
Set bit 4
4
1
BS5
Set bit 5
5
1
BS6
Set bit 6
6
1
BS7
Set bit 7
7
1
BS8
Set bit 8
8
1
BS9
Set bit 9
9
1
CTRL0
CTRL0
Port configuration register 0 (GPIOn_CTRL0)
0x0
32
read-write
n
0x0
0x0
CFG0
Port n.0 configuration bits
2
2
CFG1
Port n.1 configuration bits
6
2
CFG2
Port n.2 configuration bits
10
2
CFG3
Port n.3 configuration bits
14
2
CFG4
Port n.4 configuration bits
18
2
CFG5
Port n.5 configuration bits
22
2
CFG6
Port n.6 configuration bits
26
2
CFG7
Port n.7 configuration bits
30
2
MOD0
Port n.0 mode bits
0
2
MOD1
Port n.1 mode bits
4
2
MOD2
Port n.2 mode bits
8
2
MOD3
Port n.3 mode bits
12
2
MOD4
Port n.4 mode bits
16
2
MOD5
Port n.5 mode bits
20
2
MOD6
Port n.6 mode bits
24
2
MOD7
Port n.7 mode bits
28
2
CTRL1
CTRL1
Port configuration register 1 (GPIOn_CTRL1)
0x4
32
read-write
n
0x0
0x0
CFG10
Port n.10 configuration bits
10
2
CFG11
Port n.11 configuration bits
14
2
CFG12
Port n.12 configuration bits
18
2
CFG13
Port n.13 configuration bits
22
2
CFG14
Port n.14 configuration bits
26
2
CFG15
Port n.15 configuration bits
30
2
CFG8
Port n.8 configuration bits
2
2
CFG9
Port n.9 configuration bits
6
2
MOD10
Port n.10 mode bits
8
2
MOD11
Port n.11 mode bits
12
2
MOD12
Port n.12 mode bits
16
2
MOD13
Port n.13 mode bits
20
2
MOD14
Port n.14 mode bits
24
2
MOD15
Port n.15 mode bits
28
2
MOD8
Port n.8 mode bits
0
2
MOD9
Port n.9 mode bits
4
2
DIN
DIN
Port input data register (GPIOn_DIN)
0x8
32
read-only
n
0x0
0x0
DIN0
Port input data
0
1
DIN1
Port input data
1
1
DIN10
Port input data
10
1
DIN11
Port input data
11
1
DIN12
Port input data
12
1
DIN13
Port input data
13
1
DIN14
Port input data
14
1
DIN15
Port input data
15
1
DIN2
Port input data
2
1
DIN3
Port input data
3
1
DIN4
Port input data
4
1
DIN5
Port input data
5
1
DIN6
Port input data
6
1
DIN7
Port input data
7
1
DIN8
Port input data
8
1
DIN9
Port input data
9
1
DOUT
DOUT
Port output data register (GPIOn_DOUT)
0xC
32
read-write
n
0x0
0x0
DOUT0
Port output data
0
1
DOUT1
Port output data
1
1
DOUT10
Port output data
10
1
DOUT11
Port output data
11
1
DOUT12
Port output data
12
1
DOUT13
Port output data
13
1
DOUT14
Port output data
14
1
DOUT15
Port output data
15
1
DOUT2
Port output data
2
1
DOUT3
Port output data
3
1
DOUT4
Port output data
4
1
DOUT5
Port output data
5
1
DOUT6
Port output data
6
1
DOUT7
Port output data
7
1
DOUT8
Port output data
8
1
DOUT9
Port output data
9
1
LOCK
LOCK
Port configuration lock register (GPIOn_LOCK)
0x18
32
read-write
n
0x0
0x0
LCK0
Port A Lock bit 0
0
1
LCK1
Port A Lock bit 1
1
1
LCK10
Port A Lock bit 10
10
1
LCK11
Port A Lock bit 11
11
1
LCK12
Port A Lock bit 12
12
1
LCK13
Port A Lock bit 13
13
1
LCK14
Port A Lock bit 14
14
1
LCK15
Port A Lock bit 15
15
1
LCK2
Port A Lock bit 2
2
1
LCK3
Port A Lock bit 3
3
1
LCK4
Port A Lock bit 4
4
1
LCK5
Port A Lock bit 5
5
1
LCK6
Port A Lock bit 6
6
1
LCK7
Port A Lock bit 7
7
1
LCK8
Port A Lock bit 8
8
1
LCK9
Port A Lock bit 9
9
1
LCKK
Lock key
16
1
GPIOG
General purpose I/O
GPIO
0x0
0x0
0x400
registers
n
BC
BC
Port bit clear register (GPIOn_BC)
0x14
32
write-only
n
0x0
0x0
BC0
Clear bit 0
0
1
BC1
Clear bit 1
1
1
BC10
Clear bit 10
10
1
BC11
Clear bit 11
11
1
BC12
Clear bit 12
12
1
BC13
Clear bit 13
13
1
BC14
Clear bit 14
14
1
BC15
Clear bit 15
15
1
BC2
Clear bit 1
2
1
BC3
Clear bit 3
3
1
BC4
Clear bit 4
4
1
BC5
Clear bit 5
5
1
BC6
Clear bit 6
6
1
BC7
Clear bit 7
7
1
BC8
Clear bit 8
8
1
BC9
Clear bit 9
9
1
BSC
BSC
Port bit set/reset register (GPIOn_BSC)
0x10
32
write-only
n
0x0
0x0
BC0
Clear bit 0
16
1
BC1
Clear bit 1
17
1
BC10
Clear bit 10
26
1
BC11
Clear bit 11
27
1
BC12
Clear bit 12
28
1
BC13
Clear bit 13
29
1
BC14
Clear bit 14
30
1
BC15
Clear bit 15
31
1
BC2
Clear bit 2
18
1
BC3
Clear bit 3
19
1
BC4
Clear bit 4
20
1
BC5
Clear bit 5
21
1
BC6
Clear bit 6
22
1
BC7
Clear bit 7
23
1
BC8
Clear bit 8
24
1
BC9
Clear bit 9
25
1
BS0
Set bit 0
0
1
BS1
Set bit 1
1
1
BS10
Set bit 10
10
1
BS11
Set bit 11
11
1
BS12
Set bit 12
12
1
BS13
Set bit 13
13
1
BS14
Set bit 14
14
1
BS15
Set bit 15
15
1
BS2
Set bit 1
2
1
BS3
Set bit 3
3
1
BS4
Set bit 4
4
1
BS5
Set bit 5
5
1
BS6
Set bit 6
6
1
BS7
Set bit 7
7
1
BS8
Set bit 8
8
1
BS9
Set bit 9
9
1
CTRL0
CTRL0
Port configuration register 0 (GPIOn_CTRL0)
0x0
32
read-write
n
0x0
0x0
CFG0
Port n.0 configuration bits
2
2
CFG1
Port n.1 configuration bits
6
2
CFG2
Port n.2 configuration bits
10
2
CFG3
Port n.3 configuration bits
14
2
CFG4
Port n.4 configuration bits
18
2
CFG5
Port n.5 configuration bits
22
2
CFG6
Port n.6 configuration bits
26
2
CFG7
Port n.7 configuration bits
30
2
MOD0
Port n.0 mode bits
0
2
MOD1
Port n.1 mode bits
4
2
MOD2
Port n.2 mode bits
8
2
MOD3
Port n.3 mode bits
12
2
MOD4
Port n.4 mode bits
16
2
MOD5
Port n.5 mode bits
20
2
MOD6
Port n.6 mode bits
24
2
MOD7
Port n.7 mode bits
28
2
CTRL1
CTRL1
Port configuration register 1 (GPIOn_CTRL1)
0x4
32
read-write
n
0x0
0x0
CFG10
Port n.10 configuration bits
10
2
CFG11
Port n.11 configuration bits
14
2
CFG12
Port n.12 configuration bits
18
2
CFG13
Port n.13 configuration bits
22
2
CFG14
Port n.14 configuration bits
26
2
CFG15
Port n.15 configuration bits
30
2
CFG8
Port n.8 configuration bits
2
2
CFG9
Port n.9 configuration bits
6
2
MOD10
Port n.10 mode bits
8
2
MOD11
Port n.11 mode bits
12
2
MOD12
Port n.12 mode bits
16
2
MOD13
Port n.13 mode bits
20
2
MOD14
Port n.14 mode bits
24
2
MOD15
Port n.15 mode bits
28
2
MOD8
Port n.8 mode bits
0
2
MOD9
Port n.9 mode bits
4
2
DIN
DIN
Port input data register (GPIOn_DIN)
0x8
32
read-only
n
0x0
0x0
DIN0
Port input data
0
1
DIN1
Port input data
1
1
DIN10
Port input data
10
1
DIN11
Port input data
11
1
DIN12
Port input data
12
1
DIN13
Port input data
13
1
DIN14
Port input data
14
1
DIN15
Port input data
15
1
DIN2
Port input data
2
1
DIN3
Port input data
3
1
DIN4
Port input data
4
1
DIN5
Port input data
5
1
DIN6
Port input data
6
1
DIN7
Port input data
7
1
DIN8
Port input data
8
1
DIN9
Port input data
9
1
DOUT
DOUT
Port output data register (GPIOn_DOUT)
0xC
32
read-write
n
0x0
0x0
DOUT0
Port output data
0
1
DOUT1
Port output data
1
1
DOUT10
Port output data
10
1
DOUT11
Port output data
11
1
DOUT12
Port output data
12
1
DOUT13
Port output data
13
1
DOUT14
Port output data
14
1
DOUT15
Port output data
15
1
DOUT2
Port output data
2
1
DOUT3
Port output data
3
1
DOUT4
Port output data
4
1
DOUT5
Port output data
5
1
DOUT6
Port output data
6
1
DOUT7
Port output data
7
1
DOUT8
Port output data
8
1
DOUT9
Port output data
9
1
LOCK
LOCK
Port configuration lock register (GPIOn_LOCK)
0x18
32
read-write
n
0x0
0x0
LCK0
Port A Lock bit 0
0
1
LCK1
Port A Lock bit 1
1
1
LCK10
Port A Lock bit 10
10
1
LCK11
Port A Lock bit 11
11
1
LCK12
Port A Lock bit 12
12
1
LCK13
Port A Lock bit 13
13
1
LCK14
Port A Lock bit 14
14
1
LCK15
Port A Lock bit 15
15
1
LCK2
Port A Lock bit 2
2
1
LCK3
Port A Lock bit 3
3
1
LCK4
Port A Lock bit 4
4
1
LCK5
Port A Lock bit 5
5
1
LCK6
Port A Lock bit 6
6
1
LCK7
Port A Lock bit 7
7
1
LCK8
Port A Lock bit 8
8
1
LCK9
Port A Lock bit 9
9
1
LCKK
Lock key
16
1
I2C1
Inter integrated circuit 1
I2C
0x0
0x0
0x400
registers
n
I2C1_EV
I2C1 event interrupt
31
I2C1_ER
I2C1 error interrupt
32
ADD1
ADD1
Own address register 1
0x8
32
read-write
n
0x0
0x0
ADD0
Interface address
0
1
ADD1_7
Interface address
1
7
ADD8_9
Interface address
8
2
ADDCFG
15
1
ADDMODE
Addressing mode (slave mode)
16
1
ADD2
ADD2
Own address register 2
0xC
32
read-write
n
0x0
0x0
ADD2
Interface address
1
7
DUALEN
Dual addressing mode enable
0
1
CLKCTRL
CLKCTRL
Clock control register
0x1C
32
read-write
n
0x0
0x0
CDR
Clock control register in Fast/Standard mode (Master mode)
0
12
FASTMODE
I2C master mode selection
15
1
FMDC
Fast mode duty cycle
14
1
CTRL1
CTRL1
Control register 1
0x0
32
read-write
n
0x0
0x0
ACKEN
Acknowledge enable
10
1
ACKPOS
Acknowledge/PEC Position (for data reception)
11
1
ARPEN
ARP enable
4
1
BCEN
General call enable
6
1
I2CEN
Peripheral enable
0
1
PECEN
PEC enable
5
1
SMB
SMBus mode
1
1
SMBT
SMBus type
3
1
SMB_ALT
SMBus alert
13
1
STA
Start generation
8
1
STOP
Stop generation
9
1
STRDIS
Clock stretching disable (Slave mode)
7
1
SWRST
Software reset
15
1
TPECEN
Packet error checking
12
1
CTRL2
CTRL2
Control register 2
0x4
32
read-write
n
0x0
0x0
BUFIE
Buffer interrupt enable
10
1
DMAEN
DMA requests enable
11
1
ERRIE
Error interrupt enable
8
1
EVTIE
Event interrupt enable
9
1
FREQ
Peripheral clock frequency
0
6
LAST
DMA last transfer
12
1
DATA
DATA
Data register
0x10
32
read-write
n
0x0
0x0
DATA
8-bit data register
0
8
STS1
STS1
Status register 1
0x14
32
read-write
n
0x0
0x0
ADDR10F
10-bit header sent (Master mode)
3
1
read-only
ADDRF
Address sent (master mode)/matched (slave mode)
1
1
read-only
AEF
Acknowledge failure
10
1
read-write
ALF
Arbitration lost (master mode)
9
1
read-write
BEF
Bus error
8
1
read-write
BTCF
Byte transfer finished
2
1
read-only
OUF
Overrun/Underrun
11
1
read-write
PECEF
PEC Error in reception
12
1
read-write
RXBENF
Data register not empty (receivers)
6
1
read-only
SBDF
Stop detection (slave mode)
4
1
read-only
SBTCF
Start bit (Master mode)
0
1
read-only
SMB_ALTF
SMBus alert
15
1
read-write
TIMEOUT
Timeout or Tlow error
14
1
read-write
TXBENF
Data register empty (transmitters)
7
1
read-only
STS2
STS2
Status register 2
0x18
32
read-only
n
0x0
0x0
BUSYF
Bus busy
1
1
DMAF
Dual flag (Slave mode)
7
1
MMF
Master/slave
0
1
PEC_DATA
acket error checking register
8
8
RBF
General call address (Slave mode)
4
1
RWMF
Transmitter/receiver
2
1
SMB_DAF
SMBus device default address (Slave mode)
5
1
SMB_HHF
SMBus host header (Slave mode)
6
1
SWITCH
SWITCH
I2C Switching register
0x100
32
read-write
n
0x0
0x0
SWITCH
I2C Switching
0
1
TRISE
TRISE
TRISE register
0x20
32
read-write
n
0x0
0x0
TRISE
Maximum rise time in Fast/Standard mode (Master mode)
0
6
I2C2
Inter integrated circuit 2
I2C
0x0
0x0
0x400
registers
n
I2C2_EV
I2C2 event interrupt
33
I2C2_ER
I2C2 error interrupt
34
ADD1
ADD1
Own address register 1
0x8
32
read-write
n
0x0
0x0
ADD0
Interface address
0
1
ADD1_7
Interface address
1
7
ADD8_9
Interface address
8
2
ADDCFG
15
1
ADDMODE
Addressing mode (slave mode)
16
1
ADD2
ADD2
Own address register 2
0xC
32
read-write
n
0x0
0x0
ADD2
Interface address
1
7
DUALEN
Dual addressing mode enable
0
1
CLKCTRL
CLKCTRL
Clock control register
0x1C
32
read-write
n
0x0
0x0
CDR
Clock control register in Fast/Standard mode (Master mode)
0
12
FASTMODE
I2C master mode selection
15
1
FMDC
Fast mode duty cycle
14
1
CTRL1
CTRL1
Control register 1
0x0
32
read-write
n
0x0
0x0
ACKEN
Acknowledge enable
10
1
ACKPOS
Acknowledge/PEC Position (for data reception)
11
1
ARPEN
ARP enable
4
1
BCEN
General call enable
6
1
I2CEN
Peripheral enable
0
1
PECEN
PEC enable
5
1
SMB
SMBus mode
1
1
SMBT
SMBus type
3
1
SMB_ALT
SMBus alert
13
1
STA
Start generation
8
1
STOP
Stop generation
9
1
STRDIS
Clock stretching disable (Slave mode)
7
1
SWRST
Software reset
15
1
TPECEN
Packet error checking
12
1
CTRL2
CTRL2
Control register 2
0x4
32
read-write
n
0x0
0x0
BUFIE
Buffer interrupt enable
10
1
DMAEN
DMA requests enable
11
1
ERRIE
Error interrupt enable
8
1
EVTIE
Event interrupt enable
9
1
FREQ
Peripheral clock frequency
0
6
LAST
DMA last transfer
12
1
DATA
DATA
Data register
0x10
32
read-write
n
0x0
0x0
DATA
8-bit data register
0
8
STS1
STS1
Status register 1
0x14
32
read-write
n
0x0
0x0
ADDR10F
10-bit header sent (Master mode)
3
1
read-only
ADDRF
Address sent (master mode)/matched (slave mode)
1
1
read-only
AEF
Acknowledge failure
10
1
read-write
ALF
Arbitration lost (master mode)
9
1
read-write
BEF
Bus error
8
1
read-write
BTCF
Byte transfer finished
2
1
read-only
OUF
Overrun/Underrun
11
1
read-write
PECEF
PEC Error in reception
12
1
read-write
RXBENF
Data register not empty (receivers)
6
1
read-only
SBDF
Stop detection (slave mode)
4
1
read-only
SBTCF
Start bit (Master mode)
0
1
read-only
SMB_ALTF
SMBus alert
15
1
read-write
TIMEOUT
Timeout or Tlow error
14
1
read-write
TXBENF
Data register empty (transmitters)
7
1
read-only
STS2
STS2
Status register 2
0x18
32
read-only
n
0x0
0x0
BUSYF
Bus busy
1
1
DMAF
Dual flag (Slave mode)
7
1
MMF
Master/slave
0
1
PEC_DATA
acket error checking register
8
8
RBF
General call address (Slave mode)
4
1
RWMF
Transmitter/receiver
2
1
SMB_DAF
SMBus device default address (Slave mode)
5
1
SMB_HHF
SMBus host header (Slave mode)
6
1
TRISE
TRISE
TRISE register
0x20
32
read-write
n
0x0
0x0
TRISE
Maximum rise time in Fast/Standard mode (Master mode)
0
6
IWDT
Independent watchdog
IWDT
0x0
0x0
0x400
registers
n
CNTRLD
CNTRLD
Reload values register (IWDT_CNTRLD)
0x8
32
read-write
n
0x0
0x0
CNTRLD
Watchdog counter reload value
0
12
DIV
DIV
Frequency Divider register (IWDT_DIV)
0x4
32
read-write
n
0x0
0x0
DIV
Prescaler divider
0
3
KEYWORD
KEYWORD
Key register (IWDT_KEYWORD)
0x0
32
write-only
n
0x0
0x0
KEYWORD
Key value
0
16
STS
STS
Status register (IWDT_STS)
0xC
32
read-only
n
0x0
0x0
CNTRU
Watchdog counter reload value update
1
1
DVU
Watchdog prescaler value update
0
1
NVIC
Nested Vectored Interrupt Controller
NVIC
0x0
0x0
0x1001
registers
n
IABR0
IABR0
Interrupt Active Bit Register
0x300
32
read-only
n
0x0
0x0
ACTIVE
ACTIVE
0
32
IABR1
IABR1
Interrupt Active Bit Register
0x304
32
read-only
n
0x0
0x0
ACTIVE
ACTIVE
0
32
ICER0
ICER0
Interrupt Clear-Enable Register
0x180
32
read-write
n
0x0
0x0
CLRENA
CLRENA
0
32
ICER1
ICER1
Interrupt Clear-Enable Register
0x184
32
read-write
n
0x0
0x0
CLRENA
CLRENA
0
32
ICPR0
ICPR0
Interrupt Clear-Pending Register
0x280
32
read-write
n
0x0
0x0
CLRPEND
CLRPEND
0
32
ICPR1
ICPR1
Interrupt Clear-Pending Register
0x284
32
read-write
n
0x0
0x0
CLRPEND
CLRPEND
0
32
ICTR
ICTR
Interrupt Controller Type Register
0x4
32
read-only
n
0x0
0x0
INTLINESNUM
Total number of interrupt lines in groups
0
4
IPR0
IPR0
Interrupt Priority Register
0x400
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR1
IPR1
Interrupt Priority Register
0x404
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR10
IPR10
Interrupt Priority Register
0x428
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR11
IPR11
Interrupt Priority Register
0x42C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR12
IPR12
Interrupt Priority Register
0x430
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR13
IPR13
Interrupt Priority Register
0x434
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR14
IPR14
Interrupt Priority Register
0x438
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR2
IPR2
Interrupt Priority Register
0x408
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR3
IPR3
Interrupt Priority Register
0x40C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR4
IPR4
Interrupt Priority Register
0x410
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR5
IPR5
Interrupt Priority Register
0x414
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR6
IPR6
Interrupt Priority Register
0x418
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR7
IPR7
Interrupt Priority Register
0x41C
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR8
IPR8
Interrupt Priority Register
0x420
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
IPR9
IPR9
Interrupt Priority Register
0x424
32
read-write
n
0x0
0x0
IPR_N0
IPR_N0
0
8
IPR_N1
IPR_N1
8
8
IPR_N2
IPR_N2
16
8
IPR_N3
IPR_N3
24
8
ISER0
ISER0
Interrupt Set-Enable Register
0x100
32
read-write
n
0x0
0x0
SETENA
SETENA
0
32
ISER1
ISER1
Interrupt Set-Enable Register
0x104
32
read-write
n
0x0
0x0
SETENA
SETENA
0
32
ISPR0
ISPR0
Interrupt Set-Pending Register
0x200
32
read-write
n
0x0
0x0
SETPEND
SETPEND
0
32
ISPR1
ISPR1
Interrupt Set-Pending Register
0x204
32
read-write
n
0x0
0x0
SETPEND
SETPEND
0
32
STIR
STIR
Software Triggered Interrupt Register
0xF00
32
write-only
n
0x0
0x0
INTID
interrupt to be triggered
0
9
PMU
Power control
PMU
0x0
0x0
0x400
registers
n
PVD
PVD through EXTI line detection interrupt
1
CTRL
CTRL
Power control register (PMU_CTRL)
0x0
32
read-write
n
0x0
0x0
BAKRWEN
Disable Bakr Domain write protection
8
1
LPSM
Low Power Deep Sleep
0
1
PLMS
PVD Level Selection
5
3
PVMEN
Power Voltage Detector Enable
4
1
RSBF
Clear STANDBY Flag
3
1
RWUPF
Clear Wake-up Flag
2
1
SBMDS
Power Down Deep Sleep
1
1
CTRLF
CTRLF
Power control/status register (PMU_CTRLF)
0x4
32
read-write
n
0x0
0x0
PVMF
PVD Output
2
1
read-only
SBMF
STANDBY Flag
1
1
read-only
WUPEN
Enable WKUP pin
8
1
read-write
WUPF
Wake-Up Flag
0
1
read-only
RCM
Reset and clock management unit
RCM
0x0
0x0
0x400
registers
n
RCM
RCM global interrupt
5
AHBCLKEN
AHBCLKEN
AHB clock enable register (RCM_AHBCLKEN)
0x14
32
read-write
n
0x0
0x0
CRCCLKE
6
1
DMA1CLKE
DMA1 clock enable
0
1
DMA2CLKE
DMA2 clock enable
1
1
EMMCCLKEN
FSMC clock enable
8
1
FMCCLKE
CRC clock enable
4
1
FPUCLKE
FLITF clock enable
3
1
QSPICLKE
5
1
SDIOCLKE
SDIO clock enable
10
1
SRAMCLKE
SRAM interface clock enable
2
1
APB1CLKEN
APB1CLKEN
APB1 clock enable register (RCM_APB1CLKEN)
0x1C
32
read-write
n
0x0
0x0
BAKRCLKE
Bakr interface clock enable
27
1
CANCLKE
CAN clock enable
25
1
DACCLKE
DAC interface clock enable
29
1
I2C1CLKE
I2C 1 clock enable
21
1
I2C2CLKE
I2C 2 clock enable
22
1
PMUCLKE
Power interface clock enable
28
1
SPI2CLKE
SPI 2 clock enable
14
1
SPI3CLKE
SPI 3 clock enable
15
1
TMR2CLKE
Timer 2 clock enable
0
1
TMR3CLKE
Timer 3 clock enable
1
1
TMR4CLKE
Timer 4 clock enable
2
1
TMR5CLKE
Timer 5 clock enable
3
1
TMR6CLKE
Timer 6 clock enable
4
1
TMR7CLKE
Timer 7 clock enable
5
1
UART4CLKE
UART 4 clock enable
19
1
UART5CLKE
UART 5 clock enable
20
1
USART2CLKE
USART 2 clock enable
17
1
USART3CLKE
USART 3 clock enable
18
1
USBCLKE
USB clock enable
23
1
WWDTCLKE
Window watchdog clock enable
11
1
APB1RST
APB1RST
APB1 peripheral reset register (RCM_APB1RST)
0x10
32
read-write
n
0x0
0x0
BAKRRST
Bakr interface reset
26
1
CANRST
CAN reset
24
1
DACRST
DAC interface reset
28
1
I2C1RST
I2C1 reset
20
1
I2C2RST
I2C2 reset
21
1
PMURST
Power interface reset
27
1
SPI2RST
SPI2 reset
14
1
SPI3RST
SPI3 reset
15
1
TMR2RST
Timer 2 reset
0
1
TMR3RST
Timer 3 reset
1
1
TMR4RST
Timer 4 reset
2
1
TMR5RST
Timer 5 reset
3
1
TMR6RST
Timer 6 reset
4
1
TMR7RST
Timer 7 reset
5
1
UART4RST
UART 4 reset
18
1
UART5RST
UART 5 reset
19
1
USART2RST
USART 2 reset
16
1
USART3RST
USART 3 reset
17
1
USBRST
USB reset
22
1
WWDTRST
Window watchdog reset
11
1
APB2CLKEN
APB2CLKEN
APB2 clock enable register (RCM_APB2CLKEN)
0x18
32
read-write
n
0x0
0x0
ADC1CLKE
ADC 1 interface clock enable
9
1
ADC2CLKE
ADC 2 interface clock enable
10
1
ADC3CLKE
ADC3 interface clock enable
15
1
AFIOCLKE
Alternate function I/O clock enable
0
1
PACLKE
I/O port A clock enable
2
1
PBCLKE
I/O port B clock enable
3
1
PCCLKE
I/O port C clock enable
4
1
PDCLKE
I/O port D clock enable
5
1
PECLKE
I/O port E clock enable
6
1
PFCLKE
I/O port F clock enable
7
1
PGCLKE
I/O port G clock enable
8
1
SPI1CLKE
SPI 1 clock enable
12
1
TMR1CLKE
TMR1 Timer clock enable
11
1
TMR8CLKE
TMR8 Timer clock enable
13
1
USART1CLKE
USART1 clock enable
14
1
APB2RST
APB2RST
APB2 peripheral reset register (RCM_APB2RST)
0xC
32
read-write
n
0x0
0x0
ADC1RST
ADC 1 interface reset
9
1
ADC2RST
ADC 2 interface reset
10
1
ADC3RST
ADC 3 interface reset
15
1
AFIORST
Alternate function I/O reset
0
1
PARST
IO port A reset
2
1
PBRST
IO port B reset
3
1
PCRST
IO port C reset
4
1
PDRST
IO port D reset
5
1
PERST
IO port E reset
6
1
PFRST
IO port F reset
7
1
PGRST
IO port G reset
8
1
SPI1RST
SPI 1 reset
12
1
TMR1RST
TMR1 timer reset
11
1
TMR8RST
TMR8 timer reset
13
1
USART1RST
USART1 reset
14
1
BD
BD
Bakr domain control register (RCM_BD)
0x20
32
read-write
n
0x0
0x0
BDRST
Bakr domain software reset
16
1
read-write
LXTBYP
External Low Speed oscillator bypass
2
1
read-write
LXTEN
External Low Speed oscillator enable
0
1
read-write
LXTRDYF
External Low Speed oscillator ready
1
1
read-only
RTCEN
RTC clock enable
15
1
read-write
RTCSEL
RTC clock source selection
8
2
read-write
CFG
CFG
Clock configuration register (RCM_CFGR)
0x4
32
read-write
n
0x0
0x0
ADCDIV
ADC prescaler
14
2
read-write
AHBDIV
AHB prescaler
4
4
read-write
APB1DIV
APB Low speed prescaler (APB1)
8
3
read-write
APB2DIV
APB High speed prescaler (APB2)
11
3
read-write
COC
Microcontroller clock output
24
3
read-write
FPUDIV
27
1
read-write
PLLMF
PLL Multiplication Factor
18
4
read-write
PLLSEL
PLL entry clock source
16
1
read-write
PLLXTDIV
HSE divider for PLL entry
17
1
read-write
SCS
System Clock Switch Status
2
2
read-only
SCSEL
System clock Switch
0
2
read-write
USBDIV
USB OTG FS prescaler
22
1
read-write
CSTS
CSTS
Control/status register (RCM_CSTS)
0x24
32
read-write
n
0x0
0x0
CLRRSTF
Remove reset flag
24
1
read-write
IWDTRSTF
Independent watchdog reset flag
29
1
read-write
LIRCEN
Internal low speed oscillator enable
0
1
read-write
LIRCRDYF
Internal low speed oscillator ready
1
1
read-only
LPRRSTF
Low-power reset flag
31
1
read-write
PINRSTF
PIN reset flag
26
1
read-write
PWRRSTF
POR/PDR reset flag
27
1
read-write
SWRSTF
Software reset flag
28
1
read-write
WWDTRSTF
Window watchdog reset flag
30
1
read-write
CTRL
CTRL
Clock control register (RCM_CTRL)
0x0
32
read-write
n
0x0
0x0
CSSEN
Clock Security System enable
19
1
read-write
HIRCCAL
Internal High Speed clock Calibration
8
8
read-only
HIRCEN
Internal High Speed clock enable
0
1
read-write
HIRCRDYF
Internal High Speed clock ready flag
1
1
read-only
HIRCTRIM
Internal High Speed clock trimming
3
5
read-write
HXTBYP
External High Speed clock Bypass
18
1
read-write
HXTEN
External High Speed clock enable
16
1
read-write
HXTRDYF
External High Speed clock ready flag
17
1
read-only
PLLEN
PLL enable
24
1
read-write
PLLRDYF
PLL clock ready flag
25
1
read-only
INT
INT
Clock interrupt control register (RCM_INT)
0x8
32
read-write
n
0x0
0x0
CSSIF
Clock Security System Interrupt flag
7
1
read-only
CSSIFC
Clock security system interrupt clear
23
1
write-only
HIRCRDYC
HIR Ready Interrupt Clear
18
1
write-only
HIRCRDYIE
HIR Ready Interrupt Enable
10
1
read-write
HIRCRDYIF
HIR Ready Interrupt flag
2
1
read-only
HXTRDYC
HXT Ready Interrupt Clear
19
1
write-only
HXTRDYIE
HXT Ready Interrupt Enable
11
1
read-write
HXTRDYIF
HXT Ready Interrupt flag
3
1
read-only
LIRCRDYC
LIR Ready Interrupt Clear
16
1
write-only
LIRCRDYIE
LIR Ready Interrupt Enable
8
1
read-write
LIRCRDYIF
LIR Ready Interrupt flag
0
1
read-only
LXTRDYC
LXT Ready Interrupt Clear
17
1
write-only
LXTRDYIE
LXT Ready Interrupt Enable
9
1
read-write
LXTRDYIF
LXT Ready Interrupt flag
1
1
read-only
PLLRDYC
PLL Ready Interrupt Clear
20
1
write-only
PLLRDYIE
PLL Ready Interrupt Enable
12
1
read-write
PLLRDYIF
PLL Ready Interrupt flag
4
1
read-only
RTC
Real time clock
RTC
0x0
0x0
0x400
registers
n
RTC
RTC global interrupt
3
RTCAlarm
RTC Alarms through EXTI line interrupt
41
ALMH
ALMH
RTC alarm clock register High Bit
0x20
32
write-only
n
0x0
0x0
ALM
RTC alarm register high
0
16
ALML
ALML
RTC alarm clock register Low Bit
0x24
32
write-only
n
0x0
0x0
ALM
RTC alarm register low
0
16
CNTH
CNTH
RTC count register High Bit
0x18
32
read-write
n
0x0
0x0
CNT
RTC counter register high
0
16
CNTL
CNTL
RTC count register Low Bit
0x1C
32
read-write
n
0x0
0x0
CNT
RTC counter register Low
0
16
CSTS
CSTS
Control and State register
0x4
32
read-write
n
0x0
0x0
ALMIF
Alarm Flag
1
1
read-write
CFGEN
Configuration Flag
4
1
read-write
OWIF
Overflow Flag
2
1
read-write
RTOPC
RTC operation OFF
5
1
read-only
SECIF
Second Flag
0
1
read-write
SYNCF
Registers Synchronized Flag
3
1
read-write
CTRL
CTRL
Control register
0x0
32
read-write
n
0x0
0x0
ALMIEN
Alarm interrupt Enable
1
1
OWIEN
Overflow interrupt Enable
2
1
SECIEN
Second interrupt Enable
0
1
DIVH
DIVH
RTC predivider remainder register High Bit
0x10
32
read-only
n
0x0
0x0
DIV
RTC prescaler divider register high
0
4
DIVL
DIVL
RTC predivider remainder register Low Bit
0x14
32
read-only
n
0x0
0x0
DIV
RTC prescaler divider register Low
0
16
RDIVH
RDIVH
RTC predivision loading register High Bit
0x8
32
write-only
n
0x0
0x0
DIV
RTC Prescaler Load Register High
0
4
RDIVL
RDIVL
RTC predivision loading register Low Bit
0xC
32
write-only
n
0x0
0x0
DIV
RTC Prescaler Divider Register Low
0
16
SPI1
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI1
SPI1 global interrupt
35
CRCPOLY
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
CTRL1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BMEN
Bidirectional data mode enable
15
1
BMTX
Output enable in bidirectional mode
14
1
BRC
3
3
CLKPHA
0
1
CLKPOL
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNXT
CRC transfer next
12
1
DFL
Data frame format
11
1
ISS
Internal slave select
8
1
LSBF
7
1
MSTMODE
2
1
SPIEN
SPI enable
6
1
SSC
9
1
UMRXO
Receive only
10
1
CTRL2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
RXBNEIE
RX buffer not empty interrupt enable
6
1
RX_DMAEN
Rx buffer DMA enable
0
1
SSOEN
SS output enable
2
1
TXBEIE
Tx buffer empty interrupt enable
7
1
TX_DMAEN
Tx buffer DMA enable
1
1
DATA
DR
data register
0xC
32
read-write
n
0x0
0x0
DATA
Data register
0
16
RXCRC
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RXCRC
Rx CRC register
0
16
STS
SR
status register
0x8
32
read-write
n
0x0
0x0
BUSYF
Busy flag
7
1
read-only
CRCEF
CRC error flag
4
1
read-write
MEF
Mode fault
5
1
read-only
RXBNEF
Receive buffer not empty
0
1
read-only
RXOF
Overrun flag
6
1
read-only
ST
Channel side
2
1
read-only
TXBEF
Transmit buffer empty
1
1
read-only
UDF
Underrun flag
3
1
read-only
TXCRC
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TXCRC
Tx CRC register
0
16
SPI2
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI2
SPI2 global interrupt
36
CRCPOLY
CRCPR
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOLY
CRC polynomial register
0
16
CTRL1
CR1
control register 1
0x0
32
read-write
n
0x0
0x0
BMEN
Bidirectional data mode enable
15
1
BMTX
Output enable in bidirectional mode
14
1
BRC
3
3
CLKPHA
0
1
CLKPOL
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNXT
CRC transfer next
12
1
DFL
Data frame format
11
1
ISS
Internal slave select
8
1
LSBF
7
1
MSTMODE
2
1
SPIEN
SPI enable
6
1
SSC
9
1
UMRXO
Receive only
10
1
CTRL2
CR2
control register 2
0x4
32
read-write
n
0x0
0x0
ERRIE
Error interrupt enable
5
1
RXBNEIE
RX buffer not empty interrupt enable
6
1
RX_DMAEN
Rx buffer DMA enable
0
1
SSOEN
SS output enable
2
1
TXBEIE
Tx buffer empty interrupt enable
7
1
TX_DMAEN
Tx buffer DMA enable
1
1
DATA
DR
data register
0xC
32
read-write
n
0x0
0x0
DATA
Data register
0
16
RXCRC
RXCRCR
RX CRC register
0x14
32
read-only
n
0x0
0x0
RXCRC
Rx CRC register
0
16
STS
SR
status register
0x8
32
read-write
n
0x0
0x0
BUSYF
Busy flag
7
1
read-only
CRCEF
CRC error flag
4
1
read-write
MEF
Mode fault
5
1
read-only
RXBNEF
Receive buffer not empty
0
1
read-only
RXOF
Overrun flag
6
1
read-only
ST
Channel side
2
1
read-only
TXBEF
Transmit buffer empty
1
1
read-only
UDF
Underrun flag
3
1
read-only
TXCRC
TXCRCR
TX CRC register
0x18
32
read-only
n
0x0
0x0
TXCRC
Tx CRC register
0
16
TMR1
Advanced timer
TMR
0x0
0x0
0x400
registers
n
TMR1_BRK
TMR1 Break interrupt
24
TMR1_UP
TMR1 Update interrupt
25
TMR1_TRG_COM
TMR1 Trigger
26
TMR1_CC
TMR1 Capture Compare interrupt
27
AOUTORLD
AOUTORLD
auto-reload register
0x2C
32
read-write
n
0x0
0x0
AOUTORLD
Auto-reload value
0
16
BDT
BDT
Brake and dead zone registers
0x44
32
read-write
n
0x0
0x0
AOEN
Automatic output enable
14
1
BRKEN
Break enable
12
1
BRKPOL
Break polarity
13
1
DTS
Dead-time generator setup
0
8
IMOS
Off-state selection for Idle mode
10
1
PROTCFG
Lock configuration
8
2
RMOS
Off-state selection for Run mode
11
1
WOEN
Main output enable
15
1
CCM1
CCM1_COMPARE
capture/compare mode register 1 (Compare mode)
0x18
32
read-write
n
0x0
0x0
CC1MS
Capture/Compare 1 selection
0
2
CC2MS
Capture/Compare 2 selection
8
2
OC1BEN
Output Compare 1 preload enable
3
1
OC1CEN
Output Compare 1 clear enable
7
1
OC1FEN
Output Compare 1 fast enable
2
1
OC1MS
Output Compare 1 mode
4
3
OC2BEN
Output Compare 2 preload enable
11
1
OC2CEN
Output Compare 2 clear enable
15
1
OC2FEN
Output Compare 2 fast enable
10
1
OC2MS
Output Compare 2 mode
12
3
CCM1_CAPTURE
CCM1_CAPTURE
capture/compare mode register 1 (Capture mode)
CCM1
0x18
32
read-write
n
0x0
0x0
CC1MS
Capture/Compare 1 selection
0
2
CC2MS
Capture/Compare 2 selection
8
2
IC1D
Input capture 1 prescaler
2
2
IC1FC
Input capture 1 filter
4
4
IC2D
Input capture 2 prescaler
10
2
IC2FC
Input capture 2 filter
12
4
CCM2
CCM2_COMPARE
capture/compare mode register 2 (Compare mode)
0x1C
32
read-write
n
0x0
0x0
CC3MS
Capture/Compare 3 selection
0
2
CC4MS
Capture/Compare 4 selection
8
2
OC3BEN
Output compare 3 preload enable
3
1
OC3CEN
Output compare 3 clear enable
7
1
OC3FEN
Output compare 3 fast enable
2
1
OC3MS
Output compare 3 mode
4
3
OC4BEN
Output compare 4 preload enable
11
1
OC4CEN
Output compare 4 clear enable
15
1
OC4FEN
Output compare 4 fast enable
10
1
OC4MS
Output compare 4 mode
12
3
CCM2_CAPTURE
CCM2_CAPTURE
capture/compare mode register 2 (Capture mode)
CCM2
0x1C
32
read-write
n
0x0
0x0
CC3MS
Capture/compare 3 selection
0
2
CC4MS
Capture/Compare 4 selection
8
2
IC3D
Input capture 3 prescaler
2
2
IC3FC
Input capture 3 filter
4
4
IC4D
Input capture 4 prescaler
10
2
IC4FC
Input capture 4 filter
12
4
CH1CC
CH1CC
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CH1CC
Capture/Compare 1 value
0
16
CH2CC
CH2CC
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CH2CC
Capture/Compare 2 value
0
16
CH3CC
CH3CC
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CH3CC
Capture/Compare 3 value
0
16
CH4CC
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CH4CC
Capture/Compare 4 value
0
16
CHCTRL
CHCTRL
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CH1CCEN
Capture/Compare 1 output enable
0
1
CH1CCP
Capture/Compare 1 output Polarity
1
1
CH1OCNEN
Capture/Compare 1 complementary output enable
2
1
CH1OCNP
Capture/Compare 1 output Polarity
3
1
CH2CCEN
Capture/Compare 2 output enable
4
1
CH2CCP
Capture/Compare 2 output Polarity
5
1
CH2OCNEN
Capture/Compare 2 complementary output enable
6
1
CH2OCNP
Capture/Compare 2 output Polarity
7
1
CH3CCEN
Capture/Compare 3 output enable
8
1
CH3CCP
Capture/Compare 3 output Polarity
9
1
CH3OCNEN
Capture/Compare 3 complementary output enable
10
1
CH3OCNP
Capture/Compare 3 output Polarity
11
1
CH4CCEN
Capture/Compare 4 output enable
12
1
CH4CCP
Capture/Compare 3 output Polarity
13
1
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CTRL1
CTRL1
control register 1
0x0
32
read-write
n
0x0
0x0
ARBEN
Auto-reload preload enable
7
1
CKDR
Clock division
8
2
CNTDIR
Direction
4
1
CNTEN
Counter enable
0
1
CNTMODE
Center-aligned mode selection
5
2
NGUE
Update disable
1
1
SPMEN
One-pulse mode
3
1
UES
Update request source
2
1
CTRL2
CTRL2
control register 2
0x4
32
read-write
n
0x0
0x0
CCBEN
Capture/compare preloaded control
0
1
CCDS
Capture/compare DMA selection
3
1
CCUS
Capture/compare control update selection
2
1
CH1ISO
Output Idle state 1
8
1
CH1NISO
Output Idle state 1
9
1
CH2ISO
Output Idle state 2
10
1
CH2NISO
Output Idle state 2
11
1
CH3ISO
Output Idle state 3
12
1
CH3NISO
Output Idle state 3
13
1
CH4ISO
Output Idle state 4
14
1
MMFC
Master mode selection
4
3
TI1IS
TI1 selection
7
1
DCTRL
DCTRL
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIEN
DIEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BRKIEN
Break interrupt enable
7
1
CCUIEN
COM interrupt enable
5
1
CH1CCDEN
Capture/Compare 1 DMA request enable
9
1
CH1CCIEN
Capture/Compare 1 interrupt enable
1
1
CH2CCDEN
Capture/Compare 2 DMA request enable
10
1
CH2CCIEN
Capture/Compare 2 interrupt enable
2
1
CH3CCDEN
Capture/Compare 3 DMA request enable
11
1
CH3CCIEN
Capture/Compare 3 interrupt enable
3
1
CH4CCDEN
Capture/Compare 4 DMA request enable
12
1
CH4CCIEN
Capture/Compare 4 interrupt enable
4
1
CMDEN
COM DMA request enable
13
1
TDEN
Trigger DMA request enable
14
1
TRGIEN
Trigger interrupt enable
6
1
UDEN
Update DMA request enable
8
1
UDIEN
Update interrupt enable
0
1
DIV
DIV
prescaler
0x28
32
read-write
n
0x0
0x0
DIV
Prescaler value
0
16
DMAB
DMAB
Consecutive DMA addresses
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
REPCNT
REPCNT
Repeat count register
0x30
32
read-write
n
0x0
0x0
REPCNT
Auto-reload value
0
16
SCEG
SCEG
event generation register
0x14
32
write-only
n
0x0
0x0
BEG
Break generation
7
1
CCUEG
Capture/Compare control update generation
5
1
CH1CCG
Capture/compare 1 generation
1
1
CH2CCG
Capture/compare 2 generation
2
1
CH3CCG
Capture/compare 3 generation
3
1
CH4CCG
Capture/compare 4 generation
4
1
TEG
Trigger generation
6
1
UEG
Update generation
0
1
SMCTRL
SMCTRL
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECM2EN
External clock enable
14
1
ETDC
External trigger prescaler
12
2
ETFC
External trigger filter
8
4
ETPC
External trigger polarity
15
1
ITC
Trigger selection
4
3
MSMEN
Master/Slave mode
7
1
SMFC
Slave mode selection
0
3
STS
STS
status register
0x10
32
read-write
n
0x0
0x0
BRKIF
Break interrupt flag
7
1
CCUIF
COM interrupt flag
5
1
CH1CCIF
Capture/compare 1 interrupt flag
1
1
CH1RCF
Capture/Compare 1 overcapture flag
9
1
CH2CCIF
Capture/Compare 2 interrupt flag
2
1
CH2RCF
Capture/compare 2 overcapture flag
10
1
CH3CCIF
Capture/Compare 3 interrupt flag
3
1
CH3RCF
Capture/Compare 3 overcapture flag
11
1
CH4CCIF
Capture/Compare 4 interrupt flag
4
1
CH4RCF
Capture/Compare 4 overcapture flag
12
1
TRGIF
Trigger interrupt flag
6
1
UDIF
Update interrupt flag
0
1
TMR2
General purpose timer
TMR
0x0
0x0
0x400
registers
n
TMR2
TMR2 global interrupt
28
AOUTORLD
AOUTORLD
auto-reload register
0x2C
32
read-write
n
0x0
0x0
AOUTORLD
Auto-reload value
0
16
CCM1_Input
CCM1_Input
capture/compare mode register 1 (input mode)
CCM1_Output
0x18
32
read-write
n
0x0
0x0
CC1MS
Capture/Compare 1 selection
0
2
CC2MS
Capture/Compare 2 selection
8
2
IC1D
Input capture 1 prescaler
2
2
IC1FC
Input capture 1 filter
4
4
IC2D
Input capture 2 prescaler
10
2
IC2FC
Input capture 2 filter
12
4
CCM1_Output
CCM1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CC1MS
Capture/Compare 1 selection
0
2
CC2MS
Capture/Compare 2 selection
8
2
OC1BEN
Output Compare 1 preload enable
3
1
OC1CEN
Output Compare 1 clear enable
7
1
OC1FEN
Output Compare 1 fast enable
2
1
OC1MS
Output Compare 1 mode
4
3
OC2BEN
Output Compare 2 preload enable
11
1
OC2CEN
Output Compare 2 clear enable
15
1
OC2FEN
Output Compare 2 fast enable
10
1
OC2MS
Output Compare 2 mode
12
3
CCM2_Input
CCM2_Input
capture/compare mode register 2 (input mode)
CCM2_Output
0x1C
32
read-write
n
0x0
0x0
CC3MS
Capture/compare 3 selection
0
2
CC4MS
Capture/Compare 4 selection
8
2
IC3D
Input capture 3 prescaler
2
2
IC3FC
Input capture 3 filter
4
4
IC4D
Input capture 4 prescaler
10
2
IC4FC
Input capture 4 filter
12
4
CCM2_Output
CCM2_Output
capture/compare mode register (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3MS
Capture/Compare 3 selection
0
2
CC4MS
Capture/Compare 4 selection
8
2
OC3BEN
Output compare 3 preload enable
3
1
OC3CEN
Output compare 3 clear enable
7
1
OC3FEN
Output compare 3 fast enable
2
1
OC3MS
Output compare 3 mode
4
3
OC4BEN
Output compare 4 preload enable
11
1
OC4CEN
Output compare 4 clear enable
15
1
OC4FEN
Output compare 4 fast enable
10
1
OC4MS
Output compare 4 mode
12
3
CH1CC
CH1CC
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CH1CC
Capture/Compare 1 value
0
16
CH2CC
CH2CC
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CH2CC
Capture/Compare 2 value
0
16
CH3CC
CH3CC
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CH3CC
Capture/Compare 3 value
0
16
CH4CC
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CH4CC
Capture/Compare 4 value
0
16
CHCTRL
CHCTRL
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CH1CCEN
Capture/Compare 1 output enable
0
1
CH1CCP
Capture/Compare 1 output Polarity
1
1
CH1OCNEN
Capture/Compare 1 complementary output enable
2
1
CH1OCNP
Capture/Compare 1 output Polarity
3
1
CH2CCEN
Capture/Compare 2 output enable
4
1
CH2CCP
Capture/Compare 2 output Polarity
5
1
CH2OCNEN
Capture/Compare 2 complementary output enable
6
1
CH2OCNP
Capture/Compare 2 output Polarity
7
1
CH3CCEN
Capture/Compare 3 output enable
8
1
CH3CCP
Capture/Compare 3 output Polarity
9
1
CH3OCNEN
Capture/Compare 3 complementary output enable
10
1
CH3OCNP
Capture/Compare 3 output Polarity
11
1
CH4CCEN
Capture/Compare 4 output enable
12
1
CH4CCP
Capture/Compare 3 output Polarity
13
1
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CTRL1
CTRL1
control register 1
0x0
32
read-write
n
0x0
0x0
ARBEN
Auto-reload preload enable
7
1
CKDR
Clock division
8
2
CNTDIR
Direction
4
1
CNTEN
Counter enable
0
1
CNTMODE
Center-aligned mode selection
5
2
NGUE
Update disable
1
1
SPMEN
One-pulse mode
3
1
UES
Update request source
2
1
CTRL2
CTRL2
control register 2
0x4
32
read-write
n
0x0
0x0
MMFC
Master mode selection
4
3
TI1IS
TI1 selection
7
1
DCTRL
DCTRL
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIEN
DIEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CH1CCDEN
Capture/Compare 1 DMA request enable
9
1
CH1CCIEN
Capture/Compare 1 interrupt enable
1
1
CH2CCDEN
Capture/Compare 2 DMA request enable
10
1
CH2CCIEN
Capture/Compare 2 interrupt enable
2
1
CH3CCDEN
Capture/Compare 3 DMA request enable
11
1
CH3CCIEN
Capture/Compare 3 interrupt enable
3
1
CH4CCDEN
Capture/Compare 4 DMA request enable
12
1
CH4CCIEN
Capture/Compare 4 interrupt enable
4
1
TDEN
Trigger DMA request enable
14
1
TRGIEN
Trigger interrupt enable
6
1
UDEN
Update DMA request enable
8
1
UDIEN
Update interrupt enable
0
1
DIV
DIV
prescaler
0x28
32
read-write
n
0x0
0x0
DIV
Prescaler value
0
16
DMAB
DMAB
Consecutive DMA addresses
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
SCEG
SCEG
event generation register
0x14
32
write-only
n
0x0
0x0
CCUEG
Capture/Compare control update generation
5
1
CH1CCG
Capture/compare 1 generation
1
1
CH2CCG
Capture/compare 2 generation
2
1
CH3CCG
Capture/compare 3 generation
3
1
CH4CCG
Capture/compare 4 generation
4
1
TEG
Trigger generation
6
1
UEG
Update generation
0
1
SMCTRL
SMCTRL
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECM2EN
External clock enable
14
1
ETDC
External trigger prescaler
12
2
ETFC
External trigger filter
8
4
ETPC
External trigger polarity
15
1
ITC
Trigger selection
4
3
MSMEN
Master/Slave mode
7
1
SMFC
Slave mode selection
0
3
STS
STS
status register
0x10
32
read-write
n
0x0
0x0
CH1CCIF
Capture/compare 1 interrupt flag
1
1
CH1RCF
Capture/Compare 1 overcapture flag
9
1
CH2CCIF
Capture/Compare 2 interrupt flag
2
1
CH2RCF
Capture/compare 2 overcapture flag
10
1
CH3CCIF
Capture/Compare 3 interrupt flag
3
1
CH3RCF
Capture/Compare 3 overcapture flag
11
1
CH4CCIF
Capture/Compare 4 interrupt flag
4
1
CH4RCF
Capture/Compare 4 overcapture flag
12
1
TRGIF
Trigger interrupt flag
6
1
UDIF
Update interrupt flag
0
1
TMR3
General purpose timer
TMR
0x0
0x0
0x400
registers
n
TMR3
TMR3 global interrupt
29
AOUTORLD
AOUTORLD
auto-reload register
0x2C
32
read-write
n
0x0
0x0
AOUTORLD
Auto-reload value
0
16
CCM1_Input
CCM1_Input
capture/compare mode register 1 (input mode)
CCM1_Output
0x18
32
read-write
n
0x0
0x0
CC1MS
Capture/Compare 1 selection
0
2
CC2MS
Capture/Compare 2 selection
8
2
IC1D
Input capture 1 prescaler
2
2
IC1FC
Input capture 1 filter
4
4
IC2D
Input capture 2 prescaler
10
2
IC2FC
Input capture 2 filter
12
4
CCM1_Output
CCM1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CC1MS
Capture/Compare 1 selection
0
2
CC2MS
Capture/Compare 2 selection
8
2
OC1BEN
Output Compare 1 preload enable
3
1
OC1CEN
Output Compare 1 clear enable
7
1
OC1FEN
Output Compare 1 fast enable
2
1
OC1MS
Output Compare 1 mode
4
3
OC2BEN
Output Compare 2 preload enable
11
1
OC2CEN
Output Compare 2 clear enable
15
1
OC2FEN
Output Compare 2 fast enable
10
1
OC2MS
Output Compare 2 mode
12
3
CCM2_Input
CCM2_Input
capture/compare mode register 2 (input mode)
CCM2_Output
0x1C
32
read-write
n
0x0
0x0
CC3MS
Capture/compare 3 selection
0
2
CC4MS
Capture/Compare 4 selection
8
2
IC3D
Input capture 3 prescaler
2
2
IC3FC
Input capture 3 filter
4
4
IC4D
Input capture 4 prescaler
10
2
IC4FC
Input capture 4 filter
12
4
CCM2_Output
CCM2_Output
capture/compare mode register (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3MS
Capture/Compare 3 selection
0
2
CC4MS
Capture/Compare 4 selection
8
2
OC3BEN
Output compare 3 preload enable
3
1
OC3CEN
Output compare 3 clear enable
7
1
OC3FEN
Output compare 3 fast enable
2
1
OC3MS
Output compare 3 mode
4
3
OC4BEN
Output compare 4 preload enable
11
1
OC4CEN
Output compare 4 clear enable
15
1
OC4FEN
Output compare 4 fast enable
10
1
OC4MS
Output compare 4 mode
12
3
CH1CC
CH1CC
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CH1CC
Capture/Compare 1 value
0
16
CH2CC
CH2CC
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CH2CC
Capture/Compare 2 value
0
16
CH3CC
CH3CC
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CH3CC
Capture/Compare 3 value
0
16
CH4CC
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CH4CC
Capture/Compare 4 value
0
16
CHCTRL
CHCTRL
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CH1CCEN
Capture/Compare 1 output enable
0
1
CH1CCP
Capture/Compare 1 output Polarity
1
1
CH1OCNEN
Capture/Compare 1 complementary output enable
2
1
CH1OCNP
Capture/Compare 1 output Polarity
3
1
CH2CCEN
Capture/Compare 2 output enable
4
1
CH2CCP
Capture/Compare 2 output Polarity
5
1
CH2OCNEN
Capture/Compare 2 complementary output enable
6
1
CH2OCNP
Capture/Compare 2 output Polarity
7
1
CH3CCEN
Capture/Compare 3 output enable
8
1
CH3CCP
Capture/Compare 3 output Polarity
9
1
CH3OCNEN
Capture/Compare 3 complementary output enable
10
1
CH3OCNP
Capture/Compare 3 output Polarity
11
1
CH4CCEN
Capture/Compare 4 output enable
12
1
CH4CCP
Capture/Compare 3 output Polarity
13
1
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CTRL1
CTRL1
control register 1
0x0
32
read-write
n
0x0
0x0
ARBEN
Auto-reload preload enable
7
1
CKDR
Clock division
8
2
CNTDIR
Direction
4
1
CNTEN
Counter enable
0
1
CNTMODE
Center-aligned mode selection
5
2
NGUE
Update disable
1
1
SPMEN
One-pulse mode
3
1
UES
Update request source
2
1
CTRL2
CTRL2
control register 2
0x4
32
read-write
n
0x0
0x0
MMFC
Master mode selection
4
3
TI1IS
TI1 selection
7
1
DCTRL
DCTRL
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIEN
DIEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CH1CCDEN
Capture/Compare 1 DMA request enable
9
1
CH1CCIEN
Capture/Compare 1 interrupt enable
1
1
CH2CCDEN
Capture/Compare 2 DMA request enable
10
1
CH2CCIEN
Capture/Compare 2 interrupt enable
2
1
CH3CCDEN
Capture/Compare 3 DMA request enable
11
1
CH3CCIEN
Capture/Compare 3 interrupt enable
3
1
CH4CCDEN
Capture/Compare 4 DMA request enable
12
1
CH4CCIEN
Capture/Compare 4 interrupt enable
4
1
TDEN
Trigger DMA request enable
14
1
TRGIEN
Trigger interrupt enable
6
1
UDEN
Update DMA request enable
8
1
UDIEN
Update interrupt enable
0
1
DIV
DIV
prescaler
0x28
32
read-write
n
0x0
0x0
DIV
Prescaler value
0
16
DMAB
DMAB
Consecutive DMA addresses
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
SCEG
SCEG
event generation register
0x14
32
write-only
n
0x0
0x0
CCUEG
Capture/Compare control update generation
5
1
CH1CCG
Capture/compare 1 generation
1
1
CH2CCG
Capture/compare 2 generation
2
1
CH3CCG
Capture/compare 3 generation
3
1
CH4CCG
Capture/compare 4 generation
4
1
TEG
Trigger generation
6
1
UEG
Update generation
0
1
SMCTRL
SMCTRL
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECM2EN
External clock enable
14
1
ETDC
External trigger prescaler
12
2
ETFC
External trigger filter
8
4
ETPC
External trigger polarity
15
1
ITC
Trigger selection
4
3
MSMEN
Master/Slave mode
7
1
SMFC
Slave mode selection
0
3
STS
STS
status register
0x10
32
read-write
n
0x0
0x0
CH1CCIF
Capture/compare 1 interrupt flag
1
1
CH1RCF
Capture/Compare 1 overcapture flag
9
1
CH2CCIF
Capture/Compare 2 interrupt flag
2
1
CH2RCF
Capture/compare 2 overcapture flag
10
1
CH3CCIF
Capture/Compare 3 interrupt flag
3
1
CH3RCF
Capture/Compare 3 overcapture flag
11
1
CH4CCIF
Capture/Compare 4 interrupt flag
4
1
CH4RCF
Capture/Compare 4 overcapture flag
12
1
TRGIF
Trigger interrupt flag
6
1
UDIF
Update interrupt flag
0
1
TMR4
General purpose timer
TMR
0x0
0x0
0x400
registers
n
TMR4
TMR4 global interrupt
30
AOUTORLD
AOUTORLD
auto-reload register
0x2C
32
read-write
n
0x0
0x0
AOUTORLD
Auto-reload value
0
16
CCM1_Input
CCM1_Input
capture/compare mode register 1 (input mode)
CCM1_Output
0x18
32
read-write
n
0x0
0x0
CC1MS
Capture/Compare 1 selection
0
2
CC2MS
Capture/Compare 2 selection
8
2
IC1D
Input capture 1 prescaler
2
2
IC1FC
Input capture 1 filter
4
4
IC2D
Input capture 2 prescaler
10
2
IC2FC
Input capture 2 filter
12
4
CCM1_Output
CCM1_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CC1MS
Capture/Compare 1 selection
0
2
CC2MS
Capture/Compare 2 selection
8
2
OC1BEN
Output Compare 1 preload enable
3
1
OC1CEN
Output Compare 1 clear enable
7
1
OC1FEN
Output Compare 1 fast enable
2
1
OC1MS
Output Compare 1 mode
4
3
OC2BEN
Output Compare 2 preload enable
11
1
OC2CEN
Output Compare 2 clear enable
15
1
OC2FEN
Output Compare 2 fast enable
10
1
OC2MS
Output Compare 2 mode
12
3
CCM2_Input
CCM2_Input
capture/compare mode register 2 (input mode)
CCM2_Output
0x1C
32
read-write
n
0x0
0x0
CC3MS
Capture/compare 3 selection
0
2
CC4MS
Capture/Compare 4 selection
8
2
IC3D
Input capture 3 prescaler
2
2
IC3FC
Input capture 3 filter
4
4
IC4D
Input capture 4 prescaler
10
2
IC4FC
Input capture 4 filter
12
4
CCM2_Output
CCM2_Output
capture/compare mode register (output mode)
0x1C
32
read-write
n
0x0
0x0
CC3MS
Capture/Compare 3 selection
0
2
CC4MS
Capture/Compare 4 selection
8
2
OC3BEN
Output compare 3 preload enable
3
1
OC3CEN
Output compare 3 clear enable
7
1
OC3FEN
Output compare 3 fast enable
2
1
OC3MS
Output compare 3 mode
4
3
OC4BEN
Output compare 4 preload enable
11
1
OC4CEN
Output compare 4 clear enable
15
1
OC4FEN
Output compare 4 fast enable
10
1
OC4MS
Output compare 4 mode
12
3
CH1CC
CH1CC
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CH1CC
Capture/Compare 1 value
0
16
CH2CC
CH2CC
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CH2CC
Capture/Compare 2 value
0
16
CH3CC
CH3CC
capture/compare register 3
0x3C
32
read-write
n
0x0
0x0
CH3CC
Capture/Compare 3 value
0
16
CH4CC
CCR4
capture/compare register 4
0x40
32
read-write
n
0x0
0x0
CH4CC
Capture/Compare 4 value
0
16
CHCTRL
CHCTRL
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CH1CCEN
Capture/Compare 1 output enable
0
1
CH1CCP
Capture/Compare 1 output Polarity
1
1
CH1OCNEN
Capture/Compare 1 complementary output enable
2
1
CH1OCNP
Capture/Compare 1 output Polarity
3
1
CH2CCEN
Capture/Compare 2 output enable
4
1
CH2CCP
Capture/Compare 2 output Polarity
5
1
CH2OCNEN
Capture/Compare 2 complementary output enable
6
1
CH2OCNP
Capture/Compare 2 output Polarity
7
1
CH3CCEN
Capture/Compare 3 output enable
8
1
CH3CCP
Capture/Compare 3 output Polarity
9
1
CH3OCNEN
Capture/Compare 3 complementary output enable
10
1
CH3OCNP
Capture/Compare 3 output Polarity
11
1
CH4CCEN
Capture/Compare 4 output enable
12
1
CH4CCP
Capture/Compare 3 output Polarity
13
1
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CTRL1
CTRL1
control register 1
0x0
32
read-write
n
0x0
0x0
ARBEN
Auto-reload preload enable
7
1
CKDR
Clock division
8
2
CNTDIR
Direction
4
1
CNTEN
Counter enable
0
1
CNTMODE
Center-aligned mode selection
5
2
NGUE
Update disable
1
1
SPMEN
One-pulse mode
3
1
UES
Update request source
2
1
CTRL2
CTRL2
control register 2
0x4
32
read-write
n
0x0
0x0
MMFC
Master mode selection
4
3
TI1IS
TI1 selection
7
1
DCTRL
DCTRL
DMA control register
0x48
32
read-write
n
0x0
0x0
DBA
DMA base address
0
5
DBL
DMA burst length
8
5
DIEN
DIEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CH1CCDEN
Capture/Compare 1 DMA request enable
9
1
CH1CCIEN
Capture/Compare 1 interrupt enable
1
1
CH2CCDEN
Capture/Compare 2 DMA request enable
10
1
CH2CCIEN
Capture/Compare 2 interrupt enable
2
1
CH3CCDEN
Capture/Compare 3 DMA request enable
11
1
CH3CCIEN
Capture/Compare 3 interrupt enable
3
1
CH4CCDEN
Capture/Compare 4 DMA request enable
12
1
CH4CCIEN
Capture/Compare 4 interrupt enable
4
1
TDEN
Trigger DMA request enable
14
1
TRGIEN
Trigger interrupt enable
6
1
UDEN
Update DMA request enable
8
1
UDIEN
Update interrupt enable
0
1
DIV
DIV
prescaler
0x28
32
read-write
n
0x0
0x0
DIV
Prescaler value
0
16
DMAB
DMAB
Consecutive DMA addresses
0x4C
32
read-write
n
0x0
0x0
DMAB
DMA register for burst accesses
0
16
SCEG
SCEG
event generation register
0x14
32
write-only
n
0x0
0x0
CCUEG
Capture/Compare control update generation
5
1
CH1CCG
Capture/compare 1 generation
1
1
CH2CCG
Capture/compare 2 generation
2
1
CH3CCG
Capture/compare 3 generation
3
1
CH4CCG
Capture/compare 4 generation
4
1
TEG
Trigger generation
6
1
UEG
Update generation
0
1
SMCTRL
SMCTRL
slave mode control register
0x8
32
read-write
n
0x0
0x0
ECM2EN
External clock enable
14
1
ETDC
External trigger prescaler
12
2
ETFC
External trigger filter
8
4
ETPC
External trigger polarity
15
1
ITC
Trigger selection
4
3
MSMEN
Master/Slave mode
7
1
SMFC
Slave mode selection
0
3
STS
STS
status register
0x10
32
read-write
n
0x0
0x0
CH1CCIF
Capture/compare 1 interrupt flag
1
1
CH1RCF
Capture/Compare 1 overcapture flag
9
1
CH2CCIF
Capture/Compare 2 interrupt flag
2
1
CH2RCF
Capture/compare 2 overcapture flag
10
1
CH3CCIF
Capture/Compare 3 interrupt flag
3
1
CH3RCF
Capture/Compare 3 overcapture flag
11
1
CH4CCIF
Capture/Compare 4 interrupt flag
4
1
CH4RCF
Capture/Compare 4 overcapture flag
12
1
TRGIF
Trigger interrupt flag
6
1
UDIF
Update interrupt flag
0
1
USART1
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART1
USART1 global interrupt
37
BR
BR
Baud rate register
0x8
32
read-write
n
0x0
0x0
FRACTION
fraction of USARTDIV
0
4
MANTISSA
mantissa of USARTDIV
4
12
CTRL1
CTRL1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
PCEN
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PMSEL
Parity selection
9
1
RXBNEIE
RXNE interrupt enable
5
1
RXEN
Receiver enable
2
1
RXWUP
Receiver wakeup
1
1
TXBEIE
TXE interrupt enable
7
1
TXBK
Send break
0
1
TXCIE
Transmission complete interrupt enable
6
1
TXEN
Transmitter enable
3
1
UEN
USART enable
13
1
WLS
Word length
12
1
WUPM
Wakeup method
11
1
CTRL2
CTRL2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADDR
Address of the USART node
0
4
CKPEN
Clock enable
11
1
CLKPHA
Clock phase
9
1
CLKPOL
Clock polarity
10
1
LBCEN
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOPB
STOP bits
12
2
CTRL3
CTRL3
Control register 3
0x14
32
read-write
n
0x0
0x0
CTSEN
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
ERRIE
Error interrupt enable
0
1
HDEN
Half-duplex selection
3
1
IRDAEN
IrDA mode enable
1
1
IRDALP
IrDA low-power
2
1
NACKEN
Smartcard NACK enable
4
1
RTSEN
RTS enable
8
1
RXDMAEN
DMA enable receiver
6
1
SCEN
Smartcard mode enable
5
1
TXDMAEN
DMA enable transmitter
7
1
DATA
DATA
TX Buffer Data Register
0x4
32
read-write
n
0x0
0x0
DATA
Data value
0
9
GTDIV
GTDIV
Guard time and divider number register
0x18
32
read-write
n
0x0
0x0
DIV
Prescaler value
0
8
GT
Guard time value
8
8
STS
STS
Status register
0x0
32
read-write
n
0x0
0x0
CTSF
CTS flag
9
1
read-write
FEF
Framing error
1
1
read-only
IDLEF
IDLE line detected
4
1
read-only
LBDF
LIN break detection flag
8
1
read-write
NEF
Noise error flag
2
1
read-only
OVREF
Overrun error
3
1
read-only
PEF
Parity error
0
1
read-only
RXBNEF
Read data register not empty
5
1
read-write
TXBEF
Transmit data register empty
7
1
read-only
TXCF
Transmission complete
6
1
read-write
USART2
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART2
USART2 global interrupt
38
BR
BR
Baud rate register
0x8
32
read-write
n
0x0
0x0
FRACTION
fraction of USARTDIV
0
4
MANTISSA
mantissa of USARTDIV
4
12
CTRL1
CTRL1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
PCEN
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PMSEL
Parity selection
9
1
RXBNEIE
RXNE interrupt enable
5
1
RXEN
Receiver enable
2
1
RXWUP
Receiver wakeup
1
1
TXBEIE
TXE interrupt enable
7
1
TXBK
Send break
0
1
TXCIE
Transmission complete interrupt enable
6
1
TXEN
Transmitter enable
3
1
UEN
USART enable
13
1
WLS
Word length
12
1
WUPM
Wakeup method
11
1
CTRL2
CTRL2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADDR
Address of the USART node
0
4
CKPEN
Clock enable
11
1
CLKPHA
Clock phase
9
1
CLKPOL
Clock polarity
10
1
LBCEN
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOPB
STOP bits
12
2
CTRL3
CTRL3
Control register 3
0x14
32
read-write
n
0x0
0x0
CTSEN
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
ERRIE
Error interrupt enable
0
1
HDEN
Half-duplex selection
3
1
IRDAEN
IrDA mode enable
1
1
IRDALP
IrDA low-power
2
1
NACKEN
Smartcard NACK enable
4
1
RTSEN
RTS enable
8
1
RXDMAEN
DMA enable receiver
6
1
SCEN
Smartcard mode enable
5
1
TXDMAEN
DMA enable transmitter
7
1
DATA
DATA
TX Buffer Data Register
0x4
32
read-write
n
0x0
0x0
DATA
Data value
0
9
GTDIV
GTDIV
Guard time and divider number register
0x18
32
read-write
n
0x0
0x0
DIV
Prescaler value
0
8
GT
Guard time value
8
8
STS
STS
Status register
0x0
32
read-write
n
0x0
0x0
CTSF
CTS flag
9
1
read-write
FEF
Framing error
1
1
read-only
IDLEF
IDLE line detected
4
1
read-only
LBDF
LIN break detection flag
8
1
read-write
NEF
Noise error flag
2
1
read-only
OVREF
Overrun error
3
1
read-only
PEF
Parity error
0
1
read-only
RXBNEF
Read data register not empty
5
1
read-write
TXBEF
Transmit data register empty
7
1
read-only
TXCF
Transmission complete
6
1
read-write
USART3
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART3
USART3 global interrupt
39
BR
BR
Baud rate register
0x8
32
read-write
n
0x0
0x0
FRACTION
fraction of USARTDIV
0
4
MANTISSA
mantissa of USARTDIV
4
12
CTRL1
CTRL1
Control register 1
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable
4
1
PCEN
Parity control enable
10
1
PEIE
PE interrupt enable
8
1
PMSEL
Parity selection
9
1
RXBNEIE
RXNE interrupt enable
5
1
RXEN
Receiver enable
2
1
RXWUP
Receiver wakeup
1
1
TXBEIE
TXE interrupt enable
7
1
TXBK
Send break
0
1
TXCIE
Transmission complete interrupt enable
6
1
TXEN
Transmitter enable
3
1
UEN
USART enable
13
1
WLS
Word length
12
1
WUPM
Wakeup method
11
1
CTRL2
CTRL2
Control register 2
0x10
32
read-write
n
0x0
0x0
ADDR
Address of the USART node
0
4
CKPEN
Clock enable
11
1
CLKPHA
Clock phase
9
1
CLKPOL
Clock polarity
10
1
LBCEN
Last bit clock pulse
8
1
LBDIE
LIN break detection interrupt enable
6
1
LBDL
lin break detection length
5
1
LINEN
LIN mode enable
14
1
STOPB
STOP bits
12
2
CTRL3
CTRL3
Control register 3
0x14
32
read-write
n
0x0
0x0
CTSEN
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
ERRIE
Error interrupt enable
0
1
HDEN
Half-duplex selection
3
1
IRDAEN
IrDA mode enable
1
1
IRDALP
IrDA low-power
2
1
NACKEN
Smartcard NACK enable
4
1
RTSEN
RTS enable
8
1
RXDMAEN
DMA enable receiver
6
1
SCEN
Smartcard mode enable
5
1
TXDMAEN
DMA enable transmitter
7
1
DATA
DATA
TX Buffer Data Register
0x4
32
read-write
n
0x0
0x0
DATA
Data value
0
9
GTDIV
GTDIV
Guard time and divider number register
0x18
32
read-write
n
0x0
0x0
DIV
Prescaler value
0
8
GT
Guard time value
8
8
STS
STS
Status register
0x0
32
read-write
n
0x0
0x0
CTSF
CTS flag
9
1
read-write
FEF
Framing error
1
1
read-only
IDLEF
IDLE line detected
4
1
read-only
LBDF
LIN break detection flag
8
1
read-write
NEF
Noise error flag
2
1
read-only
OVREF
Overrun error
3
1
read-only
PEF
Parity error
0
1
read-only
RXBNEF
Read data register not empty
5
1
read-write
TXBEF
Transmit data register empty
7
1
read-only
TXCF
Transmission complete
6
1
read-write
WWDT
Window watchdog
WWDT
0x0
0x0
0x400
registers
n
WWDT
Window Watchdog interrupt
0
CFG
CFG
Configuration register (WWDT_CFR)
0x4
32
read-write
n
0x0
0x0
EWIEN
Early Wakeup Interrupt
9
1
WDDATA
7-bit window value
0
7
WDTTB
Timer Base
7
2
CTRL
CTRL
Control register (WWDT_CR)
0x0
32
read-write
n
0x0
0x0
CNT
7-bit counter (MSB to LSB)
0
7
WWDTEN
Activation bit
7
1
STS
STS
Status register (WWDT_SR)
0x8
32
read-write
n
0x0
0x0
EWIF
Early Wakeup Interrupt
0
1