AutoChips
AC780x
2024.05.02
AC780x Microcontroller
CM0PLUS
r0p1
little
2
false
8
32
ACMP0
Analog comparator
ACMP
0x0
0x0
0x34
registers
n
ACMP0
ACMP0 interrupt
4
CR0
ACMP Configuration Register 0
0x0
32
read-write
n
0x0
0x0
EN
Analog Comparator Enable
7
1
read-write
0
The ACMP is disabled.
#0
1
The ACMP is enabled.
#1
IE
ACMP Interrupt Enable
4
1
read-write
0
Disable the ACMP Interrupt.
#0
1
Enable the ACMP Interrupt.
#1
MOD
ACMP sensitivity modes of the interrupt trigger
0
2
read-write
00
ACMP interrupt on output falling edge.
#00
01
ACMP interrupt on output rising edge.
#01
10
ACMP interrupt on output falling edge.
#10
11
ACMP interrupt on output falling or rising edge.
#11
OPE
ACMP hall output Enable
2
1
read-write
0
ACMP hall output Disabled.
#0
1
ACMP hall output enabled.
#1
OUTEN
ACMP Output Enable
3
1
read-write
0
Disable ACMP OUTPUT.
#0
1
Enable ACMP OUTPUT.
#1
CR1
ACMP Configuration Register 1
0x4
32
read-write
n
0x0
0x0
NSEL
ACMP Negative Input Select
0
4
read-write
0000
External input 0
#0000
0001
External input 1
#0001
0010
External input 2
#0010
0011
External input 3
#0011
0100
External input 4
#0100
0101
External input 5
#0101
0110
External input 6
#0110
0111
DAC output
#0111
PSEL
ACMP Positive Input Select
4
4
read-write
0000
External input 0
#0000
0001
External input 1
#0001
0010
External input 2
#0010
0011
External input 3
#0011
0100
External input 4
#0100
0101
External input 5
#0101
0110
External input 6
#0110
0111
DAC output
#0111
CR2
ACMP configuration register 2
0x8
32
read-write
n
0x0
0x0
DACEN
DAC Enable
7
1
read-write
0
The DAC is disabled
#0
1
The DAC is enabled
#1
DACVAL
DAC Output Value
0
6
read-write
CR3
ACMP configuration register 3
0xC
32
read-write
n
0x0
0x0
NSPLEN
ACMP negative input polling mode enable
3
1
read-write
0
ACMP negative input polling mode disabled
#0
1
ACMP negative input polling mode enabled
#1
PSPLEN
ACMP positive input polling mode enable
7
1
read-write
0
ACMP positive input polling mode disabled
#0
1
ACMP positive input polling mode enabled
#1
CR4
ACMP configuration register 4
0x10
32
read-write
n
0x0
0x0
PLSEQ
ACMP polling channel sequence set
0
8
read-write
DACSR
ACMP DAC reference select register
0x2C
32
read-write
n
0x0
0x0
DACREF
ACMP DAC reference select
0
1
read-write
0
DAC selects bandgap as reference
#0
1
DAC selects Vdd as reference
#1
DR
ACMP data output register 0
0x14
32
read-only
n
0x0
0x0
O
ACMP normal mode output
8
1
O0
ACMP polling mode channel 0 output
0
1
O1
ACMP polling mode channel 1 output
1
1
O2
ACMP polling mode channel 2 output
2
1
O3
ACMP polling mode channel 3 output
3
1
O4
ACMP polling mode channel 4 output
4
1
O5
ACMP polling mode channel 5 output
5
1
O6
ACMP polling mode channel 6 output
6
1
O7
ACMP polling mode channel 7 output
7
1
FD
ACMP polling frequency divider register
0x1C
32
read-write
n
0x0
0x0
PLFD
ACMP polling mode frequency divider
0
2
read-write
00
source_clk/256
#00
01
source_clk/100
#01
10
source_clk/70
#10
11
source_clk/50
#11
OPA
ACMP hall output A set register
0x20
32
read-write
n
0x0
0x0
OPASEL
ACMP Hall output A set
0
3
read-write
000
polling channel 0
#000
001
polling channel 1
#001
010
polling channel 2
#010
011
polling channel 3
#011
100
polling channel 4
#100
101
polling channel 5
#101
110
polling channel 6
#110
111
polling channel 7
#111
OPB
ACMP hall output B set register
0x24
32
read-write
n
0x0
0x0
OPBSEL
ACMP Hall output B set
0
3
read-write
000
polling channel 0
#000
001
polling channel 1
#001
010
polling channel 2
#010
011
polling channel 3
#011
100
polling channel 4
#100
101
polling channel 5
#101
110
polling channel 6
#110
111
polling channel 7
#111
OPC
ACMP hall output C set register
0x28
32
read-write
n
0x0
0x0
OPCSEL
ACMP Hall output C set
0
3
read-write
000
polling channel 0
#000
001
polling channel 1
#001
010
polling channel 2
#010
011
polling channel 3
#011
100
polling channel 4
#100
101
polling channel 5
#101
110
polling channel 6
#110
111
polling channel 7
#111
SR
ACMP status register 0
0x18
32
read-write
n
0x0
0x0
F
ACMP normal mode interrupt flag
8
1
read-write
F0
ACMP polling mode channel 0 interrupt flag
0
1
read-write
F1
ACMP polling mode channel 1 interrupt flag
1
1
read-write
F2
ACMP polling mode channel 2 interrupt flag
2
1
read-write
F3
ACMP polling mode channel 3 interrupt flag
3
1
read-write
F4
ACMP polling mode channel 4 interrupt flag
4
1
read-write
F5
ACMP polling mode channel 5 interrupt flag
5
1
read-write
F6
ACMP polling mode channel 6 interrupt flag
6
1
read-write
F7
ACMP polling mode channel 7 interrupt flag
7
1
read-write
WPF
ACMP low power mode wakeup interrupt flag
9
1
read-write
ACMP_ANACFG
ACMP Analog Config
ACMP
0x0
0x0
0x4
registers
n
CFG0
ACMP analog config register 0
0x0
32
read-write
n
0x0
0x0
HYST
Hysteresis voltage
23
1
read-write
0
20mV
#0
1
40mV
#1
LPF
Low pass filter
21
2
read-write
00
200KHz
#00
01
500KHz
#01
10
750KHz
#10
11
1MHz
#11
ADC0
Analog to Digital Converter
ADC0
0x0
0x0
0x50
registers
n
ADC0
ADC0 interrupt
25
AMOHR
AMO High threshold and offset register
0x24
32
read-write
n
0x0
0x0
AMOHO
High offset value
16
12
read-write
AMOHT
AMO High threshold value
0
12
read-write
AMOLR
AMO Low threshold and offset register
0x28
32
read-write
n
0x0
0x0
AMOLO
Low offset value
16
12
read-write
AMOLT
AMO Low threshold value
0
12
read-write
CTRL0
ADC Control Register 0
0x4
32
read-write
n
0x0
0x0
ALIGN
Data Alignment
22
1
read-write
0
Right Alignment
#0
1
Left Alignment
#1
AMOCH
Analog monitor detecting channel
0
5
read-write
AMOEN
Regular Group Analog Monitor Detect function Enable
7
1
read-write
AMOIE
AMO interrupt Enable
18
1
read-write
0
AMO interrupt Disabled
#0
1
AMO interrupt Enabled, An interrupt is generated when the AMO bit is set
#1
AMOMODE
Analog monitor type
23
1
read-write
0
Level mode
#0
1
Edge mode
#1
AMOSGL
Analog monitor detecting channel
5
1
read-write
0
AMO used in All channels
#0
1
AMO function used in single channel defined in AMOCH register
#1
CONT
Continuous conversion
14
1
read-write
0
Single conversion mode
#0
1
Continuous conversion mode
#1
DISCEN
Discontinous mode on regular channels
13
1
read-write
0
Regular group Discontinous mode disabled
#0
1
Regular group Discontinous mode enabled
#1
DISCNUM
Discontinuous conversion length of channel
8
3
read-write
DMAEN
DMA Function Enable
19
1
read-write
0
DMA function Disabled
#0
1
DMA function Enabled
#1
EOCIE
EOC interrupt Enable
16
1
read-write
0
EOC interrupt Disabled
#0
1
EOC interrupt Enabled, An interrupt is generated when the EOC bit is set
#1
EXTTRIG
Regular group trig source select
20
1
read-write
0
Internal trigger source(software trig)
#0
1
External trigger source
#1
IAMOEN
Injection Group Analog Monitor Detect function Enable
6
1
read-write
IAUTO
Injection Group Automatic conversion
11
1
read-write
0
Injection group automatic conversion disabled
#0
1
Injection group automatic conversion enabled
#1
IDISCEN
Discontinous mode on injected channels
12
1
read-write
0
Injection group Discontinous mode disabled
#0
1
Injection group Discontinous mode enabled
#1
IEOCIE
IEOC interrupt Enable
17
1
read-write
0
IEOC interrupt Disabled
#0
1
IEOC interrupt Enabled, An interrupt is generated when the IEOC bit is set
#1
IEXTTRIG
Inject group trig source select
21
1
read-write
0
Internal trigger source(software trig)
#0
1
External trigger source
#1
INTERVAL
Interval mode
24
1
read-write
0
Normal mode
#0
1
Interval mode
#1
ISWSTART
Software trigger for Inject channels
30
1
read-write
SCAN
Scan Mode
15
1
read-write
0
Scan mode disabled
#0
1
Scan mode enabled
#1
SWSTART
Software trigger for regular channels
31
1
read-write
CTRL1
ADC Control Register 1
0x8
32
read-write
n
0x0
0x0
ADON
ADC converter ON/OFF
0
1
read-write
0
Disable ADC conversion
#0
1
Enable ADC and to start conversion
#1
CALEN
Calibration
1
1
read-write
0
Disable Calibration
#0
1
Enable Calibration
#1
PSC
Bus Clock prescaler
12
4
read-write
IDR0
ADC Injection Group data Register(n)
0x3C
32
read-only
n
0x0
0x0
IDR
Injection group data Value
0
12
read-only
IDR1
ADC Injection Group data Register(n)
0x40
32
read-only
n
0x0
0x0
IDR
Injection group data Value
0
12
read-only
IDR2
ADC Injection Group data Register(n)
0x44
32
read-only
n
0x0
0x0
IDR
Injection group data Value
0
12
read-only
IDR3
ADC Injection Group data Register(n)
0x48
32
read-only
n
0x0
0x0
IDR
Injection group data Value
0
12
read-only
IOFR0
ADC Injection Group Offset Register(n)
0x14
32
read-write
n
0x0
0x0
IOFR
Injection group offset Value
0
12
read-write
IOFR1
ADC Injection Group Offset Register(n)
0x18
32
read-write
n
0x0
0x0
IOFR
Injection group offset Value
0
12
read-write
IOFR2
ADC Injection Group Offset Register(n)
0x1C
32
read-write
n
0x0
0x0
IOFR
Injection group offset Value
0
12
read-write
IOFR3
ADC Injection Group Offset Register(n)
0x20
32
read-write
n
0x0
0x0
IOFR
Injection group offset Value
0
12
read-write
ISQR
ADC injection group sequence configure register
0x38
32
read-write
n
0x0
0x0
ISQ0
channel selection for injection group 0
0
5
read-write
ISQ1
channel selection for injection group 1
5
5
read-write
ISQ2
channel selection for injection group 2
10
5
read-write
ISQ3
channel selection for injection group 3
15
5
read-write
ISQL
length of injection group
20
2
read-write
RDR
ADC Regular Group data Register
0x4C
32
read-only
n
0x0
0x0
RDR
Regular group data Value
0
12
read-only
RSQR0
ADC regular group sequence configure register 0
0x2C
32
read-write
n
0x0
0x0
RSQ12
channel selection for regular group 12
0
5
read-write
RSQ13
channel selection for regular group 13
5
5
read-write
RSQL
Length of regular group
20
4
read-write
RSQR1
ADC regular group sequence configure register 1
0x30
32
read-write
n
0x0
0x0
RSQ10
channel selection for regular group 10
20
5
read-write
RSQ11
channel selection for regular group 11
25
5
read-write
RSQ6
channel selection for regular group 6
0
5
read-write
RSQ7
channel selection for regular group 7
5
5
read-write
RSQ8
channel selection for regular group 8
10
5
read-write
RSQ9
channel selection for regular group 9
15
5
read-write
RSQR2
ADC regular group sequence configure register 2
0x34
32
read-write
n
0x0
0x0
RSQ0
channel selection for regular group 0
0
5
read-write
RSQ1
channel selection for regular group 1
5
5
read-write
RSQ2
channel selection for regular group 2
10
5
read-write
RSQ3
channel selection for regular group 3
15
5
read-write
RSQ4
channel selection for regular group 4
20
5
read-write
RSQ5
channel selection for regular group 5
25
5
read-write
SPT0
ADC Sample time setting register 0
0xC
32
read-write
n
0x0
0x0
SPT10
Sample time for Channel 10
0
3
read-write
000
9 ADCCLK
#000
001
7 ADCCLK
#001
010
15 ADCCLK
#010
011
33 ADCCLK
#011
100
64 ADCCLK
#100
101
140 ADCCLK
#101
110
215 ADCCLK
#110
111
5 ADCCLK
#111
SPT11
Sample time for Channel 11
3
3
read-write
000
9 ADCCLK
#000
001
7 ADCCLK
#001
010
15 ADCCLK
#010
011
33 ADCCLK
#011
100
64 ADCCLK
#100
101
140 ADCCLK
#101
110
215 ADCCLK
#110
111
5 ADCCLK
#111
SPT12
Sample time for Channel 12
6
3
read-write
000
9 ADCCLK
#000
001
7 ADCCLK
#001
010
15 ADCCLK
#010
011
33 ADCCLK
#011
100
64 ADCCLK
#100
101
140 ADCCLK
#101
110
215 ADCCLK
#110
111
5 ADCCLK
#111
SPT13
Sample time for Channel 13
9
3
read-write
000
9 ADCCLK
#000
001
7 ADCCLK
#001
010
15 ADCCLK
#010
011
33 ADCCLK
#011
100
64 ADCCLK
#100
101
140 ADCCLK
#101
110
215 ADCCLK
#110
111
5 ADCCLK
#111
SPT1
ADC Sample time setting register 1
0x10
32
read-write
n
0x0
0x0
SPT0
Sample time for Channel 0
0
3
read-write
000
9 ADCCLK
#000
001
7 ADCCLK
#001
010
15 ADCCLK
#010
011
33 ADCCLK
#011
100
64 ADCCLK
#100
101
140 ADCCLK
#101
110
215 ADCCLK
#110
111
5 ADCCLK
#111
SPT1
Sample time for Channel 1
3
3
read-write
000
9 ADCCLK
#000
001
7 ADCCLK
#001
010
15 ADCCLK
#010
011
33 ADCCLK
#011
100
64 ADCCLK
#100
101
140 ADCCLK
#101
110
215 ADCCLK
#110
111
5 ADCCLK
#111
SPT2
Sample time for Channel 2
6
3
read-write
000
9 ADCCLK
#000
001
7 ADCCLK
#001
010
15 ADCCLK
#010
011
33 ADCCLK
#011
100
64 ADCCLK
#100
101
140 ADCCLK
#101
110
215 ADCCLK
#110
111
5 ADCCLK
#111
SPT3
Sample time for Channel 3
9
3
read-write
000
9 ADCCLK
#000
001
7 ADCCLK
#001
010
15 ADCCLK
#010
011
33 ADCCLK
#011
100
64 ADCCLK
#100
101
140 ADCCLK
#101
110
215 ADCCLK
#110
111
5 ADCCLK
#111
SPT4
Sample time for Channel 4
12
3
read-write
000
9 ADCCLK
#000
001
7 ADCCLK
#001
010
15 ADCCLK
#010
011
33 ADCCLK
#011
100
64 ADCCLK
#100
101
140 ADCCLK
#101
110
215 ADCCLK
#110
111
5 ADCCLK
#111
SPT5
Sample time for Channel 5
15
3
read-write
000
9 ADCCLK
#000
001
7 ADCCLK
#001
010
15 ADCCLK
#010
011
33 ADCCLK
#011
100
64 ADCCLK
#100
101
140 ADCCLK
#101
110
215 ADCCLK
#110
111
5 ADCCLK
#111
SPT6
Sample time for Channel 6
18
3
read-write
000
9 ADCCLK
#000
001
7 ADCCLK
#001
010
15 ADCCLK
#010
011
33 ADCCLK
#011
100
64 ADCCLK
#100
101
140 ADCCLK
#101
110
215 ADCCLK
#110
111
5 ADCCLK
#111
SPT7
Sample time for Channel 7
21
3
read-write
000
9 ADCCLK
#000
001
7 ADCCLK
#001
010
15 ADCCLK
#010
011
33 ADCCLK
#011
100
64 ADCCLK
#100
101
140 ADCCLK
#101
110
215 ADCCLK
#110
111
5 ADCCLK
#111
SPT8
Sample time for Channel 8
24
3
read-write
000
9 ADCCLK
#000
001
7 ADCCLK
#001
010
15 ADCCLK
#010
011
33 ADCCLK
#011
100
64 ADCCLK
#100
101
140 ADCCLK
#101
110
215 ADCCLK
#110
111
5 ADCCLK
#111
SPT9
Sample time for Channel 9
27
3
read-write
000
9 ADCCLK
#000
001
7 ADCCLK
#001
010
15 ADCCLK
#010
011
33 ADCCLK
#011
100
64 ADCCLK
#100
101
140 ADCCLK
#101
110
215 ADCCLK
#110
111
5 ADCCLK
#111
STR
ADC status Register
0x0
32
read-write
n
0x0
0x0
AAMO
Analog monitor Abnormal event occurs(Edge mode)
6
1
read-write
0
No analog monitor event
#0
1
Analog monitor abnormal event occurs
#1
AMO
Analog monitor event occurs(Level mode)
0
1
read-write
0
No analog monitor event
#0
1
Analog monitor event occurs
#1
EOC
Regular group conversion completed flag
1
1
read-write
0
Regular group conversion not completed
#0
1
Regular group conversion completed
#1
IDLE
ADC idle status indicate
4
1
read-only
0
Busy status
#0
1
Idle status
#1
IEOC
Injection group conversion completed flag
2
1
read-write
0
Injection group conversion not completed
#0
1
Injection group conversion completed
#1
NAMO
Analog monitor normal event occurs(Edge mode)
5
1
read-write
0
No analog monitor event
#0
1
Analog monitor normal event occurs
#1
CAN0
Controller Area Network
CAN0
0x0
0x0
0xC0
registers
n
CAN0
CAN0 interrupt
24
ACF
Acceptance Code Register
0xB8
32
read-write
n
0x0
0x0
ACODE
Acceptance Code
0
29
read-write
AIDE
Acceptance Mask IDE Bit value
29
1
read-write
0
Acceptance filter accepts only extended frames
#0
1
Acceptance filter accepts only extended frames
#1
AIDEE
Acceptance Mask IDE bit check enable
30
1
read-write
0
Acceptance filter accepts both standard or extended frames
#0
1
Acceptance filter accepts either standard or extended as defined by AIDE
#1
ACFCTRL
Acceptance Filter Control Register
0xB4
32
read-write
n
0x0
0x0
ACFADR
Acceptance filter address
0
4
read-write
ACFEN
Acceptance Filter Enable
16
16
read-write
SELMASK
Select Acceptance MASK
5
1
read-write
0
Registers ACF_x point to acceptance code
#0
1
Registers ACF_x point to acceptance mask
#1
TIMEEN
TIME-stamping Enable
8
1
read-write
0
Disabled
#0
1
Enabled
#1
TIMEPOS
TIME-stamping Position
9
1
read-write
0
SOF
#0
1
EOF
#1
CTRL0
Config state and transmit/receive control register 0
0xA0
32
read-write
n
0x0
0x0
BUSOFF
BUS off status
0
1
read-write
0
The controller status is bus on
#0
1
The controller status is bus off
#1
FDISO
FD ISO mode
23
1
read-write
0
Bosch CAN FD (non-ISO) mode
#0
1
ISO CAN FD mode (ISO 11898-1:2015)
#1
LBME
Loop back mode, external
6
1
read-write
0
Disabled
#0
1
Enabled
#1
LBMI
Loop back mode internal
5
1
read-write
0
Disabled
#0
1
Enabled
#1
LOM
Listen Only mode
14
1
read-write
0
Disabled
#0
1
Enabled
#1
RACTIVE
Reception Active
2
1
read-only
0
No receive activity
#0
1
The controller is currently receiving a frame
#1
RBALL
Receive Buffer stores ALL data frames
27
1
read-write
0
Normal operation
#0
1
RB stores correct data frames as well as data frames with error
#1
RESET
reset request bit
7
1
read-write
0
No local reset of CAN-CTRL
#0
1
The host controller performs a local reset of CAN-CTRL
#1
ROM
Receive Buffer Overflow Mode
30
1
read-write
0
The oldest message will be overwritten
#0
1
The new message will not be stored
#1
ROV
Receive Buffer Overflow
29
1
read-only
0
No Overflow
#0
1
Overflow. At least one message is lost
#1
RREL
Receive Buffer Release
28
1
read-write
0
No release
#0
1
Release: The host has read the RB
#1
RSTAT
Receive Buffer status bits
24
2
read-only
00
empty
#00
01
less than empty and more than almost full (AFWL)
#01
11
full
#01
10
almost full (programmable threshold by AFWL) but not full and no overflow
#10
SACK
Self-Acknowledge when LBME = 1
31
1
read-write
0
No self-ACK
#0
1
Self-ACK when LBME=1
#1
STBY
Transceiver Standby mode
13
1
read-write
0
Disabled
#0
1
Enabled
#1
TACTIVE
Transmission Active
1
1
read-only
0
No transmit activity
#0
1
The controller is currently transmitting a frame
#1
TBSEL
Transmit Buffer Select
15
1
read-write
0
PTB (high-priority buffer)
#0
1
STB
#1
TPA
Transmit Primary Abort
11
1
read-write
0
no abort
#0
1
Aborts a transmission from PTB which has been requested by TPE=1 but not started yet
#1
TPE
Transmit Primary Enable
12
1
read-write
0
No transmission for the PTB
#0
1
Transmission enable for the message in the high-priority PTB
#1
TPSS
Transmission Primary single shot mode for PTB
4
1
read-write
0
Disabled
#0
1
Enabled
#1
TSA
Transmit Secondary Abort
8
1
read-write
0
No abort
#0
1
Aborts a transmission from STB which has been requested but not started yet
#1
TSALL
Transmit Secondary All frames
9
1
read-write
0
No transmission for the STB
#0
1
Transmission enable of all messages in the STB
#1
TSMODE
Transmit buffer Secondary operation Mode
21
1
read-write
0
FIFO mode
#0
1
priority decision mode
#1
TSNEXT
Transmit Buffer Secondary next
22
1
read-write
0
No action
#0
1
STB slot filled, select next slot
#1
TSONE
Transmit Secondary one Frame
10
1
read-write
0
No transmission for the STB
#0
1
Transmission enable of one in the STB
#1
TSSS
Transmission Secondary single shot mode for STB
3
1
read-write
0
Disabled
#0
1
Enabled
#1
TSSTAT
Transmit Secondary status bits
16
2
read-only
00
STB is empty
#00
01
STB is less than or equal to half full
#01
11
STB is full
#01
10
STB is more than half full
#10
CTRL1
CAN interrupt enable/disable and flag control register 1
0xA4
32
read-write
n
0x0
0x0
AFWL
Receive Buffer Almost Full Warning Limit
28
4
read-write
AIF
Abort Interrupt Flag
8
1
read-write
0
No abort has been executed
#0
1
After setting TPA or TSA the appropriated message(s) have been aborted
#1
ALIE
Arbitration Lost Interrupt Enable
19
1
read-write
ALIF
Arbitration Lost Interrupt Flag
18
1
read-write
BEIE
Bus Error Interrupt Enable
17
1
read-write
BEIF
Bus Error Interrupt flag
16
1
read-write
EIE
Error Interrupt Enable
1
1
read-write
0
Disabled
#0
1
Enabled
#1
EIF
Error Interrupt Flag
9
1
read-write
0
There has been no change
#0
1
The border of the error warning limit has been crossed in either direction,or the BUSOFF bit has been changed in either direction
#1
EPASS
Error Passive Mode Active enable bit
22
1
read-only
0
Not active (node is error active)
#0
1
Active (node is error active)
#1
EPIE
Error Passive Interrupt Enable
21
1
read-write
EPIF
Error Passive Interrupt Flag
20
1
read-write
EWARN
Error Warning Limit Reached
23
1
read-only
0
The values in both counters are less than EWL
#0
1
One of the error counters RECNT or TECNT is equal or bigger than EWL
#1
EWL
Programmable Error Warnig Limit
24
4
read-write
RAFIE
RB Almost Full Interrupt Enable
4
1
read-write
0
Disabled
#0
1
Enabled
#1
RAFIF
RB Almost Full Interrupt flag
12
1
read-write
0
number of filled RB slots more than or equal AFWL_i
#0
1
number of filled RB slots less than AFWL_i
#1
RFIE
RB Full Interrupt Enable
5
1
read-write
0
Disabled
#0
1
Enabled
#1
RFIF
RB Full Interrupt flag
13
1
read-write
0
The RB FIFO is not ful
#0
1
All RBs are full. If no RB will be released until the next valid message is received,the oldest message will be lost
#1
RIE
Receive Interrupt enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
RIF
Receive Interrupt flag
15
1
read-write
0
No frame has been received
#0
1
Data or a remote frame has been received and is available in the receive buffer
#1
ROIE
RB Overflow Interrupt enable
6
1
read-write
0
Disabled
#0
1
Enabled
#1
ROIF
RB Overflow Interrupt flag
14
1
read-write
0
No RB overwritten
#0
1
At least one received message has been overwritten in the RB
#1
TPIE
Transmit Primary Interrupt Enable
3
1
read-write
0
Disabled
#0
1
Enabled
#1
TPIF
Transmission Primary Interrupt Flag
11
1
read-write
0
No transmission of the PTB has been completed
#0
1
The requested transmission of the PTB has been successfully completed
#1
TSFF
Transmit Secondary Buffer full flag
0
1
read-write
0
The STB is not filled with the maximal number of messages
#0
1
The STB is filled with the maximal number of messages
#1
TSIE
Transmit Secondary Interrupt Enable
2
1
read-write
0
Disabled
#0
1
Enabled
#1
TSIF
Transmission Secondary Interrupt Flag
10
1
read-write
0
No transmission of the STB has been completed successfully
#0
1
The requested transmission of the STB has been successfully completed
#1
ERRINFO
CAN error type and transmit/receive error conunter register
0xB0
32
read-write
n
0x0
0x0
ALC
Arbitration Lost Capture
0
5
read-only
KOER
Kind of Error
5
3
read-only
0000
No error
#0000
001
Bit error
#001
010
Form error
#010
011
Stuff error
#011
100
Acknowledge error
#100
101
CRC error
#101
110
Other error
#1100
111
Not used
#111
RECNT
Receive Error Count
16
8
read-only
SSPOFF
Second Sample Point Offset
8
7
read-write
TDCEN
Transmitter Delay Compensation Enable
15
1
read-write
TECNT
Transmit Error Count
24
8
read-only
FBITRATE
FAST CAN(CAN_FD) baudrate configuration register
0xAC
32
read-write
n
0x0
0x0
f_PRESC
Prescaler
24
8
read-write
f_SEG_1
Bit Timing Segment 1
0
8
read-write
f_SEG_2
Bit Timing Segment 2
8
7
read-write
f_SJW
Synchronization Jump Width
16
7
read-write
SBITRATE
Normat CAN baudrate configuration register
0xA8
32
read-write
n
0x0
0x0
S_PRESC
Prescaler
24
8
read-write
S_SEG_1
Bit Timing Segment 1
0
8
read-write
S_SEG_2
Bit Timing Segment 2
8
7
read-write
S_SJW
Synchronization Jump Width
16
7
read-write
VERSION
Version Information Register 0
0xBC
32
read-write
n
0x0
0x0
VERSION
Version of CAN-CTRL
0
16
read-only
CKGEN
Clock Generator
CKGEN
0x0
0x0
0x18
registers
n
CTRL
CKGEN Control Register
0x0
32
read-write
n
0x0
0x0
APBCLK_DIV
APB Clcok Divider
8
2
read-write
00
APB Clock Divided By 1
#00
01
APB Clock Divided By 2
#01
10
APB Clock Divided By 3
#10
11
APB Clock Divided By 4
#11
CAN0_CLK_SEL
CAN0 Clock Source Select
26
1
read-write
0
External XOSC Clock
#0
1
AHB Clock Divided
#1
CAN0_TIMCLK_DIV
CAN0 Clock Divider
21
2
read-write
00
CAN0 Clock Divided By 8
#00
01
CAN0 Clock Divided By 16
#01
10
CAN0 Clock Divided By 24
#10
11
CAN0 Clock Divided By 48
#11
PLL_REF_SEL
PLL Reference Clock Select
20
1
read-write
0
Internal RC
#0
1
External XOSC
#1
SYSCLK_DIV
System Clcok Divider
4
2
read-write
00
System Clock Divided By 1
#00
01
System Clock Divided By 2
#01
10
System Clock Divided By 3
#10
11
System Clock Divided By 4
#11
SYSCLK_SEL
system clock select
0
2
read-write
00
Internal RC
#00
01
PLL Output
#1
10
External XOSC
#10
XOSC_MON_EN
XOSC Monitor Function Enable
16
1
read-write
0
Monitor Function Disable
#0
1
Monitor Function Enable
#1
PERI_CLK_EN_0
Periph Clock Enable Control 0
0x4
32
read-write
n
0x0
0x0
CAN0_EN
CAN0 Clock Enable
28
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
CRC_EN
CRC Clock Enable
26
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
DMA0_EN
DMA0 Clock Enable
21
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
GPIO_EN
GPIO Clock Enable
23
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
I2C0_EN
I2C0 Clock Enable
8
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
I2C1_EN
I2C1 Clock Enable
9
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
PWDT0_EN
PWDT0 Clock Enable
10
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
PWM0_EN
PWM0 Clock Enable
11
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
PWM1_EN
PWM1 Clock Enable
12
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
RTC_EN
RTC Clock Enable
20
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
SPI0_EN
SPI0 Clock Enable
6
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
SPI1_EN
SPI1 Clock Enable
7
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
TIMER_EN
TIMER Clock Enable
19
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
UART0_EN
UART0 Clock Enable
0
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
UART1_EN
UART1 Clock Enable
1
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
UART2_EN
UART2 Clock Enable
2
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
WDG_EN
WDG Clock Enable
25
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
PERI_CLK_EN_1
Periph Clock Enable Control 1
0x8
32
read-write
n
0x0
0x0
ACMP0_EN
ACMP0 Clock Enable
3
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
ADC0_EN
ADC0 Clock Enable
2
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
CTU_EN
CTU APB Clock Enable
1
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
PWDT1_EN
PWDT1 Clock Enable
5
1
read-write
0
Clock Disable
#0
1
Clock Enable
#1
PERI_SFT_RST0
Periph Software Reset Control 0
0x18
32
read-write
n
0x0
0x0
SRST_CAN0
CAN0 Software Reset
28
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
SRST_CRC
CRC Software Reset
26
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
SRST_DMA0
DMA0 Software Reset
21
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
SRST_GPIO
GPIO Software Reset
23
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
SRST_I2C0
I2C0 Software Reset
8
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
SRST_I2C1
I2C1 Software Reset
9
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
SRST_PWDT0
PWDT0 Software Reset
10
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
SRST_PWM0
PWM0 Software Reset
11
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
SRST_PWM1
PWM1 Software Reset
12
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
SRST_RTC
RTC Software Reset
20
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
SRST_SPI0
SPI0 Software Reset
6
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
SRST_SPI1
SPI1 Software Reset
7
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
SRST_TIMER
TIMER Software Reset
19
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
SRST_UART0
UART0 Software Reset
0
1
read-write
0
Reset Active
#0
1
Reset Inactive
#1
SRST_UART1
UART1 Software Reset
1
1
read-write
0
Reset Active
#0
1
Reset Inactive
#1
SRST_UART2
UART2 Software Reset
2
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
SRST_WDG
WDG Software Reset
25
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
PERI_SFT_RST1
Periph Software Reset Control 1
0x1C
32
read-write
n
0x0
0x0
SRST_ACMP0
ACMP0 Software Reset
3
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
SRST_ADC0
ADC0 Software Reset
2
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
SRST_ANA_REG
Analog Register Software Reset
4
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
SRST_CTU
CTU Software Reset
1
1
read-write
0
Reset Active
#0
1
Reset Inactive
#1
SRST_PWDT1
PWDT1 Software Reset
5
1
read-write
0
Reset Actsive
#0
1
Reset Inactive
#1
RESET_CTRL
MCU Reset Control
0xC
32
read-write
n
0x0
0x0
CPU_LOCKUP_RST_EN
CPU Lockup Reset Enable
25
1
read-write
0
Disable
#0
1
Enable
#1
CPU_SYSRST_EN
CPU System Reset Enable
24
1
read-write
0
Disable
#0
1
Enable
#1
ECC2_RST_EN
ECC2 Error Reset Enable
23
1
read-write
0
Disable
#0
1
Enable
#1
EXT_RST_DEGLITCH_EN
EXT Reset Deglitch Enable
0
1
read-write
0
Deglitch Disable
#0
1
Deglitch Enable
#1
EXT_RST_DEGLITCH_VALUE
Deglitch Value Set
1
7
read-write
PLL_UNLOCK_RST_EN
PLL Unlock Reset Enable
22
1
read-write
0
Disable
#0
1
Enable
#1
XOSC_LOSS_RST_EN
XOSC Loss Reset Enable
26
1
read-write
0
Disable
#0
1
Enable
#1
RESET_STATUS
MCU Reset Status
0x10
32
read-write
n
0x0
0x0
CLR_RESET_STATUS
clear All Reset Status
16
1
read-write
0
reset update
#0
1
clear all reset status
#1
CPU_LOCKUP_RST_STATUS
CPU Lockup Reset Flag
7
1
read-only
0
Reset Not Happen
#0
1
Reset Happen
#1
CPU_SYSRESET_STATUS
CPU Sysreset Reset Flag
6
1
read-only
0
Reset Not Happen
#0
1
Reset Happen
#1
EXT_RESET_STATUS
EXT Reset Flag
2
1
read-only
0
Reset Not Happen
#0
1
Reset Happen
#1
LVD_RESET_STATUS
LVD Reset Flag
1
1
read-only
0
Reset Not Happen
#0
1
Reset Happen
#1
PLL_UNLOCK_RST_STATUS
PLL Unlock Reset Flag
8
1
read-only
0
Reset Not Happen
#0
1
Reset Happen
#1
POR_RESET_STATUS
POR Reset Flag
0
1
read-only
0
Reset Not Happen
#0
1
Reset Happen
#1
WDT_32K_RESET_STATUS
WDT 32K Reset Flag
5
1
read-only
0
Reset Not Happen
#0
1
Reset Happen
#1
WDT_RESET_STATUS
WDT Reset Flag
4
1
read-only
0
Reset Not Happen
#0
1
Reset Happen
#1
XOSC_LOSS_STATUS
XOSC Loss Flag
9
1
read-only
0
Reset Not Happen
#0
1
Reset Happen
#1
SYSPLL1_CFG0
MCU System PLL Config 0
0x8890
32
read-write
n
0x0
0x0
SYSPLL1_FBKDIV
Feedback-Divider
15
8
read-write
SYSPLL1_POSDIV
Post-divider Ratio
25
5
read-write
00000
NONE
#00000
00001
VCO/2
#00001
00010
VCO/4
#00010
00011
VCO/6
#00011
00100
VCO/8
#00100
00101
VCO/10
#00101
00110
VCO/12
#00110
00111
VCO/14
#00111
01000
VCO/16
#01000
01001
VCO/18
#01001
01010
VCO/20
#01010
01011
VCO/22
#01011
01100
VCO/24
#01100
01101
VCO/26
#01101
01110
VCO/28
#01110
01111
VCO/30
#01111
10000
VCO/32
#10000
10001
VCO/34
#10001
10010
VCO/36
#10010
10011
VCO/38
#10011
10100
VCO/40
#10100
10101
VCO/42
#10101
10110
VCO/44
#10110
10111
VCO/46
#10111
11000
VCO/48
#11000
11001
VCO/50
#11001
11010
VCO/52
#11010
11011
VCO/54
#11011
11100
VCO/56
#11100
11101
VCO/58
#11101
11110
VCO/60
#11110
11111
VCO/62
#11111
SYSPLL1_PREDIV
Pre-Divider
30
2
read-write
00
Fref=Fin/1
#00
01
Fref=Fin/2
#01
10
Fref=Fin/4
#10
CRC
CRC Cyclic redundancy check
CRC
0x0
0x0
0xC
registers
n
CTRL
Control Register
0x8
32
read-write
n
0x0
0x0
FXOR
Complement Read Of CRC Check Result
2
1
read-write
TCRC
16 or 32 CRC Type
0
1
read-write
TOTR
Type Of Transpose For Read Check Result
4
2
read-write
TOTW
Type Of Transpose For Write Check Data
6
2
read-write
WAS
Decide Load Data or Seed
1
1
read-write
DATA
DATA Register
0x0
32
read-write
n
0x0
0x0
DATA
Load Data or Seed
0
32
read-write
POLY
POLY Register
0x4
32
read-write
n
0x0
0x0
POLY
Load Polynomial
0
32
read-write
CTU
Connect Module Unit
CTU
0x0
0x0
0x10
registers
n
CONFIG0
CTU Configuration Register 0
0x0
32
read-write
n
0x0
0x0
ACIC
Analog Comparator to Input Capture Enable
11
1
read-write
0
ACMP0 Output is not connected to PWM1 Channel0
#0
1
ACMP0 Output is connected to PWM1 Channel0
#1
ADHWT0
ADC Hardware Trigger Source for regular group
20
3
read-write
000
RTC Overflow as ADC hardware Trigger
#000
001
PWM0 Init as ADC Hardware Trigger
#001
010
PWM0 Match Trigger with 8-bit programmable counter delay
#010
011
PWM1 Init as ADC Hardware Trigger
#011
100
PWM1 Match Trigger with 8-bit programmable counter delay
#100
101
Timer Channel0 overflow as ADC hardware Trigger
#101
110
Timer Channel1 overflow as ADC Hardware Trigger
#110
111
ACMP0 Out as ADC Hardware Trigger
#111
DELAY0
Regular Group Trigger Delay Counter
24
8
read-write
DLYACT0
Regular Group Trigger Delay Active
23
1
read-only
0
Delay0 is inactive
#0
1
Delay0 is active
#1
PSC
Clock Prescaler
16
3
read-write
000
Clock divided by 1
#000
001
Clock divided by 2
#001
010
Clock divided by 4
#010
011
Clock divided by 8
#011
100
Clock divided by 16
#100
101
Clock divided by 32
#101
110
Clock divided by 64
#110
111
Clock divided by 128
#111
PWMSYNC
PWM SW Synchronization Selection
14
1
read-write
0
No Synchronization triggered
#0
1
Generate PWM Synchronization to trigger PWM Modules
#1
RTCC
Real-Time Counter Capture
10
1
read-write
0
RTC Overflow is not connected to PWM1 Channel 1
#0
1
RTC overflow is connected to PWM1 Channel 1
#1
RXDCE
UART0_RX Capture Selection
12
1
read-write
0
UART0_RX input connect to UART0 Only
#0
1
UART0_RX input connected to PWM0 Channel1
#1
RXDFE
UART0 RxD filter Selection
9
1
read-write
00
RXD input signal is connected to UART0 modulate directly
#00
01
RXD input signal is filtered by ACMP0, then injected to UART0
#01
TXDME
UART0 TX Modulation Selection
15
1
read-write
0
UART0_TX is connected to PIN out directly
#0
1
UART0_TX is modulated by PWM0 Channel 0
#1
CONFIG1
CTU Configuration Register 1
0x4
32
read-write
n
0x0
0x0
ADHWT1
ADC Hardware Trigger Source for injection group
6
3
read-write
000
RTC Overflow as the ADC hardware trigger
#000
001
PWM0 Init as ADC Hardware Trigger
#001
010
PWM0 Match Trigger with 8-bit programmable counter delay
#010
011
PWM1 Init as ADC Hardware Trigger
#011
100
PWM1 Match Trigger with 8-bit programmable counter delay
#100
101
Timer Channel0 overflow as the ADC hardware trigger
#101
110
Timer Channel1 overflow as the ADC hardware trigger
#110
111
ACMP0 output as the ADC hardware trigger
#111
DELAY1
Injection Group Trigger Delay Counter
23
8
read-write
DLYACT1
Injection Group Trigger Delay Active
22
1
read-only
0
Delay1 is inactive
#0
1
Delay1 is active
#1
PWDT0IN3S
PWDT0 IN3 Select
9
2
read-write
00
UART0 RX is connected to PWDT0_IN3
#00
01
UART1 RX is connected to PWDT0_IN3
#01
10
UART2 RX is connected to PWDT0_IN3
#10
11
ACMP0_OUT is Connected to PWDT0_IN3
#11
PWDT1IN3S
PWDT1 IN3 Select
11
2
read-write
00
UART0 RX is connected to PWDT1_IN3
#00
01
UART1 RX is connected to PWDT1_IN3
#01
10
UART2 RX is connected to PWDT1_IN3
#10
11
ACMP0_OUT is Connected to PWDT1_IN3
#11
DMA0_CHANNEL0
DMA channel
DMA0_CHANNEL0
0x0
0x0
0x30
registers
n
DMA0_CHANNEL0
DMA0 channel 0 interrupt
13
CHAN_ENABLE
Channel Enable Register
0x24
32
read-write
n
0x0
0x0
CHAN_ENABLE
channel enable
0
1
read-write
CHAN_LENGTH
Channel Length Register
0x14
32
read-write
n
0x0
0x0
CHAN_LENGTH
DMA channel transfer length
0
16
read-write
CONFIG
DMA Config Register
0x10
32
read-write
n
0x0
0x0
CHAN_CIRCULAR
channel circular mode enable or disable
9
1
read-write
CHAN_DIR
channel read data direction select
10
1
read-write
READ_FROM_PERIPH
DMA read from peripheral
#0000
READ_FROM_MEM
DMA read from memory
#0001
CHAN_PRIORITY
channel priority select
1
2
read-write
LOW
DMA channel priority low
#0000
MEDIUM
DMA channel priority medium
#0001
HIGH
DMA channel priority high
#0010
VERY_HIGH
DMA channel priority very high
#0011
MEM2MEM
memory to memory transfer enable or disable
0
1
read-write
MEM_BYTE_MODE
memory word segmentation transfer number
11
2
read-write
MEM_INCREMENT
memory address increase or fix
7
1
read-write
MEM_SIZE
memory size select
3
2
read-write
8BIT
MEM SIZE 8BIT
#0000
16BIT
MEM SIZE 16BIT
#0001
32BIT
MEM SIZE 32BIT
#0010
PERIPH_INCREMENT
peripheral address increase or fix
8
1
read-write
PERIPH_SEL
peripheral select
16
4
read-write
UART0_TX
UART0_TX as DMA peripheral
#0000
UART0_RX
UART0_RX as DMA peripheral
#0001
UART1_TX
UART1_TX as DMA peripheral
#0010
UART1_RX
UART1_RX as DMA peripheral
#0011
UART2_TX
UART2_TX as DMA peripheral
#0100
UART2_RX
UART2_RX as DMA peripheral
#0101
SPI0_TX
SPI0_TX as DMA peripheral
#0110
SPI0_RX
SPI0_RX as DMA peripheral
#0111
SPI1_TX
SPI1_TX as DMA peripheral
#1000
SPI1_RX
SPI1_RX as DMA peripheral
#1001
I2C0_TX
I2C0_TX as DMA peripheral
#1010
I2C0_RX
I2C0_RX as DMA peripheral
#1011
I2C1_TX
I2C1_TX as DMA peripheral
#1100
I2C1_RX
I2C1_RX as DMA peripheral
#1101
ADC0
ADC0 as DMA peripheral
#1110
PERIPH_SIZE
peripheral size select
5
2
read-write
8BIT
PERIPH SIZE 8BIT
#0000
16BIT
PERIPH SIZE 16BIT
#0001
32BIT
PERIPH SIZE 32BIT
#0010
DATA_TRANS_NUM
Data Transfer Number Register
0x28
32
read-write
n
0x0
0x0
DATA_TRANS_NUM
data has been transfered number
0
16
read-write
FIFO_LEFT_NUM
Internal FIFO Data Left Number Register
0x2C
32
read-write
n
0x0
0x0
FIFO_LEFT_NUM
internal fifo data left number
0
6
read-write
INTEN
Interrupt Enable Register
0x4
32
read-write
n
0x0
0x0
FINISH_INTERRUPT_ENABLE
transfer finished interrupt enable or disable
0
1
read-write
HALF_FINISH_INTERRUPT_ENABLE
transfer half finished interrupt enable or disable
1
1
read-write
TRANS_ERROR_INTERRUPT_ENABLE
transfer error interrupt enable or disable
2
1
read-write
MEM_END_ADDR
Memory End Address Register
0x1C
32
read-write
n
0x0
0x0
MEM_END_ADDR
set memory end address
0
32
read-write
MEM_START_ADDR
Memory Start Address Register
0x18
32
read-write
n
0x0
0x0
MEM_START_ADDR
memory start address
0
32
read-write
PERIPH_ADDR
Peripheral Address Register
0x20
32
read-write
n
0x0
0x0
PERIPH_ADDR
set peripheral address
0
32
read-write
RST
Reset Register
0x8
32
read-write
n
0x0
0x0
FLUSH
dma flush enable or disable
2
1
read-write
HARD_RST
hard reset enable or disable
1
1
read-write
WARM_RST
warm reset enable or disable
0
1
read-write
STATUS
Status Register
0x0
32
read-write
n
0x0
0x0
FINISH
transfer finished flag
0
1
read-write
HALF_FINISH
transfer half finished flag
1
1
read-write
TRANS_ERROR
transfer error flag
2
1
read-write
STOP
Stop Register
0xC
32
read-write
n
0x0
0x0
STOP
DMA channel stop enable or disable
0
1
read-write
DMA0_TOP_RST
DMA0 All Channnels Share The Registers
DMA0
0x0
0x0
0x4
registers
n
TOP_RST
TOP_RST Register
0x0
32
read-write
n
0x0
0x0
HARD_RST
hard reset
1
1
read-write
WARM_RST
warm reset
0
1
read-write
ECC_SRAM
SRAM Error Check and Correction
ECC_SRAM
0x0
0x0
0xC
registers
n
ECC_SRAM
ECC SRAM interrupt
26
CTRL
SRAM ECC status and control register
0x0
32
read-write
n
0x0
0x0
ERR2_IRQEN
ECC 2 bit error interrupt enable
1
1
read-write
0
ECC 2 bit error interrupt disabled
#0
1
ECC 2 bit error interrupt enabled
#1
ERR2_STATUS
ECC 2 bit error status
2
1
read-only
0
ECC 2 bit error is inactive
#0
1
ECC 2 bit error is active
#1
ERR_STATUS
ECC (2bit/1)bit error status
4
2
read-write
00
ECC has no error
#00
01
ECC 2 bit error is active
#01
#10
ECC 1 bit error is active
#10
11
ECC 1 bit error is active
#11
ERR1_ADDR
ECC 1 bit error address
0x4
32
read-only
n
0x0
0x0
ERR1_ADDR
ECC 1 bit Error Address
0
13
read-only
ERR2_ADDR
ECC 2 bit error address
0x8
32
read-only
n
0x0
0x0
ERR2_ADDR
ECC 2 bit Error Address
0
13
read-only
EFLASH
Embedded Flash
EFLASH
0x0
0x0
0x48
registers
n
KEY
Key sequence register
0x0
32
read-write
n
0x0
0x0
KEY
Key sequence value
0
32
read-write
EXTI
External Interrupt
GPIO
0x0
0x0
0x18
registers
n
EXTI0
GPIOx PIN0 external interrupt
27
EXTI1
GPIOx PIN1 external interrupt
28
EXTI2
GPIOx PIN2 external interrupt
29
EXTI3_8
GPIOx PIN3~8 external interrupt
30
EXTI9_15
GPIOx PIN9~15 external interrupt
31
EXTICR0
EXTI Control Register
0x10
32
read-write
n
0x0
0x0
EXTI0
select PORTx for GPIOx_PIN0 external interrupt
0
4
read-write
PA
PA[x] Pin
#0000
PB
PB[x] Pin
#0001
PC
PC[x] Pin
#0010
EXTI1
select PORTx for GPIOx_PIN1 external interrupt
4
4
read-write
PA
PA[x] Pin
#0000
PB
PB[x] Pin
#0001
PC
PC[x] Pin
#0010
EXTI2
select PORTx for GPIOx_PIN2 external interrupt
8
4
read-write
PA
PA[x] Pin
#0000
PB
PB[x] Pin
#0001
PC
PC[x] Pin
#0010
EXTI3
select PORTx for GPIOx_PIN4 external interrupt
12
4
read-write
PA
PA[x] Pin
#0000
PB
PB[x] Pin
#0001
PC
PC[x] Pin
#0010
EXTICR1
EXTI Control Register
0x14
32
read-write
n
0x0
0x0
EXTI0
select PORTx for GPIOx_PIN0 external interrupt
0
4
read-write
PA
PA[x] Pin
#0000
PB
PB[x] Pin
#0001
PC
PC[x] Pin
#0010
EXTI1
select PORTx for GPIOx_PIN1 external interrupt
4
4
read-write
PA
PA[x] Pin
#0000
PB
PB[x] Pin
#0001
PC
PC[x] Pin
#0010
EXTI2
select PORTx for GPIOx_PIN2 external interrupt
8
4
read-write
PA
PA[x] Pin
#0000
PB
PB[x] Pin
#0001
PC
PC[x] Pin
#0010
EXTI3
select PORTx for GPIOx_PIN4 external interrupt
12
4
read-write
PA
PA[x] Pin
#0000
PB
PB[x] Pin
#0001
PC
PC[x] Pin
#0010
EXTICR2
EXTI Control Register
0x18
32
read-write
n
0x0
0x0
EXTI0
select PORTx for GPIOx_PIN0 external interrupt
0
4
read-write
PA
PA[x] Pin
#0000
PB
PB[x] Pin
#0001
PC
PC[x] Pin
#0010
EXTI1
select PORTx for GPIOx_PIN1 external interrupt
4
4
read-write
PA
PA[x] Pin
#0000
PB
PB[x] Pin
#0001
PC
PC[x] Pin
#0010
EXTI2
select PORTx for GPIOx_PIN2 external interrupt
8
4
read-write
PA
PA[x] Pin
#0000
PB
PB[x] Pin
#0001
PC
PC[x] Pin
#0010
EXTI3
select PORTx for GPIOx_PIN4 external interrupt
12
4
read-write
PA
PA[x] Pin
#0000
PB
PB[x] Pin
#0001
PC
PC[x] Pin
#0010
EXTICR3
EXTI Control Register
0x1C
32
read-write
n
0x0
0x0
EXTI0
select PORTx for GPIOx_PIN0 external interrupt
0
4
read-write
PA
PA[x] Pin
#0000
PB
PB[x] Pin
#0001
PC
PC[x] Pin
#0010
EXTI1
select PORTx for GPIOx_PIN1 external interrupt
4
4
read-write
PA
PA[x] Pin
#0000
PB
PB[x] Pin
#0001
PC
PC[x] Pin
#0010
EXTI2
select PORTx for GPIOx_PIN2 external interrupt
8
4
read-write
PA
PA[x] Pin
#0000
PB
PB[x] Pin
#0001
PC
PC[x] Pin
#0010
EXTI3
select PORTx for GPIOx_PIN4 external interrupt
12
4
read-write
PA
PA[x] Pin
#0000
PB
PB[x] Pin
#0001
PC
PC[x] Pin
#0010
FTSR
EXTI Falling edge Register
0xC
32
read-write
n
0x0
0x0
FTSR0
GPIOx_PIN0 exti falling edge enable flag
0
1
read-write
FTSR1
GPIOx_PIN1 exti falling edge enable flag
1
1
read-write
FTSR10
GPIOx_PIN10 exti falling edge enable flag
10
1
read-write
FTSR11
GPIOx_PIN11 exti falling edge enable flag
11
1
read-write
FTSR12
GPIOx_PIN12 exti falling edge enable flag
12
1
read-write
FTSR13
GPIOx_PIN13 exti falling edge enable flag
13
1
read-write
FTSR14
GPIOx_PIN14 exti falling edge enable flag
14
1
read-write
FTSR15
GPIOx_PIN15 exti falling edge enable flag
15
1
read-write
FTSR2
GPIOx_PIN2 exti falling edge enable flag
2
1
read-write
FTSR3
GPIOx_PIN3 exti falling edge enable flag
3
1
read-write
FTSR4
GPIOx_PIN4 exti falling edge enable flag
4
1
read-write
FTSR5
GPIOx_PIN5 exti falling edge enable flag
5
1
read-write
FTSR6
GPIOx_PIN6 exti falling edge enable flag
6
1
read-write
FTSR7
GPIOx_PIN7 exti falling edge enable flag
7
1
read-write
FTSR8
GPIOx_PIN8 exti falling edge enable flag
8
1
read-write
FTSR9
GPIOx_PIN9 exti falling edge enable flag
9
1
read-write
IMR
EXTI Mask Register
0x4
32
read-write
n
0x0
0x0
IMR0
GPIOx_PIN0 exti mask flag
0
1
read-write
IMR1
GPIOx_PIN1 exti mask flag
1
1
read-write
IMR10
GPIOx_PIN10 exti mask flag
10
1
read-write
IMR11
GPIOx_PIN11 exti mask flag
11
1
read-write
IMR12
GPIOx_PIN12 exti mask flag
12
1
read-write
IMR13
GPIOx_PIN13 exti mask flag
13
1
read-write
IMR14
GPIOx_PIN14 exti mask flag
14
1
read-write
IMR15
GPIOx_PIN15 exti mask flag
15
1
read-write
IMR2
GPIOx_PIN2 exti mask flag
2
1
read-write
IMR3
GPIOx_PIN3 exti mask flag
3
1
read-write
IMR4
GPIOx_PIN4 exti mask flag
4
1
read-write
IMR5
GPIOx_PIN5 exti mask flag
5
1
read-write
IMR6
GPIOx_PIN6 exti mask flag
6
1
read-write
IMR7
GPIOx_PIN7 exti mask flag
7
1
read-write
IMR8
GPIOx_PIN8 exti mask flag
8
1
read-write
IMR9
GPIOx_PIN9 exti mask flag
9
1
read-write
PR
EXTI Pending Register
0x0
32
read-write
n
0x0
0x0
PR0
GPIOx_PIN0 exti flag
0
1
read-write
PR1
GPIOx_PIN1 exti flag
1
1
read-write
PR10
GPIOx_PIN10 exti flag
10
1
read-write
PR11
GPIOx_PIN11 exti flag
11
1
read-write
PR12
GPIOx_PIN12 exti flag
12
1
read-write
PR13
GPIOx_PIN13 exti flag
13
1
read-write
PR14
GPIOx_PIN14 exti flag
14
1
read-write
PR15
GPIOx_PIN15 exti flag
15
1
read-write
PR2
GPIOx_PIN2 exti flag
2
1
read-write
PR3
GPIOx_PIN3 exti flag
3
1
read-write
PR4
GPIOx_PIN4 exti flag
4
1
read-write
PR5
GPIOx_PIN5 exti flag
5
1
read-write
PR6
GPIOx_PIN6 exti flag
6
1
read-write
PR7
GPIOx_PIN7 exti flag
7
1
read-write
PR8
GPIOx_PIN8 exti flag
8
1
read-write
PR9
GPIOx_PIN9 exti flag
9
1
read-write
RTSR
EXTI Rasing edge Register
0x8
32
read-write
n
0x0
0x0
RTSR0
GPIOx_PIN0 exti rasing edge enable flag
0
1
read-write
RTSR1
GPIOx_PIN1 exti rasing edge enable flag
1
1
read-write
RTSR10
GPIOx_PIN10 exti rasing edge enable flag
10
1
read-write
RTSR11
GPIOx_PIN11 exti rasing edge enable flag
11
1
read-write
RTSR12
GPIOx_PIN12 exti rasing edge enable flag
12
1
read-write
RTSR13
GPIOx_PIN13 exti rasing edge enable flag
13
1
read-write
RTSR14
GPIOx_PIN14 exti rasing edge enable flag
14
1
read-write
RTSR15
GPIOx_PIN15 exti rasing edge enable flag
15
1
read-write
RTSR2
GPIOx_PIN2 exti rasing edge enable flag
2
1
read-write
RTSR3
GPIOx_PIN3 exti rasing edge enable flag
3
1
read-write
RTSR4
GPIOx_PIN4 exti rasing edge enable flag
4
1
read-write
RTSR5
GPIOx_PIN5 exti rasing edge enable flag
5
1
read-write
RTSR6
GPIOx_PIN6 exti rasing edge enable flag
6
1
read-write
RTSR7
GPIOx_PIN7 exti rasing edge enable flag
7
1
read-write
RTSR8
GPIOx_PIN8 exti rasing edge enable flag
8
1
read-write
RTSR9
GPIOx_PIN9 exti rasing edge enable flag
9
1
read-write
GPIOA
General Purpose Input/Output
GPIO
0x0
0x0
0x30
registers
n
BRR
GPIO Bit Reset Register
0x10
32
read-write
n
0x0
0x0
BR0
Port x, Reset bit 0
0
1
read-write
BR1
Port x, Reset bit 1
1
1
read-write
BR10
Port x, Reset bit 10
10
1
read-write
BR11
Port x, Reset bit 11
11
1
read-write
BR12
Port x, Reset bit 12
12
1
read-write
BR13
Port x, Reset bit 13
13
1
read-write
BR14
Port x, Reset bit 14
14
1
read-write
BR15
Port x, Reset bit 15
15
1
read-write
BR2
Port x, Reset bit 2
2
1
read-write
BR3
Port x, Reset bit 3
3
1
read-write
BR4
Port x, Reset bit 4
4
1
read-write
BR5
Port x, Reset bit 5
5
1
read-write
BR6
Port x, Reset bit 6
6
1
read-write
BR7
Port x, Reset bit 7
7
1
read-write
BR8
Port x, Reset bit 8
8
1
read-write
BR9
Port x, Reset bit 9
9
1
read-write
BSRR
GPIO Bit Set, Reset Register
0xC
32
read-write
n
0x0
0x0
BR0
Port x, Reset bit 0
16
1
read-write
BR1
Port x, Reset bit 1
17
1
read-write
BR10
Port x, Reset bit 10
26
1
read-write
BR11
Port x, Reset bit 11
27
1
read-write
BR12
Port x, Reset bit 12
28
1
read-write
BR13
Port x, Reset bit 13
29
1
read-write
BR14
Port x, Reset bit 14
30
1
read-write
BR15
Port x, Reset bit 15
31
1
read-write
BR2
Port x, Reset bit 2
18
1
read-write
BR3
Port x, Reset bit 3
19
1
read-write
BR4
Port x, Reset bit 4
20
1
read-write
BR5
Port x, Reset bit 5
21
1
read-write
BR6
Port x, Reset bit 6
22
1
read-write
BR7
Port x, Reset bit 7
23
1
read-write
BR8
Port x, Reset bit 8
24
1
read-write
BR9
Port x, Reset bit 9
25
1
read-write
BS0
Port x, Set bit 0
0
1
read-write
BS1
Port x, Set bit 1
1
1
read-write
BS10
Port x, Set bit 10
10
1
read-write
BS11
Port x, Set bit 11
11
1
read-write
BS12
Port x, Set bit 12
12
1
read-write
BS13
Port x, Set bit 13
13
1
read-write
BS14
Port x, Set bit 14
14
1
read-write
BS15
Port x, Set bit 15
15
1
read-write
BS2
Port x, Set bit 2
2
1
read-write
BS3
Port x, Set bit 3
3
1
read-write
BS4
Port x, Set bit 4
4
1
read-write
BS5
Port x, Set bit 5
5
1
read-write
BS6
Port x, Set bit 6
6
1
read-write
BS7
Port x, Set bit 7
7
1
read-write
BS8
Port x, Set bit 8
8
1
read-write
BS9
Port x, Set bit 9
9
1
read-write
CR
GPIOx Configuration Register
0x0
32
read-write
n
0x0
0x0
MODE0
MODE0[0] bits (Port x mode bits, pin 0)
0
1
read-write
MODE1
MODE1[0] bits (Port x mode bits, pin 1)
1
1
read-write
MODE10
MODE10[0] bits (Port x mode bits, pin 10)
10
1
read-write
MODE11
MODE11[0] bits (Port x mode bits, pin 11)
11
1
read-write
MODE12
MODE12[0] bits (Port x mode bits, pin 12)
12
1
read-write
MODE13
MODE13[0] bits (Port x mode bits, pin 13)
13
1
read-write
MODE14
MODE14[0] bits (Port x mode bits, pin 14)
14
1
read-write
MODE15
MODE15[0] bits (Port x mode bits, pin 15)
15
1
read-write
MODE2
MODE2[0] bits (Port x mode bits, pin 2)
2
1
read-write
MODE3
MODE3[0] bits (Port x mode bits, pin 3)
3
1
read-write
MODE4
MODE4[0] bits (Port x mode bits, pin 4)
4
1
read-write
MODE5
MODE5[0] bits (Port x mode bits, pin 5)
5
1
read-write
MODE6
MODE6[0] bits (Port x mode bits, pin 6)
6
1
read-write
MODE7
MODE7[0] bits (Port x mode bits, pin 7)
7
1
read-write
MODE8
MODE8[0] bits (Port x mode bits, pin 8)
8
1
read-write
MODE9
MODE9[0] bits (Port x mode bits, pin 9)
9
1
read-write
E4_E2
GPIO E4_E2 Register
0x20
32
read-write
n
0x0
0x0
E4_E2_0
Port x, Pin 0 driving current
0
2
read-write
4mA
Driving 4mA
#00
8mA
Driving 8mA
#01
12mA
Driving 12mA
#10
16mA
Driving 16mA
#11
E4_E2_1
Port x, Pin 1 driving current
2
2
read-write
4mA
Driving 4mA
#00
8mA
Driving 8mA
#01
12mA
Driving 12mA
#10
16mA
Driving 16mA
#11
E4_E2_10
Port x, Pin 10 driving current
20
2
read-write
4mA
Driving 4mA
#00
8mA
Driving 8mA
#01
12mA
Driving 12mA
#10
16mA
Driving 16mA
#11
E4_E2_11
Port x, Pin 11 driving current
22
2
read-write
4mA
Driving 4mA
#00
8mA
Driving 8mA
#01
12mA
Driving 12mA
#10
16mA
Driving 16mA
#11
E4_E2_12
Port x, Pin 12 driving current
24
2
read-write
4mA
Driving 4mA
#00
8mA
Driving 8mA
#01
12mA
Driving 12mA
#10
16mA
Driving 16mA
#11
E4_E2_13
Port x, Pin 13 driving current
26
2
read-write
4mA
Driving 4mA
#00
8mA
Driving 8mA
#01
12mA
Driving 12mA
#10
16mA
Driving 16mA
#11
E4_E2_14
Port x, Pin 14 driving current
28
2
read-write
4mA
Driving 4mA
#00
8mA
Driving 8mA
#01
12mA
Driving 12mA
#10
16mA
Driving 16mA
#11
E4_E2_15
Port x, Pin 15 driving current
30
2
read-write
4mA
Driving 4mA
#00
8mA
Driving 8mA
#01
12mA
Driving 12mA
#10
16mA
Driving 16mA
#11
E4_E2_2
Port x, Pin 2 driving current
4
2
read-write
4mA
Driving 4mA
#00
8mA
Driving 8mA
#01
12mA
Driving 12mA
#10
16mA
Driving 16mA
#11
E4_E2_3
Port x, Pin 3 driving current
6
2
read-write
4mA
Driving 4mA
#00
8mA
Driving 8mA
#01
12mA
Driving 12mA
#10
16mA
Driving 16mA
#11
E4_E2_4
Port x, Pin 4 driving current
8
2
read-write
4mA
Driving 4mA
#00
8mA
Driving 8mA
#01
12mA
Driving 12mA
#10
16mA
Driving 16mA
#11
E4_E2_5
Port x, Pin 5 driving current
10
2
read-write
4mA
Driving 4mA
#00
8mA
Driving 8mA
#01
12mA
Driving 12mA
#10
16mA
Driving 16mA
#11
E4_E2_6
Port x, Pin 6 driving current
12
2
read-write
4mA
Driving 4mA
#00
8mA
Driving 8mA
#01
12mA
Driving 12mA
#10
16mA
Driving 16mA
#11
E4_E2_7
Port x, Pin 7 driving current
14
2
read-write
4mA
Driving 4mA
#00
8mA
Driving 8mA
#01
12mA
Driving 12mA
#10
16mA
Driving 16mA
#11
E4_E2_8
Port x, Pin 8 driving current
16
2
read-write
4mA
Driving 4mA
#00
8mA
Driving 8mA
#01
12mA
Driving 12mA
#10
16mA
Driving 16mA
#11
E4_E2_9
Port x, Pin 9 driving current
18
2
read-write
4mA
Driving 4mA
#00
8mA
Driving 8mA
#01
12mA
Driving 12mA
#10
16mA
Driving 16mA
#11
IDR
GPIO Input Data Register
0x4
32
read-only
n
0x0
0x0
IDR0
Port input data, bit 0
0
1
read-write
IDR1
Port input data, bit 1
1
1
read-write
IDR10
Port input data, bit 10
10
1
read-write
IDR11
Port input data, bit 11
11
1
read-write
IDR12
Port input data, bit 12
12
1
read-write
IDR13
Port input data, bit 13
13
1
read-write
IDR14
Port input data, bit 14
14
1
read-write
IDR15
Port input data, bit 15
15
1
read-write
IDR2
Port input data, bit 2
2
1
read-write
IDR3
Port input data, bit 3
3
1
read-write
IDR4
Port input data, bit 4
4
1
read-write
IDR5
Port input data, bit 5
5
1
read-write
IDR6
Port input data, bit 6
6
1
read-write
IDR7
Port input data, bit 7
7
1
read-write
IDR8
Port input data, bit 8
8
1
read-write
IDR9
Port input data, bit 9
9
1
read-write
ODR
GPIO Output Data Register
0x8
32
read-write
n
0x0
0x0
ODR0
Port output data, bit 0
0
1
read-write
ODR1
Port output data, bit 1
1
1
read-write
ODR10
Port output data, bit 10
10
1
read-write
ODR11
Port output data, bit 11
11
1
read-write
ODR12
Port output data, bit 12
12
1
read-write
ODR13
Port output data, bit 13
13
1
read-write
ODR14
Port output data, bit 14
14
1
read-write
ODR15
Port output data, bit 15
15
1
read-write
ODR2
Port output data, bit 2
2
1
read-write
ODR3
Port output data, bit 3
3
1
read-write
ODR4
Port output data, bit 4
4
1
read-write
ODR5
Port output data, bit 5
5
1
read-write
ODR6
Port output data, bit 6
6
1
read-write
ODR7
Port output data, bit 7
7
1
read-write
ODR8
Port output data, bit 8
8
1
read-write
ODR9
Port output data, bit 9
9
1
read-write
PD
GPIO Pull Down Register
0x18
32
read-write
n
0x0
0x0
PD0
Port x, Pin 0 pull down
0
1
read-write
PD1
Port x, Pin 1 pull down
1
1
read-write
PD10
Port x, Pin 10 pull down
10
1
read-write
PD11
Port x, Pin 11 pull down
11
1
read-write
PD12
Port x, Pin 12 pull down
12
1
read-write
PD13
Port x, Pin 13 pull down
13
1
read-write
PD14
Port x, Pin 14 pull down
14
1
read-write
PD15
Port x, Pin 15 pull down
15
1
read-write
PD2
Port x, Pin 2 pull down
2
1
read-write
PD3
Port x, Pin 3 pull down
3
1
read-write
PD4
Port x, Pin 4 pull down
4
1
read-write
PD5
Port x, Pin 5 pull down
5
1
read-write
PD6
Port x, Pin 6 pull down
6
1
read-write
PD7
Port x, Pin 7 pull down
7
1
read-write
PD8
Port x, Pin 8 pull down
8
1
read-write
PD9
Port x, Pin 9 pull down
9
1
read-write
PU
GPIO Pull Up Register
0x1C
32
read-write
n
0x0
0x0
PU0
Port x, Pin 0 pull up
0
1
read-write
PU1
Port x, Pin 1 pull up
1
1
read-write
PU10
Port x, Pin 10 pull up
10
1
read-write
PU11
Port x, Pin 11 pull up
11
1
read-write
PU12
Port x, Pin 12 pull up
12
1
read-write
PU13
Port x, Pin 13 pull up
13
1
read-write
PU14
Port x, Pin 14 pull up
14
1
read-write
PU15
Port x, Pin 15 pull up
15
1
read-write
PU2
Port x, Pin 2 pull up
2
1
read-write
PU3
Port x, Pin 3 pull up
3
1
read-write
PU4
Port x, Pin 4 pull up
4
1
read-write
PU5
Port x, Pin 5 pull up
5
1
read-write
PU6
Port x, Pin 6 pull up
6
1
read-write
PU7
Port x, Pin 7 pull up
7
1
read-write
PU8
Port x, Pin 8 pull up
8
1
read-write
PU9
Port x, Pin 9 pull up
9
1
read-write
I2C0
Inter-Integrated Circuit
I2C
0x0
0x0
0x34
registers
n
I2C0
I2C0 Interrupt
11
ADDR0
Address Register 0
0x0
32
read-write
n
0x0
0x0
AD
7Bit Address
1
7
read-write
ADDR1
Address register 1
0x4
32
read-write
n
0x0
0x0
AD
10Bit Address
0
3
read-write
RAD
7bit Range Address
4
7
read-write
RMEN
7bit Range Enable
12
1
read-write
CTRL0
Control Register 0
0x10
32
read-write
n
0x0
0x0
IICEN
I2C Module Enable
7
1
read-write
IICIE
I2C interrupt Enable
6
1
read-write
MSTR
I2C operation mode Select
5
1
read-write
0
Slave Mode
#0
1
Master Mode
#1
TACK
Transmit Acknowledge Enable
3
1
read-write
0
ACK will sent to the bus on the following receiving byte
#0
1
NACK will sent to the bus on the following receiving byte
#1
TX
Master Transmit Direction Select
4
1
read-write
WUEN
wakeup enable
2
1
read-write
CTRL1
Control Register 1
0x14
32
read-write
n
0x0
0x0
ADEXT
Slave Address Extension
6
1
read-write
ARBEN
Arbitration Enable
3
1
read-write
GCAEN
Slave General Call Enable
7
1
read-write
STREN
Slave SCL Strech Enable
0
1
read-write
SYNCEN
SCL Sync Enable
4
1
read-write
CTRL2
Control Register 2
0x18
32
read-write
n
0x0
0x0
MNTEN
Slave Monitor Function Enable
0
1
read-write
NACKIE
NACK Get Interrupt Enable
1
1
read-write
RXFIE
Slave RX Buffer Full Interrupt Enable
5
1
read-write
RXOFIE
Slave RX Buffer Overflow Error Interrupt Enable
7
1
read-write
TXEMIE
Slave TX Buffer Empty Interrupt Enable
4
1
read-write
TXUFIE
Slave TX Buffer Underflow Error Interrupt Enable
6
1
read-write
CTRL3
Control Register 3
0x1C
32
read-write
n
0x0
0x0
DMARXEN
DMARX Enable
1
1
read-write
DMATXEN
DMATX Enable
0
1
read-write
DATA
Data Register
0x2C
32
read-write
n
0x0
0x0
DATA
Data
0
8
read-write
MAK
Slave Monitor Function ACK bit
8
1
read-only
DGLCFG
Deglitch Configuration Register
0x28
32
read-write
n
0x0
0x0
DGLEN
I2C Deglitch Filter Enable
7
1
read-write
DGL_CNT
Deglitch Counter
0
4
read-write
SSIE
I2C Bus START or STOP Interrupt Enable
5
1
read-write
STARTF
I2C Bus Start Flag
4
1
read-write
STOPF
I2C Bus Stop Flag
6
1
read-write
SAMPLE_CNT
SAMPLE_CNT Register
0x8
32
read-write
n
0x0
0x0
SAMPLE_CNT
Adjust the width of each sample
0
8
read-write
STARTSTOP
START_STOP Register
0x30
32
read-write
n
0x0
0x0
START
Master Send Start Signal
0
1
read-write
STOP
Matsre Send I2C Stop Signal
1
1
read-write
STATUS0
Status Register 0
0x20
32
read-write
n
0x0
0x0
ARBLOST
Arbitration Lost Flag
4
1
read-write
BND
Byte Tx End Flag(include ACK bit, 9 SCL)
7
1
read-write
BUSY
Indicates The Status of The Bus in Slave/Master
5
1
read-only
RACK
Acknowledge Received(master or slave TX mode)
0
1
read-write
READY
Internal Hardware Core Is Ready For New Command or Not
3
1
read-only
SAMF
Slave Address Match Flag
6
1
read-write
SRW
Slave Read/Write Direction
2
1
read-only
STATUS1
Status Register 1
0x24
32
read-write
n
0x0
0x0
RXFF
Slave RX Buffer Full flag
1
1
read-write
RXOF
Slave RX Buffer Overflow Flag
3
1
read-write
TXEF
Slave TX Buffer Empty Flag
0
1
read-write
TXUF
Slave TX Buffer Underflow Flag
2
1
read-write
STEP_CNT
STEP_CNT Register
0xC
32
read-write
n
0x0
0x0
STEP_CNT
Specifies the number of Samples per half pulse width
0
8
read-write
MMDIVSQRT
Division and Square root mudule
MMDIVSQRT
0x0
0x0
0x1C
registers
n
CSR
Control/Status Register
0x14
32
read-write
n
0x0
0x0
BUSY
MMDIVSQRT is busy for performing a divide or square root flag
31
1
read-only
DIV
current or last operation was a div flag
30
1
read-only
REM
quotient or the remainder is returned in the RES register
2
1
read-write
SQRT
current or last operation was a sqrt flag
29
1
read-only
USIGN
unsigned or signed is written in DEND/DSOR
1
1
read-write
DEND
Dividend Register
0x0
32
read-write
n
0x0
0x0
DEND
Input dividend (numerator) for the divide
0
32
read-write
DSFT
Dividend Shifter Register
0x8
32
read-write
n
0x0
0x0
DSFT
Input Shifter for the divide (0, 32)
0
5
read-write
DSOR
Divisor Register
0x4
32
read-write
n
0x0
0x0
DSOR
Input divisor (denominator) for the divide
0
32
read-write
RCNDX
RCNDX Register
0xC
32
read-write
n
0x0
0x0
RCNDX
Input square data x
0
32
read-write
RCNDY
RCNDY Register
0x10
32
read-write
n
0x0
0x0
RCNDY
Input square data y
0
32
read-write
RESULT
Result Register
0x18
32
read-only
n
0x0
0x0
RESULT
Output result
0
32
read-only
PMUX
PinMux Function
GPIO
0x0
0x0
0x4
registers
n
PINMUX0
PinMux Function Register
0x0
32
read-write
n
0x0
0x0
PINMUX0
GPIO_PA0 pinmux
0
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX1
GPIO_PA1 pinmux
3
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX2
GPIO_PA2 pinmux
6
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX3
GPIO_PA3 pinmux
9
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX4
GPIO_PA4 pinmux
12
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX5
GPIO_PA5 pinmux
15
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX6
GPIO_PA6 pinmux
18
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX7
GPIO_PA7 pinmux
21
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX8
GPIO_PA8 pinmux
24
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX9
GPIO_PA9 pinmux
27
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX1
PinMux Function Register
0x4
32
read-write
n
0x0
0x0
PINMUX0
GPIO_PA0 pinmux
0
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX1
GPIO_PA1 pinmux
3
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX2
GPIO_PA2 pinmux
6
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX3
GPIO_PA3 pinmux
9
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX4
GPIO_PA4 pinmux
12
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX5
GPIO_PA5 pinmux
15
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX6
GPIO_PA6 pinmux
18
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX7
GPIO_PA7 pinmux
21
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX8
GPIO_PA8 pinmux
24
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX9
GPIO_PA9 pinmux
27
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX2
PinMux Function Register
0x8
32
read-write
n
0x0
0x0
PINMUX0
GPIO_PA0 pinmux
0
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX1
GPIO_PA1 pinmux
3
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX2
GPIO_PA2 pinmux
6
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX3
GPIO_PA3 pinmux
9
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX4
GPIO_PA4 pinmux
12
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX5
GPIO_PA5 pinmux
15
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX6
GPIO_PA6 pinmux
18
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX7
GPIO_PA7 pinmux
21
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX8
GPIO_PA8 pinmux
24
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX9
GPIO_PA9 pinmux
27
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX3
PinMux Function Register
0xC
32
read-write
n
0x0
0x0
PINMUX0
GPIO_PA0 pinmux
0
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX1
GPIO_PA1 pinmux
3
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX2
GPIO_PA2 pinmux
6
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX3
GPIO_PA3 pinmux
9
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX4
GPIO_PA4 pinmux
12
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX5
GPIO_PA5 pinmux
15
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX6
GPIO_PA6 pinmux
18
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX7
GPIO_PA7 pinmux
21
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX8
GPIO_PA8 pinmux
24
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX9
GPIO_PA9 pinmux
27
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX4
PinMux Function Register
0x10
32
read-write
n
0x0
0x0
PINMUX0
GPIO_PA0 pinmux
0
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX1
GPIO_PA1 pinmux
3
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX2
GPIO_PA2 pinmux
6
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX3
GPIO_PA3 pinmux
9
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX4
GPIO_PA4 pinmux
12
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX5
GPIO_PA5 pinmux
15
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX6
GPIO_PA6 pinmux
18
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX7
GPIO_PA7 pinmux
21
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX8
GPIO_PA8 pinmux
24
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PINMUX9
GPIO_PA9 pinmux
27
3
read-write
FUNC0
Function 0
#000
FUNC1
Function 1
#001
FUNC2
Function 2
#010
FUNC3
Function 3
#011
PWDT0
Pulse Width Detection Timer
PWDT0
0x0
0x0
0x12
registers
n
PWDT0
PWDT0 interrupt
0
INIT0
PWDT Initialize Register 0
0x0
32
read-write
n
0x0
0x0
EDGE
PWDT Input Edge Sensitivity
10
2
read-write
00
The first falling-edge starts the pulse width measurement, and on all the subsequent falling edges, the pulse width is captured.
#00
01
The first rising edge starts the pulse width measurement, and on all the subsequent rising and falling edges, the pulse width is captured.
#01
10
The first falling edge starts the pulse width measurement, and on all the subsequent rising and falling edges, the pulse width is captured.
#10
11
The first-rising edge starts the pulse width measurement, and on all the subsequent rising edges, the pulse width is captured.
#11
IE
PWDT Module Interrupt Enable
5
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
OVF
PWDT Counter Overflow flag
0
1
read-write
0
Counter no overflow
#0
1
Counter overflow
#1
OVIE
PWDT Counter Overflow Interrupt Enable
3
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
PINSEL
PWDT Pulse Inputs Selection
12
2
read-write
00
PWDTIN[0] as input
#00
01
PWDTIN[1] as input
#01
10
PWDTIN[2] as input
#10
11
PWDTIN[3] as input
#11
PPW
Positive Pulse Width
16
16
read-only
PRDYIE
PWDT Pulse Width Data Ready Interrupt Enable
4
1
read-write
0
Disable interrupt
#0
1
Enable interrupt
#1
PSC0
PWDT Clock Prescaler 0
7
3
read-write
000
Clock divided by 1
#000
001
Clock divided by 2
#001
010
Clock divided by 4
#010
011
Clock divided by 8
#011
100
Clock divided by 16
#100
101
Clock divided by 32
#101
110
Clock divided by 64
#110
111
Clock divided by 128
#111
PSC1
PWDT Clock Prescaler 1
14
2
read-write
00
Clock divided by 1
#00
01
Clock divided by 2
#01
10
Clock divided by 4
#10
PWDTEN
PWDT Module Enable
6
1
read-write
0
PWDT disabled
#0
1
PWDT enabled
#1
RDYF
PWDT Pulse Width Ready Flag
1
1
read-write
0
PWDT pulse width register is not up-to-date
#0
1
PWDT pulse width register has been updated
#1
INIT1
Pulse Width Detection Timer Initialize Register 1
0x8
32
read-write
n
0x0
0x0
CMPEN
PWDT Compare Mode Enable Bit
11
1
read-write
0
Set the pwt_in0 ~ pwt_in2 derived from acmp0_pwt_a ~ acmp0_pwt_c
#0
1
Set the pwt_in0 ~ pwt_in2 derived from pad pwt_in0 ~ pwt_in2
#1
FILTEN
PWDT input filter function Enable Bit
8
1
read-write
0
Filter disable
#0
1
Filter enable
#1
FILTPSC
PWDT input filter prescaler
4
4
read-write
FILTVAL
PWDT filter Value
0
4
read-write
HALLEN
Hall Sensor Signal Detect function Enable Bit
9
1
read-write
0
Hall Sensor Signal Detect function Disable
#0
1
Hall Sensor Signal Detect function Enable
#1
HALLSTATUS
HALL Sensor Status Value
28
3
read-only
TIMEN
PWDT Timer Function Enable Bit
10
1
read-write
0
PWDT Timer Function Disable
#0
1
PWDT Timer Function Enable
#1
TIMLDVAL
PWDT Timer Load Value
12
16
read-write
NPW
Negative Pulse Width
0x4
32
read-only
n
0x0
0x0
NPW
Negative Pulse Width
0
16
read-only
PWDTC
PWDT Counter
16
16
read-only
PWM0
Pulse Width Modulation
PWM
0x0
0x0
0xA0
registers
n
PWM0
PWM0 interrupt
2
CAPFILTER
Input Capture Filter Control
0x78
32
read-write
n
0x0
0x0
CH0CAPFVAL
Channel 0 Input Filter
0
5
read-write
CH1CAPFVAL
Channel 1 Input Filter
5
5
read-write
CH2CAPFVAL
Channel 2 Input Filter
10
5
read-write
CH3CAPFVAL
Channel 3 Input Filter
15
5
read-write
CH0SCR
Channel (n) Status And Control Register
0xC
32
read-write
n
0x0
0x0
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
CHIF
Channel Interrupt Flag
7
1
read-write
0
No channel event has occurred.
#0
1
Channel event has occurred.
#1
DIR
Match point direction
1
1
read-write
0
Down count match
#0
1
Up count match
#1
ELSR0
Edge or Level Select Register 0
2
1
read-write
ELSR1
Edge or Level Select Register 1
3
1
read-write
MSR0
Channel Mode Select Register 0
4
1
read-write
MSR1
Channel Mode Select Register 1
5
1
read-write
CH0V
Channel (n) Value
0x10
32
read-write
n
0x0
0x0
CHCVAL
Channel Count Value
0
16
read-write
CH1SCR
Channel (n) Status And Control Register
0x14
32
read-write
n
0x0
0x0
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
CHIF
Channel Interrupt Flag
7
1
read-write
0
No channel event has occurred.
#0
1
Channel event has occurred.
#1
DIR
Match point direction
1
1
read-write
0
Down count match
#0
1
Up count match
#1
ELSR0
Edge or Level Select Register 0
2
1
read-write
ELSR1
Edge or Level Select Register 1
3
1
read-write
MSR0
Channel Mode Select Register 0
4
1
read-write
MSR1
Channel Mode Select Register 1
5
1
read-write
CH1V
Channel (n) Value
0x18
32
read-write
n
0x0
0x0
CHCVAL
Channel Count Value
0
16
read-write
CH2SCR
Channel (n) Status And Control Register
0x1C
32
read-write
n
0x0
0x0
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
CHIF
Channel Interrupt Flag
7
1
read-write
0
No channel event has occurred.
#0
1
Channel event has occurred.
#1
DIR
Match point direction
1
1
read-write
0
Down count match
#0
1
Up count match
#1
ELSR0
Edge or Level Select Register 0
2
1
read-write
ELSR1
Edge or Level Select Register 1
3
1
read-write
MSR0
Channel Mode Select Register 0
4
1
read-write
MSR1
Channel Mode Select Register 1
5
1
read-write
CH2V
Channel (n) Value
0x20
32
read-write
n
0x0
0x0
CHCVAL
Channel Count Value
0
16
read-write
CH3SCR
Channel (n) Status And Control Register
0x24
32
read-write
n
0x0
0x0
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
CHIF
Channel Interrupt Flag
7
1
read-write
0
No channel event has occurred.
#0
1
Channel event has occurred.
#1
DIR
Match point direction
1
1
read-write
0
Down count match
#0
1
Up count match
#1
ELSR0
Edge or Level Select Register 0
2
1
read-write
ELSR1
Edge or Level Select Register 1
3
1
read-write
MSR0
Channel Mode Select Register 0
4
1
read-write
MSR1
Channel Mode Select Register 1
5
1
read-write
CH3V
Channel (n) Value
0x28
32
read-write
n
0x0
0x0
CHCVAL
Channel Count Value
0
16
read-write
CH4SCR
Channel (n) Status And Control Register
0x2C
32
read-write
n
0x0
0x0
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
CHIF
Channel Interrupt Flag
7
1
read-write
0
No channel event has occurred.
#0
1
Channel event has occurred.
#1
DIR
Match point direction
1
1
read-write
0
Down count match
#0
1
Up count match
#1
ELSR0
Edge or Level Select Register 0
2
1
read-write
ELSR1
Edge or Level Select Register 1
3
1
read-write
MSR0
Channel Mode Select Register 0
4
1
read-write
MSR1
Channel Mode Select Register 1
5
1
read-write
CH4V
Channel (n) Value
0x30
32
read-write
n
0x0
0x0
CHCVAL
Channel Count Value
0
16
read-write
CH5SCR
Channel (n) Status And Control Register
0x34
32
read-write
n
0x0
0x0
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
CHIF
Channel Interrupt Flag
7
1
read-write
0
No channel event has occurred.
#0
1
Channel event has occurred.
#1
DIR
Match point direction
1
1
read-write
0
Down count match
#0
1
Up count match
#1
ELSR0
Edge or Level Select Register 0
2
1
read-write
ELSR1
Edge or Level Select Register 1
3
1
read-write
MSR0
Channel Mode Select Register 0
4
1
read-write
MSR1
Channel Mode Select Register 1
5
1
read-write
CH5V
Channel (n) Value
0x38
32
read-write
n
0x0
0x0
CHCVAL
Channel Count Value
0
16
read-write
CH6SCR
Channel (n) Status And Control Register
0x3C
32
read-write
n
0x0
0x0
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
CHIF
Channel Interrupt Flag
7
1
read-write
0
No channel event has occurred.
#0
1
Channel event has occurred.
#1
DIR
Match point direction
1
1
read-write
0
Down count match
#0
1
Up count match
#1
ELSR0
Edge or Level Select Register 0
2
1
read-write
ELSR1
Edge or Level Select Register 1
3
1
read-write
MSR0
Channel Mode Select Register 0
4
1
read-write
MSR1
Channel Mode Select Register 1
5
1
read-write
CH6V
Channel (n) Value
0x40
32
read-write
n
0x0
0x0
CHCVAL
Channel Count Value
0
16
read-write
CH7SCR
Channel (n) Status And Control Register
0x44
32
read-write
n
0x0
0x0
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
CHIF
Channel Interrupt Flag
7
1
read-write
0
No channel event has occurred.
#0
1
Channel event has occurred.
#1
DIR
Match point direction
1
1
read-write
0
Down count match
#0
1
Up count match
#1
ELSR0
Edge or Level Select Register 0
2
1
read-write
ELSR1
Edge or Level Select Register 1
3
1
read-write
MSR0
Channel Mode Select Register 0
4
1
read-write
MSR1
Channel Mode Select Register 1
5
1
read-write
CH7V
Channel (n) Value
0x48
32
read-write
n
0x0
0x0
CHCVAL
Channel Count Value
0
16
read-write
CHOPOLCR
Channel Output Polarity Register
0x70
32
read-write
n
0x0
0x0
CH0POL
Channel 0 Polarity
0
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
CH1POL
Channel 1 Polarity
1
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
CH2POL
Channel 2 Polarity
2
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
CH3POL
Channel 3 Polarity
3
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
CH4POL
Channel 4 Polarity
4
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
CH5POL
Channel 5 Polarity
5
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
CH6POL
Channel 6 Polarity
6
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
CH7POL
Channel 7 Polarity
7
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
CHOSWCR
PWM CHannel Output Software Control Register
0x94
32
read-write
n
0x0
0x0
CH0SWCV
Channel 0 Software Output Control Value
8
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH0SWEN
Channel 0 Software Output Control Enable
0
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH1SWCV
Channel 1 Software Output Control Value
9
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH1SWEN
Channel 1 Software Output Control Enable
1
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH2SWCV
Channel 2 Software Output Control Value
10
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH2SWEN
Channel 2 Software Output Control Enable
2
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH3SWCV
Channel 3 Software Output Control Value
11
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH3SWEN
Channel 3 Software Output Control Enable
3
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH4SWCV
Channel 4 Software Output Control Value
12
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH4SWEN
Channel 4 Software Output Control Enable
4
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH5SWCV
Channel 5 Software Output Control Value
13
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH5SWEN
Channel 5 Software Output Control Enable
5
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH6SWCV
Channel 6 Software Output Control Value
14
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH6SWEN
Channel 6 Software Output Control Enable
6
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH7SWCV
Channel 7 Software Output Control Value
15
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH7SWEN
Channel 7 Software Output Control Enable
7
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CNT
PWM Counter Current Count Value
0x4
32
read-write
n
0x0
0x0
COUNT
Current Counter Value
0
16
read-write
CNTIN
Counter Initial Value
0x4C
32
read-write
n
0x0
0x0
CNTINIT
no description available
0
16
read-write
CONF
Configuration
0x84
32
read-write
n
0x0
0x0
CNTOFNUM
Count Overflow Flag Number
0
7
read-write
EVENT0PSC
Channel0 input event prescaler
16
2
read-write
00
Event divided by 1
#00
01
Event divided by 2
#01
10
Event divided by 4
#10
11
Event divided by 8
#11
EVENT1PSC
Channel1 input event prescaler
18
2
read-write
00
Event divided by 1
#00
01
Event divided by 2
#01
10
Event divided by 4
#10
11
Event divided by 8
#11
EVENT2PSC
Channel2 input event prescaler
20
2
read-write
00
Event divided by 1
#00
01
Event divided by 2
#01
10
Event divided by 4
#10
11
Event divided by 8
#11
EVENT3PSC
Channel3 input event prescaler
22
2
read-write
00
Event divided by 1
#00
01
Event divided by 2
#01
10
Event divided by 4
#10
11
Event divided by 8
#11
EVENT4PSC
Channel4 input event prescaler
24
2
read-write
00
Event divided by 1
#00
01
Event divided by 2
#01
10
Event divided by 4
#10
11
Event divided by 8
#11
EVENT5PSC
Channel5 input event prescaler
26
2
read-write
00
Event divided by 1
#00
01
Event divided by 2
#01
10
Event divided by 4
#10
11
Event divided by 8
#11
EVENT6PSC
Channel6 input event prescaler
28
2
read-write
00
Event divided by 1
#00
01
Event divided by 2
#01
10
Event divided by 4
#10
11
Event divided by 8
#11
EVENT7PSC
Channel7 input event prescaler
30
2
read-write
00
Event divided by 1
#00
01
Event divided by 2
#01
10
Event divided by 4
#10
11
Event divided by 8
#11
GTBEEN
Global Time Base Enable
9
1
read-write
0
Global time base is disabled
#0
1
Global time base is enabled
#1
GTBEOUT
Global Time Base Output
10
1
read-write
0
Global time base signal generation is disabled
#0
1
Global time base signal generation is enabled
#1
DTSET
Deadtime Setting Register
0x68
32
read-write
n
0x0
0x0
DTPSC
Deadtime Prescaler Control Value
6
2
read-write
0x
Divide the system clock by 1.
#0x
10
Divide the system clock by 4.
#10
11
Divide the system clock by 16.
#11
DTVAL
Deadtime Value
0
6
read-write
EXTTRIG
PWM External Trigger
0x6C
32
read-write
n
0x0
0x0
CH0TRIG
Channel 0 Trigger Enable
0
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH1TRIG
Channel 1 Trigger Enable
1
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH2TRIG
Channel 2 Trigger Enable
2
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH3TRIG
Channel 3 Trigger Enable
3
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH4TRIG
Channel 4 Trigger Enable
4
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH5TRIG
Channel 5 Trigger Enable
5
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH6TRIG
Channel 6 Trigger Enable
6
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH7TRIG
Channel 7 Trigger Enable
7
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
INITTRIGEN
Initialization Trigger Enable
8
1
read-write
0
The generation of initialization trigger is disabled.
#0
1
The generation of initialization trigger is enabled.
#1
TRIGF
Channel Trigger Flag
9
1
read-only
0
No channel trigger was generated.
#0
1
A channel trigger was generated.
#1
FDSR
Fault Detect Status Register
0x74
32
read-write
n
0x0
0x0
FAULTDF
Fault Detection Flag
7
1
read-only
0
No fault condition was detected.
#0
1
A fault condition was detected.
#1
FAULTDF0
Fault Detection Flag 0
0
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTDF1
Fault Detection Flag 1
1
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTDF2
Fault Detection Flag 2
2
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTIN
Fault Inputs
5
1
read-only
0
The logic OR of the enabled fault inputs is 0.
#0
1
The logic OR of the enabled fault inputs is 1.
#1
WPEN
Write Protection Enable
6
1
read-write
0
Write protection is disabled. Write protected bits can be written.
#0
1
Write protection is enabled. Write protected bits cannot be written.
#1
FFAFER
Fault Filter and Fault Enable Register
0x7C
32
read-write
n
0x0
0x0
FER0EN
Fault Input 0 Enable
0
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FER1EN
Fault Input 1 Enable
1
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FER2EN
Fault Input 2 Enable
2
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FF0EN
Fault Input 0 Filter Enable
4
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FF1EN
Fault Input 1 Filter Enable
5
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FF2EN
Fault Input 2 Filter Enable
6
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFVAL
Fault Input Filter
8
8
read-write
FLTPOL
PWM Fault Input Polarity
0x88
32
read-write
n
0x0
0x0
FLT0POL
Fault Input 0 Polarity
0
1
read-write
0
The fault input polarity is active high
#0
1
The fault input polarity is active low
#1
FLT1POL
Fault Input 1 Polarity
1
1
read-write
0
The fault input polarity is active high
#0
1
The fault input polarity is active low
#1
FLT2POL
Fault Input 2 Polarity
2
1
read-write
0
The fault input polarity is active high
#0
1
The fault input polarity is active low
#1
FUNCSEL
PWM Features(Functions) Mode Selection Register
0x54
32
read-write
n
0x0
0x0
FAULTIE
Fault Interrupt Enable
7
1
read-write
0
Fault control interrupt is disabled.
#0
1
Fault control interrupt is enabled.
#1
FAULTMODE
Fault Control Mode
5
2
read-write
00
Fault control is disabled for all channels.
#00
01
Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
#01
10
Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
#10
11
Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
#11
INIT
Initialize The Channels Output
1
1
read-write
PWMSYNC
PWM Synchronization Mode
3
1
read-write
0
No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and PWM counter synchronization.
#0
1
Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and PWM counter synchronization.
#1
PWMSYNCEN
PWM Synchronization functio Enable
0
1
read-write
WPDIS
Write Protection Enable Register
2
1
read-write
0
Write protection is enabled.
#0
1
Write protection is disabled.
#1
INIT
PWM Initialize, Include Clock and Prescale Setting
0x0
32
read-write
n
0x0
0x0
CLKPSC
Prescale Factor Selection
8
16
read-write
CLKSRC
Clock Source Selection
3
2
read-write
00
No clock selected. This in effect disables the PWM counter.
#00
01
APB clock
#01
10
HSI clock
#10
CNTMODE
PWM Counter Mode Select
5
1
read-write
0
Up Counting mode
#0
1
Up-Down Counting mode
#1
CNTOF
PWM Counter Overflow Flag
7
1
read-write
0
PWM counter has not overflowed.
#0
1
PWM counter has overflowed.
#1
CNTOIE
PWM Counter Overflow Interrupt Enable
6
1
read-write
0
Disable CNTOF interrupts. Use software polling.
#0
1
Enable CNTOF interrupts. An interrupt is generated when CNTOF equals one.
#1
INVCR
PWM Inverse Control Register
0x90
32
read-write
n
0x0
0x0
PAIR0INVEN
Pair Channels 0 Inverting Enable
0
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
PAIR1INVEN
Pair Channels 1 Inverting Enable
1
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
PAIR2INVEN
Pair Channels 2 Inverting Enable
2
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
PAIR3INVEN
Pair Channels 3 Inverting Enable
3
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
MCVR
PWM Counter Max Count Value Register
0x8
32
read-write
n
0x0
0x0
MCVR
Counter Max Count Value
0
16
read-write
MODESEL
PWM Function Mode Selection
0x64
32
read-write
n
0x0
0x0
PAIR0COMBINEN
Combine Channels For Pair0
0
1
read-write
0
Channels 0 and 1 are independent.
#0
1
Channels 0 and 1 are combined.
#1
PAIR0COMPEN
Complement Channels for Pair0
1
1
read-write
0
The channel 1 output is the same as the channel 0 output.
#0
1
The channel 1 output is the complement of the channel 0 output.
#1
PAIR0DECAP
Dual Edge Capture Mode Captures for Pair0
3
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
PAIR0DECAPEN
Dual Edge Capture Mode Enable for Pair0
2
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
PAIR0DTEN
Deadtime Enable for Pair0
4
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
PAIR0FAULTEN
Fault Control Enable for Pair0
6
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
PAIR0SYNCEN
Synchronization Enable for Pair0
5
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
PAIR1COMBINEN
Combine Channels For Pair1
8
1
read-write
0
Channels 2 and 3 are independent.
#0
1
Channels 2 and 3 are combined.
#1
PAIR1COMPEN
Complement Of Channel (n) For Pair1
9
1
read-write
0
The channel 3 output is the same as the channel 2 output.
#0
1
The channel 3 output is the complement of the channel 2 output.
#1
PAIR1DECAP
Dual Edge Capture Mode Captures For Pair1
11
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
PAIR1DECAPEN
Dual Edge Capture Mode Enable For Pair1
10
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
PAIR1DTEN
Deadtime Enable For Pair1
12
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
PAIR1FAULTEN
Fault Control Enable For Pair1
14
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
PAIR1SYNCEN
Synchronization Enable For Pair1
13
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
PAIR2COMBINEN
Combine Channels For Pair2
16
1
read-write
0
Channels 4 and 5 are independent.
#0
1
Channels 4 and 5 are combined.
#1
PAIR2COMPEN
Complement Of Channel (n) For Pair2
17
1
read-write
0
The channel 5 output is the same as the channel 4 output.
#0
1
The channel 5 output is the complement of the channel 4 output.
#1
PAIR2DECAP
Dual Edge Capture Mode Captures For Pair2
19
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
PAIR2DECAPEN
Dual Edge Capture Mode Enable For Pair2
18
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
PAIR2DTEN
Deadtime Enable For Pair2
20
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
PAIR2FAULTEN
Fault Control Enable For Pair2
22
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
PAIR2SYNCEN
Synchronization Enable For Pair2
21
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
PAIR3COMBINEN
Combine Channels For Pair3
24
1
read-write
0
Channels 6 and 7 are independent.
#0
1
Channels 6 and 7 are combined.
#1
PAIR3COMPEN
Complement Of Channel (n) For Pair3
25
1
read-write
0
The channel 7 output is the same as the channel 6 output.
#0
1
The channel 7 output is the complement of the channel 6 output.
#1
PAIR3DECAP
Dual Edge Capture Mode Captures For Pair3
27
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
PAIR3DECAPEN
Dual Edge Capture Mode Enable For Pair3
26
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
PAIR3DTEN
Deadtime Enable For Pair3
28
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
PAIR3FAULTEN
Fault Control Enable For Pair3
30
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
PAIR3SYNCEN
Synchronization Enable For Pair3
29
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
OMCR
Output Mask Control Register
0x60
32
read-write
n
0x0
0x0
CH0OMEN
Channel 0 Output Mask
0
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH1OMEN
Channel 1 Output Mask
1
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH2OMEN
Channel 2 Output Mask
2
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH3OMEN
Channel 3 Output Mask
3
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH4OMEN
Channel 4 Output Mask
4
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH5OMEN
Channel 5 Output Mask
5
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH6OMEN
Channel 6 Output Mask
6
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH7OMEN
Channel 7 Output Mask
7
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
OUTINIT
Initial Value For Channels Output
0x5C
32
read-write
n
0x0
0x0
CH0OIV
Channel 0 Output Initialization Value
0
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH1OIV
Channel 1 Output Initialization Value
1
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH2OIV
Channel 2 Output Initialization Value
2
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH3OIV
Channel 3 Output Initialization Value
3
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH4OIV
Channel 4 Output Initialization Value
4
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH5OIV
Channel 5 Output Initialization Value
5
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH6OIV
Channel 6 Output Initialization Value
6
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH7OIV
Channel 7 Output Initialization Value
7
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
QDI
Quadrature Decoder Interface Configuration Register
0x80
32
read-write
n
0x0
0x0
CNTOFDIR
Overflow Direction
1
1
read-only
0
Set on the bottom of counting
#0
1
Set on the top of counting
#1
PHAPOL
Phase A Input Polarity
5
1
read-write
0
Normal polarity
#0
1
Inverted polarity
#1
PHBPOL
Phase B Input Polarity
4
1
read-write
0
Normal polarity
#0
1
Inverted polarity
#1
QDIEN
Quadrature Decoder Mode Enable
0
1
read-write
0
Quadrature Decoder is Disable
#0
1
Quadrature Decoder is Enable
#1
QUADIR
Counting Direction
2
1
read-only
0
Counting direction is decreasing
#0
1
Counting direction is increasing
#1
QUADMODE
Quadrature Decoder Mode
3
1
read-write
0
Phase A and phase B encoding mode
#0
1
Count and direction encoding mode
#1
STR
Status Register
0x50
32
read-write
n
0x0
0x0
CH0SF
Channel 0 Status Flag
0
1
read-write
0
No channel event has occurred.
#0
1
Channel event has occurred.
#1
CH1SF
Channel 1 Status Flag
1
1
read-write
0
No channel event has occurred.
#0
1
Channel event has occurred.
#1
CH2SF
Channel 2 Status Flag
2
1
read-write
0
No channel event has occurred.
#0
1
Channel event has occurred.
#1
CH3SF
Channel 3 Status Flag
3
1
read-write
0
No channel event has occurred.
#0
1
Channel event has occurred.
#1
CH4SF
Channel 4 Status Flag
4
1
read-write
0
No channel event has occurred.
#0
1
Channel event has occurred.
#1
CH5SF
Channel 5 Status Flag
5
1
read-write
0
No channel event has occurred.
#0
1
Channel event has occurred.
#1
CH6SF
Channel 6 Status Flag
6
1
read-write
0
No channel event has occurred.
#0
1
Channel event has occurred.
#1
CH7SF
Channel 7 Status Flag
7
1
read-write
0
No channel event has occurred.
#0
1
Channel event has occurred.
#1
SYNC
Synchronization
0x58
32
read-write
n
0x0
0x0
MAXSYNCP
Maximum Loading Point Enable
1
1
read-write
0
The maximum loading point is disabled.
#0
1
The maximum loading point is enabled.
#1
MINSYNCP
Minimum Loading Point Enable
0
1
read-write
0
The minimum loading point is disabled.
#0
1
The minimum loading point is enabled.
#1
OMSYNCP
Output Mask Synchronization Point
3
1
read-write
0
OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
#0
1
OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
#1
SWSYNC
PWM Synchronization Software Trigger
7
1
read-write
0
Software trigger is not selected.
#0
1
Software trigger is selected.
#1
SYNCPOL
CHPOLR Register Synchronization
11
1
read-write
0
CHPOLR register is updated with its buffer value at all rising edges of system clock.
#0
1
CHPOLR register is updated with its buffer value by the PWM synchronization.
#1
TRIG0
PWM Synchronization Hardware Trigger 0
4
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
TRIG1
PWM Synchronization Hardware Trigger 1
5
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
TRIG2
PWM Synchronization Hardware Trigger 2
6
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
SYNCONF
Synchronization Configuration
0x8C
32
read-write
n
0x0
0x0
CNTINC
CNTIN Register Synchronization
2
1
read-write
0
CNTIN register is updated with its buffer value at all rising edges of system clock.
#0
1
CNTIN register is updated with its buffer value by the PWM synchronization.
#1
CNTVHWSYNC
no description available
16
1
read-write
0
A hardware trigger does not activate the PWM counter synchronization.
#0
1
A hardware trigger activates the PWM counter synchronization.
#1
CNTVSWSYNC
no description available
8
1
read-write
0
The software trigger does not activate the PWM counter synchronization.
#0
1
The software trigger activates the PWM counter synchronization.
#1
HWPOL
Channel POL synchronization is activeated by a hardwaretrigger
22
1
read-write
0
The hardware trigger does not activate the POL register synchronization.
#0
1
>The hardware trigger activates POL register synchronization.
#1
HWTRIGMODESEL
Hardware Trigger Mode
0
1
read-write
0
PWM clears the TRIGj bit when the hardware trigger j is detected
#0
1
PWM does not clear the TRIGj bit when the hardware trigger j is detected
#1
INVC
INVCTRL Register Synchronization
4
1
read-write
0
INVCTRL register is updated with its buffer value at all rising edges of system clock.
#0
1
INVCTRL register is updated with its buffer value by the PWM synchronization.
#1
INVHWSYNC
no description available
19
1
read-write
0
A hardware trigger does not activate the INVCTRL register synchronization.
#0
1
A hardware trigger activates the INVCTRL register synchronization.
#1
INVSWSYNC
no description available
11
1
read-write
0
The software trigger does not activate the INVCTRL register synchronization.
#0
1
The software trigger activates the INVCTRL register synchronization.
#1
OMVHWSYNC
no description available
18
1
read-write
0
A hardware trigger does not activate the OUTMASK register synchronization.
#0
1
A hardware trigger activates the OUTMASK register synchronization.
#1
OMVSWSYNC
no description available
10
1
read-write
0
The software trigger does not activate the OUTMASK register synchronization.
#0
1
The software trigger activates the OUTMASK register synchronization.
#1
PWMSVHWSYNC
no description available
17
1
read-write
0
A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
#0
1
A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
#1
PWMSVSWSYNC
no description available
9
1
read-write
0
The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
#0
1
The software trigger activates MOD, CNTIN, and CV registers synchronization.
#1
SWOC
SWOCTRL Register Synchronization
5
1
read-write
0
SWOCTRL register is updated with its buffer value at all rising edges of system clock.
#0
1
SWOCTRL register is updated with its buffer value by the PWM synchronization.
#1
SWPOL
Channel POL synchronization is activeated by a softwaretrigger
21
1
read-write
0
The software trigger does not activate the POL register synchronization.
#0
1
The software trigger activates POL register synchronization.
#1
SWVHWSYNC
no description available
20
1
read-write
0
A hardware trigger does not activate the SWOCTRL register synchronization.
#0
1
A hardware trigger activates the SWOCTRL register synchronization.
#1
SWVSWSYNC
no description available
12
1
read-write
0
The software trigger does not activate the SWOCTRL register synchronization.
#0
1
The software trigger activates the SWOCTRL register synchronization.
#1
SYNCMODE
Synchronization Mode
7
1
read-write
0
Legacy PWM synchronization is selected.
#0
1
Enhanced PWM synchronization is selected.
#1
RTC
Real-time counter
RTC
0x0
0x0
0x14
registers
n
RTC
RTC Interrupt
21
CNT
RTC Count Value
0x8
32
read-only
n
0x0
0x0
CNT
Count Value
0
32
read-only
MOD
RTC Modulo Value
0x4
32
read-write
n
0x0
0x0
MOD
Modulo Value
0
32
read-write
PS
RTC Prescaler Register
0xC
32
read-write
n
0x0
0x0
RTCPS
Prescale Value
0
20
read-write
PSCNT
RTC Prescaler Counter Register
0x10
32
read-only
n
0x0
0x0
PSCNT
Prescaler Counter Register
0
20
read-only
SC
RTC Status and Control Register
0x0
32
read-write
n
0x0
0x0
RPIE
RTC Prescaler Interrupt Enable
16
1
read-write
RPIF
RTC Prescaler Interrupt Flag
17
1
read-write
RTCLKS
RTC Clock Source Select
14
2
read-write
00
Bus Clock
#00
01
Interval 32KHz
#01
10
External XOSC
#10
11
External Pin In
#11
RTCO
RTC Counter Output Enable
4
1
read-write
RTIE
RTC Interrupt Enable
6
1
read-write
RTIF
RTC Interrupt Flag
7
1
read-write
SPI0
Serial Peripheral Interface
SPI
0x0
0x0
0x18
registers
n
SPI0
SPI0 interrupt
9
CFG0
SPI Configuration Register 0
0x0
32
read-write
n
0x0
0x0
CS_HOLD
CS hold count
16
8
read-write
CS_SETUP
CS Setup Count
24
8
read-write
SCK_HIGH
SCK High Count
0
8
read-write
SCK_LOW
SCK low count
8
8
read-write
CFG1
SPI Configuration Register 1
0x4
32
read-write
n
0x0
0x0
CONT_CS
CS continuous output enable
28
1
read-write
CPHA
clock phase
17
1
read-write
CPHA_0
the second SCK transition is the first data capture edge
0
CPHA_1
the first SCK transition is the first data capture edge
1
CPOL
clock polarity
16
1
read-write
CPOL_0
SCK is 0 when idle
0
CPOL_1
SCK is 1 when idle
1
CSOE
CS hardware output enable
25
1
read-write
CS_IDLE
CS idle count
0
8
read-write
DMARXEN
DMA RX channel enable
15
1
read-write
DMATXEN
DMA TX channel enable
14
1
read-write
FRMSIZE
frame size
20
4
read-write
4BIT
Frame size is 4 bits
#0000
4BIT
Frame size is 4 bits
#0001
4BIT
Frame size is 4 bits
#0010
4BIT
Frame size is 4 bits
#0011
5BIT
Frame size is 5 bits
#0100
6BIT
Frame size is 6 bits
#0101
7BIT
Frame size is 7 bits
#0110
8BIT
Frame size is 8 bits
#0111
9BIT
Frame size is 9 bits
#1000
10BIT
Frame size is 10 bits
#1001
11BIT
Frame size is 11 bits
#1010
12BIT
Frame size is 12 bits
#1011
13BIT
Frame size is 13 bits
#1100
14BIT
Frame size is 14 bits
#1101
15BIT
Frame size is 15 bits
#1110
16BIT
Frame size is 16 bits
#1111
MODFEN
mode fault detect enable
26
1
read-write
MODFIE
mode fault interrupt enable
13
1
read-write
MSBF
TX MSB first Select
18
1
read-write
MSTR
master/slave mode selection
12
1
read-write
SLAVE
SPI slave mode
0
MASTER
SPI master mode
1
RMSBF
RX MSB first Select
19
1
read-write
RXFIE
RX buffer full interrupt enable
9
1
read-write
RXOIE
RX buffer overflow interrupt enable
11
1
read-write
TXEIE
TX buffer empty interrupt enable
8
1
read-write
TXUIE
TX buffer underflow interrupt enable
10
1
read-write
WKUEN
wake up function enable(only valid for slave mode)
30
1
read-write
CFG2
SPI configuration register 2
0x14
32
read-write
n
0x0
0x0
MNOV
Master No Overflow mode enable bit
1
1
read-write
ROEN
RX only mode enable bit
3
1
read-write
TOEN
TX only mode enable bit
2
1
read-write
CMD
SPI Command Register
0x8
32
read-write
n
0x0
0x0
CSRLS
CS release(only valid for CS continuous output)
5
1
read-write
ROTRIG
Master RX only mode edge
6
1
read-write
SPIEN
SPI Enable
0
1
read-write
SWRST
software reset
4
1
read-write
DATA
SPI Data Register
0x10
32
read-write
n
0x0
0x0
DATA
Data
0
16
read-write
STATUS
SPI Status Register
0xC
32
read-write
n
0x0
0x0
IDLEF
SPI IDLE flag
8
1
read-write
MEBY
SPI master engine busy flag
7
1
read-write
MODEF
Mode error flag
4
1
read-write
RXFF
RX buffer Full flag
1
1
read-write
RXOF
RX buffer overflow flag
3
1
read-write
TXEF
TX buffer empty flag
0
1
read-write
TXUF
TX buffer underflow flag
2
1
read-write
SPM
System Power Manage
SPM
0x0
0x0
0x18
registers
n
SPM
SPM interrupt
23
EN_PERIPH_SLEEP_ACK
Enable Periph Sleep Ack
0x10
32
read-write
n
0x0
0x0
ACMP0
Enable ACMP0 Sleep ack
0
1
read-write
0
Disable
#0
1
Enable
#1
ADC0
Enable ADC0 Sleep ACK
16
1
read-write
0
Disable
#0
1
Enable
#1
CAN0
Enable CAN0 Sleep ACK
7
1
read-write
0
Disable
#0
1
Enable
#1
DMA0
Enable DMA0 Sleep ACK
15
1
read-write
0
Disable
#0
1
Enable
#1
EFLASH
Enable Flash Sleep ACK
18
1
read-write
0
Disable
#0
1
Enable
#1
I2C0
Enable I2C0 Sleep ACK
2
1
read-write
0
Disable
#0
1
Enable
#1
I2C1
Enable I2C1 Sleep ACK
3
1
read-write
0
Disable
#0
1
Enable
#1
SPI0
Enable SPI0 Sleep ACK
4
1
read-write
0
Disable
#0
1
Enable
#1
SPI1
Enable SPI1 Sleep ACK
5
1
read-write
0
Disable
#0
1
Enable
#1
UART0
Enable UART0 Sleep ACK
9
1
read-write
0
Disable
#0
1
Enable
#1
UART1
Enable UART1 Sleep ACK
10
1
read-write
0
Disable
#0
1
Enable
#1
UART2
Enable UART2 Sleep ACK
11
1
read-write
0
Disable
#0
1
Enable
#1
EN_PERIPH_WAKEUP
Enable Periph Sleep Ack
0x14
32
read-write
n
0x0
0x0
ACMP0
Enable ACMP0 Wakeup
0
1
read-write
0
Disable
#0
1
Enable
#1
ADC0
Enable ADC0 Wakeup
16
1
read-write
0
Disable
#0
1
Enable
#1
CAN0
Enable CAN0 Wakeup
7
1
read-write
0
Disable
#0
1
Enable
#1
GPIO
Enable GPIO Wakeup
17
1
read-write
0
Disable
#0
1
Enable
#1
I2C0
Enable I2C0 Wakeup
2
1
read-write
0
Disable
#0
1
Enable
#1
I2C1
Enable I2C1 Wakeup
3
1
read-write
0
Disable
#0
1
Enable
#1
NMI
Enable NMI Wakeup
18
1
read-write
0
Disable
#0
1
Enable
#1
PVD
Enable PVD Wakeup
19
1
read-write
0
Disable
#0
1
Enable
#1
RTC
Enable RTC Wakeup
15
1
read-write
0
Disable
#0
1
Enable
#1
SPI0
Enable SPI0 Wakeup
4
1
read-write
0
Disable
#0
1
Enable
#1
SPI1
Enable SPI1 Wakeup
5
1
read-write
0
Disable
#0
1
Enable
#1
UART0
Enable UART0 Wakeup
9
1
read-write
0
Disable
#0
1
Enable
#1
UART1
Enable UART1 Wakeup
10
1
read-write
0
Disable
#0
1
Enable
#1
UART2
Enable UART2 Wakeup
11
1
read-write
0
Disable
#0
1
Enable
#1
PERIPH_SLEEP_ACK_STATUS
Periph Sleep Ack Status Set
0xC
32
read-only
n
0x0
0x0
ACMP0
ACMP0 Sleep ACK Status
0
1
read-only
0
No ACK
#0
1
ACK
#1
ADC0
ADC0 Sleep ACK Status
16
1
read-only
0
No ACK
#0
1
ACK
#1
CAN0
CAN0 Sleep ACK Status
7
1
read-only
0
No ACK
#0
1
ACK
#1
DMA0
DMA0 Sleep ACK Status
15
1
read-only
0
No ACK
#0
1
ACK
#1
EFLASH
Flash Idle Status
18
1
read-only
0
Busy
#0
1
Idle
#1
I2C0
I2C0 Sleep ACK Status
2
1
read-only
0
No ACK
#0
1
ACK
#1
I2C1
I2C1 Sleep ACK Status
3
1
read-only
0
No ACK
#0
1
ACK
#1
SPI0
SPI0 Sleep ACK Status
4
1
read-only
0
No ACK
#0
1
ACK
#1
SPI1
SPI1 Sleep ACK Status
5
1
read-only
0
No ACK
#0
1
ACK
#1
UART0
UART0 Sleep ACK Status
9
1
read-only
0
No ACK
#0
1
ACK
#1
UART1
UART1 Sleep ACK Status
10
1
read-only
0
No ACK
#0
1
ACK
#1
UART2
UART2 Sleep ACK Status
11
1
read-only
0
No ACK
#0
1
ACK
#1
PWR_MGR_CFG0
Power Manage Config Register 0
0x0
32
read-write
n
0x0
0x0
EN_CAN0_FILTER
Enable CAN0 Filter Interrupt Wakeup
5
1
read-write
0
Disable
#0
1
Enable
#1
EN_DPWRLVD
Enable Low Voltage Detect Power
3
1
read-write
0
Disable
#0
1
Enable
#1
EN_FAST_BOOT
Enable Fast Boot Mode
1
1
read-write
0
Dsable
#0
1
Enable
#1
EN_IO_SUS
Enable IO Suspend In Stop Mode
7
1
read-write
0
IO Keep Status
#0
1
IO Change To Suspend
#1
EN_LVD
Enable Low Voltage Detect Function
4
1
read-write
0
Disable
#0
1
Enable
#1
EN_PVD
Enable Programmable Voltage Detect
2
1
read-write
0
Disable
#0
1
Enable
#1
PWR_EN
SPM Power Control Enable
0
1
read-write
0
Disable
#0
1
Enable
#1
SLEEP_MODE
Mcu Sleep Mode
8
2
read-write
00
Stop Mode 0
#00
01
Stop Mode 1
#01
10
Standby Mode
#10
PWR_MGR_CFG1
Power Manage Config Register 1
0x4
32
read-write
n
0x0
0x0
PORLPVD
PVDLVD Level Set
0
4
read-write
0010
VLVDL=2.65V VPVDL=2.9V
#0010
1010
VLVDL=4.3V VPVDL=4.6V
#1010
SYSPLL_ON
System PLL Enable
27
1
read-write
0
Disable PLL
#0
1
Enable PLL
#1
SYSPLL_RDY
System PLL Ready Flag
30
1
read-only
0
Not Ready
#0
1
Ready
#1
XOSC_HSEBYP
Extern High-Speed Clock Bypass
28
1
read-write
0
Disable XOSC HSE Bypass
#0
1
Enable XOSC HSE Bypass
#1
XOSC_HSEON
Extern High-Speed Clock Enable
29
1
read-write
0
Disable XOSC HSE
#0
1
Enable XOSC HSE
#1
XOSC_RDY
XOSC Clock Ready Flag
31
1
read-only
0
Not Ready
#0
1
Ready
#1
WAKEUP_IRQ_STATUS
SPM Wakeup IRQ Status
0x1C
32
read-write
n
0x0
0x0
ACMP0
ACMP0 Wakeup Flag
0
1
read-only
0
Invalid
#0
1
Valid
#1
ADC0
ADC0 Wakeup Flag
16
1
read-only
0
Invalid
#0
1
Valid
#1
CAN0
CAN0 Wakeup Flag
7
1
read-only
0
Invalid
#0
1
Valid
#1
DMA0
DMA0 Wakeup Flag
15
1
read-only
0
Invalid
#0
1
Valid
#1
GPIO
GPIO Wakeup fLAG
17
1
read-only
0
Invalid
#0
1
Valid
#1
I2C0
I2C0 Wakeup Flag
2
1
read-only
0
Invalid
#0
1
Valid
#1
I2C1
I2C1 Wakeup Flag
3
1
read-only
0
Invalid
#0
1
Valid
#1
NMI
NMI Wakeup fLAG
18
1
read-only
0
Invalid
#0
1
Valid
#1
OVER_COUNT
SPM Overcount Wakeup fLAG
20
1
read-only
0
Invalid
#0
1
Valid
#1
PVD
PVD Wakeup fLAG
19
1
read-only
0
Invalid
#0
1
Valid
#1
SPI0
SPI0 Wakeup Flag
4
1
read-only
0
Invalid
#0
1
Valid
#1
SPI1
SPI1 Wakeup Flag
5
1
read-only
0
Invalid
#0
1
Valid
#1
UART0
UART0 Wakeup Flag
9
1
read-only
0
Invalid
#0
1
Valid
#1
UART1
UART1 Wakeup Flag
10
1
read-only
0
Invalid
#0
1
Valid
#1
UART2
UART2 Wakeup Flag
11
1
read-only
0
Invalid
#0
1
Valid
#1
TIMER_CHANNEL0
Timer channel
TIMER_CHANNEL0
0x0
0x0
0x10
registers
n
TIMER_CHANNEL0
TIMER channel 0 interrupt
17
CVAL
Timer Current Count Value Register
0x4
32
read-only
n
0x0
0x0
CVAL
Timer Current Count Value
0
32
read-only
INIT
Timer Initialize Control Register
0x8
32
read-write
n
0x0
0x0
LINKEN
Timer Link Mode Enable
2
1
read-write
0
Timer is not linked,Timer is seperated
#0
1
Timer is Linked to previous timer
#1
TEN
Timer Channel Enable
0
1
read-write
0
Timer channel disabled
#0
1
Timer channel enabled
#1
TIE
Timer Channel Interrupt Enable
1
1
read-write
0
Interrupt disabled
#0
1
Interrupt enabled
#1
LDVAL
Timer Load Value Register
0x0
32
read-write
n
0x0
0x0
LDVAL
Timer Load Value
0
32
read-write
TF
Timer Flag Register
0xC
32
read-write
n
0x0
0x0
TFLG
Timer Status Flag
0
1
read-write
0
Timeout has not yet occurred
#0
1
Timeout has occurred
#1
TIMER_CTRL
Timer Control
TIMER_CTRL
0x0
0x0
0x100
registers
n
MCR
Timer Module Control Regitser
0x0
32
read-write
n
0x0
0x0
MDIS
Timers Module Disable
1
1
read-write
0
Timers enabled
#0
1
Timers disabled
#1
UART0
Universal Asynchronous Receiver/Transmitter
UART0
0x0
0x0
0x60
registers
n
UART0
UART0 interrupt
5
BRKLGH
LIN Break Length Select Register
0x60
32
read-write
n
0x0
0x0
BRKLGH
Break length
0
4
read-write
CNTR
Uart Counter time delay in RS485 mode
0x54
32
read-write
n
0x0
0x0
CNTR
Uart Counter time delay in RS485 mode
0
8
read-write
DIV_FRAC
Uart Fractional Divider Address
0x44
32
read-write
n
0x0
0x0
DIV_FRAC
uart fractional divider
0
8
read-write
DIV_H
Divisor high 8 bits register
0x8
32
read-write
n
0x0
0x0
DIV_H
uart baud rate divisor high 8 bits
0
8
read-write
DIV_L
Divisor low 8 bits register
0x4
32
read-write
n
0x0
0x0
DIV_L
uart baud rate divisor low 8 bits
0
8
read-write
DMA_EN
uart DMA enable register
0x40
32
read-write
n
0x0
0x0
RX_DMA_EN
uart RX DMA enable bit
0
1
read-write
TX_DMA_EN
uart TX DMA enable bit
1
1
read-write
EFR
hardware flow control register
0x18
32
read-write
n
0x0
0x0
CTS
hardware transmiison flow control enable/disable bit
7
1
read-write
RTS
hardware reception flow control enable/disable bit
6
1
read-write
FCR
FIFO Control Register
0x14
32
read-write
n
0x0
0x0
FIFOE
RX and TX FIFO enable/disable bit
0
1
read-write
GUARD
uart guard time register
0x34
32
read-write
n
0x0
0x0
GUARD_CNT
Guard interval count value
0
4
read-write
GUARD_EN
Guard interval time added enabling signal
4
1
read-write
IDLE
Uart IDLE register
0x58
32
read-write
n
0x0
0x0
IDLEIE
IDLE interrupt enable bit
4
1
read-write
ILEN
Bus idle detect enable/disable
7
1
read-write
IER
Interrupt Enable register
0x1C
32
read-write
n
0x0
0x0
EDCTS
CTS_n changing interrupt enable bit
7
1
read-write
EFE
overflow or frame error interrupt enable bit
4
1
read-write
ENE
noise error interrupt enable bit
5
1
read-write
EOEBI
overflow error or break error interrupt enable bit
6
1
read-write
EPE
parity error interrupt enable bit
3
1
read-write
ERXNE
receiving data not empty interrupt enable bit
0
1
read-write
ETC
transmitting completed interrupt enable bit
2
1
read-write
ETXDF
TX register or TX FIFO full interrupt enable bit
8
1
read-write
ETXE
transmitting data empty interrupt enable bit
1
1
read-write
LCR0
uart control register 0
0xC
32
read-write
n
0x0
0x0
EPS
odd/eveen number select bit
4
1
read-write
PEN
uart parity enable/disable bit
3
1
read-write
SP
stick parity
5
1
read-write
STB
Number of STOP bits
2
1
read-write
SUB
Sets up break
6
1
read-write
WLS1_WLS0
uart data mode select bits
0
2
read-write
5_BIT
5 BITS
#00
6_BIT
6 BITS
#01
7_BIT
7 BITS
#10
8_BIT
8 BITS
#11
LCR1
uart control register 1
0x10
32
read-write
n
0x0
0x0
INVRX
uart rx input inverse enable/disable bit
6
1
read-write
INVTX
uart tx output inverse enable/disable bit
7
1
read-write
LOOP
uart loop back mode enable
4
1
read-write
RXEN
uart receiver enable
0
1
read-write
TXEN
uart Transmitter enable
1
1
read-write
WLS2
uart 9 bit data mode enable/disable bit
5
1
read-write
LINCR
LIN Control register
0x5C
32
read-write
n
0x0
0x0
BRKWAKIE
Break wakeup interrupt enable/disable
1
1
read-write
LABAUDEN
0x55 used as automatic baudrate detection enable/disable
3
1
read-write
LBRKDL
Lin break length detection interrupt enable/disable
5
1
read-write
LBRKIE
Lin break byte detection interrupt enable/disable
6
1
read-write
LINEN
Lin mode interrupt enable/disable
7
1
read-write
SDBRK
Lin mode transfer 13 zero enable/disable
4
1
read-write
SYNERRIE
Synch byte error interrupt enable/disable
2
1
read-write
LSR0
Line Status Register 0
0x20
32
read-write
n
0x0
0x0
BI
break error flag
4
1
read-write
DR
Data ready flag
0
1
read-write
FE
frame error flag
3
1
read-write
NE
noise error flag
7
1
read-write
OE
overrun error flag
1
1
read-write
PE
parity error flag
2
1
read-write
TC
Transmitting finished flag
6
1
read-write
THRE
TX holding register or TX FIFO empty flag
5
1
read-write
TXDF
TX register or TX FIFO full flag
8
1
read-write
LSR1
Line Status Register 1
0x24
32
read-write
n
0x0
0x0
BRKWAK
LIN BREAK wakeup flag
4
1
read-write
CTS
Hardware flow status - CTS
6
1
read-write
DCTS
Pin CTS_n signal changing flag
3
1
read-write
FBRK
LIN break occurrer flag
2
1
read-write
IDLE
IDLE flag
0
1
read-write
RTS
Hardware flow status - RTS
7
1
read-write
SYNERR
SYNERR flag
1
1
read-write
UART_IDLE
UART IDLE
5
1
read-write
RBR
RX/TX Data Register
0x0
32
read-write
n
0x0
0x0
RBR_THR
RX/TX Data Register
0
9
read-write
RS485CR
Uart RS485 control register
0x4C
32
read-write
n
0x0
0x0
DLYEN
Delay insert between the last stop bit and rts_n or dtr_n de-assertion
4
1
read-write
INVPOL
inverse the polarity of rts_n
5
1
read-write
RS485EN
RS485 mode enable bit
7
1
read-write
SLEEP_EN
uart sleep enable register
0x3C
32
read-write
n
0x0
0x0
SLEEP_EN
uart sleep function enable bit
0
1
read-write
SMP_CNT
uart sample counter register
0x28
32
read-write
n
0x0
0x0
SMP_CNT
uart sample counter
0
2
read-write
WDG
Watchdog
WDG
0x0
0x0
0x14
registers
n
WDG
WDG interrupt
8
CNT
Watchdog Counter Value
0x8
32
read-write
n
0x0
0x0
CNT
Counter Value
0
32
read-write
CS0
Watchdog Control and Status Register 0
0x0
32
read-write
n
0x0
0x0
EN
Watchdog Enable
7
1
read-write
0
Watchdog disabled.
#0
1
Watchdog enabled.
#1
INT
Watchdog Interrupt Enable
6
1
read-write
0
Watchdog interrupts are disabled. Watchdog resets are not delayed.
#0
1
Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks.
#1
UPDATE
Allow Updates WDG Config
5
1
read-write
0
Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
#0
1
Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.
#1
CS1
Watchdog Control and Status Register 1
0x4
32
read-write
n
0x0
0x0
CLK
Watchdog Clock Source
0
2
read-write
00
Bus clock
#00
01
Internal 32Khz LPOSC
#01
10
Internal 8Mhz LFOSC
#10
11
External XOSC
#11
FLG
Watchdog Interrupt Flag
6
1
read-write
0
No interrupt occurred.
#0
1
An interrupt occurred.
#1
PRES
Watchdog Prescalar
4
1
read-write
0
256 prescalar disabled.
#0
1
256 prescalar enabled.
#1
WIN
Watchdog Window
7
1
read-write
0
Window mode disabled.
#0
1
Window mode enabled.
#1
TOVAL
Watchdog Timeout Value Register
0xC
32
read-write
n
0x0
0x0
TOVAL
Timeout Value
0
32
read-write
WIN
Watchdog Window Register
0x10
32
read-write
n
0x0
0x0
WIN
Window Value
0
32
read-write