AutoChips AC78xx 2024.04.26 ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 100 MHz. CM3 r2p1 little true 3 false 8 32 ACMP0 Analog comparator ACMP 0x0 0x0 0x30 registers n ACMP0_ 45 CR0 ACMP0 Configuration Register 0 0x0 32 read-write n 0x0 0x0 EN Analog Comparator Enable 7 1 read-write 0 The ACMP is disabled. #0 1 The ACMP is enabled. #1 HYST Analog Comparator Hysterisis Selection 6 1 read-write 0 20 mV. #0 1 30 mV. #1 IE ACMP0 Interrupt Enable 4 1 read-write 0 Disable the ACMP Interrupt. #0 1 Enable the ACMP Interrupt. #1 MOD ACMP0 sensitivity modes of the interrupt trigger 0 2 read-write 00 ACMP0 interrupt on output falling edge. #00 01 ACMP0 interrupt on output rising edge. #01 10 ACMP0 interrupt on output falling edge. #10 11 ACMP0 interrupt on output falling or rising edge. #11 OPE ACMP0 hall output Enable 2 1 read-write 0 ACMP0 hall output Disabled. #0 1 ACMP0 hall output enabled. #1 CR1 ACMP Configuration Register 1 0x4 32 read-write n 0x0 0x0 NSEL ACMP0 Negative Input Select 0 3 read-write 000 External input 0 #000 001 External input 1 #001 010 External input 2 #010 011 External input 3 #011 100 External input 4 #100 101 DAC0 Output #101 110 ACMP0 output tie 0 #110 111 ACMP0 output tie 0 #111 PSEL ACMP0 Positive Input Select 4 3 read-write 000 External input 0 #000 001 External input 1 #001 010 External input 2 #010 011 External input 3 #011 100 External input 4 #100 101 DAC0 Output #101 110 ACMP0 output tie 0 #110 111 ACMP0 output tie 0 #111 CR2 ACMP0 configuration register 2 0x8 32 read-write n 0x0 0x0 DACEN DAC Enable 7 1 read-write 0 The DAC0 is disabled. #0 1 The DAC0 is enabled. #1 VAL DAC0 Output Level Selection 0 6 read-write CR3 ACMP0 configuration register 3 0xC 32 read-write n 0x0 0x0 NSPLEN ACMP0 negative input polling mode enable 3 1 read-write 0 ACMP0 negative input polling mode disabled #0 1 ACMP0 negative input polling mode enabled #1 PSPLEN ACMP0 positive input polling mode enable 7 1 read-write 0 ACMP0 positive input polling mode disabled #0 1 ACMP0 positive input polling mode enabled #1 CR4 ACMP0 configuration register 4 0x10 32 read-write n 0x0 0x0 PLSEQ ACMP0 polling channel sequence set 0 6 read-write DACSR ACMP DAC reference select register 0x2C 32 read-write n 0x0 0x0 DACREF ACMP DAC reference select 0 1 read-write 0 DAC selects bandgap as reference #0 1 DAC selects Vdd as reference #1 DR ACMP0 data output register 0 0x14 32 read-write n 0x0 0x0 O ACMP0 normal mode output 7 1 read-write O0 ACMP0 polling mode channel 0 output 0 1 read-write O1 ACMP0 polling mode channel 1 output 1 1 read-write O2 ACMP0 polling mode channel 2 output 2 1 read-write O3 ACMP0 polling mode channel 3 output 3 1 read-write O4 ACMP0 polling mode channel 4 output 4 1 read-write O5 ACMP0 polling mode channel 5 output 5 1 read-write FD ACMP0 polling frequency divider register 0x1C 32 read-write n 0x0 0x0 PLFD ACMP0 polling mode frequency divider 0 2 read-write 00 source_clk/256 #00 01 source_clk/100 #01 10 source_clk/70 #10 11 source_clk/50 #11 OPA ACMP0 hall output A set register 0x20 32 read-write n 0x0 0x0 OPASEL ACMP0 Hall output A set 0 3 read-write 000 polling channel 0 #000 001 polling channel 1 #001 010 polling channel 2 #010 011 polling channel 3 #011 100 polling channel 4 #100 101 polling channel 5 #101 110 ACMP0 output tie 0 #110 111 ACMP0 output tie 0 #111 OPB ACMP0 hall output B set register 0x24 32 read-write n 0x0 0x0 OPBSEL ACMP0 Hall output B set 0 3 read-write 000 polling channel 0 #000 001 polling channel 1 #001 010 polling channel 2 #010 011 polling channel 3 #011 100 polling channel 4 #100 101 polling channel 5 #101 110 ACMP0 output tie 0 #110 111 ACMP0 output tie 0 #111 OPC ACMP0 hall output C set register 0x28 32 read-write n 0x0 0x0 OPCSEL ACMP0 Hall output C set 0 3 read-write 000 polling channel 0 #000 001 polling channel 1 #001 010 polling channel 2 #010 011 polling channel 3 #011 100 polling channel 4 #100 101 polling channel 5 #101 110 ACMP0 output tie 0 #110 111 ACMP0 output tie 0 #111 SR ACMP0 status register 0 0x18 32 read-write n 0x0 0x0 F ACMP0 normal mode interrupt flag 7 1 read-write F0 ACMP0 polling mode channel 0 interrupt flag 0 1 read-write F1 ACMP0 polling mode channel 1 interrupt flag 1 1 read-write F2 ACMP0 polling mode channel 2 interrupt flag 2 1 read-write F3 ACMP0 polling mode channel 3 interrupt flag 3 1 read-write F4 ACMP0 polling mode channel 4 interrupt flag 4 1 read-write F5 ACMP0 polling mode channel 5 interrupt flag 5 1 read-write WPF ACMP0 low power mode wakeup interrupt flag 6 1 read-write ACMP1 Analog comparator ACMP 0x0 0x0 0x10 registers n ACMP1_ 46 ACMP0_CR0 ACMP1 Configuration Register 0 0x0 32 read-write n 0x0 0x0 EN Analog Comparator Enable 7 1 read-write 0 The ACMP1 is disabled. #0 1 The ACMP1 is enabled. #1 HYST Analog Comparator Hysterisis Selection 6 1 read-write 0 20 mV. #0 1 30 mV. #1 IE ACMP1 Interrupt Enable 4 1 read-write 0 Disable the ACMP1 Interrupt. #0 1 Enable the ACMP1 Interrupt. #1 MOD ACMP1 sensitivity modes of the interrupt trigger 0 2 read-write 00 ACMP1 interrupt on output falling edge. #00 01 ACMP1 interrupt on output rising edge. #01 10 ACMP1 interrupt on output falling edge. #10 11 ACMP1 interrupt on output falling or rising edge. #11 ACMP0_CR1 ACMP1 Configuration Register 1 0x4 32 read-write n 0x0 0x0 NSEL ACMP1 Negative Input Select 0 3 read-write 000 External input 0 #000 001 External input 1 #001 010 External input 2 #010 011 External input 3 #011 100 External input 4 #100 101 DAC1 Output #101 110 ACMP1 output tie 0 #110 111 ACMP1 output tie 0 #111 PSEL ACMP1 Positive Input Select 4 3 read-write 000 External input 0 #000 001 External input 1 #001 010 External input 2 #010 011 External input 3 #011 100 External input 4 #100 101 DAC1 Output #101 110 ACMP1 output tie 0 #110 111 ACMP1 output tie 0 #111 ACMP0_CR2 ACMP1 configuration register 2 0x8 32 read-write n 0x0 0x0 DACEN DAC1 Enable 7 1 read-write 0 The DAC1 is disabled. #0 1 The DAC1 is enabled. #1 VAL DAC1 Output Level Selection 0 6 read-write ACMP0_DSR ACMP0 data output register 0 0xC 32 read-write n 0x0 0x0 F ACMP1 interrupt Flag 4 1 read-write O ACMP1 output 0 1 read-write WUF ACMP1 low power wakeup interrupt flag 6 1 read-write ADC Analog to Digital Convert Module ADC 0x0 0x0 0x50 registers n ADC 44 AWDH AWD High threshold register 0x24 32 read-write n 0x0 0x0 AWDH High threshold value for analog watchdog 0 12 read-write AWDL AWD Low threshold register 0x28 32 read-write n 0x0 0x0 AWDL Low threshold value for analog watchdog 0 12 read-write CTRL1 ADC control register 1 0x4 32 read-write n 0x0 0x0 ALIGN Data Alignment 22 1 read-write 0 Right Alignment #0 1 Left Alignment #1 AMOCH Analog monitor detecting channel 0 5 read-write AMOEN Regular Group Analog Monitor Detect function Enable 7 1 read-write AMOIE AMO interrupt Enable 18 1 read-write 0 AMO interrupt Disabled #0 1 AMO interrupt Enabled, An interrupt is generated when the AMO bit is set #1 AMOSGL Analog monitor detecting channel 5 1 read-write 0 AMO used in All channels #0 1 AMO function used in single channel defined in AMOCH register #1 CONT Continuous conversion 14 1 read-write 0 Single conversion mode #0 1 continuous conversion mode #1 DISCEN Discontinous mode on regular channels 13 1 read-write 0 regular group Discontinous mode disabled #0 1 regular group Discontinous mode enabled #1 DISCNUM Discontinuous conversion length of channel 8 3 read-write DMAEN DMA Function Enable 19 1 read-write 0 DMA function Disabled #0 1 DMA function Enabled #1 EOCIE EOC interrupt Enable 16 1 read-write 0 EOC interrupt Disabled #0 1 EOC interrupt Enabled, An interrupt is generated when the EOC bit is set #1 EXTTRIG Regular group trig source select 20 1 read-write 0 Internal trigger source(software trig) #0 1 external trigger source #1 IAMOEN Injection Group Analog Monitor Detect function Enable 6 1 read-write IAUTO Injection Group Automatic conversion 11 1 read-write 0 Injection group automatic conversion disabled #0 1 Injection group automatic conversion enabled #1 IDISCEN Discontinous mode on injected channels 12 1 read-write 0 Injection group Discontinous mode disabled #0 1 Injection group Discontinous mode enabled #1 IEOCIE IEOC interrupt Enable 17 1 read-write 0 IEOC interrupt Disabled #0 1 IEOC interrupt Enabled, An interrupt is generated when the IEOC bit is set #1 IEXTTRIG Inject group trig source select 21 1 read-write 0 Internal trigger source(software trig) #0 1 external trigger source #1 ISWSTART software trigger for Inject channels 30 1 read-write SCAN Scan Mode 15 1 read-write 0 Scan mode disabled #0 1 Scan mode enabled #1 SWSTART software trigger for regular channels 31 1 read-write CTRL2 ADC Control Register 2 0x8 32 read-write n 0x0 0x0 ADON ADC converter ON/OFF register 0 1 read-write 0 Disable ADC conversion and go to power down mode #0 1 Enable ADC and to start conversion #1 PSC Bus Clock prescaler 12 4 Read-write IDR1 ADC Injection Group data Register(n) 0x78 32 read-only n 0x0 0x0 IDR Injection group data Value 0 12 read-only IDR2 ADC Injection Group data Register(n) 0xB8 32 read-only n 0x0 0x0 IDR Injection group data Value 0 12 read-only IDR3 ADC Injection Group data Register(n) 0xFC 32 read-only n 0x0 0x0 IDR Injection group data Value 0 12 read-only IDR4 ADC Injection Group data Register(n) 0x144 32 read-only n 0x0 0x0 IDR Injection group data Value 0 12 read-only IOFR1 ADC Injection Group Offset Register(n) 0x28 32 read-write n 0x0 0x0 IOFR Injection group offset Value 0 12 read-write IOFR2 ADC Injection Group Offset Register(n) 0x40 32 read-write n 0x0 0x0 IOFR Injection group offset Value 0 12 read-write IOFR3 ADC Injection Group Offset Register(n) 0x5C 32 read-write n 0x0 0x0 IOFR Injection group offset Value 0 12 read-write IOFR4 ADC Injection Group Offset Register(n) 0x7C 32 read-write n 0x0 0x0 IOFR Injection group offset Value 0 12 read-write ISQR ADC injection group sequence configure register 0x38 32 read-write n 0x0 0x0 ISQ1 channel selection for injection group 1 0 5 read-write ISQ2 channel selection for injection group 2 5 5 read-write ISQ3 channel selection for injection group 3 10 5 read-write ISQ4 channel selection for injection group 4 15 5 read-write ISQL length of injection group 20 2 read-write RDR ADC Regular Group data Register 0x4C 32 read-only n 0x0 0x0 IDR Regular group data Value 0 12 read-only RSQR1 ADC regular group sequence configure register 1 0x2C 32 read-write n 0x0 0x0 RSQ13 channel selection for regular group 13 0 5 read-write RSQ14 channel selection for regular group 14 5 5 read-write RSQ15 channel selection for regular group 15 10 5 read-write RSQ16 channel selection for regular group 16 15 5 read-write RSQL length of regular group 20 4 read-write RSQR2 ADC regular group sequence configure register 2 0x30 32 read-write n 0x0 0x0 RSQ10 channel selection for regular group 10 15 5 read-write RSQ11 channel selection for regular group 11 20 5 read-write RSQ12 channel selection for regular group 12 25 5 read-write RSQ7 channel selection for regular group 7 0 5 read-write RSQ8 channel selection for regular group 8 5 5 read-write RSQ9 channel selection for regular group 9 10 5 read-write RSQR3 ADC regular group sequence configure register 3 0x34 32 read-write n 0x0 0x0 RSQ1 channel selection for regular group 1 0 5 read-write RSQ2 channel selection for regular group 2 5 5 read-write RSQ3 channel selection for regular group 3 10 5 read-write RSQ4 channel selection for regular group 4 15 5 read-write RSQ5 channel selection for regular group 5 20 5 read-write RSQ6 channel selection for regular group 6 25 5 read-write SPT1 ADC Sample time setting register 1 0xC 32 read-write n 0x0 0x0 SPT10 Sample time for Channel 10 0 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 SPT11 Sample time for Channel 11 3 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 SPT12 Sample time for Channel 12 6 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 SPT13 Sample time for Channel 13 9 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 SPT14 Sample time for Channel 14 12 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 SPT15 Sample time for Channel 15 15 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 SPT16 Sample time for Channel 16 18 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 SPT17 Sample time for Channel 17 21 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 SPT2 ADC Sample time setting register 2 0x10 32 read-write n 0x0 0x0 SPT0 Sample time for Channel 0 0 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 SPT1 Sample time for Channel 1 3 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 SPT2 Sample time for Channel 2 6 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 SPT3 Sample time for Channel 3 9 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 SPT4 Sample time for Channel 4 12 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 SPT5 Sample time for Channel 5 15 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 SPT6 Sample time for Channel 6 18 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 SPT7 Sample time for Channel 7 21 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 SPT8 Sample time for Channel 8 24 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 SPT9 Sample time for Channel 9 27 3 read-write 000 6 ADCCLK #000 001 14 ADCCLK #001 010 29 ADCCLK #010 011 42 ADCCLK #011 100 56 ADCCLK #100 101 72 ADCCLK #101 110 215 ADCCLK #110 111 3 ADCCLK #111 STR ADC status Register 0x0 32 read-write n 0x0 0x0 AMO Analog monitor event occrs 0 1 read-write 0 no analog monitor event #0 1 analog monitor event occurs,write 0 to clear #1 EOC Regular group conversion completed flag 1 1 read-write 0 Regular group conversion not completed #0 1 Regular group conversion completed,write 0 or Read ADC_RDR to clear #1 IDLE ADC idle state indicate(is useful for sleep function) 3 1 Read-Only 0 ADC not in idle state #0 1 ADC is in idle state #1 IEOC Injection group conversion completed flag 2 1 read-write 0 Injection group conversion not completed #0 1 Injection group conversion completed,write 0 to clear #1 CAN1 CAN1 CAN1 0x0 0x0 0x2C registers n CAN1 42 ACF0 Acceptance Code Register 0x18 32 read-write n 0x0 0x0 ACODE Acceptance Code 0 29 read-write AIDE Acceptance Mask IDE Bit value 29 1 read-write AIDEE Acceptance Mask IDE bit check enable 30 1 read-write ACFCTRL Acceptance Filter Control Register 0x14 32 read-write n 0x0 0x0 ACFADR Acceptance filter address 0 4 read-write AE0 Acceptance Filter Enable 16 1 read-write AE1 Acceptance Filter Enable 17 1 read-write AE10 Acceptance Filter Enable 26 1 read-write AE11 Acceptance Filter Enable 27 1 read-write AE12 Acceptance Filter Enable 28 1 read-write AE13 Acceptance Filter Enable 29 1 read-write AE14 Acceptance Filter Enable 30 1 read-write AE15 Acceptance Filter Enable 31 1 read-write AE2 Acceptance Filter Enable 18 1 read-write AE3 Acceptance Filter Enable 19 1 read-write AE4 Acceptance Filter Enable 20 1 read-write AE5 Acceptance Filter Enable 21 1 read-write AE6 Acceptance Filter Enable 22 1 read-write AE7 Acceptance Filter Enable 23 1 read-write AE8 Acceptance Filter Enable 24 1 read-write AE9 Acceptance Filter Enable 25 1 read-write SELMASK Select Acceptance MASK 5 1 read-write CFG TTCAN:Trigger Configuration 0x24 32 read-write n 0x0 0x0 TEW Transmit enable window 12 4 read-write TRIG trigger time 16 16 read-write TTPTR Transmit Trigger TB Slot Pointer 0 6 read-write TTYPE trigger type 8 3 read-write EALCAP Error and Arbitration Lost Capture Register 0x10 32 read-write n 0x0 0x0 ALC Arbitration Lost Capture 0 5 read-only KOER Kind of Error 5 3 read-only RECNT Receive Error Count 16 8 read-only TECNT Transmit Error Count 24 8 read-only MSG TTCAN: Reference Message 0x20 32 read-write n 0x0 0x0 ID Reference Message 0 29 read-write IDE Reference Message IDE Bit 31 1 read-write RTIE Receive and Transmit Interrupt Enable Register 0x4 32 read-write n 0x0 0x0 AFWL Receive Buffer Almost Full Warning Limit 28 4 read-write AIF Abort Interrupt Flag 8 1 read-write ALIE Arbitration Lost Interrupt Enable 19 1 read-write ALIF Arbitration Lost Interrupt Flag 18 1 read-write BEIE Bus Error Interrupt Enable 17 1 read-write BEIF Bus Error Interrupt flag 16 1 read-write EIE Error Interrupt Enable 1 1 read-write EIF Error Interrupt Flag 9 1 read-write EPASS Error Passive Mode Active enable bit 22 1 read-write EPIE Error Passive Interrupt Enable 21 1 read-write EPIF Error Passive Interrupt Flag 20 1 read-write EWARN Error Warning Limit Reached 23 1 read-write EWL Programmable Error Warnig Limit 24 4 read-write RAFIE RB Almost Full Interrupt Enable 4 1 read-write RAFIF RB Almost Full Interrupt flag 12 1 read-write RFIE RB Full Interrupt Enable 5 1 read-write RFIF RB Full Interrupt flag 13 1 read-write RIE Receive Interrupt enable 7 1 read-write RIF Receive Interrupt flag 15 1 read-write ROIE RB Overflow Interrupt enable 6 1 read-write ROIF RB Overflow Interrupt flag 14 1 read-write TPIE Transmit Primary Interrupt Enable 3 1 read-write TPIF Transmission Primary Interrupt Flag 11 1 read-write TSFF Transmit Secondary Buffer full flag 0 1 read-write TSIE Transmit Secondary Interrupt Enable 2 1 read-write TSIF Transmission Secondary Interrupt Flag 10 1 read-write STAT configuration and status register 0x0 32 read-write n 0x0 0x0 BUSOFF BUS off status 0 1 read-write LBME Loop back mode, external 6 1 read-write LBMI Loop back mode internal 5 1 read-write LOM Listen Only mode 14 1 read-write RACTIVE Reception Active 2 1 read-write RESET reset request bit 7 1 read-write ROM Receive Buffer Overflow Mode 30 1 read-write ROV Receive Buffer Overflow 29 1 read-write RREL Receive Buffer Release 28 1 read-write RSTAT Receive Buffer status bits 24 2 read-only STBY Transceiver Standby mode 13 1 read-write TACTIVE Transmission Active 1 1 read-write TBSEL Transmit Buffer Select 15 1 read-write TPA Transmit Primary Abort 11 1 read-write TPE Transmit Primary Enable 12 1 read-write TPSS Transmission Primary single shot mode for PTB 4 1 read-write TSA Transmit Secondary Abort 8 1 read-write TSALL Transmit Secondary All frames 9 1 read-write TSMODE Transmit buffer Secondary operation Mode 21 1 read-write TSNEXT Transmit Buffer Secondary next 22 1 read-write TSONE Transmit Secondary one Frame 10 1 read-write TSSS Transmission Secondary single shot mode for STB 3 1 read-write TSSTAT Transmit Secondary status bits 16 2 read-write TTTBM TTCAN Transmit Buffer Mode 20 1 read-write S_Seg Bit Timing Register 0x8 32 read-write n 0x0 0x0 S_PRESC Prescaler 24 8 read-write S_Seg_1 Bit Timing Segment 1 0 8 read-write S_Seg_2 Bit Timing Segment 2 8 7 read-write S_SJW Synchronization Jump Width 16 7 read-write VER Version Information Register 0 0x1C 32 read-write n 0x0 0x0 PRESC TTCAN Timer Prescaler 25 2 read-write TBE set TB slot to "Empty" 23 1 read-write TBF set TB slot to "Filled" 22 1 read-write TBPTR pointer to a TB message slot 16 6 read-write TEIF Trigger Error Interrupt Flag 29 1 read-write TTEN Timer Trigger Enable 24 1 read-write TTIE Timer Trigger Interrupt Enable 28 1 read-write TTIF Timer Trigger Interrupt Flag 27 1 read-write VER Version of CAN-CTRL 0 16 read-write WTIE Watch Trigger Interrupt Enable 31 1 read-write WTIF Watch Trigger Interrupt Flag 30 1 read-write WTRIG TTCAN: Watch Trigger Tim 0x28 32 read-write n 0x0 0x0 WTRIG watch trigger time 0 16 read-write CAN2 CAN2 CAN2 0x0 0x0 0x2C registers n CAN2 43 ACF0 Acceptance Code Register 0x18 32 read-write n 0x0 0x0 ACODE Acceptance Code 0 29 read-write AIDE Acceptance Mask IDE Bit value 29 1 read-write AIDEE Acceptance Mask IDE bit check enable 30 1 read-write ACFCTRL Acceptance Filter Control Register 0x14 32 read-write n 0x0 0x0 ACFADR Acceptance filter address 0 4 read-write AE0 Acceptance Filter Enable 16 1 read-write AE1 Acceptance Filter Enable 17 1 read-write AE10 Acceptance Filter Enable 26 1 read-write AE11 Acceptance Filter Enable 27 1 read-write AE12 Acceptance Filter Enable 28 1 read-write AE13 Acceptance Filter Enable 29 1 read-write AE14 Acceptance Filter Enable 30 1 read-write AE15 Acceptance Filter Enable 31 1 read-write AE2 Acceptance Filter Enable 18 1 read-write AE3 Acceptance Filter Enable 19 1 read-write AE4 Acceptance Filter Enable 20 1 read-write AE5 Acceptance Filter Enable 21 1 read-write AE6 Acceptance Filter Enable 22 1 read-write AE7 Acceptance Filter Enable 23 1 read-write AE8 Acceptance Filter Enable 24 1 read-write AE9 Acceptance Filter Enable 25 1 read-write SELMASK Select Acceptance MASK 5 1 read-write CFG TTCAN:Trigger Configuration 0x24 32 read-write n 0x0 0x0 TEW Transmit enable window 12 4 read-write TRIG trigger time 16 16 read-write TTPTR Transmit Trigger TB Slot Pointer 0 6 read-write TTYPE trigger type 8 3 read-write EALCAP Error and Arbitration Lost Capture Register 0x10 32 read-write n 0x0 0x0 ALC Arbitration Lost Capture 0 5 read-only KOER Kind of Error 5 3 read-only RECNT Receive Error Count 16 8 read-only TECNT Transmit Error Count 24 8 read-only MSG TTCAN: Reference Message 0x20 32 read-write n 0x0 0x0 ID Reference Message 0 29 read-write IDE Reference Message IDE Bit 31 1 read-write RTIE Receive and Transmit Interrupt Enable Register 0x4 32 read-write n 0x0 0x0 AFWL Receive Buffer Almost Full Warning Limit 28 4 read-write AIF Abort Interrupt Flag 8 1 read-write ALIE Arbitration Lost Interrupt Enable 19 1 read-write ALIF Arbitration Lost Interrupt Flag 18 1 read-write BEIE Bus Error Interrupt Enable 17 1 read-write BEIF Bus Error Interrupt flag 16 1 read-write EIE Error Interrupt Enable 1 1 read-write EIF Error Interrupt Flag 9 1 read-write EPASS Error Passive Mode Active enable bit 22 1 read-write EPIE Error Passive Interrupt Enable 21 1 read-write EPIF Error Passive Interrupt Flag 20 1 read-write EWARN Error Warning Limit Reached 23 1 read-write EWL Programmable Error Warnig Limit 24 4 read-write RAFIE RB Almost Full Interrupt Enable 4 1 read-write RAFIF RB Almost Full Interrupt flag 12 1 read-write RFIE RB Full Interrupt Enable 5 1 read-write RFIF RB Full Interrupt flag 13 1 read-write RIE Receive Interrupt enable 7 1 read-write RIF Receive Interrupt flag 15 1 read-write ROIE RB Overflow Interrupt enable 6 1 read-write ROIF RB Overflow Interrupt flag 14 1 read-write TPIE Transmit Primary Interrupt Enable 3 1 read-write TPIF Transmission Primary Interrupt Flag 11 1 read-write TSFF Transmit Secondary Buffer full flag 0 1 read-write TSIE Transmit Secondary Interrupt Enable 2 1 read-write TSIF Transmission Secondary Interrupt Flag 10 1 read-write STAT configuration and status register 0x0 32 read-write n 0x0 0x0 BUSOFF BUS off status 0 1 read-write LBME Loop back mode, external 6 1 read-write LBMI Loop back mode internal 5 1 read-write LOM Listen Only mode 14 1 read-write RACTIVE Reception Active 2 1 read-write RESET reset request bit 7 1 read-write ROM Receive Buffer Overflow Mode 30 1 read-write ROV Receive Buffer Overflow 29 1 read-write RREL Receive Buffer Release 28 1 read-write RSTAT Receive Buffer status bits 24 2 read-only STBY Transceiver Standby mode 13 1 read-write TACTIVE Transmission Active 1 1 read-write TBSEL Transmit Buffer Select 15 1 read-write TPA Transmit Primary Abort 11 1 read-write TPE Transmit Primary Enable 12 1 read-write TPSS Transmission Primary single shot mode for PTB 4 1 read-write TSA Transmit Secondary Abort 8 1 read-write TSALL Transmit Secondary All frames 9 1 read-write TSMODE Transmit buffer Secondary operation Mode 21 1 read-write TSNEXT Transmit Buffer Secondary next 22 1 read-write TSONE Transmit Secondary one Frame 10 1 read-write TSSS Transmission Secondary single shot mode for STB 3 1 read-write TSSTAT Transmit Secondary status bits 16 2 read-write TTTBM TTCAN Transmit Buffer Mode 20 1 read-write S_Seg Bit Timing Register 0x8 32 read-write n 0x0 0x0 S_PRESC Prescaler 24 8 read-write S_Seg_1 Bit Timing Segment 1 0 8 read-write S_Seg_2 Bit Timing Segment 2 8 7 read-write S_SJW Synchronization Jump Width 16 7 read-write VER Version Information Register 0 0x1C 32 read-write n 0x0 0x0 PRESC TTCAN Timer Prescaler 25 2 read-write TBE set TB slot to "Empty" 23 1 read-write TBF set TB slot to "Filled" 22 1 read-write TBPTR pointer to a TB message slot 16 6 read-write TEIF Trigger Error Interrupt Flag 29 1 read-write TTEN Timer Trigger Enable 24 1 read-write TTIE Timer Trigger Interrupt Enable 28 1 read-write TTIF Timer Trigger Interrupt Flag 27 1 read-write VER Version of CAN-CTRL 0 16 read-write WTIE Watch Trigger Interrupt Enable 31 1 read-write WTIF Watch Trigger Interrupt Flag 30 1 read-write WTRIG TTCAN: Watch Trigger Tim 0x28 32 read-write n 0x0 0x0 WTRIG watch trigger time 0 16 read-write CTU Connect Module Unit CTU 0x0 0x0 0x10 registers n CONFIG1 CTU Configuration Register 1 0x0 32 read-write n 0x0 0x0 ACIC Analog Comparator to Input Capture Enable 11 1 read-write 0 ACMP0 Output is not connected to PWM1 Channel0 #0 1 ACMP1 Output is connected to PWM1 Channel0 #1 ACTRG ACMP Trigger PWM2 Selection 5 1 read-write 0 ACMP0 Output Trigger PWM #0 1 ACMP1 Output Trigger PWM #1 ADHWT1 ADC Hardware Trigger Source for regular group 20 3 read-write 000 RTC Overflow as ADC hardware Trigger #000 001 PWM0 as ADC Hardware Trigger #001 010 PWM2 Init Trigger with 8-bit programmable counter delay #010 011 PWM2 Match Trigger with 8-bit programmable counter delay #011 100 Timer Channel0 overflow as ADC Hardware Trigger #100 101 Timer Channel1 overflow as ADC hardware Trigger #101 110 ACMP0 Out as ADC Hardware Trigger #110 111 ACMP1 Out as ADC Hardware Trigger #111 CLK BUS Clock Output Selection 16 3 read-write 000 BUS Clock #000 001 Bus Divided by 2 #001 010 Bus Divided by 4 #010 011 Bus Divided by 8 #011 100 Bus Divided by 16 #100 101 Bus Divided by 32 #101 110 Bus Divided by 64 #110 111 Bus Divided by 128 #111 DELAY Trigger Delay Counter 24 8 read-write DLYACT Trigger Delay Active 23 1 read-write 0 Delay is inactive #0 1 Delay is active #1 PWMSYNC PWM SW Synchronization Selection 14 1 read-write 0 No Synchronization triggered #0 1 Generate PWM Synchronization to trigger PWM Modules #1 RTCC Real-Time Counter Capture 10 1 read-write 0 RTC Overflow is not connected to PWM1 Channel 1 #0 1 RTC overflow is connected to PWM1 Channel 1 #1 RXDCE UART0_RX Capture Selection 12 1 read-write 0 UART1_RX input connect to UART1 Only #0 1 UART1_RX input connected to PWM0 Channel 1 #1 RXDFE UART1 RxD filter Selection 8 2 read-write 00 RXD1 input signal is connected to UART1 modulate directly #00 01 RXD1 input signal is filtered by ACMP0, then injected to UART1 #01 10 RXD1 input signal is filtered by ACMP1, then injected to UART1 #10 11 Not Defined #11 TXDME UART1 TX Modulation Selection 15 1 read-write 0 UART1_TX is connected to PIN out directly #0 1 UART1_TX is modulated by PWM0 Channel 0 #1 CONFIG2 CTU Configuration Register 2 0x4 32 read-write n 0x0 0x0 ACPWTS PWDT ACMP_OUT Select 3 1 read-write 0 ACMP1_OUT is Connected to PWDT_IN3 #0 1 ACMP0_OUT is Connected to PWDT_IN3 #1 ADHWT2 ADC Hardware Trigger Source for injection group 6 3 read-write 000 RTC Overflow as the ADC hardware trigger #000 001 PWM0 as the ADC hardware trigger #001 010 PWM2 init trigger with 8-bit programmable count delay as ADC hardware trigger #010 011 PWM2 match trigger with 8-bit programmable count delay as ADC hardware trigger #011 100 Timer Channel0 overflow as the ADC hardware trigger #100 101 Timer Channel1 overflow as the ADC hardware trigger #101 110 ACMP0 output as the ADC hardware trigger #110 111 ACMP1 output as the ADC hardware trigger #111 UARTPWDTS PWDT UART RX Select 4 2 read-write 00 UART0 RX is connected to PWDT_IN3 #00 01 UART1 RX is connected to PWDT_IN3 #01 10 UART2 RX is connected to PWDT_IN3 #10 11 ACMP_OUT is Connected to PWTIN3 #11 I2C1 Inter-Integrated Circuit I2C 0x0 0x0 0x44 registers n I2C1 15 ADDR1 I2C Address Register 1 0x0 32 read-write n 0x0 0x0 AD Address 1 7 read-write ADDR2 I2C ADDR register 2 0x4 32 read-write n 0x0 0x0 AD Address 0 3 read-write CONTROL1 I2C Control Register 1 0x10 32 read-write n 0x0 0x0 IICEN I2C Module Enable 7 1 read-write IICIE I2C interrupt Enable 6 1 read-write MSTR I2C operation mode Select 5 1 read-write 0 Slave Mode #0 1 Master Mode #1 TACK Transmit Acknowledge Enable 3 1 read-write 0 ACK will sent to the bus on the following receiving byte #0 1 NACK will sent to the bus on the following receiving byte #1 TX Transmit Mode Select(valid for master) 4 1 read-write WUEN wakeup enable 2 1 read-write CONTROL2 I2C Control Register 2 0x14 32 read-write n 0x0 0x0 ADEXT Address Extension(valid for Slave) 6 1 read-write ARBEN Arbitration Enable 3 1 read-write GCAEN General Call enable(valid for Slave) 7 1 read-write STREN SCL Strech enable(Valid for slave) 0 1 read-write SYNCEN SCL Sync Enable 4 1 read-write CONTROL3 I2C Control Register 3 0x18 32 read-write n 0x0 0x0 MNTEN Monitor Function Enable 0 1 read-write NACKIE NACK get interrupt Enable 1 1 read-write RXFIE RX buffer full interrupt enable 5 1 read-write RXOFIE RX buffer overflow interrupt enable 7 1 read-write TXEMIE TX buffer empty interrupt enable 4 1 read-write TXUFIE TX buffer underflow error interrupt enable 6 1 read-write CONTROL4 I2C Control Register 4 0x1C 32 read-write n 0x0 0x0 DMARXEN DMARX enable 1 1 read-write DMATXEN DMATX enable 0 1 read-write DATA I2C Data Register 0x2C 32 read-write n 0x0 0x0 DATA Data 0 8 read-write MAK Slave Monitor Function ACK bit 8 1 read-only DGL_CFG I2C Deglitch Configuration Register 0x28 32 read-write n 0x0 0x0 DGLEN I2C Deglitch filter Enable 7 1 read-write DGL_CNT Deglitch Counter 0 4 read-write SSIE I2C Bus STOP or START interrupt Enable 5 1 read-write STARTF I2C Bus Start Detect Flag 4 1 read-write STOPF I2C Bus Stop detect Flag 6 1 read-write SAMPLE_CNT I2C SAMPLE CNT Register 0x8 32 read-write n 0x0 0x0 SAMPLE_CNT_DIV Adjust the width of each sample 0 8 read-write START_STOP I2C START_STOP Register 0x30 32 read-write n 0x0 0x0 START I2C Start(valid for master) 0 1 read-write STOP I2C Stop(valid for master) 1 1 read-write STATUS1 I2C Status Register 1 0x20 32 read-write n 0x0 0x0 ARBLOST Arbitration lost flag 4 1 read-write BND Byte end flag 7 1 read-only BUSY indicates the status of the bus regardless of slave or master mode 5 1 read-only RACK Acknowledge received(master or Slave TX mode) 0 1 read-Only READY internal hardware core is ready for new command or not 3 1 read-only SAMF Address match 6 1 read-write SRW Slave read/write 2 1 read-only STATUS2 I2C Status Register 2 0x24 32 read-write n 0x0 0x0 IDLE I2C Core Hardware state 7 1 read-only RXFF RX buffer Full flag(only valid for slave) 1 1 read-write RXOF RX buffer overflow flag(only valid for slave) 3 1 read-only TXEF TX buffer empty flag(only valid for slave) 0 1 read-write TXUF TX buffer underflow flag(only valid for slave) 2 1 read-only STEP_CNT I2C STEP CNT Register 0xC 32 read-write n 0x0 0x0 STEP_CNT_DIV Specifies the number of Samples per half pulse width 0 8 read-write I2C2 Inter-Integrated Circuit I2C 0x0 0x0 0x44 registers n I2C2 16 ADDR1 I2C Address Register 1 0x0 32 read-write n 0x0 0x0 AD Address 1 7 read-write ADDR2 I2C ADDR register 2 0x4 32 read-write n 0x0 0x0 AD Address 0 3 read-write CONTROL1 I2C Control Register 1 0x10 32 read-write n 0x0 0x0 IICEN I2C Module Enable 7 1 read-write IICIE I2C interrupt Enable 6 1 read-write MSTR I2C operation mode Select 5 1 read-write 0 Slave Mode #0 1 Master Mode #1 TACK Transmit Acknowledge Enable 3 1 read-write 0 ACK will sent to the bus on the following receiving byte #0 1 NACK will sent to the bus on the following receiving byte #1 TX Transmit Mode Select(valid for master) 4 1 read-write WUEN wakeup enable 2 1 read-write CONTROL2 I2C Control Register 2 0x14 32 read-write n 0x0 0x0 ADEXT Address Extension(valid for Slave) 6 1 read-write ARBEN Arbitration Enable 3 1 read-write GCAEN General Call enable(valid for Slave) 7 1 read-write STREN SCL Strech enable(Valid for slave) 0 1 read-write SYNCEN SCL Sync Enable 4 1 read-write CONTROL3 I2C Control Register 3 0x18 32 read-write n 0x0 0x0 MNTEN Monitor Function Enable 0 1 read-write NACKIE NACK get interrupt Enable 1 1 read-write RXFIE RX buffer full interrupt enable 5 1 read-write RXOFIE RX buffer overflow interrupt enable 7 1 read-write TXEMIE TX buffer empty interrupt enable 4 1 read-write TXUFIE TX buffer underflow error interrupt enable 6 1 read-write CONTROL4 I2C Control Register 4 0x1C 32 read-write n 0x0 0x0 DMARXEN DMARX enable 1 1 read-write DMATXEN DMATX enable 0 1 read-write DATA I2C Data Register 0x2C 32 read-write n 0x0 0x0 DATA Data 0 8 read-write MAK Slave Monitor Function ACK bit 8 1 read-only DGL_CFG I2C Deglitch Configuration Register 0x28 32 read-write n 0x0 0x0 DGLEN I2C Deglitch filter Enable 7 1 read-write DGL_CNT Deglitch Counter 0 4 read-write SSIE I2C Bus STOP or START interrupt Enable 5 1 read-write STARTF I2C Bus Start Detect Flag 4 1 read-write STOPF I2C Bus Stop detect Flag 6 1 read-write SAMPLE_CNT I2C SAMPLE CNT Register 0x8 32 read-write n 0x0 0x0 SAMPLE_CNT_DIV Adjust the width of each sample 0 8 read-write START_STOP I2C START_STOP Register 0x30 32 read-write n 0x0 0x0 START I2C Start(valid for master) 0 1 read-write STOP I2C Stop(valid for master) 1 1 read-write STATUS1 I2C Status Register 1 0x20 32 read-write n 0x0 0x0 ARBLOST Arbitration lost flag 4 1 read-write BND Byte end flag 7 1 read-only BUSY indicates the status of the bus regardless of slave or master mode 5 1 read-only RACK Acknowledge received(master or Slave TX mode) 0 1 read-Only READY internal hardware core is ready for new command or not 3 1 read-only SAMF Address match 6 1 read-write SRW Slave read/write 2 1 read-only STATUS2 I2C Status Register 2 0x24 32 read-write n 0x0 0x0 IDLE I2C Core Hardware state 7 1 read-only RXFF RX buffer Full flag(only valid for slave) 1 1 read-write RXOF RX buffer overflow flag(only valid for slave) 3 1 read-only TXEF TX buffer empty flag(only valid for slave) 0 1 read-write TXUF TX buffer underflow flag(only valid for slave) 2 1 read-only STEP_CNT I2C STEP CNT Register 0xC 32 read-write n 0x0 0x0 STEP_CNT_DIV Specifies the number of Samples per half pulse width 0 8 read-write LIN0 LIN Interface LIN0 0x0 0x0 0x84 registers n LIN0 38 BDHR Buffer data High register 0x34 32 read-write n 0x0 0x0 DATA4 Data 4 0 8 read-write DATA5 Data 5 8 8 read-write DATA6 Data 6 16 8 read-write DATA7 Data 7 24 8 read-write BDLR Buffer data low register 0x30 32 read-write n 0x0 0x0 DATA0 Data 0 0 8 read-write DATA1 Data 1 8 8 read-write DATA2 Data 2 16 8 read-write DATA3 Data 3 24 8 read-write CS LIN Checksum field register 0x28 32 read-write n 0x0 0x0 CS LIN Checksum field value 0 8 read-write CTRL1 LIN Control Register 1 0x4 32 read-write n 0x0 0x0 ATWU Control the behavior of the LIN hardware during sleep mode 12 1 read-write BDL Break delimiter length 15 1 read-write BLT LIN Break Length threshold select 4 1 read-write BTL LIN Break field transmit length in master mode 8 4 read-write DIOB LIN State machine goes to IDLE on bit error detection 23 1 read-write HIL Header inter-byte length between sync field and PID filed in master mode 16 2 read-write LBM LIN Loop back Mode enable bit 1 1 read-write MCS Disable the hardware checksum calculation 14 1 read-write RIL Response inter byte length between response data 20 2 read-write RSE LIN Slave Automatic Resynchronization Enable 13 1 read-write RSL Response inter space length, only for master mode 18 2 read-write SCM LIN software control Mode enable bit 3 1 read-write SM LIN Slave Mode enable bit 0 1 read-write STM LIN Self Test Mode enable bit 2 1 read-write CTRL2 LIN Control register 2 0x8 32 read-write n 0x0 0x0 HTR Header Transmission Requeset 0 1 read-write RDR Response Discard Request 3 1 read-write RTR Data Transmission Request 2 1 read-write WUTR Wakeup TX Request 4 1 read-write ESTS LIN Error Status register 0x14 32 read-write n 0x0 0x0 BDEF Break Delimiter Error Flag 4 1 write-clear BEF Bit Error Flag 7 1 write-clear BOF Buffer Overrun Flag 1 1 write-clear CEF Checksum Error Flag 6 1 write-clear FEF Framing Error Flag 2 1 write-clear IPEF Identifier Parity Error Flag 3 1 write-clear LZEF Long Zero Error Flag 9 1 write-clear NF Noise Flag 0 1 write-clear SFEF Synch Field Error Flag 5 1 write-clear TOEF Time Out Error Flag 8 1 write-clear FBR LIN fractional baud rate register 0x24 32 read-write n 0x0 0x0 FBR Fractional baud rate divide value 0 4 read-write FRM LIN Frame Control register 0x2C 32 read-write n 0x0 0x0 CST Checksum type 8 1 read-write DFL Data field length 11 2 read-write DIR Direction 9 1 read-write ID Identifier 0 6 read-write IBR LIN integer baud rate register 0x20 32 read-write n 0x0 0x0 IBR Integer baud rate divide value 0 12 read-write IEN LIN Interrupt Enable Register 0xC 32 read-write n 0x0 0x0 BEIE Bit Error Interrupt Enable 13 1 read-write BOIE Buffer Overrun Interrupt enable 9 1 read-write CEIE Checksum error Interrupt enable 12 1 read-write FEIE Framing Error Interrupt Enable 8 1 read-write HEIE Header Error Interrupt Enable 11 1 read-write HTRIE Header Received Interrupt enable 0 1 read-write LZIE Long Zero Interrupt Enable 15 1 read-write RRIE Response Reception Complete Interrupt Enable 2 1 read-write RTIE Response Transmitted Interrupt Enable 1 1 read-write TOIE Timeout Interrupt Enable 14 1 read-write WUIE Wakeup Interrupt enable 5 1 read-write IFCR0 LIN ID filter control register 0x88 32 read-write n 0x0 0x0 CST Checksum type 8 1 read-write DFL Data Field Length 10 3 read-write DIR Direction 9 1 read-write ID Identifier 0 6 read-write IFCR1 LIN ID filter control register 0xD0 32 read-write n 0x0 0x0 CST Checksum type 8 1 read-write DFL Data Field Length 10 3 read-write DIR Direction 9 1 read-write ID Identifier 0 6 read-write IFCR10 LIN ID filter control register 0x40C 32 read-write n 0x0 0x0 CST Checksum type 8 1 read-write DFL Data Field Length 10 3 read-write DIR Direction 9 1 read-write ID Identifier 0 6 read-write IFCR11 LIN ID filter control register 0x47C 32 read-write n 0x0 0x0 CST Checksum type 8 1 read-write DFL Data Field Length 10 3 read-write DIR Direction 9 1 read-write ID Identifier 0 6 read-write IFCR12 LIN ID filter control register 0x4F0 32 read-write n 0x0 0x0 CST Checksum type 8 1 read-write DFL Data Field Length 10 3 read-write DIR Direction 9 1 read-write ID Identifier 0 6 read-write IFCR13 LIN ID filter control register 0x568 32 read-write n 0x0 0x0 CST Checksum type 8 1 read-write DFL Data Field Length 10 3 read-write DIR Direction 9 1 read-write ID Identifier 0 6 read-write IFCR14 LIN ID filter control register 0x5E4 32 read-write n 0x0 0x0 CST Checksum type 8 1 read-write DFL Data Field Length 10 3 read-write DIR Direction 9 1 read-write ID Identifier 0 6 read-write IFCR15 LIN ID filter control register 0x664 32 read-write n 0x0 0x0 CST Checksum type 8 1 read-write DFL Data Field Length 10 3 read-write DIR Direction 9 1 read-write ID Identifier 0 6 read-write IFCR2 LIN ID filter control register 0x11C 32 read-write n 0x0 0x0 CST Checksum type 8 1 read-write DFL Data Field Length 10 3 read-write DIR Direction 9 1 read-write ID Identifier 0 6 read-write IFCR3 LIN ID filter control register 0x16C 32 read-write n 0x0 0x0 CST Checksum type 8 1 read-write DFL Data Field Length 10 3 read-write DIR Direction 9 1 read-write ID Identifier 0 6 read-write IFCR4 LIN ID filter control register 0x1C0 32 read-write n 0x0 0x0 CST Checksum type 8 1 read-write DFL Data Field Length 10 3 read-write DIR Direction 9 1 read-write ID Identifier 0 6 read-write IFCR5 LIN ID filter control register 0x218 32 read-write n 0x0 0x0 CST Checksum type 8 1 read-write DFL Data Field Length 10 3 read-write DIR Direction 9 1 read-write ID Identifier 0 6 read-write IFCR6 LIN ID filter control register 0x274 32 read-write n 0x0 0x0 CST Checksum type 8 1 read-write DFL Data Field Length 10 3 read-write DIR Direction 9 1 read-write ID Identifier 0 6 read-write IFCR7 LIN ID filter control register 0x2D4 32 read-write n 0x0 0x0 CST Checksum type 8 1 read-write DFL Data Field Length 10 3 read-write DIR Direction 9 1 read-write ID Identifier 0 6 read-write IFCR8 LIN ID filter control register 0x338 32 read-write n 0x0 0x0 CST Checksum type 8 1 read-write DFL Data Field Length 10 3 read-write DIR Direction 9 1 read-write ID Identifier 0 6 read-write IFCR9 LIN ID filter control register 0x3A0 32 read-write n 0x0 0x0 CST Checksum type 8 1 read-write DFL Data Field Length 10 3 read-write DIR Direction 9 1 read-write ID Identifier 0 6 read-write IFEN LIN ID Filter enable register 0x38 32 read-write n 0x0 0x0 EN Filter Number Enable 0 16 read-write IFMI LIN ID Filter match index register 0x40 32 read-write n 0x0 0x0 IFMI ID Filter match index 0 5 read-write IFMR LIN ID Filter mode register 0x3C 32 read-write n 0x0 0x0 IFM ID Filter Mode 0 8 read-write STS LIN Status Register 0x10 32 read-write n 0x0 0x0 DRF Data Reception Completed Flag 2 1 write-clear DTF Data Transmission Completed Flag 1 1 write-clear HTRF Header Transmission/Reception Flag 0 1 write-clear PS LIN receive pin state 4 1 read-only RRIP Response RX in Progress 6 1 read-only RTIP Response TX in Progress 5 1 read-only STS LIN mode status 8 4 read-only WUF Wake-up Flag 3 1 write-clear SYS LIN System Control Register 0x0 32 read-write n 0x0 0x0 LM LIN Mode Select 0 2 read-write TO1 LIN Time out control register 1 0x18 32 read-write n 0x0 0x0 HTO Header timeout value 0 6 read-write TO2 LIN Time out control register 2 0x1C 32 read-write n 0x0 0x0 TOEN Header timeout enable 0 1 read-write PWDT Pulse Width Detection Timer PWDT 0x0 0x0 0x12 registers n PWDT 0 INIT0 PWDT Initialize Register 0 0x0 32 read-write n 0x0 0x0 EDGE PWDT Input Edge Sensitivity 10 2 read-write 00 The first falling-edge starts the pulse width measurement, and on all the subsequent falling edges, the pulse width is captured. #00 01 The first rising edge starts the pulse width measurement, and on all the subsequent rising and falling edges, the pulse width is captured. #01 10 The first falling edge starts the pulse width measurement, and on all the subsequent rising and falling edges, the pulse width is captured. #10 11 The first-rising edge starts the pulse width measurement, and on all the subsequent rising edges, the pulse width is captured. #11 IE PWDT Module Interrupt Enable 5 1 read-write 0 Disables the PWDT to generate interrupt. #0 1 Enables the PWDT to generate interrupt. #1 OVF PWDT Counter Overflow flag 0 1 read-write 0 PWDT counter no overflow. #0 1 PWDT counter runs from 0xFFFF to 0x0000. #1 OVIE PWDT Counter Overflow Interrupt Enable 3 1 read-write 0 Disable PWDT to generate interrupt when PWDTOV is set. #0 1 Enable PWDT to generate interrupt when PWDTOV is set. #1 PCLKSEL PWDT Clock Source Selection 15 1 read-write 0 Bus clock is selected as the clock source of PWDT counter. #0 1 Alternative clock is selected as the clock source of PWDT counter. #1 PINSEL PWDT Pulse Inputs Selection 12 2 read-write 00 PWDTIN[0] is enabled. #00 01 PWDTIN[1] is enabled. #01 10 PWDTIN[2] enabled. #10 11 PWDTIN[3] enabled. #11 PPWCV Positive Pulse Width Count Value 16 16 read-only PRDYIE PWDT Pulse Width Data Ready Interrupt Enable 4 1 read-write 0 Disable PWDT to generate interrupt when PWDTRDY is set. #0 1 Enable PWDT to generate interrupt when PWDTRDY is set. #1 PSC PWDT Clock Prescaler (CLKPRE) Setting 7 3 read-write 000 Clock divided by 1. #000 001 Clock divided by 2. #001 010 Clock divided by 4. #010 011 Clock divided by 8. #011 100 Clock divided by 16. #100 101 Clock divided by 32. #101 110 Clock divided by 64. #110 111 Clock divided by 128. #111 PWDTEN PWDT Module Enable 6 1 read-write 0 The PWDT is disabled. #0 1 The PWDT is enabled. #1 RDYF PWDT Pulse Width Valid Flag 1 1 read-write 0 PWDT pulse width register(s) is not up-to-date. #0 1 PWDT pulse width register(s) has been updated. #1 SR PWDT Soft Reset Register 2 1 write-only 0 No action taken. #0 1 Writing 1 to this field will perform soft reset to PWDT. #1 INIT1 Pulse Width Detection Timer Initialize Register 1 0x8 32 read-write n 0x0 0x0 CMPEN PWDT Compare Mode Enable Bit 11 1 read-write 0 enable the pwt_in0 ~ pwt_in2 derived from acmp0_pwt_a ~ acmp0_pwt_c external #0 1 enable the pwt_in0 ~ pwt_in2 derived from acmp0_pwt_a ~ acmp0_pwt_c internally #1 FILTEN PWDT input filter function Enable Bit 8 1 read-write 0 PWDT input filter function is disable #0 1 PWDT input filter function is enable #1 FILTPSC PWDT input filter function Enable Bit 4 4 read-write FILTVAL PWDT filter Value 0 4 read-write HALLEN Hall Sensor Signal Detect function Enable Bit 9 1 read-write 0 Hall Sensor Signal Detect function Disable #0 1 Hall Sensor Signal Detect function Enable #1 HALLSTATUS HALL Sensor C Status Value 28 3 read-only TIMCNTVAL PWDT Timer Load Value 12 16 read-write TIMEN PWDT Timer Function Enable Bit 10 1 read-write 0 PWDT Timer Function Disable #0 1 PWDT Timer Function Enable . #1 NPWCV Negative Pulse Width Count Value 0x4 32 read-only n 0x0 0x0 NPWCV Negative Pulse Width. It is suggested to use half-word (16-bit) or word (32-bit) to read out this value. 0 16 read-only PWDTC PWDT Counter. It is suggested to use half-word (16-bit) or word (32-bit) to read out this value. 16 16 read-only PWM0 Pulse Width Management Module PWM 0x0 0x0 0xA0 registers n PWM0 34 CAPFILTER Input Capture Filter Control 0x78 32 read-write n 0x0 0x0 CH0CAPFVAL Channel 0 Input Filter 0 5 read-write CH1CAPFVAL Channel 1 Input Filter 5 5 read-write CH2CAPFVAL Channel 2 Input Filter 10 5 read-write CH3CAPFVAL Channel 3 Input Filter 15 5 read-write CH0SCR Channel (n) Status And Control Register 0x18 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH1SCR Channel (n) Status And Control Register 0x2C 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH2SCR Channel (n) Status And Control Register 0x48 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH2V Channel (n) Value 0x58 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH3SCR Channel (n) Status And Control Register 0x6C 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH3V Channel (n) Value 0x80 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH4SCR Channel (n) Status And Control Register 0x98 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH4V Channel (n) Value 0xB0 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH5SCR Channel (n) Status And Control Register 0xCC 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH5V Channel (n) Value 0xE8 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CHOPOLCR Channels Output Polarity Control Register 0x70 32 read-write n 0x0 0x0 CH0POL Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH1POL Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH2POL Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH3POL Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH4POL Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH5POL Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CHOSWCR PWM CHannel Software Output Control Register 0x94 32 read-write n 0x0 0x0 CH0SWCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH0SWEN Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1SWCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1SWEN Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2SWCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2SWEN Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3SWCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3SWEN Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4SWCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4SWEN Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5SWCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5SWEN Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CNT PWM Counter Current Count Value 0x4 32 read-write n 0x0 0x0 COUNT Current Counter Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write n 0x0 0x0 CNTINIT no description available 0 16 read-write CONF Configuration 0x84 32 read-write n 0x0 0x0 BDMMODE Debug Mode 7 2 read-write CNTOFNUM Count Overflow Flag Number 0 7 read-write EVENTPSC PWM Channel Input Event Prescale Setting 16 12 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 DTSET Deadtime Paramenters Setting Register 0x68 32 read-write n 0x0 0x0 DTPSC Deadtime Prescaler Control Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 DTVAL Deadtime Value 0 6 read-write EXTTRIG PWM External Trigger 0x6C 32 read-write n 0x0 0x0 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 FDSR Fault Detect Status Register 0x74 32 read-write n 0x0 0x0 FAULTDF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FAULTDF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTDF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTDF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTDF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FFAFER Fault Filter and Fault Enable Register 0x7C 32 read-write n 0x0 0x0 FER0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FER1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FER2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FER3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FF0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FF1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FF2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FF3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write FLTPOL PWM Fault Input Polarity 0x88 32 read-write n 0x0 0x0 FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FUNCSEL PWM Features(Functions) Mode Selection Register 0x54 32 read-write n 0x0 0x0 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 FAULTMODE Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 INIT Initialize The Channels Output 1 1 read-write PWMEN2 PWM Enhance function Enable 0 1 read-write PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and PWM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and PWM counter synchronization. #1 WPDIS Write Protection Enable Register 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 INIT PWM Initialize, Include Clock and Prescale Setting 0x0 32 read-write n 0x0 0x0 CLKPSC Prescale Factor Selection 8 16 read-write CLKSRC Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the PWM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CNTMODE PWM Counter Mode Select 5 1 read-write 0 PWM counter operates in Up Counting mode. #0 1 PWM counter operates in Up-Down Counting mode. #1 CNTOF PWM Counter Overflow Flag 7 1 read-only 0 PWM counter has not overflowed. #0 1 PWM counter has overflowed. #1 CNTOIE PWM Counter Overflow Interrupt Enable 6 1 read-write 0 Disable CNTOF interrupts. Use software polling. #0 1 Enable CNTOF interrupts. An interrupt is generated when CNTOF equals one. #1 INVCR PWM Inverse Control Register 0x90 32 read-write n 0x0 0x0 PAIR0INVEN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 PAIR1INVEN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 PAIR2INVEN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 MCVR PWM Counter Max Count Value Register 0x8 32 read-write n 0x0 0x0 MCVR no description available 0 16 read-write MODESEL PWM Function Mode Selection 0x64 32 read-write n 0x0 0x0 PAIR0COMBINEN Combine Channels For Pair0 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 PAIR0COMPEN Complement Channels for Pair0 1 1 read-write 0 The channel 1 output is the same as the channel 0 output. #0 1 The channel 1 output is the complement of the channel 0 output. #1 PAIR0DECAP Dual Edge Capture Mode Captures for Pair0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 PAIR0DECAPEN Dual Edge Capture Mode Enable for Pair0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 PAIR0DTEN Deadtime Enable for Pair0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 PAIR0FAULTEN Fault Control Enable for Pair0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 PAIR0SYNCEN Synchronization Enable for Pair0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 PAIR1COMBINEN Combine Channels For Pair1 8 1 read-write 0 Channels 2 and 3 are independent. #0 1 Channels 2 and 3 are combined. #1 PAIR1COMPEN Complement Of Channel (n) For Pair1 9 1 read-write 0 The channel 3 output is the same as the channel 2 output. #0 1 The channel 3 output is the complement of the channel 2 output. #1 PAIR1DECAP Dual Edge Capture Mode Captures For Pair1 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 PAIR1DECAPEN Dual Edge Capture Mode Enable For Pair1 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 PAIR1DTEN Deadtime Enable For Pair1 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 PAIR1FAULTEN Fault Control Enable For Pair1 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 PAIR1SYNCEN Synchronization Enable For Pair1 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 PAIR2COMBINEN Combine Channels For Pair2 16 1 read-write 0 Channels 4 and 5 are independent. #0 1 Channels 4 and 5 are combined. #1 PAIR2COMPEN Complement Of Channel (n) For Pair2 17 1 read-write 0 The channel 5 output is the same as the channel 4 output. #0 1 The channel 5 output is the complement of the channel 4 output. #1 PAIR2DECAP Dual Edge Capture Mode Captures For Pair2 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 PAIR2DECAPEN Dual Edge Capture Mode Enable For Pair2 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 PAIR2DTEN Deadtime Enable For Pair2 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 PAIR2FAULTEN Fault Control Enable For Pair2 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 PAIR2SYNCEN Synchronization Enable For Pair2 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 OMCR Output Mask Control Register 0x60 32 read-write n 0x0 0x0 CH0OMEN Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OMEN Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OMEN Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OMEN Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OMEN Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OMEN Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 OUTINIT Initial Value For Channels Output 0x5C 32 read-write n 0x0 0x0 CH0OIV Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OIV Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OIV Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OIV Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OIV Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OIV Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 QEI Quadrature Encoder/Decoder Interface Configuration Register 0x80 32 read-write n 0x0 0x0 PHAFLTREN Phase A Input Filter Enable Register 7 1 read-write 0 Phase A input filter is disabled #0 1 Phase A input filter is enabled #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity #0 1 Inverted polarity #1 PHBFLTREN Phase B Input Filter Enable Register 6 1 read-write 0 Phase B input filter is disabled #0 1 Phase B input filter is enabled #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity #0 1 Inverted polarity #1 QEIEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder is Disable #0 1 Quadrature Decoder is Enable #1 QUADIR Quadrature Decoder Mode Enable 2 1 read-write 0 Quadrature Decoder is Disable #0 1 Quadrature Decoder is Enable #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode #1 TOFDIR Timer Overflow Direction in Quadrature Decoder Mode 1 1 read-write 0 TOF bit was set on the bottom of counting #0 1 TOF bit was set on the top of counting #1 STR Status Register 0x50 32 read-write n 0x0 0x0 CH0SF Channel 0 Status Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1SF Channel 1 Status Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2SF Channel 2 Status Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3SF Channel 3 Status Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4SF Channel 4 Status Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5SF Channel 5 Status Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 SYNC Synchronization 0x58 32 read-write n 0x0 0x0 ACMPTRIG PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 MAXSYNCP Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 MINSYNCP Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 OMSYNCP Output Mask Synchronization Point 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 PWM0TRIG PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 REINIT PWM Counter Reinitialization By Synchronization (PWM counter synchronization) 2 1 read-write 0 PWM counter continues to count normally. #0 1 PWM counter is updated with its initial value when the selected trigger is detected. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 SWTRIG PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write n 0x0 0x0 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 CNTVHWSYNC no description available 16 1 read-write 0 A hardware trigger does not activate the PWM counter synchronization. #0 1 A hardware trigger activates the PWM counter synchronization. #1 CNTVSWSYNC no description available 8 1 read-write 0 The software trigger does not activate the PWM counter synchronization. #0 1 The software trigger activates the PWM counter synchronization. #1 HWPOL Channel POL synchronization is activeated by a hardwaretrigger 22 1 read-write 0 The hardware trigger does not activate the POL register synchronization. #0 1 >The hardware trigger activates POL register synchronization. #1 HWTRIGMODESEL Hardware Trigger Mode 0 1 read-write 0 PWM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 PWM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 INVHWSYNC no description available 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 INVSWSYNC no description available 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 OMVHWSYNC no description available 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 OMVSWSYNC no description available 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 PWMSVHWSYNC no description available 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 PWMSVSWSYNC no description available 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SWPOL Channel POL synchronization is activeated by a softwaretrigger 21 1 read-write 0 The software trigger does not activate the POL register synchronization. #0 1 The software trigger activates POL register synchronization. #1 SWVHWSYNC no description available 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 SWVSWSYNC no description available 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 PWM1 Pulse Width Management Module PWM 0x0 0x0 0xA0 registers n PWM1 35 CAPFILTER Input Capture Filter Control 0x78 32 read-write n 0x0 0x0 CH0CAPFVAL Channel 0 Input Filter 0 5 read-write CH1CAPFVAL Channel 1 Input Filter 5 5 read-write CH2CAPFVAL Channel 2 Input Filter 10 5 read-write CH3CAPFVAL Channel 3 Input Filter 15 5 read-write CH0SCR Channel (n) Status And Control Register 0x18 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH1SCR Channel (n) Status And Control Register 0x2C 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH2SCR Channel (n) Status And Control Register 0x48 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH2V Channel (n) Value 0x58 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH3SCR Channel (n) Status And Control Register 0x6C 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH3V Channel (n) Value 0x80 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH4SCR Channel (n) Status And Control Register 0x98 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH4V Channel (n) Value 0xB0 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH5SCR Channel (n) Status And Control Register 0xCC 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH5V Channel (n) Value 0xE8 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CHOPOLCR Channels Output Polarity Control Register 0x70 32 read-write n 0x0 0x0 CH0POL Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH1POL Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH2POL Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH3POL Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH4POL Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH5POL Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CHOSWCR PWM CHannel Software Output Control Register 0x94 32 read-write n 0x0 0x0 CH0SWCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH0SWEN Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1SWCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1SWEN Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2SWCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2SWEN Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3SWCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3SWEN Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4SWCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4SWEN Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5SWCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5SWEN Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CNT PWM Counter Current Count Value 0x4 32 read-write n 0x0 0x0 COUNT Current Counter Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write n 0x0 0x0 CNTINIT no description available 0 16 read-write CONF Configuration 0x84 32 read-write n 0x0 0x0 BDMMODE Debug Mode 7 2 read-write CNTOFNUM Count Overflow Flag Number 0 7 read-write EVENTPSC PWM Channel Input Event Prescale Setting 16 12 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 DTSET Deadtime Paramenters Setting Register 0x68 32 read-write n 0x0 0x0 DTPSC Deadtime Prescaler Control Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 DTVAL Deadtime Value 0 6 read-write EXTTRIG PWM External Trigger 0x6C 32 read-write n 0x0 0x0 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 FDSR Fault Detect Status Register 0x74 32 read-write n 0x0 0x0 FAULTDF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FAULTDF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTDF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTDF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTDF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FFAFER Fault Filter and Fault Enable Register 0x7C 32 read-write n 0x0 0x0 FER0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FER1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FER2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FER3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FF0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FF1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FF2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FF3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write FLTPOL PWM Fault Input Polarity 0x88 32 read-write n 0x0 0x0 FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FUNCSEL PWM Features(Functions) Mode Selection Register 0x54 32 read-write n 0x0 0x0 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 FAULTMODE Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 INIT Initialize The Channels Output 1 1 read-write PWMEN2 PWM Enhance function Enable 0 1 read-write PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and PWM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and PWM counter synchronization. #1 WPDIS Write Protection Enable Register 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 INIT PWM Initialize, Include Clock and Prescale Setting 0x0 32 read-write n 0x0 0x0 CLKPSC Prescale Factor Selection 8 16 read-write CLKSRC Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the PWM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CNTMODE PWM Counter Mode Select 5 1 read-write 0 PWM counter operates in Up Counting mode. #0 1 PWM counter operates in Up-Down Counting mode. #1 CNTOF PWM Counter Overflow Flag 7 1 read-only 0 PWM counter has not overflowed. #0 1 PWM counter has overflowed. #1 CNTOIE PWM Counter Overflow Interrupt Enable 6 1 read-write 0 Disable CNTOF interrupts. Use software polling. #0 1 Enable CNTOF interrupts. An interrupt is generated when CNTOF equals one. #1 INVCR PWM Inverse Control Register 0x90 32 read-write n 0x0 0x0 PAIR0INVEN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 PAIR1INVEN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 PAIR2INVEN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 MCVR PWM Counter Max Count Value Register 0x8 32 read-write n 0x0 0x0 MCVR no description available 0 16 read-write MODESEL PWM Function Mode Selection 0x64 32 read-write n 0x0 0x0 PAIR0COMBINEN Combine Channels For Pair0 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 PAIR0COMPEN Complement Channels for Pair0 1 1 read-write 0 The channel 1 output is the same as the channel 0 output. #0 1 The channel 1 output is the complement of the channel 0 output. #1 PAIR0DECAP Dual Edge Capture Mode Captures for Pair0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 PAIR0DECAPEN Dual Edge Capture Mode Enable for Pair0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 PAIR0DTEN Deadtime Enable for Pair0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 PAIR0FAULTEN Fault Control Enable for Pair0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 PAIR0SYNCEN Synchronization Enable for Pair0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 PAIR1COMBINEN Combine Channels For Pair1 8 1 read-write 0 Channels 2 and 3 are independent. #0 1 Channels 2 and 3 are combined. #1 PAIR1COMPEN Complement Of Channel (n) For Pair1 9 1 read-write 0 The channel 3 output is the same as the channel 2 output. #0 1 The channel 3 output is the complement of the channel 2 output. #1 PAIR1DECAP Dual Edge Capture Mode Captures For Pair1 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 PAIR1DECAPEN Dual Edge Capture Mode Enable For Pair1 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 PAIR1DTEN Deadtime Enable For Pair1 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 PAIR1FAULTEN Fault Control Enable For Pair1 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 PAIR1SYNCEN Synchronization Enable For Pair1 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 PAIR2COMBINEN Combine Channels For Pair2 16 1 read-write 0 Channels 4 and 5 are independent. #0 1 Channels 4 and 5 are combined. #1 PAIR2COMPEN Complement Of Channel (n) For Pair2 17 1 read-write 0 The channel 5 output is the same as the channel 4 output. #0 1 The channel 5 output is the complement of the channel 4 output. #1 PAIR2DECAP Dual Edge Capture Mode Captures For Pair2 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 PAIR2DECAPEN Dual Edge Capture Mode Enable For Pair2 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 PAIR2DTEN Deadtime Enable For Pair2 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 PAIR2FAULTEN Fault Control Enable For Pair2 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 PAIR2SYNCEN Synchronization Enable For Pair2 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 OMCR Output Mask Control Register 0x60 32 read-write n 0x0 0x0 CH0OMEN Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OMEN Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OMEN Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OMEN Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OMEN Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OMEN Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 OUTINIT Initial Value For Channels Output 0x5C 32 read-write n 0x0 0x0 CH0OIV Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OIV Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OIV Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OIV Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OIV Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OIV Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 QEI Quadrature Encoder/Decoder Interface Configuration Register 0x80 32 read-write n 0x0 0x0 PHAFLTREN Phase A Input Filter Enable Register 7 1 read-write 0 Phase A input filter is disabled #0 1 Phase A input filter is enabled #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity #0 1 Inverted polarity #1 PHBFLTREN Phase B Input Filter Enable Register 6 1 read-write 0 Phase B input filter is disabled #0 1 Phase B input filter is enabled #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity #0 1 Inverted polarity #1 QEIEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder is Disable #0 1 Quadrature Decoder is Enable #1 QUADIR Quadrature Decoder Mode Enable 2 1 read-write 0 Quadrature Decoder is Disable #0 1 Quadrature Decoder is Enable #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode #1 TOFDIR Timer Overflow Direction in Quadrature Decoder Mode 1 1 read-write 0 TOF bit was set on the bottom of counting #0 1 TOF bit was set on the top of counting #1 STR Status Register 0x50 32 read-write n 0x0 0x0 CH0SF Channel 0 Status Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1SF Channel 1 Status Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2SF Channel 2 Status Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3SF Channel 3 Status Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4SF Channel 4 Status Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5SF Channel 5 Status Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 SYNC Synchronization 0x58 32 read-write n 0x0 0x0 ACMPTRIG PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 MAXSYNCP Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 MINSYNCP Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 OMSYNCP Output Mask Synchronization Point 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 PWM0TRIG PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 REINIT PWM Counter Reinitialization By Synchronization (PWM counter synchronization) 2 1 read-write 0 PWM counter continues to count normally. #0 1 PWM counter is updated with its initial value when the selected trigger is detected. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 SWTRIG PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write n 0x0 0x0 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 CNTVHWSYNC no description available 16 1 read-write 0 A hardware trigger does not activate the PWM counter synchronization. #0 1 A hardware trigger activates the PWM counter synchronization. #1 CNTVSWSYNC no description available 8 1 read-write 0 The software trigger does not activate the PWM counter synchronization. #0 1 The software trigger activates the PWM counter synchronization. #1 HWPOL Channel POL synchronization is activeated by a hardwaretrigger 22 1 read-write 0 The hardware trigger does not activate the POL register synchronization. #0 1 >The hardware trigger activates POL register synchronization. #1 HWTRIGMODESEL Hardware Trigger Mode 0 1 read-write 0 PWM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 PWM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 INVHWSYNC no description available 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 INVSWSYNC no description available 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 OMVHWSYNC no description available 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 OMVSWSYNC no description available 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 PWMSVHWSYNC no description available 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 PWMSVSWSYNC no description available 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SWPOL Channel POL synchronization is activeated by a softwaretrigger 21 1 read-write 0 The software trigger does not activate the POL register synchronization. #0 1 The software trigger activates POL register synchronization. #1 SWVHWSYNC no description available 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 SWVSWSYNC no description available 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 PWM2 Pulse Width Management Module PWM 0x0 0x0 0xA0 registers n PWM2 36 CAPFILTER Input Capture Filter Control 0x78 32 read-write n 0x0 0x0 CH0CAPFVAL Channel 0 Input Filter 0 5 read-write CH1CAPFVAL Channel 1 Input Filter 5 5 read-write CH2CAPFVAL Channel 2 Input Filter 10 5 read-write CH3CAPFVAL Channel 3 Input Filter 15 5 read-write CH0SCR Channel (n) Status And Control Register 0x18 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH1SCR Channel (n) Status And Control Register 0x2C 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH2SCR Channel (n) Status And Control Register 0x48 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH2V Channel (n) Value 0x58 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH3SCR Channel (n) Status And Control Register 0x6C 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH3V Channel (n) Value 0x80 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH4SCR Channel (n) Status And Control Register 0x98 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH4V Channel (n) Value 0xB0 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH5SCR Channel (n) Status And Control Register 0xCC 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH5V Channel (n) Value 0xE8 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CHOPOLCR Channels Output Polarity Control Register 0x70 32 read-write n 0x0 0x0 CH0POL Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH1POL Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH2POL Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH3POL Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH4POL Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH5POL Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CHOSWCR PWM CHannel Software Output Control Register 0x94 32 read-write n 0x0 0x0 CH0SWCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH0SWEN Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1SWCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1SWEN Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2SWCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2SWEN Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3SWCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3SWEN Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4SWCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4SWEN Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5SWCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5SWEN Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CNT PWM Counter Current Count Value 0x4 32 read-write n 0x0 0x0 COUNT Current Counter Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write n 0x0 0x0 CNTINIT no description available 0 16 read-write CONF Configuration 0x84 32 read-write n 0x0 0x0 BDMMODE Debug Mode 7 2 read-write CNTOFNUM Count Overflow Flag Number 0 7 read-write EVENTPSC PWM Channel Input Event Prescale Setting 16 12 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 DTSET Deadtime Paramenters Setting Register 0x68 32 read-write n 0x0 0x0 DTPSC Deadtime Prescaler Control Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 DTVAL Deadtime Value 0 6 read-write EXTTRIG PWM External Trigger 0x6C 32 read-write n 0x0 0x0 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 FDSR Fault Detect Status Register 0x74 32 read-write n 0x0 0x0 FAULTDF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FAULTDF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTDF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTDF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTDF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FFAFER Fault Filter and Fault Enable Register 0x7C 32 read-write n 0x0 0x0 FER0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FER1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FER2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FER3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FF0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FF1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FF2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FF3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write FLTPOL PWM Fault Input Polarity 0x88 32 read-write n 0x0 0x0 FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FUNCSEL PWM Features(Functions) Mode Selection Register 0x54 32 read-write n 0x0 0x0 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 FAULTMODE Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 INIT Initialize The Channels Output 1 1 read-write PWMEN2 PWM Enhance function Enable 0 1 read-write PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and PWM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and PWM counter synchronization. #1 WPDIS Write Protection Enable Register 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 INIT PWM Initialize, Include Clock and Prescale Setting 0x0 32 read-write n 0x0 0x0 CLKPSC Prescale Factor Selection 8 16 read-write CLKSRC Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the PWM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CNTMODE PWM Counter Mode Select 5 1 read-write 0 PWM counter operates in Up Counting mode. #0 1 PWM counter operates in Up-Down Counting mode. #1 CNTOF PWM Counter Overflow Flag 7 1 read-only 0 PWM counter has not overflowed. #0 1 PWM counter has overflowed. #1 CNTOIE PWM Counter Overflow Interrupt Enable 6 1 read-write 0 Disable CNTOF interrupts. Use software polling. #0 1 Enable CNTOF interrupts. An interrupt is generated when CNTOF equals one. #1 INVCR PWM Inverse Control Register 0x90 32 read-write n 0x0 0x0 PAIR0INVEN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 PAIR1INVEN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 PAIR2INVEN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 MCVR PWM Counter Max Count Value Register 0x8 32 read-write n 0x0 0x0 MCVR no description available 0 16 read-write MODESEL PWM Function Mode Selection 0x64 32 read-write n 0x0 0x0 PAIR0COMBINEN Combine Channels For Pair0 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 PAIR0COMPEN Complement Channels for Pair0 1 1 read-write 0 The channel 1 output is the same as the channel 0 output. #0 1 The channel 1 output is the complement of the channel 0 output. #1 PAIR0DECAP Dual Edge Capture Mode Captures for Pair0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 PAIR0DECAPEN Dual Edge Capture Mode Enable for Pair0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 PAIR0DTEN Deadtime Enable for Pair0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 PAIR0FAULTEN Fault Control Enable for Pair0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 PAIR0SYNCEN Synchronization Enable for Pair0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 PAIR1COMBINEN Combine Channels For Pair1 8 1 read-write 0 Channels 2 and 3 are independent. #0 1 Channels 2 and 3 are combined. #1 PAIR1COMPEN Complement Of Channel (n) For Pair1 9 1 read-write 0 The channel 3 output is the same as the channel 2 output. #0 1 The channel 3 output is the complement of the channel 2 output. #1 PAIR1DECAP Dual Edge Capture Mode Captures For Pair1 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 PAIR1DECAPEN Dual Edge Capture Mode Enable For Pair1 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 PAIR1DTEN Deadtime Enable For Pair1 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 PAIR1FAULTEN Fault Control Enable For Pair1 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 PAIR1SYNCEN Synchronization Enable For Pair1 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 PAIR2COMBINEN Combine Channels For Pair2 16 1 read-write 0 Channels 4 and 5 are independent. #0 1 Channels 4 and 5 are combined. #1 PAIR2COMPEN Complement Of Channel (n) For Pair2 17 1 read-write 0 The channel 5 output is the same as the channel 4 output. #0 1 The channel 5 output is the complement of the channel 4 output. #1 PAIR2DECAP Dual Edge Capture Mode Captures For Pair2 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 PAIR2DECAPEN Dual Edge Capture Mode Enable For Pair2 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 PAIR2DTEN Deadtime Enable For Pair2 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 PAIR2FAULTEN Fault Control Enable For Pair2 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 PAIR2SYNCEN Synchronization Enable For Pair2 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 OMCR Output Mask Control Register 0x60 32 read-write n 0x0 0x0 CH0OMEN Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OMEN Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OMEN Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OMEN Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OMEN Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OMEN Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 OUTINIT Initial Value For Channels Output 0x5C 32 read-write n 0x0 0x0 CH0OIV Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OIV Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OIV Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OIV Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OIV Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OIV Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 QEI Quadrature Encoder/Decoder Interface Configuration Register 0x80 32 read-write n 0x0 0x0 PHAFLTREN Phase A Input Filter Enable Register 7 1 read-write 0 Phase A input filter is disabled #0 1 Phase A input filter is enabled #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity #0 1 Inverted polarity #1 PHBFLTREN Phase B Input Filter Enable Register 6 1 read-write 0 Phase B input filter is disabled #0 1 Phase B input filter is enabled #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity #0 1 Inverted polarity #1 QEIEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder is Disable #0 1 Quadrature Decoder is Enable #1 QUADIR Quadrature Decoder Mode Enable 2 1 read-write 0 Quadrature Decoder is Disable #0 1 Quadrature Decoder is Enable #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode #1 TOFDIR Timer Overflow Direction in Quadrature Decoder Mode 1 1 read-write 0 TOF bit was set on the bottom of counting #0 1 TOF bit was set on the top of counting #1 STR Status Register 0x50 32 read-write n 0x0 0x0 CH0SF Channel 0 Status Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1SF Channel 1 Status Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2SF Channel 2 Status Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3SF Channel 3 Status Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4SF Channel 4 Status Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5SF Channel 5 Status Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 SYNC Synchronization 0x58 32 read-write n 0x0 0x0 ACMPTRIG PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 MAXSYNCP Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 MINSYNCP Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 OMSYNCP Output Mask Synchronization Point 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 PWM0TRIG PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 REINIT PWM Counter Reinitialization By Synchronization (PWM counter synchronization) 2 1 read-write 0 PWM counter continues to count normally. #0 1 PWM counter is updated with its initial value when the selected trigger is detected. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 SWTRIG PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write n 0x0 0x0 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 CNTVHWSYNC no description available 16 1 read-write 0 A hardware trigger does not activate the PWM counter synchronization. #0 1 A hardware trigger activates the PWM counter synchronization. #1 CNTVSWSYNC no description available 8 1 read-write 0 The software trigger does not activate the PWM counter synchronization. #0 1 The software trigger activates the PWM counter synchronization. #1 HWPOL Channel POL synchronization is activeated by a hardwaretrigger 22 1 read-write 0 The hardware trigger does not activate the POL register synchronization. #0 1 >The hardware trigger activates POL register synchronization. #1 HWTRIGMODESEL Hardware Trigger Mode 0 1 read-write 0 PWM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 PWM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 INVHWSYNC no description available 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 INVSWSYNC no description available 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 OMVHWSYNC no description available 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 OMVSWSYNC no description available 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 PWMSVHWSYNC no description available 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 PWMSVSWSYNC no description available 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SWPOL Channel POL synchronization is activeated by a softwaretrigger 21 1 read-write 0 The software trigger does not activate the POL register synchronization. #0 1 The software trigger activates POL register synchronization. #1 SWVHWSYNC no description available 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 SWVSWSYNC no description available 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 PWM3 Pulse Width Management Module PWM 0x0 0x0 0xA0 registers n PWM3 53 CAPFILTER Input Capture Filter Control 0x78 32 read-write n 0x0 0x0 CH0CAPFVAL Channel 0 Input Filter 0 5 read-write CH1CAPFVAL Channel 1 Input Filter 5 5 read-write CH2CAPFVAL Channel 2 Input Filter 10 5 read-write CH3CAPFVAL Channel 3 Input Filter 15 5 read-write CH0SCR Channel (n) Status And Control Register 0x18 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH1SCR Channel (n) Status And Control Register 0x2C 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH2SCR Channel (n) Status And Control Register 0x48 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH2V Channel (n) Value 0x58 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH3SCR Channel (n) Status And Control Register 0x6C 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH3V Channel (n) Value 0x80 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH4SCR Channel (n) Status And Control Register 0x98 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH4V Channel (n) Value 0xB0 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CH5SCR Channel (n) Status And Control Register 0xCC 32 read-write n 0x0 0x0 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 CHIF Channel Interrupt Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 ELSR0 Edge or Level Select Register 0 2 1 read-write ELSR1 Edge or Level Select Register 1 3 1 read-write MSR0 Channel Mode Select Register 0 4 1 read-write MSR1 Channel Mode Select Register 1 5 1 read-write CH5V Channel (n) Value 0xE8 32 read-write n 0x0 0x0 CHCVAL Channel Count Value 0 16 read-write CHOPOLCR Channels Output Polarity Control Register 0x70 32 read-write n 0x0 0x0 CH0POL Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH1POL Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH2POL Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH3POL Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH4POL Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CH5POL Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 CHOSWCR PWM CHannel Software Output Control Register 0x94 32 read-write n 0x0 0x0 CH0SWCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH0SWEN Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1SWCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1SWEN Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2SWCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2SWEN Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3SWCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3SWEN Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4SWCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4SWEN Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5SWCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5SWEN Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CNT PWM Counter Current Count Value 0x4 32 read-write n 0x0 0x0 COUNT Current Counter Value 0 16 read-write CNTIN Counter Initial Value 0x4C 32 read-write n 0x0 0x0 CNTINIT no description available 0 16 read-write CONF Configuration 0x84 32 read-write n 0x0 0x0 BDMMODE Debug Mode 7 2 read-write CNTOFNUM Count Overflow Flag Number 0 7 read-write EVENTPSC PWM Channel Input Event Prescale Setting 16 12 read-write GTBEEN Global Time Base Enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global Time Base Output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 DTSET Deadtime Paramenters Setting Register 0x68 32 read-write n 0x0 0x0 DTPSC Deadtime Prescaler Control Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 DTVAL Deadtime Value 0 6 read-write EXTTRIG PWM External Trigger 0x6C 32 read-write n 0x0 0x0 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 TRIGF Channel Trigger Flag 7 1 read-only 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 FDSR Fault Detect Status Register 0x74 32 read-write n 0x0 0x0 FAULTDF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FAULTDF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTDF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTDF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTDF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 FFAFER Fault Filter and Fault Enable Register 0x7C 32 read-write n 0x0 0x0 FER0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FER1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FER2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FER3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FF0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FF1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FF2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FF3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write FLTPOL PWM Fault Input Polarity 0x88 32 read-write n 0x0 0x0 FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A 1 at the fault input indicates a fault. #0 1 The fault input polarity is active low. A 0 at the fault input indicates a fault. #1 FUNCSEL PWM Features(Functions) Mode Selection Register 0x54 32 read-write n 0x0 0x0 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 FAULTMODE Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 INIT Initialize The Channels Output 1 1 read-write PWMEN2 PWM Enhance function Enable 0 1 read-write PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and PWM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and PWM counter synchronization. #1 WPDIS Write Protection Enable Register 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 INIT PWM Initialize, Include Clock and Prescale Setting 0x0 32 read-write n 0x0 0x0 CLKPSC Prescale Factor Selection 8 16 read-write CLKSRC Clock Source Selection 3 2 read-write 00 No clock selected. This in effect disables the PWM counter. #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CNTMODE PWM Counter Mode Select 5 1 read-write 0 PWM counter operates in Up Counting mode. #0 1 PWM counter operates in Up-Down Counting mode. #1 CNTOF PWM Counter Overflow Flag 7 1 read-only 0 PWM counter has not overflowed. #0 1 PWM counter has overflowed. #1 CNTOIE PWM Counter Overflow Interrupt Enable 6 1 read-write 0 Disable CNTOF interrupts. Use software polling. #0 1 Enable CNTOF interrupts. An interrupt is generated when CNTOF equals one. #1 INVCR PWM Inverse Control Register 0x90 32 read-write n 0x0 0x0 PAIR0INVEN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 PAIR1INVEN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 PAIR2INVEN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 MCVR PWM Counter Max Count Value Register 0x8 32 read-write n 0x0 0x0 MCVR no description available 0 16 read-write MODESEL PWM Function Mode Selection 0x64 32 read-write n 0x0 0x0 PAIR0COMBINEN Combine Channels For Pair0 0 1 read-write 0 Channels 0 and 1 are independent. #0 1 Channels 0 and 1 are combined. #1 PAIR0COMPEN Complement Channels for Pair0 1 1 read-write 0 The channel 1 output is the same as the channel 0 output. #0 1 The channel 1 output is the complement of the channel 0 output. #1 PAIR0DECAP Dual Edge Capture Mode Captures for Pair0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 PAIR0DECAPEN Dual Edge Capture Mode Enable for Pair0 2 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 PAIR0DTEN Deadtime Enable for Pair0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 PAIR0FAULTEN Fault Control Enable for Pair0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 PAIR0SYNCEN Synchronization Enable for Pair0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 PAIR1COMBINEN Combine Channels For Pair1 8 1 read-write 0 Channels 2 and 3 are independent. #0 1 Channels 2 and 3 are combined. #1 PAIR1COMPEN Complement Of Channel (n) For Pair1 9 1 read-write 0 The channel 3 output is the same as the channel 2 output. #0 1 The channel 3 output is the complement of the channel 2 output. #1 PAIR1DECAP Dual Edge Capture Mode Captures For Pair1 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 PAIR1DECAPEN Dual Edge Capture Mode Enable For Pair1 10 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 PAIR1DTEN Deadtime Enable For Pair1 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 PAIR1FAULTEN Fault Control Enable For Pair1 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 PAIR1SYNCEN Synchronization Enable For Pair1 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 PAIR2COMBINEN Combine Channels For Pair2 16 1 read-write 0 Channels 4 and 5 are independent. #0 1 Channels 4 and 5 are combined. #1 PAIR2COMPEN Complement Of Channel (n) For Pair2 17 1 read-write 0 The channel 5 output is the same as the channel 4 output. #0 1 The channel 5 output is the complement of the channel 4 output. #1 PAIR2DECAP Dual Edge Capture Mode Captures For Pair2 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 PAIR2DECAPEN Dual Edge Capture Mode Enable For Pair2 18 1 read-write 0 The Dual Edge Capture mode in this pair of channels is disabled. #0 1 The Dual Edge Capture mode in this pair of channels is enabled. #1 PAIR2DTEN Deadtime Enable For Pair2 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 PAIR2FAULTEN Fault Control Enable For Pair2 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 PAIR2SYNCEN Synchronization Enable For Pair2 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 OMCR Output Mask Control Register 0x60 32 read-write n 0x0 0x0 CH0OMEN Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OMEN Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OMEN Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OMEN Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OMEN Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OMEN Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 OUTINIT Initial Value For Channels Output 0x5C 32 read-write n 0x0 0x0 CH0OIV Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OIV Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OIV Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OIV Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OIV Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OIV Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 QEI Quadrature Encoder/Decoder Interface Configuration Register 0x80 32 read-write n 0x0 0x0 PHAFLTREN Phase A Input Filter Enable Register 7 1 read-write 0 Phase A input filter is disabled #0 1 Phase A input filter is enabled #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity #0 1 Inverted polarity #1 PHBFLTREN Phase B Input Filter Enable Register 6 1 read-write 0 Phase B input filter is disabled #0 1 Phase B input filter is enabled #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity #0 1 Inverted polarity #1 QEIEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature Decoder is Disable #0 1 Quadrature Decoder is Enable #1 QUADIR Quadrature Decoder Mode Enable 2 1 read-write 0 Quadrature Decoder is Disable #0 1 Quadrature Decoder is Enable #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode #1 TOFDIR Timer Overflow Direction in Quadrature Decoder Mode 1 1 read-write 0 TOF bit was set on the bottom of counting #0 1 TOF bit was set on the top of counting #1 STR Status Register 0x50 32 read-write n 0x0 0x0 CH0SF Channel 0 Status Flag 0 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1SF Channel 1 Status Flag 1 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2SF Channel 2 Status Flag 2 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3SF Channel 3 Status Flag 3 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4SF Channel 4 Status Flag 4 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5SF Channel 5 Status Flag 5 1 read-write 0 No channel event has occurred. #0 1 A channel event has occurred. #1 SYNC Synchronization 0x58 32 read-write n 0x0 0x0 ACMPTRIG PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 MAXSYNCP Maximum Loading Point Enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 MINSYNCP Minimum Loading Point Enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 OMSYNCP Output Mask Synchronization Point 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 PWM0TRIG PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 REINIT PWM Counter Reinitialization By Synchronization (PWM counter synchronization) 2 1 read-write 0 PWM counter continues to count normally. #0 1 PWM counter is updated with its initial value when the selected trigger is detected. #1 SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 SWTRIG PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write n 0x0 0x0 CNTINC CNTIN Register Synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 CNTVHWSYNC no description available 16 1 read-write 0 A hardware trigger does not activate the PWM counter synchronization. #0 1 A hardware trigger activates the PWM counter synchronization. #1 CNTVSWSYNC no description available 8 1 read-write 0 The software trigger does not activate the PWM counter synchronization. #0 1 The software trigger activates the PWM counter synchronization. #1 HWPOL Channel POL synchronization is activeated by a hardwaretrigger 22 1 read-write 0 The hardware trigger does not activate the POL register synchronization. #0 1 >The hardware trigger activates POL register synchronization. #1 HWTRIGMODESEL Hardware Trigger Mode 0 1 read-write 0 PWM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #0 1 PWM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. #1 INVC INVCTRL Register Synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 INVHWSYNC no description available 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 INVSWSYNC no description available 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 OMVHWSYNC no description available 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 OMVSWSYNC no description available 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 PWMSVHWSYNC no description available 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 PWMSVSWSYNC no description available 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SWOC SWOCTRL Register Synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SWPOL Channel POL synchronization is activeated by a softwaretrigger 21 1 read-write 0 The software trigger does not activate the POL register synchronization. #0 1 The software trigger activates POL register synchronization. #1 SWVHWSYNC no description available 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 SWVSWSYNC no description available 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 RTC Real-time counter RTC 0x0 0x0 0x14 registers n RTC 32 CNT RTC Count Value 0x8 32 read-write n 0x0 0x0 CNT Count Value 0 32 read-write MOD RTC Modulo Value 0x4 32 read-write n 0x0 0x0 MOD Modulo 0 32 read-write PSCNT RTC Prescaler Counter Register 0x10 32 read-write n 0x0 0x0 PSCNT RTC Prescaler Counter Register 0 20 read-write RTCPS RTC Real Time Prescaler Register 0xC 32 read-write n 0x0 0x0 RTCPS RTC Prescale Value 0 20 read-write SC RTC Status and Control Register 0x0 32 read-write n 0x0 0x0 RPIE Real-Time Prescaler Interrupt Enable 16 1 read-write RPIF Real-Time Prescaler Interrupt Flag 17 1 read-write RTCLKS Real-Time Clock Source Select 14 2 read-write 00 External clock source #00 01 Real-Time clock source is 1KHz(LPOCLK) #01 10 Internal reference clock(ICSIRCLK) #10 11 Bus Clock #11 RTCO Real-Time Counter Output 4 1 read-write RTIE Real-Time Interrupt Enable 6 1 read-write RTIF Real-Time Interrupt Flag 7 1 read-write SPI1 Serial Peripheral Interface SPI 0x0 0x0 0x18 registers n SPI1 13 CFG0 SPI Configuration Register 0 0x0 32 read-write n 0x0 0x0 CS_HOLD CS hold Count 16 8 read-write CS_SETUP CS Setup Count 24 8 read-write SCK_HIGH SCK High Count 0 8 read-write SCK_LOW SCK Low Count 8 8 read-write CFG1 SPI Configuration Register 1 0x4 32 read-write n 0x0 0x0 CONT_CS CS continuous output enable 28 1 read-write CPHA clock phase 17 1 read-write 0 the second SCK transition is the first data capture edge #0 1 the first SCK transition is the first data capture edge #1 CPOL clock polarity 16 1 read-write 0 SCK is 0 when idle #0 1 SCK is 1 when idle #1 CSOE CS hardware output enable 25 1 read-write CS_IDLE CS idle count 0 8 read-write DMARXEN DMA RX channel enable 15 1 read-write DMATXEN DMA TX channel enable 14 1 read-write FRMSIZE frame size 20 4 read-write MODFEN mode fault detect enable 26 1 read-write MODFIE mode fault interrupt enable 13 1 read-write MSBF TX MSB first Select 18 1 read-write MSTR master/slave mode selection 12 1 read-write 0 slave mode #0 1 master mode #1 RMSBF RX MSB first Select 19 1 read-write RXFIE no description available 9 1 read-write RXOIE RX buffer overflow interrupt enable 11 1 read-write TXEIE TX buffer empty interrupt enable 8 1 read-write TXUIE TX buffer underflow interrupt enable 10 1 read-write WKUEN wake up function enable(only valid for slave mode) 30 1 read-write CFG2 SPI configuration register 2 0x14 32 read-write n 0x0 0x0 MNDC Master No Overflow mode enable bit 1 1 read-write ROEN RX only mode enable bit 3 1 read-write TOEN TX only mode enable bit 2 1 read-write CMD SPI Command Register 0x8 32 read-write n 0x0 0x0 CSRLS CS release(only valid for CS continuous output) 5 1 read-write ROTRIG Master RX only mode trigger 6 1 read-write SPIEN SPI Enable 0 1 read-write SWRST software reset 4 1 read-write DATA SPI Data Register 0x10 32 read-write n 0x0 0x0 DATA Data 0 16 read-write STATUS SPI Status Register 0xC 32 read-write n 0x0 0x0 IDLEF SPI IDLE flag 8 1 read-write MEBY SPI master engine busy flag 7 1 read-write MODEF Mode error flag 4 1 read-write RXFF RX buffer Full flag 1 1 read-write RXOF RX buffer overflow flag 3 1 read-write TXEF TX buffer empty flag 0 1 read-write TXUF TX buffer underflow flag 2 1 read-write SPI2 Serial Peripheral Interface SPI 0x0 0x0 0x18 registers n SPI2 14 CFG0 SPI Configuration Register 0 0x0 32 read-write n 0x0 0x0 CS_HOLD CS hold Count 16 8 read-write CS_SETUP CS Setup Count 24 8 read-write SCK_HIGH SCK High Count 0 8 read-write SCK_LOW SCK Low Count 8 8 read-write CFG1 SPI Configuration Register 1 0x4 32 read-write n 0x0 0x0 CONT_CS CS continuous output enable 28 1 read-write CPHA clock phase 17 1 read-write 0 the second SCK transition is the first data capture edge #0 1 the first SCK transition is the first data capture edge #1 CPOL clock polarity 16 1 read-write 0 SCK is 0 when idle #0 1 SCK is 1 when idle #1 CSOE CS hardware output enable 25 1 read-write CS_IDLE CS idle count 0 8 read-write DMARXEN DMA RX channel enable 15 1 read-write DMATXEN DMA TX channel enable 14 1 read-write FRMSIZE frame size 20 4 read-write MODFEN mode fault detect enable 26 1 read-write MODFIE mode fault interrupt enable 13 1 read-write MSBF TX MSB first Select 18 1 read-write MSTR master/slave mode selection 12 1 read-write 0 slave mode #0 1 master mode #1 RMSBF RX MSB first Select 19 1 read-write RXFIE no description available 9 1 read-write RXOIE RX buffer overflow interrupt enable 11 1 read-write TXEIE TX buffer empty interrupt enable 8 1 read-write TXUIE TX buffer underflow interrupt enable 10 1 read-write WKUEN wake up function enable(only valid for slave mode) 30 1 read-write CFG2 SPI configuration register 2 0x14 32 read-write n 0x0 0x0 MNDC Master No Overflow mode enable bit 1 1 read-write ROEN RX only mode enable bit 3 1 read-write TOEN TX only mode enable bit 2 1 read-write CMD SPI Command Register 0x8 32 read-write n 0x0 0x0 CSRLS CS release(only valid for CS continuous output) 5 1 read-write ROTRIG Master RX only mode trigger 6 1 read-write SPIEN SPI Enable 0 1 read-write SWRST software reset 4 1 read-write DATA SPI Data Register 0x10 32 read-write n 0x0 0x0 DATA Data 0 16 read-write STATUS SPI Status Register 0xC 32 read-write n 0x0 0x0 IDLEF SPI IDLE flag 8 1 read-write MEBY SPI master engine busy flag 7 1 read-write MODEF Mode error flag 4 1 read-write RXFF RX buffer Full flag 1 1 read-write RXOF RX buffer overflow flag 3 1 read-write TXEF TX buffer empty flag 0 1 read-write TXUF TX buffer underflow flag 2 1 read-write TIMER Timer Setting TIMER 0x0 0x0 0x100 registers n MCR Timer Module Control Regitser 0x0 32 read-write n 0x0 0x0 MDIS Timers Module Disable Register 1 1 read-write 0 Timers are enabled. #0 1 Timers are disabled. #1 TIMER0 Timer0 Function TIMER0 0x0 0x0 0x10 registers n TIMER0 29 CVAL Timer Current Count Value Register 0x4 32 read-only n 0x0 0x0 CNT Current Timer Count Value 0 32 read-only INIT Timer Initialize Control Register 0x8 32 read-write n 0x0 0x0 LINKEN Timer Link Mode 2 1 read-write 0 Timer is not linked,Timer is seperated. #0 1 Timer is Linked to previous timer. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TIMEREN Timer Enable 0 1 read-write 0 Timer is disabled. #0 1 Timer is enabled. #1 INITVAL Timer Init Load Value Register 0x0 32 read-write n 0x0 0x0 LDVAL Timer Init Load Value 0 32 read-write TF Timer Flag Register 0xC 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 TIMER1 Timer1 Function TIMER1 0x0 0x0 0x10 registers n TIMER1 30 CVAL Timer Current Count Value Register 0x4 32 read-only n 0x0 0x0 CNT Current Timer Count Value 0 32 read-only INIT Timer Initialize Control Register 0x8 32 read-write n 0x0 0x0 LINKEN Timer Link Mode 2 1 read-write 0 Timer is not linked,Timer is seperated. #0 1 Timer is Linked to previous timer. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TIMEREN Timer Enable 0 1 read-write 0 Timer is disabled. #0 1 Timer is enabled. #1 INITVAL Timer Init Load Value Register 0x0 32 read-write n 0x0 0x0 LDVAL Timer Init Load Value 0 32 read-write TF Timer Flag Register 0xC 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 TIMER2 Timer2 Function TIMER2 0x0 0x0 0x10 registers n TIMER2 47 CVAL Timer Current Count Value Register 0x4 32 read-only n 0x0 0x0 CNT Current Timer Count Value 0 32 read-only INIT Timer Initialize Control Register 0x8 32 read-write n 0x0 0x0 LINKEN Timer Link Mode 2 1 read-write 0 Timer is not linked,Timer is seperated. #0 1 Timer is Linked to previous timer. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TIMEREN Timer Enable 0 1 read-write 0 Timer is disabled. #0 1 Timer is enabled. #1 INITVAL Timer Init Load Value Register 0x0 32 read-write n 0x0 0x0 LDVAL Timer Init Load Value 0 32 read-write TF Timer Flag Register 0xC 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 TIMER3 Timer3 Function TIMER3 0x0 0x0 0x10 registers n TIMER3 48 CVAL Timer Current Count Value Register 0x4 32 read-only n 0x0 0x0 CNT Current Timer Count Value 0 32 read-only INIT Timer Initialize Control Register 0x8 32 read-write n 0x0 0x0 LINKEN Timer Link Mode 2 1 read-write 0 Timer is not linked,Timer is seperated. #0 1 Timer is Linked to previous timer. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TIMEREN Timer Enable 0 1 read-write 0 Timer is disabled. #0 1 Timer is enabled. #1 INITVAL Timer Init Load Value Register 0x0 32 read-write n 0x0 0x0 LDVAL Timer Init Load Value 0 32 read-write TF Timer Flag Register 0xC 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 TIMER4 Timer4 Function TIMER4 0x0 0x0 0x10 registers n TIMER4 49 CVAL Timer Current Count Value Register 0x4 32 read-only n 0x0 0x0 CNT Current Timer Count Value 0 32 read-only INIT Timer Initialize Control Register 0x8 32 read-write n 0x0 0x0 LINKEN Timer Link Mode 2 1 read-write 0 Timer is not linked,Timer is seperated. #0 1 Timer is Linked to previous timer. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TIMEREN Timer Enable 0 1 read-write 0 Timer is disabled. #0 1 Timer is enabled. #1 INITVAL Timer Init Load Value Register 0x0 32 read-write n 0x0 0x0 LDVAL Timer Init Load Value 0 32 read-write TF Timer Flag Register 0xC 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 TIMER5 Timer5 Function TIMER5 0x0 0x0 0x10 registers n TIMER5 50 CVAL Timer Current Count Value Register 0x4 32 read-only n 0x0 0x0 CNT Current Timer Count Value 0 32 read-only INIT Timer Initialize Control Register 0x8 32 read-write n 0x0 0x0 LINKEN Timer Link Mode 2 1 read-write 0 Timer is not linked,Timer is seperated. #0 1 Timer is Linked to previous timer. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TIMEREN Timer Enable 0 1 read-write 0 Timer is disabled. #0 1 Timer is enabled. #1 INITVAL Timer Init Load Value Register 0x0 32 read-write n 0x0 0x0 LDVAL Timer Init Load Value 0 32 read-write TF Timer Flag Register 0xC 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 TIMER6 Timer6 Function TIMER6 0x0 0x0 0x10 registers n TIMER6 51 CVAL Timer Current Count Value Register 0x4 32 read-only n 0x0 0x0 CNT Current Timer Count Value 0 32 read-only INIT Timer Initialize Control Register 0x8 32 read-write n 0x0 0x0 LINKEN Timer Link Mode 2 1 read-write 0 Timer is not linked,Timer is seperated. #0 1 Timer is Linked to previous timer. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TIMEREN Timer Enable 0 1 read-write 0 Timer is disabled. #0 1 Timer is enabled. #1 INITVAL Timer Init Load Value Register 0x0 32 read-write n 0x0 0x0 LDVAL Timer Init Load Value 0 32 read-write TF Timer Flag Register 0xC 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 TIMER7 Timer7 Function TIMER7 0x0 0x0 0x10 registers n TIMER7 52 CVAL Timer Current Count Value Register 0x4 32 read-only n 0x0 0x0 CNT Current Timer Count Value 0 32 read-only INIT Timer Initialize Control Register 0x8 32 read-write n 0x0 0x0 LINKEN Timer Link Mode 2 1 read-write 0 Timer is not linked,Timer is seperated. #0 1 Timer is Linked to previous timer. #1 TIE Timer Interrupt Enable 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TIMEREN Timer Enable 0 1 read-write 0 Timer is disabled. #0 1 Timer is enabled. #1 INITVAL Timer Init Load Value Register 0x0 32 read-write n 0x0 0x0 LDVAL Timer Init Load Value 0 32 read-write TF Timer Flag Register 0xC 32 read-write n 0x0 0x0 TIF Timer Interrupt Flag 0 1 read-write 0 Timeout has not yet occurred. #0 1 Timeout has occurred. #1 UART1 UART1 UART1 0x0 0x0 0x60 registers n UART1 1 CNTR Uart Counter time delay in RS485 mode 0x54 32 read-write n 0x0 0x0 CNTR Uart Counter time delay in RS485 mode 0 8 read-write DIV_FRAC Uart Fractional Divider Address 0x44 32 read-write n 0x0 0x0 DIV_FRAC uart fractional divider 0 8 read-write DIV_H Divisor high 8 bits register 0x8 32 read-write n 0x0 0x0 DIV_H uart baud rate divisor high 8 bits 0 8 read-write DIV_L Divisor low 8 bits register 0x4 32 read-write n 0x0 0x0 DIV_L uart baud rate divisor low 8 bits 0 8 read-write DMA uart DMA enable register 0x40 32 read-write n 0x0 0x0 RXDMAEN uart RX DMA enable bit 0 1 read-write TXDMAEN uart TX DMA enable bit 1 1 read-write EFR hardware flow control register 0x18 32 read-write n 0x0 0x0 CTS hardware transmiison flow control enable/disable bit 6 1 read-write RTS hardware reception flow control enable/disable bit 7 1 read-write FCR FIFO Control Register 0x14 32 read-write n 0x0 0x0 FIFOE RX and TX FIFO enable/disable bit 0 1 read-write GUARD uart guard time register 0x34 32 read-write n 0x0 0x0 GUARD_CNT Guard interval count value 0 4 read-write GUARD_EN Guard interval time added enabling signal 4 1 read-write IER Interrupt Enable register 0x1C 32 read-write n 0x0 0x0 EDCTS CTS_n changing interrupt enable bit 7 1 read-write EFE overflow or frame error interrupt enable bit 4 1 read-write ENE noise error interrupt enable bit 5 1 read-write EOEBI overflow error or break error interrupt enable bit 6 1 read-write EPE parity error interrupt enable bit 3 1 read-write ERXEN receiving data not empty interrupt enable bit 0 1 read-write ETC transmitting completed interrupt enable bit 2 1 read-write ETXE transmitting data empty interrupt enable bit 1 1 read-write LCR0 uart control register 0 0xC 32 read-write n 0x0 0x0 EPS odd/eveen number select bit 4 1 read-write PEN uart parity enable/disable bit 3 1 read-write SP stick parity 5 1 read-write STB Number of STOP bits 2 1 read-write SUB Sets up break 6 1 read-write WLS uart data mode select bits 0 2 read-write LCR1 uart control register 1 0x10 32 read-write n 0x0 0x0 INVRX uart rx input inverse enable/disable bit 6 1 read-write INVTX uart tx output inverse enable/disable bit 7 1 read-write LOOP uart loop back mode enable 4 1 read-write RXEN uart receiver enable 0 1 read-write TXEN uart Transmitter enable 1 1 read-write WLS2 uart 9 bit data mode enable/disable bit 5 1 read-write LSR0 Line Status Register 0 0x20 32 read-write n 0x0 0x0 BI break error flag 4 1 read-write DR Data ready flag 0 1 read-write FE frame error flag 3 1 read-write NE noise error flag 7 1 read-write OE overrun error flag 1 1 read-write PE parity error flag 2 1 read-write TC Transmitting finished flag 6 1 read-write THRE the empty flag of TX holding register or TX FIFO 5 1 read-write LSR1 Line Status Register 1 0x24 32 read-write n 0x0 0x0 CTS Hardware flow status - CTS 6 1 read-write DCTS flag of pin CTS_n signal changing 3 1 read-write FBRK LIN break occurrer flag 2 1 read-write IDLE IDLE flag 0 1 read-write RTS Hardware flow status - RTS 7 1 read-write UART_IDLE UART IDLE 5 1 read-write MULCOMCR Uart multiprocessor communication control register 0x58 32 read-write n 0x0 0x0 IDLEIE IDLE interrupt enable bit 4 1 read-write MULCOMEN Multi communication enable bit 7 1 read-write RWUCRT Receiver wakeup control 5 1 read-write WAKESEL Wakeup method select 6 1 read-write RBR RX/TX Data Register 0x0 32 read-write n 0x0 0x0 RBR_THR RX/TX Data Register 0 8 read-write RS485CR Uart RS485 control register 0x4C 32 read-write n 0x0 0x0 DLYEN Delay insert between the last stop bit and rts_n or dtr_n de-assertion 4 1 read-write INVPOL inverse the polarity of rts_n 5 1 read-write RS485EN RS485 mode enable bit 7 1 read-write SLADDR Uart address for wake up 0x50 32 read-write n 0x0 0x0 SLADDR slave address for RS485 0 8 read-write SLEEP uart sleep enable register 0x3C 32 read-write n 0x0 0x0 SLEEP_EN uart sleep function enable bit 0 1 read-write SMP_CNT uart sample counter register 0x28 32 read-write n 0x0 0x0 SMP_CNT uart sample counter 0 2 read-write UART2 UART2 UART2 0x0 0x0 0x60 registers n UART2 2 CNTR Uart Counter time delay in RS485 mode 0x54 32 read-write n 0x0 0x0 CNTR Uart Counter time delay in RS485 mode 0 8 read-write DIV_FRAC Uart Fractional Divider Address 0x44 32 read-write n 0x0 0x0 DIV_FRAC uart fractional divider 0 8 read-write DIV_H Divisor high 8 bits register 0x8 32 read-write n 0x0 0x0 DIV_H uart baud rate divisor high 8 bits 0 8 read-write DIV_L Divisor low 8 bits register 0x4 32 read-write n 0x0 0x0 DIV_L uart baud rate divisor low 8 bits 0 8 read-write DMA uart DMA enable register 0x40 32 read-write n 0x0 0x0 RXDMAEN uart RX DMA enable bit 0 1 read-write TXDMAEN uart TX DMA enable bit 1 1 read-write EFR hardware flow control register 0x18 32 read-write n 0x0 0x0 CTS hardware transmiison flow control enable/disable bit 6 1 read-write RTS hardware reception flow control enable/disable bit 7 1 read-write FCR FIFO Control Register 0x14 32 read-write n 0x0 0x0 FIFOE RX and TX FIFO enable/disable bit 0 1 read-write GUARD uart guard time register 0x34 32 read-write n 0x0 0x0 GUARD_CNT Guard interval count value 0 4 read-write GUARD_EN Guard interval time added enabling signal 4 1 read-write IER Interrupt Enable register 0x1C 32 read-write n 0x0 0x0 EDCTS CTS_n changing interrupt enable bit 7 1 read-write EFE overflow or frame error interrupt enable bit 4 1 read-write ENE noise error interrupt enable bit 5 1 read-write EOEBI overflow error or break error interrupt enable bit 6 1 read-write EPE parity error interrupt enable bit 3 1 read-write ERXEN receiving data not empty interrupt enable bit 0 1 read-write ETC transmitting completed interrupt enable bit 2 1 read-write ETXE transmitting data empty interrupt enable bit 1 1 read-write LCR0 uart control register 0 0xC 32 read-write n 0x0 0x0 EPS odd/eveen number select bit 4 1 read-write PEN uart parity enable/disable bit 3 1 read-write SP stick parity 5 1 read-write STB Number of STOP bits 2 1 read-write SUB Sets up break 6 1 read-write WLS uart data mode select bits 0 2 read-write LCR1 uart control register 1 0x10 32 read-write n 0x0 0x0 INVRX uart rx input inverse enable/disable bit 6 1 read-write INVTX uart tx output inverse enable/disable bit 7 1 read-write LOOP uart loop back mode enable 4 1 read-write RXEN uart receiver enable 0 1 read-write TXEN uart Transmitter enable 1 1 read-write WLS2 uart 9 bit data mode enable/disable bit 5 1 read-write LSR0 Line Status Register 0 0x20 32 read-write n 0x0 0x0 BI break error flag 4 1 read-write DR Data ready flag 0 1 read-write FE frame error flag 3 1 read-write NE noise error flag 7 1 read-write OE overrun error flag 1 1 read-write PE parity error flag 2 1 read-write TC Transmitting finished flag 6 1 read-write THRE the empty flag of TX holding register or TX FIFO 5 1 read-write LSR1 Line Status Register 1 0x24 32 read-write n 0x0 0x0 CTS Hardware flow status - CTS 6 1 read-write DCTS flag of pin CTS_n signal changing 3 1 read-write FBRK LIN break occurrer flag 2 1 read-write IDLE IDLE flag 0 1 read-write RTS Hardware flow status - RTS 7 1 read-write UART_IDLE UART IDLE 5 1 read-write MULCOMCR Uart multiprocessor communication control register 0x58 32 read-write n 0x0 0x0 IDLEIE IDLE interrupt enable bit 4 1 read-write MULCOMEN Multi communication enable bit 7 1 read-write RWUCRT Receiver wakeup control 5 1 read-write WAKESEL Wakeup method select 6 1 read-write RBR RX/TX Data Register 0x0 32 read-write n 0x0 0x0 RBR_THR RX/TX Data Register 0 8 read-write RS485CR Uart RS485 control register 0x4C 32 read-write n 0x0 0x0 DLYEN Delay insert between the last stop bit and rts_n or dtr_n de-assertion 4 1 read-write INVPOL inverse the polarity of rts_n 5 1 read-write RS485EN RS485 mode enable bit 7 1 read-write SLADDR Uart address for wake up 0x50 32 read-write n 0x0 0x0 SLADDR slave address for RS485 0 8 read-write SLEEP uart sleep enable register 0x3C 32 read-write n 0x0 0x0 SLEEP_EN uart sleep function enable bit 0 1 read-write SMP_CNT uart sample counter register 0x28 32 read-write n 0x0 0x0 SMP_CNT uart sample counter 0 2 read-write UART3 UART3 UART3 0x0 0x0 0x60 registers n UART3 3 CNTR Uart Counter time delay in RS485 mode 0x54 32 read-write n 0x0 0x0 CNTR Uart Counter time delay in RS485 mode 0 8 read-write DIV_FRAC Uart Fractional Divider Address 0x44 32 read-write n 0x0 0x0 DIV_FRAC uart fractional divider 0 8 read-write DIV_H Divisor high 8 bits register 0x8 32 read-write n 0x0 0x0 DIV_H uart baud rate divisor high 8 bits 0 8 read-write DIV_L Divisor low 8 bits register 0x4 32 read-write n 0x0 0x0 DIV_L uart baud rate divisor low 8 bits 0 8 read-write DMA uart DMA enable register 0x40 32 read-write n 0x0 0x0 RXDMAEN uart RX DMA enable bit 0 1 read-write TXDMAEN uart TX DMA enable bit 1 1 read-write EFR hardware flow control register 0x18 32 read-write n 0x0 0x0 CTS hardware transmiison flow control enable/disable bit 6 1 read-write RTS hardware reception flow control enable/disable bit 7 1 read-write FCR FIFO Control Register 0x14 32 read-write n 0x0 0x0 FIFOE RX and TX FIFO enable/disable bit 0 1 read-write GUARD uart guard time register 0x34 32 read-write n 0x0 0x0 GUARD_CNT Guard interval count value 0 4 read-write GUARD_EN Guard interval time added enabling signal 4 1 read-write IER Interrupt Enable register 0x1C 32 read-write n 0x0 0x0 EDCTS CTS_n changing interrupt enable bit 7 1 read-write EFE overflow or frame error interrupt enable bit 4 1 read-write ENE noise error interrupt enable bit 5 1 read-write EOEBI overflow error or break error interrupt enable bit 6 1 read-write EPE parity error interrupt enable bit 3 1 read-write ERXEN receiving data not empty interrupt enable bit 0 1 read-write ETC transmitting completed interrupt enable bit 2 1 read-write ETXE transmitting data empty interrupt enable bit 1 1 read-write LCR0 uart control register 0 0xC 32 read-write n 0x0 0x0 EPS odd/eveen number select bit 4 1 read-write PEN uart parity enable/disable bit 3 1 read-write SP stick parity 5 1 read-write STB Number of STOP bits 2 1 read-write SUB Sets up break 6 1 read-write WLS uart data mode select bits 0 2 read-write LCR1 uart control register 1 0x10 32 read-write n 0x0 0x0 INVRX uart rx input inverse enable/disable bit 6 1 read-write INVTX uart tx output inverse enable/disable bit 7 1 read-write LOOP uart loop back mode enable 4 1 read-write RXEN uart receiver enable 0 1 read-write TXEN uart Transmitter enable 1 1 read-write WLS2 uart 9 bit data mode enable/disable bit 5 1 read-write LSR0 Line Status Register 0 0x20 32 read-write n 0x0 0x0 BI break error flag 4 1 read-write DR Data ready flag 0 1 read-write FE frame error flag 3 1 read-write NE noise error flag 7 1 read-write OE overrun error flag 1 1 read-write PE parity error flag 2 1 read-write TC Transmitting finished flag 6 1 read-write THRE the empty flag of TX holding register or TX FIFO 5 1 read-write LSR1 Line Status Register 1 0x24 32 read-write n 0x0 0x0 CTS Hardware flow status - CTS 6 1 read-write DCTS flag of pin CTS_n signal changing 3 1 read-write FBRK LIN break occurrer flag 2 1 read-write IDLE IDLE flag 0 1 read-write RTS Hardware flow status - RTS 7 1 read-write UART_IDLE UART IDLE 5 1 read-write MULCOMCR Uart multiprocessor communication control register 0x58 32 read-write n 0x0 0x0 IDLEIE IDLE interrupt enable bit 4 1 read-write MULCOMEN Multi communication enable bit 7 1 read-write RWUCRT Receiver wakeup control 5 1 read-write WAKESEL Wakeup method select 6 1 read-write RBR RX/TX Data Register 0x0 32 read-write n 0x0 0x0 RBR_THR RX/TX Data Register 0 8 read-write RS485CR Uart RS485 control register 0x4C 32 read-write n 0x0 0x0 DLYEN Delay insert between the last stop bit and rts_n or dtr_n de-assertion 4 1 read-write INVPOL inverse the polarity of rts_n 5 1 read-write RS485EN RS485 mode enable bit 7 1 read-write SLADDR Uart address for wake up 0x50 32 read-write n 0x0 0x0 SLADDR slave address for RS485 0 8 read-write SLEEP uart sleep enable register 0x3C 32 read-write n 0x0 0x0 SLEEP_EN uart sleep function enable bit 0 1 read-write SMP_CNT uart sample counter register 0x28 32 read-write n 0x0 0x0 SMP_CNT uart sample counter 0 2 read-write UART4 UART4 UART4 0x0 0x0 0x60 registers n UART4 4 CNTR Uart Counter time delay in RS485 mode 0x54 32 read-write n 0x0 0x0 CNTR Uart Counter time delay in RS485 mode 0 8 read-write DIV_FRAC Uart Fractional Divider Address 0x44 32 read-write n 0x0 0x0 DIV_FRAC uart fractional divider 0 8 read-write DIV_H Divisor high 8 bits register 0x8 32 read-write n 0x0 0x0 DIV_H uart baud rate divisor high 8 bits 0 8 read-write DIV_L Divisor low 8 bits register 0x4 32 read-write n 0x0 0x0 DIV_L uart baud rate divisor low 8 bits 0 8 read-write DMA uart DMA enable register 0x40 32 read-write n 0x0 0x0 RXDMAEN uart RX DMA enable bit 0 1 read-write TXDMAEN uart TX DMA enable bit 1 1 read-write EFR hardware flow control register 0x18 32 read-write n 0x0 0x0 CTS hardware transmiison flow control enable/disable bit 6 1 read-write RTS hardware reception flow control enable/disable bit 7 1 read-write FCR FIFO Control Register 0x14 32 read-write n 0x0 0x0 FIFOE RX and TX FIFO enable/disable bit 0 1 read-write GUARD uart guard time register 0x34 32 read-write n 0x0 0x0 GUARD_CNT Guard interval count value 0 4 read-write GUARD_EN Guard interval time added enabling signal 4 1 read-write IER Interrupt Enable register 0x1C 32 read-write n 0x0 0x0 EDCTS CTS_n changing interrupt enable bit 7 1 read-write EFE overflow or frame error interrupt enable bit 4 1 read-write ENE noise error interrupt enable bit 5 1 read-write EOEBI overflow error or break error interrupt enable bit 6 1 read-write EPE parity error interrupt enable bit 3 1 read-write ERXEN receiving data not empty interrupt enable bit 0 1 read-write ETC transmitting completed interrupt enable bit 2 1 read-write ETXE transmitting data empty interrupt enable bit 1 1 read-write LCR0 uart control register 0 0xC 32 read-write n 0x0 0x0 EPS odd/eveen number select bit 4 1 read-write PEN uart parity enable/disable bit 3 1 read-write SP stick parity 5 1 read-write STB Number of STOP bits 2 1 read-write SUB Sets up break 6 1 read-write WLS uart data mode select bits 0 2 read-write LCR1 uart control register 1 0x10 32 read-write n 0x0 0x0 INVRX uart rx input inverse enable/disable bit 6 1 read-write INVTX uart tx output inverse enable/disable bit 7 1 read-write LOOP uart loop back mode enable 4 1 read-write RXEN uart receiver enable 0 1 read-write TXEN uart Transmitter enable 1 1 read-write WLS2 uart 9 bit data mode enable/disable bit 5 1 read-write LSR0 Line Status Register 0 0x20 32 read-write n 0x0 0x0 BI break error flag 4 1 read-write DR Data ready flag 0 1 read-write FE frame error flag 3 1 read-write NE noise error flag 7 1 read-write OE overrun error flag 1 1 read-write PE parity error flag 2 1 read-write TC Transmitting finished flag 6 1 read-write THRE the empty flag of TX holding register or TX FIFO 5 1 read-write LSR1 Line Status Register 1 0x24 32 read-write n 0x0 0x0 CTS Hardware flow status - CTS 6 1 read-write DCTS flag of pin CTS_n signal changing 3 1 read-write FBRK LIN break occurrer flag 2 1 read-write IDLE IDLE flag 0 1 read-write RTS Hardware flow status - RTS 7 1 read-write UART_IDLE UART IDLE 5 1 read-write MULCOMCR Uart multiprocessor communication control register 0x58 32 read-write n 0x0 0x0 IDLEIE IDLE interrupt enable bit 4 1 read-write MULCOMEN Multi communication enable bit 7 1 read-write RWUCRT Receiver wakeup control 5 1 read-write WAKESEL Wakeup method select 6 1 read-write RBR RX/TX Data Register 0x0 32 read-write n 0x0 0x0 RBR_THR RX/TX Data Register 0 8 read-write RS485CR Uart RS485 control register 0x4C 32 read-write n 0x0 0x0 DLYEN Delay insert between the last stop bit and rts_n or dtr_n de-assertion 4 1 read-write INVPOL inverse the polarity of rts_n 5 1 read-write RS485EN RS485 mode enable bit 7 1 read-write SLADDR Uart address for wake up 0x50 32 read-write n 0x0 0x0 SLADDR slave address for RS485 0 8 read-write SLEEP uart sleep enable register 0x3C 32 read-write n 0x0 0x0 SLEEP_EN uart sleep function enable bit 0 1 read-write SMP_CNT uart sample counter register 0x28 32 read-write n 0x0 0x0 SMP_CNT uart sample counter 0 2 read-write UART5 UART5 UART5 0x0 0x0 0x60 registers n UART5 5 CNTR Uart Counter time delay in RS485 mode 0x54 32 read-write n 0x0 0x0 CNTR Uart Counter time delay in RS485 mode 0 8 read-write DIV_FRAC Uart Fractional Divider Address 0x44 32 read-write n 0x0 0x0 DIV_FRAC uart fractional divider 0 8 read-write DIV_H Divisor high 8 bits register 0x8 32 read-write n 0x0 0x0 DIV_H uart baud rate divisor high 8 bits 0 8 read-write DIV_L Divisor low 8 bits register 0x4 32 read-write n 0x0 0x0 DIV_L uart baud rate divisor low 8 bits 0 8 read-write DMA uart DMA enable register 0x40 32 read-write n 0x0 0x0 RXDMAEN uart RX DMA enable bit 0 1 read-write TXDMAEN uart TX DMA enable bit 1 1 read-write EFR hardware flow control register 0x18 32 read-write n 0x0 0x0 CTS hardware transmiison flow control enable/disable bit 6 1 read-write RTS hardware reception flow control enable/disable bit 7 1 read-write FCR FIFO Control Register 0x14 32 read-write n 0x0 0x0 FIFOE RX and TX FIFO enable/disable bit 0 1 read-write GUARD uart guard time register 0x34 32 read-write n 0x0 0x0 GUARD_CNT Guard interval count value 0 4 read-write GUARD_EN Guard interval time added enabling signal 4 1 read-write IER Interrupt Enable register 0x1C 32 read-write n 0x0 0x0 EDCTS CTS_n changing interrupt enable bit 7 1 read-write EFE overflow or frame error interrupt enable bit 4 1 read-write ENE noise error interrupt enable bit 5 1 read-write EOEBI overflow error or break error interrupt enable bit 6 1 read-write EPE parity error interrupt enable bit 3 1 read-write ERXEN receiving data not empty interrupt enable bit 0 1 read-write ETC transmitting completed interrupt enable bit 2 1 read-write ETXE transmitting data empty interrupt enable bit 1 1 read-write LCR0 uart control register 0 0xC 32 read-write n 0x0 0x0 EPS odd/eveen number select bit 4 1 read-write PEN uart parity enable/disable bit 3 1 read-write SP stick parity 5 1 read-write STB Number of STOP bits 2 1 read-write SUB Sets up break 6 1 read-write WLS uart data mode select bits 0 2 read-write LCR1 uart control register 1 0x10 32 read-write n 0x0 0x0 INVRX uart rx input inverse enable/disable bit 6 1 read-write INVTX uart tx output inverse enable/disable bit 7 1 read-write LOOP uart loop back mode enable 4 1 read-write RXEN uart receiver enable 0 1 read-write TXEN uart Transmitter enable 1 1 read-write WLS2 uart 9 bit data mode enable/disable bit 5 1 read-write LSR0 Line Status Register 0 0x20 32 read-write n 0x0 0x0 BI break error flag 4 1 read-write DR Data ready flag 0 1 read-write FE frame error flag 3 1 read-write NE noise error flag 7 1 read-write OE overrun error flag 1 1 read-write PE parity error flag 2 1 read-write TC Transmitting finished flag 6 1 read-write THRE the empty flag of TX holding register or TX FIFO 5 1 read-write LSR1 Line Status Register 1 0x24 32 read-write n 0x0 0x0 CTS Hardware flow status - CTS 6 1 read-write DCTS flag of pin CTS_n signal changing 3 1 read-write FBRK LIN break occurrer flag 2 1 read-write IDLE IDLE flag 0 1 read-write RTS Hardware flow status - RTS 7 1 read-write UART_IDLE UART IDLE 5 1 read-write MULCOMCR Uart multiprocessor communication control register 0x58 32 read-write n 0x0 0x0 IDLEIE IDLE interrupt enable bit 4 1 read-write MULCOMEN Multi communication enable bit 7 1 read-write RWUCRT Receiver wakeup control 5 1 read-write WAKESEL Wakeup method select 6 1 read-write RBR RX/TX Data Register 0x0 32 read-write n 0x0 0x0 RBR_THR RX/TX Data Register 0 8 read-write RS485CR Uart RS485 control register 0x4C 32 read-write n 0x0 0x0 DLYEN Delay insert between the last stop bit and rts_n or dtr_n de-assertion 4 1 read-write INVPOL inverse the polarity of rts_n 5 1 read-write RS485EN RS485 mode enable bit 7 1 read-write SLADDR Uart address for wake up 0x50 32 read-write n 0x0 0x0 SLADDR slave address for RS485 0 8 read-write SLEEP uart sleep enable register 0x3C 32 read-write n 0x0 0x0 SLEEP_EN uart sleep function enable bit 0 1 read-write SMP_CNT uart sample counter register 0x28 32 read-write n 0x0 0x0 SMP_CNT uart sample counter 0 2 read-write UART6 UART6 UART6 0x0 0x0 0x60 registers n UART6 6 CNTR Uart Counter time delay in RS485 mode 0x54 32 read-write n 0x0 0x0 CNTR Uart Counter time delay in RS485 mode 0 8 read-write DIV_FRAC Uart Fractional Divider Address 0x44 32 read-write n 0x0 0x0 DIV_FRAC uart fractional divider 0 8 read-write DIV_H Divisor high 8 bits register 0x8 32 read-write n 0x0 0x0 DIV_H uart baud rate divisor high 8 bits 0 8 read-write DIV_L Divisor low 8 bits register 0x4 32 read-write n 0x0 0x0 DIV_L uart baud rate divisor low 8 bits 0 8 read-write DMA uart DMA enable register 0x40 32 read-write n 0x0 0x0 RXDMAEN uart RX DMA enable bit 0 1 read-write TXDMAEN uart TX DMA enable bit 1 1 read-write EFR hardware flow control register 0x18 32 read-write n 0x0 0x0 CTS hardware transmiison flow control enable/disable bit 6 1 read-write RTS hardware reception flow control enable/disable bit 7 1 read-write FCR FIFO Control Register 0x14 32 read-write n 0x0 0x0 FIFOE RX and TX FIFO enable/disable bit 0 1 read-write GUARD uart guard time register 0x34 32 read-write n 0x0 0x0 GUARD_CNT Guard interval count value 0 4 read-write GUARD_EN Guard interval time added enabling signal 4 1 read-write IER Interrupt Enable register 0x1C 32 read-write n 0x0 0x0 EDCTS CTS_n changing interrupt enable bit 7 1 read-write EFE overflow or frame error interrupt enable bit 4 1 read-write ENE noise error interrupt enable bit 5 1 read-write EOEBI overflow error or break error interrupt enable bit 6 1 read-write EPE parity error interrupt enable bit 3 1 read-write ERXEN receiving data not empty interrupt enable bit 0 1 read-write ETC transmitting completed interrupt enable bit 2 1 read-write ETXE transmitting data empty interrupt enable bit 1 1 read-write LCR0 uart control register 0 0xC 32 read-write n 0x0 0x0 EPS odd/eveen number select bit 4 1 read-write PEN uart parity enable/disable bit 3 1 read-write SP stick parity 5 1 read-write STB Number of STOP bits 2 1 read-write SUB Sets up break 6 1 read-write WLS uart data mode select bits 0 2 read-write LCR1 uart control register 1 0x10 32 read-write n 0x0 0x0 INVRX uart rx input inverse enable/disable bit 6 1 read-write INVTX uart tx output inverse enable/disable bit 7 1 read-write LOOP uart loop back mode enable 4 1 read-write RXEN uart receiver enable 0 1 read-write TXEN uart Transmitter enable 1 1 read-write WLS2 uart 9 bit data mode enable/disable bit 5 1 read-write LINCR Uart Lin control register 0x5C 32 read-write n 0x0 0x0 LABAUDEN 0x55 used to auto baud-rate detection enable bit 3 1 read-write LBRKDL LIN Mode break detect length 5 1 read-write LBRKIE LIN Break character detect interrupt enable bit 6 1 read-write LINEN LIN Mode enable bit 7 1 read-write SDBRK LIN Mode whether transmit enable bit 4 1 read-write LSR0 Line Status Register 0 0x20 32 read-write n 0x0 0x0 BI break error flag 4 1 read-write DR Data ready flag 0 1 read-write FE frame error flag 3 1 read-write NE noise error flag 7 1 read-write OE overrun error flag 1 1 read-write PE parity error flag 2 1 read-write TC Transmitting finished flag 6 1 read-write THRE the empty flag of TX holding register or TX FIFO 5 1 read-write LSR1 Line Status Register 1 0x24 32 read-write n 0x0 0x0 CTS Hardware flow status - CTS 6 1 read-write DCTS flag of pin CTS_n signal changing 3 1 read-write FBRK LIN break occurrer flag 2 1 read-write IDLE IDLE flag 0 1 read-write RTS Hardware flow status - RTS 7 1 read-write UART_IDLE UART IDLE 5 1 read-write MULCOMCR Uart multiprocessor communication control register 0x58 32 read-write n 0x0 0x0 IDLEIE IDLE interrupt enable bit 4 1 read-write MULCOMEN Multi communication enable bit 7 1 read-write RWUCRT Receiver wakeup control 5 1 read-write WAKESEL Wakeup method select 6 1 read-write RBR RX/TX Data Register 0x0 32 read-write n 0x0 0x0 RBR_THR RX/TX Data Register 0 8 read-write RS485CR Uart RS485 control register 0x4C 32 read-write n 0x0 0x0 DLYEN Delay insert between the last stop bit and rts_n or dtr_n de-assertion 4 1 read-write INVPOL inverse the polarity of rts_n 5 1 read-write RS485EN RS485 mode enable bit 7 1 read-write SLADDR Uart address for wake up 0x50 32 read-write n 0x0 0x0 SLADDR slave address for RS485 0 8 read-write SLEEP uart sleep enable register 0x3C 32 read-write n 0x0 0x0 SLEEP_EN uart sleep function enable bit 0 1 read-write SMP_CNT uart sample counter register 0x28 32 read-write n 0x0 0x0 SMP_CNT uart sample counter 0 2 read-write WDOG Watchdog timer WDOG 0x0 0x0 0x14 registers n WDOG 33 CNT Watchdog Counter Value 0x8 32 read-write n 0x0 0x0 CNT Watchdog Counter Value 0 32 read-write CS1 Watchdog Control and Status Register 1 0x0 32 read-write n 0x0 0x0 DBG Debug Enable 2 1 read-write 0 Watchdog disabled in chip debug mode. #0 1 Watchdog enabled in chip debug mode. #1 EN Watchdog Enable 7 1 read-write 0 Watchdog disabled. #0 1 Watchdog enabled. #1 INT Watchdog Interrupt 6 1 read-write 0 Watchdog interrupts are disabled. Watchdog resets are not delayed. #0 1 Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks. #1 STOP Stop Enable 0 1 read-write 0 Watchdog disabled in chip stop mode. #0 1 Watchdog enabled in chip stop mode. #1 TST Watchdog Test 3 2 read-write 00 Watchdog test mode disabled. #00 01 Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. #01 10 Watchdog test mode enabled, only the low byte is used. WDOG_CNTL is compared with WDOG_TOVALL. #10 11 Watchdog test mode enabled, only the high byte is used. WDOG_CNTH is compared with WDOG_TOVALH. #11 UPDATE Allow updates 5 1 read-write 0 Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. #0 1 Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. #1 WAIT Wait Enable 1 1 read-write 0 Watchdog disabled in chip wait mode. #0 1 Watchdog enabled in chip wait mode. #1 CS2 Watchdog Control and Status Register 2 0x4 32 read-write n 0x0 0x0 CLK Watchdog Clock 0 2 read-write 00 Bus clock. #00 01 1 kHz internal low-power oscillator (LPOCLK). #01 10 32 kHz internal oscillator (ICSIRCLK). #10 11 External clock source. #11 FLG Watchdog Interrupt Flag 6 1 read-write 0 No interrupt occurred. #0 1 An interrupt occurred. #1 PRES Watchdog Prescalar 4 1 read-write 0 256 prescalar disabled. #0 1 256 prescalar enabled. #1 WIN Watchdog Window 7 1 read-write 0 Window mode disabled. #0 1 Window mode enabled. #1 TOVAL Watchdog Timeout Value Register 0xC 32 read-write n 0x0 0x0 TOVAL WatchDog Timeout Value 0 32 read-write WIN Watchdog Window Register 0x10 32 read-write n 0x0 0x0 WIN Watchdog Window 0 32 read-write