CMS
BAT32G135
2024.04.25
ARM 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48MHz, etc.
CM0+
r0p1
little
2
false
8
32
ADC
A/D Converter
ADC
0x0
0x0
0x100
registers
n
ADC
ADC interrupt request
21
ADCR
12-bit A/D conversion result register
0xE
16
read-write
n
0x0
0x0
ADCRH
Higher 8-bit A/D conversion result register
ADCR
0xF
8
read-write
n
0x0
0x0
ADFLG
A/D flag register
0x16
8
read-write
n
0x0
0x0
ADLL
Conversion result comparison lower limit setting register
0xA
8
read-write
n
0x0
0x0
ADM0
A/D mode register 0
0x0
8
read-write
n
0x0
0x0
ADCE
A/D enable
0
1
ADCS
A/D conversion operation control
7
8
FR
A/D conversion clock (fAD) select
3
6
ADM1
A/D mode register 1
0x2
8
read-write
n
0x0
0x0
ADMD
A/D conversion channel select mode
7
8
Select
Select mode
0
Scan
Scan mode
1
ADMODE
A/D mode select
0
2
ADSCM
A/D conversion mode
3
4
Sequential
Sequential conversion mode
0
OneShot
One-shot conversion mode
1
ADM2
A/D mode register 2
0x4
8
read-write
n
0x0
0x0
ADRCK
the upper limit and lower limit conversion result values
3
4
ADREFM
Selection of the - side reference voltage of A/D converter
5
6
VSS
Supplied from VSS
0
AVREFM
Supplied from AVREFM
1
ADREFP
Selection of the + side reference voltage of A/D converter
6
8
VDD
Supplied from VDD
0b00
AVREFP0
Supplied from AVREFP
0b01
AVREFP1
Supplied from inside AVREF of A/D
0b10
CHRDE
output CH number in A/D conversion result in Scan mode
1
2
ADNDIS
A/D charge/discharge control register
0x11
8
read-write
n
0x0
0x0
ADNSMP
A/D sampling time control register
0xC
8
read-write
n
0x0
0x0
ADS
Analog input channel specification register
0x8
8
read-write
n
0x0
0x0
ADSMPWAIT
A/D sampling wait control register
0x15
8
read-write
n
0x0
0x0
ADTES
A/D test register
0x10
8
read-write
n
0x0
0x0
ADTRG
A/D mode register 2
0x6
8
read-write
n
0x0
0x0
ADTMD
A/D conversion trigger mode
6
8
ADTRS
A/D hard trigger select
0
2
ADUL
Conversion result comparison upper limit setting register
0xB
8
read-write
n
0x0
0x0
BGR
Temperature Sensor calibration data
BGR
0x0
0x0
0x8
registers
n
VBG25
The A/D conversion value of VBGR at 25 degrees and 3.0V reference voltage
0x4
-1
read-only
n
0x0
0x0
VBG85
The A/D conversion value of VBGR at 85 degrees and 3.0V reference voltage
0x0
-1
read-only
n
0x0
0x0
CGC
Clock Generate Control
CLK
0x0
0x0
0x2000
registers
n
LVI
Low Voltage detection interrupt
0
CKC
System clock control register
0x4
8
read-write
n
0x0
0x0
CLS
Status of CPU/peripheral hardware clock (fCLK)
7
8
read-only
fMAIN
Main system clock (fMAIN)
0
fSUB
Subsystem clock (fSUB)
1
CSS
Selection of CPU/peripheral hardware clock (fCLK)
6
7
read-write
fMAIN
Main system clock (fMAIN)
0
fSUB
Subsystem clock (fSUB)
1
MCM0
Main system clock (fMAIN) operation control
4
5
read-write
fIH
Select the high-speed on-chip oscillator clock (fIH) as the main system clock (fMAIN)
0
fMX
Select the high-speed system clock (fMX) as the main system clock (fMAIN)
1
MCS
Status of Main system clock (fMAIN)
5
6
read-only
fIH
High-speed on-chip oscillator clock (fIH)
0
fMX
High-speed system clock (fMX)
1
CMC
Clock operaton Mode Control Register
0x0
8
read-write
n
0x0
0x0
AMPH
Control of X1 clock oscillation frequency
0
1
read-write
AMPHS
Control of XT1 clock oscillation frequency
1
3
read-write
EXCLK
External Clock input mode
7
8
read-write
EXCLKS
External Clock input mode
5
6
read-write
OSCSEL
Main OSC Select
6
7
read-write
OSCSELS
Sub OSC Select
4
5
read-write
CSC
Clock operation Status Register
0x1
8
read-write
n
0x0
0x0
HIOSTOP
High-speed on-chip oscillator clock operation control
0
1
read-write
START
High-speed on-chip oscillator operating
0
STOP
High-speed on-chip oscillator stopped
1
MSTOP
High-speed system clock operation control
7
8
read-write
START
X1 oscillator operating or External clock from EXCLK pin is valid
0
STOP
X1 oscillator stop or External clock from EXCLK pin is invalid
1
XTSTOP
Subsystem clock operation control
6
7
read-write
START
XT1 oscillator operating or External clock from EXCLKS pin is valid
0
STOP
XT1 oscillator stop or External clock from EXCLKS pin is invalid
1
HIOTRM
High-speed on-chip oscillator trimming register
0x1800
8
read-write
n
0x0
0x0
HOCODIV
High-speed on-chip oscillator frequency select register
0x1820
8
read-write
n
0x0
0x0
LOSCSEL
LOCO Frequency Select register
0x5
8
read-write
n
0x0
0x0
LOSCSEL
LOCO Frequency Select
0
1
Disabled
LOCO's Frequency is 15K
0
Enable
LOCO's Frequency is 30K
1
OSMC
Subsystem clock supply mode control register
0x23
8
read-write
n
0x0
0x0
RTCLPC
Setting in DEEPSLEEP mode or SLEEP mode while subsystem clock is selected as CPU clock
7
8
read-write
Enable
Enables supply of subsystem clock to peripheral function
0
Disable
Stops supply of subsystem clock to peripheral functions other than real-time clock and 15-bit interval timer.
1
WUTMMCK0
Selection of operation clock for real-time clock, 15-bit interval timer
4
5
read-write
fSUB
The subsystem clock is selected as the operation clock for the real-time clock and the 15-bit interval timer. The low-speed on-chip oscillator cannot be selected as the count source for timer A.
0
fIL
The low-speed on-chip oscillator clock is selected as the operation clock for the real-time clock and the 15-bit interval timer. Either the low-speed on-chip oscillator or the subsystem clock can be selected as the count source for timer A.
1
OSTC
Oscillation stabilization time counter status
0x2
8
read-only
n
0x0
0x0
OSTS
Oscillation stabilization time select register
0x3
8
read-write
n
0x0
0x0
PER0
Peripheral enable register 0
0x20
8
read-write
n
0x0
0x0
ADCEN
Control of the ADC input clock
5
6
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
IICA0EN
Control of the IICA0 input clock
4
5
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
IRDAEN
Control of the IRDA input clock
6
7
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
RTCEN
Control of the RTC input clock
7
8
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
SCI0EN
Control of the SCI0 input clock
2
3
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
SCI1EN
Control of the SCI1 input clock
3
4
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
TM40EN
Control of the TM40 input clock
0
1
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
TM41EN
Control of the TM41 input clock
1
2
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
PER1
Peripheral enable register 1
0x41A
8
read-write
n
0x0
0x0
DMAEN
Control of the DMA input clock
3
4
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
EPWMEN
Control of the EPWM input clock
2
3
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
PGACMPEN
Control of the PGACMP input clock
5
6
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
SPIEN
Control of the SPI input clock
7
8
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
PRCR
LOSCSEL's Protect register
0x6
8
read-write
n
0x0
0x0
SUBCKSEL
SubSystem Clock select register
0x7
8
read-write
n
0x0
0x0
SELLOSC
Select LOSC or SUBOSC
0
1
SUBOSC
Select SUBOSC as the SubSystem clock
0
LOSC
Select LOSC as the SubSystem clock
1
CMP
Comparator
CMP
0x0
0x0
0x100
registers
n
CMP0
CMP0 interrupt request
24
CMP1
CMP1 interrupt request
25
C0RVM
Comparator internal reference voltage select register 0
0x4
-1
read-write
n
0x0
0x0
C1RVM
Comparator internal reference voltage select register 1
0x5
-1
read-write
n
0x0
0x0
CMPSEL0
Comparator 0 input signal selection control register
0xA
-1
read-write
n
0x0
0x0
C0REFS
Selection of the input signal on the negative side of Comparator 0
0
2
CMP0SEL
Selection of the input signal on the positive side of Comparator 0
7
8
CMPSEL1
Comparator 1 input signal selection control register
0xB
-1
read-write
n
0x0
0x0
C1REFS
Selection of the input signal on the negative side of Comparator 1
0
3
CMP1SEL
Selection of the input signal on the positive side of Comparator 1
6
8
COMPFIR
Comparator filter control register
0x1
-1
read-write
n
0x0
0x0
C0EDG
Comparator 0 edge detection selection
3
4
C0EPO
Comparator 0 edge polarity switching
2
3
C0FCK
Comparator 0 filter selection
0
2
C1EDG
Comparator 1 edge detection selection
7
8
C1EPO
Comparator 1 edge polarity switching
6
7
C1FCK
Comparator 1 filter selection
4
6
COMPMDR
Comparator mode setting register
0x0
-1
read-write
n
0x0
0x0
C0ENB
Comparator 0 operation 1enable
0
1
C0MON
Comparator 0 monitor flag
3
4
C1ENB
Comparator 1 operation enable
4
5
C1MON
Comparator 1 monitor flag
7
8
COMPOCR
Comparator output control register
0x2
-1
read-write
n
0x0
0x0
C0IE
Comparator 0 interrupt request enable
0
1
C0OE
VOUT0 pin output enable
1
2
C0OP
VOUT0 output polarity selection
2
3
C1IE
Comparator 1 interrupt request enable
4
5
C1OE
VOUT1 pin output enable
5
6
C1OP
VOUT1 output polarity selection
6
7
C1OTWMD
TIMER WINDOW output mode control bit of comparator 1
7
8
CVRCTL
Comparator internal reference voltage control register
0x3
-1
read-write
n
0x0
0x0
CVRE0
Control bit for internal reference voltage 0
1
2
CVRE1
Control bit for internal reference voltage 1
5
6
CVRVS0
Power supply selection bit for internal reference voltage
0
1
CVRVS1
Ground selection bit for internal reference voltage
4
5
CRC
General Purpose CRC
CRC
0x0
0x0
0x100
registers
n
CRCD
CRC data register
0xA
16
read-write
n
0x0
0x0
CRCIN
CRC input register
0xBC
8
read-write
n
0x0
0x0
DBG
DBG Controller
DBG
0x0
0x0
0x100
registers
n
DBGSTOPCR
Debug Stop Control register
0x4
-1
read-write
n
0x0
0x0
FRZEN0
Stop Timer family macros when cpu halted
0
1
FRZEN1
Stop Communation family macros when cpu halted
1
2
RESMSK
Mask internal reset in debug mode
2
3
RPERMSK
Mask RAM parity error in debug mode
16
17
SWDIS
SWD Disable
24
25
DBGSTR
Debug status register
0x0
-1
read-only
n
0x0
0x0
CDBGPWRUPACK
DBG Power Up Acknowledgement
29
30
CDBGPWRUPREQ
DBG Power Up Request
28
29
DMA
Enhanced DMA Controller
DMA
0x0
0x0
0x100
registers
n
DMABAR
DMA base address register
0x8
32
read-write
n
0x0
0x0
DMAEN0
DMA activation enable register %s
0x0
8
read-write
n
0x0
0x0
DMAEN1
DMA activation enable register %s
0x1
8
read-write
n
0x0
0x0
DMAEN2
DMA activation enable register %s
0x2
8
read-write
n
0x0
0x0
DMAIF0
DMA Trigger enable register %s
0x10
8
read-write
n
0x0
0x0
DMAIF1
DMA Trigger enable register %s
0x11
8
read-write
n
0x0
0x0
DMAIF2
DMA Trigger enable register %s
0x12
8
read-write
n
0x0
0x0
IFPRCR
DMA Trigger Protect register
0xC
32
read-write
n
0x0
0x0
DMAVEC
DMA Vector and Control Data Area
DMAVEC
0x0
0x0
0x2C0
registers
n
DMACR
DMA Control register
0x0
16
read-write
n
0x0
0x0
CHNE
Enabling/disabling chain transfers
4
5
read-write
disable
Chain transfers disabled
0
enable
Chain transfers enabled
1
DAMOD
Destination address control
3
4
read-write
Fixed
Fixed
0
Incremented
Incremented
1
MODE
Transfer mode selection
0
1
read-write
Normal
Normal mode
0
Repeat
Repeat mode
1
RPTINT
Enabling/disabling repeat mode interrupts
5
6
read-write
disable
Interrupt generation disabled
0
enable
Interrupt generation enabled
1
RPTSEL
Repeat area selection
1
2
read-write
destination
Transfer destination is the repeat area
0
source
Transfer source is the repeat area
1
SAMOD
Source address control
2
3
read-write
Fixed
Fixed
0
Incremented
Incremented
1
SZ
Transfer Data size selection
6
8
read-write
BYTE
8 bits
0
HALF
16 bits
1
WORD
32 bits
2
DMACT
DMA Transfer Count register
0x4
16
read-write
n
0x0
0x0
DMBLS
DMA Block Size register
0x2
16
read-write
n
0x0
0x0
DMDAR
DMA Destination Address register
0xC
32
read-write
n
0x0
0x0
DMRLD
DMA Transfer Count Reload register
0x6
16
read-write
n
0x0
0x0
DMSAR
DMA Source Address register
0x8
32
read-write
n
0x0
0x0
VEC0
DMA vector area
0x0
8
read-write
n
0x0
0x0
VEC1
DMA vector area
0x1
8
read-write
n
0x0
0x0
VEC10
DMA vector area
0xA
8
read-write
n
0x0
0x0
VEC11
DMA vector area
0xB
8
read-write
n
0x0
0x0
VEC12
DMA vector area
0xC
8
read-write
n
0x0
0x0
VEC13
DMA vector area
0xD
8
read-write
n
0x0
0x0
VEC14
DMA vector area
0xE
8
read-write
n
0x0
0x0
VEC15
DMA vector area
0xF
8
read-write
n
0x0
0x0
VEC16
DMA vector area
0x10
8
read-write
n
0x0
0x0
VEC17
DMA vector area
0x11
8
read-write
n
0x0
0x0
VEC18
DMA vector area
0x12
8
read-write
n
0x0
0x0
VEC19
DMA vector area
0x13
8
read-write
n
0x0
0x0
VEC2
DMA vector area
0x2
8
read-write
n
0x0
0x0
VEC20
DMA vector area
0x14
8
read-write
n
0x0
0x0
VEC21
DMA vector area
0x15
8
read-write
n
0x0
0x0
VEC22
DMA vector area
0x16
8
read-write
n
0x0
0x0
VEC23
DMA vector area
0x17
8
read-write
n
0x0
0x0
VEC24
DMA vector area
0x18
8
read-write
n
0x0
0x0
VEC25
DMA vector area
0x19
8
read-write
n
0x0
0x0
VEC26
DMA vector area
0x1A
8
read-write
n
0x0
0x0
VEC27
DMA vector area
0x1B
8
read-write
n
0x0
0x0
VEC28
DMA vector area
0x1C
8
read-write
n
0x0
0x0
VEC29
DMA vector area
0x1D
8
read-write
n
0x0
0x0
VEC3
DMA vector area
0x3
8
read-write
n
0x0
0x0
VEC30
DMA vector area
0x1E
8
read-write
n
0x0
0x0
VEC31
DMA vector area
0x1F
8
read-write
n
0x0
0x0
VEC4
DMA vector area
0x4
8
read-write
n
0x0
0x0
VEC5
DMA vector area
0x5
8
read-write
n
0x0
0x0
VEC6
DMA vector area
0x6
8
read-write
n
0x0
0x0
VEC7
DMA vector area
0x7
8
read-write
n
0x0
0x0
VEC8
DMA vector area
0x8
8
read-write
n
0x0
0x0
VEC9
DMA vector area
0x9
8
read-write
n
0x0
0x0
ELC
Event Link Controller
ELC
0x0
0x0
0x100
registers
n
ELSELR00
Event output destination select register 00
0x0
-1
read-write
n
0x0
0x0
ELSELR01
Event output destination select register 01
0x1
-1
read-write
n
0x0
0x0
ELSELR02
Event output destination select register 02
0x2
-1
read-write
n
0x0
0x0
ELSELR03
Event output destination select register 03
0x3
-1
read-write
n
0x0
0x0
ELSELR04
Event output destination select register 04
0x4
-1
read-write
n
0x0
0x0
ELSELR05
Event output destination select register 05
0x5
-1
read-write
n
0x0
0x0
ELSELR06
Event output destination select register 06
0x6
-1
read-write
n
0x0
0x0
ELSELR07
Event output destination select register 07
0x7
-1
read-write
n
0x0
0x0
ELSELR08
Event output destination select register 08
0x8
-1
read-write
n
0x0
0x0
ELSELR09
Event output destination select register 09
0x9
-1
read-write
n
0x0
0x0
ELSELR10
Event output destination select register 10
0xA
-1
read-write
n
0x0
0x0
ELSELR11
Event output destination select register 11
0xB
-1
read-write
n
0x0
0x0
ELSELR12
Event output destination select register 12
0xC
-1
read-write
n
0x0
0x0
ELSELR13
Event output destination select register 13
0xD
-1
read-write
n
0x0
0x0
ELSELR14
Event output destination select register 14
0xE
-1
read-write
n
0x0
0x0
EPWM
Enhance PWM controller
EPWM
0x0
0x0
0x100
registers
n
EPWMCTL
EPWMO0n output control register
0x8
16
read-write
n
0x0
0x0
IE00
EPWM0%s output inverted enable register
8
9
IE01
EPWM0%s output inverted enable register
9
9
IE02
EPWM0%s output inverted enable register
10
9
IE03
EPWM0%s output inverted enable register
11
9
IE04
EPWM0%s output inverted enable register
12
9
IE05
EPWM0%s output inverted enable register
13
9
IE06
EPWM0%s output inverted enable register
14
9
IE07
EPWM0%s output inverted enable register
15
9
OE00
EPWM0%s output enable register
0
1
OE01
EPWM0%s output enable register
1
1
OE02
EPWM0%s output enable register
2
1
OE03
EPWM0%s output enable register
3
1
OE04
EPWM0%s output enable register
4
1
OE05
EPWM0%s output enable register
5
1
OE06
EPWM0%s output enable register
6
1
OE07
EPWM0%s output enable register
7
1
EPWMSRC
Input source select register
0x0
16
read-write
n
0x0
0x0
SRC00
Selsect the source clock of EPWM0%s
0
1
SRC01
Selsect the source clock of EPWM0%s
1
1
SRC02
Selsect the source clock of EPWM0%s
2
1
SRC03
Selsect the source clock of EPWM0%s
3
1
SRC04
Selsect the source clock of EPWM0%s
4
1
SRC05
Selsect the source clock of EPWM0%s
5
1
SRC06
Selsect the source clock of EPWM0%s
6
1
SRC07
Selsect the source clock of EPWM0%s
7
1
EPWMSTC
EPWMO0n cutoff control register
0x4
16
read-write
n
0x0
0x0
HS_SEL
Output forced cutoff release mode selection
3
4
IN_EG
Output forced cutoff source edge/output forced cutoff release edge selection
2
3
REL_SEL
Cutoff release timing select register
4
5
SC_SEL0
Cutoff source selection
0
1
SC_SEL1
Cutoff source selection
1
1
EPWMSTL
EPWMO0n cutoff output level register
0xC
16
read-write
n
0x0
0x0
IO00
EPWM00 output enable register
0
1
IO01
EPWM00 output enable register
1
1
IO10
EPWM01 output enable register
2
3
IO11
EPWM01 output enable register
3
3
IO20
EPWM02 output enable register
4
5
IO21
EPWM02 output enable register
5
5
IO30
EPWM03 output enable register
6
7
IO31
EPWM03 output enable register
7
7
IO40
EPWM04 output enable register
8
9
IO41
EPWM04 output enable register
9
9
IO50
EPWM05 output enable register
10
11
IO51
EPWM05 output enable register
11
11
IO60
EPWM06 output enable register
12
13
IO61
EPWM06 output enable register
13
13
IO70
EPWM07 output enable register
14
15
IO71
EPWM07 output enable register
15
15
EPWMSTR
Status register
0x10
16
read-write
n
0x0
0x0
HZCLR
software release cutoff register
0
1
SHTFLG
cutoff status register
1
2
FMC
Flash Memory Controller
FMC
0x0
0x0
0x400
registers
n
FMC
Flash erase or write finish
31
FLCERCNT
Flash chip erase control register
0x10
-1
read-write
n
0x0
0x0
FLERMD
Flash erase mode register
0xC
-1
read-write
n
0x0
0x0
FLERVCNT
Flash erase recovery time (Trcv) control register
0x3C
-1
read-write
n
0x0
0x0
FLNVSCNT
Flash address setup time (Tnvs) control register
0x18
-1
read-write
n
0x0
0x0
FLOPMD1
Flash operation mode register 1
0x4
-1
read-write
n
0x0
0x0
FLOPMD2
Flash operation mode register 2
0x8
-1
read-write
n
0x0
0x0
FLPROCNT
Flash program control register
0x1C
-1
read-write
n
0x0
0x0
FLPROT
Flash protect control register
0x20
-1
read-write
n
0x0
0x0
FLPRVCNT
Flash program recovery time (Trcv) control register
0x38
-1
read-write
n
0x0
0x0
FLSERCNT
Flash sector erase control register
0x14
-1
read-write
n
0x0
0x0
FLSTS
Flash status register
0x0
-1
read-write
n
0x0
0x0
EVF
Flash hardware verification error flag
2
3
OVF
Flash erase or write operaiton finish
0
1
IICA
Serial Interface I2C with multimaster and wakeup supported
IICA
0x0
0x0
0x200
registers
n
IICA
IICA interrupt request
16
IICA0
IICA shift register 0
0x120
-1
read-write
n
0x0
0x0
IICCTL00
IICA control register 0
0x0
-1
read-write
n
0x0
0x0
ACKE
Acknowledgment control
2
3
IICE
I2C operation enable
7
8
LREL
Exit from communications
6
7
SPIE
Enable generation of interrupt request when stop condition is detected
4
5
SPT
Stop condition trigger
0
1
STT
Start condition trigger
1
2
WREL
Wait cancellation
5
6
WTIM
Control of wait and interrupt request generation
3
4
IICCTL01
IICA control register 0
0x1
-1
read-write
n
0x0
0x0
CLD
Detection of SCLAn pin level (valid only when IICEn = 1)
5
6
read-only
DAD
Detection of SDAAn pin level (valid only when IICEn = 1)
4
5
read-only
DFC
Digital filter operation control
2
3
read-write
PRS
Operation clock (fMCK) contro
0
1
read-write
SMC
Operation mode switching
3
4
read-write
WUP
Control of address match wakeup
7
8
read-write
IICF0
IICA flag register 0
0x122
-1
read-write
n
0x0
0x0
IICBSY
I2C bus status flag
6
7
read-only
IICRSV
Communication reservation function disable bit
0
1
read-write
STCEN
Initial start enable trigger
1
2
read-write
STCF
STT clear flag
7
8
read-only
IICS0
IICA status register 0
0x121
-1
read-only
n
0x0
0x0
ACKD
Detection of acknowledge (ACK)
2
3
ALD
Detection of arbitration loss
6
7
COI
Detection of matching addresses
4
5
EXC
Detection of extension code reception
5
6
MSTS
Master status check flag
7
8
SPD
Detection of stop condition
0
1
STD
Detection of start condition
1
2
TRC
Detection of transmit/receive status
3
4
IICWH0
IICA high-level width setting register 0
0x3
-1
read-write
n
0x0
0x0
IICWL0
IICA low-level width setting register 0
0x2
-1
read-write
n
0x0
0x0
SVA0
Slave address register 0
0x4
-1
read-write
n
0x0
0x0
INT
Interrupt Controller
INT
0x0
0x0
0x200
registers
n
IFL
Interrupt flag register
0x0
8
read-write
n
0x0
0x0
MKL
Interrupt mask register
0x0
8
read-write
n
0x0
0x0
INTM
Pin input edge detection
INTM
0x0
0x0
0x100
registers
n
INTP0
INTP0 External interrupt request input is valid
1
INTP1
INTP1 External interrupt request input is valid
2
INTP2
INTP2 External interrupt request input is valid
3
INTP3
INTP3 External interrupt request input is valid
4
EGN0
External interrupt falling edge enable register
0x1
-1
read-write
n
0x0
0x0
EGN0
0
1
EGN1
1
2
EGN2
2
3
EGN3
3
4
EGP0
External interrupt rising edge enable register
0x0
-1
read-write
n
0x0
0x0
EGP0
0
1
EGP1
1
2
EGP2
2
3
EGP3
3
4
IRDA
IrDA communication module based on Infrared Data Association stardard 1.0
IRDA
0x0
0x0
0x1
registers
n
IRCR
IrDA control register
0x0
-1
read-write
n
0x0
0x0
IRCKS
IrRxD clock selection
4
7
IRE
IrRxD enable
7
8
IRRXINV
IrRxD data polarity switching
2
3
IRTXINV
IrRxD data polarity switching
3
4
KEY
Key interrupt
KEY
0x0
0x0
0x10
registers
n
KEY
KEY return interrupt request
6
KRM
Key return mode register
0x7
-1
read-write
n
0x0
0x0
LVD
Voltage detector
LVD
0x0
0x0
0x100
registers
n
LVI
Low Voltage detection interrupt
0
LVIM
Voltage detection register
0x1
8
read-write
n
0x0
0x0
LVIF
Voltage detection flag
0
1
read-only
GE
Supply voltage (VDD) greater or equal to detection voltage (VLVD), or when LVD is off
0
LT
Supply voltage (VDD) less than detection voltage (VLVD)
1
LVIOMSK
Mask status flag of LVD output
1
2
read-only
Invalid
Mask of LVD output is invalid
0
Valid
Mask of LVD output is valid
1
LVISEN
Enable rewritting LVIS register
7
8
read-only
Disable
Disabling of rewriting the LVIS register
0
Enable
Enabling of rewriting the LVIS register
1
LVIS
Voltage detection level register
0x2
8
read-write
n
0x0
0x0
LVILV
LVD detection level
0
1
read-write
High
High-voltage detection level (VLVDH)
0
Low
Low-voltage detection level (VLVDL or VLVD)
1
LVIMD
Operation mode of voltage detection
7
8
read-write
IRQ
interrupt mode
0
Reset
reset mode
1
MISC
Miscellaneous function
MISC
0x0
0x0
0x100
registers
n
ISC
Input switch control register
0x3
-1
read-write
n
0x0
0x0
SSIE00
The slave select input (SS00) of SPI00 is valid
7
8
INVALID
The slave select input (SS00) pin is invalid
0
VALID
The slave select input (SS00) pin is valid
1
NFEN0
Noise filter enable register 0
0x0
-1
read-write
n
0x0
0x0
SNFEN00
Enable noise filter of RxD0
0
1
SNFEN10
Enable noise filter of RxD1
2
3
SNFEN20
Enable noise filter of RxD2
4
5
NFEN1
Noise filter enable register 1
0x1
-1
read-write
n
0x0
0x0
TNFEN00
Enable noise filter of TI00
0
1
TNFEN01
Enable noise filter of TI01
1
2
TNFEN02
Enable noise filter of TI02
2
3
TNFEN03
Enable noise filter of TI03
3
4
NFEN2
Noise filter enable register 2
0x2
-1
read-write
n
0x0
0x0
TNFEN10
Enable noise filter of TI10
0
1
TNFEN11
Enable noise filter of TI11
1
2
TNFEN12
Enable noise filter of TI12
2
3
TNFEN13
Enable noise filter of TI13
3
4
RTCCL
Real-time clock select register
0xC
-1
read-write
n
0x0
0x0
TIOS0
Timer I/O select register 0
0x4
-1
read-write
n
0x0
0x0
TIOS1
Timer I/O select register 1
0x5
-1
read-write
n
0x0
0x0
PCBZ
Clock/Buzzer output controller
PCBZ
0x0
0x0
0x10
registers
n
CKS0
Clock output select registers 0
0x5
8
read-write
n
0x0
0x0
CCS
PCLBUZn output clock select
0
3
CSEL
PCLBUZn output clock select
3
4
PCLOE
PCLBUZn pin output enable
7
8
CKS1
Clock output select registers 1
0x6
-1
read-write
n
0x0
0x0
PGA
Programmable Gain Amplifier
PGA
0x0
0x0
0x100
registers
n
PGA0CTL
PGA 0 control register
0x6
-1
read-write
n
0x0
0x0
PGAEN
Programmable gain amplifier operation control
7
8
PGAVG
Programmable gain amplifier amplification factor selection
0
3
PVRVS
GND selection of feedback resistance of the programmable gain amplifier
3
4
PGA1CTL
PGA 1 control register
0x7
-1
read-write
n
0x0
0x0
PGACASC
PGA cascade enable register
0xD
-1
read-write
n
0x0
0x0
PGA0CASEN
PGA0 cascade connect enable
0
1
read-write
DISABLE
PGA0 cascade connect disable
0
ENABLE
PGA0 cascade connect enable
1
PGA1CASEN
PGA1 cascade connect enable
1
2
read-write
DISABLE
PGA1 cascade connect disable
0
ENABLE
PGA1 cascade connect enable
1
PGAPRCR
PGA protect register
0xC
-1
read-write
n
0x0
0x0
PORT
Port functions
PORT
0x0
0x0
0x1000
registers
n
INTP0PCFG
INTP0 alternate function pin configuration register
0x864
8
read-write
n
0x0
0x0
CFG
0
6
P00
P00 used as INTP0
0x01
P01
P01 used as INTP0
0x02
P10
P10 used as INTP0
0x03
P11
P11 used as INTP0
0x04
P12
P12 used as INTP0
0x05
P13
P13 used as INTP0
0x06
P14
P14 used as INTP0
0x07
P15
P15 used as INTP0
0x08
P16
P16 used as INTP0
0x09
P17
P17 used as INTP0
0x0A
P20
P20 used as INTP0
0x0B
P21
P21 used as INTP0
0x0C
P22
P22 used as INTP0
0x0D
P23
P23 used as INTP0
0x0E
P24
P24 used as INTP0
0x0F
P25
P25 used as INTP0
0x10
P26
P26 used as INTP0
0x11
P27
P27 used as INTP0
0x12
P30
P30 used as INTP0
0x13
P31
P31 used as INTP0
0x14
P40
P40 used as INTP0
0x15
P41
P41 used as INTP0
0x16
P50
P50 used as INTP0
0x17
P51
P51 used as INTP0
0x18
P60
P60 used as INTP0
0x19
P61
P61 used as INTP0
0x1A
P62
P62 used as INTP0
0x1B
P63
P63 used as INTP0
0x1C
P70
P70 used as INTP0
0x1D
P71
P71 used as INTP0
0x1E
P72
P72 used as INTP0
0x1F
P73
P73 used as INTP0
0x20
P74
P74 used as INTP0
0x21
P75
P75 used as INTP0
0x22
P120
P120 used as INTP0
0x23
P121
P121 used as INTP0
0x24
P122
P122 used as INTP0
0x25
P123
P123 used as INTP0
0x26
P124
P124 used as INTP0
0x27
P130
P130 used as INTP0
0x28
P136
P136 used as INTP0
0x29
P137
P137 used as INTP0
0x2A
P140
P140 used as INTP0
0x2B
P146
P146 used as INTP0
0x2C
P147
P147 used as INTP0
0x2D
INTP1PCFG
INTP1 alternate function pin configuration register
0x865
8
read-write
n
0x0
0x0
CFG
0
6
P00
P00 used as INTP1
0x01
P01
P01 used as INTP1
0x02
P10
P10 used as INTP1
0x03
P11
P11 used as INTP1
0x04
P12
P12 used as INTP1
0x05
P13
P13 used as INTP1
0x06
P14
P14 used as INTP1
0x07
P15
P15 used as INTP1
0x08
P16
P16 used as INTP1
0x09
P17
P17 used as INTP1
0x0A
P20
P20 used as INTP1
0x0B
P21
P21 used as INTP1
0x0C
P22
P22 used as INTP1
0x0D
P23
P23 used as INTP1
0x0E
P24
P24 used as INTP1
0x0F
P25
P25 used as INTP1
0x10
P26
P26 used as INTP1
0x11
P27
P27 used as INTP1
0x12
P30
P30 used as INTP1
0x13
P31
P31 used as INTP1
0x14
P40
P40 used as INTP1
0x15
P41
P41 used as INTP1
0x16
P50
P50 used as INTP1
0x17
P51
P51 used as INTP1
0x18
P60
P60 used as INTP1
0x19
P61
P61 used as INTP1
0x1A
P62
P62 used as INTP1
0x1B
P63
P63 used as INTP1
0x1C
P70
P70 used as INTP1
0x1D
P71
P71 used as INTP1
0x1E
P72
P72 used as INTP1
0x1F
P73
P73 used as INTP1
0x20
P74
P74 used as INTP1
0x21
P75
P75 used as INTP1
0x22
P120
P120 used as INTP1
0x23
P121
P121 used as INTP1
0x24
P122
P122 used as INTP1
0x25
P123
P123 used as INTP1
0x26
P124
P124 used as INTP1
0x27
P130
P130 used as INTP1
0x28
P136
P136 used as INTP1
0x29
P137
P137 used as INTP1
0x2A
P140
P140 used as INTP1
0x2B
P146
P146 used as INTP1
0x2C
P147
P147 used as INTP1
0x2D
INTP2PCFG
INTP2 alternate function pin configuration register
0x866
8
read-write
n
0x0
0x0
CFG
0
6
P00
P00 used as INTP2
0x01
P01
P01 used as INTP2
0x02
P10
P10 used as INTP2
0x03
P11
P11 used as INTP2
0x04
P12
P12 used as INTP2
0x05
P13
P13 used as INTP2
0x06
P14
P14 used as INTP2
0x07
P15
P15 used as INTP2
0x08
P16
P16 used as INTP2
0x09
P17
P17 used as INTP2
0x0A
P20
P20 used as INTP2
0x0B
P21
P21 used as INTP2
0x0C
P22
P22 used as INTP2
0x0D
P23
P23 used as INTP2
0x0E
P24
P24 used as INTP2
0x0F
P25
P25 used as INTP2
0x10
P26
P26 used as INTP2
0x11
P27
P27 used as INTP2
0x12
P30
P30 used as INTP2
0x13
P31
P31 used as INTP2
0x14
P40
P40 used as INTP2
0x15
P41
P41 used as INTP2
0x16
P50
P50 used as INTP2
0x17
P51
P51 used as INTP2
0x18
P60
P60 used as INTP2
0x19
P61
P61 used as INTP2
0x1A
P62
P62 used as INTP2
0x1B
P63
P63 used as INTP2
0x1C
P70
P70 used as INTP2
0x1D
P71
P71 used as INTP2
0x1E
P72
P72 used as INTP2
0x1F
P73
P73 used as INTP2
0x20
P74
P74 used as INTP2
0x21
P75
P75 used as INTP2
0x22
P120
P120 used as INTP2
0x23
P121
P121 used as INTP2
0x24
P122
P122 used as INTP2
0x25
P123
P123 used as INTP2
0x26
P124
P124 used as INTP2
0x27
P130
P130 used as INTP2
0x28
P136
P136 used as INTP2
0x29
P137
P137 used as INTP2
0x2A
P140
P140 used as INTP2
0x2B
P146
P146 used as INTP2
0x2C
P147
P147 used as INTP2
0x2D
INTP3PCFG
INTP3 alternate function pin configuration register
0x867
8
read-write
n
0x0
0x0
CFG
0
6
P00
P00 used as INTP3
0x01
P01
P01 used as INTP3
0x02
P10
P10 used as INTP3
0x03
P11
P11 used as INTP3
0x04
P12
P12 used as INTP3
0x05
P13
P13 used as INTP3
0x06
P14
P14 used as INTP3
0x07
P15
P15 used as INTP3
0x08
P16
P16 used as INTP3
0x09
P17
P17 used as INTP3
0x0A
P20
P20 used as INTP3
0x0B
P21
P21 used as INTP3
0x0C
P22
P22 used as INTP3
0x0D
P23
P23 used as INTP3
0x0E
P24
P24 used as INTP3
0x0F
P25
P25 used as INTP3
0x10
P26
P26 used as INTP3
0x11
P27
P27 used as INTP3
0x12
P30
P30 used as INTP3
0x13
P31
P31 used as INTP3
0x14
P40
P40 used as INTP3
0x15
P41
P41 used as INTP3
0x16
P50
P50 used as INTP3
0x17
P51
P51 used as INTP3
0x18
P60
P60 used as INTP3
0x19
P61
P61 used as INTP3
0x1A
P62
P62 used as INTP3
0x1B
P63
P63 used as INTP3
0x1C
P70
P70 used as INTP3
0x1D
P71
P71 used as INTP3
0x1E
P72
P72 used as INTP3
0x1F
P73
P73 used as INTP3
0x20
P74
P74 used as INTP3
0x21
P75
P75 used as INTP3
0x22
P120
P120 used as INTP3
0x23
P121
P121 used as INTP3
0x24
P122
P122 used as INTP3
0x25
P123
P123 used as INTP3
0x26
P124
P124 used as INTP3
0x27
P130
P130 used as INTP3
0x28
P136
P136 used as INTP3
0x29
P137
P137 used as INTP3
0x2A
P140
P140 used as INTP3
0x2B
P146
P146 used as INTP3
0x2C
P147
P147 used as INTP3
0x2D
IRRXDPCFG
SDI20/RXD2/IrRXD alternate function pin configuration register
SDI20PCFG
0x86B
-1
read-write
n
0x0
0x0
P0
Port register 0
0x0
8
read-write
n
0x0
0x0
P00CFG
Alterate Output Function configuration register
0x800
8
read-write
n
0x0
0x0
CFG
Alterate Output Function configuration register
0
4
GPIO
Port used as GPIO
0x00
TO10
Port used as TO10
0x01
TO11
Port used as TO11
0x02
TO12
Port used as TO12
0x03
TO13
Port used as TO13
0x04
SDO00/TxD0
Port used as SDO00/TxD0
0x05
SDO20/TxD2
Port used as SDO20/TxD2
0x06
CLKBUZ0
Port used as CLKBUZ0
0x07
SCLKO00
Port used as SCLK00 output
0x08
SCLKO20
Port used as SCLK20 output
0x09
TXD1
Port used as TXD1
0x0A
P01CFG
0x801
-1
read-write
n
0x0
0x0
P1
Port register 1
0x1
8
read-write
n
0x0
0x0
P10CFG
0x808
-1
read-write
n
0x0
0x0
P11CFG
0x809
-1
read-write
n
0x0
0x0
P12
Port register 12
0xC
8
read-write
n
0x0
0x0
P120CFG
0x840
-1
read-write
n
0x0
0x0
P121CFG
0x841
-1
read-write
n
0x0
0x0
P122CFG
0x842
-1
read-write
n
0x0
0x0
P123CFG
0x843
-1
read-write
n
0x0
0x0
P124CFG
0x844
-1
read-write
n
0x0
0x0
P12CFG
0x80A
-1
read-write
n
0x0
0x0
P13
Port register 13
0xD
8
read-write
n
0x0
0x0
P130CFG
0x848
-1
read-write
n
0x0
0x0
P136CFG
0x84E
-1
read-write
n
0x0
0x0
P137CFG
0x84F
-1
read-write
n
0x0
0x0
P13CFG
0x80B
-1
read-write
n
0x0
0x0
P14
Port register 14
0xE
8
read-write
n
0x0
0x0
P140CFG
0x850
-1
read-write
n
0x0
0x0
P146CFG
0x856
-1
read-write
n
0x0
0x0
P147CFG
0x857
-1
read-write
n
0x0
0x0
P14CFG
0x80C
-1
read-write
n
0x0
0x0
P15CFG
0x80D
-1
read-write
n
0x0
0x0
P16CFG
0x80E
-1
read-write
n
0x0
0x0
P17CFG
0x80F
-1
read-write
n
0x0
0x0
P2
Port register 2
0x2
8
read-write
n
0x0
0x0
P20CFG
0x810
-1
read-write
n
0x0
0x0
P21CFG
0x811
-1
read-write
n
0x0
0x0
P22CFG
0x812
-1
read-write
n
0x0
0x0
P23CFG
0x813
-1
read-write
n
0x0
0x0
P24CFG
0x814
-1
read-write
n
0x0
0x0
P25CFG
0x815
-1
read-write
n
0x0
0x0
P26CFG
0x816
-1
read-write
n
0x0
0x0
P27CFG
0x817
-1
read-write
n
0x0
0x0
P3
Port register 3
0x3
8
read-write
n
0x0
0x0
P30CFG
0x818
-1
read-write
n
0x0
0x0
P31CFG
0x819
-1
read-write
n
0x0
0x0
P4
Port register 4
0x4
8
read-write
n
0x0
0x0
P40CFG
0x820
-1
read-write
n
0x0
0x0
P41CFG
0x821
-1
read-write
n
0x0
0x0
P5
Port register 5
0x5
8
read-write
n
0x0
0x0
P50CFG
0x828
-1
read-write
n
0x0
0x0
P51CFG
0x829
-1
read-write
n
0x0
0x0
P6
Port register 6
0x6
8
read-write
n
0x0
0x0
P60CFG
0x830
-1
read-write
n
0x0
0x0
P61CFG
0x831
-1
read-write
n
0x0
0x0
P62CFG
0x832
-1
read-write
n
0x0
0x0
P63CFG
0x833
-1
read-write
n
0x0
0x0
P7
Port register 7
0x7
8
read-write
n
0x0
0x0
P70CFG
0x838
-1
read-write
n
0x0
0x0
P71CFG
0x839
-1
read-write
n
0x0
0x0
P72CFG
0x83A
-1
read-write
n
0x0
0x0
P73CFG
0x83B
-1
read-write
n
0x0
0x0
P74CFG
0x83C
-1
read-write
n
0x0
0x0
P75CFG
0x83D
-1
read-write
n
0x0
0x0
PCLR0
Port clear register 0
0x70
8
read-write
n
0x0
0x0
PCLR1
Port clear register 1
0x71
8
read-write
n
0x0
0x0
PCLR12
Port clear register 12
0x7C
8
read-write
n
0x0
0x0
PCLR13
Port clear register 13
0x7D
8
read-write
n
0x0
0x0
PCLR14
Port clear register 14
0x7E
8
read-write
n
0x0
0x0
PCLR2
Port clear register 2
0x72
8
read-write
n
0x0
0x0
PCLR3
Port clear register 3
0x73
8
read-write
n
0x0
0x0
PCLR4
Port clear register 4
0x74
8
read-write
n
0x0
0x0
PCLR5
Port clear register 5
0x75
8
read-write
n
0x0
0x0
PCLR6
Port clear register 6
0x76
8
read-write
n
0x0
0x0
PCLR7
Port clear register 7
0x77
8
read-write
n
0x0
0x0
PD0
Pull-down resistor option register 0
0x40
8
read-write
n
0x0
0x0
PD1
Pull-down resistor option register 1
0x41
8
read-write
n
0x0
0x0
PD12
Pull-down resistor option register 12
0x4C
8
read-write
n
0x0
0x0
PD13
Pull-down resistor option register 13
0x4D
8
read-write
n
0x0
0x0
PD14
Pull-down resistor option register 14
0x4E
8
read-write
n
0x0
0x0
PD2
Pull-down resistor option register 2
0x42
8
read-write
n
0x0
0x0
PD3
Pull-down resistor option register 3
0x43
8
read-write
n
0x0
0x0
PD5
Pull-down resistor option register 5
0x45
8
read-write
n
0x0
0x0
PD6
Pull-down resistor option register 6
0x46
8
read-write
n
0x0
0x0
PD7
Pull-down resistor option register 7
0x47
8
read-write
n
0x0
0x0
PM0
Port mode register 0
0x20
8
read-write
n
0x0
0x0
PM1
Port mode register 1
0x21
8
read-write
n
0x0
0x0
PM12
Port mode register 12
0x2C
8
read-write
n
0x0
0x0
PM13
Port mode register 13
0x2D
8
read-write
n
0x0
0x0
PM14
Port mode register 14
0x2E
8
read-write
n
0x0
0x0
PM2
Port mode register 2
0x22
8
read-write
n
0x0
0x0
PM3
Port mode register 3
0x23
8
read-write
n
0x0
0x0
PM4
Port mode register 4
0x24
8
read-write
n
0x0
0x0
PM5
Port mode register 5
0x25
8
read-write
n
0x0
0x0
PM6
Port mode register 6
0x26
8
read-write
n
0x0
0x0
PM7
Port mode register 7
0x27
8
read-write
n
0x0
0x0
PMC0
Port mode control register 0
0x60
8
read-write
n
0x0
0x0
PMC1
Port mode control register 1
0x61
8
read-write
n
0x0
0x0
PMC12
Port mode control register 12
0x6C
8
read-write
n
0x0
0x0
PMC13
Port mode control register 13
0x6D
8
read-write
n
0x0
0x0
PMC14
Port mode control register 14
0x6E
8
read-write
n
0x0
0x0
PMC2
Port mode control register 2
0x62
8
read-write
n
0x0
0x0
PMC3
Port mode control register 3
0x63
8
read-write
n
0x0
0x0
PMC5
Port mode control register 5
0x65
8
read-write
n
0x0
0x0
PMC6
Port mode control register 6
0x66
8
read-write
n
0x0
0x0
PMC7
Port mode control register 7
0x67
8
read-write
n
0x0
0x0
PMS
Port mode select register
0x87B
8
read-write
n
0x0
0x0
POM0
Port output mode register 0
0x50
8
read-write
n
0x0
0x0
POM1
Port output mode register 1
0x51
8
read-write
n
0x0
0x0
POM12
Port output mode register 12
0x5C
8
read-write
n
0x0
0x0
POM13
Port output mode register 13
0x5D
8
read-write
n
0x0
0x0
POM14
Port output mode register 14
0x5E
8
read-write
n
0x0
0x0
POM2
Port output mode register 2
0x52
8
read-write
n
0x0
0x0
POM3
Port output mode register 3
0x53
8
read-write
n
0x0
0x0
POM4
Port output mode register 4
0x54
8
read-write
n
0x0
0x0
POM5
Port output mode register 5
0x55
8
read-write
n
0x0
0x0
POM6
Port output mode register 6
0x56
8
read-write
n
0x0
0x0
POM7
Port output mode register 7
0x57
8
read-write
n
0x0
0x0
PSET0
Port set register 0
0x10
8
read-write
n
0x0
0x0
PSET1
Port set register 1
0x11
8
read-write
n
0x0
0x0
PSET12
Port set register 12
0x1C
8
read-write
n
0x0
0x0
PSET13
Port set register 13
0x1D
8
read-write
n
0x0
0x0
PSET14
Port set register 14
0x1E
8
read-write
n
0x0
0x0
PSET2
Port set register 2
0x12
8
read-write
n
0x0
0x0
PSET3
Port set register 3
0x13
8
read-write
n
0x0
0x0
PSET4
Port set register 4
0x14
8
read-write
n
0x0
0x0
PSET5
Port set register 5
0x15
8
read-write
n
0x0
0x0
PSET6
Port set register 6
0x16
8
read-write
n
0x0
0x0
PSET7
Port set register 7
0x17
8
read-write
n
0x0
0x0
PU0
Pull-up resistor option register 0
0x30
8
read-write
n
0x0
0x0
PU1
Pull-up resistor option register 1
0x31
8
read-write
n
0x0
0x0
PU12
Pull-up resistor option register 12
0x3C
8
read-write
n
0x0
0x0
PU13
Pull-up resistor option register 13
0x3D
8
read-write
n
0x0
0x0
PU14
Pull-up resistor option register 14
0x3E
8
read-write
n
0x0
0x0
PU2
Pull-up resistor option register 2
0x32
8
read-write
n
0x0
0x0
PU3
Pull-up resistor option register 3
0x33
8
read-write
n
0x0
0x0
PU4
Pull-up resistor option register 4
0x34
8
read-write
n
0x0
0x0
PU5
Pull-up resistor option register 5
0x35
8
read-write
n
0x0
0x0
PU6
Pull-up resistor option register 6
0x36
8
read-write
n
0x0
0x0
PU7
Pull-up resistor option register 7
0x37
8
read-write
n
0x0
0x0
RXD0PCFG
SDI00/RXD0/SDA00 alternate function pin configuration register
SDI00PCFG
0x868
-1
read-write
n
0x0
0x0
RXD1PCFG
RXD1 alternate function pin configuration register
0x86F
8
read-write
n
0x0
0x0
CFG
0
6
P00
P00 used as RXD1
0x01
P01
P01 used as RXD1
0x02
P10
P10 used as RXD1
0x03
P11
P11 used as RXD1
0x04
P12
P12 used as RXD1
0x05
P13
P13 used as RXD1
0x06
P14
P14 used as RXD1
0x07
P15
P15 used as RXD1
0x08
P16
P16 used as RXD1
0x09
P17
P17 used as RXD1
0x0A
P20
P20 used as RXD1
0x0B
P21
P21 used as RXD1
0x0C
P22
P22 used as RXD1
0x0D
P23
P23 used as RXD1
0x0E
P24
P24 used as RXD1
0x0F
P25
P25 used as RXD1
0x10
P26
P26 used as RXD1
0x11
P27
P27 used as RXD1
0x12
P30
P30 used as RXD1
0x13
P31
P31 used as RXD1
0x14
P40
P40 used as RXD1
0x15
P41
P41 used as RXD1
0x16
P50
P50 used as RXD1
0x17
P51
P51 used as RXD1
0x18
P60
P60 used as RXD1
0x19
P61
P61 used as RXD1
0x1A
P62
P62 used as RXD1
0x1B
P63
P63 used as RXD1
0x1C
P70
P70 used as RXD1
0x1D
P71
P71 used as RXD1
0x1E
P72
P72 used as RXD1
0x1F
P73
P73 used as RXD1
0x20
P74
P74 used as RXD1
0x21
P75
P75 used as RXD1
0x22
P120
P120 used as RXD1
0x23
P121
P121 used as RXD1
0x24
P122
P122 used as RXD1
0x25
P123
P123 used as RXD1
0x26
P124
P124 used as RXD1
0x27
P130
P130 used as RXD1
0x28
P136
P136 used as RXD1
0x29
P137
P137 used as RXD1
0x2A
P140
P140 used as RXD1
0x2B
P146
P146 used as RXD1
0x2C
P147
P147 used as RXD1
0x2D
RXD2PCFG
SDI20/RXD2/IrRXD alternate function pin configuration register
SDI20PCFG
0x86B
-1
read-write
n
0x0
0x0
SCLA0PCFG
SCLA0 alternate function pin configuration register
0x86E
8
read-write
n
0x0
0x0
CFG
0
6
P00
P00 used as SCLA0
0x01
P01
P01 used as SCLA0
0x02
P10
P10 used as SCLA0
0x03
P11
P11 used as SCLA0
0x04
P12
P12 used as SCLA0
0x05
P13
P13 used as SCLA0
0x06
P14
P14 used as SCLA0
0x07
P15
P15 used as SCLA0
0x08
P16
P16 used as SCLA0
0x09
P17
P17 used as SCLA0
0x0A
P20
P20 used as SCLA0
0x0B
P21
P21 used as SCLA0
0x0C
P22
P22 used as SCLA0
0x0D
P23
P23 used as SCLA0
0x0E
P24
P24 used as SCLA0
0x0F
P25
P25 used as SCLA0
0x10
P26
P26 used as SCLA0
0x11
P27
P27 used as SCLA0
0x12
P30
P30 used as SCLA0
0x13
P31
P31 used as SCLA0
0x14
P40
P40 used as SCLA0
0x15
P41
P41 used as SCLA0
0x16
P50
P50 used as SCLA0
0x17
P51
P51 used as SCLA0
0x18
P60
P60 used as SCLA0
0x19
P61
P61 used as SCLA0
0x1A
P62
P62 used as SCLA0
0x1B
P63
P63 used as SCLA0
0x1C
P70
P70 used as SCLA0
0x1D
P71
P71 used as SCLA0
0x1E
P72
P72 used as SCLA0
0x1F
P73
P73 used as SCLA0
0x20
P74
P74 used as SCLA0
0x21
P75
P75 used as SCLA0
0x22
P120
P120 used as SCLA0
0x23
P121
P121 used as SCLA0
0x24
P122
P122 used as SCLA0
0x25
P123
P123 used as SCLA0
0x26
P124
P124 used as SCLA0
0x27
P130
P130 used as SCLA0
0x28
P136
P136 used as SCLA0
0x29
P137
P137 used as SCLA0
0x2A
P140
P140 used as SCLA0
0x2B
P146
P146 used as SCLA0
0x2C
P147
P147 used as SCLA0
0x2D
SCLKI00PCFG
SCLKI00 alternate function pin configuration register
0x869
8
read-write
n
0x0
0x0
CFG
0
6
P00
P00 used as SCLKI00
0x01
P01
P01 used as SCLKI00
0x02
P10
P10 used as SCLKI00
0x03
P11
P11 used as SCLKI00
0x04
P12
P12 used as SCLKI00
0x05
P13
P13 used as SCLKI00
0x06
P14
P14 used as SCLKI00
0x07
P15
P15 used as SCLKI00
0x08
P16
P16 used as SCLKI00
0x09
P17
P17 used as SCLKI00
0x0A
P20
P20 used as SCLKI00
0x0B
P21
P21 used as SCLKI00
0x0C
P22
P22 used as SCLKI00
0x0D
P23
P23 used as SCLKI00
0x0E
P24
P24 used as SCLKI00
0x0F
P25
P25 used as SCLKI00
0x10
P26
P26 used as SCLKI00
0x11
P27
P27 used as SCLKI00
0x12
P30
P30 used as SCLKI00
0x13
P31
P31 used as SCLKI00
0x14
P40
P40 used as SCLKI00
0x15
P41
P41 used as SCLKI00
0x16
P50
P50 used as SCLKI00
0x17
P51
P51 used as SCLKI00
0x18
P60
P60 used as SCLKI00
0x19
P61
P61 used as SCLKI00
0x1A
P62
P62 used as SCLKI00
0x1B
P63
P63 used as SCLKI00
0x1C
P70
P70 used as SCLKI00
0x1D
P71
P71 used as SCLKI00
0x1E
P72
P72 used as SCLKI00
0x1F
P73
P73 used as SCLKI00
0x20
P74
P74 used as SCLKI00
0x21
P75
P75 used as SCLKI00
0x22
P120
P120 used as SCLKI00
0x23
P121
P121 used as SCLKI00
0x24
P122
P122 used as SCLKI00
0x25
P123
P123 used as SCLKI00
0x26
P124
P124 used as SCLKI00
0x27
P130
P130 used as SCLKI00
0x28
P136
P136 used as SCLKI00
0x29
P137
P137 used as SCLKI00
0x2A
P140
P140 used as SCLKI00
0x2B
P146
P146 used as SCLKI00
0x2C
P147
P147 used as SCLKI00
0x2D
SCLKI20PCFG
SCLKI20 alternate function pin configuration register
0x86C
8
read-write
n
0x0
0x0
CFG
0
6
P00
P00 used as SCLKI20
0x01
P01
P01 used as SCLKI20
0x02
P10
P10 used as SCLKI20
0x03
P11
P11 used as SCLKI20
0x04
P12
P12 used as SCLKI20
0x05
P13
P13 used as SCLKI20
0x06
P14
P14 used as SCLKI20
0x07
P15
P15 used as SCLKI20
0x08
P16
P16 used as SCLKI20
0x09
P17
P17 used as SCLKI20
0x0A
P20
P20 used as SCLKI20
0x0B
P21
P21 used as SCLKI20
0x0C
P22
P22 used as SCLKI20
0x0D
P23
P23 used as SCLKI20
0x0E
P24
P24 used as SCLKI20
0x0F
P25
P25 used as SCLKI20
0x10
P26
P26 used as SCLKI20
0x11
P27
P27 used as SCLKI20
0x12
P30
P30 used as SCLKI20
0x13
P31
P31 used as SCLKI20
0x14
P40
P40 used as SCLKI20
0x15
P41
P41 used as SCLKI20
0x16
P50
P50 used as SCLKI20
0x17
P51
P51 used as SCLKI20
0x18
P60
P60 used as SCLKI20
0x19
P61
P61 used as SCLKI20
0x1A
P62
P62 used as SCLKI20
0x1B
P63
P63 used as SCLKI20
0x1C
P70
P70 used as SCLKI20
0x1D
P71
P71 used as SCLKI20
0x1E
P72
P72 used as SCLKI20
0x1F
P73
P73 used as SCLKI20
0x20
P74
P74 used as SCLKI20
0x21
P75
P75 used as SCLKI20
0x22
P120
P120 used as SCLKI20
0x23
P121
P121 used as SCLKI20
0x24
P122
P122 used as SCLKI20
0x25
P123
P123 used as SCLKI20
0x26
P124
P124 used as SCLKI20
0x27
P130
P130 used as SCLKI20
0x28
P136
P136 used as SCLKI20
0x29
P137
P137 used as SCLKI20
0x2A
P140
P140 used as SCLKI20
0x2B
P146
P146 used as SCLKI20
0x2C
P147
P147 used as SCLKI20
0x2D
SDA00PCFG
SDI00/RXD0/SDA00 alternate function pin configuration register
SDI00PCFG
0x868
-1
read-write
n
0x0
0x0
SDA10PCFG
SDA10 alternate function pin configuration register
RXD1PCFG
0x86F
-1
read-write
n
0x0
0x0
SDAA0PCFG
SDAA0 alternate function pin configuration register
0x86D
8
read-write
n
0x0
0x0
CFG
0
6
P00
P00 used as SDAA0
0x01
P01
P01 used as SDAA0
0x02
P10
P10 used as SDAA0
0x03
P11
P11 used as SDAA0
0x04
P12
P12 used as SDAA0
0x05
P13
P13 used as SDAA0
0x06
P14
P14 used as SDAA0
0x07
P15
P15 used as SDAA0
0x08
P16
P16 used as SDAA0
0x09
P17
P17 used as SDAA0
0x0A
P20
P20 used as SDAA0
0x0B
P21
P21 used as SDAA0
0x0C
P22
P22 used as SDAA0
0x0D
P23
P23 used as SDAA0
0x0E
P24
P24 used as SDAA0
0x0F
P25
P25 used as SDAA0
0x10
P26
P26 used as SDAA0
0x11
P27
P27 used as SDAA0
0x12
P30
P30 used as SDAA0
0x13
P31
P31 used as SDAA0
0x14
P40
P40 used as SDAA0
0x15
P41
P41 used as SDAA0
0x16
P50
P50 used as SDAA0
0x17
P51
P51 used as SDAA0
0x18
P60
P60 used as SDAA0
0x19
P61
P61 used as SDAA0
0x1A
P62
P62 used as SDAA0
0x1B
P63
P63 used as SDAA0
0x1C
P70
P70 used as SDAA0
0x1D
P71
P71 used as SDAA0
0x1E
P72
P72 used as SDAA0
0x1F
P73
P73 used as SDAA0
0x20
P74
P74 used as SDAA0
0x21
P75
P75 used as SDAA0
0x22
P120
P120 used as SDAA0
0x23
P121
P121 used as SDAA0
0x24
P122
P122 used as SDAA0
0x25
P123
P123 used as SDAA0
0x26
P124
P124 used as SDAA0
0x27
P130
P130 used as SDAA0
0x28
P136
P136 used as SDAA0
0x29
P137
P137 used as SDAA0
0x2A
P140
P140 used as SDAA0
0x2B
P146
P146 used as SDAA0
0x2C
P147
P147 used as SDAA0
0x2D
SDI00PCFG
SDI00/RXD0/SDA00 alternate function pin configuration register
0x868
8
read-write
n
0x0
0x0
CFG
0
6
P00
P00 used as SDI00/RXD0/SDA00
0x01
P01
P01 used as SDI00/RXD0/SDA00
0x02
P10
P10 used as SDI00/RXD0/SDA00
0x03
P11
P11 used as SDI00/RXD0/SDA00
0x04
P12
P12 used as SDI00/RXD0/SDA00
0x05
P13
P13 used as SDI00/RXD0/SDA00
0x06
P14
P14 used as SDI00/RXD0/SDA00
0x07
P15
P15 used as SDI00/RXD0/SDA00
0x08
P16
P16 used as SDI00/RXD0/SDA00
0x09
P17
P17 used as SDI00/RXD0/SDA00
0x0A
P20
P20 used as SDI00/RXD0/SDA00
0x0B
P21
P21 used as SDI00/RXD0/SDA00
0x0C
P22
P22 used as SDI00/RXD0/SDA00
0x0D
P23
P23 used as SDI00/RXD0/SDA00
0x0E
P24
P24 used as SDI00/RXD0/SDA00
0x0F
P25
P25 used as SDI00/RXD0/SDA00
0x10
P26
P26 used as SDI00/RXD0/SDA00
0x11
P27
P27 used as SDI00/RXD0/SDA00
0x12
P30
P30 used as SDI00/RXD0/SDA00
0x13
P31
P31 used as SDI00/RXD0/SDA00
0x14
P40
P40 used as SDI00/RXD0/SDA00
0x15
P41
P41 used as SDI00/RXD0/SDA00
0x16
P50
P50 used as SDI00/RXD0/SDA00
0x17
P51
P51 used as SDI00/RXD0/SDA00
0x18
P60
P60 used as SDI00/RXD0/SDA00
0x19
P61
P61 used as SDI00/RXD0/SDA00
0x1A
P62
P62 used as SDI00/RXD0/SDA00
0x1B
P63
P63 used as SDI00/RXD0/SDA00
0x1C
P70
P70 used as SDI00/RXD0/SDA00
0x1D
P71
P71 used as SDI00/RXD0/SDA00
0x1E
P72
P72 used as SDI00/RXD0/SDA00
0x1F
P73
P73 used as SDI00/RXD0/SDA00
0x20
P74
P74 used as SDI00/RXD0/SDA00
0x21
P75
P75 used as SDI00/RXD0/SDA00
0x22
P120
P120 used as SDI00/RXD0/SDA00
0x23
P121
P121 used as SDI00/RXD0/SDA00
0x24
P122
P122 used as SDI00/RXD0/SDA00
0x25
P123
P123 used as SDI00/RXD0/SDA00
0x26
P124
P124 used as SDI00/RXD0/SDA00
0x27
P130
P130 used as SDI00/RXD0/SDA00
0x28
P136
P136 used as SDI00/RXD0/SDA00
0x29
P137
P137 used as SDI00/RXD0/SDA00
0x2A
P140
P140 used as SDI00/RXD0/SDA00
0x2B
P146
P146 used as SDI00/RXD0/SDA00
0x2C
P147
P147 used as SDI00/RXD0/SDA00
0x2D
SDI10PCFG
SDI10 alternate function pin configuration register
RXD1PCFG
0x86F
-1
read-write
n
0x0
0x0
SDI20PCFG
SDI20/RXD2/IrRXD alternate function pin configuration register
0x86B
8
read-write
n
0x0
0x0
CFG
0
6
P00
P00 used as SDI20/RXD2/IrRXD
0x01
P01
P01 used as SDI20/RXD2/IrRXD
0x02
P10
P10 used as SDI20/RXD2/IrRXD
0x03
P11
P11 used as SDI20/RXD2/IrRXD
0x04
P12
P12 used as SDI20/RXD2/IrRXD
0x05
P13
P13 used as SDI20/RXD2/IrRXD
0x06
P14
P14 used as SDI20/RXD2/IrRXD
0x07
P15
P15 used as SDI20/RXD2/IrRXD
0x08
P16
P16 used as SDI20/RXD2/IrRXD
0x09
P17
P17 used as SDI20/RXD2/IrRXD
0x0A
P20
P20 used as SDI20/RXD2/IrRXD
0x0B
P21
P21 used as SDI20/RXD2/IrRXD
0x0C
P22
P22 used as SDI20/RXD2/IrRXD
0x0D
P23
P23 used as SDI20/RXD2/IrRXD
0x0E
P24
P24 used as SDI20/RXD2/IrRXD
0x0F
P25
P25 used as SDI20/RXD2/IrRXD
0x10
P26
P26 used as SDI20/RXD2/IrRXD
0x11
P27
P27 used as SDI20/RXD2/IrRXD
0x12
P30
P30 used as SDI20/RXD2/IrRXD
0x13
P31
P31 used as SDI20/RXD2/IrRXD
0x14
P40
P40 used as SDI20/RXD2/IrRXD
0x15
P41
P41 used as SDI20/RXD2/IrRXD
0x16
P50
P50 used as SDI20/RXD2/IrRXD
0x17
P51
P51 used as SDI20/RXD2/IrRXD
0x18
P60
P60 used as SDI20/RXD2/IrRXD
0x19
P61
P61 used as SDI20/RXD2/IrRXD
0x1A
P62
P62 used as SDI20/RXD2/IrRXD
0x1B
P63
P63 used as SDI20/RXD2/IrRXD
0x1C
P70
P70 used as SDI20/RXD2/IrRXD
0x1D
P71
P71 used as SDI20/RXD2/IrRXD
0x1E
P72
P72 used as SDI20/RXD2/IrRXD
0x1F
P73
P73 used as SDI20/RXD2/IrRXD
0x20
P74
P74 used as SDI20/RXD2/IrRXD
0x21
P75
P75 used as SDI20/RXD2/IrRXD
0x22
P120
P120 used as SDI20/RXD2/IrRXD
0x23
P121
P121 used as SDI20/RXD2/IrRXD
0x24
P122
P122 used as SDI20/RXD2/IrRXD
0x25
P123
P123 used as SDI20/RXD2/IrRXD
0x26
P124
P124 used as SDI20/RXD2/IrRXD
0x27
P130
P130 used as SDI20/RXD2/IrRXD
0x28
P136
P136 used as SDI20/RXD2/IrRXD
0x29
P137
P137 used as SDI20/RXD2/IrRXD
0x2A
P140
P140 used as SDI20/RXD2/IrRXD
0x2B
P146
P146 used as SDI20/RXD2/IrRXD
0x2C
P147
P147 used as SDI20/RXD2/IrRXD
0x2D
SPIPCFG
SPI alternate function pins configuration register
0x87E
8
read-write
n
0x0
0x0
SS00PCFG
SS00 alternate function pin configuration register
0x86A
8
read-write
n
0x0
0x0
CFG
0
6
P00
P00 used as SS00
0x01
P01
P01 used as SS00
0x02
P10
P10 used as SS00
0x03
P11
P11 used as SS00
0x04
P12
P12 used as SS00
0x05
P13
P13 used as SS00
0x06
P14
P14 used as SS00
0x07
P15
P15 used as SS00
0x08
P16
P16 used as SS00
0x09
P17
P17 used as SS00
0x0A
P20
P20 used as SS00
0x0B
P21
P21 used as SS00
0x0C
P22
P22 used as SS00
0x0D
P23
P23 used as SS00
0x0E
P24
P24 used as SS00
0x0F
P25
P25 used as SS00
0x10
P26
P26 used as SS00
0x11
P27
P27 used as SS00
0x12
P30
P30 used as SS00
0x13
P31
P31 used as SS00
0x14
P40
P40 used as SS00
0x15
P41
P41 used as SS00
0x16
P50
P50 used as SS00
0x17
P51
P51 used as SS00
0x18
P60
P60 used as SS00
0x19
P61
P61 used as SS00
0x1A
P62
P62 used as SS00
0x1B
P63
P63 used as SS00
0x1C
P70
P70 used as SS00
0x1D
P71
P71 used as SS00
0x1E
P72
P72 used as SS00
0x1F
P73
P73 used as SS00
0x20
P74
P74 used as SS00
0x21
P75
P75 used as SS00
0x22
P120
P120 used as SS00
0x23
P121
P121 used as SS00
0x24
P122
P122 used as SS00
0x25
P123
P123 used as SS00
0x26
P124
P124 used as SS00
0x27
P130
P130 used as SS00
0x28
P136
P136 used as SS00
0x29
P137
P137 used as SS00
0x2A
P140
P140 used as SS00
0x2B
P146
P146 used as SS00
0x2C
P147
P147 used as SS00
0x2D
TI10PCFG
TI10 alternate function pin configuration register
0x860
8
read-write
n
0x0
0x0
CFG
0
6
P00
P00 used as TI10
0x01
P01
P01 used as TI10
0x02
P10
P10 used as TI10
0x03
P11
P11 used as TI10
0x04
P12
P12 used as TI10
0x05
P13
P13 used as TI10
0x06
P14
P14 used as TI10
0x07
P15
P15 used as TI10
0x08
P16
P16 used as TI10
0x09
P17
P17 used as TI10
0x0A
P20
P20 used as TI10
0x0B
P21
P21 used as TI10
0x0C
P22
P22 used as TI10
0x0D
P23
P23 used as TI10
0x0E
P24
P24 used as TI10
0x0F
P25
P25 used as TI10
0x10
P26
P26 used as TI10
0x11
P27
P27 used as TI10
0x12
P30
P30 used as TI10
0x13
P31
P31 used as TI10
0x14
P40
P40 used as TI10
0x15
P41
P41 used as TI10
0x16
P50
P50 used as TI10
0x17
P51
P51 used as TI10
0x18
P60
P60 used as TI10
0x19
P61
P61 used as TI10
0x1A
P62
P62 used as TI10
0x1B
P63
P63 used as TI10
0x1C
P70
P70 used as TI10
0x1D
P71
P71 used as TI10
0x1E
P72
P72 used as TI10
0x1F
P73
P73 used as TI10
0x20
P74
P74 used as TI10
0x21
P75
P75 used as TI10
0x22
P120
P120 used as TI10
0x23
P121
P121 used as TI10
0x24
P122
P122 used as TI10
0x25
P123
P123 used as TI10
0x26
P124
P124 used as TI10
0x27
P130
P130 used as TI10
0x28
P136
P136 used as TI10
0x29
P137
P137 used as TI10
0x2A
P140
P140 used as TI10
0x2B
P146
P146 used as TI10
0x2C
P147
P147 used as TI10
0x2D
TI11PCFG
TI11 alternate function pin configuration register
0x861
8
read-write
n
0x0
0x0
CFG
0
6
P00
P00 used as TI11
0x01
P01
P01 used as TI11
0x02
P10
P10 used as TI11
0x03
P11
P11 used as TI11
0x04
P12
P12 used as TI11
0x05
P13
P13 used as TI11
0x06
P14
P14 used as TI11
0x07
P15
P15 used as TI11
0x08
P16
P16 used as TI11
0x09
P17
P17 used as TI11
0x0A
P20
P20 used as TI11
0x0B
P21
P21 used as TI11
0x0C
P22
P22 used as TI11
0x0D
P23
P23 used as TI11
0x0E
P24
P24 used as TI11
0x0F
P25
P25 used as TI11
0x10
P26
P26 used as TI11
0x11
P27
P27 used as TI11
0x12
P30
P30 used as TI11
0x13
P31
P31 used as TI11
0x14
P40
P40 used as TI11
0x15
P41
P41 used as TI11
0x16
P50
P50 used as TI11
0x17
P51
P51 used as TI11
0x18
P60
P60 used as TI11
0x19
P61
P61 used as TI11
0x1A
P62
P62 used as TI11
0x1B
P63
P63 used as TI11
0x1C
P70
P70 used as TI11
0x1D
P71
P71 used as TI11
0x1E
P72
P72 used as TI11
0x1F
P73
P73 used as TI11
0x20
P74
P74 used as TI11
0x21
P75
P75 used as TI11
0x22
P120
P120 used as TI11
0x23
P121
P121 used as TI11
0x24
P122
P122 used as TI11
0x25
P123
P123 used as TI11
0x26
P124
P124 used as TI11
0x27
P130
P130 used as TI11
0x28
P136
P136 used as TI11
0x29
P137
P137 used as TI11
0x2A
P140
P140 used as TI11
0x2B
P146
P146 used as TI11
0x2C
P147
P147 used as TI11
0x2D
TI12PCFG
TI12 alternate function pin configuration register
0x862
8
read-write
n
0x0
0x0
CFG
0
6
P00
P00 used as TI12
0x01
P01
P01 used as TI12
0x02
P10
P10 used as TI12
0x03
P11
P11 used as TI12
0x04
P12
P12 used as TI12
0x05
P13
P13 used as TI12
0x06
P14
P14 used as TI12
0x07
P15
P15 used as TI12
0x08
P16
P16 used as TI12
0x09
P17
P17 used as TI12
0x0A
P20
P20 used as TI12
0x0B
P21
P21 used as TI12
0x0C
P22
P22 used as TI12
0x0D
P23
P23 used as TI12
0x0E
P24
P24 used as TI12
0x0F
P25
P25 used as TI12
0x10
P26
P26 used as TI12
0x11
P27
P27 used as TI12
0x12
P30
P30 used as TI12
0x13
P31
P31 used as TI12
0x14
P40
P40 used as TI12
0x15
P41
P41 used as TI12
0x16
P50
P50 used as TI12
0x17
P51
P51 used as TI12
0x18
P60
P60 used as TI12
0x19
P61
P61 used as TI12
0x1A
P62
P62 used as TI12
0x1B
P63
P63 used as TI12
0x1C
P70
P70 used as TI12
0x1D
P71
P71 used as TI12
0x1E
P72
P72 used as TI12
0x1F
P73
P73 used as TI12
0x20
P74
P74 used as TI12
0x21
P75
P75 used as TI12
0x22
P120
P120 used as TI12
0x23
P121
P121 used as TI12
0x24
P122
P122 used as TI12
0x25
P123
P123 used as TI12
0x26
P124
P124 used as TI12
0x27
P130
P130 used as TI12
0x28
P136
P136 used as TI12
0x29
P137
P137 used as TI12
0x2A
P140
P140 used as TI12
0x2B
P146
P146 used as TI12
0x2C
P147
P147 used as TI12
0x2D
TI13PCFG
TI13 alternate function pin configuration register
0x863
8
read-write
n
0x0
0x0
CFG
0
6
P00
P00 used as TI13
0x01
P01
P01 used as TI13
0x02
P10
P10 used as TI13
0x03
P11
P11 used as TI13
0x04
P12
P12 used as TI13
0x05
P13
P13 used as TI13
0x06
P14
P14 used as TI13
0x07
P15
P15 used as TI13
0x08
P16
P16 used as TI13
0x09
P17
P17 used as TI13
0x0A
P20
P20 used as TI13
0x0B
P21
P21 used as TI13
0x0C
P22
P22 used as TI13
0x0D
P23
P23 used as TI13
0x0E
P24
P24 used as TI13
0x0F
P25
P25 used as TI13
0x10
P26
P26 used as TI13
0x11
P27
P27 used as TI13
0x12
P30
P30 used as TI13
0x13
P31
P31 used as TI13
0x14
P40
P40 used as TI13
0x15
P41
P41 used as TI13
0x16
P50
P50 used as TI13
0x17
P51
P51 used as TI13
0x18
P60
P60 used as TI13
0x19
P61
P61 used as TI13
0x1A
P62
P62 used as TI13
0x1B
P63
P63 used as TI13
0x1C
P70
P70 used as TI13
0x1D
P71
P71 used as TI13
0x1E
P72
P72 used as TI13
0x1F
P73
P73 used as TI13
0x20
P74
P74 used as TI13
0x21
P75
P75 used as TI13
0x22
P120
P120 used as TI13
0x23
P121
P121 used as TI13
0x24
P122
P122 used as TI13
0x25
P123
P123 used as TI13
0x26
P124
P124 used as TI13
0x27
P130
P130 used as TI13
0x28
P136
P136 used as TI13
0x29
P137
P137 used as TI13
0x2A
P140
P140 used as TI13
0x2B
P146
P146 used as TI13
0x2C
P147
P147 used as TI13
0x2D
RST
Reset Function
RST
0x0
0x0
0x40
registers
n
RESF
Reset flag register
0x20
8
read-only
n
0x0
0x0
IAWRF
Internal reset request by illegal-memory access
1
2
clear
NONE
Internal reset request is not generated, or the RESF register is cleared.
0
DONE
Internal reset request is generated.
1
LVIRF
Internal reset request by voltage detector
0
1
clear
NONE
Internal reset request is not generated, or the RESF register is cleared.
0
DONE
Internal reset request is generated.
1
RPERF
Internal reset request by RAM parity
2
3
clear
NONE
Internal reset request is not generated, or the RESF register is cleared.
0
DONE
Internal reset request is generated.
1
SYSRF
Internal reset request by system reset request(AIRCR.SYSRESETREQ)
7
8
clear
NONE
Internal reset request is not generated, or the RESF register is cleared.
0
DONE
Internal reset request is generated.
1
WDTRF
Internal reset request by watchdog timer(WDT)
4
5
clear
NONE
Internal reset request is not generated, or the RESF register is cleared.
0
DONE
Internal reset request is generated.
1
RTC
Real-Time clock
RTC
0x0
0x0
0x100
registers
n
RTC
Real-Time Clock interrupt request
22
IT
15-bit interval timer interrupt request
23
ALARMWH
Alarm hour register
0x5B
8
read-write
n
0x0
0x0
ALARMWM
Alarm minute register
0x5A
8
read-write
n
0x0
0x0
ALARMWW
Alarm week register
0x5C
8
read-write
n
0x0
0x0
DAY
Day count register
0x56
8
read-write
n
0x0
0x0
HOUR
Hour count register
0x54
8
read-write
n
0x0
0x0
ITMC
15-bit interval timer control register
0x50
16
read-write
n
0x0
0x0
ITCMP
15-bit interval timer compare value
0
15
RINTE
15-bit interval timer operation control
15
16
MIN
Minute count register
0x53
8
read-write
n
0x0
0x0
MONTH
Month count register
0x57
8
read-write
n
0x0
0x0
RTCC0
Real-time clock control register 0
0x5D
8
read-write
n
0x0
0x0
AMPM
Selection of 12-/24-hour system
3
4
CT
Constant-period interrupt (INTRTC) selection
0
3
RCLOE
RTC1HZ pin output enable
5
6
RTCE
Real-time clock operation control
7
8
RTCC1
Real-time clock control register 1
0x5E
8
read-write
n
0x0
0x0
RIFG
Constant-period interrupt status flag
3
4
RWAIT
Wait control of real-time clock
0
1
RWST
Wait status flag of real-time clock
1
2
WAFG
Alarm detection status flag
4
5
WALE
Alarm operation control
7
8
WALIE
Control of alarm interrupt (INTRTC) function operation
6
7
SEC
Second count register
0x52
8
read-write
n
0x0
0x0
SUBCUD
Watch error correction register
0x34
16
read-write
n
0x0
0x0
DEV
watch error correction timing
15
16
F
watch error correction value
0
13
WEEK
Week count register
0x55
8
read-write
n
0x0
0x0
YEAR
Year count register
0x58
8
read-write
n
0x0
0x0
SAF
Flash memory CRC operation function (High-Speed CRC)
SAF
0x0
0x0
0x30000
registers
n
CRC0CTL
Flash memory CRC control register
0x1710
8
read-write
n
0x0
0x0
CRC0EN
Control of high-speed CRC operation
7
8
FEA
High-speed CRC operation range
0
7
CRCD
CRC data register
0x231FA
16
read-write
n
0x0
0x0
CRCIN
CRC input register
0x232AC
8
read-write
n
0x0
0x0
PGCRCL
Flash memory CRC operation result register
0x1712
16
read-write
n
0x0
0x0
RPECTL
RAM parity error control register
0x325
8
read-write
n
0x0
0x0
RPEF
Parity error status flag
0
1
read-write
NoError
No parity error has occurred
0
Error
Parity error has occurred
1
RPERDIS
Disable RAM parity error reset
7
8
read-write
Enable
Enable parity error reset
0
Disable
Disable parity error reset
1
SFRGD
SFR guard control register
0x20378
-1
read-write
n
0x0
0x0
SCI0
Serial Communication Interface 0 with UART, SPI and simplified I2C supported
SCI0
0x0
0x0
0x300
registers
n
ST0
UART0 transmission transfer end or buffer empty
10
SR0
UART0 rerception transfer
11
SRE0
UART0 rerception communication error occurrence
12
ST1
UART1 transmission transfer end or buffer empty
13
SR1
UART1 rerception transfer
14
SRE1
UART1 rerception communication error occurrence
15
RXD0
UART receive data register
SDR01
0x212
8
read-write
n
0x0
0x0
RXD1
UART receive data register
SDR03
0x246
8
read-write
n
0x0
0x0
SCR00
Serial communication operation setting register mn
0x18
-1
read-write
n
0x0
0x0
CKP
Selection of clock phase in SPI mode
12
13
DAP
Selection of data phase in SPI mode
13
14
DIR
Selection of data transfer sequence in SPI and UART modes
7
8
DLS
Setting of data length in SPI and UART modes
0
2
EOC
Mask control of error interrupt signal (INTSREx (x = 0 to 2))
10
11
PTC
Setting of parity bit in UART mode
8
10
RXE
Reception enable
14
15
SLC
Setting of stop bit in UART mode
4
6
TXE
Transmission enable
15
16
SCR01
Serial communication operation setting register mn
0x1A
-1
read-write
n
0x0
0x0
SCR02
Serial communication operation setting register mn
0x1C
-1
read-write
n
0x0
0x0
SCR03
Serial communication operation setting register mn
0x1E
-1
read-write
n
0x0
0x0
SDR00
Serial data register 0%s
0x210
-1
read-write
n
0x0
0x0
SDR01
Serial data register 0%s
0x212
-1
read-write
n
0x0
0x0
SDR02
Serial data register 0%s
0x244
-1
read-write
n
0x0
0x0
SDR03
Serial data register 0%s
0x246
-1
read-write
n
0x0
0x0
SE0
Serial channel enable status register m
0x20
-1
read-only
n
0x0
0x0
SE00
Indication of operation enable/stop status of channel 0
0
1
SE01
Indication of operation enable/stop status of channel 1
1
2
SE02
Indication of operation enable/stop status of channel 2
2
3
SE03
Indication of operation enable/stop status of channel 3
3
4
SIO00
SPI data register
SDR00
0x210
8
read-write
n
0x0
0x0
SIO01
SPI data register
SDR01
0x212
8
read-write
n
0x0
0x0
SIO10
SPI data register
SDR02
0x244
8
read-write
n
0x0
0x0
SIO11
SPI data register
SDR03
0x246
8
read-write
n
0x0
0x0
SIR00
Serial flag clear trigger register mn
0x8
-1
read-write
n
0x0
0x0
FECT
Clear trigger of framing error flag of channel n
2
3
OVCT
Clear trigger of overrun error flag of channel n
0
1
PECT
Clear trigger of parity error flag of channel n
1
2
SIR01
Serial flag clear trigger register mn
0xA
-1
read-write
n
0x0
0x0
SIR02
Serial flag clear trigger register mn
0xC
-1
read-write
n
0x0
0x0
SIR03
Serial flag clear trigger register mn
0xE
-1
read-write
n
0x0
0x0
SMR00
Serial mode register mn
0x10
-1
read-write
n
0x0
0x0
CCS
Selection of transfer clock (fTCLK) of channel n
14
15
CKS
Selection of operation clock (fMCK) of channel n
15
16
MD
Setting of operation mode of channel n
0
4
SIS
Controls inversion of level of receive data of channel n in UART mode
6
7
STS
Selection of start trigger source
8
9
SMR01
Serial mode register mn
0x12
-1
read-write
n
0x0
0x0
SMR02
Serial mode register mn
0x14
-1
read-write
n
0x0
0x0
SMR03
Serial mode register mn
0x16
-1
read-write
n
0x0
0x0
SO0
Serial output register 0
0x28
-1
read-write
n
0x0
0x0
CKO00
Serial clock output of channel 0
8
9
CKO01
Serial clock output of channel 1
9
10
CKO02
Serial clock output of channel 2
10
11
CKO03
Serial clock output of channel 3
11
12
SO00
Serial data output of channel 0
0
1
SO01
Serial data output of channel 1
1
2
SO02
Serial data output of channel 2
2
3
SO03
Serial data output of channel 3
3
4
SOE0
Serial output enable register 0
0x2A
-1
read-write
n
0x0
0x0
SOE00
Serial output enable of channel 0
0
1
SOE01
Serial output enable of channel 1
1
2
SOE02
Serial output enable of channel 2
2
3
SOE03
Serial output enable of channel 3
3
4
SOL0
Serial output level register 0
0x34
-1
read-write
n
0x0
0x0
SOL00
Selects inversion of the level of the transmit data of channel n in UART mode
0
1
SOL02
Selects inversion of the level of the transmit data of channel n in UART mode
2
3
SPS0
Serial clock select register 0
0x26
-1
read-write
n
0x0
0x0
PRS00
Prescaler 0
0
4
PRS01
Prescaler 1
4
8
SS0
Serial channel start register 0
0x22
-1
read-write
n
0x0
0x0
SS00
Operation start trigger of channel 0
0
1
SS01
Operation start trigger of channel 1
1
2
SS02
Operation start trigger of channel 2
2
3
SS03
Operation start trigger of channel 3
3
4
SSR00
Serial status register mn
0x0
-1
read-only
n
0x0
0x0
BFF
Buffer register status indication flag of channel n
5
6
FEF
Framing error detection flag of channel n
2
3
OVF
Overrun error detection flag of channel n
0
1
PEF
Parity error detection flag of channel n
1
2
TSF
Communication status indication flag of channel n
6
7
SSR01
Serial status register mn
0x2
-1
read-write
n
0x0
0x0
SSR02
Serial status register mn
0x4
-1
read-write
n
0x0
0x0
SSR03
Serial status register mn
0x6
-1
read-write
n
0x0
0x0
ST0
Serial channel stop register 0
0x24
-1
read-write
n
0x0
0x0
ST00
Operation stop trigger of channel 0
0
1
ST01
Operation stop trigger of channel 1
1
2
ST02
Operation stop trigger of channel 2
2
3
ST03
Operation stop trigger of channel 3
3
4
TXD0
UART transmit data register
SDR00
0x210
8
read-write
n
0x0
0x0
TXD1
UART transmit data register
SDR02
0x244
8
read-write
n
0x0
0x0
SCI1
Serial Communication Interface 1 with UART, SPI and simplified I2C supported
SCI1
0x0
0x0
0x300
registers
n
ST2
UART2 transmission transfer end or buffer empty
7
SR2
UART2 rerception transfer
8
SRE2
UART2 rerception communication error occurrence
9
RXD2
UART receive data register
SDR11
0x20A
8
read-write
n
0x0
0x0
SCR10
Serial communication operation setting register mn
0x18
-1
read-write
n
0x0
0x0
CKP
Selection of clock phase in SPI mode
12
13
DAP
Selection of data phase in SPI mode
13
14
DIR
Selection of data transfer sequence in SPI and UART modes
7
8
DLS
Setting of data length in SPI and UART modes
0
2
EOC
Mask control of error interrupt signal (INTSREx (x = 0 to 2))
10
11
PTC
Setting of parity bit in UART mode
8
10
RXE
Reception enable
14
15
SLC
Setting of stop bit in UART mode
4
6
TXE
Transmission enable
15
16
SCR11
Serial communication operation setting register mn
0x1A
-1
read-write
n
0x0
0x0
SDR10
Serial data register 1%s
0x208
-1
read-write
n
0x0
0x0
SDR11
Serial data register 1%s
0x20A
-1
read-write
n
0x0
0x0
SE1
Serial channel enable status register 1
0x20
-1
read-only
n
0x0
0x0
SE10
Indication of operation enable/stop status of channel 0
0
1
SE11
Indication of operation enable/stop status of channel 1
1
2
SIO20
SPI data register
SDR10
0x208
8
read-write
n
0x0
0x0
SIO21
SPI data register
SDR11
0x20A
8
read-write
n
0x0
0x0
SIR10
Serial flag clear trigger register mn
0x8
-1
read-write
n
0x0
0x0
FECT
Clear trigger of framing error flag of channel n
2
3
OVCT
Clear trigger of overrun error flag of channel n
0
1
PECT
Clear trigger of parity error flag of channel n
1
2
SIR11
Serial flag clear trigger register mn
0xA
-1
read-write
n
0x0
0x0
SMR10
Serial mode register mn
0x10
-1
read-write
n
0x0
0x0
CCS
Selection of transfer clock (fTCLK) of channel n
14
15
CKS
Selection of operation clock (fMCK) of channel n
15
16
MD
Setting of operation mode of channel n
0
4
SIS
Controls inversion of level of receive data of channel n in UART mode
6
7
STS
Selection of start trigger source
8
9
SMR11
Serial mode register mn
0x12
-1
read-write
n
0x0
0x0
SO1
Serial output register 1
0x28
-1
read-write
n
0x0
0x0
CKO10
Serial clock output of channel 0
8
9
CKO11
Serial clock output of channel 1
9
10
SO10
Serial data output of channel 0
0
1
SO11
Serial data output of channel 1
1
2
SOE1
Serial output enable register 1
0x2A
-1
read-write
n
0x0
0x0
SOE10
Serial output enable of channel 0
0
1
SOE11
Serial output enable of channel 1
1
2
SOL1
Serial output level register 1
0x34
-1
read-write
n
0x0
0x0
SOL10
Selects inversion of the level of the transmit data of channel n in UART mode
0
1
SPS1
Serial clock select register 1
0x26
-1
read-write
n
0x0
0x0
PRS10
Prescaler 0
0
4
PRS11
Prescaler 1
4
8
SS1
Serial channel start register 1
0x22
-1
read-write
n
0x0
0x0
SS10
Operation start trigger of channel 0
0
1
SS11
Operation start trigger of channel 1
1
2
SSR10
Serial status register mn
0x0
-1
read-only
n
0x0
0x0
BFF
Buffer register status indication flag of channel n
5
6
FEF
Framing error detection flag of channel n
2
3
OVF
Overrun error detection flag of channel n
0
1
PEF
Parity error detection flag of channel n
1
2
TSF
Communication status indication flag of channel n
6
7
SSR11
Serial status register mn
0x2
-1
read-write
n
0x0
0x0
ST1
Serial channel stop register 1
0x24
-1
read-write
n
0x0
0x0
ST10
Operation stop trigger of channel 0
0
1
ST11
Operation stop trigger of channel 1
1
2
TXD2
UART transmit data register
SDR10
0x208
8
read-write
n
0x0
0x0
SPI
Serial Interface SPI
SPI
0x0
0x0
0x200
registers
n
SDRI
Data buffer of reception
0xC
-1
read-write
n
0x0
0x0
SDRO
Data buffer of transmission
0x8
-1
read-write
n
0x0
0x0
SPIC
SPI control register
0x4
-1
read-write
n
0x0
0x0
CKP
Selection of clock phase for SPI
4
5
read-write
CKS
Operation clock control
0
3
read-write
DAP
Selection of data phase for SPI
3
4
read-write
SPIM
SPI mode control register
0x0
-1
read-write
n
0x0
0x0
DIR
MSB of LSB mode select
4
5
DLS
data length control
2
3
INTMD
interrupt source select
3
4
NSSE
NSS pin enable
5
6
SDRIF
Receive buffer non-empty flag
1
2
SPIE
SPI operation enable
7
8
SPTF
SPI transmission status flag
0
1
TRMD
Transfer and Receive mode
6
7
TM40
General Purpose Timer 4
TM40
0x0
0x0
0x200
registers
n
TM01H
TM40 channel 1(higher 8 bit) interrupt request
5
TM00
TM40 channel 0 interrupt request
17
TM01
TM40 channel 1 interrupt request
18
TM02
TM40 channel 2 interrupt request
19
TM03
TM40 channel 3 interrupt request
20
TCR00
Timer count register 0%s
0x0
-1
read-only
n
0x0
0x0
TCR01
Timer count register 0%s
0x2
-1
read-only
n
0x0
0x0
TCR02
Timer count register 0%s
0x4
-1
read-only
n
0x0
0x0
TCR03
Timer count register 0%s
0x6
-1
read-only
n
0x0
0x0
TDR00
Timer data register 0%s
0x198
-1
read-write
n
0x0
0x0
TDR01
Timer data register 0%s
0x19A
-1
read-write
n
0x0
0x0
TDR01H
Timer data higher register 01
TDR01
0x19B
8
read-write
n
0x0
0x0
TDR01L
Timer data lower register 01
TDR01
0x19A
8
read-write
n
0x0
0x0
TDR02
Timer data register 0%s
0x1E4
-1
read-write
n
0x0
0x0
TDR03
Timer data register 0%s
0x1E6
-1
read-write
n
0x0
0x0
TDR03H
Timer data higher register 03
TDR03
0x1E7
8
read-write
n
0x0
0x0
TDR03L
Timer data lower register 03
TDR03
0x1E6
8
read-write
n
0x0
0x0
TE0
Timer channel enable status register m
0x30
-1
read-only
n
0x0
0x0
TE00
Indication of operation enable/stop status of channel 0
0
1
TE01
Indication of operation enable/stop status of channel 1
1
2
TE02
Indication of operation enable/stop status of channel 2
2
3
TE03
Indication of operation enable/stop status of channel 3
3
4
TEH01
Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 1 is in the 8-bit timer mode
9
10
TEH03
Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 3 is in the 8-bit timer mode
11
12
TMR00
Timer mode register mn
0x10
-1
read-write
n
0x0
0x0
CCS
Selection of count clock (fTCLK) of channel n
12
13
read-write
CIS
Selection of TImn pin input valid edge
6
8
read-write
CKS
Selection of operation clock (fMCK) of channel n
14
16
read-write
MD
Operation mode of channel n
0
4
read-write
STS
Setting of start trigger or capture trigger of channel n
8
11
read-write
TMR01
Timer mode register mn
0x12
-1
read-write
n
0x0
0x0
CCS
Selection of count clock (fTCLK) of channel n
12
13
read-write
CIS
Selection of TImn pin input valid edge
6
8
read-write
CKS
Selection of operation clock (fMCK) of channel n
14
16
read-write
MD
Operation mode of channel n
0
4
read-write
SPLIT
Selection of 8 or 16-bit timer operation for channels 1 and 3
11
12
read-write
STS
Setting of start trigger or capture trigger of channel n
8
11
read-write
TMR02
Timer mode register mn
0x14
-1
read-write
n
0x0
0x0
CCS
Selection of count clock (fTCLK) of channel n
12
13
read-write
CIS
Selection of TImn pin input valid edge
6
8
read-write
CKS
Selection of operation clock (fMCK) of channel n
14
16
read-write
MASTER
Selection between using channel n independently or simultaneously with another channel (as a slave or master)
11
12
read-write
MD
Operation mode of channel n
0
4
read-write
STS
Setting of start trigger or capture trigger of channel n
8
11
read-write
TMR03
Timer mode register mn
0x16
-1
read-write
n
0x0
0x0
CCS
Selection of count clock (fTCLK) of channel n
12
13
read-write
CIS
Selection of TImn pin input valid edge
6
8
read-write
CKS
Selection of operation clock (fMCK) of channel n
14
16
read-write
MD
Operation mode of channel n
0
4
read-write
SPLIT
Selection of 8 or 16-bit timer operation for channels 1 and 3
11
12
read-write
STS
Setting of start trigger or capture trigger of channel n
8
11
read-write
TO0
Timer output register 0
0x38
-1
read-write
n
0x0
0x0
TO00
Timer output of channel 0
0
1
TO01
Timer output of channel 1
1
2
TO02
Timer output of channel 2
2
3
TO03
Timer output of channel 3
3
4
TOE0
Timer output enable register 0
0x3A
-1
read-write
n
0x0
0x0
TOE00
Timer output enable of channel 0
0
1
TOE01
Timer output enable of channel 1
1
2
TOE02
Timer output enable of channel 2
2
3
TOE03
Timer output enable of channel 3
3
4
TOL0
Timer output level register 0
0x3C
-1
read-write
n
0x0
0x0
TOL01
Control of timer output level of channel 1
1
2
TOL02
Control of timer output level of channel 2
2
3
TOL03
Control of timer output level of channel 3
3
4
TOM0
Timer output mode register 0
0x3E
-1
read-write
n
0x0
0x0
TOM01
Control of timer output mode of channel 1
1
2
TOM02
Control of timer output mode of channel 2
2
3
TOM03
Control of timer output mode of channel 3
3
4
TPS0
Timer clock select register 0
0x36
-1
read-write
n
0x0
0x0
PRS00
Prescaler 0
0
4
PRS01
Prescaler 1
4
8
PRS02
Prescaler 2
8
10
PRS03
Prescaler 3
12
14
TS0
Timer channel start register 0
0x32
-1
read-write
n
0x0
0x0
TS00
Operation enable (start) trigger of channel 0
0
1
TS01
Operation enable (start) trigger of channel 1
1
2
TS02
Operation enable (start) trigger of channel 2
2
3
TS03
Operation enable (start) trigger of channel 3
3
4
TSH01
Trigger to enable operation (start operation) of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
9
10
TSH03
Trigger to enable operation (start operation) of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
11
12
TSR00
Timer status register mn
0x20
-1
read-only
n
0x0
0x0
OVF
Counter overflow status of channel n
0
1
TSR01
Timer status register mn
0x22
-1
read-write
n
0x0
0x0
TSR02
Timer status register mn
0x24
-1
read-write
n
0x0
0x0
TSR03
Timer status register mn
0x26
-1
read-write
n
0x0
0x0
TT0
Timer channel stop register 0
0x34
-1
read-write
n
0x0
0x0
TT00
Operation stop trigger of channel 0
0
1
TT01
Operation stop trigger of channel 1
1
2
TT02
Operation stop trigger of channel 2
2
3
TT03
Operation stop trigger of channel 3
3
4
TTH01
Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
9
10
TTH03
Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
11
12
TM41
General Purpose Timer 4
TM41
0x0
0x0
0x200
registers
n
TM10
TM41 channel 0 interrupt request
27
TM11
TM41 channel 1 interrupt request
28
TM12
TM41 channel 2 interrupt request
29
TM13
TM41 channel 3 interrupt request
30
TCR10
Timer count register 0%s
0x0
-1
read-only
n
0x0
0x0
TCR11
Timer count register 0%s
0x2
-1
read-only
n
0x0
0x0
TCR12
Timer count register 0%s
0x4
-1
read-only
n
0x0
0x0
TCR13
Timer count register 0%s
0x6
-1
read-only
n
0x0
0x0
TDR10
Timer data register 0%s
0x198
-1
read-write
n
0x0
0x0
TDR11
Timer data register 0%s
0x19A
-1
read-write
n
0x0
0x0
TDR11H
Timer data higher register 01
TDR11
0x19B
8
read-write
n
0x0
0x0
TDR11L
Timer data lower register 01
TDR11
0x19A
8
read-write
n
0x0
0x0
TDR12
Timer data register 0%s
0x1E4
-1
read-write
n
0x0
0x0
TDR13
Timer data register 0%s
0x1E6
-1
read-write
n
0x0
0x0
TDR13H
Timer data higher register 03
TDR13
0x1E7
8
read-write
n
0x0
0x0
TDR13L
Timer data lower register 03
TDR13
0x1E6
8
read-write
n
0x0
0x0
TE1
Timer channel enable status register m
0x30
-1
read-only
n
0x0
0x0
TE10
Indication of operation enable/stop status of channel 0
0
1
TE11
Indication of operation enable/stop status of channel 1
1
2
TE12
Indication of operation enable/stop status of channel 2
2
3
TE13
Indication of operation enable/stop status of channel 3
3
4
TEH11
Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 1 is in the 8-bit timer mode
9
10
TEH13
Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 3 is in the 8-bit timer mode
11
12
TMR10
Timer mode register mn
0x10
-1
read-write
n
0x0
0x0
CCS
Selection of count clock (fTCLK) of channel n
12
13
read-write
CIS
Selection of TImn pin input valid edge
6
8
read-write
CKS
Selection of operation clock (fMCK) of channel n
14
16
read-write
MD
Operation mode of channel n
0
4
read-write
STS
Setting of start trigger or capture trigger of channel n
8
11
read-write
TMR11
Timer mode register mn
0x12
-1
read-write
n
0x0
0x0
CCS
Selection of count clock (fTCLK) of channel n
12
13
read-write
CIS
Selection of TImn pin input valid edge
6
8
read-write
CKS
Selection of operation clock (fMCK) of channel n
14
16
read-write
MD
Operation mode of channel n
0
4
read-write
SPLIT
Selection of 8 or 16-bit timer operation for channels 1 and 3
11
12
read-write
STS
Setting of start trigger or capture trigger of channel n
8
11
read-write
TMR12
Timer mode register mn
0x14
-1
read-write
n
0x0
0x0
CCS
Selection of count clock (fTCLK) of channel n
12
13
read-write
CIS
Selection of TImn pin input valid edge
6
8
read-write
CKS
Selection of operation clock (fMCK) of channel n
14
16
read-write
MASTER
Selection between using channel n independently or simultaneously with another channel (as a slave or master)
11
12
read-write
MD
Operation mode of channel n
0
4
read-write
STS
Setting of start trigger or capture trigger of channel n
8
11
read-write
TMR13
Timer mode register mn
0x16
-1
read-write
n
0x0
0x0
CCS
Selection of count clock (fTCLK) of channel n
12
13
read-write
CIS
Selection of TImn pin input valid edge
6
8
read-write
CKS
Selection of operation clock (fMCK) of channel n
14
16
read-write
MD
Operation mode of channel n
0
4
read-write
SPLIT
Selection of 8 or 16-bit timer operation for channels 1 and 3
11
12
read-write
STS
Setting of start trigger or capture trigger of channel n
8
11
read-write
TO1
Timer output register 0
0x38
-1
read-write
n
0x0
0x0
TO10
Timer output of channel 0
0
1
TO11
Timer output of channel 1
1
2
TO12
Timer output of channel 2
2
3
TO13
Timer output of channel 3
3
4
TOE1
Timer output enable register 0
0x3A
-1
read-write
n
0x0
0x0
TOE10
Timer output enable of channel 0
0
1
TOE11
Timer output enable of channel 1
1
2
TOE12
Timer output enable of channel 2
2
3
TOE13
Timer output enable of channel 3
3
4
TOL1
Timer output level register 0
0x3C
-1
read-write
n
0x0
0x0
TOL11
Control of timer output level of channel 1
1
2
TOL12
Control of timer output level of channel 2
2
3
TOL13
Control of timer output level of channel 3
3
4
TOM1
Timer output mode register 0
0x3E
-1
read-write
n
0x0
0x0
TOM11
Control of timer output mode of channel 1
1
2
TOM12
Control of timer output mode of channel 2
2
3
TOM13
Control of timer output mode of channel 3
3
4
TPS1
Timer clock select register 0
0x36
-1
read-write
n
0x0
0x0
PRS10
Prescaler 0
0
4
PRS11
Prescaler 1
4
8
PRS12
Prescaler 2
8
10
PRS13
Prescaler 3
12
14
TS1
Timer channel start register 0
0x32
-1
read-write
n
0x0
0x0
TS10
Operation enable (start) trigger of channel 0
0
1
TS11
Operation enable (start) trigger of channel 1
1
2
TS12
Operation enable (start) trigger of channel 2
2
3
TS13
Operation enable (start) trigger of channel 3
3
4
TSH11
Trigger to enable operation (start operation) of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
9
10
TSH13
Trigger to enable operation (start operation) of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
11
12
TSR10
Timer status register mn
0x20
-1
read-only
n
0x0
0x0
OVF
Counter overflow status of channel n
0
1
TSR11
Timer status register mn
0x22
-1
read-write
n
0x0
0x0
TSR12
Timer status register mn
0x24
-1
read-write
n
0x0
0x0
TSR13
Timer status register mn
0x26
-1
read-write
n
0x0
0x0
TT1
Timer channel stop register 0
0x34
-1
read-write
n
0x0
0x0
TT10
Operation stop trigger of channel 0
0
1
TT11
Operation stop trigger of channel 1
1
2
TT12
Operation stop trigger of channel 2
2
3
TT13
Operation stop trigger of channel 3
3
4
TTH11
Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
9
10
TTH13
Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
11
12
TSN
Temperature Sensor calibration data
TSN
0x0
0x0
0x8
registers
n
TSN25
The A/D conversion value of Temperature Sensor at 25 degrees and 3.0V reference voltage
0x4
-1
read-only
n
0x0
0x0
int16_t
TSN85
The A/D conversion value of Temperature Sensor at 85 degrees and 3.0V reference voltage
0x0
-1
read-only
n
0x0
0x0
int16_t
UID
128-bit Unique ID
UID
0x0
0x0
0x80
registers
n
UID0
UID word %s
0x0
-1
read-only
n
0x0
0x0
UID1
UID word %s
0x4
-1
read-only
n
0x0
0x0
UID2
UID word %s
0x8
-1
read-only
n
0x0
0x0
UID3
UID word %s
0xC
-1
read-only
n
0x0
0x0
WDT
Watchdog Timer with window
WDT
0x0
0x0
0xC00
registers
n
LOCKCTL
Lockup Watchdog timer enable register
0x1
-1
read-write
n
0x0
0x0
PRCR
Lockup Watchdog timer enable protect register
0x2
-1
read-write
n
0x0
0x0
WDTE
Watchdog timer enable register
0xBFD
-1
read-write
n
0x0
0x0