CMS
BAT32G137
2024.05.05
ARM 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48MHz, etc.
CM0+
r0p1
little
2
false
8
32
ADC
A/D Converter
ADC
0x0
0x0
0x100
registers
n
ADC
ADC interrupt request
21
ADCR
12-bit A/D conversion result register
0xE
16
read-write
n
0x0
0x0
ADCRH
Higher 8-bit A/D conversion result register
ADCR
0xF
8
read-write
n
0x0
0x0
ADFLG
A/D flag register
0x16
8
read-write
n
0x0
0x0
ADLL
Conversion result comparison lower limit setting register
0xA
8
read-write
n
0x0
0x0
ADM0
A/D mode register 0
0x0
8
read-write
n
0x0
0x0
ADCE
A/D enable
0
1
ADCS
A/D conversion operation control
7
8
FR
A/D conversion clock (fAD) select
3
6
ADM1
A/D mode register 1
0x2
8
read-write
n
0x0
0x0
ADMD
A/D conversion channel select mode
7
8
Select
Select mode
0
Scan
Scan mode
1
ADMODE
A/D mode select
0
2
ADSCM
A/D conversion mode
3
4
Sequential
Sequential conversion mode
0
OneShot
One-shot conversion mode
1
ADM2
A/D mode register 2
0x4
8
read-write
n
0x0
0x0
ADRCK
the upper limit and lower limit conversion result values
3
4
ADREFM
Selection of the - side reference voltage of A/D converter
5
6
VSS
Supplied from VSS
0
AVREFM
Supplied from AVREFM
1
ADREFP
Selection of the + side reference voltage of A/D converter
6
8
VDD
Supplied from VDD
0b00
AVREFP0
Supplied from AVREFP
0b01
AVREFP1
Supplied from inside AVREF of A/D
0b10
CHRDE
output CH number in A/D conversion result in Scan mode
1
2
ADNDIS
A/D charge/discharge control register
0x11
8
read-write
n
0x0
0x0
ADNSMP
A/D sampling time control register
0xC
8
read-write
n
0x0
0x0
ADS
Analog input channel specification register
0x8
8
read-write
n
0x0
0x0
ADSMPWAIT
A/D sampling wait control register
0x15
8
read-write
n
0x0
0x0
ADTES
A/D test register
0x10
8
read-write
n
0x0
0x0
ADTRG
A/D mode register 2
0x6
8
read-write
n
0x0
0x0
ADTMD
A/D conversion trigger mode
6
8
ADTRS
A/D hard trigger select
0
2
ADUL
Conversion result comparison upper limit setting register
0xB
8
read-write
n
0x0
0x0
BGR
Temperature Sensor calibration data
BGR
0x0
0x0
0x8
registers
n
VBG25
The A/D conversion value of VBGR at 25 degrees and 3.0V reference voltage
0x4
-1
read-only
n
0x0
0x0
VBG85
The A/D conversion value of VBGR at 85 degrees and 3.0V reference voltage
0x0
-1
read-only
n
0x0
0x0
CAN
CAN Controller
CAN
0x0
0x0
0x100
registers
n
C0BRP
CAN0 module bit rate prescaler register
0x5A
8
read-write
n
0x0
0x0
C0BTR
CAN0 module bit rate register
0x5C
16
read-write
n
0x0
0x0
C0CTRL
CAN0 module control register
0x50
16
read-write
n
0x0
0x0
C0ERC
CAN0 module error counter register
0x54
16
read-only
n
0x0
0x0
C0GMABT
CAN0 global automatic block transmission control register
0x6
16
read-write
n
0x0
0x0
C0GMABTD
CAN0 global automatic block transmission delay setting register
0x8
8
read-write
n
0x0
0x0
C0GMCS
CAN0 global module clock select register
0x2
8
read-write
n
0x0
0x0
C0GMCTRL
CAN0 global module control register
0x0
16
read-write
n
0x0
0x0
C0IE
CAN0 module interrupt enable register
0x56
16
read-write
n
0x0
0x0
C0INFO
CAN0 module information register
0x53
8
read-only
n
0x0
0x0
C0INTS
CAN0 module interrupt status register
0x58
16
read-write
n
0x0
0x0
C0LEC
CAN0 module last error code register
0x52
8
read-write
n
0x0
0x0
C0LIPT
CAN0 module last in-pointer register
0x5E
8
read-only
n
0x0
0x0
C0LOPT
CAN0 module last out-pointer register
0x62
8
read-only
n
0x0
0x0
C0MASK1H
CAN0 module mask 1 register
0x42
-1
read-write
n
0x0
0x0
C0MASK1L
CAN0 module mask 1 register
0x40
-1
read-write
n
0x0
0x0
C0MASK2H
CAN0 module mask 2 register
0x46
-1
read-write
n
0x0
0x0
C0MASK2L
CAN0 module mask 2 register
0x44
-1
read-write
n
0x0
0x0
C0MASK3H
CAN0 module mask 3 register
0x4A
-1
read-write
n
0x0
0x0
C0MASK3L
CAN0 module mask 3 register
0x48
-1
read-write
n
0x0
0x0
C0MASK4H
CAN0 module mask 4 register
0x4E
-1
read-write
n
0x0
0x0
C0MASK4L
CAN0 module mask 4 register
0x4C
-1
read-write
n
0x0
0x0
C0RGPT
CAN0 module receive history list register
0x60
16
read-write
n
0x0
0x0
C0TGPT
CAN0 module transmit history list register
0x64
16
read-write
n
0x0
0x0
C0TS
CAN0 module time stamp register
0x66
16
read-write
n
0x0
0x0
CANMSG00
CAN Controller Message 00
CANMSG00
0x0
0x0
0x10
registers
n
C0MCONF
CAN0 message configuration register
0x9
8
read-write
n
0x0
0x0
C0MCTRL
CAN0 message control register
0xE
16
read-write
n
0x0
0x0
C0MDB 23
CAN0 message data byte %s register
0x2
16
read-write
n
0x0
0x0
C0MDB 45
CAN0 message data byte %s register
0x4
16
read-write
n
0x0
0x0
C0MDB 67
CAN0 message data byte %s register
0x6
16
read-write
n
0x0
0x0
C0MDB0
CAN0 message data byte %s register
C0MDB01
0x0
8
read-write
n
0x0
0x0
C0MDB01
CAN0 message data byte %s register
0x0
16
read-write
n
0x0
0x0
C0MDB1
CAN0 message data byte %s register
C0MDB01
0x1
8
read-write
n
0x0
0x0
C0MDB2
CAN0 message data byte %s register
C0MDB23
0x2
8
read-write
n
0x0
0x0
C0MDB3
CAN0 message data byte %s register
C0MDB23
0x3
8
read-write
n
0x0
0x0
C0MDB4
CAN0 message data byte %s register
C0MDB45
0x4
8
read-write
n
0x0
0x0
C0MDB5
CAN0 message data byte %s register
C0MDB45
0x5
8
read-write
n
0x0
0x0
C0MDB6
CAN0 message data byte %s register
C0MDB67
0x6
8
read-write
n
0x0
0x0
C0MDB7
CAN0 message data byte %s register
C0MDB67
0x7
8
read-write
n
0x0
0x0
C0MDLC
CAN0 message data length register
0x8
8
read-write
n
0x0
0x0
C0MIDH
CAN0 message ID register
0xC
16
read-write
n
0x0
0x0
C0MIDL
CAN0 message ID register
0xA
16
read-write
n
0x0
0x0
CANMSG01
CAN Controller Message 01
CANMSG00
0x0
0x0
0x10
registers
n
C0MCONF
CAN0 message configuration register
0x9
8
read-write
n
0x0
0x0
C0MCTRL
CAN0 message control register
0xE
16
read-write
n
0x0
0x0
C0MDB 23
CAN0 message data byte %s register
0x2
16
read-write
n
0x0
0x0
C0MDB 45
CAN0 message data byte %s register
0x4
16
read-write
n
0x0
0x0
C0MDB 67
CAN0 message data byte %s register
0x6
16
read-write
n
0x0
0x0
C0MDB0
CAN0 message data byte %s register
C0MDB01
0x0
8
read-write
n
0x0
0x0
C0MDB01
CAN0 message data byte %s register
0x0
16
read-write
n
0x0
0x0
C0MDB1
CAN0 message data byte %s register
C0MDB01
0x1
8
read-write
n
0x0
0x0
C0MDB2
CAN0 message data byte %s register
C0MDB23
0x2
8
read-write
n
0x0
0x0
C0MDB3
CAN0 message data byte %s register
C0MDB23
0x3
8
read-write
n
0x0
0x0
C0MDB4
CAN0 message data byte %s register
C0MDB45
0x4
8
read-write
n
0x0
0x0
C0MDB5
CAN0 message data byte %s register
C0MDB45
0x5
8
read-write
n
0x0
0x0
C0MDB6
CAN0 message data byte %s register
C0MDB67
0x6
8
read-write
n
0x0
0x0
C0MDB7
CAN0 message data byte %s register
C0MDB67
0x7
8
read-write
n
0x0
0x0
C0MDLC
CAN0 message data length register
0x8
8
read-write
n
0x0
0x0
C0MIDH
CAN0 message ID register
0xC
16
read-write
n
0x0
0x0
C0MIDL
CAN0 message ID register
0xA
16
read-write
n
0x0
0x0
CANMSG02
CAN Controller Message 02
CANMSG00
0x0
0x0
0x10
registers
n
C0MCONF
CAN0 message configuration register
0x9
8
read-write
n
0x0
0x0
C0MCTRL
CAN0 message control register
0xE
16
read-write
n
0x0
0x0
C0MDB 23
CAN0 message data byte %s register
0x2
16
read-write
n
0x0
0x0
C0MDB 45
CAN0 message data byte %s register
0x4
16
read-write
n
0x0
0x0
C0MDB 67
CAN0 message data byte %s register
0x6
16
read-write
n
0x0
0x0
C0MDB0
CAN0 message data byte %s register
C0MDB01
0x0
8
read-write
n
0x0
0x0
C0MDB01
CAN0 message data byte %s register
0x0
16
read-write
n
0x0
0x0
C0MDB1
CAN0 message data byte %s register
C0MDB01
0x1
8
read-write
n
0x0
0x0
C0MDB2
CAN0 message data byte %s register
C0MDB23
0x2
8
read-write
n
0x0
0x0
C0MDB3
CAN0 message data byte %s register
C0MDB23
0x3
8
read-write
n
0x0
0x0
C0MDB4
CAN0 message data byte %s register
C0MDB45
0x4
8
read-write
n
0x0
0x0
C0MDB5
CAN0 message data byte %s register
C0MDB45
0x5
8
read-write
n
0x0
0x0
C0MDB6
CAN0 message data byte %s register
C0MDB67
0x6
8
read-write
n
0x0
0x0
C0MDB7
CAN0 message data byte %s register
C0MDB67
0x7
8
read-write
n
0x0
0x0
C0MDLC
CAN0 message data length register
0x8
8
read-write
n
0x0
0x0
C0MIDH
CAN0 message ID register
0xC
16
read-write
n
0x0
0x0
C0MIDL
CAN0 message ID register
0xA
16
read-write
n
0x0
0x0
CANMSG03
CAN Controller Message 03
CANMSG00
0x0
0x0
0x10
registers
n
C0MCONF
CAN0 message configuration register
0x9
8
read-write
n
0x0
0x0
C0MCTRL
CAN0 message control register
0xE
16
read-write
n
0x0
0x0
C0MDB 23
CAN0 message data byte %s register
0x2
16
read-write
n
0x0
0x0
C0MDB 45
CAN0 message data byte %s register
0x4
16
read-write
n
0x0
0x0
C0MDB 67
CAN0 message data byte %s register
0x6
16
read-write
n
0x0
0x0
C0MDB0
CAN0 message data byte %s register
C0MDB01
0x0
8
read-write
n
0x0
0x0
C0MDB01
CAN0 message data byte %s register
0x0
16
read-write
n
0x0
0x0
C0MDB1
CAN0 message data byte %s register
C0MDB01
0x1
8
read-write
n
0x0
0x0
C0MDB2
CAN0 message data byte %s register
C0MDB23
0x2
8
read-write
n
0x0
0x0
C0MDB3
CAN0 message data byte %s register
C0MDB23
0x3
8
read-write
n
0x0
0x0
C0MDB4
CAN0 message data byte %s register
C0MDB45
0x4
8
read-write
n
0x0
0x0
C0MDB5
CAN0 message data byte %s register
C0MDB45
0x5
8
read-write
n
0x0
0x0
C0MDB6
CAN0 message data byte %s register
C0MDB67
0x6
8
read-write
n
0x0
0x0
C0MDB7
CAN0 message data byte %s register
C0MDB67
0x7
8
read-write
n
0x0
0x0
C0MDLC
CAN0 message data length register
0x8
8
read-write
n
0x0
0x0
C0MIDH
CAN0 message ID register
0xC
16
read-write
n
0x0
0x0
C0MIDL
CAN0 message ID register
0xA
16
read-write
n
0x0
0x0
CANMSG04
CAN Controller Message 04
CANMSG00
0x0
0x0
0x10
registers
n
C0MCONF
CAN0 message configuration register
0x9
8
read-write
n
0x0
0x0
C0MCTRL
CAN0 message control register
0xE
16
read-write
n
0x0
0x0
C0MDB 23
CAN0 message data byte %s register
0x2
16
read-write
n
0x0
0x0
C0MDB 45
CAN0 message data byte %s register
0x4
16
read-write
n
0x0
0x0
C0MDB 67
CAN0 message data byte %s register
0x6
16
read-write
n
0x0
0x0
C0MDB0
CAN0 message data byte %s register
C0MDB01
0x0
8
read-write
n
0x0
0x0
C0MDB01
CAN0 message data byte %s register
0x0
16
read-write
n
0x0
0x0
C0MDB1
CAN0 message data byte %s register
C0MDB01
0x1
8
read-write
n
0x0
0x0
C0MDB2
CAN0 message data byte %s register
C0MDB23
0x2
8
read-write
n
0x0
0x0
C0MDB3
CAN0 message data byte %s register
C0MDB23
0x3
8
read-write
n
0x0
0x0
C0MDB4
CAN0 message data byte %s register
C0MDB45
0x4
8
read-write
n
0x0
0x0
C0MDB5
CAN0 message data byte %s register
C0MDB45
0x5
8
read-write
n
0x0
0x0
C0MDB6
CAN0 message data byte %s register
C0MDB67
0x6
8
read-write
n
0x0
0x0
C0MDB7
CAN0 message data byte %s register
C0MDB67
0x7
8
read-write
n
0x0
0x0
C0MDLC
CAN0 message data length register
0x8
8
read-write
n
0x0
0x0
C0MIDH
CAN0 message ID register
0xC
16
read-write
n
0x0
0x0
C0MIDL
CAN0 message ID register
0xA
16
read-write
n
0x0
0x0
CANMSG05
CAN Controller Message 05
CANMSG00
0x0
0x0
0x10
registers
n
C0MCONF
CAN0 message configuration register
0x9
8
read-write
n
0x0
0x0
C0MCTRL
CAN0 message control register
0xE
16
read-write
n
0x0
0x0
C0MDB 23
CAN0 message data byte %s register
0x2
16
read-write
n
0x0
0x0
C0MDB 45
CAN0 message data byte %s register
0x4
16
read-write
n
0x0
0x0
C0MDB 67
CAN0 message data byte %s register
0x6
16
read-write
n
0x0
0x0
C0MDB0
CAN0 message data byte %s register
C0MDB01
0x0
8
read-write
n
0x0
0x0
C0MDB01
CAN0 message data byte %s register
0x0
16
read-write
n
0x0
0x0
C0MDB1
CAN0 message data byte %s register
C0MDB01
0x1
8
read-write
n
0x0
0x0
C0MDB2
CAN0 message data byte %s register
C0MDB23
0x2
8
read-write
n
0x0
0x0
C0MDB3
CAN0 message data byte %s register
C0MDB23
0x3
8
read-write
n
0x0
0x0
C0MDB4
CAN0 message data byte %s register
C0MDB45
0x4
8
read-write
n
0x0
0x0
C0MDB5
CAN0 message data byte %s register
C0MDB45
0x5
8
read-write
n
0x0
0x0
C0MDB6
CAN0 message data byte %s register
C0MDB67
0x6
8
read-write
n
0x0
0x0
C0MDB7
CAN0 message data byte %s register
C0MDB67
0x7
8
read-write
n
0x0
0x0
C0MDLC
CAN0 message data length register
0x8
8
read-write
n
0x0
0x0
C0MIDH
CAN0 message ID register
0xC
16
read-write
n
0x0
0x0
C0MIDL
CAN0 message ID register
0xA
16
read-write
n
0x0
0x0
CANMSG06
CAN Controller Message 06
CANMSG00
0x0
0x0
0x10
registers
n
C0MCONF
CAN0 message configuration register
0x9
8
read-write
n
0x0
0x0
C0MCTRL
CAN0 message control register
0xE
16
read-write
n
0x0
0x0
C0MDB 23
CAN0 message data byte %s register
0x2
16
read-write
n
0x0
0x0
C0MDB 45
CAN0 message data byte %s register
0x4
16
read-write
n
0x0
0x0
C0MDB 67
CAN0 message data byte %s register
0x6
16
read-write
n
0x0
0x0
C0MDB0
CAN0 message data byte %s register
C0MDB01
0x0
8
read-write
n
0x0
0x0
C0MDB01
CAN0 message data byte %s register
0x0
16
read-write
n
0x0
0x0
C0MDB1
CAN0 message data byte %s register
C0MDB01
0x1
8
read-write
n
0x0
0x0
C0MDB2
CAN0 message data byte %s register
C0MDB23
0x2
8
read-write
n
0x0
0x0
C0MDB3
CAN0 message data byte %s register
C0MDB23
0x3
8
read-write
n
0x0
0x0
C0MDB4
CAN0 message data byte %s register
C0MDB45
0x4
8
read-write
n
0x0
0x0
C0MDB5
CAN0 message data byte %s register
C0MDB45
0x5
8
read-write
n
0x0
0x0
C0MDB6
CAN0 message data byte %s register
C0MDB67
0x6
8
read-write
n
0x0
0x0
C0MDB7
CAN0 message data byte %s register
C0MDB67
0x7
8
read-write
n
0x0
0x0
C0MDLC
CAN0 message data length register
0x8
8
read-write
n
0x0
0x0
C0MIDH
CAN0 message ID register
0xC
16
read-write
n
0x0
0x0
C0MIDL
CAN0 message ID register
0xA
16
read-write
n
0x0
0x0
CANMSG07
CAN Controller Message 07
CANMSG00
0x0
0x0
0x10
registers
n
C0MCONF
CAN0 message configuration register
0x9
8
read-write
n
0x0
0x0
C0MCTRL
CAN0 message control register
0xE
16
read-write
n
0x0
0x0
C0MDB 23
CAN0 message data byte %s register
0x2
16
read-write
n
0x0
0x0
C0MDB 45
CAN0 message data byte %s register
0x4
16
read-write
n
0x0
0x0
C0MDB 67
CAN0 message data byte %s register
0x6
16
read-write
n
0x0
0x0
C0MDB0
CAN0 message data byte %s register
C0MDB01
0x0
8
read-write
n
0x0
0x0
C0MDB01
CAN0 message data byte %s register
0x0
16
read-write
n
0x0
0x0
C0MDB1
CAN0 message data byte %s register
C0MDB01
0x1
8
read-write
n
0x0
0x0
C0MDB2
CAN0 message data byte %s register
C0MDB23
0x2
8
read-write
n
0x0
0x0
C0MDB3
CAN0 message data byte %s register
C0MDB23
0x3
8
read-write
n
0x0
0x0
C0MDB4
CAN0 message data byte %s register
C0MDB45
0x4
8
read-write
n
0x0
0x0
C0MDB5
CAN0 message data byte %s register
C0MDB45
0x5
8
read-write
n
0x0
0x0
C0MDB6
CAN0 message data byte %s register
C0MDB67
0x6
8
read-write
n
0x0
0x0
C0MDB7
CAN0 message data byte %s register
C0MDB67
0x7
8
read-write
n
0x0
0x0
C0MDLC
CAN0 message data length register
0x8
8
read-write
n
0x0
0x0
C0MIDH
CAN0 message ID register
0xC
16
read-write
n
0x0
0x0
C0MIDL
CAN0 message ID register
0xA
16
read-write
n
0x0
0x0
CANMSG08
CAN Controller Message 08
CANMSG00
0x0
0x0
0x10
registers
n
C0MCONF
CAN0 message configuration register
0x9
8
read-write
n
0x0
0x0
C0MCTRL
CAN0 message control register
0xE
16
read-write
n
0x0
0x0
C0MDB 23
CAN0 message data byte %s register
0x2
16
read-write
n
0x0
0x0
C0MDB 45
CAN0 message data byte %s register
0x4
16
read-write
n
0x0
0x0
C0MDB 67
CAN0 message data byte %s register
0x6
16
read-write
n
0x0
0x0
C0MDB0
CAN0 message data byte %s register
C0MDB01
0x0
8
read-write
n
0x0
0x0
C0MDB01
CAN0 message data byte %s register
0x0
16
read-write
n
0x0
0x0
C0MDB1
CAN0 message data byte %s register
C0MDB01
0x1
8
read-write
n
0x0
0x0
C0MDB2
CAN0 message data byte %s register
C0MDB23
0x2
8
read-write
n
0x0
0x0
C0MDB3
CAN0 message data byte %s register
C0MDB23
0x3
8
read-write
n
0x0
0x0
C0MDB4
CAN0 message data byte %s register
C0MDB45
0x4
8
read-write
n
0x0
0x0
C0MDB5
CAN0 message data byte %s register
C0MDB45
0x5
8
read-write
n
0x0
0x0
C0MDB6
CAN0 message data byte %s register
C0MDB67
0x6
8
read-write
n
0x0
0x0
C0MDB7
CAN0 message data byte %s register
C0MDB67
0x7
8
read-write
n
0x0
0x0
C0MDLC
CAN0 message data length register
0x8
8
read-write
n
0x0
0x0
C0MIDH
CAN0 message ID register
0xC
16
read-write
n
0x0
0x0
C0MIDL
CAN0 message ID register
0xA
16
read-write
n
0x0
0x0
CANMSG09
CAN Controller Message 09
CANMSG00
0x0
0x0
0x10
registers
n
C0MCONF
CAN0 message configuration register
0x9
8
read-write
n
0x0
0x0
C0MCTRL
CAN0 message control register
0xE
16
read-write
n
0x0
0x0
C0MDB 23
CAN0 message data byte %s register
0x2
16
read-write
n
0x0
0x0
C0MDB 45
CAN0 message data byte %s register
0x4
16
read-write
n
0x0
0x0
C0MDB 67
CAN0 message data byte %s register
0x6
16
read-write
n
0x0
0x0
C0MDB0
CAN0 message data byte %s register
C0MDB01
0x0
8
read-write
n
0x0
0x0
C0MDB01
CAN0 message data byte %s register
0x0
16
read-write
n
0x0
0x0
C0MDB1
CAN0 message data byte %s register
C0MDB01
0x1
8
read-write
n
0x0
0x0
C0MDB2
CAN0 message data byte %s register
C0MDB23
0x2
8
read-write
n
0x0
0x0
C0MDB3
CAN0 message data byte %s register
C0MDB23
0x3
8
read-write
n
0x0
0x0
C0MDB4
CAN0 message data byte %s register
C0MDB45
0x4
8
read-write
n
0x0
0x0
C0MDB5
CAN0 message data byte %s register
C0MDB45
0x5
8
read-write
n
0x0
0x0
C0MDB6
CAN0 message data byte %s register
C0MDB67
0x6
8
read-write
n
0x0
0x0
C0MDB7
CAN0 message data byte %s register
C0MDB67
0x7
8
read-write
n
0x0
0x0
C0MDLC
CAN0 message data length register
0x8
8
read-write
n
0x0
0x0
C0MIDH
CAN0 message ID register
0xC
16
read-write
n
0x0
0x0
C0MIDL
CAN0 message ID register
0xA
16
read-write
n
0x0
0x0
CANMSG10
CAN Controller Message 10
CANMSG00
0x0
0x0
0x10
registers
n
C0MCONF
CAN0 message configuration register
0x9
8
read-write
n
0x0
0x0
C0MCTRL
CAN0 message control register
0xE
16
read-write
n
0x0
0x0
C0MDB 23
CAN0 message data byte %s register
0x2
16
read-write
n
0x0
0x0
C0MDB 45
CAN0 message data byte %s register
0x4
16
read-write
n
0x0
0x0
C0MDB 67
CAN0 message data byte %s register
0x6
16
read-write
n
0x0
0x0
C0MDB0
CAN0 message data byte %s register
C0MDB01
0x0
8
read-write
n
0x0
0x0
C0MDB01
CAN0 message data byte %s register
0x0
16
read-write
n
0x0
0x0
C0MDB1
CAN0 message data byte %s register
C0MDB01
0x1
8
read-write
n
0x0
0x0
C0MDB2
CAN0 message data byte %s register
C0MDB23
0x2
8
read-write
n
0x0
0x0
C0MDB3
CAN0 message data byte %s register
C0MDB23
0x3
8
read-write
n
0x0
0x0
C0MDB4
CAN0 message data byte %s register
C0MDB45
0x4
8
read-write
n
0x0
0x0
C0MDB5
CAN0 message data byte %s register
C0MDB45
0x5
8
read-write
n
0x0
0x0
C0MDB6
CAN0 message data byte %s register
C0MDB67
0x6
8
read-write
n
0x0
0x0
C0MDB7
CAN0 message data byte %s register
C0MDB67
0x7
8
read-write
n
0x0
0x0
C0MDLC
CAN0 message data length register
0x8
8
read-write
n
0x0
0x0
C0MIDH
CAN0 message ID register
0xC
16
read-write
n
0x0
0x0
C0MIDL
CAN0 message ID register
0xA
16
read-write
n
0x0
0x0
CANMSG11
CAN Controller Message 11
CANMSG00
0x0
0x0
0x10
registers
n
C0MCONF
CAN0 message configuration register
0x9
8
read-write
n
0x0
0x0
C0MCTRL
CAN0 message control register
0xE
16
read-write
n
0x0
0x0
C0MDB 23
CAN0 message data byte %s register
0x2
16
read-write
n
0x0
0x0
C0MDB 45
CAN0 message data byte %s register
0x4
16
read-write
n
0x0
0x0
C0MDB 67
CAN0 message data byte %s register
0x6
16
read-write
n
0x0
0x0
C0MDB0
CAN0 message data byte %s register
C0MDB01
0x0
8
read-write
n
0x0
0x0
C0MDB01
CAN0 message data byte %s register
0x0
16
read-write
n
0x0
0x0
C0MDB1
CAN0 message data byte %s register
C0MDB01
0x1
8
read-write
n
0x0
0x0
C0MDB2
CAN0 message data byte %s register
C0MDB23
0x2
8
read-write
n
0x0
0x0
C0MDB3
CAN0 message data byte %s register
C0MDB23
0x3
8
read-write
n
0x0
0x0
C0MDB4
CAN0 message data byte %s register
C0MDB45
0x4
8
read-write
n
0x0
0x0
C0MDB5
CAN0 message data byte %s register
C0MDB45
0x5
8
read-write
n
0x0
0x0
C0MDB6
CAN0 message data byte %s register
C0MDB67
0x6
8
read-write
n
0x0
0x0
C0MDB7
CAN0 message data byte %s register
C0MDB67
0x7
8
read-write
n
0x0
0x0
C0MDLC
CAN0 message data length register
0x8
8
read-write
n
0x0
0x0
C0MIDH
CAN0 message ID register
0xC
16
read-write
n
0x0
0x0
C0MIDL
CAN0 message ID register
0xA
16
read-write
n
0x0
0x0
CANMSG12
CAN Controller Message 12
CANMSG00
0x0
0x0
0x10
registers
n
C0MCONF
CAN0 message configuration register
0x9
8
read-write
n
0x0
0x0
C0MCTRL
CAN0 message control register
0xE
16
read-write
n
0x0
0x0
C0MDB 23
CAN0 message data byte %s register
0x2
16
read-write
n
0x0
0x0
C0MDB 45
CAN0 message data byte %s register
0x4
16
read-write
n
0x0
0x0
C0MDB 67
CAN0 message data byte %s register
0x6
16
read-write
n
0x0
0x0
C0MDB0
CAN0 message data byte %s register
C0MDB01
0x0
8
read-write
n
0x0
0x0
C0MDB01
CAN0 message data byte %s register
0x0
16
read-write
n
0x0
0x0
C0MDB1
CAN0 message data byte %s register
C0MDB01
0x1
8
read-write
n
0x0
0x0
C0MDB2
CAN0 message data byte %s register
C0MDB23
0x2
8
read-write
n
0x0
0x0
C0MDB3
CAN0 message data byte %s register
C0MDB23
0x3
8
read-write
n
0x0
0x0
C0MDB4
CAN0 message data byte %s register
C0MDB45
0x4
8
read-write
n
0x0
0x0
C0MDB5
CAN0 message data byte %s register
C0MDB45
0x5
8
read-write
n
0x0
0x0
C0MDB6
CAN0 message data byte %s register
C0MDB67
0x6
8
read-write
n
0x0
0x0
C0MDB7
CAN0 message data byte %s register
C0MDB67
0x7
8
read-write
n
0x0
0x0
C0MDLC
CAN0 message data length register
0x8
8
read-write
n
0x0
0x0
C0MIDH
CAN0 message ID register
0xC
16
read-write
n
0x0
0x0
C0MIDL
CAN0 message ID register
0xA
16
read-write
n
0x0
0x0
CANMSG13
CAN Controller Message 13
CANMSG00
0x0
0x0
0x10
registers
n
C0MCONF
CAN0 message configuration register
0x9
8
read-write
n
0x0
0x0
C0MCTRL
CAN0 message control register
0xE
16
read-write
n
0x0
0x0
C0MDB 23
CAN0 message data byte %s register
0x2
16
read-write
n
0x0
0x0
C0MDB 45
CAN0 message data byte %s register
0x4
16
read-write
n
0x0
0x0
C0MDB 67
CAN0 message data byte %s register
0x6
16
read-write
n
0x0
0x0
C0MDB0
CAN0 message data byte %s register
C0MDB01
0x0
8
read-write
n
0x0
0x0
C0MDB01
CAN0 message data byte %s register
0x0
16
read-write
n
0x0
0x0
C0MDB1
CAN0 message data byte %s register
C0MDB01
0x1
8
read-write
n
0x0
0x0
C0MDB2
CAN0 message data byte %s register
C0MDB23
0x2
8
read-write
n
0x0
0x0
C0MDB3
CAN0 message data byte %s register
C0MDB23
0x3
8
read-write
n
0x0
0x0
C0MDB4
CAN0 message data byte %s register
C0MDB45
0x4
8
read-write
n
0x0
0x0
C0MDB5
CAN0 message data byte %s register
C0MDB45
0x5
8
read-write
n
0x0
0x0
C0MDB6
CAN0 message data byte %s register
C0MDB67
0x6
8
read-write
n
0x0
0x0
C0MDB7
CAN0 message data byte %s register
C0MDB67
0x7
8
read-write
n
0x0
0x0
C0MDLC
CAN0 message data length register
0x8
8
read-write
n
0x0
0x0
C0MIDH
CAN0 message ID register
0xC
16
read-write
n
0x0
0x0
C0MIDL
CAN0 message ID register
0xA
16
read-write
n
0x0
0x0
CANMSG14
CAN Controller Message 14
CANMSG00
0x0
0x0
0x10
registers
n
C0MCONF
CAN0 message configuration register
0x9
8
read-write
n
0x0
0x0
C0MCTRL
CAN0 message control register
0xE
16
read-write
n
0x0
0x0
C0MDB 23
CAN0 message data byte %s register
0x2
16
read-write
n
0x0
0x0
C0MDB 45
CAN0 message data byte %s register
0x4
16
read-write
n
0x0
0x0
C0MDB 67
CAN0 message data byte %s register
0x6
16
read-write
n
0x0
0x0
C0MDB0
CAN0 message data byte %s register
C0MDB01
0x0
8
read-write
n
0x0
0x0
C0MDB01
CAN0 message data byte %s register
0x0
16
read-write
n
0x0
0x0
C0MDB1
CAN0 message data byte %s register
C0MDB01
0x1
8
read-write
n
0x0
0x0
C0MDB2
CAN0 message data byte %s register
C0MDB23
0x2
8
read-write
n
0x0
0x0
C0MDB3
CAN0 message data byte %s register
C0MDB23
0x3
8
read-write
n
0x0
0x0
C0MDB4
CAN0 message data byte %s register
C0MDB45
0x4
8
read-write
n
0x0
0x0
C0MDB5
CAN0 message data byte %s register
C0MDB45
0x5
8
read-write
n
0x0
0x0
C0MDB6
CAN0 message data byte %s register
C0MDB67
0x6
8
read-write
n
0x0
0x0
C0MDB7
CAN0 message data byte %s register
C0MDB67
0x7
8
read-write
n
0x0
0x0
C0MDLC
CAN0 message data length register
0x8
8
read-write
n
0x0
0x0
C0MIDH
CAN0 message ID register
0xC
16
read-write
n
0x0
0x0
C0MIDL
CAN0 message ID register
0xA
16
read-write
n
0x0
0x0
CANMSG15
CAN Controller Message 15
CANMSG00
0x0
0x0
0x10
registers
n
C0MCONF
CAN0 message configuration register
0x9
8
read-write
n
0x0
0x0
C0MCTRL
CAN0 message control register
0xE
16
read-write
n
0x0
0x0
C0MDB 23
CAN0 message data byte %s register
0x2
16
read-write
n
0x0
0x0
C0MDB 45
CAN0 message data byte %s register
0x4
16
read-write
n
0x0
0x0
C0MDB 67
CAN0 message data byte %s register
0x6
16
read-write
n
0x0
0x0
C0MDB0
CAN0 message data byte %s register
C0MDB01
0x0
8
read-write
n
0x0
0x0
C0MDB01
CAN0 message data byte %s register
0x0
16
read-write
n
0x0
0x0
C0MDB1
CAN0 message data byte %s register
C0MDB01
0x1
8
read-write
n
0x0
0x0
C0MDB2
CAN0 message data byte %s register
C0MDB23
0x2
8
read-write
n
0x0
0x0
C0MDB3
CAN0 message data byte %s register
C0MDB23
0x3
8
read-write
n
0x0
0x0
C0MDB4
CAN0 message data byte %s register
C0MDB45
0x4
8
read-write
n
0x0
0x0
C0MDB5
CAN0 message data byte %s register
C0MDB45
0x5
8
read-write
n
0x0
0x0
C0MDB6
CAN0 message data byte %s register
C0MDB67
0x6
8
read-write
n
0x0
0x0
C0MDB7
CAN0 message data byte %s register
C0MDB67
0x7
8
read-write
n
0x0
0x0
C0MDLC
CAN0 message data length register
0x8
8
read-write
n
0x0
0x0
C0MIDH
CAN0 message ID register
0xC
16
read-write
n
0x0
0x0
C0MIDL
CAN0 message ID register
0xA
16
read-write
n
0x0
0x0
CGC
Clock Generate Control
CLK
0x0
0x0
0x2000
registers
n
LVI
Low Voltage detection interrupt
0
CKC
System clock control register
0x4
8
read-write
n
0x0
0x0
CLS
Status of CPU/peripheral hardware clock (fCLK)
7
8
read-only
fMAIN
Main system clock (fMAIN)
0
fSUB
Subsystem clock (fSUB)
1
CSS
Selection of CPU/peripheral hardware clock (fCLK)
6
7
read-write
fMAIN
Main system clock (fMAIN)
0
fSUB
Subsystem clock (fSUB)
1
MCM0
Main system clock (fMAIN) operation control
4
5
read-write
fIH
Select the high-speed on-chip oscillator clock (fIH) as the main system clock (fMAIN)
0
fMX
Select the high-speed system clock (fMX) as the main system clock (fMAIN)
1
MCS
Status of Main system clock (fMAIN)
5
6
read-only
fIH
High-speed on-chip oscillator clock (fIH)
0
fMX
High-speed system clock (fMX)
1
CMC
Clock operaton Mode Control Register
0x0
8
read-write
n
0x0
0x0
AMPH
Control of X1 clock oscillation frequency
0
1
read-write
AMPHS
Control of XT1 clock oscillation frequency
1
3
read-write
EXCLK
External Clock input mode
7
8
read-write
EXCLKS
External Clock input mode
5
6
read-write
OSCSEL
Main OSC Select
6
7
read-write
OSCSELS
Sub OSC Select
4
5
read-write
CSC
Clock operation Status Register
0x1
8
read-write
n
0x0
0x0
HIOSTOP
High-speed on-chip oscillator clock operation control
0
1
read-write
START
High-speed on-chip oscillator operating
0
STOP
High-speed on-chip oscillator stopped
1
MSTOP
High-speed system clock operation control
7
8
read-write
START
X1 oscillator operating or External clock from EXCLK pin is valid
0
STOP
X1 oscillator stop or External clock from EXCLK pin is invalid
1
XTSTOP
Subsystem clock operation control
6
7
read-write
START
XT1 oscillator operating or External clock from EXCLKS pin is valid
0
STOP
XT1 oscillator stop or External clock from EXCLKS pin is invalid
1
HIOTRM
High-speed on-chip oscillator trimming register
0x1800
8
read-write
n
0x0
0x0
HOCODIV
High-speed on-chip oscillator frequency select register
0x1820
8
read-write
n
0x0
0x0
OSMC
Subsystem clock supply mode control register
0x23
8
read-write
n
0x0
0x0
RTCLPC
Setting in DEEPSLEEP mode or SLEEP mode while subsystem clock is selected as CPU clock
7
8
read-write
Enable
Enables supply of subsystem clock to peripheral function
0
Disable
Stops supply of subsystem clock to peripheral functions other than real-time clock and 15-bit interval timer.
1
WUTMMCK0
Selection of operation clock for real-time clock, 15-bit interval timer, and timer A
4
5
read-write
fSUB
The subsystem clock is selected as the operation clock for the real-time clock and the 15-bit interval timer. The low-speed on-chip oscillator cannot be selected as the count source for timer A.
0
fIL
The low-speed on-chip oscillator clock is selected as the operation clock for the real-time clock and the 15-bit interval timer. Either the low-speed on-chip oscillator or the subsystem clock can be selected as the count source for timer A.
1
OSTC
Oscillation stabilization time counter status
0x2
8
read-only
n
0x0
0x0
OSTS
Oscillation stabilization time select register
0x3
8
read-write
n
0x0
0x0
PER0
Peripheral enable register 0
0x20
8
read-write
n
0x0
0x0
ADCEN
Control of the ADC input clock
5
6
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
CAN0EN
Control of the CAN input clock
1
2
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
IICA0EN
Control of the IICA0 input clock
4
5
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
IRDAEN
Control of the IRDA input clock
6
7
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
RTCEN
Control of the RTC input clock
7
8
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
SCI0EN
Control of the SCI0 input clock
2
3
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
SCI1EN
Control of the SCI1 input clock
3
4
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
TM40EN
Control of the TM4 input clock
0
1
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
PER1
Peripheral enable register 1
0x41A
8
read-write
n
0x0
0x0
DACEN
Control of the DAC input clock
7
8
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
DMAEN
Control of the DMA input clock
3
4
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
PGACMPEN
Control of the PGACMP input clock
5
6
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
PWMOPEN
Control of the PWMOP input clock
2
3
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
TMAEN
Control of the TMA input clock
0
1
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
TMBEN
Control of the TMB input clock
6
7
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
TMCEN
Control of the TMC input clock
1
2
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
TMMEN
Control of the TMM input clock
4
5
Disabled
Disables input clock supply
0
Enable
Enables input clock supply
1
CMP
Comparator
CMP
0x0
0x0
0x100
registers
n
CMP0
CMP0 interrupt request
24
CMP1
CMP1 interrupt request
25
C0RVM
Comparator internal reference voltage select register 0
0x4
-1
read-write
n
0x0
0x0
C1RVM
Comparator internal reference voltage select register 1
0x5
-1
read-write
n
0x0
0x0
CMPSEL0
Comparator 0 input signal selection control register
0xA
-1
read-write
n
0x0
0x0
C0REFS
Selection of the input signal on the negative side of Comparator 0
0
2
CMP0SEL
Selection of the input signal on the positive side of Comparator 0
7
8
CMPSEL1
Comparator 1 input signal selection control register
0xB
-1
read-write
n
0x0
0x0
C1REFS
Selection of the input signal on the negative side of Comparator 1
0
3
CMP1SEL
Selection of the input signal on the positive side of Comparator 1
6
8
COMPFIR
Comparator filter control register
0x1
-1
read-write
n
0x0
0x0
C0EDG
Comparator 0 edge detection selection
3
4
C0EPO
Comparator 0 edge polarity switching
2
3
C0FCK
Comparator 0 filter selection
0
2
C1EDG
Comparator 1 edge detection selection
7
8
C1EPO
Comparator 1 edge polarity switching
6
7
C1FCK
Comparator 1 filter selection
4
6
COMPMDR
Comparator mode setting register
0x0
-1
read-write
n
0x0
0x0
C0ENB
Comparator 0 operation enable
0
1
C0MON
Comparator 0 monitor flag
3
4
C1ENB
Comparator 1 operation enable
4
5
C1MON
Comparator 1 monitor flag
7
8
COMPOCR
Comparator output control register
0x2
-1
read-write
n
0x0
0x0
C0IE
Comparator 0 interrupt request enable
0
1
C0OE
VOUT0 pin output enable
1
2
C0OP
VOUT0 output polarity selection
2
3
C1IE
Comparator 1 interrupt request enable
4
5
C1OE
VOUT1 pin output enable
5
6
C1OP
VOUT1 output polarity selection
6
7
C1OTWMD
TIMER WINDOW output mode control bit of comparator 1
7
8
CVRCTL
Comparator internal reference voltage control register
0x3
-1
read-write
n
0x0
0x0
CVRE0
Control bit for internal reference voltage 0
1
2
CVRE1
Control bit for internal reference voltage 1
5
6
CVRVS0
Power supply selection bit for internal reference voltage
0
1
CVRVS1
Ground selection bit for internal reference voltage
4
5
CRC
General Purpose CRC
CRC
0x0
0x0
0x100
registers
n
CRCD
CRC data register
0xA
16
read-write
n
0x0
0x0
CRCIN
CRC input register
0xBC
8
read-write
n
0x0
0x0
DAC
D/A Converter
DAC
0x0
0x0
0x100
registers
n
DACS0
D/A conversion value setting register 0
0x34
-1
read-write
n
0x0
0x0
DACS1
D/A conversion value setting register 1
0x35
-1
read-write
n
0x0
0x0
DAM
D/A conversion mode register
0x36
-1
read-write
n
0x0
0x0
DACE0
D/A converter operation control
4
5
DACE1
D/A converter operation control
5
6
DAMD0
D/A converter operation mode selection
0
1
DAMD1
D/A converter operation mode selection
1
2
DBG
DBG Controller
DBG
0x0
0x0
0x100
registers
n
DBGSTOPCR
Debug Stop Control register
0x4
-1
read-write
n
0x0
0x0
FRZEN0
Stop Timer family macros when cpu halted
0
1
FRZEN1
Stop Communation family macros when cpu halted
1
2
RESMSK
Mask internal reset in debug mode
2
3
RPERMSK
Mask RAM parity error in debug mode
16
17
SWDIS
SWD Disable
24
25
DBGSTR
Debug status register
0x0
-1
read-only
n
0x0
0x0
CDBGPWRUPACK
DBG Power Up Acknowledgement
29
30
CDBGPWRUPREQ
DBG Power Up Request
28
29
DIV
Hardware divider
DIV
0x0
0x0
0x100
registers
n
DIVIDEND
Dividend register
0x0
-1
read-write
n
0x0
0x0
DIVISOR
Divisor register
0x4
-1
read-write
n
0x0
0x0
QUOTIENT
Quotient register
0x8
-1
read-only
n
0x0
0x0
REMAINDER
Remainder register
0xC
-1
read-only
n
0x0
0x0
STATUS
Status register
0x10
-1
read-only
n
0x0
0x0
BUSY
divider busy flag
8
9
read-only
DIVBYZERO
divider zero flag
9
10
read-only
DMA
Enhanced DMA Controller
DMA
0x0
0x0
0x100
registers
n
DMABAR
DMA base address register
0x8
32
read-write
n
0x0
0x0
DMAEN0
DMA activation enable register %s
0x0
8
read-write
n
0x0
0x0
DMAEN1
DMA activation enable register %s
0x1
8
read-write
n
0x0
0x0
DMAEN2
DMA activation enable register %s
0x2
8
read-write
n
0x0
0x0
DMAEN3
DMA activation enable register %s
0x3
8
read-write
n
0x0
0x0
DMAEN4
DMA activation enable register %s
0x4
8
read-write
n
0x0
0x0
DMAIF0
DMA Trigger enable register %s
0x10
8
read-write
n
0x0
0x0
DMAIF1
DMA Trigger enable register %s
0x11
8
read-write
n
0x0
0x0
DMAIF2
DMA Trigger enable register %s
0x12
8
read-write
n
0x0
0x0
DMAIF3
DMA Trigger enable register %s
0x13
8
read-write
n
0x0
0x0
DMAIF4
DMA Trigger enable register %s
0x14
8
read-write
n
0x0
0x0
IFPRCR
DMA Trigger Protect register
0xC
32
read-write
n
0x0
0x0
DMAVEC
DMA Vector and Control Data Area
DMAVEC
0x0
0x0
0x2C0
registers
n
DMACR
DMA Control register
0x0
16
read-write
n
0x0
0x0
CHNE
Enabling/disabling chain transfers
4
5
read-write
disable
Chain transfers disabled
0
enable
Chain transfers enabled
1
DAMOD
Destination address control
3
4
read-write
Fixed
Fixed
0
Incremented
Incremented
1
MODE
Transfer mode selection
0
1
read-write
Normal
Normal mode
0
Repeat
Repeat mode
1
RPTINT
Enabling/disabling repeat mode interrupts
5
6
read-write
disable
Interrupt generation disabled
0
enable
Interrupt generation enabled
1
RPTSEL
Repeat area selection
1
2
read-write
destination
Transfer destination is the repeat area
0
source
Transfer source is the repeat area
1
SAMOD
Source address control
2
3
read-write
Fixed
Fixed
0
Incremented
Incremented
1
SZ
Transfer Data size selection
6
8
read-write
BYTE
8 bits
0
HALF
16 bits
1
WORD
32 bits
2
DMACT
DMA Transfer Count register
0x4
16
read-write
n
0x0
0x0
DMBLS
DMA Block Size register
0x2
16
read-write
n
0x0
0x0
DMDAR
DMA Destination Address register
0xC
32
read-write
n
0x0
0x0
DMRLD
DMA Transfer Count Reload register
0x6
16
read-write
n
0x0
0x0
DMSAR
DMA Source Address register
0x8
32
read-write
n
0x0
0x0
VEC0
DMA vector area
0x0
8
read-write
n
0x0
0x0
VEC1
DMA vector area
0x1
8
read-write
n
0x0
0x0
VEC10
DMA vector area
0xA
8
read-write
n
0x0
0x0
VEC11
DMA vector area
0xB
8
read-write
n
0x0
0x0
VEC12
DMA vector area
0xC
8
read-write
n
0x0
0x0
VEC13
DMA vector area
0xD
8
read-write
n
0x0
0x0
VEC14
DMA vector area
0xE
8
read-write
n
0x0
0x0
VEC15
DMA vector area
0xF
8
read-write
n
0x0
0x0
VEC16
DMA vector area
0x10
8
read-write
n
0x0
0x0
VEC17
DMA vector area
0x11
8
read-write
n
0x0
0x0
VEC18
DMA vector area
0x12
8
read-write
n
0x0
0x0
VEC19
DMA vector area
0x13
8
read-write
n
0x0
0x0
VEC2
DMA vector area
0x2
8
read-write
n
0x0
0x0
VEC20
DMA vector area
0x14
8
read-write
n
0x0
0x0
VEC21
DMA vector area
0x15
8
read-write
n
0x0
0x0
VEC22
DMA vector area
0x16
8
read-write
n
0x0
0x0
VEC23
DMA vector area
0x17
8
read-write
n
0x0
0x0
VEC24
DMA vector area
0x18
8
read-write
n
0x0
0x0
VEC25
DMA vector area
0x19
8
read-write
n
0x0
0x0
VEC26
DMA vector area
0x1A
8
read-write
n
0x0
0x0
VEC27
DMA vector area
0x1B
8
read-write
n
0x0
0x0
VEC28
DMA vector area
0x1C
8
read-write
n
0x0
0x0
VEC29
DMA vector area
0x1D
8
read-write
n
0x0
0x0
VEC3
DMA vector area
0x3
8
read-write
n
0x0
0x0
VEC30
DMA vector area
0x1E
8
read-write
n
0x0
0x0
VEC31
DMA vector area
0x1F
8
read-write
n
0x0
0x0
VEC32
DMA vector area
0x20
8
read-write
n
0x0
0x0
VEC33
DMA vector area
0x21
8
read-write
n
0x0
0x0
VEC34
DMA vector area
0x22
8
read-write
n
0x0
0x0
VEC35
DMA vector area
0x23
8
read-write
n
0x0
0x0
VEC36
DMA vector area
0x24
8
read-write
n
0x0
0x0
VEC37
DMA vector area
0x25
8
read-write
n
0x0
0x0
VEC38
DMA vector area
0x26
8
read-write
n
0x0
0x0
VEC39
DMA vector area
0x27
8
read-write
n
0x0
0x0
VEC4
DMA vector area
0x4
8
read-write
n
0x0
0x0
VEC40
DMA vector area
0x28
8
read-write
n
0x0
0x0
VEC41
DMA vector area
0x29
8
read-write
n
0x0
0x0
VEC42
DMA vector area
0x2A
8
read-write
n
0x0
0x0
VEC43
DMA vector area
0x2B
8
read-write
n
0x0
0x0
VEC44
DMA vector area
0x2C
8
read-write
n
0x0
0x0
VEC45
DMA vector area
0x2D
8
read-write
n
0x0
0x0
VEC46
DMA vector area
0x2E
8
read-write
n
0x0
0x0
VEC47
DMA vector area
0x2F
8
read-write
n
0x0
0x0
VEC48
DMA vector area
0x30
8
read-write
n
0x0
0x0
VEC49
DMA vector area
0x31
8
read-write
n
0x0
0x0
VEC5
DMA vector area
0x5
8
read-write
n
0x0
0x0
VEC50
DMA vector area
0x32
8
read-write
n
0x0
0x0
VEC51
DMA vector area
0x33
8
read-write
n
0x0
0x0
VEC52
DMA vector area
0x34
8
read-write
n
0x0
0x0
VEC53
DMA vector area
0x35
8
read-write
n
0x0
0x0
VEC54
DMA vector area
0x36
8
read-write
n
0x0
0x0
VEC55
DMA vector area
0x37
8
read-write
n
0x0
0x0
VEC56
DMA vector area
0x38
8
read-write
n
0x0
0x0
VEC57
DMA vector area
0x39
8
read-write
n
0x0
0x0
VEC58
DMA vector area
0x3A
8
read-write
n
0x0
0x0
VEC59
DMA vector area
0x3B
8
read-write
n
0x0
0x0
VEC6
DMA vector area
0x6
8
read-write
n
0x0
0x0
VEC60
DMA vector area
0x3C
8
read-write
n
0x0
0x0
VEC61
DMA vector area
0x3D
8
read-write
n
0x0
0x0
VEC62
DMA vector area
0x3E
8
read-write
n
0x0
0x0
VEC63
DMA vector area
0x3F
8
read-write
n
0x0
0x0
VEC7
DMA vector area
0x7
8
read-write
n
0x0
0x0
VEC8
DMA vector area
0x8
8
read-write
n
0x0
0x0
VEC9
DMA vector area
0x9
8
read-write
n
0x0
0x0
ELC
Event Link Controller
ELC
0x0
0x0
0x100
registers
n
ELSELR00
Event output destination select register 00
0x0
-1
read-write
n
0x0
0x0
ELSELR01
Event output destination select register 01
0x1
-1
read-write
n
0x0
0x0
ELSELR02
Event output destination select register 02
0x2
-1
read-write
n
0x0
0x0
ELSELR03
Event output destination select register 03
0x3
-1
read-write
n
0x0
0x0
ELSELR04
Event output destination select register 04
0x4
-1
read-write
n
0x0
0x0
ELSELR05
Event output destination select register 05
0x5
-1
read-write
n
0x0
0x0
ELSELR06
Event output destination select register 06
0x6
-1
read-write
n
0x0
0x0
ELSELR07
Event output destination select register 07
0x7
-1
read-write
n
0x0
0x0
ELSELR08
Event output destination select register 08
0x8
-1
read-write
n
0x0
0x0
ELSELR09
Event output destination select register 09
0x9
-1
read-write
n
0x0
0x0
ELSELR10
Event output destination select register 10
0xA
-1
read-write
n
0x0
0x0
ELSELR11
Event output destination select register 11
0xB
-1
read-write
n
0x0
0x0
ELSELR12
Event output destination select register 12
0xC
-1
read-write
n
0x0
0x0
ELSELR13
Event output destination select register 13
0xD
-1
read-write
n
0x0
0x0
ELSELR14
Event output destination select register 14
0xE
-1
read-write
n
0x0
0x0
ELSELR15
Event output destination select register 15
0xF
-1
read-write
n
0x0
0x0
ELSELR16
Event output destination select register 16
0x10
-1
read-write
n
0x0
0x0
ELSELR17
Event output destination select register 17
0x11
-1
read-write
n
0x0
0x0
ELSELR18
Event output destination select register 18
0x12
-1
read-write
n
0x0
0x0
ELSELR19
Event output destination select register 19
0x13
-1
read-write
n
0x0
0x0
ELSELR20
Event output destination select register 20
0x14
-1
read-write
n
0x0
0x0
ELSELR21
Event output destination select register 21
0x15
-1
read-write
n
0x0
0x0
FMC
Flash Memory Controller
FMC
0x0
0x0
0x400
registers
n
FMC
Flash erase or write finish
31
FLCERCNT
Flash chip erase control register
0x10
-1
read-write
n
0x0
0x0
FLERMD
Flash erase mode register
0xC
-1
read-write
n
0x0
0x0
FLOPMD1
Flash operation mode register 1
0x4
-1
read-write
n
0x0
0x0
FLOPMD2
Flash operation mode register 2
0x8
-1
read-write
n
0x0
0x0
FLPROCNT
Flash program (write) control register
0x1C
-1
read-write
n
0x0
0x0
FLPROT
Flash protect control register
0x20
-1
read-write
n
0x0
0x0
FLSERCNT
Flash sector erase control register
0x14
-1
read-write
n
0x0
0x0
FLSTS
Flash status register
0x0
-1
read-write
n
0x0
0x0
EVF
Flash hardware verification error flag
2
3
OVF
Flash erase or write operaiton finish
0
1
IICA
Serial Interface I2C with multimaster and wakeup supported
IICA
0x0
0x0
0x200
registers
n
IICA
IICA interrupt request
16
IICA0
IICA shift register 0
0x120
-1
read-write
n
0x0
0x0
IICCTL00
IICA control register 0
0x0
-1
read-write
n
0x0
0x0
ACKE
Acknowledgment control
2
3
IICE
I2C operation enable
7
8
LREL
Exit from communications
6
7
SPIE
Enable generation of interrupt request when stop condition is detected
4
5
SPT
Stop condition trigger
0
1
STT
Start condition trigger
1
2
WREL
Wait cancellation
5
6
WTIM
Control of wait and interrupt request generation
3
4
IICCTL01
IICA control register 0
0x1
-1
read-write
n
0x0
0x0
CLD
Detection of SCLAn pin level (valid only when IICEn = 1)
5
6
read-only
DAD
Detection of SDAAn pin level (valid only when IICEn = 1)
4
5
read-only
DFC
Digital filter operation control
2
3
read-write
PRS
Operation clock (fMCK) contro
0
1
read-write
SMC
Operation mode switching
3
4
read-write
WUP
Control of address match wakeup
7
8
read-write
IICF0
IICA flag register 0
0x122
-1
read-write
n
0x0
0x0
IICBSY
I2C bus status flag
6
7
read-only
IICRSV
Communication reservation function disable bit
0
1
read-write
STCEN
Initial start enable trigger
1
2
read-write
STCF
STT clear flag
7
8
read-only
IICS0
IICA status register 0
0x121
-1
read-only
n
0x0
0x0
ACKD
Detection of acknowledge (ACK)
2
3
ALD
Detection of arbitration loss
6
7
COI
Detection of matching addresses
4
5
EXC
Detection of extension code reception
5
6
MSTS
Master status check flag
7
8
SPD
Detection of stop condition
0
1
STD
Detection of start condition
1
2
TRC
Detection of transmit/receive status
3
4
IICWH0
IICA high-level width setting register 0
0x3
-1
read-write
n
0x0
0x0
IICWL0
IICA low-level width setting register 0
0x2
-1
read-write
n
0x0
0x0
SVA0
Slave address register 0
0x4
-1
read-write
n
0x0
0x0
INT
Interrupt Controller
INT
0x0
0x0
0x200
registers
n
IFH
Interrupt flag register
0x1
8
read-write
n
0x0
0x0
IFL
Interrupt flag register
0x0
8
read-write
n
0x0
0x0
MKH
Interrupt mask register
0x1
8
read-write
n
0x0
0x0
MKL
Interrupt mask register
0x0
8
read-write
n
0x0
0x0
INTM
Pin input edge detection
INTM
0x0
0x0
0x100
registers
n
INTP0
INTP0 External interrupt request input is valid
1
INTP1
INTP1 External interrupt request input is valid
2
INTP2
INTP2 External interrupt request input is valid
3
INTP3
INTP3 External interrupt request input is valid
4
INTP4
INTP4 External interrupt request input is valid
5
INTP5
INTP5 External interrupt request input is valid
6
EGN0
External interrupt falling edge enable register
0x1
-1
read-write
n
0x0
0x0
EGN0
0
1
EGN1
1
2
EGN2
2
3
EGN3
3
4
EGN4
4
5
EGN5
5
6
EGN6
6
7
EGN7
7
8
EGN1
External interrupt falling edge enable register
0x3
-1
read-write
n
0x0
0x0
EGN10
2
3
EGN11
3
4
EGN8
0
1
EGN9
1
2
EGP0
External interrupt rising edge enable register
0x0
-1
read-write
n
0x0
0x0
EGP0
0
1
EGP1
1
2
EGP2
2
3
EGP3
3
4
EGP4
4
5
EGP5
5
6
EGP6
6
7
EGP7
7
8
EGP1
External interrupt rising edge enable register
0x2
-1
read-write
n
0x0
0x0
EGP10
2
3
EGP11
3
4
EGP8
0
1
EGP9
1
2
IRDA
IrDA communication module based on Infrared Data Association stardard 1.0
IRDA
0x0
0x0
0x1
registers
n
IRCR
IrDA control register
0x0
-1
read-write
n
0x0
0x0
IRCKS
IrRxD clock selection
4
7
IRE
IrRxD enable
7
8
IRRXINV
IrRxD data polarity switching
2
3
IRTXINV
IrRxD data polarity switching
3
4
KEY
Key interrupt
KEY
0x0
0x0
0x10
registers
n
KEY
KEY return interrupt request
23
KRM
Key return mode register
0x7
-1
read-write
n
0x0
0x0
LVD
Voltage detector
LVD
0x0
0x0
0x100
registers
n
LVI
Low Voltage detection interrupt
0
LVIM
Voltage detection register
0x1
8
read-write
n
0x0
0x0
LVIF
Voltage detection flag
0
1
read-only
GE
Supply voltage (VDD) greater or equal to detection voltage (VLVD), or when LVD is off
0
LT
Supply voltage (VDD) less than detection voltage (VLVD)
1
LVIOMSK
Mask status flag of LVD output
1
2
read-only
Invalid
Mask of LVD output is invalid
0
Valid
Mask of LVD output is valid
1
LVISEN
Enable rewritting LVIS register
7
8
read-only
Disable
Disabling of rewriting the LVIS register
0
Enable
Enabling of rewriting the LVIS register
1
LVIS
Voltage detection level register
0x2
8
read-write
n
0x0
0x0
LVILV
LVD detection level
0
1
read-write
High
High-voltage detection level (VLVDH)
0
Low
Low-voltage detection level (VLVDL or VLVD)
1
LVIMD
Operation mode of voltage detection
7
8
read-write
IRQ
interrupt mode
0
Reset
reset mode
1
MISC
Miscellaneous function
MISC
0x0
0x0
0x100
registers
n
ISC
Input switch control register
0x3
-1
read-write
n
0x0
0x0
ISC0
Switching external interrupt (INTP0) input
0
1
INTP0
Uses INTP0 pin as an external interrupt
0
RXD0
Uses RXD0 pin as an external interrupt
1
ISC1
Switching TI03 input
1
2
TI03
Uses TI03 pin as an timer input
0
RXD0
Uses RXD0 pin as an timer input
1
SSIE00
The slave select input (SS00) of SPI00 is valid
7
8
INVALID
The slave select input (SS00) pin is invalid
0
VALID
The slave select input (SS00) pin is valid
1
NFEN0
Noise filter enable register 0
0x0
-1
read-write
n
0x0
0x0
SNFEN00
Enable noise filter of RxD0
0
1
SNFEN10
Enable noise filter of RxD1
2
3
SNFEN20
Enable noise filter of RxD2
4
5
NFEN1
Noise filter enable register 1
0x1
-1
read-write
n
0x0
0x0
TNFEN00
Enable noise filter of TI00
0
1
TNFEN01
Enable noise filter of TI01
1
2
TNFEN02
Enable noise filter of TI02
2
3
TNFEN03
Enable noise filter of TI03
3
4
RTCCL
Real-time clock select register
0xC
-1
read-write
n
0x0
0x0
TIOS0
Timer I/O select register 0
0x4
-1
read-write
n
0x0
0x0
TIOS1
Timer I/O select register 1
0x5
-1
read-write
n
0x0
0x0
MTB
Micro Trace Buffer
MTB
0x0
0x0
0x1000
registers
n
AUTHSTATUS
MTB Authentication Status Register
0xFB8
-1
read-only
n
0x0
0x0
BASE
MTB Base Register
0xC
-1
read-only
n
0x0
0x0
CID0
CoreSight Register
0xFF0
-1
read-only
n
0x0
0x0
CID1
CoreSight Register
0xFF4
-1
read-only
n
0x0
0x0
CID2
CoreSight Register
0xFF8
-1
read-only
n
0x0
0x0
CID3
CoreSight Register
0xFFC
-1
read-only
n
0x0
0x0
DEVARCH
MTB Device Architecture Register
0xFBC
-1
read-only
n
0x0
0x0
DEVID
MTB Device Configuration Register
0xFC8
-1
read-only
n
0x0
0x0
DEVTYPE
MTB Device Type Register
0xFCC
-1
read-only
n
0x0
0x0
FLOW
MTB Flow Register
0x8
-1
read-write
n
0x0
0x0
AUTOHALT
1
2
AUTOSTOP
0
1
WATERMARK
3
32
LOCKACCESS
MTB Lock Access Register
0xFB0
-1
read-write
n
0x0
0x0
LOCKSTATUS
MTB Lock Status Register
0xFB4
-1
read-only
n
0x0
0x0
MASTER
MTB Master Register
0x4
-1
read-write
n
0x0
0x0
EN
31
32
HALTREQ
9
10
MASK
0
5
RAMPRIV
8
9
SFRWPRIV
7
8
TSTARTEN
5
6
TSTOPEN
6
7
PID0
CoreSight Register
0xFE0
-1
read-only
n
0x0
0x0
PID1
CoreSight Register
0xFE4
-1
read-only
n
0x0
0x0
PID2
CoreSight Register
0xFE8
-1
read-only
n
0x0
0x0
PID3
CoreSight Register
0xFEC
-1
read-only
n
0x0
0x0
PID4
CoreSight Register
0xFD0
-1
read-only
n
0x0
0x0
PID5
CoreSight Register
0xFD4
-1
read-only
n
0x0
0x0
PID6
CoreSight Register
0xFD8
-1
read-only
n
0x0
0x0
PID7
CoreSight Register
0xFDC
-1
read-only
n
0x0
0x0
POSITION
MTB Position Register
0x0
-1
read-write
n
0x0
0x0
POINTER
3
32
WRAP
2
3
PCBZ
Clock/Buzzer output controller
PCBZ
0x0
0x0
0x10
registers
n
CKS0
Clock output select registers 0
0x5
8
read-write
n
0x0
0x0
CCS
PCLBUZn output clock select
0
3
CSEL
PCLBUZn output clock select
3
4
PCLOE
PCLBUZn pin output enable
7
8
CKS1
Clock output select registers 1
0x6
-1
read-write
n
0x0
0x0
PGA
Programmable Gain Amplifier
PGA
0x0
0x0
0x100
registers
n
PGA0CTL
PGA 0 control register
0x6
-1
read-write
n
0x0
0x0
PGAEN
Programmable gain amplifier operation control
7
8
PGAVG
Programmable gain amplifier amplification factor selection
0
3
PVRVS
GND selection of feedback resistance of the programmable gain amplifier
3
4
PGA1CTL
PGA 1 control register
0x7
-1
read-write
n
0x0
0x0
PORT
Port functions
PORT
0x0
0x0
0x1000
registers
n
GDIDIS
Global digital input disable register
0x87D
8
read-write
n
0x0
0x0
P0
Port register 0
0x300
8
read-write
n
0x0
0x0
P1
Port register 1
0x301
8
read-write
n
0x0
0x0
P12
Port register 12
0x30C
8
read-write
n
0x0
0x0
P13
Port register 13
0x30D
8
read-write
n
0x0
0x0
P14
Port register 14
0x30E
8
read-write
n
0x0
0x0
P2
Port register 2
0x302
8
read-write
n
0x0
0x0
P3
Port register 3
0x303
8
read-write
n
0x0
0x0
P4
Port register 4
0x304
8
read-write
n
0x0
0x0
P5
Port register 5
0x305
8
read-write
n
0x0
0x0
P6
Port register 6
0x306
8
read-write
n
0x0
0x0
P7
Port register 7
0x307
8
read-write
n
0x0
0x0
PIM0
Port input mode register 0
0x40
8
read-write
n
0x0
0x0
PIM1
Port input mode register 1
0x41
8
read-write
n
0x0
0x0
PIM3
Port input mode register 3
0x43
8
read-write
n
0x0
0x0
PIM5
Port input mode register 5
0x45
8
read-write
n
0x0
0x0
PIM7
Port input mode register 7
0x47
8
read-write
n
0x0
0x0
PIOR0
Peripheral I/O redirection register 0
0x877
8
read-write
n
0x0
0x0
PIOR1
Peripheral I/O redirection register 1
0x879
8
read-write
n
0x0
0x0
PIOR2
Peripheral I/O redirection register 2
0x875
8
read-write
n
0x0
0x0
PIOR3
Peripheral I/O redirection register 3
0x87C
8
read-write
n
0x0
0x0
PM0
Port mode register 0
0x320
8
read-write
n
0x0
0x0
PM1
Port mode register 1
0x321
8
read-write
n
0x0
0x0
PM12
Port mode register 12
0x32C
8
read-write
n
0x0
0x0
PM13
Port mode register 13
0x32D
8
read-write
n
0x0
0x0
PM14
Port mode register 14
0x32E
8
read-write
n
0x0
0x0
PM2
Port mode register 2
0x322
8
read-write
n
0x0
0x0
PM3
Port mode register 3
0x323
8
read-write
n
0x0
0x0
PM4
Port mode register 4
0x324
8
read-write
n
0x0
0x0
PM5
Port mode register 5
0x325
8
read-write
n
0x0
0x0
PM6
Port mode register 6
0x326
8
read-write
n
0x0
0x0
PM7
Port mode register 7
0x327
8
read-write
n
0x0
0x0
PMC0
Port mode control register 0
0x60
8
read-write
n
0x0
0x0
PMC1
Port mode control register 1
0x61
8
read-write
n
0x0
0x0
PMC12
Port mode control register 12
0x6C
8
read-write
n
0x0
0x0
PMC14
Port mode control register 14
0x6E
8
read-write
n
0x0
0x0
PMC2
Port mode control register 2
0x62
8
read-write
n
0x0
0x0
PMS
Port mode select register
0x87B
8
read-write
n
0x0
0x0
POM0
Port output mode register 0
0x50
8
read-write
n
0x0
0x0
POM1
Port output mode register 1
0x51
8
read-write
n
0x0
0x0
POM3
Port output mode register 3
0x53
8
read-write
n
0x0
0x0
POM5
Port output mode register 5
0x55
8
read-write
n
0x0
0x0
POM7
Port output mode register 7
0x57
8
read-write
n
0x0
0x0
PU0
Pull-up resistor option register 0
0x30
8
read-write
n
0x0
0x0
PU1
Pull-up resistor option register 1
0x31
8
read-write
n
0x0
0x0
PU12
Pull-up resistor option register 12
0x3C
8
read-write
n
0x0
0x0
PU13
Pull-up resistor option register 13
0x3D
8
read-write
n
0x0
0x0
PU14
Pull-up resistor option register 14
0x3E
8
read-write
n
0x0
0x0
PU3
Pull-up resistor option register 3
0x33
8
read-write
n
0x0
0x0
PU4
Pull-up resistor option register 4
0x34
8
read-write
n
0x0
0x0
PU5
Pull-up resistor option register 5
0x35
8
read-write
n
0x0
0x0
PU7
Pull-up resistor option register 7
0x37
8
read-write
n
0x0
0x0
RST
Reset Function
RST
0x0
0x0
0x40
registers
n
RESF
Reset flag register
0x20
8
read-only
n
0x0
0x0
IAWRF
Internal reset request by illegal-memory access
1
2
clear
NONE
Internal reset request is not generated, or the RESF register is cleared.
0
DONE
Internal reset request is generated.
1
LVIRF
Internal reset request by voltage detector
0
1
clear
NONE
Internal reset request is not generated, or the RESF register is cleared.
0
DONE
Internal reset request is generated.
1
RPERF
Internal reset request by RAM parity
2
3
clear
NONE
Internal reset request is not generated, or the RESF register is cleared.
0
DONE
Internal reset request is generated.
1
SYSRF
Internal reset request by system reset request(AIRCR.SYSRESETREQ)
7
8
clear
NONE
Internal reset request is not generated, or the RESF register is cleared.
0
DONE
Internal reset request is generated.
1
WDTRF
Internal reset request by watchdog timer(WDT)
4
5
clear
NONE
Internal reset request is not generated, or the RESF register is cleared.
0
DONE
Internal reset request is generated.
1
RTC
Real-Time clock
RTC
0x0
0x0
0x100
registers
n
RTC
Real-Time Clock interrupt request
22
ALARMWH
Alarm hour register
0x5B
8
read-write
n
0x0
0x0
ALARMWM
Alarm minute register
0x5A
8
read-write
n
0x0
0x0
ALARMWW
Alarm week register
0x5C
8
read-write
n
0x0
0x0
DAY
Day count register
0x56
8
read-write
n
0x0
0x0
HOUR
Hour count register
0x54
8
read-write
n
0x0
0x0
ITMC
15-bit interval timer control register
0x50
16
read-write
n
0x0
0x0
ITCMP
15-bit interval timer compare value
0
15
RINTE
15-bit interval timer operation control
15
16
MIN
Minute count register
0x53
8
read-write
n
0x0
0x0
MONTH
Month count register
0x57
8
read-write
n
0x0
0x0
RTCC0
Real-time clock control register 0
0x5D
8
read-write
n
0x0
0x0
AMPM
Selection of 12-/24-hour system
3
4
CT
Constant-period interrupt (INTRTC) selection
0
3
RCLOE
RTC1HZ pin output enable
5
6
RTCE
Real-time clock operation control
7
8
RTCC1
Real-time clock control register 1
0x5E
8
read-write
n
0x0
0x0
RIFG
Constant-period interrupt status flag
3
4
RWAIT
Wait control of real-time clock
0
1
RWST
Wait status flag of real-time clock
1
2
WAFG
Alarm detection status flag
4
5
WALE
Alarm operation control
7
8
WALIE
Control of alarm interrupt (INTRTC) function operation
6
7
SEC
Second count register
0x52
8
read-write
n
0x0
0x0
SUBCUD
Watch error correction register
0x34
16
read-write
n
0x0
0x0
DEV
watch error correction timing
15
16
F
watch error correction value
0
13
WEEK
Week count register
0x55
8
read-write
n
0x0
0x0
YEAR
Year count register
0x58
8
read-write
n
0x0
0x0
SAF
Flash memory CRC operation function (High-Speed CRC)
SAF
0x0
0x0
0x30000
registers
n
CRC0CTL
Flash memory CRC control register
0x1710
8
read-write
n
0x0
0x0
CRC0EN
Control of high-speed CRC operation
7
8
FEA
High-speed CRC operation range
0
7
CRCD
CRC data register
0x231FA
16
read-write
n
0x0
0x0
CRCIN
CRC input register
0x232AC
8
read-write
n
0x0
0x0
PGCRCL
Flash memory CRC operation result register
0x1712
16
read-write
n
0x0
0x0
RPECTL
RAM parity error control register
0x325
8
read-write
n
0x0
0x0
RPEF
Parity error status flag
0
1
read-write
NoError
No parity error has occurred
0
Error
Parity error has occurred
1
RPERDIS
Disable RAM parity error reset
7
8
read-write
Enable
Enable parity error reset
0
Disable
Disable parity error reset
1
SFRGD
SFR guard control register
0x20378
-1
read-write
n
0x0
0x0
SCI0
Serial Communication Interface 0 with UART, SPI and simplified I2C supported
SCI0
0x0
0x0
0x300
registers
n
ST0
UART0 transmission transfer end or buffer empty
10
SR0
UART0 rerception transfer
11
SRE0
UART0 rerception communication error occurrence
12
ST1
UART1 transmission transfer end or buffer empty
13
SR1
UART1 rerception transfer
14
SRE1
UART1 rerception communication error occurrence
15
RXD0
UART receive data register
SDR01
0x212
8
read-write
n
0x0
0x0
RXD1
UART receive data register
SDR03
0x246
8
read-write
n
0x0
0x0
SCR00
Serial communication operation setting register mn
0x18
-1
read-write
n
0x0
0x0
CKP
Selection of clock phase in SPI mode
12
13
DAP
Selection of data phase in SPI mode
13
14
DIR
Selection of data transfer sequence in SPI and UART modes
7
8
DLS
Setting of data length in SPI and UART modes
0
2
EOC
Mask control of error interrupt signal (INTSREx (x = 0 to 2))
10
11
PTC
Setting of parity bit in UART mode
8
10
RXE
Reception enable
14
15
SLC
Setting of stop bit in UART mode
4
6
TXE
Transmission enable
15
16
SCR01
Serial communication operation setting register mn
0x1A
-1
read-write
n
0x0
0x0
SCR02
Serial communication operation setting register mn
0x1C
-1
read-write
n
0x0
0x0
SCR03
Serial communication operation setting register mn
0x1E
-1
read-write
n
0x0
0x0
SDR00
Serial data register 0%s
0x210
-1
read-write
n
0x0
0x0
SDR01
Serial data register 0%s
0x212
-1
read-write
n
0x0
0x0
SDR02
Serial data register 0%s
0x244
-1
read-write
n
0x0
0x0
SDR03
Serial data register 0%s
0x246
-1
read-write
n
0x0
0x0
SE0
Serial channel enable status register m
0x20
-1
read-only
n
0x0
0x0
SE00
Indication of operation enable/stop status of channel 0
0
1
SE01
Indication of operation enable/stop status of channel 1
1
2
SE02
Indication of operation enable/stop status of channel 2
2
3
SE03
Indication of operation enable/stop status of channel 3
3
4
SIO00
SPI data register
SDR00
0x210
8
read-write
n
0x0
0x0
SIO01
SPI data register
SDR01
0x212
8
read-write
n
0x0
0x0
SIO10
SPI data register
SDR02
0x244
8
read-write
n
0x0
0x0
SIO11
SPI data register
SDR03
0x246
8
read-write
n
0x0
0x0
SIR00
Serial flag clear trigger register mn
0x8
-1
read-write
n
0x0
0x0
FECT
Clear trigger of framing error flag of channel n
2
3
OVCT
Clear trigger of overrun error flag of channel n
0
1
PECT
Clear trigger of parity error flag of channel n
1
2
SIR01
Serial flag clear trigger register mn
0xA
-1
read-write
n
0x0
0x0
SIR02
Serial flag clear trigger register mn
0xC
-1
read-write
n
0x0
0x0
SIR03
Serial flag clear trigger register mn
0xE
-1
read-write
n
0x0
0x0
SMR00
Serial mode register mn
0x10
-1
read-write
n
0x0
0x0
CCS
Selection of transfer clock (fTCLK) of channel n
14
15
CKS
Selection of operation clock (fMCK) of channel n
15
16
MD
Setting of operation mode of channel n
0
4
SIS
Controls inversion of level of receive data of channel n in UART mode
6
7
STS
Selection of start trigger source
8
9
SMR01
Serial mode register mn
0x12
-1
read-write
n
0x0
0x0
SMR02
Serial mode register mn
0x14
-1
read-write
n
0x0
0x0
SMR03
Serial mode register mn
0x16
-1
read-write
n
0x0
0x0
SO0
Serial output register 0
0x28
-1
read-write
n
0x0
0x0
CKO00
Serial clock output of channel 0
8
9
CKO01
Serial clock output of channel 1
9
10
CKO02
Serial clock output of channel 2
10
11
CKO03
Serial clock output of channel 3
11
12
SO00
Serial data output of channel 0
0
1
SO01
Serial data output of channel 1
1
2
SO02
Serial data output of channel 2
2
3
SO03
Serial data output of channel 3
3
4
SOE0
Serial output enable register 0
0x2A
-1
read-write
n
0x0
0x0
SOE00
Serial output enable of channel 0
0
1
SOE01
Serial output enable of channel 1
1
2
SOE02
Serial output enable of channel 2
2
3
SOE03
Serial output enable of channel 3
3
4
SOL0
Serial output level register 0
0x34
-1
read-write
n
0x0
0x0
SOL00
Selects inversion of the level of the transmit data of channel n in UART mode
0
1
SOL02
Selects inversion of the level of the transmit data of channel n in UART mode
2
3
SPS0
Serial clock select register 0
0x26
-1
read-write
n
0x0
0x0
PRS00
Prescaler 0
0
4
PRS01
Prescaler 1
4
8
SS0
Serial channel start register 0
0x22
-1
read-write
n
0x0
0x0
SS00
Operation start trigger of channel 0
0
1
SS01
Operation start trigger of channel 1
1
2
SS02
Operation start trigger of channel 2
2
3
SS03
Operation start trigger of channel 3
3
4
SSR00
Serial status register mn
0x0
-1
read-only
n
0x0
0x0
BFF
Buffer register status indication flag of channel n
5
6
FEF
Framing error detection flag of channel n
2
3
OVF
Overrun error detection flag of channel n
0
1
PEF
Parity error detection flag of channel n
1
2
TSF
Communication status indication flag of channel n
6
7
SSR01
Serial status register mn
0x2
-1
read-write
n
0x0
0x0
SSR02
Serial status register mn
0x4
-1
read-write
n
0x0
0x0
SSR03
Serial status register mn
0x6
-1
read-write
n
0x0
0x0
ST0
Serial channel stop register 0
0x24
-1
read-write
n
0x0
0x0
ST00
Operation stop trigger of channel 0
0
1
ST01
Operation stop trigger of channel 1
1
2
ST02
Operation stop trigger of channel 2
2
3
ST03
Operation stop trigger of channel 3
3
4
TXD0
UART transmit data register
SDR00
0x210
8
read-write
n
0x0
0x0
TXD1
UART transmit data register
SDR02
0x244
8
read-write
n
0x0
0x0
SCI1
Serial Communication Interface 1 with UART, SPI and simplified I2C supported
SCI1
0x0
0x0
0x300
registers
n
ST2
UART2 transmission transfer end or buffer empty
7
SR2
UART2 rerception transfer
8
SRE2
UART2 rerception communication error occurrence
9
RXD2
UART receive data register
SDR11
0x20A
8
read-write
n
0x0
0x0
SCR10
Serial communication operation setting register mn
0x18
-1
read-write
n
0x0
0x0
CKP
Selection of clock phase in SPI mode
12
13
DAP
Selection of data phase in SPI mode
13
14
DIR
Selection of data transfer sequence in SPI and UART modes
7
8
DLS
Setting of data length in SPI and UART modes
0
2
EOC
Mask control of error interrupt signal (INTSREx (x = 0 to 2))
10
11
PTC
Setting of parity bit in UART mode
8
10
RXE
Reception enable
14
15
SLC
Setting of stop bit in UART mode
4
6
TXE
Transmission enable
15
16
SCR11
Serial communication operation setting register mn
0x1A
-1
read-write
n
0x0
0x0
SDR10
Serial data register 1%s
0x208
-1
read-write
n
0x0
0x0
SDR11
Serial data register 1%s
0x20A
-1
read-write
n
0x0
0x0
SE1
Serial channel enable status register 1
0x20
-1
read-only
n
0x0
0x0
SE10
Indication of operation enable/stop status of channel 0
0
1
SE11
Indication of operation enable/stop status of channel 1
1
2
SIO20
SPI data register
SDR10
0x208
8
read-write
n
0x0
0x0
SIO21
SPI data register
SDR11
0x20A
8
read-write
n
0x0
0x0
SIR10
Serial flag clear trigger register mn
0x8
-1
read-write
n
0x0
0x0
FECT
Clear trigger of framing error flag of channel n
2
3
OVCT
Clear trigger of overrun error flag of channel n
0
1
PECT
Clear trigger of parity error flag of channel n
1
2
SIR11
Serial flag clear trigger register mn
0xA
-1
read-write
n
0x0
0x0
SMR10
Serial mode register mn
0x10
-1
read-write
n
0x0
0x0
CCS
Selection of transfer clock (fTCLK) of channel n
14
15
CKS
Selection of operation clock (fMCK) of channel n
15
16
MD
Setting of operation mode of channel n
0
4
SIS
Controls inversion of level of receive data of channel n in UART mode
6
7
STS
Selection of start trigger source
8
9
SMR11
Serial mode register mn
0x12
-1
read-write
n
0x0
0x0
SO1
Serial output register 1
0x28
-1
read-write
n
0x0
0x0
CKO10
Serial clock output of channel 0
8
9
CKO11
Serial clock output of channel 1
9
10
SO10
Serial data output of channel 0
0
1
SO11
Serial data output of channel 1
1
2
SOE1
Serial output enable register 1
0x2A
-1
read-write
n
0x0
0x0
SOE10
Serial output enable of channel 0
0
1
SOE11
Serial output enable of channel 1
1
2
SOL1
Serial output level register 1
0x34
-1
read-write
n
0x0
0x0
SOL10
Selects inversion of the level of the transmit data of channel n in UART mode
0
1
SPS1
Serial clock select register 1
0x26
-1
read-write
n
0x0
0x0
PRS10
Prescaler 0
0
4
PRS11
Prescaler 1
4
8
SS1
Serial channel start register 1
0x22
-1
read-write
n
0x0
0x0
SS10
Operation start trigger of channel 0
0
1
SS11
Operation start trigger of channel 1
1
2
SSR10
Serial status register mn
0x0
-1
read-only
n
0x0
0x0
BFF
Buffer register status indication flag of channel n
5
6
FEF
Framing error detection flag of channel n
2
3
OVF
Overrun error detection flag of channel n
0
1
PEF
Parity error detection flag of channel n
1
2
TSF
Communication status indication flag of channel n
6
7
SSR11
Serial status register mn
0x2
-1
read-write
n
0x0
0x0
ST1
Serial channel stop register 1
0x24
-1
read-write
n
0x0
0x0
ST10
Operation stop trigger of channel 0
0
1
ST11
Operation stop trigger of channel 1
1
2
TXD2
UART transmit data register
SDR10
0x208
8
read-write
n
0x0
0x0
TM40
General Purpose Timer 4
TM40
0x0
0x0
0x200
registers
n
TM00
TM4 channel 0 interrupt request
17
TM01
TM4 channel 1 interrupt request
18
TM02
TM4 channel 2 interrupt request
19
TM03
TM4 channel 3 interrupt request
20
TCR00
Timer count register 0%s
0x0
-1
read-only
n
0x0
0x0
TCR01
Timer count register 0%s
0x2
-1
read-only
n
0x0
0x0
TCR02
Timer count register 0%s
0x4
-1
read-only
n
0x0
0x0
TCR03
Timer count register 0%s
0x6
-1
read-only
n
0x0
0x0
TDR00
Timer data register 0%s
0x198
-1
read-write
n
0x0
0x0
TDR01
Timer data register 0%s
0x19A
-1
read-write
n
0x0
0x0
TDR01H
Timer data higher register 01
TDR01
0x19B
8
read-write
n
0x0
0x0
TDR01L
Timer data lower register 01
TDR01
0x19A
8
read-write
n
0x0
0x0
TDR02
Timer data register 0%s
0x1E4
-1
read-write
n
0x0
0x0
TDR03
Timer data register 0%s
0x1E6
-1
read-write
n
0x0
0x0
TDR03H
Timer data higher register 03
TDR03
0x1E7
8
read-write
n
0x0
0x0
TDR03L
Timer data lower register 03
TDR03
0x1E6
8
read-write
n
0x0
0x0
TE0
Timer channel enable status register m
0x30
-1
read-only
n
0x0
0x0
TE00
Indication of operation enable/stop status of channel 0
0
1
TE01
Indication of operation enable/stop status of channel 1
1
2
TE02
Indication of operation enable/stop status of channel 2
2
3
TE03
Indication of operation enable/stop status of channel 3
3
4
TEH01
Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 1 is in the 8-bit timer mode
9
10
TEH03
Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 3 is in the 8-bit timer mode
11
12
TMR00
Timer mode register mn
0x10
-1
read-write
n
0x0
0x0
CCS
Selection of count clock (fTCLK) of channel n
12
13
read-write
CIS
Selection of TImn pin input valid edge
6
8
read-write
CKS
Selection of operation clock (fMCK) of channel n
14
16
read-write
MD
Operation mode of channel n
0
4
read-write
STS
Setting of start trigger or capture trigger of channel n
8
11
read-write
TMR01
Timer mode register mn
0x12
-1
read-write
n
0x0
0x0
CCS
Selection of count clock (fTCLK) of channel n
12
13
read-write
CIS
Selection of TImn pin input valid edge
6
8
read-write
CKS
Selection of operation clock (fMCK) of channel n
14
16
read-write
MD
Operation mode of channel n
0
4
read-write
SPLIT
Selection of 8 or 16-bit timer operation for channels 1 and 3
11
12
read-write
STS
Setting of start trigger or capture trigger of channel n
8
11
read-write
TMR02
Timer mode register mn
0x14
-1
read-write
n
0x0
0x0
CCS
Selection of count clock (fTCLK) of channel n
12
13
read-write
CIS
Selection of TImn pin input valid edge
6
8
read-write
CKS
Selection of operation clock (fMCK) of channel n
14
16
read-write
MASTER
Selection between using channel n independently or simultaneously with another channel (as a slave or master)
11
12
read-write
MD
Operation mode of channel n
0
4
read-write
STS
Setting of start trigger or capture trigger of channel n
8
11
read-write
TMR03
Timer mode register mn
0x16
-1
read-write
n
0x0
0x0
CCS
Selection of count clock (fTCLK) of channel n
12
13
read-write
CIS
Selection of TImn pin input valid edge
6
8
read-write
CKS
Selection of operation clock (fMCK) of channel n
14
16
read-write
MD
Operation mode of channel n
0
4
read-write
SPLIT
Selection of 8 or 16-bit timer operation for channels 1 and 3
11
12
read-write
STS
Setting of start trigger or capture trigger of channel n
8
11
read-write
TO0
Timer output register 0
0x38
-1
read-write
n
0x0
0x0
TO00
Timer output of channel 0
0
1
TO01
Timer output of channel 1
1
2
TO02
Timer output of channel 2
2
3
TO03
Timer output of channel 3
3
4
TOE0
Timer output enable register 0
0x3A
-1
read-write
n
0x0
0x0
TOE00
Timer output enable of channel 0
0
1
TOE01
Timer output enable of channel 1
1
2
TOE02
Timer output enable of channel 2
2
3
TOE03
Timer output enable of channel 3
3
4
TOL0
Timer output level register 0
0x3C
-1
read-write
n
0x0
0x0
TOL01
Control of timer output level of channel 1
1
2
TOL02
Control of timer output level of channel 2
2
3
TOL03
Control of timer output level of channel 3
3
4
TOM0
Timer output mode register 0
0x3E
-1
read-write
n
0x0
0x0
TOM01
Control of timer output mode of channel 1
1
2
TOM02
Control of timer output mode of channel 2
2
3
TOM03
Control of timer output mode of channel 3
3
4
TPS0
Timer clock select register 0
0x36
-1
read-write
n
0x0
0x0
PRS00
Prescaler 0
0
4
PRS01
Prescaler 1
4
8
PRS02
Prescaler 2
8
10
PRS03
Prescaler 3
12
14
TS0
Timer channel start register 0
0x32
-1
read-write
n
0x0
0x0
TS00
Operation enable (start) trigger of channel 0
0
1
TS01
Operation enable (start) trigger of channel 1
1
2
TS02
Operation enable (start) trigger of channel 2
2
3
TS03
Operation enable (start) trigger of channel 3
3
4
TSH01
Trigger to enable operation (start operation) of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
9
10
TSH03
Trigger to enable operation (start operation) of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
11
12
TSR00
Timer status register mn
0x20
-1
read-only
n
0x0
0x0
OVF
Counter overflow status of channel n
0
1
TSR01
Timer status register mn
0x22
-1
read-write
n
0x0
0x0
TSR02
Timer status register mn
0x24
-1
read-write
n
0x0
0x0
TSR03
Timer status register mn
0x26
-1
read-write
n
0x0
0x0
TT0
Timer channel stop register 0
0x34
-1
read-write
n
0x0
0x0
TT00
Operation stop trigger of channel 0
0
1
TT01
Operation stop trigger of channel 1
1
2
TT02
Operation stop trigger of channel 2
2
3
TT03
Operation stop trigger of channel 3
3
4
TTH01
Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
9
10
TTH03
Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
11
12
TMA
General Purpose Timer A
TMA
0x0
0x0
0xD0
registers
n
TMA
TMA interrupt request
26
TA0
Timer counter register 0
0xC0
16
read-write
n
0x0
0x0
TACR0
Timer control register 0
0x0
8
read-write
n
0x0
0x0
TCSTF
Timer count status flag
1
2
TEDGF
Active edge flag
4
5
TSTART
Timer count start
0
1
TSTOP
Timer count forced stop
2
3
TUNDF
Timer underflow flag
5
6
TAIOC0
Timer I/O control register 0
0x1
8
read-write
n
0x0
0x0
TEDGSEL
I/O polarity switch
0
1
TIOGT
TAIO count control
6
8
TIPF
TAIO input filter select
4
6
TOENA
TAO output enable
2
3
TAISR0
Timer event pin select register 0
0x3
8
read-write
n
0x0
0x0
RCCPSEL
Timer output signal select
0
3
TAMR0
Timer mode register 0
0x2
8
read-write
n
0x0
0x0
TCK
Timer count source select
4
7
TEDGPL
TAIO edge polarity select
3
4
TMOD
Operation mode select
0
3
TMB
General Purpose Timer B
TMB
0x0
0x0
0xD0
registers
n
TMB
TMB interrupt request
29
TB
Timer counter register
0x6
16
read-write
n
0x0
0x0
TBCNTC
Timer count control register
0x1
8
read-write
n
0x0
0x0
CNTEN0
counter enable 0
0
1
CNTEN1
counter enable 1
1
2
CNTEN2
counter enable 2
2
3
CNTEN3
counter enable 3
3
4
CNTEN4
counter enable 4
4
5
CNTEN5
counter enable 5
5
6
CNTEN6
counter enable 6
6
7
CNTEN7
counter enable 7
7
8
TBCR
Timer control register
0x2
8
read-write
n
0x0
0x0
TBCCLR
TB register clear source select
5
7
TBCKEG
External clock active edge select
3
5
TBTCK
Count source select
0
3
TBGRA
Timer general register %s
0x8
16
read-write
n
0x0
0x0
TBGRB
Timer general register %s
0xA
16
read-write
n
0x0
0x0
TBGRC
Timer general register %s
0xC
16
read-write
n
0x0
0x0
TBGRD
Timer general register %s
0xE
16
read-write
n
0x0
0x0
TBIER
Timer interrupt enable register
0x3
8
read-write
n
0x0
0x0
TBIMIEA
Input-capture/compare-match interrupt enable A
0
1
TBIMIEB
Input-capture/compare-match interrupt enable B
1
2
TBOVIE
Overflow interrupt enable
3
4
TBUDIE
Underflow interrupt enable
2
3
TBIOR
Timer I/O control register
0x5
8
read-write
n
0x0
0x0
TBBUFA
TBGRC register function select
3
4
TBBUFB
TBGRD register function select
7
8
TBIOA
TBGRA mode select and control
0
3
TBIOB
TBGRB mode select and control
4
7
TBMR
Timer mode register
0x0
8
read-write
n
0x0
0x0
TBDFA
Digital filer function select for TBIO0 pin
2
3
TBDFB
Digital filer function select for TBIO1 pin
3
4
TBDFCK
Digital filter function clock select
4
6
TBELCICE
EVENTC input capture request select
6
7
TBMDF
Phase counting mode select
1
2
TBPWM
PWM mode select
0
1
TBSTART
Timer count start
7
8
TBSR
Timer status enable register
0x4
8
read-write
n
0x0
0x0
TBDIRF
Count direction flag
4
5
TBIMFA
Input-capture/compare-match flag A
0
1
TBIMFB
Input-capture/compare-match flag B
1
2
TBOVF
Overflow flag
3
4
TBUDF
Underflow flag
2
3
TMC
General Purpose Timer C
TMC
0x0
0x0
0x10
registers
n
TMC
TMC interrupt request
30
TC
Timer counter register
0x0
16
read-write
n
0x0
0x0
TCBUF
Timer count buffer register
0x2
16
read-write
n
0x0
0x0
TCCR1
Timer control register 1
0x4
8
read-write
n
0x0
0x0
OVIE
Enables overflow interrupt
0
1
START_MD
Selects count start source
4
5
TCK
Selects count source
5
8
TM_TRIG
Selects a hardware start trigger from timer M
1
2
TRIG_MD_HW
Selects operation in a count mode selected by a trigger from timer M
2
3
TRIG_MD_SW
Signal for enabling TC counter reset by software
3
4
TCCR2
Timer control register 2
0x5
8
read-write
n
0x0
0x0
CMP1_TCR
Selects operation to be performed when a trigger is generated from comparator 1
1
3
TSTART
counter start
0
1
TCSR
Timer status register
0x6
8
read-write
n
0x0
0x0
TCOVF
Overflow status of TC counter
0
1
TCSB
Counter status flag
1
2
TMM
BLDC Motor control Timer M
TMM
0x0
0x0
0x2000
registers
n
TMM0
TMM channel 0 interrupt request
27
TMM1
TMM channel 1 interrupt request
28
OPCTL0
PWMOPA control register 0
0x11F8
8
read-write
n
0x0
0x0
ACT
When software release is selected: Software release timing selection
2
3
HAZAD_SET
Output cutoff hazard control selection
6
7
HS_SEL
Output forced cutoff release mode selection
0
1
HZ_REL
When software release is selected: Output cutoff release control
1
2
IN_EG
Output forced cutoff source edge/output forced cutoff release edge selection
5
6
IN_SEL
Cutoff source selection
3
5
OPDF0
PWMOPA cutoff control register 0
0x11F9
8
read-write
n
0x0
0x0
DFA0
TMIOA0 pin output forced cutoff control
0
2
DFB0
TMIOB0 pin output forced cutoff control
2
4
DFC0
TMIOC0 pin output forced cutoff control
4
6
DFD0
TMIOD0 pin output forced cutoff control
6
8
OPDF1
PWMOPA cutoff control register 1
0x11FA
8
read-write
n
0x0
0x0
DFA1
TMIOA1 pin output forced cutoff control
0
2
DFB1
TMIOB1 pin output forced cutoff control
2
4
DFC1
TMIOC1 pin output forced cutoff control
4
6
DFD1
TMIOD1 pin output forced cutoff control
6
8
OPEDGE
PWMOPA edge selection register
0x11FB
8
read-write
n
0x0
0x0
EG
Output forced cutoff release edge selection
0
2
OPSR
PWMOPA status register
0x11FC
8
read-only
n
0x0
0x0
HZIF0
Output cutoff source state
0
1
HZOF0
cutoff state
1
2
HZOF1
cutoff state
2
3
TM0
Timer M counter 0
0x16
16
read-write
n
0x0
0x0
TM1
Timer M counter 1
0x26
-1
read-write
n
0x0
0x0
TMCR0
Timer control register 0
0x10
8
read-write
n
0x0
0x0
CCLR
TMi counter clear select
5
8
CKEG
External clock edge select
3
5
TCK
Count source select
0
3
TMCR1
Timer control register 1
0x20
-1
read-write
n
0x0
0x0
TMDF0
Digital filter function select register 0
0xA
8
read-write
n
0x0
0x0
DFA
TMIOAi pin digital filter function select
0
1
DFB
TMIOBi pin digital filter function select
1
2
DFC
TMIOCi pin digital filter function select
2
3
DFCK
Clock select for digital filter function
6
8
DFD
TMIODi pin digital filter function select
3
4
TMDF1
Digital filter function select register 1
0xB
-1
read-write
n
0x0
0x0
TMELC
Timer ELC register
0x0
8
read-write
n
0x0
0x0
ELCICE0
ELC event input 0 select for timer M input capture D0
0
1
ELCICE1
ELC event input 1 select for timer M input capture D1
4
5
ELCOBE0
ELC event input 0 enable for timer M pulse output forced cutoff
1
2
ELCOBE1
ELC event input 1 enable for timer M pulse output forced cutoff
5
6
TMFCR
Timer function control register
0x6
8
read-write
n
0x0
0x0
CMD
Combination mode select
0
2
OLS0
Phase output level select
2
3
OLS1
Counter-Phase output level select
3
4
PWM3
PWM3 mode select
7
8
STCLK
External clock input select
6
7
TMGRA0
Timer M general register A0
0x18
16
read-write
n
0x0
0x0
TMGRA1
Timer M general register A1
0x28
-1
read-write
n
0x0
0x0
TMGRB0
Timer M general register B0
0x1A
16
read-write
n
0x0
0x0
TMGRB1
Timer M general register B1
0x2A
-1
read-write
n
0x0
0x0
TMGRC0
Timer M general register C0
0xF8
16
read-write
n
0x0
0x0
TMGRC1
Timer M general register C1
0xFC
-1
read-write
n
0x0
0x0
TMGRD0
Timer M general register D0
0xFA
16
read-write
n
0x0
0x0
TMGRD1
Timer M general register D1
0xFE
-1
read-write
n
0x0
0x0
TMIER0
Timer interrupt enable register 0
0x14
8
read-write
n
0x0
0x0
IMIEA
Input capture/compare match interrupt enable A
0
1
IMIEB
Input capture/compare match interrupt enable B
1
2
IMIEC
Input capture/compare match interrupt enable C
2
3
IMIED
Input capture/compare match interrupt enable D
3
4
OVIE
Overflow/underflow interrupt enable
4
5
TMIER1
Timer interrupt enable register 1
0x24
-1
read-write
n
0x0
0x0
TMIORA0
Timer I/O control register A0
0x11
8
read-write
n
0x0
0x0
IOA
TMGRA mode control
0
3
IOB
TMGRB mode control
4
7
TMIORA1
Timer I/O control register A1
0x21
-1
read-write
n
0x0
0x0
TMIORC0
Timer I/O control register C0
0x12
8
read-write
n
0x0
0x0
IOC
TMGRC mode control
0
4
IOD
TMGRD mode control
4
8
TMIORC1
Timer I/O control register C1
0x22
-1
read-write
n
0x0
0x0
TMMR
Timer mode register
0x4
8
read-write
n
0x0
0x0
TMBFC0
TMGRC0 register function select
4
5
TMBFC1
TMGRC1 register function select
6
7
TMBFD0
TMGRD0 register function select
5
6
TMBFD1
TMGRD1 register function select
7
8
TMSYNC
TMs synchronous
0
1
TMOCR
Timer output control register
0x9
8
read-write
n
0x0
0x0
TOA0
TMIOA0 initial output level select
0
1
TOA1
TMIOA1 initial output level select
4
5
TOB0
TMIOB0 initial output level select
1
2
TOB1
TMIOB1 initial output level select
5
6
TOC0
TMIOC0 initial output level select
2
3
TOC1
TMIOC1 initial output level select
6
7
TOD0
TMIOD0 initial output level select
3
4
TOD1
TMIOD1 initial output level select
7
8
TMOER1
Timer output master enable register 1
0x7
8
read-write
n
0x0
0x0
EA0
TMIOA0 output disable
0
1
EA1
TMIOA1 output disable
4
5
EB0
TMIOB0 output disable
1
2
EB1
TMIOB1 output disable
5
6
EC0
TMIOC0 output disable
2
3
EC1
TMIOC1 output disable
6
7
ED0
TMIOD0 output disable
3
4
ED1
TMIOD1 output disable
7
8
TMOER2
Timer output master enable register 2
0x8
8
read-write
n
0x0
0x0
TMPTO
INTP0 pin of pulse output forced cutoff signal input enabled
7
8
TMSHUTS
Forced cutoff flag
0
1
TMPMR
PWM function select register
0x5
8
read-write
n
0x0
0x0
TMPWMB0
PWM function of TMIOB0 select
0
1
TMPWMB1
PWM function of TMIOB1 select
4
5
TMPWMC0
PWM function of TMIOC0 select
1
2
TMPWMC1
PWM function of TMIOC1 select
5
6
TMPWMD0
PWM function of TMIOD0 select
2
3
TMPWMD1
PWM function of TMIOD1 select
6
7
TMPOCR0
PWM output level control register 0
0x15
8
read-write
n
0x0
0x0
POLB
PWM output level control B
0
1
POLC
PWM output level control C
1
2
POLD
PWM output level control D
2
3
TMPOCR1
PWM output level control register 1
0x25
-1
read-write
n
0x0
0x0
TMSR0
Timer status register 0
0x13
8
read-write
n
0x0
0x0
IMFA
Input capture/compare match flag A
0
1
IMFB
Input capture/compare match flag B
1
2
IMFC
Input capture/compare match flag C
2
3
IMFD
Input capture/compare match flag D
3
4
OVF
Overflow flag
4
5
TMSR1
Timer status register 1
0x23
-1
read-write
n
0x0
0x0
UDF
Underflow flag
5
6
TMSTR
Timer start register
0x3
8
read-write
n
0x0
0x0
CSEL0
TM0 count operation select
2
3
CSEL1
TM1 count operation select
3
4
TSTART0
TM0 count start flag
0
1
TSTART1
TM1 count start flag
1
2
TSN
Temperature Sensor calibration data
TSN
0x0
0x0
0x8
registers
n
TSN25
The A/D conversion value of Temperature Sensor at 25 degrees and 3.0V reference voltage
0x4
-1
read-only
n
0x0
0x0
int16_t
TSN85
The A/D conversion value of Temperature Sensor at 85 degrees and 3.0V reference voltage
0x0
-1
read-only
n
0x0
0x0
int16_t
UID
128-bit Unique ID
UID
0x0
0x0
0x80
registers
n
UID0
UID word %s
0x0
-1
read-only
n
0x0
0x0
UID1
UID word %s
0x4
-1
read-only
n
0x0
0x0
UID2
UID word %s
0x8
-1
read-only
n
0x0
0x0
UID3
UID word %s
0xC
-1
read-only
n
0x0
0x0
WDT
Watchdog Timer with window
WDT
0x0
0x0
0x10
registers
n
WDTE
Watchdog timer enable register
0x1
-1
read-write
n
0x0
0x0