Cmsemicon BAT32G157 2024.11.11 ARM 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 64MHz, etc. CM0+ r0p1 little 2 false 8 32 ADC A/D Converter ADC 0x40045000 0x0 0x100 registers n ADC ADC interrupt request 22 ADCR 12-bit A/D conversion result register 0xE 16 read-write n 0x0 0xFFF ADCRH Higher 8-bit A/D conversion result register ADCR 0xF 8 read-write n 0x0 0xFFFFFFFF ADFLG A/D flag register 0x16 8 read-write n 0x0 0x1F ADLL Conversion result comparison lower limit setting register 0xA 8 read-write n 0x0 0xFF ADM0 A/D mode register 0 0x0 8 read-write n 0x0 0xB9 ADCE A/D enable 0 1 ADCS A/D conversion operation control 7 8 FR A/D conversion clock (fAD) select 3 6 ADM1 A/D mode register 1 0x2 8 read-write n 0x0 0x8B ADMD A/D conversion channel select mode 7 8 Select Select mode 0 Scan Scan mode 1 ADMODE A/D mode select 0 2 ADSCM A/D conversion mode 3 4 Sequential Sequential conversion mode 0 OneShot One-shot conversion mode 1 ADM2 A/D mode register 2 0x4 8 read-write n 0x0 0xEA ADRCK the upper limit and lower limit conversion result values 3 4 ADREFM Selection of the - side reference voltage of A/D converter 5 6 VSS Supplied from VSS 0 AVREFM Supplied from AVREFM 1 ADREFP Selection of the + side reference voltage of A/D converter 6 8 VDD Supplied from VDD 0b00 AVREFP0 Supplied from AVREFP 0b01 AVREFP1 Supplied from inside AVREF of A/D 0b10 CHRDE output CH number in A/D conversion result in Scan mode 1 2 ADNDIS A/D charge/discharge control register 0x11 8 read-write n 0x0 0xFF ADNSMP A/D sampling time control register 0xC 8 read-write n 0x0 0xFF ADS Analog input channel specification register 0x8 8 read-write n 0x0 0xBF ADSMPWAIT A/D sampling wait control register 0x15 8 read-write n 0x0 0xFF ADTES A/D test register 0x10 8 read-write n 0x0 0x7 ADTRG A/D mode register 2 0x6 8 read-write n 0x0 0x33 ADTMD A/D conversion trigger mode 6 8 ADTRS A/D hard trigger select 0 2 ADUL Conversion result comparison upper limit setting register 0xB 8 read-write n 0xFF 0xFF PGA0SH PGA 0 sample and hold function register 0x1E 16 read-write n 0x0 0x83FF PGA0SH Sample and hold time selection 0 10 PGA0SHEN Sample and hold function enable control 15 16 BGR Temperature Sensor calibration data BGR 0x08500C60 0x0 0x8 registers n VBG25 The A/D conversion value of VBGR at 25 degrees and 3.0V reference voltage 0x4 -1 read-only n 0x0 0xFFFF VBG85 The A/D conversion value of VBGR at 85 degrees and 3.0V reference voltage 0x0 -1 read-only n 0x0 0xFFFF CGC Clock Generate Control CLK 0x40020400 0x0 0x2000 registers n CKC System clock control register 0x4 8 read-write n 0x0 0xF0 CLS Status of CPU/peripheral hardware clock (fCLK) 7 8 read-only fMAIN Main system clock (fMAIN) 0 fSUB Subsystem clock (fSUB) 1 CSS Selection of CPU/peripheral hardware clock (fCLK) 6 7 read-write fMAIN Main system clock (fMAIN) 0 fSUB Subsystem clock (fSUB) 1 MCM0 Main system clock (fMAIN) operation control 4 5 read-write fIH Select the high-speed on-chip oscillator clock (fIH) as the main system clock (fMAIN) 0 fMX Select the high-speed system clock (fMX) as the main system clock (fMAIN) 1 MCS Status of Main system clock (fMAIN) 5 6 read-only fIH High-speed on-chip oscillator clock (fIH) 0 fMX High-speed system clock (fMX) 1 CMC Clock operaton Mode Control Register 0x0 8 read-write n 0x0 0xF7 AMPH Control of X1 clock oscillation frequency 0 1 read-write AMPHS Control of XT1 clock oscillation frequency 1 3 read-write EXCLK External Clock input mode 7 8 read-write EXCLKS External Clock input mode 5 6 read-write OSCSEL Main OSC Select 6 7 read-write OSCSELS Sub OSC Select 4 5 read-write CSC Clock operation Status Register 0x1 8 read-write n 0x0 0xC1 HIOSTOP High-speed on-chip oscillator clock operation control 0 1 read-write START High-speed on-chip oscillator operating 0 STOP High-speed on-chip oscillator stopped 1 MSTOP High-speed system clock operation control 7 8 read-write START X1 oscillator operating or External clock from EXCLK pin is valid 0 STOP X1 oscillator stop or External clock from EXCLK pin is invalid 1 XTSTOP Subsystem clock operation control 6 7 read-write START XT1 oscillator operating or External clock from EXCLKS pin is valid 0 STOP XT1 oscillator stop or External clock from EXCLKS pin is invalid 1 HIOTRM High-speed on-chip oscillator trimming register 0x1800 8 read-write n 0x0 0x3F HOCODIV High-speed on-chip oscillator frequency select register 0x1820 8 read-write n 0x0 0x7 MCKC Main system clock control register 0x800 8 read-write n 0x0 0x17 CKSELR Select f(IH) or f(PLL) 0 1 read-write fIH Select the high-speed on-chip oscillator clock (fIH) as the main system clock (fMAIN) 0 PLL Select the PLL clock (fPLL) as the main system clock (fMAIN) 1 CKSTR Status of Main system clock (fMAIN) 7 8 read-only fIH High-speed on-chip oscillator clock (fIH) 0 fPLL PLL clock (fPLL) 1 PDIV PLL frequency select register 1 3 read-write OSMC Subsystem clock supply mode control register 0x23 8 read-write n 0x0 0x90 RTCLPC Setting in DEEPSLEEP mode or SLEEP mode while subsystem clock is selected as CPU clock 7 8 read-write Enable Enables supply of subsystem clock to peripheral function 0 Disable Stops supply of subsystem clock to peripheral functions other than real-time clock and 15-bit interval timer. 1 WUTMMCK0 Selection of operation clock for real-time clock, 15-bit interval timer 4 5 read-write fSUB The subsystem clock is selected as the operation clock for the real-time clock and the 15-bit interval timer. 0 fIL The low-speed on-chip oscillator clock is selected as the operation clock for the real-time clock and the 15-bit interval timer. 1 OSTC Oscillation stabilization time counter status 0x2 8 read-only n 0x0 0xFF OSTS Oscillation stabilization time select register 0x3 8 read-write n 0x0 0x7 PER0 Peripheral enable register 0 0x20 8 read-write n 0x0 0xFF IICA0EN Control of the IICA0 input clock 5 6 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 IICA1EN Control of the IICA1 input clock 6 7 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 RTCEN Control of the RTC input clock 7 8 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 SCI0EN Control of the SCI0 input clock 2 3 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 SCI1EN Control of the SCI1 input clock 3 4 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 SCI2EN Control of the SCI2 input clock 4 5 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 TM40EN Control of the TM4 input clock 0 1 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 TM81EN Control of the TM8 input clock 1 2 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 PER1 Peripheral enable register 1 0x41A 8 read-write n 0x0 0xFF ADCEN Control of the ADC input clock 0 1 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 DMAEN Control of the DMA input clock 3 4 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 EPWMEN Control of the EPWM input clock 2 3 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 IRDAEN Control of the IRDA input clock 4 5 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 LCDBEN Control of the LCDB input clock 1 2 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 PGACMPEN Control of the PGACMP input clock 5 6 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 SPIHS0EN Control of the SPIHS0 input clock 6 7 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 SPIHS1EN Control of the SPIHS1 input clock 7 8 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 PER2 Peripheral enable register 2 0x41B 8 read-write n 0x0 0xFF SSIEN Control of the SSI input clock 1 2 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 USBEN Control of the USB input clock 0 1 Disabled Disables input clock supply 0 Enable Enables input clock supply 1 PLLCR System PLL clock control register 0x802 8 read-write n 0x0 0x8F PLLD PLL frequency division ratio select 2 4 read-write PLLM PLL frequency multiplication factor select 1 2 read-write X12 PLL multiplication factor is 12 0 X16 PLL multiplication factor is 16 1 PLLON PLL operation control 0 1 read-write PLL STOP PLL is stopped 0 PLL ON PLL is operating 1 PLLSRSEL PLL input clock source select 7 8 read-only fIH Select the high-speed on-chip oscillator clock (fIH) as PLL input source 0 fMX Select external main system clock f(MX) as PLL input source 1 SUBCKSEL Subsystem Clock select register 0x7 8 read-write n 0x0 0x1 SELLOSC Select LOSC or SUBOSC 0 1 SUBOSC Select SUBOSC as the SubSystem clock 0 LOSC Select LOSC as the SubSystem clock 1 UPLLCR USB-dedicated system PLL clock control register 0x803 8 read-write n 0x0 0x8F UPLLD USB-dedicated PLL frequency division ratio select 2 4 read-write UPLLM USB-dedicated PLL frequency multiplication factor select 1 2 read-write X12 UPLL multiplication factor is 12 0 X16 UPLL multiplication factor is 16 1 UPLLON USB-dedicated PLL operation control 0 1 read-write UPLL STOP UPLL is stopped 0 UPLL ON UPLL is operating 1 UPLLSRSEL USB-dedicated PLL input clock source select 7 8 read-only fIH Select the high-speed on-chip oscillator clock (fIH) as UPLL input source 0 fMX Select external main system clock f(MX) as UPLL input source 1 CMP Comparator CMP 0x40043840 0x0 0x100 registers n CMP0 CMP0 interrupt request 25 CMP1 CMP1 interrupt request 26 C0RVM Comparator internal reference voltage select register 0 0x4 -1 read-write n 0x0 0xFF C1RVM Comparator internal reference voltage select register 1 0x5 -1 read-write n 0x0 0xFFFFFFFF CMP0HY Comparator 0 input voltage hysteresis control register 0xE -1 read-write n 0x0 0x33 C0HYSLS Selection of the input hysteresis voltage level of Comparator 0 0 2 C0HYSVS Selection of the input hysteresis voltage of Comparator 0 4 6 CMP1HY Comparator 1 input voltage hysteresis control register 0xF -1 read-write n 0x0 0x33 C1HYSLS Selection of the input hysteresis voltage level of Comparator 1 0 2 C1HYSVS Selection of the input hysteresis voltage of Comparator 1 4 6 CMPSEL0 Comparator 0 input signal selection control register 0xA -1 read-write n 0x0 0x83 C0REFS Selection of the input signal on the negative side of Comparator 0 0 2 CMP0SEL Selection of the input signal on the positive side of Comparator 0 7 8 CMPSEL1 Comparator 1 input signal selection control register 0xB -1 read-write n 0x0 0xC7 C1REFS Selection of the input signal on the negative side of Comparator 1 0 3 CMP1SEL Selection of the input signal on the positive side of Comparator 1 6 8 COMPFIR Comparator filter control register 0x1 -1 read-write n 0x0 0xFF C0EDG Comparator 0 edge detection selection 3 4 C0EPO Comparator 0 edge polarity switching 2 3 C0FCK Comparator 0 filter selection 0 2 C1EDG Comparator 1 edge detection selection 7 8 C1EPO Comparator 1 edge polarity switching 6 7 C1FCK Comparator 1 filter selection 4 6 COMPMDR Comparator mode setting register 0x0 -1 read-write n 0x0 0x99 C0ENB Comparator 0 operation 1enable 0 1 C0MON Comparator 0 monitor flag 3 4 C1ENB Comparator 1 operation enable 4 5 C1MON Comparator 1 monitor flag 7 8 COMPOCR Comparator output control register 0x2 -1 read-write n 0x0 0xF7 C0IE Comparator 0 interrupt request enable 0 1 C0OE VOUT0 pin output enable 1 2 C0OP VOUT0 output polarity selection 2 3 C1IE Comparator 1 interrupt request enable 4 5 C1OE VOUT1 pin output enable 5 6 C1OP VOUT1 output polarity selection 6 7 C1OTWMD TIMER WINDOW output mode control bit of comparator 1 7 8 CVRCTL Comparator internal reference voltage control register 0x3 -1 read-write n 0x0 0x33 CVRE0 Control bit for internal reference voltage 0 1 2 CVRE1 Control bit for internal reference voltage 1 5 6 CVRVS0 Power supply selection bit for internal reference voltage 0 1 CVRVS1 Ground selection bit for internal reference voltage 4 5 DBG DBG Controller DBG 0x4001B000 0x0 0x100 registers n DBGSTOPCR Debug Stop Control register 0x4 -1 read-write n 0x0 0x1010007 FRZEN0 Stop Timer family macros when cpu halted 0 1 FRZEN1 Stop Communation family macros when cpu halted 1 2 RESMSK Mask internal reset in debug mode 2 3 RPERMSK Mask RAM parity error in debug mode 16 17 SWDIS SWD Disable 24 25 DBGSTR Debug status register 0x0 -1 read-only n 0x0 0x30000000 CDBGPWRUPACK DBG Power Up Acknowledgement 29 30 CDBGPWRUPREQ DBG Power Up Request 28 29 DIV Hardware divider DIV 0x4001C000 0x0 0x100 registers n DIVIDEND Dividend register 0x0 -1 read-write n 0x0 0xFFFFFFFF DIVISOR Divisor register 0x4 -1 read-write n 0x0 0xFFFFFFFF QUOTIENT Quotient register 0x8 -1 read-only n 0x0 0xFFFFFFFF REMAINDER Remainder register 0xC -1 read-only n 0x0 0xFFFFFFFF STATUS Status register 0x10 -1 read-only n 0x0 0xFFFFFFFF BUSY divider busy flag 8 9 read-only DIVBYZERO divider zero flag 9 10 read-only DMA Enhanced DMA Controller DMA 0x40005000 0x0 0x100 registers n DMABAR DMA base address register 0x8 32 read-write n 0x0 0xFFFFFFFF DMAEN0 DMA activation enable register %s 0x0 8 read-write n 0x0 0xFF DMAEN1 DMA activation enable register %s 0x1 8 read-write n 0x0 0xFF DMAEN2 DMA activation enable register %s 0x2 8 read-write n 0x0 0xFF DMAEN3 DMA activation enable register %s 0x3 8 read-write n 0x0 0xFF DMAEN4 DMA activation enable register %s 0x4 8 read-write n 0x0 0xFF DMAIF0 DMA Trigger enable register %s 0x10 8 read-write n 0x0 0xFF DMAIF1 DMA Trigger enable register %s 0x11 8 read-write n 0x0 0xFF DMAIF2 DMA Trigger enable register %s 0x12 8 read-write n 0x0 0xFF DMAIF3 DMA Trigger enable register %s 0x13 8 read-write n 0x0 0xFF DMAIF4 DMA Trigger enable register %s 0x14 8 read-write n 0x0 0xFF IFPRCR DMA Trigger Protect register 0xC 32 read-write n 0x0 0xFFFFFFFF DMAVEC DMA Vector and Control Data Area DMAVEC 0x20000000 0x0 0x2C0 registers n DMACR DMA Control register 0x0 16 read-write n 0x0 0x0 CHNE Enabling/disabling chain transfers 4 5 read-write disable Chain transfers disabled 0 enable Chain transfers enabled 1 DAMOD Destination address control 3 4 read-write Fixed Fixed 0 Incremented Incremented 1 FIFO FIFO block transfer control 8 9 read-write disable FIFO block transfer disabled 0 enable FIFO block transfer enabled 1 MODE Transfer mode selection 0 1 read-write Normal Normal mode 0 Repeat Repeat mode 1 RPTINT Enabling/disabling repeat mode interrupts 5 6 read-write disable Interrupt generation disabled 0 enable Interrupt generation enabled 1 RPTSEL Repeat area selection 1 2 read-write destination Transfer destination is the repeat area 0 source Transfer source is the repeat area 1 SAMOD Source address control 2 3 read-write Fixed Fixed 0 Incremented Incremented 1 SZ Transfer Data size selection 6 8 read-write BYTE 8 bits 0 HALF 16 bits 1 WORD 32 bits 2 DMACT DMA Transfer Count register 0x4 16 read-write n 0x0 0x0 DMBLS DMA Block Size register 0x2 16 read-write n 0x0 0x0 DMDAR DMA Destination Address register 0xC 32 read-write n 0x0 0x0 DMRLD DMA Transfer Count Reload register 0x6 16 read-write n 0x0 0x0 DMSAR DMA Source Address register 0x8 32 read-write n 0x0 0x0 VEC0 DMA vector area 0x0 8 read-write n 0x0 0xFFFFFFFF VEC1 DMA vector area 0x1 8 read-write n 0x0 0xFFFFFFFF VEC10 DMA vector area 0xA 8 read-write n 0x0 0xFFFFFFFF VEC11 DMA vector area 0xB 8 read-write n 0x0 0xFFFFFFFF VEC12 DMA vector area 0xC 8 read-write n 0x0 0xFFFFFFFF VEC13 DMA vector area 0xD 8 read-write n 0x0 0xFFFFFFFF VEC14 DMA vector area 0xE 8 read-write n 0x0 0xFFFFFFFF VEC15 DMA vector area 0xF 8 read-write n 0x0 0xFFFFFFFF VEC16 DMA vector area 0x10 8 read-write n 0x0 0xFFFFFFFF VEC17 DMA vector area 0x11 8 read-write n 0x0 0xFFFFFFFF VEC18 DMA vector area 0x12 8 read-write n 0x0 0xFFFFFFFF VEC19 DMA vector area 0x13 8 read-write n 0x0 0xFFFFFFFF VEC2 DMA vector area 0x2 8 read-write n 0x0 0xFFFFFFFF VEC20 DMA vector area 0x14 8 read-write n 0x0 0xFFFFFFFF VEC21 DMA vector area 0x15 8 read-write n 0x0 0xFFFFFFFF VEC22 DMA vector area 0x16 8 read-write n 0x0 0xFFFFFFFF VEC23 DMA vector area 0x17 8 read-write n 0x0 0xFFFFFFFF VEC24 DMA vector area 0x18 8 read-write n 0x0 0xFFFFFFFF VEC25 DMA vector area 0x19 8 read-write n 0x0 0xFFFFFFFF VEC26 DMA vector area 0x1A 8 read-write n 0x0 0xFFFFFFFF VEC27 DMA vector area 0x1B 8 read-write n 0x0 0xFFFFFFFF VEC28 DMA vector area 0x1C 8 read-write n 0x0 0xFFFFFFFF VEC29 DMA vector area 0x1D 8 read-write n 0x0 0xFFFFFFFF VEC3 DMA vector area 0x3 8 read-write n 0x0 0xFFFFFFFF VEC30 DMA vector area 0x1E 8 read-write n 0x0 0xFFFFFFFF VEC31 DMA vector area 0x1F 8 read-write n 0x0 0xFFFFFFFF VEC32 DMA vector area 0x20 8 read-write n 0x0 0xFFFFFFFF VEC33 DMA vector area 0x21 8 read-write n 0x0 0xFFFFFFFF VEC34 DMA vector area 0x22 8 read-write n 0x0 0xFFFFFFFF VEC35 DMA vector area 0x23 8 read-write n 0x0 0xFFFFFFFF VEC36 DMA vector area 0x24 8 read-write n 0x0 0xFFFFFFFF VEC37 DMA vector area 0x25 8 read-write n 0x0 0xFFFFFFFF VEC38 DMA vector area 0x26 8 read-write n 0x0 0xFFFFFFFF VEC39 DMA vector area 0x27 8 read-write n 0x0 0xFFFFFFFF VEC4 DMA vector area 0x4 8 read-write n 0x0 0xFFFFFFFF VEC40 DMA vector area 0x28 8 read-write n 0x0 0xFFFFFFFF VEC41 DMA vector area 0x29 8 read-write n 0x0 0xFFFFFFFF VEC42 DMA vector area 0x2A 8 read-write n 0x0 0xFFFFFFFF VEC43 DMA vector area 0x2B 8 read-write n 0x0 0xFFFFFFFF VEC44 DMA vector area 0x2C 8 read-write n 0x0 0xFFFFFFFF VEC45 DMA vector area 0x2D 8 read-write n 0x0 0xFFFFFFFF VEC46 DMA vector area 0x2E 8 read-write n 0x0 0xFFFFFFFF VEC47 DMA vector area 0x2F 8 read-write n 0x0 0xFFFFFFFF VEC48 DMA vector area 0x30 8 read-write n 0x0 0xFFFFFFFF VEC49 DMA vector area 0x31 8 read-write n 0x0 0xFFFFFFFF VEC5 DMA vector area 0x5 8 read-write n 0x0 0xFFFFFFFF VEC50 DMA vector area 0x32 8 read-write n 0x0 0xFFFFFFFF VEC51 DMA vector area 0x33 8 read-write n 0x0 0xFFFFFFFF VEC52 DMA vector area 0x34 8 read-write n 0x0 0xFFFFFFFF VEC53 DMA vector area 0x35 8 read-write n 0x0 0xFFFFFFFF VEC54 DMA vector area 0x36 8 read-write n 0x0 0xFFFFFFFF VEC55 DMA vector area 0x37 8 read-write n 0x0 0xFFFFFFFF VEC56 DMA vector area 0x38 8 read-write n 0x0 0xFFFFFFFF VEC57 DMA vector area 0x39 8 read-write n 0x0 0xFFFFFFFF VEC58 DMA vector area 0x3A 8 read-write n 0x0 0xFFFFFFFF VEC59 DMA vector area 0x3B 8 read-write n 0x0 0xFFFFFFFF VEC6 DMA vector area 0x6 8 read-write n 0x0 0xFFFFFFFF VEC60 DMA vector area 0x3C 8 read-write n 0x0 0xFFFFFFFF VEC61 DMA vector area 0x3D 8 read-write n 0x0 0xFFFFFFFF VEC62 DMA vector area 0x3E 8 read-write n 0x0 0xFFFFFFFF VEC63 DMA vector area 0x3F 8 read-write n 0x0 0xFFFFFFFF VEC7 DMA vector area 0x7 8 read-write n 0x0 0xFFFFFFFF VEC8 DMA vector area 0x8 8 read-write n 0x0 0xFFFFFFFF VEC9 DMA vector area 0x9 8 read-write n 0x0 0xFFFFFFFF ELC Event Link Controller ELC 0x40043400 0x0 0x100 registers n ELSELR00 Event output destination select register 00 0x0 -1 read-write n 0x0 0xF ELSELR01 Event output destination select register 01 0x1 -1 read-write n 0x0 0xFFFFFFFF ELSELR02 Event output destination select register 02 0x2 -1 read-write n 0x0 0xFFFFFFFF ELSELR03 Event output destination select register 03 0x3 -1 read-write n 0x0 0xFFFFFFFF ELSELR04 Event output destination select register 04 0x4 -1 read-write n 0x0 0xFFFFFFFF ELSELR05 Event output destination select register 05 0x5 -1 read-write n 0x0 0xFFFFFFFF ELSELR06 Event output destination select register 06 0x6 -1 read-write n 0x0 0xFFFFFFFF ELSELR07 Event output destination select register 07 0x7 -1 read-write n 0x0 0xFFFFFFFF ELSELR08 Event output destination select register 08 0x8 -1 read-write n 0x0 0xFFFFFFFF ELSELR09 Event output destination select register 09 0x9 -1 read-write n 0x0 0xFFFFFFFF ELSELR10 Event output destination select register 10 0xA -1 read-write n 0x0 0xFFFFFFFF ELSELR11 Event output destination select register 11 0xB -1 read-write n 0x0 0xFFFFFFFF ELSELR12 Event output destination select register 12 0xC -1 read-write n 0x0 0xFFFFFFFF ELSELR13 Event output destination select register 13 0xD -1 read-write n 0x0 0xFFFFFFFF ELSELR14 Event output destination select register 14 0xE -1 read-write n 0x0 0xFFFFFFFF EPWM Enhance PWM controller EPWM 0x40044400 0x0 0x100 registers n EPWMCTL EPWMO0n output control register 0x8 16 read-write n 0x0 0xFFFF IE00 EPWM0%s output inverted enable register 8 9 IE01 EPWM0%s output inverted enable register 9 9 IE02 EPWM0%s output inverted enable register 10 9 IE03 EPWM0%s output inverted enable register 11 9 IE04 EPWM0%s output inverted enable register 12 9 IE05 EPWM0%s output inverted enable register 13 9 IE06 EPWM0%s output inverted enable register 14 9 IE07 EPWM0%s output inverted enable register 15 9 OE00 EPWM0%s output enable register 0 1 OE01 EPWM0%s output enable register 1 1 OE02 EPWM0%s output enable register 2 1 OE03 EPWM0%s output enable register 3 1 OE04 EPWM0%s output enable register 4 1 OE05 EPWM0%s output enable register 5 1 OE06 EPWM0%s output enable register 6 1 OE07 EPWM0%s output enable register 7 1 EPWMSRC Input source select register 0x0 16 read-write n 0x0 0xFFFF SRC00 Selsect the source clock of EPWM0%s 0 1 SRC01 Selsect the source clock of EPWM0%s 1 1 SRC02 Selsect the source clock of EPWM0%s 2 1 SRC03 Selsect the source clock of EPWM0%s 3 1 SRC04 Selsect the source clock of EPWM0%s 4 1 SRC05 Selsect the source clock of EPWM0%s 5 1 SRC06 Selsect the source clock of EPWM0%s 6 1 SRC07 Selsect the source clock of EPWM0%s 7 1 EPWMSTC EPWMO0n cutoff control register 0x4 16 read-write n 0x0 0xFFFF HS_SEL Output forced cutoff release mode selection 3 4 IN_EG Output forced cutoff source edge/output forced cutoff release edge selection 2 3 REL_SEL Cutoff release timing select register 4 5 SC_SEL0 Cutoff source selection 0 1 SC_SEL1 Cutoff source selection 1 1 EPWMSTL EPWMO0n cutoff output level register 0xC 16 read-write n 0x0 0xFFFF IO00 EPWM00 output enable register 0 1 IO01 EPWM00 output enable register 1 1 IO10 EPWM01 output enable register 2 3 IO11 EPWM01 output enable register 3 3 IO20 EPWM02 output enable register 4 5 IO21 EPWM02 output enable register 5 5 IO30 EPWM03 output enable register 6 7 IO31 EPWM03 output enable register 7 7 IO40 EPWM04 output enable register 8 9 IO41 EPWM04 output enable register 9 9 IO50 EPWM05 output enable register 10 11 IO51 EPWM05 output enable register 11 11 IO60 EPWM06 output enable register 12 13 IO61 EPWM06 output enable register 13 13 IO70 EPWM07 output enable register 14 15 IO71 EPWM07 output enable register 15 15 EPWMSTR Status register 0x10 16 read-write n 0x0 0x3 HZCLR software release cutoff register 0 1 SHTFLG cutoff status register 1 2 FMC Flash Memory Controller FMC 0x40020000 0x0 0x400 registers n FMC Flash erase or write finish 31 FLCERCNT Flash chip erase control register 0x10 -1 read-write n 0x0 0x800001FF FLERMD Flash erase mode register 0xC -1 read-write n 0x0 0x18 FLERVCNT Flash erase recovery time (Trcv) control register 0x3C -1 read-write n 0x0 0x803FF81FF FLNVSCNT Flash address setup time (Tnvs) control register 0x18 -1 read-write n 0x0 0x800001FF FLOPMD1 Flash operation mode register 1 0x4 -1 read-write n 0x0 0xFF FLOPMD2 Flash operation mode register 2 0x8 -1 read-write n 0x0 0xFFFFFFFF FLPROCNT Flash program control register 0x1C -1 read-write n 0x0 0x81FF81FF FLPROT Flash protect control register 0x20 -1 read-write n 0x0 0xFF FLPRVCNT Flash program recovery time (Trcv) control register 0x38 -1 read-write n 0x0 0x800001FF FLSERCNT Flash sector erase control register 0x14 -1 read-write n 0x0 0x800001FF FLSTS Flash status register 0x0 -1 read-write n 0x0 0xFFFFFFFF EVF Flash hardware verification error flag 2 3 OVF Flash erase or write operaiton finish 0 1 IICA0 Serial Interface I2C with multimaster and wakeup supported IICA0 0x40041A30 0x0 0x200 registers n IICA0 IICA0 interrupt request 16 IICA0 IICA0 shift register 0x120 -1 read-write n 0x0 0xFF IICCTL00 IICA0 control register 0 0x0 -1 read-write n 0x0 0xFF ACKE Acknowledgment control 2 3 IICE I2C operation enable 7 8 LREL Exit from communications 6 7 SPIE Enable generation of interrupt request when stop condition is detected 4 5 SPT Stop condition trigger 0 1 STT Start condition trigger 1 2 WREL Wait cancellation 5 6 WTIM Control of wait and interrupt request generation 3 4 IICCTL01 IICA0 control register 1 0x1 -1 read-write n 0x0 0xBD CLD Detection of SCLAn pin level (valid only when IICEn = 1) 5 6 read-only DAD Detection of SDAAn pin level (valid only when IICEn = 1) 4 5 read-only DFC Digital filter operation control 2 3 read-write PRS Operation clock (fMCK) contro 0 1 read-write SMC Operation mode switching 3 4 read-write WUP Control of address match wakeup 7 8 read-write IICF0 IICA0 flag register 0x122 -1 read-write n 0x0 0xFF IICBSY I2C bus status flag 6 7 read-only IICRSV Communication reservation function disable bit 0 1 read-write STCEN Initial start enable trigger 1 2 read-write STCF STT clear flag 7 8 read-only IICS0 IICA0 status register 0x121 -1 read-only n 0x0 0xFF ACKD Detection of acknowledge (ACK) 2 3 ALD Detection of arbitration loss 6 7 COI Detection of matching addresses 4 5 EXC Detection of extension code reception 5 6 MSTS Master status check flag 7 8 SPD Detection of stop condition 0 1 STD Detection of start condition 1 2 TRC Detection of transmit/receive status 3 4 IICWH0 IICA0 high-level width setting register 0x3 -1 read-write n 0xFF 0xFF IICWL0 IICA0 low-level width setting register 0x2 -1 read-write n 0xFF 0xFF SVA0 Slave address register 0x4 -1 read-write n 0x0 0xFE IICA1 Serial Interface I2C with multimaster and wakeup supported IICA1 0x40042E30 0x0 0x200 registers n IICA1 IICA1 interrupt request 17 IICA1 IICA1 shift register 0x120 -1 read-write n 0x0 0xFF IICCTL10 IICA1 control register 0 0x0 -1 read-write n 0x0 0xFF ACKE Acknowledgment control 2 3 IICE I2C operation enable 7 8 LREL Exit from communications 6 7 SPIE Enable generation of interrupt request when stop condition is detected 4 5 SPT Stop condition trigger 0 1 STT Start condition trigger 1 2 WREL Wait cancellation 5 6 WTIM Control of wait and interrupt request generation 3 4 IICCTL11 IICA1 control register 1 0x1 -1 read-write n 0x0 0xBD CLD Detection of SCLAn pin level (valid only when IICEn = 1) 5 6 read-only DAD Detection of SDAAn pin level (valid only when IICEn = 1) 4 5 read-only DFC Digital filter operation control 2 3 read-write PRS Operation clock (fMCK) contro 0 1 read-write SMC Operation mode switching 3 4 read-write WUP Control of address match wakeup 7 8 read-write IICF1 IICA1 flag register 0x122 -1 read-write n 0x0 0xFF IICBSY I2C bus status flag 6 7 read-only IICRSV Communication reservation function disable bit 0 1 read-write STCEN Initial start enable trigger 1 2 read-write STCF STT clear flag 7 8 read-only IICS1 IICA1 status register 0x121 -1 read-only n 0x0 0xFF ACKD Detection of acknowledge (ACK) 2 3 ALD Detection of arbitration loss 6 7 COI Detection of matching addresses 4 5 EXC Detection of extension code reception 5 6 MSTS Master status check flag 7 8 SPD Detection of stop condition 0 1 STD Detection of start condition 1 2 TRC Detection of transmit/receive status 3 4 IICWH1 IICA1 high-level width setting register 0x3 -1 read-write n 0xFF 0xFF IICWL1 IICA1 low-level width setting register 0x2 -1 read-write n 0xFF 0xFF SVA1 Slave address register 0x4 -1 read-write n 0x0 0xFE INT Interrupt Controller INT 0x40006000 0x0 0x200 registers n IFH Interrupt flag register 0x1 8 read-write n 0x0 0x101 IFL Interrupt flag register 0x0 8 read-write n 0x0 0x101 MKH Interrupt mask register 0x1 8 read-write n 0xFFFFFFFF 0x101 MKL Interrupt mask register 0x0 8 read-write n 0xFFFFFFFF 0x101 INTM Pin input edge detection INTM 0x40045B38 0x0 0x100 registers n INTP0 INTP0 External interrupt request 1 INTP1 INTP1 External interrupt request 2 INTP2 INTP2 External interrupt request 3 INTP3 INTP3 External interrupt request 4 EGN0 External interrupt falling edge enable register 0x1 -1 read-write n 0x0 0xFF EGN0 0 1 EGN1 1 2 EGN2 2 3 EGN3 3 4 EGN4 4 5 EGN5 5 6 EGN6 6 7 EGN7 7 8 EGP0 External interrupt rising edge enable register 0x0 -1 read-write n 0x0 0xFF EGP0 0 1 EGP1 1 2 EGP2 2 3 EGP3 3 4 EGP4 4 5 EGP5 5 6 EGP6 6 7 EGP7 7 8 IRDA IrDA communication module based on Infrared Data Association stardard 1.0 IRDA 0x400440A0 0x0 0x1 registers n IRCR IrDA control register 0x0 -1 read-write n 0x0 0xFC IRCKS IrRxD clock selection 4 7 IRE IrRxD enable 7 8 IRRXINV IrRxD data polarity switching 2 3 IRTXINV IrRxD data polarity switching 3 4 KEY Key interrupt KEY 0x40044B30 0x0 0x10 registers n KEY KEY return interrupt request 24 KRM Key return mode register 0x7 -1 read-write n 0x0 0xFF LCDB LCD Bus Interface LCDB 0x40045400 0x0 0x100 registers n LBCTL LCD Bus Interface mode register 0x0 8 read-write n 0x0 0xFF BYF Data register busy flag 0 1 EL Control the level of signal E in mod68 mode 7 8 IMD Mode of external bus interface access selection 6 7 LBC Internal clock (SPCLK) selection 4 6 TCIS INTLCDB (DMA trigger) generation control bit 3 4 TPF Flag of transfer in progress on external bus interface 1 2 LBCYC LCB Bus Interface cycle control register 0x1 8 read-write n 0x0 0xFF LBDATA LCD Bus Interface data register 0x10 16 read-write n 0x0 0xFFFF LBDATAL SPI data register LBDATA 0x10 8 read-write n 0x0 0xFFFFFFFF LBDATAR LCD Bus Interface read data register 0x12 16 read-write n 0x0 0xFFFF LBDATARL LCD Bus Interface read data register LBDATAR 0x12 8 read-write n 0x0 0xFFFFFFFF LBWST LCB Bus Interface wait control register 0x2 8 read-write n 0x0 0xFF LVD Voltage detector LVD 0x40020440 0x0 0x100 registers n LVI Low Voltage detection interrupt 0 LVIM Voltage detection register 0x1 8 read-write n 0x0 0x83 LVIF Voltage detection flag 0 1 read-only GE Supply voltage (VDD) greater or equal to detection voltage (VLVD), or when LVD is off 0 LT Supply voltage (VDD) less than detection voltage (VLVD) 1 LVIOMSK Mask status flag of LVD output 1 2 read-only Invalid Mask of LVD output is invalid 0 Valid Mask of LVD output is valid 1 LVISEN Enable rewritting LVIS register 7 8 read-only Disable Disabling of rewriting the LVIS register 0 Enable Enabling of rewriting the LVIS register 1 LVIS Voltage detection level register 0x2 8 read-write n 0x0 0x81 LVILV LVD detection level 0 1 read-write High High-voltage detection level (VLVDH) 0 Low Low-voltage detection level (VLVDL or VLVD) 1 LVIMD Operation mode of voltage detection 7 8 read-write IRQ interrupt mode 0 Reset reset mode 1 MISC Miscellaneous function MISC 0x40040470 0x0 0x100 registers n ISC Input switch control register 0x3 -1 read-write n 0x0 0x83 ISC0 The input selection of INTP0 0 1 INTP0 Select INTP0 as the input of INTP0 0 RXD0 Select RXD0 as the input of INTP0 1 ISC1 The input selection of TI03 1 2 TI03 Select TI03 as the input of TI03 0 RXD0 Select RXD0 as the input of TI03 1 SSIE00 The slave select input (SS00) of SPI00 is valid 7 8 INVALID The slave select input (SS00) pin is invalid 0 VALID The slave select input (SS00) pin is valid 1 NFEN0 Noise filter enable register 0 0x0 -1 read-write n 0x0 0x15 SNFEN00 Enable noise filter of RxD0 0 1 SNFEN10 Enable noise filter of RxD1 2 3 SNFEN20 Enable noise filter of RxD2 4 5 NFEN1 Noise filter enable register 1 0x1 -1 read-write n 0x0 0xF TNFEN00 Enable noise filter of TI00 0 1 TNFEN01 Enable noise filter of TI01 1 2 TNFEN02 Enable noise filter of TI02 2 3 TNFEN03 Enable noise filter of TI03 3 4 NFEN2 Noise filter enable register 2 0x2 -1 read-write n 0x0 0xF TNFEN10 Enable noise filter of TI10 0 1 TNFEN11 Enable noise filter of TI11 1 2 TNFEN12 Enable noise filter of TI12 2 3 TNFEN13 Enable noise filter of TI13 3 4 TNFEN14 Enable noise filter of TI14 4 5 TNFEN15 Enable noise filter of TI15 5 6 TNFEN16 Enable noise filter of TI16 6 7 TNFEN17 Enable noise filter of TI17 7 8 RTCCL Real-time clock select register 0xC -1 read-write n 0x0 0xE3 TIOS0 Timer I/O select register 0 0x4 -1 read-write n 0x0 0x83 TIOS1 Timer I/O select register 1 0x5 -1 read-write n 0x0 0x1 PCBZ Clock/Buzzer output controller PCBZ 0x40040FA0 0x0 0x10 registers n CKS0 Clock output select registers 0 0x5 8 read-write n 0x0 0xFF CCS PCLBUZn output clock select 0 3 CSEL PCLBUZn output clock select 3 4 PCLOE PCLBUZn pin output enable 7 8 CKS1 Clock output select registers 1 0x6 -1 read-write n 0x0 0xFFFFFFFF PGA Programmable Gain Amplifier PGA 0x40043840 0x0 0x2000 registers n PGA0CTL PGA 0 control register 0x6 -1 read-write n 0x0 0x9F PGA0INHL PGA0IN and PGA0GNA input selection of the programmable gain amplifier 4 5 PGA0R1_N Differential or single-ended input selection of the programmable gain amplifier 3 4 PGAEN Programmable gain amplifier operation control 7 8 PGAVG Programmable gain amplifier amplification factor selection 0 3 PORT Port functions PORT 0x40040000 0x0 0x1000 registers n INTP0PCFG Alternate INTP pin configuration register 0x9E0 8 read-write n 0x0 0x7 CFG 0 3 PC00 PC00 used as INTP0 pin 0x00 PC01 PC01 used as INTP0 pin 0x01 PC02 PC02 used as INTP0 pin 0x02 PC03 PC03 used as INTP0 pin 0x03 PC04 PC04 used as INTP0 pin 0x04 PC05 PC05 used as INTP0 pin 0x05 PC06 PC06 used as INTP0 pin 0x06 PC07 PC07 used as INTP0 pin 0x07 INTP1PCFG Alternate INTP pin configuration register 0x9E1 8 read-write n 0x0 0x7 CFG 0 3 PC12 PC12 used as INTP1 pin 0x00 PC13 PC13 used as INTP1 pin 0x01 PC14 PC14 used as INTP1 pin 0x02 PC15 PC15 used as INTP1 pin 0x03 PC08 PC08 used as INTP1 pin 0x04 PC09 PC09 used as INTP1 pin 0x05 PC10 PC10 used as INTP1 pin 0x06 PC11 PC11 used as INTP1 pin 0x07 INTP2PCFG Alternate INTP pin configuration register 0x9E2 8 read-write n 0x0 0x7 CFG 0 3 PA00 PA00 used as INTP2 pin 0x00 PA01 PA01 used as INTP2 pin 0x01 PA02 PA02 used as INTP2 pin 0x02 PA03 PA03 used as INTP2 pin 0x03 PA11 PA11 used as INTP2 pin 0x04 PA12 PA12 used as INTP2 pin 0x05 PA13 PA13 used as INTP2 pin 0x06 PA14 PA14 used as INTP2 pin 0x07 INTP3PCFG Alternate INTP pin configuration register 0x9E3 8 read-write n 0x0 0x7 CFG 0 3 PA04 PA04 used as INTP3 pin 0x00 PA05 PA05 used as INTP3 pin 0x01 PA06 PA06 used as INTP3 pin 0x02 PA07 PA07 used as INTP3 pin 0x03 PA08 PA08 used as INTP3 pin 0x04 PA09 PA09 used as INTP3 pin 0x05 PA10 PA10 used as INTP3 pin 0x06 INTP4PCFG Alternate INTP pin configuration register 0x9E4 8 read-write n 0x0 0x7 CFG 0 3 PD00 PD00 used as INTP4 pin 0x00 PD01 PD01 used as INTP4 pin 0x01 PD12 PD12 used as INTP4 pin 0x02 PD13 PD13 used as INTP4 pin 0x03 PD14 PD14 used as INTP4 pin 0x04 PD15 PD15 used as INTP4 pin 0x05 PD02 PD02 used as INTP4 pin 0x06 PD03 PD03 used as INTP4 pin 0x07 INTP5PCFG Alternate INTP pin configuration register 0x9E5 8 read-write n 0x0 0x7 CFG 0 3 PD04 PD04 used as INTP5 pin 0x00 PD05 PD05 used as INTP5 pin 0x01 PD06 PD06 used as INTP5 pin 0x02 PD07 PD07 used as INTP5 pin 0x03 PD08 PD08 used as INTP5 pin 0x04 PD09 PD09 used as INTP5 pin 0x05 PD10 PD10 used as INTP5 pin 0x06 PD11 PD11 used as INTP5 pin 0x07 INTP6PCFG Alternate INTP pin configuration register 0x9E6 8 read-write n 0x0 0x7 CFG 0 3 PB00 PB00 used as INTP6 pin 0x00 PH04 PH04 used as INTP6 pin 0x01 PH03 PH03 used as INTP6 pin 0x02 PH02 PH02 used as INTP6 pin 0x03 PH01 PH01 used as INTP6 pin 0x04 PB01 PB01 used as INTP6 pin 0x05 PB02 PB02 used as INTP6 pin 0x06 INTP7PCFG Alternate INTP pin configuration register 0x9E7 8 read-write n 0x0 0x7 CFG 0 3 PB03 PB03 used as INTP7 pin 0x00 PB04 PB04 used as INTP7 pin 0x01 PB05 PB05 used as INTP7 pin 0x02 PB06 PB06 used as INTP7 pin 0x03 PB07 PB07 used as INTP7 pin 0x04 PB08 PB08 used as INTP7 pin 0x05 IRRXDPCFG RXD1PCFG 0x9A4 8 read-write n 0x0 0xFFFFFFFF PA Port register A 0x0 16 read-write n 0x0 0x7FFF PA00CFG 0x90B -1 read-write n 0x0 0xFFFFFFFF PA01CFG 0x90C -1 read-write n 0x0 0xFFFFFFFF PA02CFG 0x90D -1 read-write n 0x0 0xFFFFFFFF PA03CFG 0x90E -1 read-write n 0x0 0xFFFFFFFF PA04CFG 0x927 -1 read-write n 0x0 0xFFFFFFFF PA05CFG 0x928 -1 read-write n 0x0 0xFFFFFFFF PA06CFG 0x929 -1 read-write n 0x0 0xFFFFFFFF PA07CFG 0x92A -1 read-write n 0x0 0xFFFFFFFF PA08CFG 0x92B -1 read-write n 0x0 0xFFFFFFFF PA09CFG 0x92C -1 read-write n 0x0 0xFFFFFFFF PA10CFG 0x92D -1 read-write n 0x0 0xFFFFFFFF PA11CFG 0x94B -1 read-write n 0x0 0xFFFFFFFF PA12CFG 0x94C -1 read-write n 0x0 0xFFFFFFFF PA13CFG 0x94D -1 read-write n 0x0 0xFFFFFFFF PA14CFG 0x94E -1 read-write n 0x0 0xFFFFFFFF PB Port register B 0x2 16 read-write n 0x0 0x1FF PB00CFG Alterate Output Function configuration register 0x900 8 read-write n 0x0 0xF CFG Alterate Output Function configuration register 0 4 GPIO Port used as GPIO 0x00 TO00 Port used as TO00 0x01 TO01 Port used as TO01 0x02 TO02 Port used as TO02 0x03 TO03 Port used as TO03 0x04 SDO00/TxD0 Port used as SDO00/TxD0 0x05 PB01CFG Alterate Output Function configuration register 0x940 8 read-write n 0x0 0xF CFG Alterate Output Function configuration register 0 4 GPIO Port used as GPIO 0x00 TO14 Port used as TO14 0x01 TO15 Port used as TO15 0x02 TO16 Port used as TO16 0x03 TO17 Port used as TO17 0x04 SDO10/TxD1 Port used as SDO20/TxD2 0x05 CLKBUZ1 Port used as CLKBUZ1 0x06 PB02CFG 0x941 -1 read-write n 0x0 0xFFFFFFFF PB03CFG 0x942 -1 read-write n 0x0 0xFFFFFFFF PB04CFG 0x943 -1 read-write n 0x0 0xFFFFFFFF PB05CFG 0x944 -1 read-write n 0x0 0xFFFFFFFF PB06CFG 0x945 -1 read-write n 0x0 0xFFFFFFFF PB07CFG 0x946 -1 read-write n 0x0 0xFFFFFFFF PB08CFG 0x947 -1 read-write n 0x0 0xFFFFFFFF PC Port register C 0x4 16 read-write n 0x0 0xFFFF PC00CFG 0x948 -1 read-write n 0x0 0xFFFFFFFF PC01CFG 0x949 -1 read-write n 0x0 0xFFFFFFFF PC02CFG 0x94A -1 read-write n 0x0 0xFFFFFFFF PC03CFG Alterate Output Function configuration register 0x920 8 read-write n 0x0 0xF CFG Alterate Output Function configuration register 0 4 GPIO Port used as GPIO 0x00 TO10 Port used as TO10 0x01 TO11 Port used as TO11 0x02 TO12 Port used as TO12 0x03 TO13 Port used as TO13 0x04 SDO10/TxD1 Port used as SDO10/TxD1 0x05 SPIHS0_SCKO Port used as SPIHS0_SCKO 0x06 SPIHS0_MO Port used as SPIHS0_MO 0x07 SPIHS0_SO Port used as SPIHS0_SO 0x08 PC04CFG 0x921 -1 read-write n 0x0 0xFFFFFFFF PC05CFG 0x922 -1 read-write n 0x0 0xFFFFFFFF PC06CFG 0x923 -1 read-write n 0x0 0xFFFFFFFF PC07CFG 0x924 -1 read-write n 0x0 0xFFFFFFFF PC08CFG 0x907 -1 read-write n 0x0 0xFFFFFFFF PC09CFG 0x908 -1 read-write n 0x0 0xFFFFFFFF PC10CFG 0x909 -1 read-write n 0x0 0xFFFFFFFF PC11CFG 0x90A -1 read-write n 0x0 0xFFFFFFFF PC12CFG 0x925 -1 read-write n 0x0 0xFFFFFFFF PC13CFG 0x926 -1 read-write n 0x0 0xFFFFFFFF PC14CFG 0x905 -1 read-write n 0x0 0xFFFFFFFF PC15CFG 0x906 -1 read-write n 0x0 0xFFFFFFFF PCLRA Port clear register A 0x70 16 read-write n 0x0 0x7FFF PCLRB Port clear register B 0x72 16 read-write n 0x0 0x1FF PCLRC Port clear register C 0x74 16 read-write n 0x0 0xFFFF PCLRD Port clear register D 0x76 16 read-write n 0x0 0xFFFF PCLRH Port clear register H 0x7E 16 read-write n 0x0 0x1E PD Port register D 0x6 16 read-write n 0x0 0xFFFF PD00CFG 0x92E -1 read-write n 0x0 0xFFFFFFFF PD01CFG 0x92F -1 read-write n 0x0 0xFFFFFFFF PD02CFG 0x94F -1 read-write n 0x0 0xFFFFFFFF PD03CFG 0x950 -1 read-write n 0x0 0xFFFFFFFF PD04CFG 0x951 -1 read-write n 0x0 0xFFFFFFFF PD05CFG 0x952 -1 read-write n 0x0 0xFFFFFFFF PD06CFG 0x953 -1 read-write n 0x0 0xFFFFFFFF PD07CFG 0x90F -1 read-write n 0x0 0xFFFFFFFF PD08CFG 0x910 -1 read-write n 0x0 0xFFFFFFFF PD09CFG 0x911 -1 read-write n 0x0 0xFFFFFFFF PD10CFG 0x912 -1 read-write n 0x0 0xFFFFFFFF PD11CFG 0x913 -1 read-write n 0x0 0xFFFFFFFF PD12CFG 0x930 -1 read-write n 0x0 0xFFFFFFFF PD13CFG 0x931 -1 read-write n 0x0 0xFFFFFFFF PD14CFG 0x932 -1 read-write n 0x0 0xFFFFFFFF PD15CFG 0x933 -1 read-write n 0x0 0xFFFFFFFF PDA Pull-down resistor option register A 0x30 16 read-write n 0x0 0x7E7F PDB Pull-down resistor option register B 0x32 16 read-write n 0x0 0x1FF PDC Pull-down resistor option register C 0x34 16 read-write n 0x0 0xFFFF PDD Pull-down resistor option register D 0x36 16 read-write n 0x0 0xFFFF PH Port register H 0xE 16 read-write n 0x0 0x1F PH01CFG 0x904 -1 read-write n 0x0 0xFFFFFFFF PH02CFG 0x903 -1 read-write n 0x0 0xFFFFFFFF PH03CFG 0x902 -1 read-write n 0x0 0xFFFFFFFF PH04CFG 0x901 -1 read-write n 0x0 0xFFFFFFFF PMA Port mode register A 0x10 16 read-write n 0xFFFF 0x7FFF PMB Port mode register B 0x12 16 read-write n 0xFFFF 0x1FF PMC Port mode register C 0x14 16 read-write n 0xFFFF 0xFFFF PMCA Port mode control register A 0x50 16 read-write n 0xFFFF 0x787F PMCB Port mode control register B 0x52 16 read-write n 0xFFF7 0x1DE PMCC Port mode control register C 0x54 16 read-write n 0xFFFF 0xFFF PMCD Port mode control register D 0x56 16 read-write n 0xFFFF 0x1F0 PMD Port mode register D 0x16 16 read-write n 0xFFFF 0xFFFF PMH Port mode register H 0x1E 16 read-write n 0xFFFF 0x1E POMA Port output mode register A 0x40 16 read-write n 0x0 0x7FFF POMB Port output mode register B 0x42 16 read-write n 0x0 0x1FF POMC Port output mode register C 0x44 16 read-write n 0x0 0xFFFF POMD Port output mode register D 0x46 16 read-write n 0x0 0xFFFF POMH Port output mode register H 0x4E 16 read-write n 0x0 0x1E PREADA Port read register A 0x80 16 read-write n 0x0 0x7FFF PREADB Port read register B 0x82 16 read-write n 0x0 0x1FF PREADC Port read register C 0x84 16 read-write n 0x0 0xFFFF PREADD Port read register D 0x86 16 read-write n 0x0 0xFFFF PREADH Port read register H 0x8E 16 read-write n 0x0 0x1F PSETA Port set register A 0x60 16 read-write n 0x0 0x7FFF PSETB Port set register B 0x62 16 read-write n 0x0 0xFFFF PSETC Port set register C 0x64 16 read-write n 0x0 0xFFFF PSETD Port set register D 0x66 16 read-write n 0x0 0xFFFF PSETH Port set register H 0x6E 16 read-write n 0x0 0x1E PUA Pull-up resistor option register A 0x20 16 read-write n 0x400 0x7C7F PUB Pull-up resistor option register B 0x22 16 read-write n 0x8 0x1FF PUC Pull-up resistor option register C 0x24 16 read-write n 0x0 0xFFFF PUD Pull-up resistor option register D 0x26 16 read-write n 0x1 0xFFFF PUH Pull-up resistor option register H 0x2E 16 read-write n 0x3 0x7 RXD0PCFG 0x984 8 read-write n 0x0 0xFFFFFFFF RXD1PCFG 0x9A4 -1 read-write n 0x0 0xFFFFFFFF RXD2PCFG 0x9C4 -1 read-write n 0x0 0xFFFFFFFF SCLA0PCFG 0x985 -1 read-write n 0x0 0xFFFFFFFF SCLA1PCFG 0x9C6 -1 read-write n 0x0 0xFFFFFFFF SDAA0PCFG 0x986 -1 read-write n 0x0 0xFFFFFFFF SDAA1PCFG 0x9C7 -1 read-write n 0x0 0xFFFFFFFF SDI00PCFG RXD0PCFG 0x984 8 read-write n 0x0 0xFFFFFFFF SDI10PCFG RXD1PCFG 0x9A4 8 read-write n 0x0 0xFFFFFFFF SDI20PCFG RXD2PCFG 0x9C4 8 read-write n 0x0 0xFFFFFFFF SPIHS0_MIPCFG 0x9A7 -1 read-write n 0x0 0xFFFFFFFF SPIHS0_SCKIPCFG 0x9A5 -1 read-write n 0x0 0xFFFFFFFF SPIHS0_SIPCFG 0x9A6 -1 read-write n 0x0 0xFFFFFFFF SPIHS1_NSSPCFG 0x9C5 -1 read-write n 0x0 0xFFFFFFFF TI00PCFG Alternate function pin configuration register 0x980 8 read-write n 0x0 0x1F CFG Alternate function pin configuration register 0 6 PB00 PB00 used as peripheral function pin 0x01 PH04 PH04 used as peripheral function pin 0x02 PH03 PH03 used as peripheral function pin 0x03 PH02 PH02 used as peripheral function pin 0x04 PH01 PH01 used as peripheral function pin 0x05 PC14 PC14 used as peripheral function pin 0x06 PC15 PC15 used as peripheral function pin 0x07 PC08 PC08 used as peripheral function pin 0x08 PC09 PC09 used as peripheral function pin 0x09 PC10 PC10 used as peripheral function pin 0x0A PC11 PC11 used as peripheral function pin 0x0B PA00 PA00 used as peripheral function pin 0x0C PA01 PA01 used as peripheral function pin 0x0D PA02 PA02 used as peripheral function pin 0x0E PA03 PA03 used as peripheral function pin 0x0F PD07 PD07 used as peripheral function pin 0x10 PD08 PD08 used as peripheral function pin 0x11 PD09 PD09 used as peripheral function pin 0x12 PD10 PD10 used as peripheral function pin 0x13 PD11 PD11 used as peripheral function pin 0x14 TI01PCFG 0x981 -1 read-write n 0x0 0xFFFFFFFF TI02PCFG 0x982 -1 read-write n 0x0 0xFFFFFFFF TI03PCFG 0x983 -1 read-write n 0x0 0xFFFFFFFF TI10PCFG Alternate function pin configuration register 0x9A0 8 read-write n 0x0 0x1F CFG 0 6 PC03 PC03 used as peripheral function pin 0x01 PC04 PC04 used as peripheral function pin 0x02 PC05 PC05 used as peripheral function pin 0x03 PC06 PC06 used as peripheral function pin 0x04 PC07 PC07 used as peripheral function pin 0x05 PC12 PC12 used as peripheral function pin 0x06 PC13 PC13 used as peripheral function pin 0x07 PA04 PA04 used as peripheral function pin 0x08 PA05 PA05 used as peripheral function pin 0x09 PA06 PA06 used as peripheral function pin 0x0A PA07 PA07 used as peripheral function pin 0x0B PA08 PA08 used as peripheral function pin 0x0C PA09 PA09 used as peripheral function pin 0x0D PA10 PA10 used as peripheral function pin 0x0E PD00 PD00 used as peripheral function pin 0x0F PD01 PD01 used as peripheral function pin 0x10 PD12 PD12 used as peripheral function pin 0x11 PD13 PD13 used as peripheral function pin 0x12 PD14 PD14 used as peripheral function pin 0x13 PD15 PD15 used as peripheral function pin 0x14 TI11PCFG 0x9A1 -1 read-write n 0x0 0xFFFFFFFF TI12PCFG 0x9A2 -1 read-write n 0x0 0xFFFFFFFF TI13PCFG 0x9A3 -1 read-write n 0x0 0xFFFFFFFF TI14PCFG Alternate function pin configuration register 0x9C0 8 read-write n 0x0 0x1F CFG 0 6 PB01 PB01 used as peripheral function pin 0x01 PB02 PB02 used as peripheral function pin 0x02 PB03 PB03 used as peripheral function pin 0x03 PB04 PB04 used as peripheral function pin 0x04 PB05 PB05 used as peripheral function pin 0x05 PB06 PB06 used as peripheral function pin 0x06 PB07 PB07 used as peripheral function pin 0x07 PB08 PB08 used as peripheral function pin 0x08 PC00 PC00 used as peripheral function pin 0x09 PC01 PC01 used as peripheral function pin 0x0A PC02 PC02 used as peripheral function pin 0x0B PA11 PA11 used as peripheral function pin 0x0C PA12 PA12 used as peripheral function pin 0x0D PA13 PA13 used as peripheral function pin 0x0E PA14 PA14 used as peripheral function pin 0x0F PD02 PD02 used as peripheral function pin 0x10 PD03 PD03 used as peripheral function pin 0x11 PD04 PD04 used as peripheral function pin 0x12 PD05 PD05 used as peripheral function pin 0x13 PD06 PD06 used as peripheral function pin 0x14 TI15PCFG 0x9C1 -1 read-write n 0x0 0xFFFFFFFF TI16PCFG 0x9C2 -1 read-write n 0x0 0xFFFFFFFF TI17PCFG 0x9C3 -1 read-write n 0x0 0xFFFFFFFF USBPMR USB port configuration register 0x47D 8 read-write n 0x3 0x3 DMPMR USB_DP and USB_DM pin function select 0 2 read-write GPIO PA07 and PA08 did not use as USB pins 0 USB PA07 used as USB_DP and PA08 used as USB_DM 3 USBPRCR USB port configuration protect register 0x47E 8 read-write n 0x0 0xFF QSPI QSPI communication module QSPI 0x64000000 0x0 0x1000 registers n SFMCMD Communication Mode Control Register 0x14 32 read-write n 0x0 0x1 DCOM Mode select for communication with the SPI bus 0 1 SFMCNT1 External QSPI Address Register 0x804 32 read-write n 0x0 0xFC000000 QSPI_EXT Bank switching address 26 32 SFMCOM Communication Port Register 0x10 32 read-write n 0x0 0xF SFMD Port for direct communication with the SPI bus 0 8 SFMCST Communication Status Register 0x18 32 read-write n 0x0 0x81 COMBSY SPI bus cycle completion state in direct communication 0 1 read-only EROMR ROM access detection status in direct communication mode 8 9 SFMPMD Port Control Register 0x34 32 read-write n 0x0 0x4 SFMWPL WP pin specification 2 3 SFMSAC Address Mode Control Register 0x24 32 read-write n 0x0 0x11 SFM4BC Default instruction code select 4 5 SFMAS Number of address bytes select for the serial interface 0 1 SFMSDC Dummy Cycle Control Register 0x28 32 read-write n 0x0 0xFFCF SFMDN Number of dummy cycles select for Fast Read instructions 0 4 SFMXD Mode data for serial flash (control XIP mode) 8 16 SFMXEN XIP mode permission 7 8 SFMXST XIP mode status 6 7 read-only SFMSIC Instruction Code Register 0x20 32 read-write n 0x0 0xF SFMCIC Serial flash instruction code to substitute 0 8 SFMSKC Clock Control Register 0x8 32 read-write n 0x0 0x3F SFMDTY Duty ratio correction function select for the QSPCLK signal 5 6 SFMDV Serial interface reference cycle select 0 5 SFMSMD Transfer Mode Control Register 0x0 32 read-write n 0x0 0x1FF7 SFMCCE Read instruction code select 15 16 SFMMD3 SPI mode select. An initial value is determined by input to CFGMD3 8 9 SFMOEX Extension select for the I/O buffer output enable signal for the serial interface 9 10 SFMOHW Hold time adjustment for serial transmission 10 11 SFMOSW Setup time adjustment for serial transmission 11 12 SFMPAE Function select for stopping prefetch at locations other than on byte boundaries 7 8 SFMPFE Prefetch function select 6 7 SFMRM Serial interface read mode select 0 3 SFMSE QSSL extension function select after SPI bus access 4 6 SFMSPC SPI Protocol Control Register 0x30 32 read-write n 0x0 0x13 SFMSDE Minimum time select for input output switch 4 5 SFMSPI SPI protocol select 0 2 SFMSSC Chip Selection Control Register 0x4 32 read-write n 0x0 0x1F SFMSHD QSSL signal release timing select 4 5 SFMSLD QSSL signal output timing select 5 6 SFMSW Minimum high-level width select for QSSL signal 0 4 SFMSST Status Register 0xC 32 read-only n 0x0 0xDF PFCNT Number of bytes of prefetched data 0 5 PFFUL Prefetch buffer state 6 7 PFOFF Prefetch function operation state 7 8 RST Reset Function RST 0x40020420 0x0 0x40 registers n RESF Reset flag register 0x20 8 read-only n 0x0 0x97 IAWRF Internal reset request by illegal-memory access 1 2 clear NONE Internal reset request is not generated, or the RESF register is cleared. 0 DONE Internal reset request is generated. 1 LVIRF Internal reset request by voltage detector 0 1 clear NONE Internal reset request is not generated, or the RESF register is cleared. 0 DONE Internal reset request is generated. 1 RPERF Internal reset request by RAM parity 2 3 clear NONE Internal reset request is not generated, or the RESF register is cleared. 0 DONE Internal reset request is generated. 1 SYSRF Internal reset request by system reset request(AIRCR.SYSRESETREQ) 7 8 clear NONE Internal reset request is not generated, or the RESF register is cleared. 0 DONE Internal reset request is generated. 1 WDTRF Internal reset request by watchdog timer(WDT) 4 5 clear NONE Internal reset request is not generated, or the RESF register is cleared. 0 DONE Internal reset request is generated. 1 RTC Real-Time clock RTC 0x40044F00 0x0 0x100 registers n RTC Real-Time Clock interrupt request 23 ALARMWH Alarm hour register 0x5B 8 read-write n 0x12 0x3F ALARMWM Alarm minute register 0x5A 8 read-write n 0x0 0x7F ALARMWW Alarm week register 0x5C 8 read-write n 0x0 0x3F DAY Day count register 0x56 8 read-write n 0x1 0x3F HOUR Hour count register 0x54 8 read-write n 0x12 0x3F ITMC 15-bit interval timer control register 0x50 16 read-write n 0x7FFF 0xFFFF ITCMP 15-bit interval timer compare value 0 15 RINTE 15-bit interval timer operation control 15 16 MIN Minute count register 0x53 8 read-write n 0x0 0x7F MONTH Month count register 0x57 8 read-write n 0x1 0x1F RTCC0 Real-time clock control register 0 0x5D 8 read-write n 0x0 0xAF AMPM Selection of 12-/24-hour system 3 4 CT Constant-period interrupt (INTRTC) selection 0 3 RCLOE RTC1HZ pin output enable 5 6 RTCE Real-time clock operation control 7 8 RTCC1 Real-time clock control register 1 0x5E 8 read-write n 0x0 0xDB RIFG Constant-period interrupt status flag 3 4 RWAIT Wait control of real-time clock 0 1 RWST Wait status flag of real-time clock 1 2 WAFG Alarm detection status flag 4 5 WALE Alarm operation control 7 8 WALIE Control of alarm interrupt (INTRTC) function operation 6 7 SEC Second count register 0x52 8 read-write n 0x0 0x7F SUBCUD Watch error correction register 0x34 16 read-write n 0x0 0xFFFF DEV watch error correction timing 15 16 F watch error correction value 0 13 WEEK Week count register 0x55 8 read-write n 0x0 0x7 YEAR Year count register 0x58 8 read-write n 0x0 0xFF SAF Flash memory CRC operation function (High-Speed CRC) SAF 0x40020100 0x0 0x30000 registers n CRC0CTL Flash memory CRC control register 0x1710 8 read-write n 0x0 0xFF CRC0EN Control of high-speed CRC operation 7 8 FEA High-speed CRC operation range 0 7 CRCD CRC data register 0x231FA 16 read-write n 0x0 0xFF CRCIN CRC input register 0x232AC 8 read-write n 0x0 0xFF PGCRCL Flash memory CRC operation result register 0x1712 16 read-write n 0x0 0xFFFF RPECTL RAM parity error control register 0x325 8 read-write n 0x0 0x81 RPEF Parity error status flag 0 1 read-write NoError No parity error has occurred 0 Error Parity error has occurred 1 RPERDIS Disable RAM parity error reset 7 8 read-write Enable Enable parity error reset 0 Disable Disable parity error reset 1 SFRGD SFR guard control register 0x20378 -1 read-write n 0x0 0xF SCI0 Serial Communication Interface 0 with UART, SPI and simplified I2C supported SCI0 0x40041000 0x0 0x200 registers n ST0 UART0 transmission transfer end or buffer empty 7 SR0 UART0 rerception transfer 8 SRE0 UART0 rerception communication error occurrence 9 RXD0 UART receive data register SDR01 0x112 8 read-write n 0x0 0xFFFFFFFF SCR00 Serial communication operation setting register mn 0xC -1 read-write n 0x87 0xF7BF CKP Selection of clock phase in SPI mode 12 13 DAP Selection of data phase in SPI mode 13 14 DIR Selection of data transfer sequence in SPI and UART modes 7 8 DLS Setting of data length in SPI and UART modes 0 4 EOC Mask control of error interrupt signal (INTSREx (x = 0 to 2)) 10 11 PTC Setting of parity bit in UART mode 8 10 RXE Reception enable 14 15 SLC Setting of stop bit in UART mode 4 6 TXE Transmission enable 15 16 SCR01 Serial communication operation setting register mn 0xE -1 read-write n 0x0 0xFFFFFFFF SDR00 Serial data register 0%s 0x110 -1 read-write n 0x0 0xFFFF SDR01 Serial data register 0%s 0x112 -1 read-write n 0x0 0xFFFF SE0 Serial channel enable status register m 0x10 -1 read-only n 0x0 0x3 SE00 Indication of operation enable/stop status of channel 0 0 1 SE01 Indication of operation enable/stop status of channel 1 1 2 SIO00 SPI data register SDR00 0x110 8 read-write n 0x0 0xFFFFFFFF SIO01 SPI data register SDR01 0x112 8 read-write n 0x0 0xFFFFFFFF SIR00 Serial flag clear trigger register mn 0x4 -1 read-write n 0x0 0x7 FECT Clear trigger of framing error flag of channel n 2 3 OVCT Clear trigger of overrun error flag of channel n 0 1 PECT Clear trigger of parity error flag of channel n 1 2 SIR01 Serial flag clear trigger register mn 0x6 -1 read-write n 0x0 0xFFFFFFFF SMR00 Serial mode register mn 0x8 -1 read-write n 0x20 0xC147 CCS Selection of transfer clock (fTCLK) of channel n 14 15 CKS Selection of operation clock (fMCK) of channel n 15 16 MD Setting of operation mode of channel n 0 3 SIS Controls inversion of level of receive data of channel n in UART mode 6 7 STS Selection of start trigger source 8 9 SMR01 Serial mode register mn 0xA -1 read-write n 0x0 0xFFFFFFFF SO0 Serial output register 0 0x18 -1 read-write n 0xF0F 0xF0F CKO00 Serial clock output of channel 0 8 9 CKO01 Serial clock output of channel 1 9 10 SO00 Serial data output of channel 0 0 1 SO01 Serial data output of channel 1 1 2 SOE0 Serial output enable register 0 0x1A -1 read-write n 0x0 0x3 SOE00 Serial output enable of channel 0 0 1 SOE01 Serial output enable of channel 1 1 2 SOL0 Serial output level register 0 0x20 -1 read-write n 0x0 0x1 SOL00 Selects inversion of the level of the transmit data of channel n in UART mode 0 1 SPS0 Serial clock select register 0 0x16 -1 read-write n 0x0 0xFF PRS00 Prescaler 0 0 4 PRS01 Prescaler 1 4 8 SS0 Serial channel start register 0 0x12 -1 read-write n 0x0 0x3 SS00 Operation start trigger of channel 0 0 1 SS01 Operation start trigger of channel 1 1 2 SSR00 Serial status register mn 0x0 -1 read-only n 0x0 0x67 BFF Buffer register status indication flag of channel n 5 6 FEF Framing error detection flag of channel n 2 3 OVF Overrun error detection flag of channel n 0 1 PEF Parity error detection flag of channel n 1 2 TSF Communication status indication flag of channel n 6 7 SSR01 Serial status register mn 0x2 -1 read-write n 0x0 0xFFFFFFFF ST0 Serial channel stop register 0 0x14 -1 read-write n 0x0 0x3 ST00 Operation stop trigger of channel 0 0 1 ST01 Operation stop trigger of channel 1 1 2 TXD0 UART transmit data register SDR00 0x110 8 read-write n 0x0 0xFFFFFFFF SCI1 Serial Communication Interface 1 with UART, SPI and simplified I2C supported SCI1 0x40041200 0x0 0x200 registers n ST1 UART1 transmission transfer end or buffer empty 10 SR1 UART1 rerception transfer 11 SRE1 UART1 rerception communication error occurrence 12 RXD1 UART receive data register SDR11 0x112 8 read-write n 0x0 0xFFFFFFFF SCR10 Serial communication operation setting register mn 0xC -1 read-write n 0x87 0xF7BF CKP Selection of clock phase in SPI mode 12 13 DAP Selection of data phase in SPI mode 13 14 DIR Selection of data transfer sequence in SPI and UART modes 7 8 DLS Setting of data length in SPI and UART modes 0 2 EOC Mask control of error interrupt signal (INTSREx (x = 0 to 2)) 10 11 PTC Setting of parity bit in UART mode 8 10 RXE Reception enable 14 15 SLC Setting of stop bit in UART mode 4 6 TXE Transmission enable 15 16 SCR11 Serial communication operation setting register mn 0xE -1 read-write n 0x0 0xFFFFFFFF SDR10 Serial data register 1%s 0x110 -1 read-write n 0x0 0xFFFF SDR11 Serial data register 1%s 0x112 -1 read-write n 0x0 0xFFFF SE1 Serial channel enable status register 1 0x10 -1 read-only n 0x0 0x3 SE10 Indication of operation enable/stop status of channel 0 0 1 SE11 Indication of operation enable/stop status of channel 1 1 2 SIO10 SPI data register SDR10 0x110 8 read-write n 0x0 0xFFFFFFFF SIO11 SPI data register SDR11 0x112 8 read-write n 0x0 0xFFFFFFFF SIR10 Serial flag clear trigger register mn 0x4 -1 read-write n 0x0 0x7 FECT Clear trigger of framing error flag of channel n 2 3 OVCT Clear trigger of overrun error flag of channel n 0 1 PECT Clear trigger of parity error flag of channel n 1 2 SIR11 Serial flag clear trigger register mn 0x6 -1 read-write n 0x0 0xFFFFFFFF SMR10 Serial mode register mn 0x8 -1 read-write n 0x20 0xC147 CCS Selection of transfer clock (fTCLK) of channel n 14 15 CKS Selection of operation clock (fMCK) of channel n 15 16 MD Setting of operation mode of channel n 0 3 SIS Controls inversion of level of receive data of channel n in UART mode 6 7 STS Selection of start trigger source 8 9 SMR11 Serial mode register mn 0xA -1 read-write n 0x0 0xFFFFFFFF SO1 Serial output register 1 0x18 -1 read-write n 0xF0F 0xF0F CKO10 Serial clock output of channel 0 8 9 CKO11 Serial clock output of channel 1 9 10 SO10 Serial data output of channel 0 0 1 SO11 Serial data output of channel 1 1 2 SOE1 Serial output enable register 1 0x1A -1 read-write n 0x0 0x3 SOE10 Serial output enable of channel 0 0 1 SOE11 Serial output enable of channel 1 1 2 SOL1 Serial output level register 1 0x20 -1 read-write n 0x0 0x1 SOL10 Selects inversion of the level of the transmit data of channel n in UART mode 0 1 SPS1 Serial clock select register 1 0x16 -1 read-write n 0x0 0xFF PRS10 Prescaler 0 0 4 PRS11 Prescaler 1 4 8 SS1 Serial channel start register 1 0x12 -1 read-write n 0x0 0x3 SS10 Operation start trigger of channel 0 0 1 SS11 Operation start trigger of channel 1 1 2 SSR10 Serial status register mn 0x0 -1 read-only n 0x0 0x67 BFF Buffer register status indication flag of channel n 5 6 FEF Framing error detection flag of channel n 2 3 OVF Overrun error detection flag of channel n 0 1 PEF Parity error detection flag of channel n 1 2 TSF Communication status indication flag of channel n 6 7 SSR11 Serial status register mn 0x2 -1 read-write n 0x0 0xFFFFFFFF ST1 Serial channel stop register 1 0x14 -1 read-write n 0x0 0x3 ST10 Operation stop trigger of channel 0 0 1 ST11 Operation stop trigger of channel 1 1 2 TXD1 UART transmit data register SDR10 0x110 8 read-write n 0x0 0xFFFFFFFF SCI2 Serial Communication Interface 2 with UART, SPI and simplified I2C supported SCI1 0x40041400 0x0 0x200 registers n ST2 UART2 transmission transfer end or buffer empty 13 SR2 UART2 rerception transfer 14 SRE2 UART2 rerception communication error occurrence 15 RXD2 UART receive data register SDR21 0x112 8 read-write n 0x0 0xFFFFFFFF SCR20 Serial communication operation setting register mn 0xC -1 read-write n 0x87 0xF7BF CKP Selection of clock phase in SPI mode 12 13 DAP Selection of data phase in SPI mode 13 14 DIR Selection of data transfer sequence in SPI and UART modes 7 8 DLS Setting of data length in SPI and UART modes 0 2 EOC Mask control of error interrupt signal (INTSREx (x = 0 to 2)) 10 11 PTC Setting of parity bit in UART mode 8 10 RXE Reception enable 14 15 SLC Setting of stop bit in UART mode 4 6 TXE Transmission enable 15 16 SCR21 Serial communication operation setting register mn 0xE -1 read-write n 0x0 0xFFFFFFFF SDR20 Serial data register 2%s 0x110 -1 read-write n 0x0 0xFFFF SDR21 Serial data register 2%s 0x112 -1 read-write n 0x0 0xFFFF SE2 Serial channel enable status register 2 0x10 -1 read-only n 0x0 0x3 SE20 Indication of operation enable/stop status of channel 0 0 1 SE21 Indication of operation enable/stop status of channel 1 1 2 SIO20 SPI data register SDR20 0x110 8 read-write n 0x0 0xFFFFFFFF SIO21 SPI data register SDR21 0x112 8 read-write n 0x0 0xFFFFFFFF SIR20 Serial flag clear trigger register mn 0x4 -1 read-write n 0x0 0x7 FECT Clear trigger of framing error flag of channel n 2 3 OVCT Clear trigger of overrun error flag of channel n 0 1 PECT Clear trigger of parity error flag of channel n 1 2 SIR21 Serial flag clear trigger register mn 0x6 -1 read-write n 0x0 0xFFFFFFFF SMR20 Serial mode register mn 0x8 -1 read-write n 0x20 0xC147 CCS Selection of transfer clock (fTCLK) of channel n 14 15 CKS Selection of operation clock (fMCK) of channel n 15 16 MD Setting of operation mode of channel n 0 3 SIS Controls inversion of level of receive data of channel n in UART mode 6 7 STS Selection of start trigger source 8 9 SMR21 Serial mode register mn 0xA -1 read-write n 0x0 0xFFFFFFFF SO2 Serial output register 0 0x18 -1 read-write n 0xF0F 0xF0F CKO11 Serial clock output of channel 1 9 10 CKO20 Serial clock output of channel 0 8 9 SO20 Serial data output of channel 0 0 1 SO21 Serial data output of channel 1 1 2 SOE2 Serial output enable register 2 0x1A -1 read-write n 0x0 0x3 SOE20 Serial output enable of channel 0 0 1 SOE21 Serial output enable of channel 1 1 2 SOL2 Serial output level register 2 0x20 -1 read-write n 0x0 0x1 SOL20 Selects inversion of the level of the transmit data of channel n in UART mode 0 1 SPS2 Serial clock select register 0 0x16 -1 read-write n 0x0 0xFF PRS20 Prescaler 0 0 4 PRS21 Prescaler 1 4 8 SS2 Serial channel start register 2 0x12 -1 read-write n 0x0 0x3 SS20 Operation start trigger of channel 0 0 1 SS21 Operation start trigger of channel 1 1 2 SSR20 Serial status register mn 0x0 -1 read-only n 0x0 0x67 BFF Buffer register status indication flag of channel n 5 6 FEF Framing error detection flag of channel n 2 3 OVF Overrun error detection flag of channel n 0 1 PEF Parity error detection flag of channel n 1 2 TSF Communication status indication flag of channel n 6 7 SSR21 Serial status register mn 0x2 -1 read-write n 0x0 0xFFFFFFFF ST2 Serial channel stop register 2 0x14 -1 read-write n 0x0 0x3 ST20 Operation stop trigger of channel 0 0 1 ST21 Operation stop trigger of channel 1 1 2 TXD2 UART transmit data register SDR20 0x110 8 read-write n 0x0 0xFFFFFFFF SPIHS0 Serial Interface SPI0 SPIHS0 0x40042400 0x0 0x200 registers n SDRI0 Data buffer of reception 0xC -1 read-write n 0x0 0xFFFF SDRO0 Data buffer of transmission 0x8 -1 read-write n 0x0 0xFFFF SPIC0 SPI control register 0x4 -1 read-write n 0x0 0x1F CKP Selection of clock phase for SPI 4 5 read-write CKS Operation clock control 0 3 read-write DAP Selection of data phase for SPI 3 4 read-write SPIM0 SPI mode control register 0x0 -1 read-write n 0x0 0xFE DIR MSB of LSB mode select 4 5 DLS data length control 2 3 INTMD interrupt source select 3 4 NSSE NSS pin enable 5 6 RECMD Receive mode selection 1 2 SPIE SPI operation enable 7 8 TRMD Transfer and Receive mode 6 7 SPIS0 SPI status register 0x10 -1 read-write n 0x0 0x3 SDRIF Receive buffer non-empty flag 1 2 SPTF SPI transmission status flag 0 1 SPIHS1 Serial Interface SPI1 SPIHS1 0x40042800 0x0 0x200 registers n SDRI1 Data buffer of reception 0xC -1 read-write n 0x0 0xFFFF SDRO1 Data buffer of transmission 0x8 -1 read-write n 0x0 0xFFFF SPIC1 SPI control register 0x4 -1 read-write n 0x0 0x1F CKP Selection of clock phase for SPI 4 5 read-write CKS Operation clock control 0 3 read-write DAP Selection of data phase for SPI 3 4 read-write SPIM1 SPI mode control register 0x0 -1 read-write n 0x0 0xFE DIR MSB of LSB mode select 4 5 DLS data length control 2 3 INTMD interrupt source select 3 4 NSSE NSS pin enable 5 6 RECMD Receive mode selection 1 2 SPIE SPI operation enable 7 8 TRMD Transfer and Receive mode 6 7 SPIS1 SPI status register 0x10 -1 read-write n 0x0 0x3 SDRIF Receive buffer non-empty flag 1 2 SPTF SPI transmission status flag 0 1 SSI Serial Sound Interface SSI 0x40090000 0x0 0x100 registers n SSICR Control Register 0x0 32 read-write n 0x0 0x7E3F7FFB BCKP Select Bit Clock Polarity 13 14 CKDV Select Bit Clock Division Ratio 4 8 CKS Select an Audio Clock for Master Mode Communication 30 31 DEL Select Serial Data Delay 8 9 DWL Select Data Word Length 19 22 IIEN Idle Mode Interrupt Output Enable 25 26 LRCKP Select the Initial Value and Polarity of LR Clock/Frame Synchronization Signal 12 13 MST Master Enable 14 15 MUEN Mute Enable 3 4 PDTA Select Placement Data Alignment 9 10 REN Reception Enable 0 1 ROIEN Receive Overflow Interrupt Output Enable 26 27 RUIEN Receive Underflow Interrupt Output Enable 27 28 SDTA Select Serial Data Alignment 10 11 SPDP Select Serial Padding Polarity 11 12 SWL Select System Word Length 16 19 TEN Transmission Enable 1 2 TOIEN Transmit Overflow Interrupt Output Enable 28 29 TUIEN Transmit Underflow Interrupt Output Enable 29 30 SSIFCR FIFO Control Register 0x10 32 read-write n 0x0 0x8001080F AUCKE AUDIO_MCK Enable in Master Mode Communication 31 32 BSW Byte Swap Enable 11 12 RFRST Receive FIFO Data Register Reset 0 1 RIE Receive Data Full Interrupt Output Enable 3 4 SSIRST Software Reset 16 17 TFRST Transmit FIFO Data Register Reset 1 2 TIE Transmit Data Empty Interrupt Output Enable 4 5 SSIFRDR Receive FIFO Data Register 0x1C 32 read-write n 0x0 0xFFFFFFFF SSIFSR FIFO Status Register 0x14 32 read-write n 0x0 0xF010F01 RDC Number of Receive FIFO Data Indication Flag 8 12 RDF Receive Data Full Flag 0 1 TDC Number of Transmit FIFO Data Indication Flag 24 28 TDE Transmit Data Empty Flag 15 16 SSIFTDR Transmit FIFO Data Register 0x18 32 read-write n 0x0 0xFFFFFFFF SSISCR Status Control Register 0x24 32 read-write n 0x0 0x707 RDFS RDF Setting Condition Select 0 3 TDES TDE Setting Condition Select 8 11 SSISR Status Register 0x4 32 read-write n 0x0 0x3E000000 IIRQ Idle Mode Status Flag 25 26 ROIRQ Receive Overflow Error Status Flag 26 27 RUIRQ Receive Underflow Error Status Flag 27 28 TOIRQ Transmit Overflow Error Status Flag 28 29 TUIRQ Transmit Underflow Error Status Flag 29 30 SSITDMR TDM Mode Register 0x20 32 read-write n 0x0 0x303 BCKASTP Enable Stopping BCK Output When SSIE is in Idle Status 9 10 LRCONT Enable LRCK/FS Continuation 8 9 read-only OMOD Audio Format Select 0 2 TM40 General Purpose Timer 4 TM4 0x40041D80 0x0 0x200 registers n TM00 TM40 channel 0 interrupt request 18 TM01 TM40 channel 1 interrupt request 19 TM02 TM40 channel 2 interrupt request 20 TM03 TM40 channel 3 interrupt request 21 TCR00 Timer count register 0%s 0x0 -1 read-only n 0xFFFF 0xFFFF TCR01 Timer count register 0%s 0x2 -1 read-only n 0xFFFF 0xFFFF TCR02 Timer count register 0%s 0x4 -1 read-only n 0xFFFF 0xFFFF TCR03 Timer count register 0%s 0x6 -1 read-only n 0xFFFF 0xFFFF TDR00 Timer data register 0%s 0x198 -1 read-write n 0x0 0xFFFF TDR01 Timer data register 0%s 0x19A -1 read-write n 0x0 0xFFFF TDR01H Timer data higher register 01 TDR01 0x19B 8 read-write n 0x0 0xFFFFFFFF TDR01L Timer data lower register 01 TDR01 0x19A 8 read-write n 0x0 0xFFFFFFFF TDR02 Timer data register 0%s 0x1E4 -1 read-write n 0x0 0xFFFF TDR03 Timer data register 0%s 0x1E6 -1 read-write n 0x0 0xFFFF TDR03H Timer data higher register 03 TDR03 0x1E7 8 read-write n 0x0 0xFFFFFFFF TDR03L Timer data lower register 03 TDR03 0x1E6 8 read-write n 0x0 0xFFFFFFFF TE0 Timer channel enable status register m 0x30 -1 read-only n 0x0 0xFFFF TE00 Indication of operation enable/stop status of channel 0 0 1 TE01 Indication of operation enable/stop status of channel 1 1 2 TE02 Indication of operation enable/stop status of channel 2 2 3 TE03 Indication of operation enable/stop status of channel 3 3 4 TEH01 Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 1 is in the 8-bit timer mode 9 10 TEH03 Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 3 is in the 8-bit timer mode 11 12 TMR00 Timer mode register mn 0x10 -1 read-write n 0x0 0xFFFF CCS Selection of count clock (fTCLK) of channel n 12 13 read-write CIS Selection of TImn pin input valid edge 6 8 read-write CKS Selection of operation clock (fMCK) of channel n 14 16 read-write MD Operation mode of channel n 0 4 read-write STS Setting of start trigger or capture trigger of channel n 8 11 read-write TMR01 Timer mode register mn 0x12 -1 read-write n 0x0 0xFFFF CCS Selection of count clock (fTCLK) of channel n 12 13 read-write CIS Selection of TImn pin input valid edge 6 8 read-write CKS Selection of operation clock (fMCK) of channel n 14 16 read-write MD Operation mode of channel n 0 4 read-write SPLIT Selection of 8 or 16-bit timer operation for channels 1 and 3 11 12 read-write STS Setting of start trigger or capture trigger of channel n 8 11 read-write TMR02 Timer mode register mn 0x14 -1 read-write n 0x0 0xFFFF CCS Selection of count clock (fTCLK) of channel n 12 13 read-write CIS Selection of TImn pin input valid edge 6 8 read-write CKS Selection of operation clock (fMCK) of channel n 14 16 read-write MASTER Selection between using channel n independently or simultaneously with another channel (as a slave or master) 11 12 read-write MD Operation mode of channel n 0 4 read-write STS Setting of start trigger or capture trigger of channel n 8 11 read-write TMR03 Timer mode register mn 0x16 -1 read-write n 0x0 0xFFFF CCS Selection of count clock (fTCLK) of channel n 12 13 read-write CIS Selection of TImn pin input valid edge 6 8 read-write CKS Selection of operation clock (fMCK) of channel n 14 16 read-write MD Operation mode of channel n 0 4 read-write SPLIT Selection of 8 or 16-bit timer operation for channels 1 and 3 11 12 read-write STS Setting of start trigger or capture trigger of channel n 8 11 read-write TO0 Timer output register 0 0x38 -1 read-write n 0x0 0xFFFF TO00 Timer output of channel 0 0 1 TO01 Timer output of channel 1 1 2 TO02 Timer output of channel 2 2 3 TO03 Timer output of channel 3 3 4 TOE0 Timer output enable register 0 0x3A -1 read-write n 0x0 0xFFFF TOE00 Timer output enable of channel 0 0 1 TOE01 Timer output enable of channel 1 1 2 TOE02 Timer output enable of channel 2 2 3 TOE03 Timer output enable of channel 3 3 4 TOL0 Timer output level register 0 0x3C -1 read-write n 0x0 0xFFFF TOL01 Control of timer output level of channel 1 1 2 TOL02 Control of timer output level of channel 2 2 3 TOL03 Control of timer output level of channel 3 3 4 TOM0 Timer output mode register 0 0x3E -1 read-write n 0x0 0xFFFF TOM01 Control of timer output mode of channel 1 1 2 TOM02 Control of timer output mode of channel 2 2 3 TOM03 Control of timer output mode of channel 3 3 4 TPS0 Timer clock select register 0 0x36 -1 read-write n 0x0 0xFFFF PRS00 Prescaler 0 0 4 PRS01 Prescaler 1 4 8 PRS02 Prescaler 2 8 10 PRS03 Prescaler 3 12 14 TS0 Timer channel start register 0 0x32 -1 read-write n 0x0 0xFFFF TS00 Operation enable (start) trigger of channel 0 0 1 TS01 Operation enable (start) trigger of channel 1 1 2 TS02 Operation enable (start) trigger of channel 2 2 3 TS03 Operation enable (start) trigger of channel 3 3 4 TSH01 Trigger to enable operation (start operation) of the higher 8-bit timer when channel 1 is in the 8-bit timer mode 9 10 TSH03 Trigger to enable operation (start operation) of the higher 8-bit timer when channel 3 is in the 8-bit timer mode 11 12 TSR00 Timer status register mn 0x20 -1 read-only n 0x0 0xFFFF OVF Counter overflow status of channel n 0 1 TSR01 Timer status register mn 0x22 -1 read-write n 0x0 0xFFFFFFFF TSR02 Timer status register mn 0x24 -1 read-write n 0x0 0xFFFFFFFF TSR03 Timer status register mn 0x26 -1 read-write n 0x0 0xFFFFFFFF TT0 Timer channel stop register 0 0x34 -1 read-write n 0x0 0xFFFF TT00 Operation stop trigger of channel 0 0 1 TT01 Operation stop trigger of channel 1 1 2 TT02 Operation stop trigger of channel 2 2 3 TT03 Operation stop trigger of channel 3 3 4 TTH01 Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode 9 10 TTH03 Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode 11 12 TM81 General Purpose Timer 4 TM8 0x40042180 0x0 0x200 registers n TM10 TM81 channel 0 interrupt request 27 TM11 TM81 channel 1 interrupt request 28 TM12 TM81 channel 2 interrupt request 29 TM13 TM81 channel 3 interrupt request 30 TCR10 Timer count register 0%s 0x0 -1 read-only n 0xFFFF 0xFFFF TCR11 Timer count register 0%s 0x2 -1 read-only n 0xFFFF 0xFFFF TCR12 Timer count register 0%s 0x4 -1 read-only n 0xFFFF 0xFFFF TCR13 Timer count register 0%s 0x6 -1 read-only n 0xFFFF 0xFFFF TCR14 Timer count register 0%s 0x8 -1 read-only n 0xFFFF 0xFFFF TCR15 Timer count register 0%s 0xA -1 read-only n 0xFFFF 0xFFFF TCR16 Timer count register 0%s 0xC -1 read-only n 0xFFFF 0xFFFF TCR17 Timer count register 0%s 0xE -1 read-only n 0xFFFF 0xFFFF TDR10 Timer data register 00 0x198 16 read-write n 0x0 0xFFFF TDR11 Timer data register 01 0x19A 16 read-write n 0x0 0xFFFF TDR11H Timer data higher register 11 TDR11 0x19B 8 read-write n 0x0 0xFFFFFFFF TDR11L Timer data lower register 11 TDR11 0x19A 8 read-write n 0x0 0xFFFFFFFF TDR12 Timer data register 02 0x1E4 16 read-write n 0x0 0xFFFF TDR13 Timer data register 03 0x1E6 16 read-write n 0x0 0xFFFF TDR13H Timer data higher register 13 TDR13 0x1E7 8 read-write n 0x0 0xFFFFFFFF TDR13L Timer data lower register 13 TDR13 0x1E6 8 read-write n 0x0 0xFFFFFFFF TDR14 Timer data register 04 0x1E8 16 read-write n 0x0 0xFFFF TDR15 Timer data register 05 0x1EA 16 read-write n 0x0 0xFFFF TDR16 Timer data register 06 0x1EC 16 read-write n 0x0 0xFFFF TDR17 Timer data register 07 0x1EE 16 read-write n 0x0 0xFFFF TE1 Timer channel enable status register m 0x30 -1 read-only n 0x0 0xFFFF TE10 Indication of operation enable/stop status of channel 0 0 1 TE11 Indication of operation enable/stop status of channel 1 1 2 TE12 Indication of operation enable/stop status of channel 2 2 3 TE13 Indication of operation enable/stop status of channel 3 3 4 TE14 Indication of operation enable/stop status of channel 4 4 5 TE15 Indication of operation enable/stop status of channel 5 5 6 TE16 Indication of operation enable/stop status of channel 6 6 7 TE17 Indication of operation enable/stop status of channel 7 7 8 TMR10 Timer mode register mn 0x10 -1 read-write n 0x0 0xFFFF CCS Selection of count clock (fTCLK) of channel n 12 13 read-write CIS Selection of TImn pin input valid edge 6 8 read-write CKS Selection of operation clock (fMCK) of channel n 14 16 read-write MD Operation mode of channel n 0 4 read-write STS Setting of start trigger or capture trigger of channel n 8 11 read-write TMR11 Timer mode register mn 0x12 -1 read-write n 0x0 0xFFFF CCS Selection of count clock (fTCLK) of channel n 12 13 read-write CIS Selection of TImn pin input valid edge 6 8 read-write CKS Selection of operation clock (fMCK) of channel n 14 16 read-write MD Operation mode of channel n 0 4 read-write SPLIT Selection of 8 or 16-bit timer operation for channels 1 and 3 11 12 read-write STS Setting of start trigger or capture trigger of channel n 8 11 read-write TMR12 Timer mode register mn 0x14 -1 read-write n 0x0 0xFFFF CCS Selection of count clock (fTCLK) of channel n 12 13 read-write CIS Selection of TImn pin input valid edge 6 8 read-write CKS Selection of operation clock (fMCK) of channel n 14 16 read-write MASTER Selection between using channel n independently or simultaneously with another channel (as a slave or master) 11 12 read-write MD Operation mode of channel n 0 4 read-write STS Setting of start trigger or capture trigger of channel n 8 11 read-write TMR13 Timer mode register mn 0x16 -1 read-write n 0x0 0xFFFF CCS Selection of count clock (fTCLK) of channel n 12 13 read-write CIS Selection of TImn pin input valid edge 6 8 read-write CKS Selection of operation clock (fMCK) of channel n 14 16 read-write MD Operation mode of channel n 0 4 read-write SPLIT Selection of 8 or 16-bit timer operation for channels 1 and 3 11 12 read-write STS Setting of start trigger or capture trigger of channel n 8 11 read-write TMR14 Timer mode register mn 0x18 -1 read-write n 0x0 0xFFFF CCS Selection of count clock (fTCLK) of channel n 12 13 read-write CIS Selection of TImn pin input valid edge 6 8 read-write CKS Selection of operation clock (fMCK) of channel n 14 16 read-write MASTER Selection between using channel n independently or simultaneously with another channel (as a slave or master) 11 12 read-write MD Operation mode of channel n 0 4 read-write STS Setting of start trigger or capture trigger of channel n 8 11 read-write TMR15 Timer mode register mn 0x1A -1 read-write n 0x0 0xFFFF CCS Selection of count clock (fTCLK) of channel n 12 13 read-write CIS Selection of TImn pin input valid edge 6 8 read-write CKS Selection of operation clock (fMCK) of channel n 14 16 read-write MD Operation mode of channel n 0 4 read-write STS Setting of start trigger or capture trigger of channel n 8 11 read-write TMR16 Timer mode register mn 0x1C -1 read-write n 0x0 0xFFFF CCS Selection of count clock (fTCLK) of channel n 12 13 read-write CIS Selection of TImn pin input valid edge 6 8 read-write CKS Selection of operation clock (fMCK) of channel n 14 16 read-write MASTER Selection between using channel n independently or simultaneously with another channel (as a slave or master) 11 12 read-write MD Operation mode of channel n 0 4 read-write STS Setting of start trigger or capture trigger of channel n 8 11 read-write TMR17 Timer mode register mn 0x1E -1 read-write n 0x0 0xFFFF CCS Selection of count clock (fTCLK) of channel n 12 13 read-write CIS Selection of TImn pin input valid edge 6 8 read-write CKS Selection of operation clock (fMCK) of channel n 14 16 read-write MD Operation mode of channel n 0 4 read-write STS Setting of start trigger or capture trigger of channel n 8 11 read-write TO1 Timer output register 0 0x38 -1 read-write n 0x0 0xFFFF TO10 Timer output of channel 0 0 1 TO11 Timer output of channel 1 1 2 TO12 Timer output of channel 2 2 3 TO13 Timer output of channel 3 3 4 TO14 Timer output of channel 4 4 5 TO15 Timer output of channel 5 5 6 TO16 Timer output of channel 6 6 7 TO17 Timer output of channel 7 7 8 TOE1 Timer output enable register 0 0x3A -1 read-write n 0x0 0xFFFF TOE10 Timer output enable of channel 0 0 1 TOE11 Timer output enable of channel 1 1 2 TOE12 Timer output enable of channel 2 2 3 TOE13 Timer output enable of channel 3 3 4 TOE14 Timer output enable of channel 4 4 5 TOE15 Timer output enable of channel 5 5 6 TOE16 Timer output enable of channel 6 6 7 TOE17 Timer output enable of channel 7 7 8 TOL1 Timer output level register 0 0x3C -1 read-write n 0x0 0xFFFF TOL11 Control of timer output level of channel 1 1 2 TOL12 Control of timer output level of channel 2 2 3 TOL13 Control of timer output level of channel 3 3 4 TOL14 Control of timer output level of channel 4 4 5 TOL15 Control of timer output level of channel 5 5 6 TOL16 Control of timer output level of channel 6 6 7 TOL17 Control of timer output level of channel 7 7 8 TOM1 Timer output mode register 0 0x3E -1 read-write n 0x0 0xFFFF TOM11 Control of timer output mode of channel 1 1 2 TOM12 Control of timer output mode of channel 2 2 3 TOM13 Control of timer output mode of channel 3 3 4 TOM14 Control of timer output mode of channel 4 4 5 TOM15 Control of timer output mode of channel 5 5 6 TOM16 Control of timer output mode of channel 6 6 7 TOM17 Control of timer output mode of channel 7 7 8 TPS1 Timer clock select register 0 0x36 -1 read-write n 0x0 0xFFFF PRS10 Prescaler 0 0 4 PRS11 Prescaler 1 4 8 PRS12 Prescaler 2 8 10 PRS13 Prescaler 3 12 14 TS1 Timer channel start register 0 0x32 -1 read-write n 0x0 0xFFFF TS10 Operation enable (start) trigger of channel 0 0 1 TS11 Operation enable (start) trigger of channel 1 1 2 TS12 Operation enable (start) trigger of channel 2 2 3 TS13 Operation enable (start) trigger of channel 3 3 4 TS14 Operation enable (start) trigger of channel 4 4 5 TS15 Operation enable (start) trigger of channel 5 5 6 TS16 Operation enable (start) trigger of channel 6 6 7 TS17 Operation enable (start) trigger of channel 7 7 8 TSR10 Timer status register mn 0x20 -1 read-only n 0x0 0xFFFF OVF Counter overflow status of channel n 0 1 TSR11 Timer status register mn 0x22 -1 read-write n 0x0 0xFFFFFFFF TSR12 Timer status register mn 0x24 -1 read-write n 0x0 0xFFFFFFFF TSR13 Timer status register mn 0x26 -1 read-write n 0x0 0xFFFFFFFF TSR14 Timer status register mn 0x28 -1 read-write n 0x0 0xFFFFFFFF TSR15 Timer status register mn 0x2A -1 read-write n 0x0 0xFFFFFFFF TSR16 Timer status register mn 0x2C -1 read-write n 0x0 0xFFFFFFFF TSR17 Timer status register mn 0x2E -1 read-write n 0x0 0xFFFFFFFF TT1 Timer channel stop register 0 0x34 -1 read-write n 0x0 0xFFFF TT10 Operation stop trigger of channel 0 0 1 TT11 Operation stop trigger of channel 1 1 2 TT12 Operation stop trigger of channel 2 2 3 TT13 Operation stop trigger of channel 3 3 4 TT14 Operation stop trigger of channel 4 4 5 TT15 Operation stop trigger of channel 5 5 6 TT16 Operation stop trigger of channel 6 6 7 TT17 Operation stop trigger of channel 7 7 8 TSN Temperature Sensor calibration data TSN 0x08500C68 0x0 0x8 registers n TSN25 The A/D conversion value of Temperature Sensor at 25 degrees and 3.0V reference voltage 0x4 -1 read-only n 0x0 0xFFFF int16_t TSN85 The A/D conversion value of Temperature Sensor at 85 degrees and 3.0V reference voltage 0x0 -1 read-only n 0x0 0xFFFF int16_t UID 128-bit Unique ID UID 0x0850084C 0x0 0x80 registers n UID0 UID word %s 0x0 -1 read-only n 0x0 0xFFFFFFFF UID1 UID word %s 0x4 -1 read-only n 0x0 0xFFFFFFFF UID2 UID word %s 0x8 -1 read-only n 0x0 0xFFFFFFFF UID3 UID word %s 0xC -1 read-only n 0x0 0xFFFFFFFF USBF USB Full Speed Module USBF 0x40080000 0x0 0x500 registers n USBI INTUSBI interrupt request 5 USBR INTUSBR interrupt request 6 BEMPENB BEMP Interrupt Enable Register 0x3A -1 read-write n 0x0 0x3FF PIPE0BEMPE BEMP Interrupt Enable for Pipe 0 0 1 PIPE1BEMPE BEMP Interrupt Enable for Pipe 1 1 2 PIPE2BEMPE BEMP Interrupt Enable for Pipe 2 2 3 PIPE3BEMPE BEMP Interrupt Enable for Pipe 3 3 4 PIPE4BEMPE BEMP Interrupt Enable for Pipe 4 4 5 PIPE5BEMPE BEMP Interrupt Enable for Pipe 5 5 6 PIPE6BEMPE BEMP Interrupt Enable for Pipe 6 6 7 PIPE7BEMPE BEMP Interrupt Enable for Pipe 7 7 8 PIPE8BEMPE BEMP Interrupt Enable for Pipe 8 8 9 PIPE9BEMPE BEMP Interrupt Enable for Pipe 9 9 10 BEMPSTS BEMP Interrupt Status Register 0x4A -1 read-write n 0x0 0x3FF PIPE0BEMP BEMP Interrupt Status for Pipe 0 0 1 PIPE1BEMP BEMP Interrupt Status for Pipe 1 1 2 PIPE2BEMP BEMP Interrupt Status for Pipe 2 2 3 PIPE3BEMP BEMP Interrupt Status for Pipe 3 3 4 PIPE4BEMP BEMP Interrupt Status for Pipe 4 4 5 PIPE5BEMP BEMP Interrupt Status for Pipe 5 5 6 PIPE6BEMP BEMP Interrupt Status for Pipe 6 6 7 PIPE7BEMP BEMP Interrupt Status for Pipe 7 7 8 PIPE8BEMP BEMP Interrupt Status for Pipe 8 8 9 PIPE9BEMP BEMP Interrupt Status for Pipe 9 9 10 BRDYENB BRDY Interrupt Enable Register 0x36 -1 read-write n 0x0 0x3FF PIPE0BRDYE BRDY Interrupt Enable for Pipe 0 0 1 PIPE1BRDYE BRDY Interrupt Enable for Pipe 1 1 2 PIPE2BRDYE BRDY Interrupt Enable for Pipe 2 2 3 PIPE3BRDYE BRDY Interrupt Enable for Pipe 3 3 4 PIPE4BRDYE BRDY Interrupt Enable for Pipe 4 4 5 PIPE5BRDYE BRDY Interrupt Enable for Pipe 5 5 6 PIPE6BRDYE BRDY Interrupt Enable for Pipe 6 6 7 PIPE7BRDYE BRDY Interrupt Enable for Pipe 7 7 8 PIPE8BRDYE BRDY Interrupt Enable for Pipe 8 8 9 PIPE9BRDYE BRDY Interrupt Enable for Pipe 9 9 10 BRDYSTS BRDY Interrupt Status Register 0x46 -1 read-write n 0x0 0x3FF PIPE0BRDY BRDY Interrupt Status for Pipe 0 0 1 PIPE1BRDY BRDY Interrupt Status for Pipe 1 1 2 PIPE2BRDY BRDY Interrupt Status for Pipe 2 2 3 PIPE3BRDY BRDY Interrupt Status for Pipe 3 3 4 PIPE4BRDY BRDY Interrupt Status for Pipe 4 4 5 PIPE5BRDY BRDY Interrupt Status for Pipe 5 5 6 PIPE6BRDY BRDY Interrupt Status for Pipe 6 6 7 PIPE7BRDY BRDY Interrupt Status for Pipe 7 7 8 PIPE8BRDY BRDY Interrupt Status for Pipe 8 8 9 PIPE9BRDY BRDY Interrupt Status for Pipe 9 9 10 CFIFO CFIFO Port Register 0x14 -1 read-write n 0x0 0xFFFFFFFF CFIFOCTR CFIFO Port Control Register 0x22 -1 read-write n 0x0 0xE0FF BCLR CPU Buffer Clear 14 15 BVAL Buffer Memory Valid Flag 15 16 DTLN Receive Data Length 0 8 FRDY FIFO Port Ready 13 14 CFIFOL CFIFO Port Register CFIFO 0x14 8 read-write n 0x0 0xFFFFFFFF CFIFOSEL CFIFO Port Select Register 0x20 -1 read-write n 0x0 0xC52F BIGEND CFIFO Port Endian Control 8 9 CURPIPE CFIFO Port Access Pipe Specification 0 4 ISEL CFIFO Port Access Direction When DCP is Selected 5 6 MBW CFIFO Port Access Bit Width 10 11 RCNT Read Count Mode 15 16 REW USB_EXICEN Output Pin Contro 14 15 D0FIFO D0FIFO Port Register 0x18 -1 read-write n 0x0 0xFFFFFFFF D0FIFOCTR D1FIFO Port Control Register 0x2A -1 read-write n 0x0 0xFFFFFFFF D0FIFOL D0FIFO Port Register D0FIFO 0x18 8 read-write n 0x0 0xFFFFFFFF D0FIFOSEL D0FIFO Port Select Register 0x28 -1 read-write n 0x0 0xF50F BIGEND FIFO Port Endian Control 8 9 CURPIPE FIFO Port Access Pipe Specification 0 4 DCLRM Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read 13 14 DREQE DMA/DTC Transfer Request Enable 12 13 MBW FIFO Port Access Bit Width 10 11 RCNT Read Count Mode 15 16 REW USB_EXICEN Output Pin Contro 14 15 D1FIFO D1FIFO Port Register 0x1C -1 read-write n 0x0 0xFFFFFFFF D1FIFOCTR D1FIFO Port Control Register 0x2E -1 read-write n 0x0 0xFFFFFFFF D1FIFOL D1FIFO Port Register D1FIFO 0x1C 8 read-write n 0x0 0xFFFFFFFF D1FIFOSEL D1FIFO Port Select Register 0x2C -1 read-write n 0x0 0xFFFFFFFF DCPCFG DCP Configuration Register 0x5C -1 read-write n 0x0 0x90 DIR Transfer Direction 4 5 SHTNAK Pipe Disabled at End of Transfer 7 8 DCPCTR DCP Control Register 0x60 -1 read-write n 0x0 0xC9E3 BSTS Buffer Status 15 16 CCPL Control Transfer End Enable 2 3 PBUSY Pipe Busy 5 6 PID Response PID 0 2 SQCLR Sequence Toggle Bit Clear 8 9 SQMON Sequence Toggle Bit Monitor 6 7 SQSET Sequence Toggle Bit Set 7 8 SUREQ Setup Token Transmission 14 15 SUREQCLR SUREQ Bit Clear 11 12 DCPMAXP DCP Maximum Packet Size Register 0x5E -1 read-write n 0x0 0xF07F DEVSEL Device Select 12 16 MXPS Maximum Packet Size 0 7 DEVADDn0 Device Address %s Configuration Register 0xD0 16 read-write n 0x0 0xC0 USBSPD Transfer Speed of Communication Target Device 6 8 DEVADDn1 Device Address %s Configuration Register 0xD2 16 read-write n 0x0 0xC0 USBSPD Transfer Speed of Communication Target Device 6 8 DEVADDn2 Device Address %s Configuration Register 0xD4 16 read-write n 0x0 0xC0 USBSPD Transfer Speed of Communication Target Device 6 8 DEVADDn3 Device Address %s Configuration Register 0xD6 16 read-write n 0x0 0xC0 USBSPD Transfer Speed of Communication Target Device 6 8 DEVADDn4 Device Address %s Configuration Register 0xD8 16 read-write n 0x0 0xC0 USBSPD Transfer Speed of Communication Target Device 6 8 DEVADDn5 Device Address %s Configuration Register 0xDA 16 read-write n 0x0 0xC0 USBSPD Transfer Speed of Communication Target Device 6 8 DVSTCTR0 Device State Control Register 0 0x8 -1 read-write n 0x0 0xFF7 EXICEN USB_EXICEN Output Pin Contro 10 11 HNPBTOA Host Negotiation Protocol (HNP) Control 11 12 RESUME Resume Output 5 6 RHST USB Bus Reset Status 0 3 RWUPE Wakeup Detection Enable 7 8 UACT USB Bus Enable 4 5 USBRST USB Bus Reset Output 6 7 VBUSEN USB_VBUSEN Output Pin Control 9 10 WKUP Wakeup Output 8 9 FRMNUM Frame Number Register 0x4C -1 read-write n 0x0 0xC7FF CRCE Receive Data Error 14 15 FRNM Frame Number 0 11 read-only OVRN Overrun/Underrun Detection Status 15 16 INTENB0 Interrupt Enable Register 0 0x30 -1 read-write n 0x0 0xFF00 BEMPE Buffer Empty Interrupt Enable 10 11 BRDYE Buffer Ready Interrupt Enable 8 9 CTRE Control Transfer Stage Transition Interrupt Enable 11 12 DVSE Device State Transition Interrupt Enable 12 13 NRDYE Buffer Not Ready Response Interrupt Enable 9 10 RSME Resume Interrupt Enable 14 15 SOFE Frame Number Update Interrupt Enable 13 14 VBSE VBUS Interrupt Enable 15 16 INTENB1 Interrupt Enable Register 1 0x32 -1 read-write n 0x0 0xD871 ATTCHE Connection Detection Interrupt Enable 11 12 BCHGE USB Bus Change Interrupt Enable 14 15 DTCHE Disconnection Detection Interrupt Enable 12 13 EOFERRE Setup Transaction Error Interrupt Enable 6 7 OVRCRE Overcurrent Input Change Interrupt Enable 15 16 PDDETINTE0 PDDETINT0 Detection Interrupt Enable 0 1 SACKE Setup Transaction Normal Response Interrupt Enable 4 5 SIGNE Setup Transaction Error Interrupt Enable 5 6 INTSTS0 Interrupt Status Register 0 0x40 -1 read-write n 0x0 0xFFFF BEMP Buffer Empty Interrupt Status 10 11 BRDY Buffer Ready Interrupt Status 8 9 CTRT Control Transfer Stage Transition Interrupt Status 11 12 CTSQ Control Transfer Stage 0 3 DVSQ Device State 4 7 DVST Device State Transition Interrupt Status 12 13 NRDY Buffer Not Ready Interrupt Status 9 10 RESM Resume Interrupt Status 14 15 SOFR Frame Number Update Interrupt Status 13 14 VALID USB Request Reception 3 4 VBINT VBUS Interrupt Status 15 16 VBSTS VBUS Input Status 7 8 INTSTS1 Interrupt Status Register 1 0x42 -1 read-write n 0x0 0xD871 ATTCH Connection Detection Interrupt Status 11 12 BCHG USB Bus Change Interrupt Status 14 15 DTCH Disconnection Detection Interrupt Status 12 13 EOFERR Setup Transaction Error Interrupt Status 6 7 OVRCR Overcurrent Input Change Interrupt Status 15 16 PDDETINT0 PDDETINT0 Detection Interrupt Status 0 1 SACK Setup Transaction Normal Response Interrupt Status 4 5 SIGN Setup Transaction Error Interrupt Status 5 6 NRDYENB NRDY Interrupt Enable Register 0x38 -1 read-write n 0x0 0x3FF PIPE0NRDYE NRDY Interrupt Enable for Pipe 0 0 1 PIPE1NRDYE NRDY Interrupt Enable for Pipe 1 1 2 PIPE2NRDYE NRDY Interrupt Enable for Pipe 2 2 3 PIPE3NRDYE NRDY Interrupt Enable for Pipe 3 3 4 PIPE4NRDYE NRDY Interrupt Enable for Pipe 4 4 5 PIPE5NRDYE NRDY Interrupt Enable for Pipe 5 5 6 PIPE6NRDYE NRDY Interrupt Enable for Pipe 6 6 7 PIPE7NRDYE NRDY Interrupt Enable for Pipe 7 7 8 PIPE8NRDYE NRDY Interrupt Enable for Pipe 8 8 9 PIPE9NRDYE NRDY Interrupt Enable for Pipe 9 9 10 NRDYSTS NRDY Interrupt Status Register 0x48 -1 read-write n 0x0 0x3FF PIPE0NRDY NRDY Interrupt Status for Pipe 0 0 1 PIPE1NRDY NRDY Interrupt Status for Pipe 1 1 2 PIPE2NRDY NRDY Interrupt Status for Pipe 2 2 3 PIPE3NRDY NRDY Interrupt Status for Pipe 3 3 4 PIPE4NRDY NRDY Interrupt Status for Pipe 4 4 5 PIPE5NRDY NRDY Interrupt Status for Pipe 5 5 6 PIPE6NRDY NRDY Interrupt Status for Pipe 6 6 7 PIPE7NRDY NRDY Interrupt Status for Pipe 7 7 8 PIPE8NRDY NRDY Interrupt Status for Pipe 8 8 9 PIPE9NRDY NRDY Interrupt Status for Pipe 9 9 10 PIPE1CTR PIPE1 Control Registers 0x70 -1 read-write n 0x0 0xC7E3 ACLRM Auto Buffer Clear Mode 9 10 ATREPM Auto Response Mode 10 11 BSTS Buffer Status 15 16 INBUFM Transmit Buffer Monitor 14 15 PBUSY Pipe Busy 5 6 PID Response PID 0 2 SQCLR Sequence Toggle Bit Clear 8 9 SQMON Sequence Toggle Bit Confirmation 6 7 SQSET Sequence Toggle Bit Set 7 8 PIPE1TRE PIPE%s Transaction Counter Enable Register 0x90 -1 read-write n 0x0 0x300 TRCLR Transaction Counter Clear 8 9 TRENB Transaction Counter Enable 9 10 PIPE1TRN PIPE%s Transaction Counter Register 0x92 16 read-write n 0x0 0xFFFF PIPE2CTR PIPE2 Control Registers 0x72 -1 read-write n 0x0 0xFFFFFFFF PIPE2TRE PIPE%s Transaction Counter Enable Register 0x94 -1 read-write n 0x0 0x300 TRCLR Transaction Counter Clear 8 9 TRENB Transaction Counter Enable 9 10 PIPE2TRN PIPE%s Transaction Counter Register 0x96 16 read-write n 0x0 0xFFFF PIPE3CTR PIPE3 Control Registers 0x74 -1 read-write n 0x0 0xFFFFFFFF PIPE3TRE PIPE%s Transaction Counter Enable Register 0x98 -1 read-write n 0x0 0x300 TRCLR Transaction Counter Clear 8 9 TRENB Transaction Counter Enable 9 10 PIPE3TRN PIPE%s Transaction Counter Register 0x9A 16 read-write n 0x0 0xFFFF PIPE4CTR PIPE4 Control Registers 0x76 -1 read-write n 0x0 0xFFFFFFFF PIPE4TRE PIPE%s Transaction Counter Enable Register 0x9C -1 read-write n 0x0 0x300 TRCLR Transaction Counter Clear 8 9 TRENB Transaction Counter Enable 9 10 PIPE4TRN PIPE%s Transaction Counter Register 0x9E 16 read-write n 0x0 0xFFFF PIPE5CTR PIPE5 Control Registers 0x78 -1 read-write n 0x0 0xFFFFFFFF PIPE5TRE PIPE%s Transaction Counter Enable Register 0xA0 -1 read-write n 0x0 0x300 TRCLR Transaction Counter Clear 8 9 TRENB Transaction Counter Enable 9 10 PIPE5TRN PIPE%s Transaction Counter Register 0xA2 16 read-write n 0x0 0xFFFF PIPE6CTR PIPE6 Control Registers 0x7A -1 read-write n 0x0 0x83E3 ACLRM Auto Buffer Clear Mode 9 10 BSTS Buffer Status 15 16 PBUSY Pipe Busy 5 6 PID Response PID 0 2 SQCLR Sequence Toggle Bit Clear 8 9 SQMON Sequence Toggle Bit Confirmation 6 7 SQSET Sequence Toggle Bit Set 7 8 PIPE7CTR PIPE7 Control Registers 0x7C -1 read-write n 0x0 0xFFFFFFFF PIPE8CTR PIPE8 Control Registers 0x7E -1 read-write n 0x0 0xFFFFFFFF PIPE9CTR PIPE9 Control Registers 0x80 -1 read-write n 0x0 0xFFFFFFFF PIPECFG Pipe Configuration Register 0x68 -1 read-write n 0x0 0xC69F BFRE BRDY Interrupt Operation Specification 10 11 DBLB Double Buffer Mode 9 10 DIR Transfer Direction 4 5 EPNUM Endpoint Number 0 4 SHTNAK Pipe Disabled at End of Transfer 7 8 TYPE Transfer Type 14 16 PIPEMAXP Pipe Maximum Packet Size Register 0x6C -1 read-write n 0x0 0xF1FF DEVSEL Device Select 12 16 MXPS Maximum Packet Size 0 9 PIPEPERI Pipe Cycle Control Register 0x6E -1 read-write n 0x0 0x1007 IFIS Isochronous IN Buffer Flush 12 13 IITV Interval Error Detection Interval 0 3 PIPESEL Pipe Window Select Register 0x64 -1 read-write n 0x0 0xF PIPESEL Pipe Window Select 0 4 SOFCFG SOF Output Configuration Register 0x3C -1 read-write n 0x0 0x150 BRDYM BRDY Interrupt Status Clear Timing 6 7 EDGESTS Edge Interrupt Output Status Monitor 4 5 TRNENSEL Transaction-Enabled Time Select 8 9 SYSCFG System Configuration Control Register 0x0 -1 read-write n 0x0 0x579 CNEN CNEN Single-Ended Receiver Enable 8 9 DCFM Controller Function Select 6 7 DMRPU D- Line Resistor Control 3 4 DPRPU D+ Line Resistor Control 4 5 DRPD D+/D- Line Resistor Control 5 6 SCKE USB Clock Enable 10 11 USBE USBFS Operation Enable 0 1 SYSSTS0 System Configuration Status Register 0 0x4 -1 read-write n 0x0 0xC047 DMRPU External ID0 Input Pin Monitor 2 3 HTACT USB Host Sequencer Status Monitor 6 7 LNST USB Data Line Status Monitor 0 2 OVCMON External USB_OVRCURA/USB_OVRCURB Input Pin Monitor 14 16 USBBCCTRL BC Control Register 0 0xB0 -1 read-write n 0x0 0x3BF BATCHGE0 BC (Battery Charger) Function General Enable Control 7 8 CHGDETSTS0 D- Pin 0.6 V Input Detection Status 8 9 IDMSINKE0 D- Pin 0.6 V Input Detection (Comparator and Sink) Control 2 3 IDPSINKE0 D+ Pin 0.6 V Input Detection (Comparator and Sink) Control 4 5 IDPSRCE0 D+ Pin IDPSRC Output Control 1 2 PDDETSTS0 D+ Pin 0.6 V Input Detection Status 9 10 RPDME0 D- Pin Pull-Down Control 0 1 VDMSRCE0 D- Pin VDMSRC (0.6 V) Output Contro 5 6 VDPSRCE0 D+ Pin VDPSRC (0.6 V) Output Contro 3 4 USBINDX USB Request Index Register 0x58 -1 read-write n 0x0 0xFFFF USBLENG USB Request Length Register 0x5A -1 read-write n 0x0 0xFFFF USBMC USB Module Control Register 0xCC -1 read-write n 0x0 0x81 VDCEN USB Regulator On/Off Control 7 8 VDDUSBE USB Reference Power Supply Circuit On/Off Control 0 1 USBREQ USB Request Type Register 0x54 -1 read-write n 0x0 0xFFFF BMREQUESTTYPE Request Type 0 8 BREQUEST Request 8 16 USBVAL USB Request Value Register 0x56 -1 read-write n 0x0 0xFFFF WDT Watchdog Timer with window WDT 0x40020404 0x0 0xC00 registers n LOCKCTL Lockup Watchdog timer enable register 0x1 -1 read-write n 0x0 0x1 PRCR Lockup Watchdog timer enable protect register 0x2 -1 read-write n 0x0 0xFF WDTE Watchdog timer enable register 0xBFD -1 read-write n 0x0 0xAC