Cmsemicon CMS32F030 2024.04.24 CMS32F030 CM0 r0p0 little 3 false 8 32 ADC ADC Control Register. ADC 0x0 0x0 0xFFF registers n ADC_IRQHandler 7 ADCCON ADC Config register 0x0 -1 read-write n 0x0 0x0 ADCDIV ADC Clock Div 0 3 ADCEN ADC enable control 4 5 ENUM disable disable config 0 enable enable config 1 ADCMS ADC mode select 3 4 ENUM One one conversion 0 Continuous continuous conversion 1 ADCDATA0 ADC channle0 conversion value 0x8 -1 read-only n 0x0 0x0 ADCDATA1 ADC channle1 conversion value 0xC -1 read-only n 0x0 0x0 ADCDATA10 ADC channle10 conversion value 0x30 -1 read-only n 0x0 0x0 ADCDATA11 ADC channle11 conversion value 0x34 -1 read-only n 0x0 0x0 ADCDATA12 ADC channle12 conversion value 0x38 -1 read-only n 0x0 0x0 ADCDATA13 ADC channle13 conversion value 0x3C -1 read-only n 0x0 0x0 ADCDATA14 ADC channle14 conversion value 0x40 -1 read-only n 0x0 0x0 ADCDATA15 ADC channle15 conversion value 0x44 -1 read-only n 0x0 0x0 ADCDATA2 ADC channle2 conversion value 0x10 -1 read-only n 0x0 0x0 ADCDATA3 ADC channle3 conversion value 0x14 -1 read-only n 0x0 0x0 ADCDATA4 ADC channle4 conversion value 0x18 -1 read-only n 0x0 0x0 ADCDATA5 ADC channle5 conversion value 0x1C -1 read-only n 0x0 0x0 ADCDATA6 ADC channle6 conversion value 0x20 -1 read-only n 0x0 0x0 ADCDATA7 ADC channle7 conversion value 0x24 -1 read-only n 0x0 0x0 ADCDATA8 ADC channle8 conversion value 0x28 -1 read-only n 0x0 0x0 ADCDATA9 ADC channle9 conversion value 0x2C -1 read-only n 0x0 0x0 ADCICLR ADC Interrupt Clear Register 0x54 -1 write-only n 0x0 0x0 ADCICLR0 channle 0 status bit clear bit 0 1 ENUM 1 clear 1 ADCICLR1 channle 1 status bit clear bit 1 2 ENUM 1 clear 1 ADCICLR10 channle 10 status bit clear bit 10 11 ENUM 1 clear 1 ADCICLR11 channle 11 status bit clear bit 11 12 ENUM 1 clear 1 ADCICLR12 channle 12 status bit clear bit 12 13 ENUM 1 clear 1 ADCICLR13 channle 13 status bit clear bit 13 14 ENUM 1 clear 1 ADCICLR14 channle 14 status bit clear bit 14 15 ENUM 1 clear 1 ADCICLR15 channle 15 status bit clear bit 15 16 ENUM 1 clear 1 ADCICLR2 channle 2 status bit clear bit 2 3 ENUM 1 clear 1 ADCICLR3 channle 3 status bit clear bit 3 4 ENUM 1 clear 1 ADCICLR4 channle 4 status bit clear bit 4 5 ENUM 1 clear 1 ADCICLR5 channle 5 status bit clear bit 5 6 ENUM 1 clear 1 ADCICLR6 channle 6 status bit clear bit 6 7 ENUM 1 clear 1 ADCICLR7 channle 7 status bit clear bit 7 8 ENUM 1 clear 1 ADCICLR8 channle 8 status bit clear bit 8 9 ENUM 1 clear 1 ADCICLR9 channle 9 status bit clear bit 9 10 ENUM 1 clear 1 ADCIMSC ADC Interrupt Mask Set and Clear Register. 0x48 -1 read-only n 0x0 0x0 ADCIMSC0 ADC channle 0 interrupt enable config bit 0 1 ENUM 0 disable channle 0 0 1 enable channle 0 1 ADCIMSC1 ADC channle 1 interrupt enable config bit 1 2 ENUM 0 disable channle 1 0 1 enable channle 1 1 ADCIMSC10 ADC channle 10 interrupt enable config bit 10 11 ENUM 0 disable channle 10 0 1 enable channle 10 1 ADCIMSC11 ADC channle 11 interrupt enable config bit 11 12 ENUM 0 disable channle 11 0 1 enable channle 11 1 ADCIMSC12 ADC channle 12 interrupt enable config bit 12 13 ENUM 0 disable channle 12 0 1 enable channle 12 1 ADCIMSC13 ADC channle 13 interrupt enable config bit 13 14 ENUM 0 disable channle 13 0 1 enable channle 13 1 ADCIMSC14 ADC channle 14 interrupt enable config bit 14 15 ENUM 0 disable channle 14 0 1 enable channle 14 1 ADCIMSC15 ADC channle 15 interrupt enable config bit 15 16 ENUM 0 disable channle 15 0 1 enable channle 15 1 ADCIMSC2 ADC channle 2 interrupt enable config bit 2 3 ENUM 0 disable channle 2 0 1 enable channle 2 1 ADCIMSC3 ADC channle 3 interrupt enable config bit 3 4 ENUM 0 disable channle 3 0 1 enable channle 3 1 ADCIMSC4 ADC channle 4 interrupt enable config bit 4 5 ENUM 0 disable channle 4 0 1 enable channle 4 1 ADCIMSC5 ADC channle 5 interrupt enable config bit 5 6 ENUM 0 disable channle 5 0 1 enable channle 5 1 ADCIMSC6 ADC channle 6 interrupt enable config bit 6 7 ENUM 0 disable channle 6 0 1 enable channle 6 1 ADCIMSC7 ADC channle 7 interrupt enable config bit 7 8 ENUM 0 disable channle 7 0 1 enable channle 7 1 ADCIMSC8 ADC channle 8 interrupt enable config bit 8 9 ENUM 0 disable channle 8 0 1 enable channle 8 1 ADCIMSC9 ADC channle 9 interrupt enable config bit 9 10 ENUM 0 disable channle 9 0 1 enable channle 9 1 ADCMIS ADC Masked Interrupt Status Register. 0x50 -1 read-only n 0x0 0x0 ADCMIS0 ADC channle 0 interrupt status 0 1 ADCMIS1 ADC channle 1 interrupt status 1 2 ADCMIS10 ADC channle 10 interrupt status 10 11 ADCMIS11 ADC channle 11 interrupt status 11 12 ADCMIS12 ADC channle 12 interrupt status 12 13 ADCMIS13 ADC channle 13 interrupt status 13 14 ADCMIS14 ADC channle 14 interrupt status 14 15 ADCMIS15 ADC channle 14 interrupt status 15 16 ADCMIS2 ADC channle 2 interrupt status 2 3 ADCMIS3 ADC channle 3 interrupt status 3 4 ADCMIS4 ADC channle 4 interrupt status 4 5 ADCMIS5 ADC channle 5 interrupt status 5 6 ADCMIS6 ADC channle 6 interrupt status 6 7 ADCMIS7 ADC channle 7 interrupt status 7 8 ADCMIS8 ADC channle 8 interrupt status 8 9 ADCMIS9 ADC channle 9 interrupt status 9 10 ADCRIS ADC Raw Interrupt Status Register. 0x4C -1 write-only n 0x0 0x0 ADCRIS0 ADC channle 0 interrupt source status 0 1 ADCRIS1 ADC channle 1 interrupt source status 1 2 ADCRIS10 ADC channle 10 interrupt source status 10 11 ADCRIS11 ADC channle 11 interrupt source status 11 12 ADCRIS12 ADC channle 12 interrupt source status 12 13 ADCRIS13 ADC channle 13 interrupt source status 13 14 ADCRIS14 ADC channle 14 interrupt source status 14 15 ADCRIS15 ADC channle 15 interrupt source status 15 16 ADCRIS2 ADC channle 2 interrupt source status 2 3 ADCRIS3 ADC channle 3 interrupt source status 3 4 ADCRIS4 ADC channle 4 interrupt source status 4 5 ADCRIS5 ADC channle 5 interrupt source status 5 6 ADCRIS6 ADC channle 6 interrupt source status 6 7 ADCRIS7 ADC channle 7 interrupt source status 7 8 ADCRIS8 ADC channle 8 interrupt source status 8 9 ADCRIS9 ADC channle 9 interrupt source status 9 10 ADCSCAN ADC Scan register 0x4 -1 read-write n 0x0 0x0 ADCE0 ADC channle 0 enable bit 0 1 ENUM disable disable channle 0 0 enable enable channle 0 1 ADCE1 ADC channle 1 enable bit 1 2 ENUM disable disable channle 1 0 enable enable channle 1 1 ADCE10 ADC channle 10 enable bit 10 11 ENUM disable disable channle 10 0 enable enable channle 10 1 ADCE11 ADC channle 11 enable bit 11 12 ENUM disable disable channle 11 0 enable enable channle 11 1 ADCE12 ADC channle 12 enable bit 12 13 ENUM disable disable channle 12 0 enable enable channle 12 1 ADCE13 ADC channle 0 enable bit 13 14 ENUM disable disable channle 13 0 enable enable channle 13 1 ADCE14 ADC channle 14 enable bit 14 15 ENUM disable disable channle 14 0 enable enable channle 14 1 ADCE15 ADC channle 15 enable bit 15 16 ENUM disable disable channle 15 0 enable enable channle 15 1 ADCE2 ADC channle 2 enable bit 2 3 ENUM disable disable channle 2 0 enable enable channle 2 1 ADCE3 ADC channle 3 enable bit 3 4 ENUM disable disable channle 3 0 enable enable channle 3 1 ADCE4 ADC channle 4 enable bit 4 5 ENUM disable disable channle 4 0 enable enable channle 4 1 ADCE5 ADC channle 5 enable bit 5 6 ENUM disable disable channle 5 0 enable enable channle 5 1 ADCE6 ADC channle 6 enable bit 6 7 ENUM disable disable channle 6 0 enable enable channle 6 1 ADCE7 ADC channle 7 enable bit 7 8 ENUM disable disable channle 7 0 enable enable channle 7 1 ADCE8 ADC channle 8 enable bit 8 9 ENUM disable disable channle 8 0 enable enable channle 8 1 ADCE9 ADC channle 9 enable bit 9 10 ENUM disable disable channle 9 0 enable enable channle 9 1 ADCST ADC start convesion. 16 17 ENUM 0 end conversion 0 1 start conversion 1 EPWM EPWM Decription EPWM 0x0 0x0 0xFFF registers n EPWM EPWM IRQ 8 BRKCTL BRKCTL Description 0x40 32 read-write n 0x0 0x0 CLKDIV CLKDIV Description 0x4 32 read-write n 0x0 0x0 CLKPSC CLKPSC Description 0x0 32 read-write n 0x0 0x0 CMPDAT0 CMPDAT0 Description 0x24 32 read-write n 0x0 0x0 CMPDAT1 CMPDAT1 Description 0x28 32 read-write n 0x0 0x0 CMPDAT2 CMPDAT2 Description 0x2C 32 read-write n 0x0 0x0 CMPDAT3 CMPDAT3 Description 0x30 32 read-write n 0x0 0x0 CMPDAT4 CMPDAT4 Description 0x34 32 read-write n 0x0 0x0 CMPDAT5 CMPDAT5 Description 0x38 32 read-write n 0x0 0x0 CON CON Description 0x8 32 read-write n 0x0 0x0 DTCTL DTCTL Description 0x44 32 read-write n 0x0 0x0 ICLR ICLR Description 0x54 32 write-only n 0x0 0x0 IFA IFA Description 0x58 32 read-write n 0x0 0x0 IMSC IMSC Description 0x48 32 read-write n 0x0 0x0 LOCK LOCK Description 0x5C 32 read-write n 0x0 0x0 MIS MIS Description 0x50 32 read-only n 0x0 0x0 PERIOD0 PERIOD0 Description 0xC 32 read-write n 0x0 0x0 PERIOD1 PERIOD1 Description 0x10 32 read-write n 0x0 0x0 PERIOD2 PERIOD2 Description 0x14 32 read-write n 0x0 0x0 PERIOD3 PERIOD3 Description 0x18 32 read-write n 0x0 0x0 PERIOD4 PERIOD4 Description 0x1C 32 read-write n 0x0 0x0 PERIOD5 PERIOD5 Description 0x20 32 read-write n 0x0 0x0 POEN POEN Description 0x3C 32 read-write n 0x0 0x0 RIS RIS Description 0x4C 32 read-only n 0x0 0x0 FMC FMC Control Register. FMC 0x0 0x0 0xFFF registers n ADR FMC Address Register. 0x4 -1 read-write n 0x0 0x0 ADDR0 keep 2'b00. 0 2 read-only ADDR2 It supports word operation. 2 29 CMD FMC Command Register. 0xC -1 read-write n 0x0 0x0 FUNC FMC function 0 3 ENUM default default 0 Read data read data 1 Write data Write data 2 Page erasure page erasure 3 All erasure all erasure 6 CON FMC Control Register. 0x0 -1 read-write n 0x0 0x0 FMCB FMC Busy 5 6 ENUM Normal operation FMC normal operation 0 Busy FMC Busy 1 FMCE Flash Boot Address Mapping Enable. 4 5 ENUM Boot from ISP ROM Flash mapping is enabled. Boot from ISP ROM 0 Boot from Flash Rom Flash mapping is disable. 1 DAT FMC Data Register. 0x8 -1 read-write n 0x0 0x0 DAT FMC Data register 0 32 LOCK FMC Lock Register. 0x10 -1 read-write n 0x0 0x0 LOCK write 0x55AA6699,enable FMC other register.write other value,disable FMC other register. 0 32 ENUM disable write 0x00. 0x00 enable write 0x55AA6699. 0x55AA6699 GPIO0 General Purpose I/O GPIO 0x0 0x0 0xFFF registers n DI GPIO x Data Input Register. 0xC -1 read-only n 0x0 0x0 DIx0 Px.0 0 1 ENUM 0 0 0 1 1 1 DIx1 Px.1 1 2 ENUM 0 0 0 1 1 1 DIx2 Px.2 2 3 ENUM 0 0 0 1 1 1 DIx3 Px.3 3 4 ENUM 0 0 0 1 1 1 DIx4 Px.4 4 5 ENUM 0 0 0 1 1 1 DIx5 Px.5 5 6 ENUM 0 0 0 1 1 1 DIx6 Px6 6 7 ENUM 0 0 0 1 1 1 DIx7 Px.7 7 8 ENUM 0 0 0 1 1 1 DIDB GPIO x Data Input De-bounce Register. 0x2C -1 read-write n 0x0 0x0 DIDB0 Px.0 input De-bounce. 0 1 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB1 Px.1 input De-bounce. 1 2 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB2 Px.2 input De-bounce. 2 3 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB3 Px.3 input De-bounce. 3 4 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB4 Px.4 input De-bounce. 4 5 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB5 Px.5 input De-bounce. 5 6 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB6 Px.6 input De-bounce. 6 7 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB7 Px.7 input De-bounce. 7 8 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DO GPIO x Data Output Write Mask Register. 0x8 -1 read-write n 0x0 0x0 DOx0 Px.0 0 1 ENUM 0 0 0 1 1 1 DOx1 Px.1 1 2 ENUM 0 0 0 1 1 1 DOx2 Px.2 2 3 ENUM 0 0 0 1 1 1 DOx3 Px.3 3 4 ENUM 0 0 0 1 1 1 DOx4 Px.4 4 5 ENUM 0 0 0 1 1 1 DOx5 Px.5 5 6 ENUM 0 0 0 1 1 1 DOx6 Px.6 6 7 ENUM 0 0 0 1 1 1 DOx7 Px.7 7 8 ENUM 0 0 0 1 1 1 DOCLR GPIO x Data Output Clear Register 0x34 -1 write-only n 0x0 0x0 DOC0 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 0 1 ENUM no effect no effect 0 clear to low clear to low 1 DOC1 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 1 2 ENUM no effect no effect 0 clear to low clear to low 1 DOC2 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 2 3 ENUM no effect no effect 0 clear to low clear to low 1 DOC3 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 3 4 ENUM no effect no effect 0 clear to low clear to low 1 DOC4 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 4 5 ENUM no effect no effect 0 clear to low clear to low 1 DOC5 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 5 6 ENUM no effect no effect 0 clear to low clear to low 1 DOC6 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 6 7 ENUM no effect no effect 0 clear to low clear to low 1 DOC7 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 7 8 ENUM no effect no effect 0 clear to low clear to low 1 DOM GPIO x Data Output Write Mask Register. 0x4 -1 read-write n 0x0 0x0 DOMx0 Data Output Write Mask Register. 0 1 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx1 Data Output Write Mask Register. 1 2 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx2 Data Output Write Mask Register. 2 3 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx3 Data Output Write Mask Register. 3 4 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx4 Data Output Write Mask Register. 4 5 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx5 Data Output Write Mask Register. 5 6 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx6 Data Output Write Mask Register. 6 7 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx7 Data Output Write Mask Register. 7 8 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOSET GPIO x Data Output Set Register. 0x30 -1 write-only n 0x0 0x0 DOS0 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 0 1 ENUM no effect no effect 0 set to high set to high 1 DOS1 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 1 2 ENUM no effect no effect 0 set to high set to high 1 DOS2 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 2 3 ENUM no effect no effect 0 set to high set to high 1 DOS3 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 3 4 ENUM no effect no effect 0 set to high set to high 1 DOS4 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 4 5 ENUM no effect no effect 0 set to high set to high 1 DOS5 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 5 6 ENUM no effect no effect 0 set to high set to high 1 DOS6 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 6 7 ENUM no effect no effect 0 set to high set to high 1 DOS7 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 7 8 ENUM no effect no effect 0 set to high set to high 1 DR GPIO x Drive current Set Register. 0x38 -1 read-write n 0x0 0x0 DR0 Drive curent set bit. 0 1 ENUM set to low large current. 0 set to high. low current. 1 DR1 Drive curent set bit. 1 2 ENUM set to low large current. 0 set to high. low current. 1 DR2 Drive curent set bit. 2 3 ENUM set to low large current. 0 set to high. low current. 1 DR3 Drive curent set bit. 3 4 ENUM set to low large current. 0 set to high. low current. 1 DR4 Drive curent set bit. 4 5 ENUM set to low large current. 0 set to high. low current. 1 DR5 Drive curent set bit. 5 6 ENUM set to low large current. 0 set to high. low current. 1 DR6 Drive curent set bit. 6 7 ENUM set to low large current. 0 set to high. low current. 1 DR7 Drive curent set bit. 7 8 ENUM set to low large current. 0 set to high. low current. 1 IANY GPIO x Interrupt Any Edge Register. 0x28 -1 read-write n 0x0 0x0 IANY0 Px.0 interrupt Trigger Any Edge. 0 1 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY1 Px.1 interrupt Trigger Any Edge. 1 2 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY2 Px.2 interrupt Trigger Any Edge. 2 3 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY3 Px.3 interrupt Trigger Any Edge. 3 4 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY4 Px.4 interrupt Trigger Any Edge. 4 5 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY5 Px.5 interrupt Trigger Any Edge. 5 6 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY6 Px.6 interrupt Trigger Any Edge. 6 7 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY7 Px.7 interrupt Trigger Any Edge. 7 8 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 ICLR GPIO x Interrupt Clear Register 0x1C -1 write-only n 0x0 0x0 MIS0 Writing a 1 to this bit clears PX.0 interrupt status 0 1 ENUM 0 0 0 1 1 1 MIS1 Writing a 1 to this bit clears PX.1 interrupt status 1 2 ENUM 0 0 0 1 1 1 MIS2 Writing a 1 to this bit clears PX.2 interrupt status 2 3 ENUM 0 0 0 1 1 1 MIS3 Writing a 1 to this bit clears PX.3 interrupt status 3 4 ENUM 0 0 0 1 1 1 MIS4 Writing a 1 to this bit clears PX.4 interrupt status 4 5 ENUM 0 0 0 1 1 1 MIS5 Writing a 1 to this bit clears PX.5 interrupt status 5 6 ENUM 0 0 0 1 1 1 MIS6 Writing a 1 to this bit clears PX.6 interrupt status 6 7 ENUM 0 0 0 1 1 1 MIS7 Writing a 1 to this bit clears PX.7 interrupt status 7 8 ENUM 0 0 0 1 1 1 IMSC GPIO x Interrupt Mask Set and Clear Register. 0x10 -1 read-write n 0x0 0x0 IMSC0 Px.0 interrupt mask set and clear register 0 1 ENUM 0 0 0 1 1 1 IMSC1 Px.1 interrupt mask set and clear register 1 2 ENUM 0 0 0 1 1 1 IMSC2 Px.2 interrupt mask set and clear register 2 3 ENUM 0 0 0 1 1 1 IMSC3 Px.3 interrupt mask set and clear register 3 4 ENUM 0 0 0 1 1 1 IMSC4 Px.4 interrupt mask set and clear register 4 5 ENUM 0 0 0 1 1 1 IMSC5 Px.5 interrupt mask set and clear register 5 6 ENUM 0 0 0 1 1 1 IMSC6 Px.6 interrupt mask set and clear register 6 7 ENUM 0 0 0 1 1 1 IMSC7 Px.7 interrupt mask set and clear register 7 8 ENUM 0 0 0 1 1 1 ITYPE GPIO x Interrupt Type Register 0x20 -1 read-write n 0x0 0x0 ITYPE0 Px.0 interrupt Type Register. 0 1 ENUM 0 0 0 1 1 1 ITYPE1 Px.1 interrupt Type Register. 1 2 ENUM 0 0 0 1 1 1 ITYPE2 Px.2 interrupt Type Register. 2 3 ENUM 0 0 0 1 1 1 ITYPE3 Px.3 interrupt Type Register. 3 4 ENUM 0 0 0 1 1 1 ITYPE4 Px.4 interrupt Type Register. 4 5 ENUM 0 0 0 1 1 1 ITYPE5 Px.5 interrupt Type Register. 5 6 ENUM 0 0 0 1 1 1 ITYPE6 Px.6 interrupt Type Register. 6 7 ENUM 0 0 0 1 1 1 ITYPE7 Px.7 interrupt Type Register. 7 8 ENUM 0 0 0 1 1 1 IVAL GPIO x Interrupt Value Register 0x24 -1 read-write n 0x0 0x0 IVAL0 Px.0 interrupt Trigger Value. 0 1 ENUM 0 0 0 1 1 1 IVAL1 Px.1 interrupt Trigger Value. 1 2 ENUM 0 0 0 1 1 1 IVAL2 Px.2 interrupt Trigger Value. 2 3 ENUM 0 0 0 1 1 1 IVAL3 Px.3 interrupt Trigger Value. 3 4 ENUM 0 0 0 1 1 1 IVAL4 Px.4 interrupt Trigger Value. 4 5 ENUM 0 0 0 1 1 1 IVAL5 Px.5 interrupt Trigger Value. 5 6 ENUM 0 0 0 1 1 1 IVAL6 Px.6 interrupt Trigger Value. 6 7 ENUM 0 0 0 1 1 1 IVAL7 Px.7 interrupt Trigger Value. 7 8 ENUM 0 0 0 1 1 1 MIS GPIO x Masked Interrupt Status Register. 0x18 -1 read-only n 0x0 0x0 MIS0 Px.0 Masked interrupt status 0 1 ENUM 0 0 0 1 1 1 MIS1 Px.1 Masked interrupt status 1 2 ENUM 0 0 0 1 1 1 MIS2 Px.2 Masked interrupt status 2 3 ENUM 0 0 0 1 1 1 MIS3 Px.3 Masked interrupt status 3 4 ENUM 0 0 0 1 1 1 MIS4 Px.4 Masked interrupt status 4 5 ENUM 0 0 0 1 1 1 MIS5 Px.5 Masked interrupt status 5 6 ENUM 0 0 0 1 1 1 MIS6 Px.6 Masked interrupt status 6 7 ENUM 0 0 0 1 1 1 MIS7 Px.7 Masked interrupt status 7 8 ENUM 0 0 0 1 1 1 PMS GPIO x Pin Mode Select Register 0x0 -1 read-write n 0x0 0x0 PMS0 Px.0 0 2 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS1 Px.1 2 4 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS2 Px.2 4 6 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS3 Px.3 6 8 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS4 Px.4 8 10 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS5 Px.5 10 12 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS6 Px.6 12 14 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS7 Px.7 14 16 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 RIS GPIO x Raw Interrupt Status Register. 0x14 -1 read-only n 0x0 0x0 RIS0 Px.0 raw interrupt status 0 1 ENUM 0 0 0 1 1 1 RIS1 Px.1 raw interrupt status 1 2 ENUM 0 0 0 1 1 1 RIS2 Px.2 raw interrupt status 2 3 ENUM 0 0 0 1 1 1 RIS3 Px.3 raw interrupt status 3 4 ENUM 0 0 0 1 1 1 RIS4 Px.4 raw interrupt status 4 5 ENUM 0 0 0 1 1 1 RIS5 Px.5 raw interrupt status 5 6 ENUM 0 0 0 1 1 1 RIS6 Px.6 raw interrupt status 6 7 ENUM 0 0 0 1 1 1 RIS7 Px.7 raw interrupt status 7 8 ENUM 0 0 0 1 1 1 SR GPIO x Drive rate Register. 0x3C -1 read-write n 0x0 0x0 SR0 Drive rate set bit. 0 1 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR1 Drive rate set bit. 1 2 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR2 Drive rate set bit. 2 3 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR3 Drive rate set bit. 3 4 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR4 Drive rate set bit. 4 5 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR5 Drive rate set bit. 5 6 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR6 Drive rate set bit. 6 7 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR7 Drive rate set bit. 7 8 ENUM clear to low high speed rate. 0 set to high low speed rate 1 GPIO1 General Purpose I/O GPIO 0x0 0x0 0xFFF registers n DI GPIO x Data Input Register. 0xC -1 read-only n 0x0 0x0 DIx0 Px.0 0 1 ENUM 0 0 0 1 1 1 DIx1 Px.1 1 2 ENUM 0 0 0 1 1 1 DIx2 Px.2 2 3 ENUM 0 0 0 1 1 1 DIx3 Px.3 3 4 ENUM 0 0 0 1 1 1 DIx4 Px.4 4 5 ENUM 0 0 0 1 1 1 DIx5 Px.5 5 6 ENUM 0 0 0 1 1 1 DIx6 Px6 6 7 ENUM 0 0 0 1 1 1 DIx7 Px.7 7 8 ENUM 0 0 0 1 1 1 DIDB GPIO x Data Input De-bounce Register. 0x2C -1 read-write n 0x0 0x0 DIDB0 Px.0 input De-bounce. 0 1 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB1 Px.1 input De-bounce. 1 2 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB2 Px.2 input De-bounce. 2 3 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB3 Px.3 input De-bounce. 3 4 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB4 Px.4 input De-bounce. 4 5 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB5 Px.5 input De-bounce. 5 6 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB6 Px.6 input De-bounce. 6 7 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB7 Px.7 input De-bounce. 7 8 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DO GPIO x Data Output Write Mask Register. 0x8 -1 read-write n 0x0 0x0 DOx0 Px.0 0 1 ENUM 0 0 0 1 1 1 DOx1 Px.1 1 2 ENUM 0 0 0 1 1 1 DOx2 Px.2 2 3 ENUM 0 0 0 1 1 1 DOx3 Px.3 3 4 ENUM 0 0 0 1 1 1 DOx4 Px.4 4 5 ENUM 0 0 0 1 1 1 DOx5 Px.5 5 6 ENUM 0 0 0 1 1 1 DOx6 Px.6 6 7 ENUM 0 0 0 1 1 1 DOx7 Px.7 7 8 ENUM 0 0 0 1 1 1 DOCLR GPIO x Data Output Clear Register 0x34 -1 write-only n 0x0 0x0 DOC0 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 0 1 ENUM no effect no effect 0 clear to low clear to low 1 DOC1 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 1 2 ENUM no effect no effect 0 clear to low clear to low 1 DOC2 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 2 3 ENUM no effect no effect 0 clear to low clear to low 1 DOC3 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 3 4 ENUM no effect no effect 0 clear to low clear to low 1 DOC4 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 4 5 ENUM no effect no effect 0 clear to low clear to low 1 DOC5 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 5 6 ENUM no effect no effect 0 clear to low clear to low 1 DOC6 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 6 7 ENUM no effect no effect 0 clear to low clear to low 1 DOC7 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 7 8 ENUM no effect no effect 0 clear to low clear to low 1 DOM GPIO x Data Output Write Mask Register. 0x4 -1 read-write n 0x0 0x0 DOMx0 Data Output Write Mask Register. 0 1 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx1 Data Output Write Mask Register. 1 2 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx2 Data Output Write Mask Register. 2 3 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx3 Data Output Write Mask Register. 3 4 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx4 Data Output Write Mask Register. 4 5 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx5 Data Output Write Mask Register. 5 6 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx6 Data Output Write Mask Register. 6 7 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx7 Data Output Write Mask Register. 7 8 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOSET GPIO x Data Output Set Register. 0x30 -1 write-only n 0x0 0x0 DOS0 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 0 1 ENUM no effect no effect 0 set to high set to high 1 DOS1 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 1 2 ENUM no effect no effect 0 set to high set to high 1 DOS2 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 2 3 ENUM no effect no effect 0 set to high set to high 1 DOS3 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 3 4 ENUM no effect no effect 0 set to high set to high 1 DOS4 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 4 5 ENUM no effect no effect 0 set to high set to high 1 DOS5 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 5 6 ENUM no effect no effect 0 set to high set to high 1 DOS6 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 6 7 ENUM no effect no effect 0 set to high set to high 1 DOS7 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 7 8 ENUM no effect no effect 0 set to high set to high 1 DR GPIO x Drive current Set Register. 0x38 -1 read-write n 0x0 0x0 DR0 Drive curent set bit. 0 1 ENUM set to low large current. 0 set to high. low current. 1 DR1 Drive curent set bit. 1 2 ENUM set to low large current. 0 set to high. low current. 1 DR2 Drive curent set bit. 2 3 ENUM set to low large current. 0 set to high. low current. 1 DR3 Drive curent set bit. 3 4 ENUM set to low large current. 0 set to high. low current. 1 DR4 Drive curent set bit. 4 5 ENUM set to low large current. 0 set to high. low current. 1 DR5 Drive curent set bit. 5 6 ENUM set to low large current. 0 set to high. low current. 1 DR6 Drive curent set bit. 6 7 ENUM set to low large current. 0 set to high. low current. 1 DR7 Drive curent set bit. 7 8 ENUM set to low large current. 0 set to high. low current. 1 IANY GPIO x Interrupt Any Edge Register. 0x28 -1 read-write n 0x0 0x0 IANY0 Px.0 interrupt Trigger Any Edge. 0 1 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY1 Px.1 interrupt Trigger Any Edge. 1 2 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY2 Px.2 interrupt Trigger Any Edge. 2 3 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY3 Px.3 interrupt Trigger Any Edge. 3 4 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY4 Px.4 interrupt Trigger Any Edge. 4 5 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY5 Px.5 interrupt Trigger Any Edge. 5 6 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY6 Px.6 interrupt Trigger Any Edge. 6 7 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY7 Px.7 interrupt Trigger Any Edge. 7 8 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 ICLR GPIO x Interrupt Clear Register 0x1C -1 write-only n 0x0 0x0 MIS0 Writing a 1 to this bit clears PX.0 interrupt status 0 1 ENUM 0 0 0 1 1 1 MIS1 Writing a 1 to this bit clears PX.1 interrupt status 1 2 ENUM 0 0 0 1 1 1 MIS2 Writing a 1 to this bit clears PX.2 interrupt status 2 3 ENUM 0 0 0 1 1 1 MIS3 Writing a 1 to this bit clears PX.3 interrupt status 3 4 ENUM 0 0 0 1 1 1 MIS4 Writing a 1 to this bit clears PX.4 interrupt status 4 5 ENUM 0 0 0 1 1 1 MIS5 Writing a 1 to this bit clears PX.5 interrupt status 5 6 ENUM 0 0 0 1 1 1 MIS6 Writing a 1 to this bit clears PX.6 interrupt status 6 7 ENUM 0 0 0 1 1 1 MIS7 Writing a 1 to this bit clears PX.7 interrupt status 7 8 ENUM 0 0 0 1 1 1 IMSC GPIO x Interrupt Mask Set and Clear Register. 0x10 -1 read-write n 0x0 0x0 IMSC0 Px.0 interrupt mask set and clear register 0 1 ENUM 0 0 0 1 1 1 IMSC1 Px.1 interrupt mask set and clear register 1 2 ENUM 0 0 0 1 1 1 IMSC2 Px.2 interrupt mask set and clear register 2 3 ENUM 0 0 0 1 1 1 IMSC3 Px.3 interrupt mask set and clear register 3 4 ENUM 0 0 0 1 1 1 IMSC4 Px.4 interrupt mask set and clear register 4 5 ENUM 0 0 0 1 1 1 IMSC5 Px.5 interrupt mask set and clear register 5 6 ENUM 0 0 0 1 1 1 IMSC6 Px.6 interrupt mask set and clear register 6 7 ENUM 0 0 0 1 1 1 IMSC7 Px.7 interrupt mask set and clear register 7 8 ENUM 0 0 0 1 1 1 ITYPE GPIO x Interrupt Type Register 0x20 -1 read-write n 0x0 0x0 ITYPE0 Px.0 interrupt Type Register. 0 1 ENUM 0 0 0 1 1 1 ITYPE1 Px.1 interrupt Type Register. 1 2 ENUM 0 0 0 1 1 1 ITYPE2 Px.2 interrupt Type Register. 2 3 ENUM 0 0 0 1 1 1 ITYPE3 Px.3 interrupt Type Register. 3 4 ENUM 0 0 0 1 1 1 ITYPE4 Px.4 interrupt Type Register. 4 5 ENUM 0 0 0 1 1 1 ITYPE5 Px.5 interrupt Type Register. 5 6 ENUM 0 0 0 1 1 1 ITYPE6 Px.6 interrupt Type Register. 6 7 ENUM 0 0 0 1 1 1 ITYPE7 Px.7 interrupt Type Register. 7 8 ENUM 0 0 0 1 1 1 IVAL GPIO x Interrupt Value Register 0x24 -1 read-write n 0x0 0x0 IVAL0 Px.0 interrupt Trigger Value. 0 1 ENUM 0 0 0 1 1 1 IVAL1 Px.1 interrupt Trigger Value. 1 2 ENUM 0 0 0 1 1 1 IVAL2 Px.2 interrupt Trigger Value. 2 3 ENUM 0 0 0 1 1 1 IVAL3 Px.3 interrupt Trigger Value. 3 4 ENUM 0 0 0 1 1 1 IVAL4 Px.4 interrupt Trigger Value. 4 5 ENUM 0 0 0 1 1 1 IVAL5 Px.5 interrupt Trigger Value. 5 6 ENUM 0 0 0 1 1 1 IVAL6 Px.6 interrupt Trigger Value. 6 7 ENUM 0 0 0 1 1 1 IVAL7 Px.7 interrupt Trigger Value. 7 8 ENUM 0 0 0 1 1 1 MIS GPIO x Masked Interrupt Status Register. 0x18 -1 read-only n 0x0 0x0 MIS0 Px.0 Masked interrupt status 0 1 ENUM 0 0 0 1 1 1 MIS1 Px.1 Masked interrupt status 1 2 ENUM 0 0 0 1 1 1 MIS2 Px.2 Masked interrupt status 2 3 ENUM 0 0 0 1 1 1 MIS3 Px.3 Masked interrupt status 3 4 ENUM 0 0 0 1 1 1 MIS4 Px.4 Masked interrupt status 4 5 ENUM 0 0 0 1 1 1 MIS5 Px.5 Masked interrupt status 5 6 ENUM 0 0 0 1 1 1 MIS6 Px.6 Masked interrupt status 6 7 ENUM 0 0 0 1 1 1 MIS7 Px.7 Masked interrupt status 7 8 ENUM 0 0 0 1 1 1 PMS GPIO x Pin Mode Select Register 0x0 -1 read-write n 0x0 0x0 PMS0 Px.0 0 2 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS1 Px.1 2 4 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS2 Px.2 4 6 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS3 Px.3 6 8 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS4 Px.4 8 10 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS5 Px.5 10 12 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS6 Px.6 12 14 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS7 Px.7 14 16 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 RIS GPIO x Raw Interrupt Status Register. 0x14 -1 read-only n 0x0 0x0 RIS0 Px.0 raw interrupt status 0 1 ENUM 0 0 0 1 1 1 RIS1 Px.1 raw interrupt status 1 2 ENUM 0 0 0 1 1 1 RIS2 Px.2 raw interrupt status 2 3 ENUM 0 0 0 1 1 1 RIS3 Px.3 raw interrupt status 3 4 ENUM 0 0 0 1 1 1 RIS4 Px.4 raw interrupt status 4 5 ENUM 0 0 0 1 1 1 RIS5 Px.5 raw interrupt status 5 6 ENUM 0 0 0 1 1 1 RIS6 Px.6 raw interrupt status 6 7 ENUM 0 0 0 1 1 1 RIS7 Px.7 raw interrupt status 7 8 ENUM 0 0 0 1 1 1 SR GPIO x Drive rate Register. 0x3C -1 read-write n 0x0 0x0 SR0 Drive rate set bit. 0 1 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR1 Drive rate set bit. 1 2 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR2 Drive rate set bit. 2 3 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR3 Drive rate set bit. 3 4 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR4 Drive rate set bit. 4 5 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR5 Drive rate set bit. 5 6 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR6 Drive rate set bit. 6 7 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR7 Drive rate set bit. 7 8 ENUM clear to low high speed rate. 0 set to high low speed rate 1 GPIO2 General Purpose I/O GPIO 0x0 0x0 0xFFF registers n DI GPIO x Data Input Register. 0xC -1 read-only n 0x0 0x0 DIx0 Px.0 0 1 ENUM 0 0 0 1 1 1 DIx1 Px.1 1 2 ENUM 0 0 0 1 1 1 DIx2 Px.2 2 3 ENUM 0 0 0 1 1 1 DIx3 Px.3 3 4 ENUM 0 0 0 1 1 1 DIx4 Px.4 4 5 ENUM 0 0 0 1 1 1 DIx5 Px.5 5 6 ENUM 0 0 0 1 1 1 DIx6 Px6 6 7 ENUM 0 0 0 1 1 1 DIx7 Px.7 7 8 ENUM 0 0 0 1 1 1 DIDB GPIO x Data Input De-bounce Register. 0x2C -1 read-write n 0x0 0x0 DIDB0 Px.0 input De-bounce. 0 1 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB1 Px.1 input De-bounce. 1 2 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB2 Px.2 input De-bounce. 2 3 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB3 Px.3 input De-bounce. 3 4 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB4 Px.4 input De-bounce. 4 5 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB5 Px.5 input De-bounce. 5 6 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB6 Px.6 input De-bounce. 6 7 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB7 Px.7 input De-bounce. 7 8 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DO GPIO x Data Output Write Mask Register. 0x8 -1 read-write n 0x0 0x0 DOx0 Px.0 0 1 ENUM 0 0 0 1 1 1 DOx1 Px.1 1 2 ENUM 0 0 0 1 1 1 DOx2 Px.2 2 3 ENUM 0 0 0 1 1 1 DOx3 Px.3 3 4 ENUM 0 0 0 1 1 1 DOx4 Px.4 4 5 ENUM 0 0 0 1 1 1 DOx5 Px.5 5 6 ENUM 0 0 0 1 1 1 DOx6 Px.6 6 7 ENUM 0 0 0 1 1 1 DOx7 Px.7 7 8 ENUM 0 0 0 1 1 1 DOCLR GPIO x Data Output Clear Register 0x34 -1 write-only n 0x0 0x0 DOC0 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 0 1 ENUM no effect no effect 0 clear to low clear to low 1 DOC1 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 1 2 ENUM no effect no effect 0 clear to low clear to low 1 DOC2 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 2 3 ENUM no effect no effect 0 clear to low clear to low 1 DOC3 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 3 4 ENUM no effect no effect 0 clear to low clear to low 1 DOC4 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 4 5 ENUM no effect no effect 0 clear to low clear to low 1 DOC5 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 5 6 ENUM no effect no effect 0 clear to low clear to low 1 DOC6 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 6 7 ENUM no effect no effect 0 clear to low clear to low 1 DOC7 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 7 8 ENUM no effect no effect 0 clear to low clear to low 1 DOM GPIO x Data Output Write Mask Register. 0x4 -1 read-write n 0x0 0x0 DOMx0 Data Output Write Mask Register. 0 1 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx1 Data Output Write Mask Register. 1 2 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx2 Data Output Write Mask Register. 2 3 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx3 Data Output Write Mask Register. 3 4 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx4 Data Output Write Mask Register. 4 5 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx5 Data Output Write Mask Register. 5 6 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx6 Data Output Write Mask Register. 6 7 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx7 Data Output Write Mask Register. 7 8 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOSET GPIO x Data Output Set Register. 0x30 -1 write-only n 0x0 0x0 DOS0 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 0 1 ENUM no effect no effect 0 set to high set to high 1 DOS1 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 1 2 ENUM no effect no effect 0 set to high set to high 1 DOS2 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 2 3 ENUM no effect no effect 0 set to high set to high 1 DOS3 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 3 4 ENUM no effect no effect 0 set to high set to high 1 DOS4 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 4 5 ENUM no effect no effect 0 set to high set to high 1 DOS5 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 5 6 ENUM no effect no effect 0 set to high set to high 1 DOS6 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 6 7 ENUM no effect no effect 0 set to high set to high 1 DOS7 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 7 8 ENUM no effect no effect 0 set to high set to high 1 DR GPIO x Drive current Set Register. 0x38 -1 read-write n 0x0 0x0 DR0 Drive curent set bit. 0 1 ENUM set to low large current. 0 set to high. low current. 1 DR1 Drive curent set bit. 1 2 ENUM set to low large current. 0 set to high. low current. 1 DR2 Drive curent set bit. 2 3 ENUM set to low large current. 0 set to high. low current. 1 DR3 Drive curent set bit. 3 4 ENUM set to low large current. 0 set to high. low current. 1 DR4 Drive curent set bit. 4 5 ENUM set to low large current. 0 set to high. low current. 1 DR5 Drive curent set bit. 5 6 ENUM set to low large current. 0 set to high. low current. 1 DR6 Drive curent set bit. 6 7 ENUM set to low large current. 0 set to high. low current. 1 DR7 Drive curent set bit. 7 8 ENUM set to low large current. 0 set to high. low current. 1 IANY GPIO x Interrupt Any Edge Register. 0x28 -1 read-write n 0x0 0x0 IANY0 Px.0 interrupt Trigger Any Edge. 0 1 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY1 Px.1 interrupt Trigger Any Edge. 1 2 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY2 Px.2 interrupt Trigger Any Edge. 2 3 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY3 Px.3 interrupt Trigger Any Edge. 3 4 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY4 Px.4 interrupt Trigger Any Edge. 4 5 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY5 Px.5 interrupt Trigger Any Edge. 5 6 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY6 Px.6 interrupt Trigger Any Edge. 6 7 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY7 Px.7 interrupt Trigger Any Edge. 7 8 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 ICLR GPIO x Interrupt Clear Register 0x1C -1 write-only n 0x0 0x0 MIS0 Writing a 1 to this bit clears PX.0 interrupt status 0 1 ENUM 0 0 0 1 1 1 MIS1 Writing a 1 to this bit clears PX.1 interrupt status 1 2 ENUM 0 0 0 1 1 1 MIS2 Writing a 1 to this bit clears PX.2 interrupt status 2 3 ENUM 0 0 0 1 1 1 MIS3 Writing a 1 to this bit clears PX.3 interrupt status 3 4 ENUM 0 0 0 1 1 1 MIS4 Writing a 1 to this bit clears PX.4 interrupt status 4 5 ENUM 0 0 0 1 1 1 MIS5 Writing a 1 to this bit clears PX.5 interrupt status 5 6 ENUM 0 0 0 1 1 1 MIS6 Writing a 1 to this bit clears PX.6 interrupt status 6 7 ENUM 0 0 0 1 1 1 MIS7 Writing a 1 to this bit clears PX.7 interrupt status 7 8 ENUM 0 0 0 1 1 1 IMSC GPIO x Interrupt Mask Set and Clear Register. 0x10 -1 read-write n 0x0 0x0 IMSC0 Px.0 interrupt mask set and clear register 0 1 ENUM 0 0 0 1 1 1 IMSC1 Px.1 interrupt mask set and clear register 1 2 ENUM 0 0 0 1 1 1 IMSC2 Px.2 interrupt mask set and clear register 2 3 ENUM 0 0 0 1 1 1 IMSC3 Px.3 interrupt mask set and clear register 3 4 ENUM 0 0 0 1 1 1 IMSC4 Px.4 interrupt mask set and clear register 4 5 ENUM 0 0 0 1 1 1 IMSC5 Px.5 interrupt mask set and clear register 5 6 ENUM 0 0 0 1 1 1 IMSC6 Px.6 interrupt mask set and clear register 6 7 ENUM 0 0 0 1 1 1 IMSC7 Px.7 interrupt mask set and clear register 7 8 ENUM 0 0 0 1 1 1 ITYPE GPIO x Interrupt Type Register 0x20 -1 read-write n 0x0 0x0 ITYPE0 Px.0 interrupt Type Register. 0 1 ENUM 0 0 0 1 1 1 ITYPE1 Px.1 interrupt Type Register. 1 2 ENUM 0 0 0 1 1 1 ITYPE2 Px.2 interrupt Type Register. 2 3 ENUM 0 0 0 1 1 1 ITYPE3 Px.3 interrupt Type Register. 3 4 ENUM 0 0 0 1 1 1 ITYPE4 Px.4 interrupt Type Register. 4 5 ENUM 0 0 0 1 1 1 ITYPE5 Px.5 interrupt Type Register. 5 6 ENUM 0 0 0 1 1 1 ITYPE6 Px.6 interrupt Type Register. 6 7 ENUM 0 0 0 1 1 1 ITYPE7 Px.7 interrupt Type Register. 7 8 ENUM 0 0 0 1 1 1 IVAL GPIO x Interrupt Value Register 0x24 -1 read-write n 0x0 0x0 IVAL0 Px.0 interrupt Trigger Value. 0 1 ENUM 0 0 0 1 1 1 IVAL1 Px.1 interrupt Trigger Value. 1 2 ENUM 0 0 0 1 1 1 IVAL2 Px.2 interrupt Trigger Value. 2 3 ENUM 0 0 0 1 1 1 IVAL3 Px.3 interrupt Trigger Value. 3 4 ENUM 0 0 0 1 1 1 IVAL4 Px.4 interrupt Trigger Value. 4 5 ENUM 0 0 0 1 1 1 IVAL5 Px.5 interrupt Trigger Value. 5 6 ENUM 0 0 0 1 1 1 IVAL6 Px.6 interrupt Trigger Value. 6 7 ENUM 0 0 0 1 1 1 IVAL7 Px.7 interrupt Trigger Value. 7 8 ENUM 0 0 0 1 1 1 MIS GPIO x Masked Interrupt Status Register. 0x18 -1 read-only n 0x0 0x0 MIS0 Px.0 Masked interrupt status 0 1 ENUM 0 0 0 1 1 1 MIS1 Px.1 Masked interrupt status 1 2 ENUM 0 0 0 1 1 1 MIS2 Px.2 Masked interrupt status 2 3 ENUM 0 0 0 1 1 1 MIS3 Px.3 Masked interrupt status 3 4 ENUM 0 0 0 1 1 1 MIS4 Px.4 Masked interrupt status 4 5 ENUM 0 0 0 1 1 1 MIS5 Px.5 Masked interrupt status 5 6 ENUM 0 0 0 1 1 1 MIS6 Px.6 Masked interrupt status 6 7 ENUM 0 0 0 1 1 1 MIS7 Px.7 Masked interrupt status 7 8 ENUM 0 0 0 1 1 1 PMS GPIO x Pin Mode Select Register 0x0 -1 read-write n 0x0 0x0 PMS0 Px.0 0 2 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS1 Px.1 2 4 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS2 Px.2 4 6 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS3 Px.3 6 8 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS4 Px.4 8 10 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS5 Px.5 10 12 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS6 Px.6 12 14 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS7 Px.7 14 16 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 RIS GPIO x Raw Interrupt Status Register. 0x14 -1 read-only n 0x0 0x0 RIS0 Px.0 raw interrupt status 0 1 ENUM 0 0 0 1 1 1 RIS1 Px.1 raw interrupt status 1 2 ENUM 0 0 0 1 1 1 RIS2 Px.2 raw interrupt status 2 3 ENUM 0 0 0 1 1 1 RIS3 Px.3 raw interrupt status 3 4 ENUM 0 0 0 1 1 1 RIS4 Px.4 raw interrupt status 4 5 ENUM 0 0 0 1 1 1 RIS5 Px.5 raw interrupt status 5 6 ENUM 0 0 0 1 1 1 RIS6 Px.6 raw interrupt status 6 7 ENUM 0 0 0 1 1 1 RIS7 Px.7 raw interrupt status 7 8 ENUM 0 0 0 1 1 1 SR GPIO x Drive rate Register. 0x3C -1 read-write n 0x0 0x0 SR0 Drive rate set bit. 0 1 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR1 Drive rate set bit. 1 2 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR2 Drive rate set bit. 2 3 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR3 Drive rate set bit. 3 4 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR4 Drive rate set bit. 4 5 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR5 Drive rate set bit. 5 6 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR6 Drive rate set bit. 6 7 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR7 Drive rate set bit. 7 8 ENUM clear to low high speed rate. 0 set to high low speed rate 1 GPIO3 General Purpose I/O GPIO 0x0 0x0 0xFFF registers n DI GPIO x Data Input Register. 0xC -1 read-only n 0x0 0x0 DIx0 Px.0 0 1 ENUM 0 0 0 1 1 1 DIx1 Px.1 1 2 ENUM 0 0 0 1 1 1 DIx2 Px.2 2 3 ENUM 0 0 0 1 1 1 DIx3 Px.3 3 4 ENUM 0 0 0 1 1 1 DIx4 Px.4 4 5 ENUM 0 0 0 1 1 1 DIx5 Px.5 5 6 ENUM 0 0 0 1 1 1 DIx6 Px6 6 7 ENUM 0 0 0 1 1 1 DIx7 Px.7 7 8 ENUM 0 0 0 1 1 1 DIDB GPIO x Data Input De-bounce Register. 0x2C -1 read-write n 0x0 0x0 DIDB0 Px.0 input De-bounce. 0 1 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB1 Px.1 input De-bounce. 1 2 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB2 Px.2 input De-bounce. 2 3 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB3 Px.3 input De-bounce. 3 4 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB4 Px.4 input De-bounce. 4 5 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB5 Px.5 input De-bounce. 5 6 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB6 Px.6 input De-bounce. 6 7 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB7 Px.7 input De-bounce. 7 8 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DO GPIO x Data Output Write Mask Register. 0x8 -1 read-write n 0x0 0x0 DOx0 Px.0 0 1 ENUM 0 0 0 1 1 1 DOx1 Px.1 1 2 ENUM 0 0 0 1 1 1 DOx2 Px.2 2 3 ENUM 0 0 0 1 1 1 DOx3 Px.3 3 4 ENUM 0 0 0 1 1 1 DOx4 Px.4 4 5 ENUM 0 0 0 1 1 1 DOx5 Px.5 5 6 ENUM 0 0 0 1 1 1 DOx6 Px.6 6 7 ENUM 0 0 0 1 1 1 DOx7 Px.7 7 8 ENUM 0 0 0 1 1 1 DOCLR GPIO x Data Output Clear Register 0x34 -1 write-only n 0x0 0x0 DOC0 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 0 1 ENUM no effect no effect 0 clear to low clear to low 1 DOC1 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 1 2 ENUM no effect no effect 0 clear to low clear to low 1 DOC2 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 2 3 ENUM no effect no effect 0 clear to low clear to low 1 DOC3 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 3 4 ENUM no effect no effect 0 clear to low clear to low 1 DOC4 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 4 5 ENUM no effect no effect 0 clear to low clear to low 1 DOC5 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 5 6 ENUM no effect no effect 0 clear to low clear to low 1 DOC6 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 6 7 ENUM no effect no effect 0 clear to low clear to low 1 DOC7 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 7 8 ENUM no effect no effect 0 clear to low clear to low 1 DOM GPIO x Data Output Write Mask Register. 0x4 -1 read-write n 0x0 0x0 DOMx0 Data Output Write Mask Register. 0 1 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx1 Data Output Write Mask Register. 1 2 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx2 Data Output Write Mask Register. 2 3 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx3 Data Output Write Mask Register. 3 4 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx4 Data Output Write Mask Register. 4 5 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx5 Data Output Write Mask Register. 5 6 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx6 Data Output Write Mask Register. 6 7 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx7 Data Output Write Mask Register. 7 8 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOSET GPIO x Data Output Set Register. 0x30 -1 write-only n 0x0 0x0 DOS0 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 0 1 ENUM no effect no effect 0 set to high set to high 1 DOS1 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 1 2 ENUM no effect no effect 0 set to high set to high 1 DOS2 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 2 3 ENUM no effect no effect 0 set to high set to high 1 DOS3 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 3 4 ENUM no effect no effect 0 set to high set to high 1 DOS4 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 4 5 ENUM no effect no effect 0 set to high set to high 1 DOS5 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 5 6 ENUM no effect no effect 0 set to high set to high 1 DOS6 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 6 7 ENUM no effect no effect 0 set to high set to high 1 DOS7 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 7 8 ENUM no effect no effect 0 set to high set to high 1 DR GPIO x Drive current Set Register. 0x38 -1 read-write n 0x0 0x0 DR0 Drive curent set bit. 0 1 ENUM set to low large current. 0 set to high. low current. 1 DR1 Drive curent set bit. 1 2 ENUM set to low large current. 0 set to high. low current. 1 DR2 Drive curent set bit. 2 3 ENUM set to low large current. 0 set to high. low current. 1 DR3 Drive curent set bit. 3 4 ENUM set to low large current. 0 set to high. low current. 1 DR4 Drive curent set bit. 4 5 ENUM set to low large current. 0 set to high. low current. 1 DR5 Drive curent set bit. 5 6 ENUM set to low large current. 0 set to high. low current. 1 DR6 Drive curent set bit. 6 7 ENUM set to low large current. 0 set to high. low current. 1 DR7 Drive curent set bit. 7 8 ENUM set to low large current. 0 set to high. low current. 1 IANY GPIO x Interrupt Any Edge Register. 0x28 -1 read-write n 0x0 0x0 IANY0 Px.0 interrupt Trigger Any Edge. 0 1 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY1 Px.1 interrupt Trigger Any Edge. 1 2 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY2 Px.2 interrupt Trigger Any Edge. 2 3 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY3 Px.3 interrupt Trigger Any Edge. 3 4 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY4 Px.4 interrupt Trigger Any Edge. 4 5 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY5 Px.5 interrupt Trigger Any Edge. 5 6 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY6 Px.6 interrupt Trigger Any Edge. 6 7 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY7 Px.7 interrupt Trigger Any Edge. 7 8 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 ICLR GPIO x Interrupt Clear Register 0x1C -1 write-only n 0x0 0x0 MIS0 Writing a 1 to this bit clears PX.0 interrupt status 0 1 ENUM 0 0 0 1 1 1 MIS1 Writing a 1 to this bit clears PX.1 interrupt status 1 2 ENUM 0 0 0 1 1 1 MIS2 Writing a 1 to this bit clears PX.2 interrupt status 2 3 ENUM 0 0 0 1 1 1 MIS3 Writing a 1 to this bit clears PX.3 interrupt status 3 4 ENUM 0 0 0 1 1 1 MIS4 Writing a 1 to this bit clears PX.4 interrupt status 4 5 ENUM 0 0 0 1 1 1 MIS5 Writing a 1 to this bit clears PX.5 interrupt status 5 6 ENUM 0 0 0 1 1 1 MIS6 Writing a 1 to this bit clears PX.6 interrupt status 6 7 ENUM 0 0 0 1 1 1 MIS7 Writing a 1 to this bit clears PX.7 interrupt status 7 8 ENUM 0 0 0 1 1 1 IMSC GPIO x Interrupt Mask Set and Clear Register. 0x10 -1 read-write n 0x0 0x0 IMSC0 Px.0 interrupt mask set and clear register 0 1 ENUM 0 0 0 1 1 1 IMSC1 Px.1 interrupt mask set and clear register 1 2 ENUM 0 0 0 1 1 1 IMSC2 Px.2 interrupt mask set and clear register 2 3 ENUM 0 0 0 1 1 1 IMSC3 Px.3 interrupt mask set and clear register 3 4 ENUM 0 0 0 1 1 1 IMSC4 Px.4 interrupt mask set and clear register 4 5 ENUM 0 0 0 1 1 1 IMSC5 Px.5 interrupt mask set and clear register 5 6 ENUM 0 0 0 1 1 1 IMSC6 Px.6 interrupt mask set and clear register 6 7 ENUM 0 0 0 1 1 1 IMSC7 Px.7 interrupt mask set and clear register 7 8 ENUM 0 0 0 1 1 1 ITYPE GPIO x Interrupt Type Register 0x20 -1 read-write n 0x0 0x0 ITYPE0 Px.0 interrupt Type Register. 0 1 ENUM 0 0 0 1 1 1 ITYPE1 Px.1 interrupt Type Register. 1 2 ENUM 0 0 0 1 1 1 ITYPE2 Px.2 interrupt Type Register. 2 3 ENUM 0 0 0 1 1 1 ITYPE3 Px.3 interrupt Type Register. 3 4 ENUM 0 0 0 1 1 1 ITYPE4 Px.4 interrupt Type Register. 4 5 ENUM 0 0 0 1 1 1 ITYPE5 Px.5 interrupt Type Register. 5 6 ENUM 0 0 0 1 1 1 ITYPE6 Px.6 interrupt Type Register. 6 7 ENUM 0 0 0 1 1 1 ITYPE7 Px.7 interrupt Type Register. 7 8 ENUM 0 0 0 1 1 1 IVAL GPIO x Interrupt Value Register 0x24 -1 read-write n 0x0 0x0 IVAL0 Px.0 interrupt Trigger Value. 0 1 ENUM 0 0 0 1 1 1 IVAL1 Px.1 interrupt Trigger Value. 1 2 ENUM 0 0 0 1 1 1 IVAL2 Px.2 interrupt Trigger Value. 2 3 ENUM 0 0 0 1 1 1 IVAL3 Px.3 interrupt Trigger Value. 3 4 ENUM 0 0 0 1 1 1 IVAL4 Px.4 interrupt Trigger Value. 4 5 ENUM 0 0 0 1 1 1 IVAL5 Px.5 interrupt Trigger Value. 5 6 ENUM 0 0 0 1 1 1 IVAL6 Px.6 interrupt Trigger Value. 6 7 ENUM 0 0 0 1 1 1 IVAL7 Px.7 interrupt Trigger Value. 7 8 ENUM 0 0 0 1 1 1 MIS GPIO x Masked Interrupt Status Register. 0x18 -1 read-only n 0x0 0x0 MIS0 Px.0 Masked interrupt status 0 1 ENUM 0 0 0 1 1 1 MIS1 Px.1 Masked interrupt status 1 2 ENUM 0 0 0 1 1 1 MIS2 Px.2 Masked interrupt status 2 3 ENUM 0 0 0 1 1 1 MIS3 Px.3 Masked interrupt status 3 4 ENUM 0 0 0 1 1 1 MIS4 Px.4 Masked interrupt status 4 5 ENUM 0 0 0 1 1 1 MIS5 Px.5 Masked interrupt status 5 6 ENUM 0 0 0 1 1 1 MIS6 Px.6 Masked interrupt status 6 7 ENUM 0 0 0 1 1 1 MIS7 Px.7 Masked interrupt status 7 8 ENUM 0 0 0 1 1 1 PMS GPIO x Pin Mode Select Register 0x0 -1 read-write n 0x0 0x0 PMS0 Px.0 0 2 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS1 Px.1 2 4 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS2 Px.2 4 6 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS3 Px.3 6 8 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS4 Px.4 8 10 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS5 Px.5 10 12 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS6 Px.6 12 14 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS7 Px.7 14 16 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 RIS GPIO x Raw Interrupt Status Register. 0x14 -1 read-only n 0x0 0x0 RIS0 Px.0 raw interrupt status 0 1 ENUM 0 0 0 1 1 1 RIS1 Px.1 raw interrupt status 1 2 ENUM 0 0 0 1 1 1 RIS2 Px.2 raw interrupt status 2 3 ENUM 0 0 0 1 1 1 RIS3 Px.3 raw interrupt status 3 4 ENUM 0 0 0 1 1 1 RIS4 Px.4 raw interrupt status 4 5 ENUM 0 0 0 1 1 1 RIS5 Px.5 raw interrupt status 5 6 ENUM 0 0 0 1 1 1 RIS6 Px.6 raw interrupt status 6 7 ENUM 0 0 0 1 1 1 RIS7 Px.7 raw interrupt status 7 8 ENUM 0 0 0 1 1 1 SR GPIO x Drive rate Register. 0x3C -1 read-write n 0x0 0x0 SR0 Drive rate set bit. 0 1 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR1 Drive rate set bit. 1 2 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR2 Drive rate set bit. 2 3 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR3 Drive rate set bit. 3 4 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR4 Drive rate set bit. 4 5 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR5 Drive rate set bit. 5 6 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR6 Drive rate set bit. 6 7 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR7 Drive rate set bit. 7 8 ENUM clear to low high speed rate. 0 set to high low speed rate 1 GPIO4 General Purpose I/O GPIO 0x0 0x0 0xFFF registers n DI GPIO x Data Input Register. 0xC -1 read-only n 0x0 0x0 DIx0 Px.0 0 1 ENUM 0 0 0 1 1 1 DIx1 Px.1 1 2 ENUM 0 0 0 1 1 1 DIx2 Px.2 2 3 ENUM 0 0 0 1 1 1 DIx3 Px.3 3 4 ENUM 0 0 0 1 1 1 DIx4 Px.4 4 5 ENUM 0 0 0 1 1 1 DIx5 Px.5 5 6 ENUM 0 0 0 1 1 1 DIx6 Px6 6 7 ENUM 0 0 0 1 1 1 DIx7 Px.7 7 8 ENUM 0 0 0 1 1 1 DIDB GPIO x Data Input De-bounce Register. 0x2C -1 read-write n 0x0 0x0 DIDB0 Px.0 input De-bounce. 0 1 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB1 Px.1 input De-bounce. 1 2 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB2 Px.2 input De-bounce. 2 3 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB3 Px.3 input De-bounce. 3 4 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB4 Px.4 input De-bounce. 4 5 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB5 Px.5 input De-bounce. 5 6 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB6 Px.6 input De-bounce. 6 7 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DIDB7 Px.7 input De-bounce. 7 8 ENUM don't filter The input data is directly from the pin 0 filter There will be two stages DFF filter 1 DO GPIO x Data Output Write Mask Register. 0x8 -1 read-write n 0x0 0x0 DOx0 Px.0 0 1 ENUM 0 0 0 1 1 1 DOx1 Px.1 1 2 ENUM 0 0 0 1 1 1 DOx2 Px.2 2 3 ENUM 0 0 0 1 1 1 DOx3 Px.3 3 4 ENUM 0 0 0 1 1 1 DOx4 Px.4 4 5 ENUM 0 0 0 1 1 1 DOx5 Px.5 5 6 ENUM 0 0 0 1 1 1 DOx6 Px.6 6 7 ENUM 0 0 0 1 1 1 DOx7 Px.7 7 8 ENUM 0 0 0 1 1 1 DOCLR GPIO x Data Output Clear Register 0x34 -1 write-only n 0x0 0x0 DOC0 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 0 1 ENUM no effect no effect 0 clear to low clear to low 1 DOC1 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 1 2 ENUM no effect no effect 0 clear to low clear to low 1 DOC2 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 2 3 ENUM no effect no effect 0 clear to low clear to low 1 DOC3 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 3 4 ENUM no effect no effect 0 clear to low clear to low 1 DOC4 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 4 5 ENUM no effect no effect 0 clear to low clear to low 1 DOC5 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 5 6 ENUM no effect no effect 0 clear to low clear to low 1 DOC6 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 6 7 ENUM no effect no effect 0 clear to low clear to low 1 DOC7 Data Output clear Register.DO can be cleared by writing 1 to the DOC in the GPIOxDOCLR register. Writing a zero to this bit has no effect. 7 8 ENUM no effect no effect 0 clear to low clear to low 1 DOM GPIO x Data Output Write Mask Register. 0x4 -1 read-write n 0x0 0x0 DOMx0 Data Output Write Mask Register. 0 1 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx1 Data Output Write Mask Register. 1 2 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx2 Data Output Write Mask Register. 2 3 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx3 Data Output Write Mask Register. 3 4 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx4 Data Output Write Mask Register. 4 5 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx5 Data Output Write Mask Register. 5 6 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx6 Data Output Write Mask Register. 6 7 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOMx7 Data Output Write Mask Register. 7 8 ENUM GPIOxDO is not masked. GPIOxDO is not masked. 0 GPIOxDO is masked. No changed by writing GPIOxDO. GPIOxDO is masked. No changed by writing GPIOxDO. 1 DOSET GPIO x Data Output Set Register. 0x30 -1 write-only n 0x0 0x0 DOS0 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 0 1 ENUM no effect no effect 0 set to high set to high 1 DOS1 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 1 2 ENUM no effect no effect 0 set to high set to high 1 DOS2 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 2 3 ENUM no effect no effect 0 set to high set to high 1 DOS3 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 3 4 ENUM no effect no effect 0 set to high set to high 1 DOS4 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 4 5 ENUM no effect no effect 0 set to high set to high 1 DOS5 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 5 6 ENUM no effect no effect 0 set to high set to high 1 DOS6 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 6 7 ENUM no effect no effect 0 set to high set to high 1 DOS7 Data Output Set Register.DO can be set by writing 1 to the DO in the GPIOxDOSET register.Writing a zero to this bit has no effect. 7 8 ENUM no effect no effect 0 set to high set to high 1 DR GPIO x Drive current Set Register. 0x38 -1 read-write n 0x0 0x0 DR0 Drive curent set bit. 0 1 ENUM set to low large current. 0 set to high. low current. 1 DR1 Drive curent set bit. 1 2 ENUM set to low large current. 0 set to high. low current. 1 DR2 Drive curent set bit. 2 3 ENUM set to low large current. 0 set to high. low current. 1 DR3 Drive curent set bit. 3 4 ENUM set to low large current. 0 set to high. low current. 1 DR4 Drive curent set bit. 4 5 ENUM set to low large current. 0 set to high. low current. 1 DR5 Drive curent set bit. 5 6 ENUM set to low large current. 0 set to high. low current. 1 DR6 Drive curent set bit. 6 7 ENUM set to low large current. 0 set to high. low current. 1 DR7 Drive curent set bit. 7 8 ENUM set to low large current. 0 set to high. low current. 1 IANY GPIO x Interrupt Any Edge Register. 0x28 -1 read-write n 0x0 0x0 IANY0 Px.0 interrupt Trigger Any Edge. 0 1 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY1 Px.1 interrupt Trigger Any Edge. 1 2 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY2 Px.2 interrupt Trigger Any Edge. 2 3 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY3 Px.3 interrupt Trigger Any Edge. 3 4 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY4 Px.4 interrupt Trigger Any Edge. 4 5 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY5 Px.5 interrupt Trigger Any Edge. 5 6 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY6 Px.6 interrupt Trigger Any Edge. 6 7 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 IANY7 Px.7 interrupt Trigger Any Edge. 7 8 ENUM depended on IANY Falling or Rising edge depended on GPIOxIANY0 0 Any edge Any edge can trigger 1 ICLR GPIO x Interrupt Clear Register 0x1C -1 write-only n 0x0 0x0 MIS0 Writing a 1 to this bit clears PX.0 interrupt status 0 1 ENUM 0 0 0 1 1 1 MIS1 Writing a 1 to this bit clears PX.1 interrupt status 1 2 ENUM 0 0 0 1 1 1 MIS2 Writing a 1 to this bit clears PX.2 interrupt status 2 3 ENUM 0 0 0 1 1 1 MIS3 Writing a 1 to this bit clears PX.3 interrupt status 3 4 ENUM 0 0 0 1 1 1 MIS4 Writing a 1 to this bit clears PX.4 interrupt status 4 5 ENUM 0 0 0 1 1 1 MIS5 Writing a 1 to this bit clears PX.5 interrupt status 5 6 ENUM 0 0 0 1 1 1 MIS6 Writing a 1 to this bit clears PX.6 interrupt status 6 7 ENUM 0 0 0 1 1 1 MIS7 Writing a 1 to this bit clears PX.7 interrupt status 7 8 ENUM 0 0 0 1 1 1 IMSC GPIO x Interrupt Mask Set and Clear Register. 0x10 -1 read-write n 0x0 0x0 IMSC0 Px.0 interrupt mask set and clear register 0 1 ENUM 0 0 0 1 1 1 IMSC1 Px.1 interrupt mask set and clear register 1 2 ENUM 0 0 0 1 1 1 IMSC2 Px.2 interrupt mask set and clear register 2 3 ENUM 0 0 0 1 1 1 IMSC3 Px.3 interrupt mask set and clear register 3 4 ENUM 0 0 0 1 1 1 IMSC4 Px.4 interrupt mask set and clear register 4 5 ENUM 0 0 0 1 1 1 IMSC5 Px.5 interrupt mask set and clear register 5 6 ENUM 0 0 0 1 1 1 IMSC6 Px.6 interrupt mask set and clear register 6 7 ENUM 0 0 0 1 1 1 IMSC7 Px.7 interrupt mask set and clear register 7 8 ENUM 0 0 0 1 1 1 ITYPE GPIO x Interrupt Type Register 0x20 -1 read-write n 0x0 0x0 ITYPE0 Px.0 interrupt Type Register. 0 1 ENUM 0 0 0 1 1 1 ITYPE1 Px.1 interrupt Type Register. 1 2 ENUM 0 0 0 1 1 1 ITYPE2 Px.2 interrupt Type Register. 2 3 ENUM 0 0 0 1 1 1 ITYPE3 Px.3 interrupt Type Register. 3 4 ENUM 0 0 0 1 1 1 ITYPE4 Px.4 interrupt Type Register. 4 5 ENUM 0 0 0 1 1 1 ITYPE5 Px.5 interrupt Type Register. 5 6 ENUM 0 0 0 1 1 1 ITYPE6 Px.6 interrupt Type Register. 6 7 ENUM 0 0 0 1 1 1 ITYPE7 Px.7 interrupt Type Register. 7 8 ENUM 0 0 0 1 1 1 IVAL GPIO x Interrupt Value Register 0x24 -1 read-write n 0x0 0x0 IVAL0 Px.0 interrupt Trigger Value. 0 1 ENUM 0 0 0 1 1 1 IVAL1 Px.1 interrupt Trigger Value. 1 2 ENUM 0 0 0 1 1 1 IVAL2 Px.2 interrupt Trigger Value. 2 3 ENUM 0 0 0 1 1 1 IVAL3 Px.3 interrupt Trigger Value. 3 4 ENUM 0 0 0 1 1 1 IVAL4 Px.4 interrupt Trigger Value. 4 5 ENUM 0 0 0 1 1 1 IVAL5 Px.5 interrupt Trigger Value. 5 6 ENUM 0 0 0 1 1 1 IVAL6 Px.6 interrupt Trigger Value. 6 7 ENUM 0 0 0 1 1 1 IVAL7 Px.7 interrupt Trigger Value. 7 8 ENUM 0 0 0 1 1 1 MIS GPIO x Masked Interrupt Status Register. 0x18 -1 read-only n 0x0 0x0 MIS0 Px.0 Masked interrupt status 0 1 ENUM 0 0 0 1 1 1 MIS1 Px.1 Masked interrupt status 1 2 ENUM 0 0 0 1 1 1 MIS2 Px.2 Masked interrupt status 2 3 ENUM 0 0 0 1 1 1 MIS3 Px.3 Masked interrupt status 3 4 ENUM 0 0 0 1 1 1 MIS4 Px.4 Masked interrupt status 4 5 ENUM 0 0 0 1 1 1 MIS5 Px.5 Masked interrupt status 5 6 ENUM 0 0 0 1 1 1 MIS6 Px.6 Masked interrupt status 6 7 ENUM 0 0 0 1 1 1 MIS7 Px.7 Masked interrupt status 7 8 ENUM 0 0 0 1 1 1 PMS GPIO x Pin Mode Select Register 0x0 -1 read-write n 0x0 0x0 PMS0 Px.0 0 2 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS1 Px.1 2 4 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS2 Px.2 4 6 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS3 Px.3 6 8 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS4 Px.4 8 10 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS5 Px.5 10 12 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS6 Px.6 12 14 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 PMS7 Px.7 14 16 ENUM Pull Up pull up in 0 Push Pop Out push pop out 1 Open Drain push pop out 2 IN push pop out 3 RIS GPIO x Raw Interrupt Status Register. 0x14 -1 read-only n 0x0 0x0 RIS0 Px.0 raw interrupt status 0 1 ENUM 0 0 0 1 1 1 RIS1 Px.1 raw interrupt status 1 2 ENUM 0 0 0 1 1 1 RIS2 Px.2 raw interrupt status 2 3 ENUM 0 0 0 1 1 1 RIS3 Px.3 raw interrupt status 3 4 ENUM 0 0 0 1 1 1 RIS4 Px.4 raw interrupt status 4 5 ENUM 0 0 0 1 1 1 RIS5 Px.5 raw interrupt status 5 6 ENUM 0 0 0 1 1 1 RIS6 Px.6 raw interrupt status 6 7 ENUM 0 0 0 1 1 1 RIS7 Px.7 raw interrupt status 7 8 ENUM 0 0 0 1 1 1 SR GPIO x Drive rate Register. 0x3C -1 read-write n 0x0 0x0 SR0 Drive rate set bit. 0 1 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR1 Drive rate set bit. 1 2 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR2 Drive rate set bit. 2 3 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR3 Drive rate set bit. 3 4 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR4 Drive rate set bit. 4 5 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR5 Drive rate set bit. 5 6 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR6 Drive rate set bit. 6 7 ENUM clear to low high speed rate. 0 set to high low speed rate 1 SR7 Drive rate set bit. 7 8 ENUM clear to low high speed rate. 0 set to high low speed rate 1 IIC0 IIC0 Control Register. IIC 0x0 0x0 0xFFF registers n I2C0_IRQHandler 24 ADM0 I2C Slave Address Mask Register 0. 0x18 -1 read-write n 0x0 0x0 MASK Mask bits 1 8 ENUM low output The received corresponding address bit doesn't care. 0 high output The received corresponding address bit should be exact the same as address register. The mask register has no effect on comparison to the General Call address. When an address-match interrupt occurs, the processor will have to read the data register (DAT) to determine what the received address was that actually caused the match. 1 ADM1 I2C Slave Address Mask Register 1. 0x2C -1 read-write n 0x0 0x0 MASK Mask bits 1 8 ENUM low output The received corresponding address bit doesn't care. 0 high output The received corresponding address bit should be exact the same as address register. The mask register has no effect on comparison to the General Call address. When an address-match interrupt occurs, the processor will have to read the data register (DAT) to determine what the received address was that actually caused the match. 1 ADM2 I2C Slave Address MaskRegister 2. 0x34 -1 read-write n 0x0 0x0 MASK Mask bits 1 8 ENUM low output The received corresponding address bit doesn't care. 0 high output The received corresponding address bit should be exact the same as address register. The mask register has no effect on comparison to the General Call address.When an address-match interrupt occurs, the processor will have to read the data register (DAT) to determine what the received address was that actually caused the match. 1 ADM3 I2C Slave Address Mask Register 3. 0x3C -1 read-write n 0x0 0x0 MASK Mask bits 1 8 ENUM low output The received corresponding address bit doesn't care. 0 high output The received corresponding address bit should be exact the same as address register.The mask register has no effect on comparison to the General Call address. When an address-match interrupt occurs, the processor will have to read the data register (DAT) to determine what the received address was that actually caused the match. 1 ADR0 I2C Slave Address Register 0. 0x14 -1 read-write n 0x0 0x0 Address The I2C device address for slave mode. 1 8 GC General Call enable bit. 0 1 ENUM Disable Disable General call 0 Enable Enable General call 1 ADR1 I2C Slave Address Register 1. 0x28 -1 read-write n 0x0 0x0 Address The I2C device address for slave mode. 1 8 GC General call enable bit 0 1 ENUM disable disable general call 0 enable enable general call 1 ADR2 I2C Slave Address Register 2. 0x30 -1 read-write n 0x0 0x0 Address The I2C device address for slave mode. 1 8 GC General call enable bit 0 1 ENUM disable disable general call 0 enable enable general call 1 ADR3 I2C Slave Address Register 3. 0x38 -1 read-write n 0x0 0x0 Address The I2C device address for slave mode. 1 8 GC General call enable bit 0 1 ENUM disable disable general call 0 enable enable general call 1 CLK I2C Clock Control Register 0x10 -1 read-write n 0x0 0x0 M FSCL = PCLK / (2Mx(N+1)x10) 4 7 N FSAMP = PCLK / 2M 0 4 CONCLR I2C Control Clear Register 0x4 -1 write-only n 0x0 0x0 AAC Assert acknowledge clear. Writing a 1 to this bit clears the AAC bit in the I2C0CONSET register. Writing 0 has no effect. 2 3 I2CENC I2C interface disable. Writing a 1 to this bit clears the I2CENC bit in the I2C0CONSET register. Writing 0 has no effect. 6 7 I2CIEC I2C interrupt disable. Writing a 1 to this bit clears the I2CIEC bit in the I2C0CONSET register. Writing 0 has no effect. 7 8 SIC I2C interrupt clear. Writing a 1 to this bit clears the SIC bit in the I2C0CONSET register. Writing 0 has no effect. 3 4 STAC START flag clear. Writing a 1 to this bit clears the STA bit in the I2C0CONSET register. Writing 0 has no effect. 5 6 CONSET I2C Control Set Register 0x0 -1 read-write n 0x0 0x0 AA Assert acknowledge flag. (AA can be cleared by writing 1 to the AAC bit in the I2C0CONCLR register.) (The I2C will not respond as a slave unless AA is set.) 0: A not acknowledge (HIGH level to SDA) will be returned during the acknowledge clock pulse on the SCL line, when a data byte has been received while the I2C is in the master or slave mode. 1: An acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line on the following situations: 1. The add ress in the Slave Address Register has been received. 2. The General Call address has been received while the General Call bit (GC) in the ADR register is set. 3. A data byte has been received while the I2C is in the master or slave mode. 2 3 ADRF I2C Slave Address FLAG (7-bitaddressing) (Read Only) 0 1 ENUM not match I2C slave address is not match. 0 match I2C slave address is match with 7-bit address. This bit is clear when new data is transmit/receive. 1 GCF I2C General Call FLAG (Read Only) 8 9 ENUM not match I2C General call address is not match. 0 match I2C General call address is match.This bit is clear when new data is transmit/receive. 1 I2CEN I2C interface enable. (I2CEN can be cleared by writing 1 to the I2CENC bit in the I2C0CONCLR register.) (The Multi-Function pin function of SDA and SCL must be set to I2C function.) 6 7 ENUM Disable Disable I2C interface. 0 Enable Enable I2C interface. 1 I2CIE Interrupt Enable 7 8 ENUM Disable Disable I2C interrupt 0 Enable Enable I2C interrupt 1 SI I2C interrupt flag. (SI can be cleared by writing 1 to the SIC bit in the I2C0CONCLR register.) This bit is set when the I2C state changes, and if bit I2CIE is set, the I2C interrupt is requested. However, entering state F8 does not set SI since there is nothing for an interrupt service routine to do in that case. The SI is clear by software. 3 4 ENUM 0 write 0 0 1 write 1 1 STA START flag. (STA can be cleared by writing 1 to the STAC bit in the I2C0CONCLR register.) When STA is set to one, the I2C enters master mode and will send a START condition on the bus when the bus is free. If the STA bit is set to one when the I2C is already in master mode, then a repeated START condition will be sent. If the STA bit is set to one while the I2C is being accessed in slave mode, the I2C will complete the data transfer in slave mode then enter master mode when the bus has been released.The STA bit is cleared automatically after a START condition has been sent: writing a zero to this bit has no effect. 5 6 ENUM 0 write 0 0 1 write 1 1 STO STO flag 4 5 ENUM Disable Disable PWM0 0 Enable Enable PWM0 1 XADRF I2C Extended Slave Address FLAG (10-bit addressing) (Read Only) 1 2 ENUM not match I2C slave address is not match. 0 match I2C slave address is match with 10-bit address. This bit is clear when new data is transmit/receive. 1 DAT I2C Data Register 0xC -1 read-write n 0x0 0x0 Data This register holds data values that have been received or are to be transmitted. 0 8 RST I2C Software Reset Register 0x24 -1 write-only n 0x0 0x0 RST I2C software reset by writes 0x07. 0 8 STAT I2C Status Register 0x8 -1 read-only n 0x0 0x0 Status Interrupt status code 0 8 ENUM Bus error (Master mode only) Bus error (Master mode only) 0x00 Address + Write bit transmitted, Not ACK received Address + Write bit transmitted, Not ACK received 0x020 START condition transmitted START condition transmitted 0x08 Repeated START condition transmitted Repeated START condition transmitted 0x10 Address + Write bit transmitted, ACK received Address + Write bit transmitted, ACK received 0x18 Data byte transmitted in master mode, ACK received Data byte transmitted in master mode, ACK received 0x28 Data byte transmitted in master mode, Not ACK received Data byte transmitted in master mode, Not ACK received 0x30 Arbitration lost in address or data byte Arbitration lost in address or data byte 0x38 Address + Read bit transmitted, ACK received Address + Read bit transmitted, ACK received 0x40 Address + Read bit transmitted, Not ACK received Address + Read bit transmitted, Not ACK received 0x48 Data byte received in master mode, ACK transmitted Data byte received in master mode, ACK transmitted 0x50 Data byte received in master mode, Not ACK transmitted Data byte received in master mode, Not ACK transmitted 0x58 Slave address + Write bit received, ACK transmitted Slave address + Write bit received, ACK transmitted 0x60 General Call Address received, ACK transmitted General Call Address received, ACK transmitted 0x70 Arbitration lost in address as master Arbitration lost in address as master, General Call Address received, ACK transmitted 0x78 Arbitration lost in address as master Arbitration lost in address as master, General Call Address received, ACK transmitted 0x78 Arbitration lost in address as master Arbitration lost in address as master, General Call Address received, ACK transmitted 0x78 Data byte received after slave address received, ACK transmitted Data byte received after slave address received, ACK transmitted 0x80 Data byte received after slave address received Data byte received after slave address received, Not ACK transmitted 0x88 Data byte received after General Call Address received Data byte received after General Call Address received, ACK transmitted 0x90 Data received after General Call received, Not ACK Data byte received after General Call Address received, Not ACK transmitted 0x98 STOP or repeated START condition received in slave mode STOP or repeated START condition received in slave mode 0xA0 Slave address + Read bit received, ACK transmitted Slave address + Read bit received, ACK transmitted 0xA8 Data byte transmitted in slave mode, ACK received Data byte transmitted in slave mode, ACK received 0xB8 Data byte transmitted in slave mode, Not ACK received Data byte transmitted in slave mode, Not ACK received 0xC0 Last byte transmitted in slave mode, ACK received Last byte transmitted in slave mode, ACK received 0xC8 Last byte transmitted in slave mode, Not ACK received Last byte transmitted in slave mode, Not ACK received 0xD0 Unused Unused 0xD8 Unused Unused 0xD8 Second Address byte transmitted, ACK received Second Address byte transmitted, ACK received 0xE0 Second Address byte transmitted, Not ACK received Second Address byte transmitted, Not ACK received 0xE8 No relevant status information, IFLG=0 No relevant status information, IFLG=0 0xF8 XADM0 I2C Extended Slave Address Mask Register 0. 0x20 -1 read-write n 0x0 0x0 MASK Mask bits 1 9 ENUM don't care The received corresponding address bit is don't care. 0 care The received corresponding address bit should be exact the same as address register. The mask register has no effect on comparison to the General Call address.When an address-match interrupt occurs, the processor will have to read the data register (DAT) to determine what the received address was that actually caused the match. 1 XADR0 I2C Extended Slave Address Register 0. 0x1C -1 read-write n 0x0 0x0 Address The I2C device address for slave mode. 1 11 GC General Call enable bit 0 1 ENUM disable disable general call 0 enable enable general call 1 PWM PWM Control Register. PWM 0x0 0x0 0xFFF registers n CP_IRQHandler 6 PWMCON0 PWM group 0 contol register 0x0 -1 read-write n 0x0 0x0 CHS Capture channel select 2 3 ENUM CH A channel A 0 CH B channel B 1 CMS Capture mode select 0 2 ENUM rising edge capture on rising edge 0 falling edge capture on falling edge 1 form rising to falling edge count from rising edge to falling edge 2 form falling to rising count from falling edge to rising edge 3 PWMEN PWM enable 6 7 ENUM Disable Disable PWM0 0 Enable Enable PWM0 1 PWMPS PWM prescale select 4 6 ENUM PCLK 0x0: PCLk 0x0 PCLK/4 0x1: PCLk/4 0x1 PCLK/16 0x1: PCLk/4 0x2 PCLK/64 0x1: PCLk/4 0x3 PWMS PWM Select 3 4 ENUM capture 0: Capture Mode 0 pwm 1: PWM mode 1 PWMCON1 PWM group 0 contol register 0x10 -1 read-write n 0x0 0x0 CHS Capture channel select 2 3 ENUM CH A channel A 0 CH B channel B 1 CMS Capture mode select 0 2 ENUM rising edge capture on rising edge 0 falling edge capture on falling edge 1 form rising to falling edge count from rising edge to falling edge 2 form falling to rising count from falling edge to rising edge 3 PWMEN PWM enable 6 7 ENUM Disable Disable PWM0 0 Enable Enable PWM0 1 PWMPS PWM prescale select 4 6 ENUM PCLK 0x0: PCLk 0x0 PCLK/4 0x1: PCLk/4 0x1 PCLK/16 0x1: PCLk/4 0x2 PCLK/64 0x1: PCLk/4 0x3 PWMS PWM Select 3 4 ENUM capture 0: Capture Mode 0 pwm 1: PWM mode 1 PWMCON2 PWM group 0 contol register 0x20 -1 read-write n 0x0 0x0 CHS Capture channel select 2 3 ENUM CH A channel A 0 CH B channel B 1 CMS Capture mode select 0 2 ENUM rising edge capture on rising edge 0 falling edge capture on falling edge 1 form rising to falling edge count from rising edge to falling edge 2 form falling to rising count from falling edge to rising edge 3 PWMEN PWM enable 6 7 ENUM Disable Disable PWM0 0 Enable Enable PWM0 1 PWMPS PWM prescale select 4 6 ENUM PCLK 0x0: PCLk 0x0 PCLK/4 0x1: PCLk/4 0x1 PCLK/16 0x1: PCLk/4 0x2 PCLK/64 0x1: PCLk/4 0x3 PWMS PWM Select 3 4 ENUM capture 0: Capture Mode 0 pwm 1: PWM mode 1 PWMCON3 PWM group 0 contol register 0x30 -1 read-write n 0x0 0x0 CHS Capture channel select 2 3 ENUM CH A channel A 0 CH B channel B 1 CMS Capture mode select 0 2 ENUM rising edge capture on rising edge 0 falling edge capture on falling edge 1 form rising to falling edge count from rising edge to falling edge 2 form falling to rising count from falling edge to rising edge 3 PWMEN PWM enable 6 7 ENUM Disable Disable PWM0 0 Enable Enable PWM0 1 PWMPS PWM prescale select 4 6 ENUM PCLK 0x0: PCLk 0x0 PCLK/4 0x1: PCLk/4 0x1 PCLK/16 0x1: PCLk/4 0x2 PCLK/64 0x1: PCLk/4 0x3 PWMS PWM Select 3 4 ENUM capture 0: Capture Mode 0 pwm 1: PWM mode 1 PWMD0A PWM group 0 channel A data register 0x8 -1 read-write n 0x0 0x0 PWMDATA PWM Output Polarity Select. 0 16 PWMOP PWM Data 16 17 ENUM low output When PWMOP ='0', PWM leading low output. 0 high output When PWMOP ='1',PWM leading high output 1 PWMD0B PWM group 0 channel B data register 0xC -1 read-write n 0x0 0x0 PWMDATB PWM Output Polarity Select. 0 16 PWMOP PWM Data 16 17 ENUM low output When PWMOP ='0',PWM leading low output. 0 high output When PWMOP ='1', PWM leading high output 1 PWMD1A PWM group 0 channel A data register 0x18 -1 read-write n 0x0 0x0 PWMDATA PWM Output Polarity Select. 0 16 PWMOP PWM Data 16 17 ENUM low output When PWMOP ='0', PWM leading low output. 0 high output When PWMOP ='1', PWM leading high output 1 PWMD1B PWM group 0 channel B data register 0x1C -1 read-write n 0x0 0x0 PWMDATB PWM Output Polarity Select. 0 16 PWMOP PWM Data 16 17 ENUM low output When PWMOP ='0', PWM leading low output. 0 high output When PWMOP ='1', PWM leading high output 1 PWMD2A PWM group 0 channel A data register 0x28 -1 read-write n 0x0 0x0 PWMDATA PWM Output Polarity Select. 0 16 PWMOP PWM Data 16 17 ENUM low output When PWMOP ='0', PWM leading low output. 0 high output When PWMOP ='1', PWM leading high output 1 PWMD2B PWM group 0 channel B data register 0x2C -1 read-write n 0x0 0x0 PWMDATB PWM Output Polarity Select. 0 16 PWMOP PWM Data 16 17 ENUM low output When PWMOP ='0', PWM leading low output. 0 high output When PWMOP ='1', PWM leading high output 1 PWMD3A PWM group 0 channel A data register 0x38 -1 read-write n 0x0 0x0 PWMDATA PWM Output Polarity Select. 0 16 PWMOP PWM Data 16 17 ENUM low output When PWMOP ='0', PWM leading low output. 0 high output When PWMOP ='1', PWM leading high output 1 PWMD3B PWM group 0 channel B data register 0x3C -1 read-write n 0x0 0x0 PWMDATB PWM Output Polarity Select. 0 16 PWMOP PWM Data 16 17 ENUM low output When PWMOP ='0', PWM leading low output. 0 high output When PWMOP ='1', PWM leading high output 1 PWMICLR PWM interrupt clear Register 0x4C -1 write-only n 0x0 0x0 PWMICLR0 Writing '1' to this bits clears PWM Group 0 Compare/Capture interrupt Status 0 1 ENUM Disable PWM Group 0 Overflow interrupt Mask disable 0 Enable PWM Group 0 Overflow interrupt Mask enable 1 PWMICLR1 Writing '1' to this bits clears PWM Group 1 Compare/Capture interrupt Status 1 2 ENUM Disable PWM Group 1 Overflow interrupt Mask disable 0 high output PWM Group 1 Overflow interrupt Mask enable 1 PWMICLR2 Writing '1' to this bits clears PWM Group 2 Compare/Capture interrupt Status 2 3 ENUM Disable PWM Group 2 Overflow interrupt Mask disable 0 high output PWM Group 2 Overflow interrupt Mask enable 1 PWMICLR3 Writing '1' to this bits clears PWM Group 3 Compare/Capture interrupt Status 3 4 ENUM Disable PWM Group 3 Overflow interrupt Mask disable 0 high output PWM Group 3 Overflow interrupt Mask enable 1 PWMICLR4 Writing '1' to this bits clears PWM Group 4 Compare/Capture interrupt Status 4 5 ENUM Disable PWM Group 4 Overflow interrupt Mask disable 0 high output PWM Group 4 Overflow interrupt Mask enable 1 PWMICLR5 Writing '1' to this bits clears PWM Group 5 Compare/Capture interrupt Status 5 6 ENUM Disable PWM Group 5 Overflow interrupt Mask disable 0 high output PWM Group 5 Overflow interrupt Mask enable 1 PWMICLR6 Writing '1' to this bits clears PWM Group 6 Compare/Capture interrupt Status 6 7 ENUM Disable PWM Group 6 Overflow interrupt Mask disable 0 high output PWM Group 6 Overflow interrupt Mask enable 1 PWMICLR7 Writing '1' to this bits clears PWM Group 7 Compare/Capture interrupt Status 7 8 ENUM Disable PWM Group 7 Overflow interrupt Mask disable 0 high output PWM Group 7 Overflow interrupt Mask enable 1 PWMIMSC PWM Interrupt Mask Set and Clear Register 0x40 -1 read-write n 0x0 0x0 PWMIMSC0 PWM Group 0 Overflow interrupt Mask Set and Clear 0 1 ENUM Disable PWM Group 0 Overflow interrupt Mask disable 0 Enable PWM Group 0 Overflow interrupt Mask enable 1 PWMIMSC1 PWM Group 1 Overflow interrupt Mask Set and Clear 1 2 ENUM Disable PWM Group 1 Overflow interrupt Mask disable 0 high output PWM Group 1 Overflow interrupt Mask enable 1 PWMIMSC2 PWM Group 2 Overflow interrupt Mask Set and Clear 2 3 ENUM Disable PWM Group 2 Overflow interrupt Mask disable 0 high output PWM Group 2 Overflow interrupt Mask enable 1 PWMIMSC3 PWM Group 3 Overflow interrupt Mask Set and Clear 3 4 ENUM Disable PWM Group 3 Overflow interrupt Mask disable 0 high output PWM Group 3 Overflow interrupt Mask enable 1 PWMIMSC4 PWM Group 4 Overflow interrupt Mask Set and Clear 4 5 ENUM Disable PWM Group 4 Overflow interrupt Mask disable 0 high output PWM Group 4 Overflow interrupt Mask enable 1 PWMIMSC5 PWM Group 5 Overflow interrupt Mask Set and Clear 5 6 ENUM Disable PWM Group 5 Overflow interrupt Mask disable 0 high output PWM Group 5 Overflow interrupt Mask enable 1 PWMIMSC6 PWM Group 6 Overflow interrupt Mask Set and Clear 6 7 ENUM Disable PWM Group 6 Overflow interrupt Mask disable 0 high output PWM Group 6 Overflow interrupt Mask enable 1 PWMIMSC7 PWM Group 7 Overflow interrupt Mask Set and Clear 7 8 ENUM Disable PWM Group 7 Overflow interrupt Mask disable 0 high output PWM Group 7 Overflow interrupt Mask enable 1 PWML0AD0 PWM group 0 load register 0x4 -1 read-write n 0x0 0x0 PWMLOAD PWM load value 0 16 RELOAD PWM reload enable field 16 17 ENUM don't reload When RELOAD ='0',Reload Value=0xFFFF 0 reload When RELOAD='1',Reload Value=PMLOAD 1 PWML1AD0 PWM group 0 load register 0x14 -1 read-write n 0x0 0x0 PWMLOAD PWM load value 0 16 RELOAD PWM reload enable field 16 17 ENUM don't reload When RELOAD ='0', Reload Value=0xFFFF 0 reload When RELOAD='1', Reload Value=PMLOAD 1 PWML2AD0 PWM group 0 load register 0x24 -1 read-write n 0x0 0x0 PWMLOAD PWM load value 0 16 RELOAD PWM reload enable field 16 17 ENUM don't reload When RELOAD ='0', Reload Value=0xFFFF 0 reload When RELOAD='1', Reload Value=PMLOAD 1 PWML3AD0 PWM group 0 load register 0x34 -1 read-write n 0x0 0x0 PWMLOAD PWM load value 0 16 RELOAD PWM reload enable field 16 17 ENUM don't reload When RELOAD ='0', Reload Value=0xFFFF 0 reload When RELOAD='1', Reload Value=PMLOAD 1 PWMMIS PWM Masked interrupt Status 0x48 -1 read-only n 0x0 0x0 PWMMIS0 PWM Group 0 MaskedCompare/Capture interrupt Status 0 1 PWMMIS1 PWM Group 1 MaskedCompare/Capture interrupt Status 1 2 PWMMIS2 PWM Group 2 MaskedCompare/Capture interrupt Status 2 3 PWMMIS3 PWM Group 3 MaskedCompare/Capture interrupt Status 3 4 PWMMIS4 PWM Group 4 MaskedCompare/Capture interrupt Status 4 5 PWMMIS5 PWM Group 5 MaskedCompare/Capture interrupt Status 5 6 PWMMIS6 PWM Group 6 MaskedCompare/Capture interrupt Status 6 7 PWMMIS7 PWM Group 7 MaskedCompare/Capture interrupt Status 7 8 PWMRIS PWM Raw interrupt Status Register 0x44 -1 read-only n 0x0 0x0 PWMRIS0 PWM Group 0 Raw Compare/Capture interrupt Status 0 1 PWMRIS1 PWM Group 1 Raw Compare/Capture interrupt Status 1 2 PWMRIS2 PWM Group 2 Raw Compare/Capture interrupt Status 2 3 PWMRIS3 PWM Group 3 Raw Compare/Capture interrupt Status 3 4 PWMRIS4 PWM Group 4 Raw Compare/Capture interrupt Status 4 5 PWMRIS5 PWM Group 5 Raw Compare/Capture interrupt Status 5 6 PWMRIS6 PWM Group 6 Raw Compare/Capture interrupt Status 6 7 PWMRIS7 PWM Group 7 Raw Compare/Capture interrupt Status 7 8 PWMRUN PWM run Register 0x50 -1 read-write n 0x0 0x0 RUN0 PWMRUN0 0 1 ENUM 0 Stop 0 1 Run 1 RUN1 PWMRUN1 1 2 ENUM 0 Stop 0 1 Run 1 RUN2 PWMRUN2 2 3 ENUM 0 Stop 0 1 Run 1 RUN3 PWMRUN3 3 4 ENUM 0 Stop 0 1 Run 1 SSP0 SSP Control Register. SSP 0x0 0x0 0xFFF registers n SSP0_IRQHandler 26 SSP0CLK SSP Clock Control Register. 0xC -1 read-write n 0x0 0x0 M 8 16 N FSSPCLK = PCLK / ((M+1)xN) N is an even value from 2 to 254 0 8 SSP0CON SSP Control Register. 0x0 -1 read-write n 0x0 0x0 CPH Clock Out Phase 7 8 ENUM first SSP controller captures serial data on the first transition clock edge of the frame. 0x0 second SSP controller captures serial data on the second transition clock edge of the frame. 0x1 CPO SSPCLK Clock Out Polarity 6 7 ENUM low SSP controller maintains the bus clock low between frames. 0 high SSP controller maintains the bus clock high between frames. 1 DSS This field controls the number of bits transferred in each frame. 0 4 ENUM 11 Bit 11-bit transfer 10 12 Bit 12-bit transfer 11 13 Bit 13-bit transfer 12 14 Bit 14-bit transfer 13 15 Bit 15-bit transfer 14 16 Bit 16-bit transfer 15 4 Bit 4-bit transfer 3 5 Bit 5-bit transfer 4 6 Bit 6-bit transfer 5 7 Bit 7-bit transfer 6 8 Bit 8-bit transfer 7 9 Bit 9-bit transfer 8 10 Bit 10-bit transfer 9 FRF Frame Format. 4 6 ENUM SPI SPI - compatible frame format 0 TISS TISS - compatible frame format 1 Microwire Microwire - compatible frame format 2 LBM Loop Back Mode 11 12 ENUM Disable Normal operation. 0 Enable Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). 1 MS Master/Slave Mode 9 10 ENUM Disable The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. 0 Enable The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. 1 SOD Slave Output Disable 8 9 ENUM Disable SSP can drive the MISO output in slave mode. 0 Enable SSP must not drive the MISO output in slave mode. 1 SSPEN SSP Enable 10 11 ENUM Disable The SSP controller is disabled. 0 Enable The SSP controller will interact with other devices on the serial bus. 1 SSP0CSCR Software Control SSP CS. 0x28 -1 read-write n 0x0 0x0 SELCS Select SSP SS0~3 active mode 0 2 ENUM SELCS SS2 line is active 2 SELCS SS2 line is active 2 SELCS SS2 line is active 2 SELCS SS2 line is active 2 SPH As SSP slave. 4 5 ENUM 0 Chip select signal cannot pull high after a frame transfer 0 1 Chip select signal must pull high after a frame transfer 1 SWCS Software Chip-Select. The chip-select line selected by SELCS is controlled 3 4 ENUM 0 Chip-Select is low 0 0 Chip-Select is low 0 SWSEL Software select mode 2 3 ENUM 0 Chip-Select is automatically controlled by the SPI module 0 1 Chip-Select is software controlled by SWCS bit 1 SSP0DAT SSP Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. 0x8 -1 read-write n 0x0 0x0 DATA 0 16 SSP0ICLR SSP Interrupt Clear Register. 0x1C -1 write-only n 0x0 0x0 RORIC Writing a 1 to this bit clears the rame was received when Rx FIFO was full interrupt. 0 1 ENUM 1 clear rx fifo 1 RTIC Writing a 1 to this bit clears the Rx FIFO was not empty and has not 1 2 ENUM 1 clear rx fifo 1 SSP0IMSC SSP Interrupt Mask Set and Clear Register. 0x10 -1 read-write n 0x0 0x0 RORIM Receive Overrun Interrupt Mask. 0 1 ENUM RORIM Rx FIFO written to while full condition interrupt is disabled. 0 RORIM Rx FIFO written to while full condition interrupt is disabled. 0 RTIM Receive Timeout Interrupt Mask. 1 2 ENUM RTIM Rx FIFO not empty and no read prior to timeout period interrupt is disabled. 0 RTIM Rx FIFO not empty and no read prior to timeout period interrupt is disabled. 0 RXIM Receive FIFO Interrupt Mask. 2 3 ENUM RXIM Rx FIFO half full or less condition interrupt is disabled. 0 RXIM Rx FIFO half full or less condition interrupt is disabled. 0 TXIM Transmit FIFO Interrupt Mask. 3 4 ENUM TXIM Tx FIFO half empty or less condition interrupt is disabled. 0 TXIM Tx FIFO half empty or less condition interrupt is disabled. 0 SSP0MIS SSP Masked Interrupt Status Register. 0x18 -1 read-only n 0x0 0x0 RORMIS This bit is 1 if another frame was completely received while the Rx FIFO was full, and this interrupt is enabled. 0 1 ENUM disable 0 enable 1 RTMIS This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at FSSPCLK. 1 2 ENUM disable 0 enable 1 RXMIS This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. 2 3 ENUM disable 0 enable 1 TXMIS This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. 3 4 ENUM disable 0 enable 1 SSP0RIS SSP Raw Interrupt Status Register. 0x14 -1 read-only n 0x0 0x0 RORRIS This bit is 1 if another frame was completely received while the Rx FIFO was full. 0 1 ENUM Empty 0 full 1 RTRIS This bit is 1 if the Rx FIFO is not empty 1 2 ENUM Empty 0 not empty 1 RXRIS This bit is 1 if the Rx FIFO is not empty 2 3 ENUM not half empty 0 half empty 1 TXRIS This bit is 1 if the Tx FIFO is at least half empty. 3 4 ENUM TX not half empty 0 TX half empty 1 SSP0STAT SSP Status Register. 0x4 -1 read-only n 0x0 0x0 BSY Busy flag. 4 5 ENUM IDLE SSP/SPI is idle 0 nEMPT SSP/SPI is currently transmitting and (or) receiving a frame or the transmit FIFO is not empty 1 RFF Receive FIFO Full. 3 4 ENUM RXFIFONFULL Receive FIFO in not full 0 RXFIFOFULL Receive FIFO is full 1 RNE Receive FIFO Not Empty. 2 3 ENUM RXFIFOEMP Receive FIFO is empty 0 RXFIFOEMP Receive FIFO is empty 0 TFE Transmit FIFO Empty. 0 1 ENUM TXFIFONMP Transmit FIFO is not empty 0 TXFIFOEPT Transmit FIFO is empty 1 TNF Transmit FIFO Not Full. 1 2 ENUM TXFIFOFULL Transmit FIFO is full 0 TXFIFONFULL Transmit FIFO is not full 1 SYSCON System configuration SYSCON 0x0 0x0 0xFFF registers n AHBCKDIV AHB CLK Division Register 0x4 -1 read-write n 0x0 0x0 AHBDIV System AHB clock divider values 0 8 APBCKDIV APB CLK Division Register 0x8 -1 read-write n 0x0 0x0 APBDIV System APB clock divider values 0 8 APBCKEN APB CLK Enable Register 0xC -1 read-write n 0x0 0x0 ADCCE ADC PCLK Enable 11 12 ENUM Disable Disable 0 Enable Enable 1 I2C0CE I2C0 PCLK Enable 7 8 ENUM Disable Disable 0 Enable Enable 1 I2C1CE I2C1 PCLK Enable 8 9 ENUM Disable Disable 0 Enable Enable 1 PWMCE Capture/PWM PCLK Enable 12 13 ENUM Disable Disable 0 Enable Enable 1 SSP0CE SSP0 PCLK Enable 9 10 ENUM Disable Disable 0 Enable Enable 1 TIMER01CE TIMER01 PCLK Enable 1 2 ENUM Disable Disable 0 Enable Enable 1 UART0CE UART0 PCLK Enable 3 4 ENUM Disable Disable 0 Enable Enable 1 UART1CE UART1 PCLK Enable 4 5 ENUM Disable Disable 0 Enable Enable 1 WDTCE WDT PCLK Enable 0 1 ENUM Disable Disable 0 Enable Enable 1 APBCKSEL APB Clock Source Select Register 0x2C -1 read-write n 0x0 0x0 TMR01SEL Timer 0/1 Clock Source Select 0 2 ENUM PCLK PCLK is select 0 PCLK PCLK is select 0 XOSC XOSC is select 2 10KHz 10KHz is select 3 CLKCON Clock Source Control Register 0x20 -1 read-write n 0x0 0x0 IRCEN IRC enable bit 3 4 ENUM disable disable 0 enable enable 1 IRCSEL IRC Select 0 1 ENUM 32M 32M 0 22.1184M 22.1184M 1 XOSCEN disable 4 5 ENUM disable disable 0 enable enable 1 XT_CHECK XT check bit 6 7 ENUM disable disable 0 enable enable 1 XT_SEL XT clock select 5 6 ENUM 32.768K 32.768K 0 HS HS 1 CLKODIV Clock Output pin Division Register 0x10 -1 read-write n 0x0 0x0 CLK_SEL CLK source select 9 11 ENUM HCLK HCLK 0 IHRC IHRC 1 XT XT 2 PLLCLK PLLCLK 3 DIV Clock output divider values 0 8 EN Clock output enable 8 9 ENUM disable disable 0 enable enable 1 CLKSEL Clock Source Select Register 0x24 -1 read-write n 0x0 0x0 CLKSEL Clock Source Select 0 2 ENUM IRC IRC is select 0 XOSC XOSC is select 1 10K IRC 10KHz is select 2 PLLCLK PLLCLK is select 3 CLKSTAT Clock Source Status Register 0x28 -1 read-only n 0x0 0x0 IRCSTB Internal OSC Status 0 1 ENUM not stable IRC is not stable or disable 0 stable IRC is stable. 1 XOSCSTB EXternal OSC Status 1 2 ENUM not stable External OSC is not stable ordisable. 0 stable External OSC is stable. 1 DID Device Identification Number Register 0x0 -1 read-only n 0x0 DNO Device number 16 32 DSF Device Size of Flash Programming memory. 0 8 ENUM 28K 28K 0x1C IOMUX Read from User Configuration IOMUX 0x30 -1 read-only n 0x0 0x0 RESETPORT External reset pin location 8 9 ENUM enable Enable external reset function.When external reset function enable, the reset pin will assign to P14 and P14 GPIO function MUX will disable. 0 disable Disable external reset function. 1 XTALPORT XTAL pin location 9 10 ENUM GPIO function P1.0/P1.1 assign to GPIO function. 0 disable P1.0/P1.1 assign to XTAL function. 1 IOP00CFG GPIO P00 Configuration Register 0x40 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 AN11 AN11 1 TXD0 TXD0 2 CTS0 CTS0 3 IOP01CFG GPIO P01 Configuration Register 0x44 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 AN12 AN12 1 RXD0 RXD0 2 RTS0 RTS0 3 SPI0_SS SPI0_SS 4 IOP04CFG GPIO P04 Configuration Register 0x50 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 PWM3B PWM3B 3 SPI0_SS SPI0_SS 4 IOP05CFG GPIO P05 Configuration Register 0x54 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 PWM3A PWM3A 3 SPI0_MOSI SPI0_MOSI 4 IOP06CFG GPIO P06 Configuration Register 0x58 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 PWM2B PWM2B 3 SPI0_MISO SPI0_MISO 4 IOP07CFG GPIO P07 Configuration Register 0x5C -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 PWM2A PWM2A 3 SPI0_CLK SPI0_CLK 4 IOP10CFG GPIO P10 Configuration Register 0x60 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 AN1 AN1 1 IOP12CFG GPIO P12 Configuration Register 0x68 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 AN2 AN2 1 RXD0 RXD0 2 PWM0A PWM0A 3 IOP13CFG GPIO P13 Configuration Register 0x6C -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 AN3 AN3 1 TXD0 TXD0 2 PWM0B PWM0B 3 IOP14CFG GPIO P14 Configuration Register 0x70 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 AN4 AN4 1 RXD1 RXD1 2 PWM2A PWM2A 3 IOP15CFG GPIO P15 Configuration Register 0x74 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 AN5 AN5 1 TXD1 TXD1 2 PWM2B PWM2B 3 IOP16CFG GPIO P16 Configuration Register 0x78 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 OSCI OSCI 1 RXD0 RXD0 2 SCL0 SCL0 3 IOP17CFG GPIO P17 Configuration Register 0x7C -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 OSCO OSCO 1 TXD0 TXD0 2 SDA0 SDA0 3 IOP21CFG GPIO P21 Configuration Register 0x84 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 IOP22CFG GPIO P22 Configuration Register 0x88 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 SCL0 SCL0 2 PWM0A PWM0A 3 CTS1 CTS1 4 IOP23CFG GPIO P23 Configuration Register 0x8C -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 SDA0 SDA0 2 PWM0B PWM0B 3 RTS1 RTS1 4 IOP24CFG GPIO P24 Configuration Register 0x90 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 RXD1 RXD1 2 PWM1A PWM1A 3 IOP25CFG GPIO P25 Configuration Register 0x94 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 TXD1 TXD1 2 PWM1B PWM1B 3 IOP26CFG GPIO P26 Configuration Register 0x98 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 PWM2A PWM2A 3 IOP30CFG GPIO P30 Configuration Register 0xA0 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 AN6 AN6 1 PWM0A PWM0A 3 IOP31CFG GPIO P31 Configuration Register 0xA4 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 AN7 AN7 1 PWM0B PWM0B 3 IOP32CFG GPIO P32 Configuration Register 0xA8 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 AN8 AN8 1 IOP34CFG GPIO P34 Configuration Register 0xB0 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 SDA0 SDA0 2 PWM3A PWM3A 3 IOP35CFG GPIO P35 Configuration Register 0xB4 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 AN10 AN10 1 SCL0 SCL0 2 PWM3B PWM3B 3 IOP36CFG GPIO P36 Configuration Register 0xB8 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 HCLKO HCLKO 3 IOP40CFG GPIO P40 Configuration Register 0xC0 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 IOP43CFG GPIO P43 Configuration Register 0xCC -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 IOP44CFG GPIO P44 Configuration Register 0xD0 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 IOP46CFG GPIO P46 Configuration Register 0xD8 -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 RXD1 RXD1 2 IOP47CFG GPIO P47 Configuration Register 0xDC -1 read-write n 0x0 0x0 CFG Pxx function config 0 3 ENUM GPIO GPIO 0 TXD1 TXD1 2 PCON Power Control Register 0x14 -1 read-write n 0x0 0x0 DEEPSLEEP deep sleep mode 1 2 ENUM disable disable 0 enable enable 1 PowerDown power donw mode 2 3 ENUM disable disable 0 enable enable 1 SLEEPMODE sleep mode 0 1 ENUM disable disable 0 enable enable 1 PLLCON PLL control register 0x114 -1 read-write n 0x0 0x0 BP PLL bypass mode 20 21 ENUM normal normal 0 Fin Pll out is source 1 EN PLL enable bit 0 1 ENUM disable disable 0 enable enable 1 FIN_DIV FLL clock source div 2 4 ENUM div 1 div 1 0 div 2 div 2 1 div 4 div 4 2 div 8 div 8 3 FIN_SEL PLL clock source select 1 2 ENUM IHRC IHRC 0 XT XT 1 M PLL enable bit 14 20 N PLL enable bit 8 14 OD PLL out div 6 8 PLLSTB PLL status bit 4 5 ENUM not stable not stable 0 stable stable 1 SEL_N PLL in source select 5 6 ENUM N no effect in clock = 1 0 N effect N effect 1 RSTCON Reset Control Register 0x18 -1 write-only n 0x0 0x0 CPURST CPU kernel Reset (Set this bit will reset the Cortex-M0 CPU kernel and FMC, but it won reload Configuration) 1 2 ENUM Normal Normal 0 Reset CPU Reset CPU 1 MCURST MCU reset 0 1 ENUM Normal Normal 0 Reset MCU Reset MCU, the Cortex-M0 CPU had issued the reset signal to reset the system by software writing 1 1 RSTSTAT Reset Status Register 0x1C -1 read-write n 0x0 0x0 CPURS CPU Reset Status 3 4 ENUM 0 No CPU reset detected. 0 1 CPU reset detected. 1 MCURS MCU Reset Status 1 2 ENUM 0 No MCU reset detected. 0 1 MCU reset detected. 1 WDTRS WDT Reset Status 0 1 ENUM 0 No WDT reset detected. 0 1 WDT reset detected. 1 SYS_ICLR Clock interrupt clear register 0x10C -1 read-write n 0x0 0x0 PLL_ICLR Clear PLL cloce interupt status bit. 1 2 ENUM 0 no effect 0 1 clear xt interrupt status bit 1 XT_ICLR Clear XT clock interrupt status bit. 0 1 ENUM 0 no effect 0 1 clear xt interrupt status bit 1 SYS_IMSC Clock Interrupt control register 0x100 -1 read-write n 0x0 0x0 PLL_IMSC PLL clock interrupt enable bit 1 2 ENUM disable disable 0 enable enable 1 XT_IMSC XT clock interrupt enable bit 0 1 ENUM disable disable 0 enable enable 1 SYS_MIS Clock interrupt status register 0x108 -1 read-write n 0x0 0x0 PLL_MIS PLL clock interrupt status bit 1 2 ENUM 0 0 0 1 1 1 XT_MIS XT clock interrupt status bit 0 1 ENUM 0 0 0 1 1 1 SYS_RIS Clock interrupt source register 0x104 -1 read-only n 0x0 0x0 PLL_RIS PLL clock source interrupe status 1 2 ENUM 0 0 0 1 1 1 XT_RIS XT clock source interrupt status 0 1 ENUM 0 0 0 1 1 1 SYS_TRIM IRC temper register 0x110 -1 read-write n 0x0 0x0 TIM0 TIM0 Control Register. TIM 0x0 0x0 0xFFF registers n TIMER01_IRQHandler 28 BGLOAD TimerBackground Load Register 0x18 -1 read-write n 0x0 0x0 BGLOAD The TMRxBGLOAD Register is 32-bits and contains the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches zero.This register provides an alternative method of accessing the TMRxBGLOADRegister.The difference is that writes toTMRxBGLOAD do not cause the counter to immediately restart from the new value. Reading from this register returns the same value returned from TMRxLOAD. 0 32 CON Timer Control Register 0x0 -1 read-write n 0x0 0x0 TMREN Timer Enable 7 8 ENUM disable Timer disable 0 enable Timer enable 1 TMRIE Interrupt Enable 5 6 ENUM disable Timer interrupt disable 0 enable Timer interrupt enable 1 TMRMS Timer mode select 6 7 ENUM free running mode Timer is in free running mode 0 periodic mode Timer is in periodic mode 1 TMROS Selects one-shot or wrapping counter mode 0 1 ENUM wrapping wrapping mode 0 one-shot one-shot mode 1 TMRPRE Timer prescale 2 4 ENUM div 1 Clock is diveded by 1 0 div 16 Clock is divided by 16 1 div 256 Clock is diveded by 256 2 TMRSZ Selects 16/32 bit counter operation 1 2 ENUM 16-bit 16-bit counter 0 32-bit 32-bit counter 1 ICLR Timerclear interrupt Register 0x14 -1 write-only n 0x0 0x0 ICLR Any write to the TMRxICLR Register clears the interrupt output from the counter. 0 32 LOAD Timer Load Register 0x4 -1 read-write n 0x0 0x0 LOAD When this register is written to directly,the current count is immediately reset to the new value at the next rising edge of TIMER CLK that is enabled by TIMER CLK enable. The value in this register is aslo overwritten if the TMRxBGLOAD Register is written to , but the current count is not immediately affected. If values are written to both the TMRxLOAD and TMRxBGLOAD Registers before an enabled rising edge on TIMER CLK, the following occurs: 1.On the next enabled TIMER CLK edge, the value written to the TMRXLOAD value replaces the current count value. 2.Then, each time the counter reaches zero, the current count value is reset to the value written to TMRxBGLOA.Reading from the TMRXLOAD Register at any time after the two writes have occurred retrieves the value written to TMRxBGLOA.That is the value that takes effect for Periodic mode after the next time the counter reaches zero. 0 32 MIS TimerMasked interrupt Status Register 0x10 -1 read-only n 0x0 0x0 MIS Enable interrupt status from the counter 0 1 RIS TimerRaw interrupt Status Register 0xC -1 read-only n 0x0 0x0 RIS Raw interrupt status from the counter 0 1 VAL TimerCurrent Value Register 0x8 -1 read-only n 0x0 0x0 VAL The TMRxVAL Register gives the current value of the decrementing counter. 0 32 TIM1 TIM0 Control Register. TIM 0x0 0x0 0xFFF registers n TIMER01_IRQHandler 28 BGLOAD TimerBackground Load Register 0x18 -1 read-write n 0x0 0x0 BGLOAD The TMRxBGLOAD Register is 32-bits and contains the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches zero.This register provides an alternative method of accessing the TMRxBGLOADRegister.The difference is that writes toTMRxBGLOAD do not cause the counter to immediately restart from the new value. Reading from this register returns the same value returned from TMRxLOAD. 0 32 CON Timer Control Register 0x0 -1 read-write n 0x0 0x0 TMREN Timer Enable 7 8 ENUM disable Timer disable 0 enable Timer enable 1 TMRIE Interrupt Enable 5 6 ENUM disable Timer interrupt disable 0 enable Timer interrupt enable 1 TMRMS Timer mode select 6 7 ENUM free running mode Timer is in free running mode 0 periodic mode Timer is in periodic mode 1 TMROS Selects one-shot or wrapping counter mode 0 1 ENUM wrapping wrapping mode 0 one-shot one-shot mode 1 TMRPRE Timer prescale 2 4 ENUM div 1 Clock is diveded by 1 0 div 16 Clock is divided by 16 1 div 256 Clock is diveded by 256 2 TMRSZ Selects 16/32 bit counter operation 1 2 ENUM 16-bit 16-bit counter 0 32-bit 32-bit counter 1 ICLR Timerclear interrupt Register 0x14 -1 write-only n 0x0 0x0 ICLR Any write to the TMRxICLR Register clears the interrupt output from the counter. 0 32 LOAD Timer Load Register 0x4 -1 read-write n 0x0 0x0 LOAD When this register is written to directly,the current count is immediately reset to the new value at the next rising edge of TIMER CLK that is enabled by TIMER CLK enable. The value in this register is aslo overwritten if the TMRxBGLOAD Register is written to , but the current count is not immediately affected. If values are written to both the TMRxLOAD and TMRxBGLOAD Registers before an enabled rising edge on TIMER CLK, the following occurs: 1.On the next enabled TIMER CLK edge, the value written to the TMRXLOAD value replaces the current count value. 2.Then, each time the counter reaches zero, the current count value is reset to the value written to TMRxBGLOA.Reading from the TMRXLOAD Register at any time after the two writes have occurred retrieves the value written to TMRxBGLOA.That is the value that takes effect for Periodic mode after the next time the counter reaches zero. 0 32 MIS TimerMasked interrupt Status Register 0x10 -1 read-only n 0x0 0x0 MIS Enable interrupt status from the counter 0 1 RIS TimerRaw interrupt Status Register 0xC -1 read-only n 0x0 0x0 RIS Raw interrupt status from the counter 0 1 VAL TimerCurrent Value Register 0x8 -1 read-only n 0x0 0x0 VAL The TMRxVAL Register gives the current value of the decrementing counter. 0 32 UART0 UART Control Register. UART 0x0 0x0 0xFFF registers n UART0_IRQHandler 15 UART0DLR UART Divisor Latch Register 0x8 -1 read-write n 0x0 0x0 DLR Divisor Latch Register. The full divisor isused to generate a baud rate from the fractional rate divider. Baud rate = PCLK/16xDLR 0 16 UART0EFR Enhanced features register 0x2C -1 read-write n 0x0 0x0 AUTOCTS Enables hardware transmission flow control 7 8 ENUM disable disable 0 enable enable 1 AUTORTS Enables hardware reception flow control (RTS=0, RTS pin is high) 6 7 ENUM disable disable 0 enable enable 1 MEEN M16x50 Enhancements Enables 4 5 ENUM disable disable 0 enable enable 1 RXSWFC RX Software Flow Control 0 2 ENUM No No RX Flow Control 0 XON1/XOFF1 Receive XON1/XOFF1 as flow control bytes 1 XON2/XOFF2 Receive XON2/XOFF2 as flow control bytes 2 XON1 XON2 and XOFF1 XOFF2 Receive XON1 XON2 and XOFF1 XOFF2 as flow control words 3 TXSWFC TX Software Flow Control 2 4 ENUM No No TX Flow Control 0 XON1/XOFF1 Transmit XON1/XOFF1 as flow control bytes 1 XON2/XOFF2 Transmit XON2/XOFF2 as flow control bytes 2 XON1 XON2 and XOFF1 XOFF2 Transmit XON1 XON2 and XOFF1 XOFF2 as flow control words 3 UART0FCR FIFO control register. Control UART FIFO usage and modes. 0x14 -1 read-write n 0x0 0x0 FIFOEN FIFO Enable 0 1 ENUM Disable FIFO UART FIFOs are disabled. Must not be used in the application. 0 Enable FIFO Active high enable for both UART RX and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the UART FIFOs. 1 RXFIFORST RX FIFO Reset 1 2 ENUM No impact No impact on either of UART FIFOs. 0 clear FIFO Writing a logic 1 to FCR[1] will clear all bytes in UART RX FIFO, reset the pointer logic. This bit is self-clearing. 1 RXTL RX Trigger Level. These two bits determine how many receiver UART FIFO characters must be written before an interrupt is activated. 6 8 ENUM level 0 Trigger level 0 (1 character). 0 level 1 Trigger level 1 (4 characters). 1 level 2 Trigger level 2 (8 characters). 2 level 3 Trigger level 3 (14 characters). 3 TXFIFORST TX FIFO Reset 2 3 ENUM no impact No impact on either of UART FIFOs. 0 TX FIFO Reset Writing a logic 1 to FCR[2] will clear all bytes in UART TX FIFO, reset the pointer logic. This bit is self-clearing. 1 TXTL TX Trigger Level. These two bits determine how many transmit UART FIFO characters must be written before an interrupt is activated. 4 6 ENUM level 0 Trigger level 0 (1 character). 0 level 1 Trigger level 1 (4 characters). 1 level 2 Trigger level 2 (8 characters). 2 level 3 Trigger level 3 (14 characters). 3 UART0IER Interrupt enable register. Contains individual interrupt enable bits for the 7 potential UART interrupts. 0xC -1 read-write n 0x0 0x0 CTSIE CTS Interrupt Enable. Enable a rising edge is detected on the CTS modem control line. 7 8 ENUM disable Disable the CTS interrupt. 0 enable Enable the CTS interrupt. 1 MDSIE Modem Status Interrupt Enable. 3 4 ENUM disable Disable the modem status interrupts. 0 enable Enable the modem status interrup 1 RBRIE RX Buffer Register Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive Time-out interrupt. 0 1 ENUM disable Disable the RBRIE interrupts. 0 enable Enable the RBRIE interrupts. 1 RLSIE RX Line Status Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from LSR[4:1]. 2 3 ENUM disable Disable the RX line status interrupts. 0 enable Enable the RX line status interrupts. 1 RTSIE RTS Interrupt Enable. Enable a rising edge is detected on the RTS modem control line. 6 7 ENUM disable Disable the RTS interrupt. 0 enable Enable the RTS interrupt. 1 THREIE TX Holding Register Empty Interrupt Enable. Enables the THREIE interrupt for UART. The status of this interrupt can be read from LSR[5]. 1 2 ENUM disable Disable the THREIE interrupts. 0 enable Enable the THREIE interrupts. 1 XOFIE XOFF Interrupt Enable. Enable an XOFF character is received. 5 6 ENUM disable Disable the XOF interrupt. 0 enable Enable the XOF interrupt. 1 UART0IIR Interrupt identification register. Identifies which interrupts are pending. 0x10 -1 read-only n 0x0 0x0 INTHFC Hardware Flow Control (CTS or RTS rising edge) If Set (indicating that an XOFF character has been received. It is cleared by reading the Interrupt Identification Register. 5 6 ENUM INTHFC No interrupt is pending. 1 INTHFC No interrupt is pending. 1 INTID Interrupt identification. 1 4 ENUM 4 - Modem Status change. 4 - Modem Status change. 0 3 - TX Holding Register Empty. 3 - TX Holding Register Empty. 1 2a - Receive Data Available. 2a - Receive Data Available. 2 1 - Receive Line Status. 1 - Receive Line Status. 3 2b - Receive FIFO Character 2b - Receive FIFO Character 6 INTSFC Software Flow Control (XOFF character received) If Set (indicating that a rising edge has been detected on either the RTS/CTS Modem Control line. It is cleared by reading the Interrupt Identification Register. 4 5 ENUM INTSFC 1 INTSFC 1 INTSTATUS Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR3-1 0 1 ENUM INT STATUS No interrupt is pending. 1 INT STATUS No interrupt is pending. 1 UART0LCR Line status register. Contains controls for frame formatting and break generation. 0x18 -1 read-write n 0x0 0x0 BCON Break Control 6 7 ENUM Disable Disable break transmission. 0 Enable Enable break transmission. Output pin UART TXD is forced to logic 0 when LCR[6] is active high. 1 PEN Parity Enable 3 4 ENUM Disable Disable parity generation and checking. 0 Enable Enable parity generation and checking. 1 PSEL Parity Select 4 6 ENUM Odd parity Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 0 Even parity Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 1 Forced 1 Forced 1 stick parity. 2 Forced 0 Forced 0 stick parity. 3 SBS Stop Bit Select 2 3 ENUM 1 Stop bit 1 stop bit. 0 2 Stop bit 2 stop bits (1.5 if LCR[1:0]=00). 1 WLS Word Length Select 0 2 ENUM 5-bit 5-bit character length. 0 6-bit 6-bit character length. 1 7-bit 7-bit character length. 2 8-bit 8-bit character length. 3 UART0LSR Line status register. Contain flags for transmit and receive status, including line errors. 0x20 -1 read-only n 0x0 0x0 BI Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO. 4 5 ENUM inactive Break interrupt status is inactive. 0 active Break interrupt status is active. 1 FE Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO. 3 4 ENUM inactive Framing error status is inactive. 0x0 active Framing error status is active. 0x1 OE Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost. 1 2 ENUM inactive Overrun error status is inactive. 0 active Overrun error status is active. 1 PE Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART RBR FIFO. 2 3 ENUM inactive Parity error status is inactive. 0 active Parity error status is active. 1 RDR Receiver Data Ready: LSR[0] is set when the RBR holds an unread character and is cleared when the UART RBR FIFO is empty. 0 1 ENUM empty RDR is empty 0 contains valid data RDR contains valid data. 1 RXFE Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR.This bit is cleared when the LSR register is read and there are no subsequent errors in the UART FIFO. 7 8 ENUM RXFE UART RBR contains at least one UART RX error. 1 RXFE UART RBR contains at least one UART RX error. 1 TEMT Transmitter Empty. TEMT is set when both THR and TSR are empty TEMT is cleared when either the TSR or the THR contain valid data. 6 7 ENUM contains valid data THR and/or the TSR contains valid data. 0 empty THR and the TSR are empty. 1 THRE Transmitter Holding Register Empty.THRE is set immediately upon detection of an empty UART THR and is cleared on a THR write. 5 6 ENUM contains valid data THR contains valid data. 0 empty THR is empty. 1 UART0MCR Modem control register 0x1C -1 read-write n 0x0 0x0 IREN IrDA mode enables 6 7 ENUM disable IrDA mode on UART is disabled, 0 enable IrDA mode on UART is enabled. 1 MLBM Modem Loop back mode 4 5 ENUM disable Disable modem loopback mode. 0 enable Enable modem loopback mode. 1 RTS Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active. 1 2 ENUM high Drive RTS pin high. 0 low Drive RTS pin low. 1 XOFFS XOFF Status This read-only bit is set to 1 when an XOFF character is received and cleared when an XON character is received 7 8 ENUM XOFFS 1 XOFFS 1 UART0MSR Modem status register 0x24 -1 read-only n 0x0 0x0 CTS Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode 4 5 DCTS Delta CTS. Set upon state change of input CTS. Cleared on an MSR read. 0 1 ENUM No change detected No change detected on modem input, CTS. 0 State change detected State change detected on modem input, CTS. 1 UART0RBR Receiver buffer register. Contain the next received character to be read. 0x0 -1 read-only n 0x0 0x0 RBR The UART Receiver Buffer Register contains the oldest received byte in the UART RX FIFO. 0 8 UART0SCR Scratch Pad Register. Eight-bit temporary storage for software. 0x28 -1 read-write n 0x0 0x0 PAD A readable, writable byte. 0 8 UART0THR Transistor holding register. The next character to be transmitted is written here. 0x4 -1 write-only n 0x0 0x0 THR Writing to the UART Transmit Holding Register causes the data to be stored in the UART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. 0 8 UART0XOFF1 XOFF1 Register 0x38 -1 read-write n 0x0 0x0 HXOFF hold the XOFF characters used in software control of transmission and reception 0 8 UART0XOFF2 XOFF2 Register 0x3C -1 read-write n 0x0 0x0 HXOFF hold the XOFF characters used in software control of transmission and reception 0 8 UART0XON1 XON1 Register 0x30 -1 read-write n 0x0 0x0 HXON hold the XON characters used in software control of transmission and reception 0 8 UART0XON2 XON2 Register 0x34 -1 read-write n 0x0 0x0 HXON hold the XON characters used in software control of transmission and reception 0 8 UART1 UART Control Register. UART 0x0 0x0 0xFFF registers n UART0_IRQHandler 15 UART0DLR UART Divisor Latch Register 0x8 -1 read-write n 0x0 0x0 DLR Divisor Latch Register. The full divisor isused to generate a baud rate from the fractional rate divider. Baud rate = PCLK/16xDLR 0 16 UART0EFR Enhanced features register 0x2C -1 read-write n 0x0 0x0 AUTOCTS Enables hardware transmission flow control 7 8 ENUM disable disable 0 enable enable 1 AUTORTS Enables hardware reception flow control (RTS=0, RTS pin is high) 6 7 ENUM disable disable 0 enable enable 1 MEEN M16x50 Enhancements Enables 4 5 ENUM disable disable 0 enable enable 1 RXSWFC RX Software Flow Control 0 2 ENUM No No RX Flow Control 0 XON1/XOFF1 Receive XON1/XOFF1 as flow control bytes 1 XON2/XOFF2 Receive XON2/XOFF2 as flow control bytes 2 XON1 XON2 and XOFF1 XOFF2 Receive XON1 XON2 and XOFF1 XOFF2 as flow control words 3 TXSWFC TX Software Flow Control 2 4 ENUM No No TX Flow Control 0 XON1/XOFF1 Transmit XON1/XOFF1 as flow control bytes 1 XON2/XOFF2 Transmit XON2/XOFF2 as flow control bytes 2 XON1 XON2 and XOFF1 XOFF2 Transmit XON1 XON2 and XOFF1 XOFF2 as flow control words 3 UART0FCR FIFO control register. Control UART FIFO usage and modes. 0x14 -1 read-write n 0x0 0x0 FIFOEN FIFO Enable 0 1 ENUM Disable FIFO UART FIFOs are disabled. Must not be used in the application. 0 Enable FIFO Active high enable for both UART RX and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the UART FIFOs. 1 RXFIFORST RX FIFO Reset 1 2 ENUM No impact No impact on either of UART FIFOs. 0 clear FIFO Writing a logic 1 to FCR[1] will clear all bytes in UART RX FIFO, reset the pointer logic. This bit is self-clearing. 1 RXTL RX Trigger Level. These two bits determine how many receiver UART FIFO characters must be written before an interrupt is activated. 6 8 ENUM level 0 Trigger level 0 (1 character). 0 level 1 Trigger level 1 (4 characters). 1 level 2 Trigger level 2 (8 characters). 2 level 3 Trigger level 3 (14 characters). 3 TXFIFORST TX FIFO Reset 2 3 ENUM no impact No impact on either of UART FIFOs. 0 TX FIFO Reset Writing a logic 1 to FCR[2] will clear all bytes in UART TX FIFO, reset the pointer logic. This bit is self-clearing. 1 TXTL TX Trigger Level. These two bits determine how many transmit UART FIFO characters must be written before an interrupt is activated. 4 6 ENUM level 0 Trigger level 0 (1 character). 0 level 1 Trigger level 1 (4 characters). 1 level 2 Trigger level 2 (8 characters). 2 level 3 Trigger level 3 (14 characters). 3 UART0IER Interrupt enable register. Contains individual interrupt enable bits for the 7 potential UART interrupts. 0xC -1 read-write n 0x0 0x0 CTSIE CTS Interrupt Enable. Enable a rising edge is detected on the CTS modem control line. 7 8 ENUM disable Disable the CTS interrupt. 0 enable Enable the CTS interrupt. 1 MDSIE Modem Status Interrupt Enable. 3 4 ENUM disable Disable the modem status interrupts. 0 enable Enable the modem status interrup 1 RBRIE RX Buffer Register Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive Time-out interrupt. 0 1 ENUM disable Disable the RBRIE interrupts. 0 enable Enable the RBRIE interrupts. 1 RLSIE RX Line Status Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from LSR[4:1]. 2 3 ENUM disable Disable the RX line status interrupts. 0 enable Enable the RX line status interrupts. 1 RTSIE RTS Interrupt Enable. Enable a rising edge is detected on the RTS modem control line. 6 7 ENUM disable Disable the RTS interrupt. 0 enable Enable the RTS interrupt. 1 THREIE TX Holding Register Empty Interrupt Enable. Enables the THREIE interrupt for UART. The status of this interrupt can be read from LSR[5]. 1 2 ENUM disable Disable the THREIE interrupts. 0 enable Enable the THREIE interrupts. 1 XOFIE XOFF Interrupt Enable. Enable an XOFF character is received. 5 6 ENUM disable Disable the XOF interrupt. 0 enable Enable the XOF interrupt. 1 UART0IIR Interrupt identification register. Identifies which interrupts are pending. 0x10 -1 read-only n 0x0 0x0 INTHFC Hardware Flow Control (CTS or RTS rising edge) If Set (indicating that an XOFF character has been received. It is cleared by reading the Interrupt Identification Register. 5 6 ENUM INTHFC No interrupt is pending. 1 INTHFC No interrupt is pending. 1 INTID Interrupt identification. 1 4 ENUM 4 - Modem Status change. 4 - Modem Status change. 0 3 - TX Holding Register Empty. 3 - TX Holding Register Empty. 1 2a - Receive Data Available. 2a - Receive Data Available. 2 1 - Receive Line Status. 1 - Receive Line Status. 3 2b - Receive FIFO Character 2b - Receive FIFO Character 6 INTSFC Software Flow Control (XOFF character received) If Set (indicating that a rising edge has been detected on either the RTS/CTS Modem Control line. It is cleared by reading the Interrupt Identification Register. 4 5 ENUM INTSFC 1 INTSFC 1 INTSTATUS Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR3-1 0 1 ENUM INT STATUS No interrupt is pending. 1 INT STATUS No interrupt is pending. 1 UART0LCR Line status register. Contains controls for frame formatting and break generation. 0x18 -1 read-write n 0x0 0x0 BCON Break Control 6 7 ENUM Disable Disable break transmission. 0 Enable Enable break transmission. Output pin UART TXD is forced to logic 0 when LCR[6] is active high. 1 PEN Parity Enable 3 4 ENUM Disable Disable parity generation and checking. 0 Enable Enable parity generation and checking. 1 PSEL Parity Select 4 6 ENUM Odd parity Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 0 Even parity Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 1 Forced 1 Forced 1 stick parity. 2 Forced 0 Forced 0 stick parity. 3 SBS Stop Bit Select 2 3 ENUM 1 Stop bit 1 stop bit. 0 2 Stop bit 2 stop bits (1.5 if LCR[1:0]=00). 1 WLS Word Length Select 0 2 ENUM 5-bit 5-bit character length. 0 6-bit 6-bit character length. 1 7-bit 7-bit character length. 2 8-bit 8-bit character length. 3 UART0LSR Line status register. Contain flags for transmit and receive status, including line errors. 0x20 -1 read-only n 0x0 0x0 BI Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO. 4 5 ENUM inactive Break interrupt status is inactive. 0 active Break interrupt status is active. 1 FE Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO. 3 4 ENUM inactive Framing error status is inactive. 0x0 active Framing error status is active. 0x1 OE Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost. 1 2 ENUM inactive Overrun error status is inactive. 0 active Overrun error status is active. 1 PE Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART RBR FIFO. 2 3 ENUM inactive Parity error status is inactive. 0 active Parity error status is active. 1 RDR Receiver Data Ready: LSR[0] is set when the RBR holds an unread character and is cleared when the UART RBR FIFO is empty. 0 1 ENUM empty RDR is empty 0 contains valid data RDR contains valid data. 1 RXFE Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR.This bit is cleared when the LSR register is read and there are no subsequent errors in the UART FIFO. 7 8 ENUM RXFE UART RBR contains at least one UART RX error. 1 RXFE UART RBR contains at least one UART RX error. 1 TEMT Transmitter Empty. TEMT is set when both THR and TSR are empty TEMT is cleared when either the TSR or the THR contain valid data. 6 7 ENUM contains valid data THR and/or the TSR contains valid data. 0 empty THR and the TSR are empty. 1 THRE Transmitter Holding Register Empty.THRE is set immediately upon detection of an empty UART THR and is cleared on a THR write. 5 6 ENUM contains valid data THR contains valid data. 0 empty THR is empty. 1 UART0MCR Modem control register 0x1C -1 read-write n 0x0 0x0 IREN IrDA mode enables 6 7 ENUM disable IrDA mode on UART is disabled, 0 enable IrDA mode on UART is enabled. 1 MLBM Modem Loop back mode 4 5 ENUM disable Disable modem loopback mode. 0 enable Enable modem loopback mode. 1 RTS Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active. 1 2 ENUM high Drive RTS pin high. 0 low Drive RTS pin low. 1 XOFFS XOFF Status This read-only bit is set to 1 when an XOFF character is received and cleared when an XON character is received 7 8 ENUM XOFFS 1 XOFFS 1 UART0MSR Modem status register 0x24 -1 read-only n 0x0 0x0 CTS Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode 4 5 DCTS Delta CTS. Set upon state change of input CTS. Cleared on an MSR read. 0 1 ENUM No change detected No change detected on modem input, CTS. 0 State change detected State change detected on modem input, CTS. 1 UART0RBR Receiver buffer register. Contain the next received character to be read. 0x0 -1 read-only n 0x0 0x0 RBR The UART Receiver Buffer Register contains the oldest received byte in the UART RX FIFO. 0 8 UART0SCR Scratch Pad Register. Eight-bit temporary storage for software. 0x28 -1 read-write n 0x0 0x0 PAD A readable, writable byte. 0 8 UART0THR Transistor holding register. The next character to be transmitted is written here. 0x4 -1 write-only n 0x0 0x0 THR Writing to the UART Transmit Holding Register causes the data to be stored in the UART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. 0 8 UART0XOFF1 XOFF1 Register 0x38 -1 read-write n 0x0 0x0 HXOFF hold the XOFF characters used in software control of transmission and reception 0 8 UART0XOFF2 XOFF2 Register 0x3C -1 read-write n 0x0 0x0 HXOFF hold the XOFF characters used in software control of transmission and reception 0 8 UART0XON1 XON1 Register 0x30 -1 read-write n 0x0 0x0 HXON hold the XON characters used in software control of transmission and reception 0 8 UART0XON2 XON2 Register 0x34 -1 read-write n 0x0 0x0 HXON hold the XON characters used in software control of transmission and reception 0 8 WDT WDT Control Register. WDT 0x0 0x0 0xFFF registers n WDT_IRQHandler 23 CON Watchdog Control Register 0x0 -1 read-write n 0x0 0x0 WDTEN WDT reset enable 8 16 WDTIEN WDT interrupt enable bit 0 1 ENUM disable disable WDT interrupt 0 enable enable WDT interrupt 1 WDTPRE WDT clock select 2 4 ENUM div 1 Clock is divided by 1 0 div 16 Clock is divided by 16 1 div 256 Clock is divided by 256 2 ICLR Watchdog Clear Interrupt Register 0x14 -1 write-only n 0x0 0x0 PWMLOAD Write 0x55AA55AA clear WDT and clear over flow Flag bit. 0 32 LOAD Watchdog Load Register 0x4 -1 read-write n 0x0 0x0 PWMLOAD PWM load value 0 32 LOCK Watchdog Lock Register 0x18 -1 read-write n 0x0 0x0 WDTKEY Enable write access to all other registers by writing 0x2AD5334C. Disable write access by writing any other value. 1 32 WDTREN Register write enable 0 1 ENUM disable Write access to all other registers is disabled 0 enable Write access to all other registers is enabled 1 MIS Watchdog Masked Interrupt Status Register 0x10 -1 read-only n 0x0 0x0 WDTMIS interrupt enable bit 0 1 ENUM disable Disable interrupt status from the counter 0 enable Enabled interrupt status from the counter 1 RIS Watchdog Raw Interrupt Status Register 0xC -1 read-only n 0x0 0x0 WDTRIS Raw interrupt status from the counter 0 1 VAL Watchdog Current Value Register 0x8 -1 read-only n 0x0 0x0 WDTVAL The WDTVAL Register gives the current value of the decrementing counter. 0 32