Dialog DA14531 2024.04.26 531 CM0 r1p0 little true 3 false 8 32 adplldig adplldig registers Peripheral_Registers 0x0 0x0 0x98 registers n ADPLL_ACC_CTRL_REG 0x64 32 read-write n 0x0 0x0 CLIP_MOD_TUNE_0_RX 0 13 read-write CLIP_MOD_TUNE_0_TX 16 29 read-write EN_CMF_AVG 31 32 read-write ADPLL_ANATST_CTRL_REG 0x60 32 read-write n 0x0 0x0 ANATSTEN 0 16 read-write ANATSTSPARE 16 32 read-write ADPLL_ANATST_RD_REG 0x94 32 read-write n 0x0 0x0 ANATSTSPARE_IN 0 16 read-only ADPLL_ANA_CTRL_REG 0x34 32 read-write n 0x0 0x0 DTCOFFSET 8 15 read-write DTC_EN 15 16 read-write DTC_LDO_DMY 27 29 read-write EN_CKDCOMOD 6 7 read-write INV_CKDCOMOD 5 6 read-write INV_CKPHV 4 5 read-write INV_CKTDC 3 4 read-write TDC_CKVIN_EN 1 2 read-write TDC_DTCIN_EN 0 1 read-write TDC_INV 2 3 read-write TDC_OFFSET 16 22 read-write TGLDETEN 7 8 read-write VPASETTLE 24 26 read-write ADPLL_ATTR_CTRL_REG 0x0 32 read-write n 0x0 0x0 PWR_MODE_RX 0 1 read-write PWR_MODE_TX 1 2 read-write ADPLL_CN_CTRL_REG 0x4 32 read-write n 0x0 0x0 CH0 16 29 read-write CN 0 7 read-write CS 8 9 read-write SGN 15 16 read-write ADPLL_DCOAMP_CAL_CTRL_REG 0x20 32 read-write n 0x0 0x0 AMPCALEN 6 7 read-write DCOAMPIC_HP_RX 16 20 read-write DCOAMPIC_HP_TX 20 24 read-write DCOAMPIC_LP_RX 24 28 read-write DCOAMPIC_LP_TX 28 32 read-write DCOAMPTM 7 8 read-write KCOARSE 0 3 read-write KMEDIUM 3 6 read-write ADPLL_DCO_RD_REG 0x80 32 read-write n 0x0 0x0 DCOAMP 26 30 read-only DCOCOARSE 0 4 read-only DCOFINE 7 13 read-only DCOMEDIUM 4 7 read-only DCOMOD 13 26 read-only ADPLL_DIV_CTRL_REG 0x38 32 read-write n 0x0 0x0 FBDIV_EN 0 1 read-write RXDIV_FB_EN_RX 1 2 read-write RXDIV_FB_EN_TX 2 3 read-write RXDIV_TRIM 8 17 read-write TXDIV_TRIM 17 26 read-write ADPLL_FIF_CTRL1_REG 0x8 32 read-write n 0x0 0x0 FIFRX_1M 0 14 read-write ADPLL_FIF_CTRL2_REG 0xC 32 read-write n 0x0 0x0 FIFRX_OFFSET 0 14 read-write FIFTX 16 30 read-write ADPLL_FREQMEAS_RD_REG 0x7C 32 read-write n 0x0 0x0 FREQDIFF 0 23 read-only MEASDONE_OUT 29 30 read-only PHVSA0 24 25 read-only PHVSA1 23 24 read-only QUALMONDET 26 27 read-only TDCBUB 25 26 read-only ADPLL_FSM_CTRL_REG 0x40 32 read-write n 0x0 0x0 TCOARSE 0 4 read-write TFINE 8 12 read-write TMEDIUM 4 8 read-write TMOD 12 16 read-write TPASETTLE 16 20 read-write TSETTLE 20 24 read-write TVPASETTLE 24 30 read-write ADPLL_INIT_CTRL_REG 0x3C 32 read-write n 0x0 0x0 DCOCOARSEIC 0 4 read-write DCOFINEIC 8 14 read-write DCOMEDIUMIC 4 7 read-write DCOMODIC 16 29 read-write ADPLL_KDCO_CAL_CTRL1_REG 0x10 32 read-write n 0x0 0x0 KDCOHFIC_1M 0 8 read-write KDCOLF_IN_1M 8 16 read-write ADPLL_KDCO_CAL_CTRL2_REG 0x14 32 read-write n 0x0 0x0 KDCOCALRX 28 29 read-write KDCOCALTX 29 30 read-write KDCOCN_IC 16 23 read-write KDCOESTDEV 30 32 read-write KDCOLFCALEN 27 28 read-write KMOD_ALPHA_1M 0 5 read-write TKDCOCAL 24 27 read-write ADPLL_KDCO_RD_REG 0x84 32 read-write n 0x0 0x0 CAL_KDCOCAL 23 24 read-only KDCOCN 16 23 read-only KDCO_HF_INT 0 8 read-only KDCO_HF_OUT 8 16 read-only ADPLL_KDTCTDC_CAL_CTRL1_REG 0x18 32 read-write n 0x0 0x0 KDTCCN_IC 16 23 read-write KDTCIC 23 32 read-write KDTC_ALPHA 0 6 read-write KDTC_PIPELINE_BYPASS 15 16 read-write KTDC_IN 6 15 read-write ADPLL_KDTCTDC_CAL_CTRL2_REG 0x1C 32 read-write n 0x0 0x0 KDTCCALEN 0 1 read-write KDTCCALLG 4 7 read-write KDTCCALMOD 1 2 read-write KDTCCALMOD1P 2 3 read-write KDTCCAL_INV 3 4 read-write KTDCCALEN 8 9 read-write PHRDLY 9 11 read-write PHRDLY_EXTRA 15 16 read-write TKDTCCAL 11 15 read-write ADPLL_KDTC_RD_REG 0x88 32 read-write n 0x0 0x0 CAL_KDTCCAL 25 26 read-only KDTCCN 9 16 read-only KDTC_ALPHA_COMP 16 25 read-only KDTC_OUT 0 9 read-only ADPLL_LF_CTRL1_REG 0x2C 32 read-write n 0x0 0x0 FINEK 5 10 read-write FINEKZ 10 16 read-write FINETAU 0 5 read-write ADPLL_LF_CTRL2_REG 0x30 32 read-write n 0x0 0x0 MODK 18 24 read-write MODKZ 24 30 read-write MODK_TUNE 6 12 read-write MODTAU 12 18 read-write MODTAU_TUNE 0 6 read-write RST_TAU_EN 30 31 read-write ADPLL_MISC_CTRL_REG 0x48 32 read-write n 0x0 0x0 DLYFCWDT 0 2 read-write ENFCWMOD 7 8 read-write ENRESIDUE 6 7 read-write MODDLY 4 6 read-write PHR_FRAC_PRESET_VAL 8 24 read-write RESDLY 2 4 read-write ADPLL_MON_CTRL_REG 0x44 32 read-write n 0x0 0x0 ENRFMEAS 6 7 read-write HOLD_STATE 8 12 read-write QUALMONFRCEN 30 31 read-write QUALMONMOD 16 18 read-write QUALMONTRHLD 24 30 read-write QUALMONWND 18 24 read-write RFMEAS_MODE 7 8 read-write TFREQMEAS 0 5 read-write TMREN 5 6 read-write ADPLL_OVERRULE_CTRL1_REG 0x50 32 read-write n 0x0 0x0 OVR_ACTIVE_SEL 0 1 read-write OVR_ACTIVE_WR 1 2 read-write OVR_DCOAMPHOLD_SEL 12 13 read-write OVR_DCOAMPHOLD_WR 13 14 read-write OVR_DCOAMP_SEL 16 17 read-write OVR_DCOAMP_WR 17 21 read-write OVR_DTC_OH_SEL 24 25 read-write OVR_DTC_OH_WR 25 32 read-write OVR_ENPAIN_SEL 4 5 read-write OVR_ENPAIN_WR 5 6 read-write OVR_RDYFORDIV_SEL 10 11 read-write OVR_RDYFORDIV_WR 11 12 read-write OVR_RXBIT_SEL 2 3 read-write OVR_RXBIT_WR 3 4 read-write OVR_SRESETN_SEL 6 7 read-write OVR_SRESETN_WR 7 8 read-write OVR_VPAEN_SEL 8 9 read-write OVR_VPAEN_WR 9 10 read-write ADPLL_OVERRULE_CTRL2_REG 0x54 32 read-write n 0x0 0x0 OVR_DCOCOARSE_SEL 0 1 read-write OVR_DCOCOARSE_WR 1 5 read-write OVR_DCOFINE_SEL 16 17 read-write OVR_DCOFINE_WR 17 23 read-write OVR_DCOMEDIUM_SEL 8 9 read-write OVR_DCOMEDIUM_WR 9 12 read-write OVR_DCOMOD_SEL 23 24 read-write OVR_DCOMOD_WR 24 32 read-write ADPLL_OVERRULE_CTRL3_REG 0x58 32 read-write n 0x0 0x0 OVR_FBDIV_EN_SEL 4 5 read-write OVR_FBDIV_EN_WR 5 6 read-write OVR_RXDIV_EN_SEL 0 1 read-write OVR_RXDIV_EN_WR 1 2 read-write OVR_RXDIV_FB_EN_SEL 6 7 read-write OVR_RXDIV_FB_EN_WR 7 8 read-write OVR_TXDIV_EN_SEL 2 3 read-write OVR_TXDIV_EN_WR 3 4 read-write ADPLL_PLLFCWDT_RD_REG 0x90 32 read-write n 0x0 0x0 PLLFCWDT 0 23 read-only ADPLL_RFPT_CTRL_REG 0x5C 32 read-write n 0x0 0x0 INV_CKRFPT 4 5 read-write RFPT_MUX 0 4 read-write RFPT_RATE 5 6 read-write ADPLL_SDMOD_CTRL_REG 0x28 32 read-write n 0x0 0x0 SDMMODERX 0 3 read-write SDMMODETX 3 6 read-write ADPLL_TUNESTATE_RD_REG 0x8C 32 read-write n 0x0 0x0 TMRVAL 4 14 read-only TUNE_STATE 0 4 read-only ADPLL_TXMOD_CTRL_REG 0x24 32 read-write n 0x0 0x0 BT_SEL 0 1 read-write EO_PACKET_DIS 4 5 read-write INV_CKMODEXT 8 9 read-write MOD_INDEX 2 4 read-write TX_DATA_INV 1 2 read-write TX_MODE 6 8 read-write ANAMISC ANAMISC registers Peripheral_Registers 0x0 0x0 0x8 registers n CLK_REF_CNT_REG Count value for oscillator calibration 0x2 16 read-write n 0x0 0x0 REF_CNT_VAL Indicates the calibration time, with a decrement counter to 1. 0 16 read-write CLK_REF_SEL_REG Select clock for oscillator calibration 0x0 16 read-write n 0x0 0x0 EXT_CNT_EN_SEL 0 : Enable XTAL_CNT counter by the REF_CLK selected by REF_CLK_SEL. 1 : Enable XTAL_CNT counter from an external input. 3 4 read-write REF_CAL_START Writing a '1' starts a calibration of the clock selected by CLK_REF_SEL_REG[REF_CLK_SEL]. This bit is cleared when calibration is finished, and CLK_REF_VAL is ready. 2 3 read-write REF_CLK_SEL Select clock input for calibration: 0x0 : RC32K 0x1 : RC32M 0x2 : XTAL32K 0x3 : RCX 0 2 read-write CLK_REF_VAL_H_REG XTAL32M reference cycles, higher 16 bits 0x6 16 read-write n 0x0 0x0 XTAL_CNT_VAL Returns the number of DIVN clock cycles counted during the calibration time, defined with REF_CNT_VAL 0 16 read-only CLK_REF_VAL_L_REG XTAL32M reference cycles, lower 16 bits 0x4 16 read-write n 0x0 0x0 XTAL_CNT_VAL Returns the number of DIVN clock cycles counted during the calibration time, defined with REF_CNT_VAL 0 16 read-only BLE BLE registers Peripheral_Registers 0x0 0x0 0x214 registers n ACTSCANSTAT_REG Active scan register 0xA4 32 read-write n 0x0 0x0 BACKOFF Active scan mode back-off counter initialization value. 16 25 read-only UPPERLIMIT Active scan mode upper limit counter value. 0 9 read-only ADVCHMAP_REG Advertising Channel Map 0x90 32 read-write n 0x0 0x0 ADVCHMAP Advertising Channel Map, defined as per the advertising connection settings. Contains advertising channels index 37 to 39. If ADVCHMAP[i] equals: 0: Do not use data channel i+37. 1: Use data channel i+37. 0 3 read-write ADVTIM_REG Advertising Packet Interval 0xA0 32 read-write n 0x0 0x0 ADVINT Advertising Packet Interval defines the time interval in between two ADV_xxx packet sent. Value is in us. Value to program depends on the used Advertising Packet type and the device filtering policy. 0 14 read-write AESCNTL_REG Start AES register 0xC0 32 read-write n 0x0 0x0 AES_MODE 0: Cipher mode 1: Decipher mode 1 2 read-write AES_START Writing a 1 starts AES-128 ciphering/deciphering process. This bit is reset once the process is finished (i.e. ble_crypt_irq interrupt occurs, even masked) 0 1 write-only AESKEY127_96_REG AES encryption key 0xD0 32 read-write n 0x0 0x0 AESKEY127_96 AES encryption 128-bit key. Bit 127 down to 96 0 32 read-write AESKEY31_0_REG AES encryption key 0xC4 32 read-write n 0x0 0x0 AESKEY31_0 AES encryption 128-bit key. Bit 31 down to 0 0 32 read-write AESKEY63_32_REG AES encryption key 0xC8 32 read-write n 0x0 0x0 AESKEY63_32 AES encryption 128-bit key. Bit 63 down to 32 0 32 read-write AESKEY95_64_REG AES encryption key 0xCC 32 read-write n 0x0 0x0 AESKEY95_64 AES encryption 128-bit key. Bit 95 down to 64 0 32 read-write AESPTR_REG Pointer to the block to encrypt/decrypt 0xD4 32 read-write n 0x0 0x0 AESPTR Pointer to the memory zone where the block to cipher/decipher using AES-128 is stored. 0 16 read-write BASETIMECNTCORR_REG Base Time Counter 0x44 32 read-write n 0x0 0x0 BASETIMECNTCORR Base Time Counter correction value. 0 27 read-write BASETIMECNT_REG Base time reference counter 0x1C 32 read-write n 0x0 0x0 BASETIMECNT Value of the 625us base time reference counter. Updated each time SAMPCLK is written. Used by the SW in order to synchronize with the HW 0 27 read-only BDADDRL_REG BLE device address LSB register 0x24 32 read-write n 0x0 0x0 BDADDRL Bluetooth Low Energy Device Address. LSB part. 0 32 read-write BDADDRU_REG BLE device address MSB register 0x28 32 read-write n 0x0 0x0 BDADDRU Bluetooth Low Energy Device Address. MSB part. 0 16 read-write PRIV_NPUB Bluetooth Low Energy Device Address privacy indicator 0: Public Bluetooth Device Address 1: Private Bluetooth Device Address 16 17 read-write BLEMPRIO0_REG Coexistence interface Priority 0 Register 0x108 32 read-write n 0x0 0x0 BLEM0 Set Priority value for Initiating (Connection Request Response) BLE message 0 4 read-write BLEM1 Set Priority value for LLCP BLE message 4 8 read-write BLEM2 Set Priority value for Data Channel transmission BLE message 8 12 read-write BLEM3 Set Priority value for Initiating (Scanning) BLE message 12 16 read-write BLEM4 Set Priority value for Active Scanning BLE message 16 20 read-write BLEM5 Set Priority value for Connectable Advertising BLE message 20 24 read-write BLEM6 Set Priority value for Non-Connectable Advertising 24 28 read-write BLEM7 Set Priority value for Passive Scanning 28 32 read-write BLEMPRIO1_REG Coexistence interface Priority 1 Register 0x10C 32 read-write n 0x0 0x0 BLEMDEFAULT Set default priority value for other BLE message than those defined above 28 32 read-write CNTL2_REG BLE Control Register 2 0x200 32 read-write n 0x0 0x0 BB_ONLY Keep to 0. 18 19 read-write BLE_ARP_ERR_MSK_N When cleared to 0 then it masks the BLE_ARP_ERR_STAT in order to not trigger a BLE_ERROR_IRQ. 23 24 read-write BLE_ARP_PHY_ERR_STAT When set to 1 then an error occured in BLE ARP sub-block and the BLE_GEN_IRQ will be aserted. It will be set if the ARP_ERROR or PHY_ERROR will be asserted and if the BLE_ARP_ERR_MSK is set to 1 . Writing the value 1 will acknowledge and clear this field. 22 23 read-write BLE_CLK_SEL BLE Clock Select. Specifies the BLE master clock absolute frequency in MHz. Typical values are 16 and 8. Value depends on the selected XTAL frequency and the value of CLK_RADIO_REG[BLE_DIV] bitfield. For example, if XTAL oscillates at 16MHz and CLK_RADIO_REG[BLE_DIV] = 1 (divide by 2), then BLE master clock frequency is 8MHz and BLE_CLK_SEL should be set to value 8. The selected BLE master clock frequency (affected by BLE_DIV and BLE_CLK_SEL) must be modified and set only during the initialization time, i.e. before setting BLE_RWBLECNTL_REG[RWBLE_EN] to 1. Refer also to BLE_RWBLECONF_REG[CLK_SEL]. 9 15 read-write BLE_CLK_STAT 0: BLE uses low power clock 1: BLE uses master clock 6 7 read-only BLE_DIAG_OVR 1: Overrule BLE_DIAG. 0: BLE_DIAG is not overruled. 3 4 read-write BLE_PHY_ERR_MSK_N 24 25 read-write BLE_PTI_SOURCE_SEL 0: Provide to COEX block the PTI value indicated by the Control Structure. Recommended value is 0 . 1: Provide to COEX block the PTI value generated dynamically by the BLE core, which is based on the PTI of the Control Structure. 17 18 read-write BLE_RSSI_SEL 0: Select Peak-hold RSSI value (default). 1: Select current Average RSSI value. 21 22 read-write EMACCERRACK Exchange Memory Access Error Acknowledge. When the SW writes a 1 to this bit then the EMACCERRSTAT bit will be cleared. When the SW writes 0 it will have no affect. The read value is always 0 . 1 2 write-only EMACCERRMSK Exchange Memory Access Error Mask: When cleared to 0 the EM_ACC_ERR will not cause an BLE_ERROR_IRQ interrupt. When set to 1 an BLE_ERROR_IRQ will be generated as long as EM_ACC_ERR is 1 . 2 3 read-write EMACCERRSTAT Exchange Memory Access Error Status: The bit is read-only and can be cleared only by writing a 1 at EMACCERRACK bitfield. This bit will be set to 1 by the hardware when the controller will access an EM page that is not mapped according to the EM_MAPPING value. When this bit is 1 then the BLE_ERROR_IRQ will be asserted as long as EMACCERRMSK is 1 . 0 1 read-only MON_LP_CLK The SW can only write a 0 to this bit. Whenever a positive edge of the low power clock used by the BLE Timers is detected, then the HW will automatically set this bit to 1 . This functionality will not work if BLE Timer is in reset state (refer to CLK_RADIO_REG[BLE_LP_RESET]). This bit can be used for SW synchronization, to debug the low power clock, etc. 7 8 read-only RADIO_PWRDN_ALLOW This active high signal indicates when it is allowed for the BLE core (embedded in the Radio sub-System power domain) to be powered down. After the assertion of the BLE_DEEPSLCNTL_REG[DEEP_SLEEP_ON] a hardware sequence based on the Low Power clock will cause the assertion of RADIO_PWRDN_ALLOW. The RADIO_PWRDN_ALLOW will be cleared to 0 when the BLE core exits from the sleep state, i.e. when the BLE_SLP_IRQ will be asserted. 8 9 read-only SW_RPL_SPI Keep to 0. 19 20 read-write WAKEUPLPSTAT The status of the BLE_WAKEUP_LP_IRQ. The Interrupt Service Routine of BLE_WAKEUP_LP_IRQ should return only when the WAKEUPLPSTAT is cleared. Note that BLE_WAKEUP_LP_IRQ is automatically acknowledged after the power up of the Radio Subsystem, plus one Low Power Clock period. 20 21 read-only COEXIFCNTL0_REG Coexistence interface Control 0 Register 0x100 32 read-write n 0x0 0x0 COEX_EN Enable / Disable control of the MWS/WLAN Coexistence control 0: Coexistence interface disabled 1: Coexistence interface enabled 0 1 read-write SYNCGEN_EN Determines whether ble_sync is generated or not. 0: ble_sync pulse not generated 1: ble_sync pulse generated 1 2 read-write WLANRXMSK Determines how wlan_rx impact BLE Tx and Rx 00: wlan_rx has no impact 01: wlan_rx can stop BLE Tx, no impact on BLE Rx (default mode) 10: wlan_rx can stop BLE Rx, no impact on BLE Tx 11: wlan_rx can stop both BLE Tx and BLE Rx 4 6 read-write WLANTXMSK Determines how wlan_tx impact BLE Tx and Rx 00: wlan_tx has no impact (default mode) 01: wlan_tx can stop BLE Tx, no impact on BLE Rx 10: wlan_tx can stop BLE Rx, no impact on BLE Tx 11: wlan_tx can stop both BLE Tx and BLE Rx 6 8 read-write WLCRXPRIOMODE Defines Bluetooth Low Energy packet ble_rx mode behavior. 00: Rx indication excluding Rx Power up delay (starts when correlator is enabled) 01: Rx indication including Rx Power up delay 10: Rx High priority indicator 11: n/a 20 22 read-write WLCTXPRIOMODE Defines Bluetooth Low Energy packet ble_tx mode behavior 00: Tx indication excluding Tx Power up delay 01: Tx indication including Tx Power up delay 10: Tx High priority indicator 11: n/a 16 18 read-write COEXIFCNTL1_REG Coexistence interface Control 1 Register 0x104 32 read-write n 0x0 0x0 WLCPDELAY Applies on ble_tx if WLCTXPRIOMODE equals 10. Applies on ble_rx if WLCRXPRIOMODE equals 10. Determines the delay (in us) in Tx/Rx enables rises the time Bluetooth Low energy Tx/Rx priority has to be provided . 0 7 read-write WLCPDURATION Applies on ble_tx if WLCTXPRIOMODE equals 10 Applies on ble_rx if WLCRXPRIOMODE equals 10 Determines how many s the priority information must be maintained Note that if WLCPDURATION = 0x00, then Tx/Rx priority levels are maintained till Tx/Rx EN are de-asserted. 8 15 read-write WLCPRXTHR Applies on ble_rx if WLCRXPRIOMODE equals 10 Determines the threshold for Rx priority setting. If ble_pti[3:0] output value is greater than WLCPRXTHR, then Rx Bluetooth Low Energy priority is considered as high, and must be provided to the WLAN coexistence interface 24 29 read-write WLCPTXTHR Applies on ble_tx if WLCTXPRIOMODE equals 10 Determines the threshold for priority setting. If ble_pti[3:0] output value is greater than WLCPTXTHR, then Tx Bluetooth Low Energy priority is considered as high, and must be provided to the WLAN coexistence interface 16 21 read-write CURRENTRXDESCPTR_REG Rx Descriptor Pointer for the Receive Buffer Chained List 0x2C 32 read-write n 0x0 0x0 CURRENTRXDESCPTR Rx Descriptor Pointer that determines the starting point of the Receive Buffer Chained List 0 15 read-write ETPTR Exchange Table Pointer that determines the starting point of the Exchange Table 16 32 read-write DEBUGADDMAX_REG Upper limit for the memory zone 0x58 32 read-write n 0x0 0x0 EM_ADDMAX Upper limit for the Exchange Memory zone indicated by the em_inzone flag 0 16 read-write REG_ADDMAX Upper limit for the Register zone indicated by the reg_inzone flag 16 32 read-write DEBUGADDMIN_REG Lower limit for the memory zone 0x5C 32 read-write n 0x0 0x0 EM_ADDMIN Lower limit for the Exchange Memory zone indicated by the em_inzone flag 0 16 read-write REG_ADDMIN Lower limit for the Register zone indicated by the reg_inzone flag 16 32 read-write DEEPSLCNTL_REG Deep-Sleep control register 0x30 32 read-write n 0x0 0x0 DEEP_SLEEP_CORR_EN 625us base time reference integer and fractional part correction. Applies when system has been woken-up from Deep Sleep Mode. It enables Fine Counter and Base Time counter when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 3 4 write-only DEEP_SLEEP_IRQ_EN Always set to 3 when DEEP_SLEEP_ON is set to 1 . It controls the generation of BLE_WAKEUP_LP_IRQ. 0 2 read-write DEEP_SLEEP_ON 0: RW-BLE Core in normal active mode 1: Request RW-BLE Core to switch in deep sleep mode. This bit is reset on DEEP_SLEEP_STAT falling edge. 2 3 write-only DEEP_SLEEP_STAT Indicator of current Deep Sleep clock mux status: 0: RW-BLE Core is not yet in Deep Sleep Mode 1: RW-BLE Core is in Deep Sleep Mode (only low_power_clk is running) 15 16 read-only EXTWKUPDSB External Wake-Up disable 0: RW-BLE Core can be woken by external wake-up 1: RW-BLE Core cannot be woken up by external wake-up 31 32 read-write SOFT_WAKEUP_REQ Wake Up Request from RW-BLE Software. Applies when system is in Deep Sleep Mode. It wakes up the RW-BLE Core when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 4 5 read-write DEEPSLSTAT_REG Duration of the last deep sleep phase register 0x38 32 read-write n 0x0 0x0 DEEPSLDUR Actual duration of the last deep sleep phase measured in low_power_clk clock cycle. DEEPSLDUR is set to zero at the beginning of the deep sleep phase, and is incremented at each low_power_clk clock cycle until the end of the deep sleep phase. 0 32 read-only DEEPSLWKUP_REG Time (measured in Low Power clock cycles) in Deep Sleep Mode before waking-up the device 0x34 32 read-write n 0x0 0x0 DEEPSLTIME Determines the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device. This ensures a maximum of 37 hours and 16mn sleep mode capabilities at 32kHz. This ensures a maximum of 36 hours and 16mn sleep mode capabilities at 32.768kHz 0 32 read-write DIAGCNTL2_REG Debug use only 0x20C 32 read-write n 0x0 0x0 DIAG4 Only relevant when DIAG4_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG4. 0 6 read-write DIAG4_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 7 8 read-write DIAG5 Only relevant when DIAG5_EN= 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG5. 8 14 read-write DIAG5_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 15 16 read-write DIAG6 Only relevant when DIAG6_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG6. 16 22 read-write DIAG6_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 23 24 read-write DIAG7 Only relevant when DIAG7_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG7. 24 30 read-write DIAG7_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 31 32 read-write DIAGCNTL3_REG Debug use only 0x210 32 read-write n 0x0 0x0 DIAG0_BIT Selects which bit from the DIAG0 word will be forwarded to bit 0 of the BLE DIagnostic Port. 0 3 read-write DIAG0_INV If set, then the specific diagnostic bit will be inverted. 3 4 read-write DIAG1_BIT Selects which bit from the DIAG1 word will be forwarded to bit 1 of the BLE DIagnostic Port. 4 7 read-write DIAG1_INV If set, then the specific diagnostic bit will be inverted. 7 8 read-write DIAG2_BIT Selects which bit from the DIAG2 word will be forwarded to bit 2 of the BLE DIagnostic Port. 8 11 read-write DIAG2_INV If set, then the specific diagnostic bit will be inverted. 11 12 read-write DIAG3_BIT Selects which bit from the DIAG3 word will be forwarded to bit 3 of the BLE DIagnostic Port. 12 15 read-write DIAG3_INV If set, then the specific diagnostic bit will be inverted. 15 16 read-write DIAG4_BIT Selects which bit from the DIAG4 word will be forwarded to bit 4 of the BLE DIagnostic Port. 16 19 read-write DIAG4_INV If set, then the specific diagnostic bit will be inverted. 19 20 read-write DIAG5_BIT Selects which bit from the DIAG5 word will be forwarded to bit 5 of the BLE DIagnostic Port. 20 23 read-write DIAG5_INV If set, then the specific diagnostic bit will be inverted. 23 24 read-write DIAG6_BIT Selects which bit from the DIAG6 word will be forwarded to bit 6 of the BLE DIagnostic Port. 24 27 read-write DIAG6_INV If set, then the specific diagnostic bit will be inverted. 27 28 read-write DIAG7_BIT Selects which bit from the DIAG7 word will be forwarded to bit 7 of the BLE DIagnostic Port. 28 31 read-write DIAG7_INV If set, then the specific diagnostic bit will be inverted. 31 32 read-write DIAGCNTL_REG Diagnostics Register 0x50 32 read-write n 0x0 0x0 DIAG0 Only relevant when DIAG0_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG0. 0 6 read-write DIAG0_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 7 8 read-write DIAG1 Only relevant when DIAG1_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG1. 8 14 read-write DIAG1_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 15 16 read-write DIAG2 Only relevant when DIAG2_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG2. 16 22 read-write DIAG2_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 23 24 read-write DIAG3 Only relevant when DIAG3_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG3. 24 30 read-write DIAG3_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 31 32 read-write DIAGSTAT_REG Debug use only 0x54 32 read-write n 0x0 0x0 DIAG0STAT Directly connected to ble_dbg0[7:0] output. Debug use only. 0 8 read-only DIAG1STAT Directly connected to ble_dbg1[7:0] output. Debug use only. 8 16 read-only DIAG2STAT Directly connected to ble_dbg2[7:0] output. Debug use only. 16 24 read-only DIAG3STAT Directly connected to ble_dbg3[7:0] output. Debug use only. 24 32 read-only EM_BASE_REG Exchange Memory Base Register 0x208 32 read-write n 0x0 0x0 BLE_EM_BASE_16_10 The physical address on the system memory map of the base of the Exchange Memory. 10 17 read-write ENBPRESET_REG Time in low power oscillator cycles register 0x3C 32 read-write n 0x0 0x0 TWEXT Minimum and recommended value is TWIRQ_RESET + 1 . In the case of wake-up due to an external wake-up request, TWEXT specifies the time delay in low power oscillator cycles to deassert BLE_WAKEUP_LP_IRQ. Refer also to GP_CONTROL_REG[BLE_WAKEUP_REQ]. Range is [0...64 ms] for 32kHz [0...62.5 ms] for 32.768kHz 21 32 read-write TWIRQ_RESET Recommended value is 1. Time in low power oscillator cycles to reset BLE_WAKEUP_LP_IRQ before the BLE sleep timer expiration. Refer also to BLE_DEEPSLWKUP_REG[DEEPSLTIME]. Range is [0...32 ms] for 32kHz [0...31.25 ms] for 32.768kHz. 0 10 read-write TWIRQ_SET Minimum value is TWIRQ_RESET + 1 . Time in low power oscillator cycles to set BLE_WAKEUP_LP_IRQ before the BLE sleep timer expiration. Refer also to BLE_DEEPSLWKUP_REG[DEEPSLTIME]. Range is [0...64 ms] for 32kHz [0...62.5 ms] for 32.768kHz 10 21 read-write ERRORTYPESTAT_REG Error Type Status registers 0x60 32 read-write n 0x0 0x0 ADV_UNDERRUN Indicates Advertising Interval Under run, occurs if time between two consecutive Advertising packet (in Advertising mode) is lower than the expected value. 0: No error 1: Error occurred 10 11 read-only CONCEVTIRQ_ERROR Indicates whether two consecutive and concurrent ble_event_irq have been generated, and not acknowledged in time by the RW-BLE Software. 0: No error 1: Error occurred 17 18 read-only CSFORMAT_ERROR Indicates whether CS-FORMAT has been programmed with an invalid value: this is a major software programming failure. 0: No error 1: Error occurred 12 13 read-only EVT_CNTL_APFM_ERROR Indicates Anticipated Pre-Fetch Mechanism error: happens when 2 consecutive events are programmed, and when the first event is not completely finished while second pre-fetch instant is reached. 0: No error 1: Error occured 7 8 read-only EVT_SCHDL_APFM_ERROR Indicates Anticipated Pre-Fetch Mechanism error: happens when 2 consecutive events are programmed, and when the first event is not completely finished while second pre-fetch instant is reached. 0: No error 1: Error occured 6 7 read-only EVT_SCHDL_EMACC_ERROR Indicates Event Scheduler Exchange Memory access error, happens when Exchange Memory accesses are not served in time, and blocks the Exchange Table entry read 0: No error 1: Error occurred 4 5 read-only EVT_SCHDL_ENTRY_ERROR Indicates Event Scheduler faced Invalid timing programing on two consecutive ET entries (e.g first one with 624s offset and second one with no offset) 0: No error 1: Error occurred 5 6 read-only IFS_UNDERRUN Indicates Inter Frame Space Under run, occurs if IFS time is not enough to update and read Control Structure/Descriptors, and/or White List parsing is not finished and/or Decryption time is too long to be finished on time 0: No error 1: Error occurred 9 10 read-only LLCHMAP_ERROR Indicates Link Layer Channel Map error, happens when actual number of CS-LLCHMAP bit set to one is different from CS-NBCHGOOD at the beginning of Frequency Hopping process 0: No error 1: Error occurred 11 12 read-only PKTCNTL_EMACC_ERROR Indicates Packet Controller Exchange Memory access error, happens when Exchange Memory accesses are not served in time and Tx/Rx data are corrupted 0: No error 1: Error occurred 2 3 read-only RADIO_EMACC_ERROR Indicates Radio Controller Exchange Memory access error, happens when Exchange Memory accesses are not served in time and data are corrupted. 0: No error 1: Error occurred 3 4 read-only RXCRYPT_ERROR Indicates real time decryption error, happens when AES-CCM decryption is too slow compared to Packet Controller requests. A 16-bytes block has to be decrypted prior the next block is received by the Packet Controller 0: No error 1: Error occurred 1 2 read-only RXDATA_PTR_ERROR Indicates whether Rx data buffer pointer value programmed is null: this is a major programming failure. 0: No error 1: Error occurred 16 17 read-only RXDESC_EMPTY_ERROR Indicates whether Rx Descriptor pointer value programmed in register is null: this is a major programming failure. 0: No error 1: Error occurred 14 15 read-only TXCRYPT_ERROR Indicates Real Time encryption error, happens when AES-CCM encryption is too slow compared to Packet Controller requests. A 16-bytes block has to be encrypted and prepared on Packet Controller request, and needs to be ready before the Packet Controller has to send ti 0: No error 1: Error occurred 0 1 read-only TXDATA_PTR_ERROR Indicates whether Tx data buffer pointer value programmed is null during Advertising / Scanning / Initiating events, or during Master / Slave connections with non-null packet length: this is a major programming failure. 0: No error 1: Error occurred 15 16 read-only TXDESC_EMPTY_ERROR Indicates whether Tx Descriptor pointer value programmed in Control Structure is null during Advertising / Scanning / Initiating events: this is a major programming failure. 0: No error 1: Error occurred 13 14 read-only WHITELIST_ERROR Indicates White List Timeout error, occurs if White List parsing is not finished on time 0: No error 1: Error occurred 8 9 read-only FINECNTCORR_REG Phase correction value register 0x40 32 read-write n 0x0 0x0 FINECNTCORR Phase correction value for the 625us reference counter (i.e. Fine Counter) in us. 0 10 read-write FINETIMECNT_REG Fine time reference counter 0x20 32 read-write n 0x0 0x0 FINECNT Value of the current s fine time reference counter. Updated each time SAMPCLK is written. Used by the SW in order to synchronize with the HW, and obtain a more precise sleep duration 0 10 read-only FINETIMTGT_REG Fine Timer Target value 0xF8 32 read-write n 0x0 0x0 FINETARGET Fine Timer Target value on which a ble_finetgtim_irq must be generated. This timer has a precision of 625us: interrupt is generated only when FINETARGET = BASETIMECNT 0 27 read-write GROSSTIMTGT_REG Gross Timer Target value 0xF4 32 read-write n 0x0 0x0 GROSSTARGET Gross Timer Target value on which a ble_grosstgtim_irq must be generated. This timer has a precision of 10ms: interrupt is generated only when GROSSTARGET[22:0] = BASETIMECNT[26:4] and BASETIMECNT[3:0] = 0. 0 23 read-write INTACK_REG Interrupt acknowledge register 0x18 32 read-write n 0x0 0x0 CRYPTINTACK Encryption engine interrupt acknowledgement bit Software writing 1 acknowledges the Encryption engine interrupt. This bit resets CRYPTINTSTAT and CRYPTINTRAWSTAT flags. Resets at 0 when action is performed 4 5 write-only CSCNTINTACK 625us base time reference interrupt acknowledgment bit Software writing 1 acknowledges the CLKN interrupt. This bit resets CLKINTSTAT and CLKINTRAWSTAT flags. Resets at 0 when action is performed 0 1 write-only ERRORINTACK Error interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt. This bit resets ERRORINTSTAT and ERRORINTRAWSTAT flags. Resets at 0 when action is performed 5 6 write-only EVENTAPFAINTACK End of event / Anticipated Pre-Fetch Abort interrupt acknowledgement bit Software writing 1 acknowledges the End of event / Anticipated Pre-Fetch Abort interrupt. This bit resets EVENTAPFAINTSTAT and EVENTAPFAINTRAWSTAT flags. Resets at 0 when action is performed 8 9 write-only EVENTINTACK End of Event interrupt acknowledgment bit Software writing 1 acknowledges the End of Advertising / Scanning / Connection interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags. Resets at 0 when action is performed 3 4 write-only FINETGTIMINTACK Fine Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Fine Timer interrupt. This bit resets FINETGTIMINTSTAT and FINETGTIMINTRAWSTAT flags. Resets at 0 when action is performed 7 8 write-only GROSSTGTIMINTACK Gross Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Gross Timer interrupt. This bit resets GROSSTGTIMINTSTAT and GROSSTGTIMINTRAWSTAT flags. Resets at 0 when action is performed 6 7 write-only RXINTACK Packet Reception interrupt acknowledgment bit Software writing 1 acknowledges the Rx interrupt. This bit resets RXINTSTAT and RXINTRAWSTAT flags. Resets at 0 when action is performed 1 2 write-only SLPINTACK End of Deep Sleep interrupt acknowledgment bit Software writing 1 acknowledges the End of Sleep Mode interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags. Resets at 0 when action is performed 2 3 write-only SWINTACK SW triggered interrupt acknowledgement bit Software writing 1 acknowledges the SW triggered interrupt. This bit resets SWINTSTAT and SWINTRAWSTAT flags. Resets at 0 when action is performed 9 10 write-only INTCNTL_REG Interrupt controller register 0xC 32 read-write n 0x0 0x0 CRYPTINTMSK Encryption engine Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 4 5 read-write CSCNTDEVMSK CSCNT interrupt mask during event. This bit allows to enable CSCNT interrupt generation during events (i.e. advertising, scanning, initiating, and connection) 0: CSCNT Interrupt not generated during events. 1: CSCNT Interrupt generated during events. 15 16 read-write CSCNTINTMSK 625us Base Time Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 0 1 read-write ERRORINTMSK Error Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 5 6 read-write EVENTAPFAINTMSK End of event / anticipated pre-fetch abort interrupt Mask 0: Interrupt not generated 1: Interrupt generated 8 9 read-write EVENTINTMSK End of event Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 3 4 read-write FINETGTIMINTMSK Fine Target Timer Mask 0: Interrupt not generated 1: Interrupt generated 7 8 read-write GROSSTGTIMINTMSK Gross Target Timer Mask 0: Interrupt not generated 1: Interrupt generated 6 7 read-write RXINTMSK Rx Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 1 2 read-write SLPINTMSK Sleep Mode Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 2 3 read-write SWINTMSK SW triggered interrupt Mask 0: Interrupt not generated 1: Interrupt generated 9 10 read-write INTRAWSTAT_REG Interrupt raw status register 0x14 32 read-write n 0x0 0x0 CRYPTINTRAWSTAT Encryption engine interrupt raw status 0: No Encryption / Decryption interrupt. 1: An Encryption / Decryption interrupt is pending. 4 5 read-only CSCNTINTRAWSTAT 625us base time reference interrupt raw status 0: No 625us Base Time interrupt. 1: A 625us Base Time interrupt is pending. 0 1 read-only ERRORINTRAWSTAT Error interrupt raw status 0: No Error interrupt. 1: An Error interrupt is pending. 5 6 read-only EVENTAPFAINTRAWSTAT End of event / Anticipated Pre-Fetch Abort interrupt raw status 0: No End of Event interrupt. 1: An End of Event interrupt is pending. 8 9 read-only EVENTINTRAWSTAT End of Event interrupt raw status 0: No End of Advertising / Scanning / Connection interrupt. 1: An End of Advertising / Scanning / Connection interrupt is pending. 3 4 read-only FINETGTIMINTRAWSTAT Fine Target Timer Error interrupt raw status 0: No Fine Target Timer interrupt. 1: A Fine Target Timer interrupt is pending. 7 8 read-only GROSSTGTIMINTRAWSTAT Gross Target Timer interrupt raw status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending. 6 7 read-only RXINTRAWSTAT Packet Reception interrupt raw status 0: No Rx interrupt. 1: An Rx interrupt is pending. 1 2 read-only SLPINTRAWSTAT Sleep interrupt raw status 0: No End of Sleep Mode interrupt. 1: An End of Sleep Mode interrupt is pending. 2 3 read-only SWINTRAWSTAT SW triggered interrupt raw status 0: No SW triggered interrupt. 1: A SW triggered interrupt is pending. 9 10 read-only INTSTAT_REG Interrupt status register 0x10 32 read-write n 0x0 0x0 CRYPTINTSTAT Masked Encryption engine interrupt status 0: No Encryption / Decryption interrupt. 1: An Encryption / Decryption interrupt is pending. 4 5 read-only CSCNTINTSTAT Masked 625us base time reference interrupt status 0: No 625us Base Time interrupt. 1: A 625us Base Time interrupt is pending. 0 1 read-only ERRORINTSTAT Masked Error interrupt status 0: No Error interrupt. 1: An Error interrupt is pending. 5 6 read-only EVENTAPFAINTSTAT End of event / Anticipated Pre-Fetch Abort interrupt status 0: No End of Event interrupt. 1: An End of Event interrupt is pending. 8 9 read-only EVENTINTSTAT Masked End of Event interrupt status 0: No End of Advertising / Scanning / Connection interrupt. 1: An End of Advertising / Scanning / Connection interrupt is pending. 3 4 read-only FINETGTIMINTSTAT Masked Fine Target Timer Error interrupt status 0: No Fine Target Timer interrupt. 1: A Fine Target Timer interrupt is pending. 7 8 read-only GROSSTGTIMINTSTAT Masked Gross Target Timer interrupt status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending. 6 7 read-only RXINTSTAT Masked Packet Reception interrupt status 0: No Rx interrupt. 1: An Rx interrupt is pending. 1 2 read-only SLPINTSTAT Masked Sleep interrupt status 0: No End of Sleep Mode interrupt. 1: An End of Sleep Mode interrupt is pending. 2 3 read-only SWINTSTAT SW triggered interrupt status 0: No SW triggered interrupt. 1: A SW triggered interrupt is pending 9 10 read-only RADIOCNTL0_REG Radio interface control register 0x70 32 read-write n 0x0 0x0 RADIOCNTL1_REG Radio interface control register 0x74 32 read-write n 0x0 0x0 XRFSEL Extended radio selection field, Must be set to 2 . 16 21 read-write RADIOCNTL2_REG Radio interface control register 0x78 32 read-write n 0x0 0x0 RADIOCNTL3_REG Radio interface control register 0x7C 32 read-write n 0x0 0x0 RADIOPWRUPDN_REG RX/TX power up/down phase register 0x80 32 read-write n 0x0 0x0 RTRIP_DELAY Defines round trip delay value. This value correspond to the addition of data latency in Tx and data latency in Rx. Value is in us 24 31 read-write RXPWRUP This register holds the length in s of the RX power up phase for the current radio device. Default value is 210us (reset value). Operating range depends on the selected radio. 16 24 read-write TXPWRDN This register extends the length in s of the TX power down phase for the current radio device. Default value is 3us (reset value). Operating range depends on the selected radio. 8 12 read-write TXPWRUP This register holds the length in s of the TX power up phase for the current radio device. Default value is 210us (reset value). Operating range depends on the selected radio. 0 8 read-write RFTESTCNTL_REG RF Testing Register 0xE0 32 read-write n 0x0 0x0 INFINITERX Applicable in RF Test Mode only 0: Normal mode of operation 1: Infinite Rx window 31 32 read-write INFINITETX Applicable in RF Test Mode only 0: Normal mode of operation. 1: Infinite Tx packet / Normal start of a packet but endless payload 15 16 read-write PRBSTYPE Applicable only in Tx/Rx RF Test mode 0: Tx Packet Payload are PRBS9 type 1: Tx Packet Payload are PRBS15 type 13 14 read-write RXPKTCNTEN Applicable in RF Test Mode only 0: Rx packet count disabled 1: Rx packet count enabled, and reported in CS-RXCCMPKTCNT and RFTESTRXSTAT-RXPKTCNT on RF abort command 27 28 read-write TXLENGTH Applicable only for Tx/Rx RF Test mode, and valid when RFTESTCNTL-TXLENGTHSRC = 1 Tx packet length in number of byte 0 9 read-write TXLENGTHSRC Applicable only in Tx/Rx RF Test mode 0: Normal mode of operation: TxDESC-TXADVLEN controls the Tx packet payload size 1: Uses RFTESTCNTL-TXLENGTH packet length (can support up to 512 bytes transmit) 14 15 read-write TXPKTCNTEN Applicable in RF Test Mode only 0: Tx packet count disabled 1: Tx packet count enabled, and reported in CS-TXCCMPKTCNT and RFTESTTXSTAT-TXPKTCNT on RF abort command 11 12 read-write TXPLDSRC Applicable only in Tx/Rx RF Test mode 0: Tx Packet Payload source is the Control Structure 1: Tx Packet Payload are PRBS generator 12 13 read-write RFTESTRXSTAT_REG RF Testing Register 0xE8 32 read-write n 0x0 0x0 RXPKTCNT Reports number of correctly received packet during Test Modes (no sync error, no CRC error). Value is valid if RFTESTCNTL-RXPKTCNTEN is set 0 32 read-only RFTESTTXSTAT_REG RF Testing Register 0xE4 32 read-write n 0x0 0x0 TXPKTCNT Reports number of transmitted packet during Test Modes. Value is valid if RFTESTCNTL-TXPKTCNTEN is set 0 32 read-only RWBLECNTL_REG BLE Control register 0x0 32 read-write n 0x0 0x0 ADVERTFILT_EN Advertising Channels Error Filtering Enable control 0: RW-BLE Core reports all errors to RW-BLE Software 1: RW-BLE Core reports only correctly received packet, without error to RW-BLE Software 9 10 read-write ADVERT_ABORT Abort the current Advertising event when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 25 26 write-only CRC_DSB 0: Normal operation. CRC removed from data stream. 1: CRC stripping disabled on Rx packets, CRC replaced by 0x000 in Tx. 17 18 read-write CRYPT_DSB 0: Normal operation. Encryption / Decryption enabled. 1: Encryption / Decryption disabled. Note that if CS-CRYPT_EN is set, then MIC is generated, and only data encryption is disabled, meaning data sent are plain data. 19 20 read-write HOP_REMAP_DSB 0: Normal operation. Frequency Hopping Remapping algorithm enabled. 1: Frequency Hopping Remapping algorithm disabled 16 17 read-write MASTER_SOFT_RST Reset the complete BLE Core except registers and timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 31 32 write-only MASTER_TGSOFT_RST Reset the timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 30 31 write-only MD_DSB 0: Normal operation of MD bits management 1: Allow a single Tx/Rx exchange whatever the MD bits are. value forced by SW from Tx Descriptorvalue just saved in Rx Descriptor during reception 22 23 read-write NESN_DSB 0: Normal operation of Acknowledge 1: Acknowledge scheme disabled: value forced by SW from Tx Descriptorvalue ignored in Rx, where no NESN error reported. 20 21 read-write REG_SOFT_RST Reset the complete register block, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Note that INT STAT will not be cleared, so the user should also write to BLE_INTACK_REG after the SW Reset 29 30 read-write RFTEST_ABORT Abort the current RF Testing defined as per CS-FORMAT when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Note that when RFTEST_ABORT is requested: 1) In case of infinite Tx, the Packet Controller FSM stops at the end of the current byte in process, and processes accordingly the packet CRC. 2) In case of Infinite Rx, the Packet Controller FSM either stops as the end of the current Packet reception (if Access address has been detected), or simply stop the processing switching off the RF. 26 27 write-only RWBLE_EN 0: Disable RW-BLE Core Exchange Table pre-fetch mechanism. 1: Enable RW-BLE Core Exchange table pre-fetch mechanism. 8 9 read-write RXWINSZDEF Default Rx Window size in us. Used when device: is master connectedperforms its second receipt.0 is not a valid value. Recommended value is 10 (in decimal). 4 8 read-write SCAN_ABORT Abort the current scan window when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 24 25 write-only SN_DSB 0: Normal operation of Sequence number 1: Sequence Number Management disabled: value forced by SW from Tx Descriptorvalue ignored in Rx, where no SN error reported. 21 22 read-write SWINT_REQ Forces the generation of ble_sw_irq when written with a 1, and proper masking is set. Resets at 0 when action is performed. No action happens if it is written with 0. 28 29 write-only SYNCERR Indicates the maximum number of errors allowed to recognize the synchronization word. 0 3 read-write WHIT_DSB 0: Normal operation. Whitening enabled. 1: Whitening disabled. 18 19 read-write RWBLECONF_REG Configuration register 0x8 32 read-write n 0x0 0x0 ADD_WIDTH Value of the RW_BLE_ADDRESS_WIDTH parameter concerted into binary. 24 30 read-only BUSWIDTH Processor bus width: 1: 32 bits 0 1 read-only CLK_SEL Operating Frequency (in MHz) 8 14 read-only COEX 1: WLAN Coexistence mechanism present 3 4 read-only DECIPHER 0: AES deciphering not present 6 7 read-only DMMODE 0: RW-BLE Core is used as a standalone BLE device 5 6 read-only INTMODE 1: Interrupts are trigger level generated, i.e. stays active at 1 till acknowledgement 4 5 read-only RFIF Radio Interface ID 16 23 read-only USECRYPT 1: AES-CCM Encryption block present 1 2 read-only USEDBG 1: Diagnostic port instantiated 2 3 read-only RXMICVAL_REG AES / CCM plain MIC value 0xDC 32 read-write n 0x0 0x0 RXMICVAL AES-CCM plain MIC value. Valid on once MIC has been extracted from Rx packet. 0 32 read-only SAMPLECLK_REG Samples the Base Time Counter 0xFC 32 read-write n 0x0 0x0 SAMP Writing a 1 samples the Base Time Counter value in BASETIMECNT register. Resets at 0 when action is performed. 0 1 write-only SWPROFILING_REG Software Profiling register 0x64 32 read-write n 0x0 0x0 SWPROFVAL Software Profiling register: used by RW-BLE Software for profiling purpose: this value is copied on Diagnostic port 0 32 read-write TIMGENCNTL_REG Timing Generator Register 0xF0 32 read-write n 0x0 0x0 APFM_EN Controls the Anticipated pre-Fetch Abort mechanism 0: Disabled 1: Enabled 31 32 read-write PREFETCHABORT_TIME Defines the instant in s at which immediate abort is required after anticipated pre-fetch abort 16 26 read-write PREFETCH_TIME Defines Exchange Table pre-fetch instant in us 0 9 read-write TXMICVAL_REG AES / CCM plain MIC value 0xD8 32 read-write n 0x0 0x0 TXMICVAL AES-CCM plain MIC value. Valid on when MIC has been calculated (in Tx) 0 32 read-only VERSION_REG Version register 0x4 32 read-write n 0x0 0x0 BUILD BLE Core Build Build number. 0 8 read-only REL BLE Core version Major release number. 16 24 read-only TYP BLE Core Type 24 32 read-only UPG BLE Core upgrade Upgrade number. 8 16 read-only WLNBDEV_REG Devices in white list 0xB8 32 read-write n 0x0 0x0 NBPRIVDEV Number of private devices in the white list. 8 16 read-write NBPUBDEV Number of public devices in the white list. 0 8 read-write WLPRIVADDPTR_REG Start address of private devices list 0xB4 32 read-write n 0x0 0x0 WLPRIVADDPTR Start address pointer of the private devices white list. 0 16 read-write WLPUBADDPTR_REG Start address of public devices list 0xB0 32 read-write n 0x0 0x0 WLPUBADDPTR Start address pointer of the public devices white list. 0 16 read-write CHIP_VERSION CHIP_VERSION registers Peripheral_Registers 0x0 0x0 0xFE registers n CHIP_ID1_REG Chip identification register 1. 0x0 16 read-write n 0x0 0x0 CHIP_ID1 First character of device type 2632 in ASCII. 0 8 read-only CHIP_ID2_REG Chip identification register 2. 0x4 16 read-write n 0x0 0x0 CHIP_ID2 Second character of device type 2632 in ASCII. 0 8 read-only CHIP_ID3_REG Chip identification register 3. 0x8 16 read-write n 0x0 0x0 CHIP_ID3 Third character of device type 2632 in ASCII. 0 8 read-only CHIP_ID4_REG Chip identification register 4. 0xC 16 read-write n 0x0 0x0 CHIP_ID4 Fourth character of device type 2632 in ASCII. 0 8 read-only CHIP_REVISION_REG Chip revision register. 0x14 16 read-write n 0x0 0x0 CHIP_REVISION Chip version, corresponds with type number in ASCII. 0x41 = 'A', 0x42 = 'B' 0 8 read-only CHIP_SWC_REG Software compatibility register. 0x10 16 read-write n 0x0 0x0 CHIP_SWC SoftWare Compatibility code. Integer (default = 0) which is incremented if a silicon change has impact on the CPU Firmware. Can be used by software developers to write silicon revision dependent code. 0 4 read-only CHIP_TEST1_REG Chip test register 1. 0xF8 16 read-write n 0x0 0x0 CHIP_LAYOUT_REVISION Chip layout revision, corresponds with type number in ASCII. 0x41 = 'A', 0x42 = 'B' 0 8 read-only CHIP_TEST2_REG Chip test register 2. 0xFC 16 read-write n 0x0 0x0 CHIP_METAL_OPTION Chip metal option value. 0 4 read-only CRG_AON CRG_AON registers Peripheral_Registers 0x0 0x0 0x26 registers n 0x0 0x26 registers n GP_DATA_REG 0x24 16 read-write n 0x0 0x0 ANA_SPARE 5 8 read-write DISABLE_CLAMP_OVERRULE 4 5 read-write SW_GP_DATA 0 4 read-write HIBERN_CTRL_REG Hibernation control register 0x10 16 read-write n 0x0 0x0 HIBERNATION_ENABLE Enables the hibernation mode when sleeping 0: deep sleep mode, PD_SLP remains on 1: hibernation mode, PD_SLP goes off. REMAP_ADR0 needs to be set to the correct source to boot from before going to sleep. 0 1 read-write HIBERN_WKUP_MASK Selects which pin to wakeup from 2 7 read-write HIBERN_WKUP_POLARITY Selects the polarity of the wakeup source. The polarity must be chosen such that the ANA_STATUS_REG[CLKLESS_WAKEUP_STAT] is '1'. Any change on the selected GPIOs will make the CLKLESS_WAKEUP_STAT go to '0', and wakeup the system from hibernation. 1 2 read-write HWR_CTRL_REG Hardware Reset control register 0x0 16 read-write n 0x0 0x0 DISABLE_HWR Disables the RST functionality on P00 0 1 read-write PAD_LATCH_REG Control the state retention of the GPIO ports 0xC 16 read-write n 0x0 0x0 PAD_LATCH_EN Direct write to the pad_latch_enable signal 0 1 read-write POWER_AON_CTRL_REG 0x20 16 read-write n 0x0 0x0 BOOST_MODE_FORCE 0x:automatic selection of boost mode 11: force boost mode 10: force buck mode 7 9 read-write CHARGE_VBAT_DISABLE Do not charge vbat high in boost mode 6 7 read-write CMP_VCONT_SLP_DISABLE Disable vcont comparator in SLP 9 10 read-write FORCE_RUNNING_COMP_DIS 14 15 read-write LDO_RET_TRIM VDD clamp level setting for hibernation mode 10 14 read-write POR_VBAT_HIGH_RST_MASK Mask rst from por_vbat_high 3 4 read-write POR_VBAT_LOW_RST_MASK Mask rst from por_vbat_low 2 3 read-write RC32K_HIGH_SPEED_FORCE 4 5 read-write RC32K_LOW_SPEED_FORCE 5 6 read-write VBAT_HL_CONNECT_RES_CTRL 00: OFF 01: Forced ON 10: Active: automatic control, Sleep: forced ON 11: Automatic control 0 2 read-write RAM_LPMX_REG 0x8 16 read-write n 0x0 0x0 RAMx_LPMX RAM[3:1] Transparent Light Sleep (TLS) Core Enable. Assert low to enable the TLS core feature, which will result in lower leakage current. In case VDD is lowered below nominal-10 percent, it may be necessary to hold this pin high to maintain data retention. 0 3 read-write RESET_STAT_REG Reset status register 0x4 16 read-write n 0x0 0x0 HWRESET_STAT Indicates that a HW Reset has happened This bit is also set with a PowerOn Reset 1 2 read-write PORESET_STAT Indicates that a PowerOn Reset has happened 0 1 read-write SWRESET_STAT Indicates that a SW Reset has been requested. The SW reset is requested by SYS_CTRL_REG[SW_RESET] or SCB->AIRCR inside the ARM. This bit is also set with a PowerOn Reset 2 3 read-write WDOGRESET_STAT Indicates that a Watchdog has happened. This bit is also set with a PowerOn Reset 3 4 read-write TEST_VDD_REG 0xF0 16 read-write n 0x0 0x0 LDOS_DISABLE 1 2 read-write TEST_VDD 0 1 read-write CRG_TIM CRG_TIM registers Peripheral_Registers 0x0 0x0 0x50 registers n CLK_RTCDIV_REG Divisor for RTC 100Hz clock 0x4C 32 read-write n 0x0 0x0 RTC_DIV_DENOM Selects the denominator for the fractional division: 0b0: 1000 0b1: 1024 19 20 read-write RTC_DIV_ENABLE Enable for the 100 Hz generation for the RTC block 20 21 read-write RTC_DIV_FRAC Fractional divisor part for RTC 100Hz generation. if RTC_DIV_DENOM=1, out of 1024 cycles will divide by , the rest is If RTC_DIV_DENOM=0, out of 1000 cycles will divide by , the rest is 0 10 read-write RTC_DIV_INT Integer divisor part for RTC 100Hz generation 10 19 read-write RTC_RESET_REQ Reset request for the RTC module 21 22 read-write CRG_TOP CRG_TOP registers Peripheral_Registers 0x0 0x0 0x56 registers n ANA_STATUS_REG Status bit of analog (power management) circuits 0x2A 16 read-write n 0x0 0x0 BANDGAP_OK Indicates that BANDGAP is OK 5 6 read-only BOOST_SELECTED 0: Buck mode detected 1: Boost mode detected 8 9 read-only CLKLESS_WAKEUP_STAT Indicates the output of the Clockless wakeup XOR tree. If this signal is '0', the chip will wake up. Use the HIBERN_WKUP_POLARITY bit to set the value to '1' before going into hibernation mode. 12 13 read-only COMP_VBAT_HIGH_NOK Indicates that VBAT_HIGH < VBAT_LOW -50 mV 4 5 read-only COMP_VBAT_HIGH_OK Indicates that VBAT_HIGH > VBAT_LOW +50 mV 3 4 read-only DCDC_OK Indicates that VBAT_LOW (buck mode) or VBAT_HIGH (boost mode) is OK 2 3 read-only FORCE_RUNNING 11 12 read-only LDO_CORE_OK Indicates that LDO_CORE output is OK 0 1 read-only LDO_GPADC_OK Indicates that LDO_GPADC output is OK 10 11 read-only LDO_LOW_OK Indicates that LDO_LOW output is OK (only valid for high current mode) 1 2 read-only LDO_XTAL_OK Indicates that LDO_XTAL output is OK 9 10 read-only POR_VBAT_HIGH Output of VBAT_HIGH supply rail voltage monitoring circuit. 0: Voltage level on VBAT_HIGH is lower than POR VBAT_HIGH threshold VTH_L (rail not ok, will result in reset if not masked) 1: Voltage level on VBAT_HIGH is higher than POR VBAT_HIGH threshold VTH_H (rail ok, reset released) 7 8 read-only POR_VBAT_LOW Output of VBAT_LOW supply rail voltage monitoring circuit. 0: Voltage level on VBAT_LOW is lower than POR VBAT_LOW threshold VTH_L (rail not ok, will result in reset if not masked) 1: Voltage level on VBAT_LOW is higher than POR VBAT_LOW threshold VTH_H (rail ok, reset released) 6 7 read-only BANDGAP_REG Bandgap trimming 0x28 16 read-write n 0x0 0x0 BGR_ITRIM Current trimming for bias 5 10 read-write BGR_TRIM Trim register for bandgap 0 5 read-write CLK_AMBA_REG HCLK, PCLK, divider and clock gates 0x0 16 read-write n 0x0 0x0 HCLK_DIV AHB interface and microprocessor clock (HCLK). HCLK is source clock divided by: 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 0 2 read-write OTP_ENABLE Clock enable for OTP controller 7 8 read-write PCLK_DIV APB interface clock (PCLK). Divider is cascaded with HCLK_DIV. PCLK is HCLK divided by: 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 4 6 read-write CLK_CTRL_REG Clock control register 0xA 16 read-write n 0x0 0x0 LP_CLK_SEL Sets the clock source of the LowerPower clock 0x0: RC32K 0x1: RCX 0x2: XTAL32K through the oscillator with an external Crystal. 0x3: XTAL32K through an external square wave generator (set PID of P0[3] to FUNC_GPIO) Change this setting before using this clock, and while RUNNING_AT_LP_CLK == 0. 3 5 read-write RUNNING_AT_LP_CLK Indicates that either the LP_CLK is being used as system clock 5 6 read-only RUNNING_AT_RC32M Indicates that the RC32M clock is used as clock 6 7 read-only RUNNING_AT_XTAL32M Indicates that the XTAL32M clock is used as clock, and may not be switched off 7 8 read-only SYS_CLK_SEL Selects the clock source. 0x0: XTAL32M (check the XTAL32M_SETTLED and XTAL32M_TRIM_READY bits!!) 0x1: RC32M 0x2/0x3: LP_CL 0 2 read-write XTAL32M_DISABLE Setting this bit instantaneously disables the 32 MHz crystal oscillator. Also, after sleep/wakeup cycle, the oscillator will not be enabled. This bit may not be set to '1'when RUNNING_AT_XTAL32M is '1' to prevent deadlock. After resetting this bit, wait for XTAL32M_SETTLED or XTAL32M_TRIM_READY to become '1' before switching to XTAL32M clock source. 2 3 read-write CLK_FREQ_TRIM_REG Xtal frequency trimming register 0x2 16 read-write n 0x0 0x0 XTAL32M_TRIM Xtal frequency fine trimming register. 0x00: highest frequency 0xFF: lowest frequency 0 8 read-write CLK_PER_REG Peripheral divider register 0x4 16 read-write n 0x0 0x0 I2C_ENABLE Enable I2C clock 5 6 read-write QUAD_ENABLE Enable the Quadrature clock 11 12 read-write SPI_ENABLE Enable SPI clock 10 11 read-write TMR_DIV Division factor for TIMER0 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 0 2 read-write TMR_ENABLE Enable TIMER0 and TIMER2 clock 3 4 read-write UART1_ENABLE Enable UART1 clock 7 8 read-write UART2_ENABLE Enable UART2 clock 6 7 read-write WAKEUPCT_ENABLE Enable Wakeup CaptureTimer clock 4 5 read-write CLK_RADIO_REG Radio PLL control register 0x8 16 read-write n 0x0 0x0 BLE_DIV Division factor for BLE core blocks 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 The programmed frequency should not be lower than 8 MHz and not faster than the programmed CPU clock frequency. Refer also to BLE_CNTL2_REG[BLE_CLK_SEL]. 4 6 read-write BLE_ENABLE Enable the BLE core clocks 7 8 read-write BLE_LP_RESET Reset for the BLE LP timer 6 7 read-write RFCU_ENABLE Enable the RF control Unit clock 3 4 read-write CLK_RC32K_REG 32 kHz RC oscillator register 0x20 16 read-write n 0x0 0x0 RC32K_DISABLE Instantly disables the 32kHz RC oscillator Sleep cycles cannot happen with this clock disabled. 0 1 read-write RC32K_TRIM 0000 = lowest frequency 0111 = default 1111 = highest frequency 1 5 read-write CLK_RC32M_REG Fast RC control register 0x24 16 read-write n 0x0 0x0 RC32M_BIAS Bias adjustment 1 5 read-write RC32M_COSC C-adjust of RC-oscillator A higher value of COSC results in a lower frequency 7 11 read-write RC32M_DISABLE Instantly disables the 32MHz RC oscillator Disabling of the oscillator during sleep happens automatically. 0 1 read-write RC32M_RANGE Coarse adjust A higher value of RANGE results in a higher frequency, values 2 and 3 are equal 5 7 read-write CLK_RCX_REG RCX-oscillator control register 0x26 16 read-write n 0x0 0x0 RCX_BIAS LDO bias current. 0x0: minimum 0xF: maximum 8 12 read-write RCX_C0 Add unit capacitance to RC-time delay. 7 8 read-write RCX_CADJUST Adjust capacitance part of RC-time delay. 0x00: minimum capacitance 0x1F: maximum capacitance 2 7 read-write RCX_ENABLE Enable the RCX oscillator 0 1 read-write RCX_RADJUST Adjust resistance part of RC-time delay. Lower resistance increases power consumption. 0x0: maximum resistance 0x1: minimum resistance 1 2 read-write CLK_XTAL32K_REG 32 kHz XTAL oscillator register 0x22 16 read-write n 0x0 0x0 XTAL32K_CUR Bias current for the 32kHz XTAL oscillator. 0000 is minimum, 1111 is maximum, 0011 is default. For each application there is an optimal setting for which the start-up behavior is optimal 3 7 read-write XTAL32K_DISABLE_AMPREG Setting this bit disables the amplitude regulation of the XTAL32kHz oscillator. Set this bit to '1' for an external clock to XTAL32Kp Keep this bit '0' with a crystal between XTAL32Kp and XTAL32Km 7 8 read-write XTAL32K_ENABLE Enables the 32kHz XTAL oscillator. Also set GP_DATA_REG[P03_P04_FILT_DIS] = 1 for lowest current consumption. 0 1 read-write XTAL32K_RBIAS Setting for the bias resistor. 00 is maximum, 11 is minimum. Prefered setting will be provided by Dialog 1 3 read-write XTAL32K_XTAL1_BIAS_DISABLE 8 9 read-write PMU_CTRL_REG Power Management Unit control register 0x10 16 read-write n 0x0 0x0 MAP_BANDGAP_EN Enable wakeup diagnostics mapping. When set, these functions are mapped (please set direction to output) P0[2]: BANDGAP_ENABLE P0[1]: Power WOKENUP Note: P0[2] assigned also to SWD_CLK, thus the debugger must be detached before entering into sleep mode with MAP_BANDGAP_EN=1. Refer also to SYS_STAT_REG->DBG_IS_UP. 6 7 read-write OTP_COPY_DIV Sets the HCLK division during OTP mirroring 4 6 read-write RADIO_SLEEP Put the digital part of the radio in powerdown 2 3 read-write RESET_ON_WAKEUP Perform a Hardware Reset after waking up. Booter will be started. 0 1 read-write TIM_SLEEP Put PD_TIM in powerdown 1 2 read-write PMU_SLEEP_REG Bandgap refresh interval during sleep 0x50 16 read-write n 0x0 0x0 BG_REFRESH_INTERVAL This is a value defining the interval every which the Bandgap will be activated for refresh. The value represents ticks of rc32k_clk/64 e.g. 30,5 us * 64 = 1,9 ms. 0 12 read-write POR_PIN_REG Selects a GPIO pin for POR generation 0x40 16 read-write n 0x0 0x0 POR_PIN_POLARITY 0: Active Low 1: Active High Note: This applies only for the GPIO pin. Reset pad has a fixed polarity 7 8 read-write POR_PIN_SELECT Selects the GPIO which is used for POR generation. 0x0: GPIO pin POReset disabled 0x1: P0_0 0x2: P0_1 ... 0xB: P0_10 0xC: P0_11 0xD - 0xF: reserved 0 4 read-write POR_TIMER_REG Time for POR to happen 0x42 16 read-write n 0x0 0x0 POR_TIME Time for the POReset to happen. Formula: Time = POR_TIME x 4096 x RC32k clock period Default value: ~3 seconds When set to 0x00, the POR TIMER is disabled. 0 7 read-write POWER_CTRL_REG Power management control 0x52 16 read-write n 0x0 0x0 CMP_VBAT_HIGH_NOK_ENABLE Enable cmp_vbat_high_nok 0 1 read-write CMP_VBAT_HIGH_OK_ENABLE Enable cmp_vbat_high_ok 1 2 read-write CP_DISABLE Disables LDO_CORE charge-pump circuit 8 9 read-write LDO_CORE_DISABLE Disables LDO_CORE 4 5 read-write LDO_CORE_RET_ENABLE LDO_CORE_RETENTION 0: Disabled 1: Enabled 3 4 read-write LDO_LOW_CTRL_REG 00: High-current mode in active, LDO_LOW OFF in sleep 01: LDO_LOW OFF 10: Low-current mode in active, Low-current mode in sleep 11: High-current mode in active, Low-current mode in sleep 5 7 read-write LDO_VREF_HOLD_FORCE Forces LDO references in HOLD mode 7 8 read-write POR_VBAT_HIGH_DISABLE Disable por_vbat_high circuit 12 13 read-write POR_VBAT_HIGH_HYST_DIS 0: Hysteresis enabled 1: Hysteresis disabled 14 15 read-write POR_VBAT_HIGH_HYST_SEL 0: Low level selected 1: High level selected 13 14 read-write POR_VBAT_LOW_DISABLE Disable por_vbat_low circuit 9 10 read-write POR_VBAT_LOW_HYST_DIS 0: Hysteresis enabled 1: Hysteresis disabled 11 12 read-write POR_VBAT_LOW_HYST_SEL 0: Low level selected 1: High level selected 10 11 read-write VBAT_HL_CONNECT Switch between VBAT_HIGH and VBAT_LOW 0: Open 1: Closed 2 3 read-write VBAT_HL_CONNECT_MODE Sets the control mode fo the switch between VBAT_HIGH and VBAT_LOW 0: Manual (default) 1: Automatic (boost mode only) 15 16 read-write POWER_LEVEL_REG Power management level and trim settings 0x54 16 read-write n 0x0 0x0 DCDC_LEVEL 00: 1.1 V 01: 1.8 V (default) 10: 2.5 V 11: 3.0 V 9 11 read-write DCDC_TRIM Delta from DCDC_LEVEL nominal value 000: -75 mV 001: -50 mV 010: -25 mV 011: 0 (default) 100: +25 mV 101: +50 mV 110: +75 mV 111: +100 mV 11 14 read-write LDO_CORE_LEVEL 0: 0.9V 1: 1.0V (testmode, do not use) 0 1 read-write LDO_CORE_RET_CUR_TRIM 00: Default value 01: 2x error amp tail current 10: 2xadaptive bias feedback ratio 11: 2x both tail current and adaptive bias feedback ratio 7 9 read-write LDO_LOW_TRIM Delta from 1.1 V nominal value 000: -75 mV 001: -50 mV 010: -25 mV 011: 0 (default) 100: +25 mV 101: +50 mV 110: +75 mV 111: +100 mV (coldboot) 1 4 read-write LDO_XTAL_TRIM Delta from 0.9 V nominal value 000: -75 mV 001: -50 mV 010: -25 mV 011: 0 (default) 100: +25 mV 101: +50 mV 110: +75 mV 111: +100 mV 4 7 read-write RAM_PWR_CTRL_REG Control power state of System RAMS 0x18 16 read-write n 0x0 0x0 RAM1_PWR_CTRL Power state control of the individual RAMs. May only change when the memory isn't accessed. When PD_SYS_IS_UP: 0x0: Normal operation 0x1: Normal operation 0x2: Retained (no access possible) 0x3: Off (memory content corrupted) When PD_MEM_IS_DOWN: 0x0: Retained 0x1: Off (memory content corrupted) 0x2: Retained 0x3: Off (memory content corrupted) 0 2 read-write RAM2_PWR_CTRL See description of RAM1_PWR_CTRL. 2 4 read-write RAM3_PWR_CTRL See description of RAM1_PWR_CTRL. 4 6 read-write SYS_CTRL_REG System Control register 0x12 16 read-write n 0x0 0x0 DEBUGGER_ENABLE Enable the debugger. This bit is set by the booter according to the OTP header. If not set, the SWDIO and SW_CLK can be used as gpio ports. 0x0: no debugger enabled. 0x1: SW_CLK = P0[2], SW_DIO=P0[5] 0x2: SW_CLK = P0[2], SW_DIO=P0[1] 0x3: SW_CLK = P0[2], SW_DIO=P0[10] 7 9 read-write DEV_PHASE Sets the development phase mode. If this bit is set, in combination with the OTP_COPY bit, the OTP DMA will emulate the OTP mirroring to System RAM. No actual writing to RAM is done, but the exact same amount of time is spend as if the mirroring would take place. This is to mimic the behavior as if the System Code is already in OTP, and the mirroring takes place after waking up, but the (development) code still resides in an external source. If this bit is set to '0' and OTP_COPY='1', then the OTP DMA will actually do the OTP mirroring at wakeup. 2 3 read-write OTPC_RESET_REQ Reset request for the OTP controller. 6 7 read-write OTP_COPY Enables OTP to SysRAM copy action after waking up PD_SYS 4 5 read-write REMAP_ADR0 Controls which memory is located at address 0x0000 for execution. 0x0: ROM 0x1: OTP 0x2: RAM (SysRAM1) 0x3: RAM (SysRAM3, 28 kBytes offset) This bitfield only takes affect after a Software Reset. 0 2 read-write SW_RESET Writing a '1' to this bit will reset the device, except for: SYS_CTRL_REG CLK_FREQ_TRIM_REG ... 15 16 write-only TIMEOUT_DISABLE Disables timeout in Power statemachine. By default, the statemachine continues if after 2 ms the blocks are not started up. This can be read back from ANA_STATUS_REG. 10 11 read-write SYS_STAT_REG System status register 0x14 16 read-write n 0x0 0x0 DBG_IS_UP Indicates that the SW debugger is attached and in connection with the ARM. 4 5 read-only RAD_IS_DOWN Indicates that PD_RAD is in power down 0 1 read-only RAD_IS_UP Indicates that PD_RAD is functional 1 2 read-only TIM_IS_DOWN Indicates that PD_TIM is in power down 2 3 read-only TIM_IS_UP Indicates that PD_TIM is functional 3 4 read-only XTAL32M_SETTLED Indicates that XTAL32M has had its settle time, as defined by TRIM_CTRL_REG[XTAL_SETTLE_N] 7 8 read-only XTAL32M_TRIM_READY Indicates that XTAL trimming mechanism is ready, i.e. the trimming equals CLK_FREQ_TRIM_REG. 6 7 read-only TRIM_CTRL_REG Control trimming of the XTAL32M 0x16 16 read-write n 0x0 0x0 XTAL_COUNT_N Defines the number of XTAL cycles to be counted, before the xtal trimming is applied, in steps of 64 cycles. 0x01: 64 0x02: 128 0x3f: 4032 0 6 read-write XTAL_SETTLE_N Designates that the XTAL can be safely used as the CPU clock. When XTAL_CLK_CNT reases this value, the signal XTAL32M_SETTLED bit in the SYS_STAT_REG will be set. Counts in steps of 64 xtal clock-cycles. 8 14 read-write XTAL_TRIM_SELECT Select which source controls the XTAL trimming 0b00: xtal counter. Starts CLK_FREQ_TRIM_REG[XTAL32M_START] after COUNT_N * 32 xtal pulses trim is changed to CLK_FREQ_TRIM_REG[XTAL32M_TRIM]. 0b01: xtal OK filter. Starts with CLK_FREQ_TRIM_REG[XTAL32M_START], when xtal is ramping is changed to CLK_FREQ_TRIM_REG[XTAL32M_TRIM]. 0b10: statically forced off. Only uses CLK_FREQ_TRIM_REG[XTAL32M_TRIM]. 0b11: xtal OK filter, 2 stage. Starts with CLK_FREQ_TRIM_REG[XTAL32M_START] switches to CLK_FREQ_TRIM_REG[XTAL32M_RAMP] after timeout (sw1='1', XTAL32M_CTRL0_REG[XTAL32M_SW_DELAY]), and switches to CLK_FREQ_TRIM_REG[XTAL32M_TRIM] when sw2='1'. 6 8 read-write XTAL32M_CTRL0_REG Control bits for XTAL32M 0x38 16 read-write n 0x0 0x0 CORE_AMPL_REG_NULLBIAS Keep bias in ampl detector alive, even when there is a large drive 1 2 read-write CORE_AMPL_TRIM Core amplitude trimming 5 8 read-write CORE_CUR_SET Core current trim setting 2 5 read-write DCBLOCK_ENABLE Enable dcblock/high pass filter circuit 0 1 read-write XTAL32M_SPARE 8 10 read-write XTAL32M_START_REG Trim values for XTAL32M 0x30 16 read-write n 0x0 0x0 XTAL32M_RAMP Xtal frequency trimming register. 0x00 : highest frequency 0xFF :lowest frequency 8 16 read-write XTAL32M_START Xtal frequency trimming register. 0x0 = highest frequency 0xF = lowest frequency. 0 8 read-write XTAL32M_TRSTAT_REG Read back value of current XTAL trimming 0x32 16 read-write n 0x0 0x0 XTAL32M_TRSTAT Reads value of the current XTAL trimming 0 8 read-only XTALRDY_CTRL_REG Control register for XTALRDY IRQ 0x34 16 read-write n 0x0 0x0 XTALRDY_CNT Number of 32kHz or 256kHz cycles between the crystal is enabled, and the XTALRDY_IRQ is fired. Frequency set by XTALRDY_CLK_SEL. 0x00: no interrupt 0 8 read-write XTALRDY_STAT_REG 0x36 16 read-write n 0x0 0x0 XTALRDY_STAT 0 8 read-only DCDC DCDC registers Peripheral_Registers 0x0 0x0 0x2 registers n CTRL_REG 0x0 16 read-write n 0x0 0x0 DCDC_CLK_DIV Idle clock divider, sets rate at which the output is monitored when the converter is idle. 0x0: Divide by 4 0x1: Divide by 8 (default) 0x2: Divide by 16 0x3: Divide by 32 1 3 read-write DCDC_ENABLE Enables hardware control of the DCDC converter. 0: DCDC converter disabled 1: DCDC converter under hardware control 0 1 read-write DCDC_ILIM_MAX Maximum value for automatic inductor peak current limit control. 0x0: 6 mA 0x1: 12 mA 0x2: 18 mA 0x3: 24 mA 0x4: 30 mA 0x5: 36 mA 0x6: 42 mA 0x7: 48 mA 0x8: 54 mA (default, limits inrush current) 0x9: 60 mA 0xA: 66 mA 0xB: 72 mA 0xC: 78 mA 0xD: 84 mA 0xE: 90 mA 0xF: 96 mA (set as default for low-ohmic batteries) 12 16 read-write DCDC_ILIM_MIN Minimum value for automatic inductor peak current limit control. 0x0: 6 mA 0x1: 12 mA 0x2: 18 mA 0x3: 24 mA 0x4: 30 mA (default) 0x5: 36 mA 0x6: 42 mA 0x7: 48 mA 0x8: 54 mA 0x9: 60 mA 0xA: 66 mA 0xB: 72 mA 0xC: 78 mA 0xD: 84 mA 0xE: 90 mA 0xF: 96 mA 8 12 read-write DCDC_OK_CLR_CNT Number of subsequent V_NOK events needed to reset VDCD_OK. 0x0: 2 0x1: 4 0x2: 8 (deafult) 0x3: 15 6 8 read-write DCDC_TIMEOUT Switch timeout, go to next state if either switch is active for longer than this setting. 0x0: Disabled 0x1: 0.25 ms 0x2: 0.50 ms 0x3: 0.75 ms 0x4: 1.00 ms (default) 0x5: 1.25 ms 0x6: 1.50 ms 0x7: 1.75 ms 3 6 read-write DMA DMA registers Peripheral_Registers 0x0 0x0 0x86 registers n CLEAR_INT_REG DMA clear interrupt register 0x84 16 read-write n 0x0 0x0 DMA_RST_IRQ_CH0 Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 0 writing a 0 will have no effect 0 1 write-only DMA_RST_IRQ_CH1 Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 1 writing a 0 will have no effect 1 2 write-only DMA_RST_IRQ_CH2 Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 2 writing a 0 will have no effect 2 3 write-only DMA_RST_IRQ_CH3 Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 3 writing a 0 will have no effect 3 4 write-only DMA0_A_STARTH_REG Start address High A of DMA channel 0 0x2 16 read-write n 0x0 0x0 DMA0_A_STARTH Source start address, upper 16 bits 0 16 read-write DMA0_A_STARTL_REG Start address Low A of DMA channel 0 0x0 16 read-write n 0x0 0x0 DMA0_A_STARTL Source start address, lower 16 bits 0 16 read-write DMA0_B_STARTH_REG Start address High B of DMA channel 0 0x6 16 read-write n 0x0 0x0 DMA0_B_STARTH Destination start address, upper 16 bits 0 16 read-write DMA0_B_STARTL_REG Start address Low B of DMA channel 0 0x4 16 read-write n 0x0 0x0 DMA0_B_STARTL Destination start address, lower 16 bits 0 16 read-write DMA0_CTRL_REG Control register for the DMA channel 0 0xC 16 read-write n 0x0 0x0 AINC Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 6 7 read-write BINC Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 5 6 read-write BW Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved 1 3 read-write CIRCULAR 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer. 7 8 read-write DMA_IDLE 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care. 11 12 read-write DMA_INIT 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'. 12 13 read-write DMA_ON 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. 0 1 read-write DMA_PRIO The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus. 8 11 read-write DREQ_MODE 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG) 4 5 read-write IRQ_ENABLE 0 = disable interrupt on this channel 1 = enable interrupt on this channel 3 4 read-write REQ_SENSE 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests 13 14 read-write DMA0_IDX_REG Index value of DMA channel 0 0xE 16 read-write n 0x0 0x0 DMA0_IDX This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW. 0 16 read-only DMA0_INT_REG DMA receive interrupt register channel 0 0x8 16 read-write n 0x0 0x0 DMA0_INT Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt. 0 16 read-write DMA0_LEN_REG DMA receive length register channel 0 0xA 16 read-write n 0x0 0x0 DMA0_LEN DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ... 0 16 read-write DMA1_A_STARTH_REG Start address High A of DMA channel 1 0x12 16 read-write n 0x0 0x0 DMA1_A_STARTH Source start address, upper 16 bits 0 16 read-write DMA1_A_STARTL_REG Start address Low A of DMA channel 1 0x10 16 read-write n 0x0 0x0 DMA1_A_STARTL Source start address, lower 16 bits 0 16 read-write DMA1_B_STARTH_REG Start address High B of DMA channel 1 0x16 16 read-write n 0x0 0x0 DMA1_B_STARTH Destination start address, upper 16 bits 0 16 read-write DMA1_B_STARTL_REG Start address Low B of DMA channel 1 0x14 16 read-write n 0x0 0x0 DMA1_B_STARTL Destination start address, lower 16 bits 0 16 read-write DMA1_CTRL_REG Control register for the DMA channel 1 0x1C 16 read-write n 0x0 0x0 AINC Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 6 7 read-write BINC Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 5 6 read-write BW Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved 1 3 read-write CIRCULAR 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer. 7 8 read-write DMA_IDLE 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care. 11 12 read-write DMA_INIT 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'. 12 13 read-write DMA_ON 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. 0 1 read-write DMA_PRIO The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus. 8 11 read-write DREQ_MODE 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG) 4 5 read-write IRQ_ENABLE 0 = disable interrupt on this channel 1 = enable interrupt on this channel 3 4 read-write REQ_SENSE 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests 13 14 read-write DMA1_IDX_REG Index value of DMA channel 1 0x1E 16 read-write n 0x0 0x0 DMA1_IDX This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW. 0 16 read-only DMA1_INT_REG DMA receive interrupt register channel 1 0x18 16 read-write n 0x0 0x0 DMA1_INT Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt. 0 16 read-write DMA1_LEN_REG DMA receive length register channel 1 0x1A 16 read-write n 0x0 0x0 DMA1_LEN DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ... 0 16 read-write DMA2_A_STARTH_REG Start address High A of DMA channel 2 0x22 16 read-write n 0x0 0x0 DMA2_A_STARTH Source start address, upper 16 bits 0 16 read-write DMA2_A_STARTL_REG Start address Low A of DMA channel 2 0x20 16 read-write n 0x0 0x0 DMA2_A_STARTL Source start address, lower 16 bits 0 16 read-write DMA2_B_STARTH_REG Start address High B of DMA channel 2 0x26 16 read-write n 0x0 0x0 DMA2_B_STARTH Destination start address, upper 16 bits 0 16 read-write DMA2_B_STARTL_REG Start address Low B of DMA channel 2 0x24 16 read-write n 0x0 0x0 DMA2_B_STARTL Destination start address, lower 16 bits 0 16 read-write DMA2_CTRL_REG Control register for the DMA channel 2 0x2C 16 read-write n 0x0 0x0 AINC Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 6 7 read-write BINC Enable increment of destination address 0 = do not increment 1 = increment according value of BW 5 6 read-write BW Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved 1 3 read-write CIRCULAR 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer. 7 8 read-write DMA_IDLE 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care. 11 12 read-write DMA_INIT 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'. 12 13 read-write DMA_ON 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. 0 1 read-write DMA_PRIO The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus. 8 11 read-write DREQ_MODE 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG) 4 5 read-write IRQ_ENABLE 0 = disable interrupt on this channel 1 = enable interrupt on this channel 3 4 read-write REQ_SENSE 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests 13 14 read-write DMA2_IDX_REG Index value of DMA channel 2 0x2E 16 read-write n 0x0 0x0 DMA2_IDX This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW. 0 16 read-only DMA2_INT_REG DMA receive interrupt register channel 2 0x28 16 read-write n 0x0 0x0 DMA2_INT Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt. 0 16 read-write DMA2_LEN_REG DMA receive length register channel 2 0x2A 16 read-write n 0x0 0x0 DMA2_LEN DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ... 0 16 read-write DMA3_A_STARTH_REG Start address High A of DMA channel 3 0x32 16 read-write n 0x0 0x0 DMA3_A_STARTH Source start address, upper 16 bits 0 16 read-write DMA3_A_STARTL_REG Start address Low A of DMA channel 3 0x30 16 read-write n 0x0 0x0 DMA3_A_STARTL Source start address, lower 16 bits 0 16 read-write DMA3_B_STARTH_REG Start address High B of DMA channel 3 0x36 16 read-write n 0x0 0x0 DMA3_B_STARTH Destination start address, upper 16 bits 0 16 read-write DMA3_B_STARTL_REG Start address Low B of DMA channel 3 0x34 16 read-write n 0x0 0x0 DMA3_B_STARTL Destination start address, lower 16 bits 0 16 read-write DMA3_CTRL_REG Control register for the DMA channel 3 0x3C 16 read-write n 0x0 0x0 AINC Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 6 7 read-write BINC Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 5 6 read-write BW Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved 1 3 read-write CIRCULAR 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer. 7 8 read-write DMA_IDLE 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care. 11 12 read-write DMA_INIT 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'. 12 13 read-write DMA_ON 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. 0 1 read-write DMA_PRIO The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus. 8 11 read-write DREQ_MODE 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG) 4 5 read-write IRQ_ENABLE 0 = disable interrupt on this channel 1 = enable interrupt on this channel 3 4 read-write REQ_SENSE 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests 13 14 read-write DMA3_IDX_REG Index value of DMA channel 3 0x3E 16 read-write n 0x0 0x0 DMA3_IDX This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW. 0 16 read-only DMA3_INT_REG DMA receive interrupt register channel 3 0x38 16 read-write n 0x0 0x0 DMA3_INT Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt. 0 16 read-write DMA3_LEN_REG DMA receive length register channel 3 0x3A 16 read-write n 0x0 0x0 DMA3_LEN DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ... 0 16 read-write INT_STATUS_REG DMA interrupt status register 0x82 16 read-write n 0x0 0x0 DMA_IRQ_CH0 0: IRQ on channel 0 is not set 1: IRQ on channel 0 is set 0 1 read-only DMA_IRQ_CH1 0: IRQ on channel 1 is not set 1: IRQ on channel 1 is set 1 2 read-only DMA_IRQ_CH2 0: IRQ on channel 2 is not set 1: IRQ on channel 2 is set 2 3 read-only DMA_IRQ_CH3 0: IRQ on channel 3 is not set 1: IRQ on channel 3 is set 3 4 read-only REQ_MUX_REG DMA channel assignments 0x80 16 read-write n 0x0 0x0 DMA01_SEL Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels. Here, the first DMA request is mapped on channel 0 and the second on channel 1. 0x0: SPI_rx / SPI_tx 0x1: Reserved 0x2: UART_rx / UART_tx 0x3: UART2_rx / UART2_tx 0x4: I2C_rx / I2C_tx 0x5: GP_ADC (Rx only) 0x6-0xE: Reserved 0xF: None Note: If any of the two available peripheral selector fields (DMA01_SEL, DMA23_SEL) have the same value, the lesser significant selector has higher priority and will control the dma acknowledge. Hence, if DMA01_SEL = DMA23_SEL, the channels 0 and 1 will generate the DMA acknowledge signals for the selected peripheral. Consequently, it is suggested to assign the intended peripheral value to a unique selector field. 0 4 read-write DMA23_SEL Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels. Here, the first DMA request is mapped on channel 2 and the second on channel 3. See DMA01_SEL for the peripherals' mapping. 4 8 read-write GPADC GPADC registers Peripheral_Registers 0x0 0x0 0x12 registers n 0x0 0x12 registers n GP_ADC_CLEAR_INT_REG General Purpose ADC Clear Interrupt Register 0xE 16 read-write n 0x0 0x0 GP_ADC_CLR_INT Writing any value to this register will clear the ADC_INT interrupt. Reading returns 0. 0 16 write-only GP_ADC_CTRL2_REG General Purpose ADC Second Control Register 0x2 16 read-write n 0x0 0x0 GP_ADC_ATTN 0: No attenuator (input voltages up to 0.9V allowed) 1: Enabling 2x attenuator (input voltages up to 1.8V allowed) 2: Enabling 3x attenuator (input voltages up to 2.7V allowed) 3: Enabling 4x attenuator (input voltages up to 3.6V allowed) Enabling the attenuator requires a longer sampling time. 0 2 read-write GP_ADC_CONV_NRS 0: 1 sample is taken or 2 in case ADC_CHOP is active. 1: 2 samples are taken. 2: 4 samples are taken. 7: 128 samples are taken. 6 9 read-write GP_ADC_I20U 1: Adds 20uA constant load current at the ADC LDO to minimize ripple on the reference voltage of the ADC. 2 3 read-write GP_ADC_OFFS_SH_CM Common mode adjust for offset shifter. Input range is CM +/- 450mV. 0: CM = 1.25V (Input range 0.80 - 1.70) 1: CM = 1.30V (Input range 0.85 - 1.75) (default) 2: CM = 1.35V (Input range 0.90 - 1.80) 3: CM = 1.40V (input range 0.95 - 1.85) 4 6 read-write GP_ADC_OFFS_SH_EN 0: Disable input shifter 1: Enable input shifter (900mV - 1800mV shifted to 0mV - 900mV) 3 4 read-write GP_ADC_SMPL_TIME 0: The sample time (switch is closed) is one ADC_CLK cycle 1: The sample time is 1*8 ADC_CLK cycles 2: The sample time is 2*8 ADC_CLK cycles 15: The sample time is 15*8 ADC_CLK cycles 9 13 read-write GP_ADC_STORE_DEL 0: Data is stored after handshake synchronisation 1: Data is stored 2 ADC_CLK cycles after internal start trigger 7: Data is stored 8 ADC_CLK cycles after internal start trigger 13 16 read-write GP_ADC_CTRL3_REG General Purpose ADC Third Control Register 0x4 16 read-write n 0x0 0x0 GP_ADC_EN_DEL Defines the delay for enabling the ADC after enabling the LDO. 0: Not allowed 1: 4x ADC_CLK period. n: n*4x ADC_CLK period. 0 8 read-write GP_ADC_INTERVAL Defines the interval between two ADC conversions in case GP_ADC_CONT is set in units of PER_CLK/1152 (typ 1kHz) 0: No extra delay between two conversions. 1: 1 ms interval between two conversions. 2: 2 ms interval between two conversions. 255: 255 ms interval between two conversions. 8 16 read-write GP_ADC_CTRL_REG General Purpose ADC Control Register 0x0 16 read-write n 0x0 0x0 DIE_TEMP_EN Enables the die-temperature sensor. Output can be measured on GPADC input 4. 12 13 read-write GP_ADC_CHOP 0: Chopper mode off 1: Chopper mode enabled. Takes two samples with opposite GP_ADC_SIGN to cancel the internal offset voltage of the ADC Highly recommended for DC-measurements. 9 10 read-write GP_ADC_CONT 0: Manual ADC mode, a single result will be generated after setting the GP_ADC_START bit. 1: Continuous ADC mode, new ADC results will be constantly stored in GP_ADC_RESULT_REG. Still GP_ADC_START has to be set to start the execution. The time between conversions is configurable with GP_ADC_INTERVAL. 2 3 read-write GP_ADC_DMA_EN 0: DMA functionality disabled 1: DMA functionality enabled 3 4 read-write GP_ADC_EN 0: LDO is off and ADC is disabled.. 1: LDO is turned on and afterwards the ADC is enabled. 0 1 read-write GP_ADC_INT 1: AD conversion ready and has generated an interrupt. Must be cleared by writing any value to GP_ADC_CLEAR_INT_REG. 4 5 read-only GP_ADC_LDO_HOLD 0: GPADC LDO tracking bandgap reference 1: GPADC LDO hold sampled bandgap reference 10 11 read-write GP_ADC_MINT 0: Disable (mask) GP_ADC_INT. 1: Enable GP_ADC_INT to ICU. 5 6 read-write GP_ADC_MUTE 0: Normal operation 1: Mute ADC input. Takes sample at mid-scale (to dertermine the internal offset and/or noise of the ADC with regards to VDD_REF which is also sampled by the ADC). 7 8 read-write GP_ADC_OFFS_SH_GAIN_SEL 11 12 read-write GP_ADC_SE 0: Differential mode 1: Single ended mode 6 7 read-write GP_ADC_SIGN 0: Default 1: Conversion with opposite sign at input and output to cancel out the internal offset of the ADC and low-frequency 8 9 read-write GP_ADC_START 0: ADC conversion ready. 1: If a 1 is written, the ADC starts a conversion. After the conversion this bit will be set to 0 and the GP_ADC_INT bit will be set. It is not allowed to write this bit while it is not (yet) zero. 1 2 read-write GP_ADC_OFFN_REG General Purpose ADC Negative Offset Register 0xA 16 read-write n 0x0 0x0 GP_ADC_OFFN Offset adjust of 'negative' array of ADC-network (effective if GP_ADC_SE=0 , or GP_ADC_SE=1 AND GP_ADC_SIGN=1 OR GP_ADC_CHOP=1 ) 0 10 read-write GP_ADC_OFFP_REG General Purpose ADC Positive Offset Register 0x8 16 read-write n 0x0 0x0 GP_ADC_OFFP Offset adjust of 'positive' array of ADC-network (effective if GP_ADC_SE=0 , or GP_ADC_SE=1 AND GP_ADC_SIGN=0 OR GP_ADC_CHOP=1 ) 0 10 read-write GP_ADC_PARAM_DIF_REG 0x1C 16 read-write n 0x0 0x0 GP_ADC_PARAM_SE_REG 0x1E 16 read-write n 0x0 0x0 GP_ADC_RESULT_REG General Purpose ADC Result Register 0x10 16 read-write n 0x0 0x0 GP_ADC_VAL Returns the 10 up to 16 bits linear value of the last AD conversion. The upper 10 bits are always valid, the lower 6 bits are only valid in case oversampling has been applied. Two samples results in one extra bit and 64 samples results in six extra bits. 0 16 read-only GP_ADC_TRIM_REG General Purpose ADC Trim Register 0xC 16 read-write n 0x0 0x0 GP_ADC_LDO_LEVEL GPADC LDO level 0: 825mV 1: 850mV 2: 875mV 3: 900mV (default) 4: 925mV 5: 950mV 6: 975mV 7:1000mV 4 7 read-write GP_ADC_OFFS_SH_VREF Offset Shifter common-mode reference fine trimming: 2mV/LSB Default = mid-scale at 1000 0 4 read-write GPIO GPIO registers Peripheral_Registers 0x0 0x0 0x20 registers n 0x0 0x20 registers n BIST_CTRL_REG 0x3C 16 read-write n 0x0 0x0 RAM_BIST_CONFIG 0 2 read-write RAM_BIST_PATTERN 12 14 read-write ROMBIST_ENABLE 2 3 read-write ROM_BIST_BUSY 5 6 read-only SYSRAM12_BIST_BUSY 11 12 read-only SYSRAM12_BIST_ENABLE 3 4 read-write SYSRAM12_BIST_FAIL 10 11 read-only SYSRAM3_BIST_BUSY 8 9 read-only SYSRAM3_BIST_ENABLE 14 15 read-write SYSRAM3_BIST_FAIL 7 8 read-only P00_MODE_REG P00 Mode Register 0x6 16 read-write n 0x0 0x0 PID Function of port 0 = GPIO (pin direction determined by PUPD field) 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SYS_CLK 6 = LP_CLK 7 = Reserved 8 = Reserved 9 = I2C_SCL 10 = I2C_SDA 11 = PWM5 12 = PWM6 13 = PWM7 14 = Reserved 15 = ADC (only for P0_1, P0_2, P0_6 and P0_7) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (signals mapped to P0[3:0] are also mapped to P0[11:8]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = Reserved 22 = Reserved 23 = PWM2 24 = PWM3 25 = PWM4 26 = SPI_DI 27 = SPI_DO 28 = SPI_CLK 29 = SPI_CSN0 30 = SPI_CSN1 31 = Reserved Note: When a certain input function (like SPI_DI) is selected on more than 1 pins, the pin of the lowest index has the highest priority. 0 5 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P010_MODE_REG P010 Mode Register 0x1A 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 5 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected 8 10 read-write P011_MODE_REG P011 Mode Register 0x1C 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 5 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected 8 10 read-write P01_MODE_REG P01 Mode Register 0x8 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 5 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P02_MODE_REG P02 Mode Register 0xA 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 5 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P03_MODE_REG P03 Mode Register 0xC 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 5 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P04_MODE_REG P04 Mode Register 0xE 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 5 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected 8 10 read-write P05_MODE_REG P05 Mode Register 0x10 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 5 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected 8 10 read-write P06_MODE_REG P06 Mode Register 0x12 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 5 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected 8 10 read-write P07_MODE_REG P07 Mode Register 0x14 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 5 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected 8 10 read-write P08_MODE_REG P08 Mode Register 0x16 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 5 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected 8 10 read-write P09_MODE_REG P09 Mode Register 0x18 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 5 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected 8 10 read-write P0_DATA_REG P0 Data input/output Register 0x0 16 read-write n 0x0 0x0 P0_DATA Sets P0 output register when written Returns the value of P0 port when read 0 12 read-write P0_RESET_DATA_REG P0 Reset port pins Register 0x4 16 read-write n 0x0 0x0 P0_RESET Writing a 1 to P0[x] sets P0[x] to 0. Writing 0 is discarded, reading returns 0. 0 12 write-only P0_SET_DATA_REG P0 Set port pins Register 0x2 16 read-write n 0x0 0x0 P0_SET Writing a 1 to P0[x] sets P0[x] to 1. Writing 0 is discarded, reading returns 0 0 12 write-only PAD_WEAK_CTRL_REG Pad driving strength control Register 0x1E 16 read-write n 0x0 0x0 PAD_LOW_DRV 0 = Normal operation 1 = Reduces the driving strength of P0_x pad. Bit x controls the driving strength of P0_x, x=0, 1,..., 11. 0 12 read-write ROMBIST_RESULTH_REG 0x40 16 read-write n 0x0 0x0 ROMBIST_RESULTH 0 16 read-only ROMBIST_RESULTL_REG 0x3E 16 read-write n 0x0 0x0 ROMBIST_RESULTL 0 16 read-only SCAN_OBSERVE_REG 0x20 16 read-write n 0x0 0x0 SCAN_FEEDBACK_MUX 0 16 read-only TEST_CTRL2_REG 0x32 16 read-write n 0x0 0x0 ANA_TEST_OUT_PARAM 12 16 read-write ANA_TEST_OUT_SEL 0 10 read-write ANA_TEST_OUT_TO_PIN 11 12 read-write TEST_CTRL3_REG 0x34 16 read-write n 0x0 0x0 ENABLE_RFPT 6 7 read-write RF_TEST_OUT_PARAM 7 13 read-write RF_TEST_OUT_SEL 0 6 read-write RF_TEST_OUT_TO_PIN 13 14 read-write TEST_CTRL4_REG 0x36 16 read-write n 0x0 0x0 RF_TEST_IN_PARAM 8 13 read-write RF_TEST_IN_SEL 0 4 read-write RF_TEST_IN_TO_PIN 13 14 read-write TEST_CTRL_REG 0x30 16 read-write n 0x0 0x0 ADPLL_SCAN_COMP_EN 12 13 read-write ADPLL_SCAN_TEST_EN 11 12 read-write CP_CAP_BIAS_TRIM 9 11 read-write LDO_CORE_CAP_BYPASS 5 6 read-write LDO_CORE_DUMMY_LOAD_ENABLE 6 7 read-write SHOW_CLOCKS 0 1 read-write SHOW_DCDC 2 3 read-write SHOW_POWER 1 2 read-write XTAL32M_CAP_TEST_EN 4 5 read-write XTAL32M_TESTCTRL0_REG 0x38 16 read-write n 0x0 0x0 BIAS_SAH_HOLD_OVERRIDE 14 16 read-write CORE_FREQ_TRIM_SW2_AMP 11 14 read-write CORE_GM_CURRENT 10 11 read-write CORE_HOLD_AMP_REG_OVERRIDE 8 10 read-write CORE_I2V_TO_TESTBUS 7 8 read-write CORE_I2V_TO_TESTBUS_10X 6 7 read-write CORE_MAX_CURRENT 5 6 read-write CORE_XTAL_DISCHARGE 4 5 read-write DCBLOCK_LV_MODE 3 4 read-write DIFFBUF_BYPASS 2 3 read-write OSC_TRIM_OPEN_DISABLE 1 2 read-write SPIKE_FLT_DISABLE 0 1 read-write XTAL32M_TESTCTRL1_REG 0x3A 16 read-write n 0x0 0x0 DISABLE_TM_CLK 0 1 read-write LDO_VREF_HOLD_OVERRIDE 1 2 read-write OSC_TRIM_CAP_BIAS 8 9 read-write PROG_VREF_SEL 4 5 read-write RFCLK_ADC_TO_GPIO 6 7 read-write RFCLK_ADPLL_TO_GPIO 5 6 read-write RFCLK_SEL_ADPLL_ADC_TO_GPIO 7 8 read-write VARICAP_TEST_ENABLE 2 3 read-write VARICAP_TEST_SEL_XTAL 3 4 read-write GPREG GPREG registers Peripheral_Registers 0x0 0x0 0xC registers n 0x0 0xC registers n BLE_TIMER_REG BLE FINECNT sampled value while in deep sleep state. 0xA 16 read-write n 0x0 0x0 BLE_TIMER_DATA Operation depends on GP_CONTROL_REG->BLE_TIMER_DATA_CTRL. If BLE_TIMER_DATA_CTRL = 0 then: This register is located at the Always On Power Domain and it holds the automatically sampled value of the BLE FINECNT timer The HW automatically samples the value into this register during the sequence of BLE Sleep On and restores automatically the value during the BLE Wake up sequence. The Software may read and modify the value while the BLE is in Sleep state. While the BLE is awake, the value of the register has no meaning, while changing the value by writing another one will have no effect in the operation of the BLE core. There is a constraint when the SW performs an write-read sequence where it has to inject a one cycle delay in between (e.g. write-NOP-read) in order to read back the correct value. If BLE_TIMER_DATA_CTRL is non 0 then write operations have the same effect as when BLE_TIMER_DATA_CTRL=0, while for read operations: BLE_TIMER_DATA_CTRL= 1: then reading BLE_TIMER_REG returns deepsldur[9:0] . BLE_TIMER_DATA_CTRL= 2: then reading BLE_TIMER_REG returns deepsltime_samp[9:0] . BLE_TIMER_DATA_CTRL= 3: then reading BLE_TIMER_REG returns {deep_sleep_stat_monitor, deepsltime_samp[18:10]}. . 0 10 read-write DEBUG_REG Various debug information register. 0x4 16 read-write n 0x0 0x0 DEBUGS_FREEZE_EN Default '1', freezing of the on-chip timers is enabled when the Cortex-M0Plus is halted in DEBUG State. If '0', freezing of the on-chip timers is depending on FREEZE_REG when the Cortex-M0Plus is halted in DEBUG State except the watchdog timer. The watchdog timer is always frozen when the Cortex-M0Plus is halted in DEBUG State. 0 1 read-write GP_CONTROL_REG General purpose system control register. 0x8 16 read-write n 0x0 0x0 BLE_TIMER_DATA_CTRL Refer to BLE_TIMER_REG. 5 7 read-write BLE_WAKEUP_LP_IRQ The current value of the BLE_WAKEUP_LP_IRQ interrupt request. 2 3 read-only BLE_WAKEUP_REQ If '1', the BLE wakes up. Must be kept high at least for 1 low power clock period. If the BLE is in deep sleep state, then by setting this bit it will cause the wakeup LP IRQ to be asserted with a delay of 3 to 4 low power cycles. 0 1 read-write CPU_DMA_BUS_PRIO Controls the CPU DMA system bus priority: If '0', the CPU has highest priority. If '1', the DMA has highest priority. 4 5 read-write GP_STATUS_REG General purpose system status register. 0x6 16 read-write n 0x0 0x0 CAL_PHASE If '1', it designates that the chip is in Calibration Phase i.e. the OTP has been initially programmed but no Calibration has occured. 0 1 read-write MEM_CTRL_REG 0xC 16 read-write n 0x0 0x0 ARB1_AHB2_WR_BUFF 9 10 read-only ARB1_AHB_WR_BUFF 8 9 read-only ARB2_AHB2_WR_BUFF 11 12 read-only ARB2_AHB_WR_BUFF 10 11 read-only RAM_DST 5 6 read-write RAM_MARGIN 6 8 read-write ROM_MARGIN_CTRL 0 4 read-write ROM_MARGIN_EN 4 5 read-write RESET_FREEZE_REG Controls unfreezing of various timers/counters. 0x2 16 read-write n 0x0 0x0 FRZ_BLETIM If '1', the the BLE master clock continues, '0' is discarded. 2 3 read-write FRZ_DMA If '1', the DMA continues, '0' is discarded. 4 5 read-write FRZ_SWTIM If '1', the SW Timer (TIMER0) continues, '0' is discarded. 1 2 read-write FRZ_WDOG If '1', the watchdog timer continues, '0' is discarded. 3 4 read-write FRZ_WKUPTIM If '1', the Wake Up Timer continues, '0' is discarded. 0 1 read-write SET_FREEZE_REG Controls freezing of various timers/counters. 0x0 16 read-write n 0x0 0x0 FRZ_BLETIM If '1', the BLE master clock is frozen, '0' is discarded. 2 3 read-write FRZ_DMA If '1', the DMA is frozen, '0' is discarded. 4 5 read-write FRZ_SWTIM If '1', the SW Timer (TIMER0) is frozen, '0' is discarded. 1 2 read-write FRZ_WDOG If '1', the watchdog timer is frozen, '0' is discarded. WATCHDOG_CTRL_REG[NMI_RST] must be '0' to allow the freeze function. 3 4 read-write FRZ_WKUPTIM If '1', the Wake Up Timer is frozen, '0' is discarded. 0 1 read-write I2C I2C registers Peripheral_Registers 0x0 0x0 0x100 registers n ACK_GENERAL_CALL_REG I2C ACK General Call Register 0x98 16 read-write n 0x0 0x0 ACK_GEN_CALL ACK General Call. When set to 1, I2C Ctrl responds with a ACK (by asserting ic_data_oe) when it receives a General Call. When set to 0, the controller does not generate General Call interrupts. 0 1 read-write CLR_ACTIVITY_REG Clear ACTIVITY Interrupt Register 0x5C 16 read-write n 0x0 0x0 CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register 0 1 read-only CLR_GEN_CALL_REG Clear GEN_CALL Interrupt Register 0x68 16 read-write n 0x0 0x0 CLR_GEN_CALL Read this register to clear the GEN_CALL interrupt (bit 11) of I2C_RAW_INTR_STAT register. 0 1 read-only CLR_INTR_REG Clear Combined and Individual Interrupt Register 0x40 16 read-write n 0x0 0x0 CLR_INTR Read this register to clear the combined interrupt, all individual interrupts, and the I2C_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing I2C_TX_ABRT_SOURCE 0 1 read-only CLR_RD_REQ_REG Clear RD_REQ Interrupt Register 0x50 16 read-write n 0x0 0x0 CLR_RD_REQ Read this register to clear the RD_REQ interrupt (bit 5) of the I2C_RAW_INTR_STAT register. 0 1 read-only CLR_RX_DONE_REG Clear RX_DONE Interrupt Register 0x58 16 read-write n 0x0 0x0 CLR_RX_DONE Read this register to clear the RX_DONE interrupt (bit 7) of the I2C_RAW_INTR_STAT register. 0 1 read-only CLR_RX_OVER_REG Clear RX_OVER Interrupt Register 0x48 16 read-write n 0x0 0x0 CLR_RX_OVER Read this register to clear the RX_OVER interrupt (bit 1) of the I2C_RAW_INTR_STAT register. 0 1 read-only CLR_RX_UNDER_REG Clear RX_UNDER Interrupt Register 0x44 16 read-write n 0x0 0x0 CLR_RX_UNDER Read this register to clear the RX_UNDER interrupt (bit 0) of the I2C_RAW_INTR_STAT register. 0 1 read-only CLR_START_DET_REG Clear START_DET Interrupt Register 0x64 16 read-write n 0x0 0x0 CLR_START_DET Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. 0 1 read-only CLR_STOP_DET_REG Clear STOP_DET Interrupt Register 0x60 16 read-write n 0x0 0x0 CLR_STOP_DET Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. Reset value: 0x0 0 1 read-only CLR_TX_ABRT_REG Clear TX_ABRT Interrupt Register 0x54 16 read-write n 0x0 0x0 CLR_TX_ABRT Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the I2C_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. 0 1 read-only CLR_TX_OVER_REG Clear TX_OVER Interrupt Register 0x4C 16 read-write n 0x0 0x0 CLR_TX_OVER Read this register to clear the TX_OVER interrupt (bit 3) of the I2C_RAW_INTR_STAT register. 0 1 read-only COMP2_VERSION I2C Component2 Version Register 0xFA 16 read-write n 0x0 0x0 IC_COMP2_VERSION 0 16 read-only COMP_PARAM1_REG Component Parameter Register 0xF4 16 read-write n 0x0 0x0 IC_COMP_PARAM1 0 16 read-only COMP_PARAM2_REG Component Parameter Register 2 0xF6 16 read-write n 0x0 0x0 IC_COMP_PARAM2 0 16 read-only COMP_TYPE2_REG I2C Component2 Type Register 0xFE 16 read-write n 0x0 0x0 IC_COMP2_TYPE 0 16 read-only COMP_TYPE_REG I2C Component Type Register 0xFC 16 read-write n 0x0 0x0 IC_COMP_TYPE 0 16 read-only COMP_VERSION_REG I2C Component Version Register 0xF8 16 read-write n 0x0 0x0 IC_COMP_VERSION 0 16 read-only CON_REG I2C Control Register 0x0 16 read-write n 0x0 0x0 I2C_10BITADDR_MASTER Controls whether the controller starts its transfers in 7- or 10-bit addressing mode when acting as a master. 0= 7-bit addressing 1= 10-bit addressing 4 5 read-write I2C_10BITADDR_SLAVE When acting as a slave, this bit controls whether the controller responds to 7- or 10-bit addresses. 0= 7-bit addressing 1= 10-bit addressing 3 4 read-write I2C_MASTER_MODE This bit controls whether the controller master is enabled. 0= master disabled 1= master enabled Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. 0 1 read-write I2C_RESTART_EN Determines whether RESTART conditions may be sent when acting as a master 0= disable 1=enable 5 6 read-write I2C_SLAVE_DISABLE Slave enabled or disabled after reset is applied, which means software does not have to configure the slave. 0=slave is enabled 1=slave is disabled Software should ensure that if this bit is written with '0', then bit 0 should also be written with a '0'. 6 7 read-write I2C_SPEED These bits control at which speed the controller operates. 1= standard mode (100 kbit/s) 2= fast mode (400 kbit/s) Note: The actuall speed depends on the pcb traces capacitance as well as on the values of the external pull-up resistorts. For an exact speed match, trimming might be required, by adjusting the values of I2C_SS_SCL_HCNT_REG, I2C_SS_SCL_LCNT_REG, I2C_FS_SCL_HCNT_REG, I2C_FS_SCL_LCNT_REG registers. The reset values of those registers were calculated with the assumption of 4.3kOhms external pull-up resistors. 1 3 read-write DATA_CMD_REG I2C Rx/Tx Data Buffer and Command Register 0x10 16 read-write n 0x0 0x0 DAT This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the controller. However, when you read this register, these bits return the value of data received on the controller's interface. 0 8 read-write I2C_CMD This bit controls whether a read or a write is performed. This bit does not control the direction when the I2C Ctrl acts as a slave. It controls only the direction when it acts as a master. 1 = Read 0 = Write When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a don't care because writes to this register are not required. In slave-transmitter mode, a 0 indicates that CPU data is to be transmitted and as DAT or IC_DATA_CMD[7:0]. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the I2C_RAW_INTR_STAT_REG), unless bit 11 (SPECIAL) in the I2C_TAR register has been cleared. If a 1 is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. NOTE: It is possible that while attempting a master I2C read transfer on the controller, a RD_REQ interrupt may have occurred simultaneously due to a remote I2C master addressing the controller. In this type of scenario, it ignores the I2C_DATA_CMD write, generates a TX_ABRT interrupt, and waits to service the RD_REQ interrupt 8 9 read-write I2C_RESTART This bit controls whether a RESTART is issued before the byte is sent or received. If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. Reset value: 0x0 10 11 read-write I2C_STOP This bit controls whether a STOP is issued after the byte is sent or received. STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 9 10 read-write DMA_CR_REG DMA Control Register 0x88 16 read-write n 0x0 0x0 RDMAE Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. 0 = Receive DMA disabled 1 = Receive DMA enabled 0 1 read-write TDMAE Transmit DMA Enable. //This bit enables/disables the transmit FIFO DMA channel. 0 = Transmit DMA disabled 1 = Transmit DMA enabled 1 2 read-write DMA_RDLR_REG I2C Receive Data Level Register 0x90 16 read-write n 0x0 0x0 DMARDL Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1 that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. 0 5 read-write DMA_TDLR_REG DMA Transmit Data Level Register 0x8C 16 read-write n 0x0 0x0 DMATDL Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. 0 5 read-write ENABLE_REG I2C Enable Register 0x6C 16 read-write n 0x0 0x0 CTRL_ENABLE Controls whether the controller is enabled. 0: Disables the controller (TX and RX FIFOs are held in an erased state) 1: Enables the controller Software can disable the controller while it is active. However, it is important that care be taken to ensure that the controller is disabled properly. When the controller is disabled, the following occurs: * The TX FIFO and RX FIFO get flushed. * Status bits in the IC_INTR_STAT register are still active until the controller goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the controller stops the current transfer at the end of the current byte and does not acknowledge the transfer. There is a two ic_clk delay when enabling or disabling the controller 0 1 read-write I2C_ABORT 0= ABORT not initiated or ABORT done 1= ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. 1 2 read-write ENABLE_STATUS_REG I2C Enable Status Register 0x9C 16 read-write n 0x0 0x0 IC_EN ic_en Status. This bit always reflects the value driven on the output port ic_en. When read as 1, the controller is deemed to be in an enabled state. When read as 0, the controller is deemed completely inactive. NOTE: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). 0 1 read-only SLV_DISABLED_WHILE_BUSY Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) I2C Ctrl is receiving the address byte of the Slave-Transmitter operation from a remote master OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, the controller is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in I2C Ctrl (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit will also be set to 1. When read as 0, the controller is deemed to have been disabled when there is master activity, or when the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. 1 2 read-only SLV_RX_DATA_LOST Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting of IC_ENABLE from 1 to 0. When read as 1, the controller is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit is also set to 1. When read as 0, the controller is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. 2 3 read-only FS_SCL_HCNT_REG Fast Speed I2C Clock SCL High Count Register 0x1C 16 read-write n 0x0 0x0 IC_FS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set. 0 16 read-write FS_SCL_LCNT_REG Fast Speed I2C Clock SCL Low Count Register 0x20 16 read-write n 0x0 0x0 IC_FS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low-period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the controller. The lower byte must be programmed first. Then the upper byte is programmed. 0 16 read-write IC_FS_SPKLEN_REG I2C SS and FS spike suppression limit Size 0xA0 16 read-write n 0x0 0x0 IC_FS_SPKLEN This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 1 hardware prevents values less than this being written, and if attempted results in 1 being set. 0 8 read-write INTR_MASK_REG I2C Interrupt Mask Register 0x30 16 read-write n 0x0 0x0 M_ACTIVITY These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 8 9 read-write M_GEN_CALL These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 11 12 read-write M_RD_REQ These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 5 6 read-write M_RX_DONE These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 7 8 read-write M_RX_FULL These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 2 3 read-write M_RX_OVER These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 1 2 read-write M_RX_UNDER These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0 1 read-write M_START_DET These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 10 11 read-write M_STOP_DET These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 9 10 read-write M_TX_ABRT These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 6 7 read-write M_TX_EMPTY These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 4 5 read-write M_TX_OVER These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 3 4 read-write INTR_STAT_REG I2C Interrupt Status Register 0x2C 16 read-write n 0x0 0x0 R_ACTIVITY This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it: => Disabling the I2C Ctrl => Reading the IC_CLR_ACTIVITY register => Reading the IC_CLR_INTR register => System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus. 8 9 read-only R_GEN_CALL Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. The controller stores the received data in the Rx buffer. 11 12 read-only R_RD_REQ This bit is set to 1 when the controller is acting as a slave and another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register 5 6 read-only R_RX_DONE When the controller is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. 7 8 read-only R_RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. 2 3 read-only R_RX_OVER Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 1 2 read-only R_RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 0 1 read-only R_START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 10 11 read-only R_STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 9 10 read-only R_TX_ABRT This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a transmit abort . When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface. 6 7 read-only R_TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0. 4 5 read-only R_TX_OVER Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared 3 4 read-only RAW_INTR_STAT_REG I2C Raw Interrupt Status Register 0x34 16 read-write n 0x0 0x0 ACTIVITY This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it: => Disabling the I2C Ctrl => Reading the IC_CLR_ACTIVITY register => Reading the IC_CLR_INTR register => System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus. 8 9 read-only GEN_CALL Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. I2C Ctrl stores the received data in the Rx buffer. 11 12 read-only RD_REQ This bit is set to 1 when I2C Ctrl is acting as a slave and another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register 5 6 read-only RX_DONE When the controller is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. 7 8 read-only RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. 2 3 read-only RX_OVER Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 1 2 read-only RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 0 1 read-only START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 10 11 read-only STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 9 10 read-only TX_ABRT This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a transmit abort . When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface. 6 7 read-only TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0. 4 5 read-only TX_OVER Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared 3 4 read-only RXFLR_REG I2C Receive FIFO Level Register 0x78 16 read-write n 0x0 0x0 RXFLR Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Size is constrained by the RXFLR value 0 6 read-only RX_TL_REG I2C Receive FIFO Threshold Register 0x38 16 read-write n 0x0 0x0 RX_TL Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in I2C_RAW_INTR_STAT register). The valid range is 0-31, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 31 sets the threshold for 32 entries. 0 5 read-write SAR_REG I2C Slave Address Register 0x8 16 read-write n 0x0 0x0 IC_SAR The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. 0 10 read-write SDA_HOLD_REG I2C SDA Hold Time Length Register 0x7C 16 read-write n 0x0 0x0 IC_SDA_HOLD SDA Hold time 0 16 read-write SDA_SETUP_REG I2C SDA Setup Register 0x94 16 read-write n 0x0 0x0 SDA_SETUP SDA Setup. This register controls the amount of time delay (number of I2C clock periods) between the rising edge of SCL and SDA changing by holding SCL low when I2C block services a read request while operating as a slave-transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. It is recommended that if the required delay is 1000ns, then for an I2C frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11.Writes to this register succeed only when IC_ENABLE[0] = 0. 0 8 read-write SS_SCL_HCNT_REG Standard Speed I2C Clock SCL High Count Register 0x14 16 read-write n 0x0 0x0 IC_SS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set. NOTE: This register must not be programmed to a value higher than 65525, because the controller uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. 0 16 read-write SS_SCL_LCNT_REG Standard Speed I2C Clock SCL Low Count Register 0x18 16 read-write n 0x0 0x0 IC_SS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted, results in 8 being set. 0 16 read-write STATUS_REG I2C Status Register 0x70 16 read-write n 0x0 0x0 I2C_ACTIVITY I2C Activity Status. 0 1 read-only MST_ACTIVITY Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. 0: Master FSM is in IDLE state so the Master part of the controller is not Active 1: Master FSM is not in IDLE state so the Master part of the controller is Active 5 6 read-only RFF Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0: Receive FIFO is not full 1: Receive FIFO is full 4 5 read-only RFNE Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries it is cleared when the receive FIFO is empty. 0: Receive FIFO is empty 1: Receive FIFO is not empty 3 4 read-only SLV_ACTIVITY Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. 0: Slave FSM is in IDLE state so the Slave part of the controller is not Active 1: Slave FSM is not in IDLE state so the Slave part of the controller is Active 6 7 read-only TFE Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0: Transmit FIFO is not empty 1: Transmit FIFO is empty 2 3 read-only TFNF Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0: Transmit FIFO is full 1: Transmit FIFO is not full 1 2 read-only TAR_REG I2C Target Address Register 0x4 16 read-write n 0x0 0x0 GC_OR_START If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the controller. 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The controller remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. 1: START BYTE 10 11 read-write IC_TAR This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. Note: If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself it can transmit to only a slave 0 10 read-write SPECIAL This bit indicates whether software performs a General Call or START BYTE command. 0: ignore bit 10 GC_OR_START and use IC_TAR normally 1: perform special I2C command as specified in GC_OR_START bit 11 12 read-write TXFLR_REG I2C Transmit FIFO Level Register 0x74 16 read-write n 0x0 0x0 TXFLR Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Size is constrained by the TXFLR value 0 6 read-only TX_ABRT_SOURCE_REG I2C Transmit Abort Source Register 0x80 16 read-write n 0x0 0x0 ABRT_10ADDR1_NOACK 1: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. 1 2 read-only ABRT_10ADDR2_NOACK 1: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave. 2 3 read-only ABRT_10B_RD_NORSTRT 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode. 10 11 read-only ABRT_7B_ADDR_NOACK 1: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. 0 1 read-only ABRT_GCALL_NOACK 1: the controller in master mode sent a General Call and no slave on the bus acknowledged the General Call. 4 5 read-only ABRT_GCALL_READ 1: the controller in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). 5 6 read-only ABRT_HS_ACKDET 1: Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). 6 7 read-only ABRT_HS_NORSTRT 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode 8 9 read-only ABRT_MASTER_DIS 1: User tries to initiate a Master operation with the Master mode disabled. 11 12 read-only ABRT_SBYTE_ACKDET 1: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). 7 8 read-only ABRT_SBYTE_NORSTRT To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first restart must be enabled (I2C_CON[5]=1), the SPECIAL bit must be cleared (I2C_TAR[11]), or the GC_OR_START bit must be cleared (I2C_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets re-asserted. 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to send a START Byte. 9 10 read-only ABRT_SLVFLUSH_TXFIFO 1: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. 13 14 read-only ABRT_SLVRD_INTX 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of 2IC_DATA_CMD register 15 16 read-only ABRT_SLV_ARBLOST 1: Slave lost the bus while transmitting data to a remote master. I2C_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never owns the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then the controller no longer own the bus. 14 15 read-only ABRT_TXDATA_NOACK 1: This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). 3 4 read-only ARB_LOST 1: Master has lost arbitration, or if I2C_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. Note: I2C can be both master and slave at the same time. 12 13 read-only TX_TL_REG I2C Transmit FIFO Threshold Register 0x3C 16 read-write n 0x0 0x0 RX_TL Transmit FIFO Threshold Level Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in I2C_RAW_INTR_STAT register). The valid range is 0-31, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 31 sets the threshold for 32 entries.. 0 5 read-write KBRD KBRD registers Peripheral_Registers 0x0 0x0 0x16 registers n CTRL_REG GPIO Kbrd control register 0x14 16 read-write n 0x0 0x0 KBRD_LEVEL 0 = enabled input will generate KBRD IRQ if that input is high. 1 = enabled input will generate KBRD IRQ if that input is low. 6 7 read-write KBRD_REL 0 = No interrupt on key release 1 = Interrupt also on key release (also debouncing if enabled) 7 8 read-write KEY_REPEAT While key is pressed, automatically generate repeating KEYB_INT after specified time unequal to 0. Repeat time: N*1 ms. N =1..63, N=0 disables the timer. 0 6 read-write GPIO_DEBOUNCE_REG debounce counter value for GPIO inputs 0xC 16 read-write n 0x0 0x0 DEB_ENABLE0 enables the debounce counter for GPIO IRQ0 6 7 read-write DEB_ENABLE1 enables the debounce counter for GPIO IRQ1 7 8 read-write DEB_ENABLE2 enables the debounce counter for GPIO IRQ2 8 9 read-write DEB_ENABLE3 enables the debounce counter for GPIO IRQ3 9 10 read-write DEB_ENABLE4 enables the debounce counter for GPIO IRQ4 10 11 read-write DEB_ENABLE_KBRD enables the debounce counter for the KBRD interface 11 12 read-write DEB_VALUE Keyboard debounce time if enabled. Generate KEYB_INT after specified time. Debounce time: N*1 ms. N =0..63 0 6 read-write GPIO_INT_LEVEL_CTRL_REG high or low level select for GPIO interrupts 0x10 16 read-write n 0x0 0x0 EDGE_LEVELn0 0: do not wait for key release after interrupt was reset for GPIO IRQ0, so a new interrupt can be initiated immediately 1: wait for key release after interrupt was reset for IRQ0 5 6 read-write EDGE_LEVELn1 see EDGE_LEVELn0, but for GPIO IRQ1 6 7 read-write EDGE_LEVELn2 see EDGE_LEVELn0, but for GPIO IRQ2 7 8 read-write EDGE_LEVELn3 see EDGE_LEVELn0, but for GPIO IRQ3 8 9 read-write EDGE_LEVELn4 see EDGE_LEVELn0, but for GPIO IRQ4 9 10 read-write INPUT_LEVEL0 0 = selected input will generate GPIO IRQ0 if that input is high. 1 = selected input will generate GPIO IRQ0 if that input is low. 0 1 read-write INPUT_LEVEL1 see INPUT_LEVEL0, but for GPIO IRQ1 1 2 read-write INPUT_LEVEL2 see INPUT_LEVEL0, but for GPIO IRQ2 2 3 read-write INPUT_LEVEL3 see INPUT_LEVEL0, but for GPIO IRQ3 3 4 read-write INPUT_LEVEL4 see INPUT_LEVEL0, but for GPIO IRQ4 4 5 read-write GPIO_IRQ0_IN_SEL_REG GPIO interrupt selection for GPIO_IRQ0 0x0 16 read-write n 0x0 0x0 KBRD_IRQ0_SEL input selection that can generate a GPIO interrupt 1: P0[0] is selected 2: P0[1] is selected 3: P0[2] is selected 4: P0[3] is selected 5: P0[4] is selected 6: P0[5] is selected 7: P0[6] is selected 8: P0[7] is selected 9: P0[8] is selected 10: P0[9] is selected 11: P0[10] is selected 12: P0[11] is selected all others: no input selected 0 4 read-write GPIO_IRQ1_IN_SEL_REG GPIO interrupt selection for GPIO_IRQ1 0x2 16 read-write n 0x0 0x0 KBRD_IRQ1_SEL see KBRD_IRQ0_SEL 0 4 read-write GPIO_IRQ2_IN_SEL_REG GPIO interrupt selection for GPIO_IRQ2 0x4 16 read-write n 0x0 0x0 KBRD_IRQ2_SEL see KBRD_IRQ0_SEL 0 4 read-write GPIO_IRQ3_IN_SEL_REG GPIO interrupt selection for GPIO_IRQ3 0x6 16 read-write n 0x0 0x0 KBRD_IRQ3_SEL see KBRD_IRQ0_SEL 0 4 read-write GPIO_IRQ4_IN_SEL_REG GPIO interrupt selection for GPIO_IRQ4 0x8 16 read-write n 0x0 0x0 KBRD_IRQ4_SEL see KBRD_IRQ0_SEL 0 4 read-write GPIO_RESET_IRQ_REG GPIO interrupt reset register 0xE 16 read-write n 0x0 0x0 RESET_GPIO0_IRQ writing a 1 to this bit will reset the GPIO0 IRQ. Reading returns 0. 0 1 write-only RESET_GPIO1_IRQ writing a 1 to this bit will reset the GPIO1 IRQ. Reading returns 0. 1 2 write-only RESET_GPIO2_IRQ writing a 1 to this bit will reset the GPIO2 IRQ. Reading returns 0. 2 3 write-only RESET_GPIO3_IRQ writing a 1 to this bit will reset the GPIO3 IRQ. Reading returns 0. 3 4 write-only RESET_GPIO4_IRQ writing a 1 to this bit will reset the GPIO4 IRQ. Reading returns 0. 4 5 write-only RESET_KBRD_IRQ writing a 1 to this bit will reset the KBRD IRQ. Reading returns 0. 5 6 write-only IRQ_IN_SEL0_REG GPIO interrupt selection for KBRD_IRQ for P0 0x12 16 read-write n 0x0 0x0 KBRD_P00_EN enable P0[0] for the keyboard interrupt 0 1 read-write KBRD_P01_EN enable P0[1] for the keyboard interrupt 1 2 read-write KBRD_P02_EN enable P0[2] for the keyboard interrupt 2 3 read-write KBRD_P03_EN enable P0[3] for the keyboard interrupt 3 4 read-write KBRD_P04_EN enable P0[4] for the keyboard interrupt 4 5 read-write KBRD_P05_EN enable P0[5] for the keyboard interrupt 5 6 read-write KBRD_P06_EN enable P0[6] for the keyboard interrupt 6 7 read-write KBRD_P07_EN enable P0[7] for the keyboard interrupt 7 8 read-write KBRD_P08_EN enable P0[8] for the keyboard interrupt 8 9 read-write KBRD_P09_EN enable P0[9] for the keyboard interrupt 9 10 read-write KBRD_P10_EN enable P0[10] for the keyboard interrupt 10 11 read-write KBRD_P11_EN enable P0[11] for the keyboard interrupt 11 12 read-write MBIST_SRAM12 MBIST_SRAM12 registers Peripheral_Registers 0x0 0x0 0x8 registers n ADDR_REG 0x0 16 read-write n 0x0 0x0 MBIST_ADDR Returns the current address register in case of a mismatch. 0 1 read-only RD_LSB_REG 0x6 16 read-write n 0x0 0x0 MBIST_LSB_DATA Returns the actual LSB read data in case of a mismatch. 0 1 read-only RD_MSB_REG 0x4 16 read-write n 0x0 0x0 MBIST_MSB_DATA Returns the actual MSB read data in case of a mismatch. 0 1 read-only STATE_REG 0x2 16 read-write n 0x0 0x0 MBIST_STATE Returns the current state in case of a mismatch. 0 1 read-only MBIST_SRAM3 MBIST_SRAM3 registers Peripheral_Registers 0x0 0x0 0x8 registers n ADDR_REG 0x0 16 read-write n 0x0 0x0 MBIST_ADDR Returns the current address register in case of a mismatch. 0 1 read-only RD_LSB_REG 0x6 16 read-write n 0x0 0x0 MBIST_LSB_DATA Returns the actual LSB read data in case of a mismatch. 0 1 read-only RD_MSB_REG 0x4 16 read-write n 0x0 0x0 MBIST_MSB_DATA Returns the actual MSB read data in case of a mismatch. 0 1 read-only STATE_REG 0x2 16 read-write n 0x0 0x0 MBIST_STATE Returns the current state in case of a mismatch. 0 1 read-only NVIC Cortex M0 NVIC registers NVIC 0x0 0x0 0x321 registers n ICER Interrupt clear-enable register 0x80 32 read-write n 0x0 0x0 ADC_IRQn ADC_IRQn (Interrupt clear-enable bit) 14 15 read-write BLE_GEN_IRQn BLE_GEN_IRQn (Interrupt clear-enable bit) 1 2 read-write BLE_WAKEUP_LP_IRQn BLE_WAKEUP_LP_IRQn (Interrupt clear-enable bit) 0 1 read-write COEX_IRQn COEX_IRQn (Interrupt clear-enable bit) 5 6 read-write CRYPTO_IRQn CRYPTO_IRQn (Interrupt clear-enable bit) 6 7 read-write DCDC_IRQn DCDC_IRQn (Interrupt clear-enable bit) 29 30 read-write DMA_IRQn DMA_IRQn (Interrupt clear-enable bit) 26 27 read-write FTDF_GEN_IRQn FTDF_GEN_IRQn (Interrupt clear-enable bit) 3 4 read-write FTDF_WAKEUP_IRQn FTDF_WAKEUP_IRQn (Interrupt clear-enable bit) 2 3 read-write I2C2_IRQn I2C2_IRQn (Interrupt clear-enable bit) 11 12 read-write I2C_IRQn I2C_IRQn (Interrupt clear-enable bit) 10 11 read-write IRGEN_IRQn IRGEN_IRQn (Interrupt clear-enable bit) 16 17 read-write KEYBRD_IRQn KEYBRD_IRQn (Interrupt clear-enable bit) 15 16 read-write MRM_IRQn MRM_IRQn (Interrupt clear-enable bit) 7 8 read-write PCM_IRQn PCM_IRQn (Interrupt clear-enable bit) 22 23 read-write QUADEC_IRQn QUADEC_IRQn (Interrupt clear-enable bit) 20 21 read-write RFCAL_IRQn RFCAL_IRQn (Interrupt clear-enable bit) 4 5 read-write RF_DIAG_IRQn RF_DIAG_IRQn (Interrupt clear-enable bit) 27 28 read-write Rsvd__irq__n Rsvd__irq__n (Reserved) 31 32 read-write SPI2_IRQn SPI2_IRQn (Interrupt clear-enable bit) 13 14 read-write SPI_IRQn SPI_IRQn (Interrupt clear-enable bit) 12 13 read-write SRC_IN_IRQn SRC_IN_IRQn (Interrupt clear-enable bit) 23 24 read-write SRC_OUT_IRQn SRC_OUT_IRQn (Interrupt clear-enable bit) 24 25 read-write SWTIM0_IRQn SWTIM0_IRQn (Interrupt clear-enable bit) 18 19 read-write SWTIM1_IRQn SWTIM1_IRQn (Interrupt clear-enable bit) 19 20 read-write TRNG_IRQn TRNG_IRQn (Interrupt clear-enable bit) 28 29 read-write UART2_IRQn UART2_IRQn (Interrupt clear-enable bit) 9 10 read-write UART_IRQn UART_IRQn (Interrupt clear-enable bit) 8 9 read-write USB_IRQn USB_IRQn (Interrupt clear-enable bit) 21 22 read-write VBUS_IRQn VBUS_IRQn (Interrupt clear-enable bit) 25 26 read-write WKUP_GPIO_IRQn WKUP_GPIO_IRQn (Interrupt clear-enable bit) 17 18 read-write XTAL16RDY_IRQn XTAL16RDY_IRQn (Interrupt clear-enable bit) 30 31 read-write ICPR Interrupt clear-pending register 0x180 32 read-write n 0x0 0x0 ADC_IRQn ADC_IRQn (Interrupt clear-pending bit) 14 15 read-write BLE_GEN_IRQn BLE_GEN_IRQn (Interrupt clear-pending bit) 1 2 read-write BLE_WAKEUP_LP_IRQn BLE_WAKEUP_LP_IRQn (Interrupt clear-pending bit) 0 1 read-write COEX_IRQn COEX_IRQn (Interrupt clear-pending bit) 5 6 read-write CRYPTO_IRQn CRYPTO_IRQn (Interrupt clear-pending bit) 6 7 read-write DCDC_IRQn DCDC_IRQn (Interrupt clear-pending bit) 29 30 read-write DMA_IRQn DMA_IRQn (Interrupt clear-pending bit) 26 27 read-write FTDF_GEN_IRQn FTDF_GEN_IRQn (Interrupt clear-pending bit) 3 4 read-write FTDF_WAKEUP_IRQn FTDF_WAKEUP_IRQn (Interrupt clear-pending bit) 2 3 read-write I2C2_IRQn I2C2_IRQn (Interrupt clear-pending bit) 11 12 read-write I2C_IRQn I2C_IRQn (Interrupt clear-pending bit) 10 11 read-write IRGEN_IRQn IRGEN_IRQn (Interrupt clear-pending bit) 16 17 read-write KEYBRD_IRQn KEYBRD_IRQn (Interrupt clear-pending bit) 15 16 read-write MRM_IRQn MRM_IRQn (Interrupt clear-pending bit) 7 8 read-write PCM_IRQn PCM_IRQn (Interrupt clear-pending bit) 22 23 read-write QUADEC_IRQn QUADEC_IRQn (Interrupt clear-pending bit) 20 21 read-write RFCAL_IRQn RFCAL_IRQn (Interrupt clear-pending bit) 4 5 read-write RF_DIAG_IRQn RF_DIAG_IRQn (Interrupt clear-pending bit) 27 28 read-write Rsvd__irq__n Rsvd__irq__n (Reserved) 31 32 read-write SPI2_IRQn SPI2_IRQn (Interrupt clear-pending bit) 13 14 read-write SPI_IRQn SPI_IRQn (Interrupt clear-pending bit) 12 13 read-write SRC_IN_IRQn SRC_IN_IRQn (Interrupt clear-pending bit) 23 24 read-write SRC_OUT_IRQn SRC_OUT_IRQn (Interrupt clear-pending bit) 24 25 read-write SWTIM0_IRQn SWTIM0_IRQn (Interrupt clear-pending bit) 18 19 read-write SWTIM1_IRQn SWTIM1_IRQn (Interrupt clear-pending bit) 19 20 read-write TRNG_IRQn TRNG_IRQn (Interrupt clear-pending bit) 28 29 read-write UART2_IRQn UART2_IRQn (Interrupt clear-pending bit) 9 10 read-write UART_IRQn UART_IRQn (Interrupt clear-pending bit) 8 9 read-write USB_IRQn USB_IRQn (Interrupt clear-pending bit) 21 22 read-write VBUS_IRQn VBUS_IRQn (Interrupt clear-pending bit) 25 26 read-write WKUP_GPIO_IRQn WKUP_GPIO_IRQn (Interrupt clear-pending bit) 17 18 read-write XTAL16RDY_IRQn XTAL16RDY_IRQn (Interrupt clear-pending bit) 30 31 read-write IPR0 Interrupt priority register 0 0x300 32 read-write n 0x0 0x0 BLE_GEN_IRQn_prio BLE_GEN_IRQn[7:0] bits (Interrupt priority) 8 16 read-write BLE_WAKEUP_LP_IRQn_prio BLE_WAKEUP_LP_IRQn[7:0] bits (Interrupt priority) 0 8 read-write FTDF_GEN_IRQn_prio FTDF_GEN_IRQn[7:0] bits (Interrupt priority) 24 32 read-write FTDF_WAKEUP_IRQn_prio FTDF_WAKEUP_IRQn[7:0] bits (Interrupt priority) 16 24 read-write IPR1 Interrupt priority register 1 0x304 32 read-write n 0x0 0x0 COEX_IRQn_prio COEX_IRQn[7:0] bits (Interrupt priority) 8 16 read-write CRYPTO_IRQn_prio CRYPTO_IRQn[7:0] bits (Interrupt priority) 16 24 read-write MRM_IRQn_prio MRM_IRQn[7:0] bits (Interrupt priority) 24 32 read-write RFCAL_IRQn_prio RFCAL_IRQn[7:0] bits (Interrupt priority) 0 8 read-write IPR2 Interrupt priority register 2 0x308 32 read-write n 0x0 0x0 I2C2_IRQn_prio I2C2_IRQn[7:0] bits (Interrupt priority) 24 32 read-write I2C_IRQn_prio I2C_IRQn[7:0] bits (Interrupt priority) 16 24 read-write UART2_IRQn_prio UART2_IRQn[7:0] bits (Interrupt priority) 8 16 read-write UART_IRQn_prio UART_IRQn[7:0] bits (Interrupt priority) 0 8 read-write IPR3 Interrupt priority register 3 0x30C 32 read-write n 0x0 0x0 ADC_IRQn_prio ADC_IRQn[7:0] bits (Interrupt priority) 16 24 read-write KEYBRD_IRQn_prio KEYBRD_IRQn[7:0] bits (Interrupt priority) 24 32 read-write SPI2_IRQn_prio SPI2_IRQn[7:0] bits (Interrupt priority) 8 16 read-write SPI_IRQn_prio SPI_IRQn[7:0] bits (Interrupt priority) 0 8 read-write IPR4 Interrupt priority register 4 0x310 32 read-write n 0x0 0x0 IRGEN_IRQn_prio IRGEN_IRQn[7:0] bits (Interrupt priority) 0 8 read-write SWTIM0_IRQn_prio SWTIM0_IRQn[7:0] bits (Interrupt priority) 16 24 read-write SWTIM1_IRQn_prio SWTIM1_IRQn[7:0] bits (Interrupt priority) 24 32 read-write WKUP_GPIO_IRQn_prio WKUP_GPIO_IRQn[7:0] bits (Interrupt priority) 8 16 read-write IPR5 Interrupt priority register 5 0x314 32 read-write n 0x0 0x0 PCM_IRQn_prio PCM_IRQn[7:0] bits (Interrupt priority) 16 24 read-write QUADEC_IRQn_prio QUADEC_IRQn[7:0] bits (Interrupt priority) 0 8 read-write SRC_IN_IRQn_prio SRC_IN_IRQn[7:0] bits (Interrupt priority) 24 32 read-write USB_IRQn_prio USB_IRQn[7:0] bits (Interrupt priority) 8 16 read-write IPR6 Interrupt priority register 6 0x318 32 read-write n 0x0 0x0 DMA_IRQn_prio DMA_IRQn[7:0] bits (Interrupt priority) 16 24 read-write RF_DIAG_IRQn_prio RF_DIAG_IRQn[7:0] bits (Interrupt priority) 24 32 read-write SRC_OUT_IRQn_prio SRC_OUT_IRQn[7:0] bits (Interrupt priority) 0 8 read-write VBUS_IRQn_prio VBUS_IRQn[7:0] bits (Interrupt priority) 8 16 read-write IPR7 Interrupt priority register 7 0x31C 32 read-write n 0x0 0x0 DCDC_IRQn_prio DCDC_IRQn[7:0] bits (Interrupt priority) 8 16 read-write RESERVED31_IRQn_DONT_USE RESERVED31_IRQn[7:0] bits (Reserved) 24 32 read-write TRNG_IRQn_prio TRNG_IRQn[7:0] bits (Interrupt priority) 0 8 read-write XTAL16RDY_IRQn_prio XTAL16RDY_IRQn[7:0] bits (Interrupt priority) 16 24 read-write ISER Interrupt set-enable register 0x0 32 read-write n 0x0 0x0 ADC_IRQn ADC_IRQn (Interrupt set-enable bit) 14 15 read-write BLE_GEN_IRQn BLE_GEN_IRQn (Interrupt set-enable bit) 1 2 read-write BLE_WAKEUP_LP_IRQn BLE_WAKEUP_LP_IRQn (Interrupt set-enable bit) 0 1 read-write COEX_IRQn COEX_IRQn (Interrupt set-enable bit) 5 6 read-write CRYPTO_IRQn CRYPTO_IRQn (Interrupt set-enable bit) 6 7 read-write DCDC_IRQn DCDC_IRQn (Interrupt set-enable bit) 29 30 read-write DMA_IRQn DMA_IRQn (Interrupt set-enable bit) 26 27 read-write FTDF_GEN_IRQn FTDF_GEN_IRQn (Interrupt set-enable bit) 3 4 read-write FTDF_WAKEUP_IRQn FTDF_WAKEUP_IRQn (Interrupt set-enable bit) 2 3 read-write I2C2_IRQn I2C2_IRQn (Interrupt set-enable bit) 11 12 read-write I2C_IRQn I2C_IRQn (Interrupt set-enable bit) 10 11 read-write IRGEN_IRQn IRGEN_IRQn (Interrupt set-enable bit) 16 17 read-write KEYBRD_IRQn KEYBRD_IRQn (Interrupt set-enable bit) 15 16 read-write MRM_IRQn MRM_IRQn (Interrupt set-enable bit) 7 8 read-write PCM_IRQn PCM_IRQn (Interrupt set-enable bit) 22 23 read-write QUADEC_IRQn QUADEC_IRQn (Interrupt set-enable bit) 20 21 read-write RFCAL_IRQn RFCAL_IRQn (Interrupt set-enable bit) 4 5 read-write RF_DIAG_IRQn RF_DIAG_IRQn (Interrupt set-enable bit) 27 28 read-write Rsvd__irq__n Rsvd__irq__n (Reserved) 31 32 read-write SPI2_IRQn SPI2_IRQn (Interrupt set-enable bit) 13 14 read-write SPI_IRQn SPI_IRQn (Interrupt set-enable bit) 12 13 read-write SRC_IN_IRQn SRC_IN_IRQn (Interrupt set-enable bit) 23 24 read-write SRC_OUT_IRQn SRC_OUT_IRQn (Interrupt set-enable bit) 24 25 read-write SWTIM0_IRQn SWTIM0_IRQn (Interrupt set-enable bit) 18 19 read-write SWTIM1_IRQn SWTIM1_IRQn (Interrupt set-enable bit) 19 20 read-write TRNG_IRQn TRNG_IRQn (Interrupt set-enable bit) 28 29 read-write UART2_IRQn UART2_IRQn (Interrupt set-enable bit) 9 10 read-write UART_IRQn UART_IRQn (Interrupt set-enable bit) 8 9 read-write USB_IRQn USB_IRQn (Interrupt set-enable bit) 21 22 read-write VBUS_IRQn VBUS_IRQn (Interrupt set-enable bit) 25 26 read-write WKUP_GPIO_IRQn WKUP_GPIO_IRQn (Interrupt set-enable bit) 17 18 read-write XTAL16RDY_IRQn XTAL16RDY_IRQn (Interrupt set-enable bit) 30 31 read-write ISPR Interrupt set-pending register 0x100 32 read-write n 0x0 0x0 ADC_IRQn ADC_IRQn (Interrupt set-pending bit) 14 15 read-write BLE_GEN_IRQn BLE_GEN_IRQn (Interrupt set-pending bit) 1 2 read-write BLE_WAKEUP_LP_IRQn BLE_WAKEUP_LP_IRQn (Interrupt set-pending bit) 0 1 read-write COEX_IRQn COEX_IRQn (Interrupt set-pending bit) 5 6 read-write CRYPTO_IRQn CRYPTO_IRQn (Interrupt set-pending bit) 6 7 read-write DCDC_IRQn DCDC_IRQn (Interrupt set-pending bit) 29 30 read-write DMA_IRQn DMA_IRQn (Interrupt set-pending bit) 26 27 read-write FTDF_GEN_IRQn FTDF_GEN_IRQn (Interrupt set-pending bit) 3 4 read-write FTDF_WAKEUP_IRQn FTDF_WAKEUP_IRQn (Interrupt set-pending bit) 2 3 read-write I2C2_IRQn I2C2_IRQn (Interrupt set-pending bit) 11 12 read-write I2C_IRQn I2C_IRQn (Interrupt set-pending bit) 10 11 read-write IRGEN_IRQn IRGEN_IRQn (Interrupt set-pending bit) 16 17 read-write KEYBRD_IRQn KEYBRD_IRQn (Interrupt set-pending bit) 15 16 read-write MRM_IRQn MRM_IRQn (Interrupt set-pending bit) 7 8 read-write PCM_IRQn PCM_IRQn (Interrupt set-pending bit) 22 23 read-write QUADEC_IRQn QUADEC_IRQn (Interrupt set-pending bit) 20 21 read-write RFCAL_IRQn RFCAL_IRQn (Interrupt set-pending bit) 4 5 read-write RF_DIAG_IRQn RF_DIAG_IRQn (Interrupt set-pending bit) 27 28 read-write Rsvd__irq__n Rsvd__irq__n (Reserved) 31 32 read-write SPI2_IRQn SPI2_IRQn (Interrupt set-pending bit) 13 14 read-write SPI_IRQn SPI_IRQn (Interrupt set-pending bit) 12 13 read-write SRC_IN_IRQn SRC_IN_IRQn (Interrupt set-pending bit) 23 24 read-write SRC_OUT_IRQn SRC_OUT_IRQn (Interrupt set-pending bit) 24 25 read-write SWTIM0_IRQn SWTIM0_IRQn (Interrupt set-pending bit) 18 19 read-write SWTIM1_IRQn SWTIM1_IRQn (Interrupt set-pending bit) 19 20 read-write TRNG_IRQn TRNG_IRQn (Interrupt set-pending bit) 28 29 read-write UART2_IRQn UART2_IRQn (Interrupt set-pending bit) 9 10 read-write UART_IRQn UART_IRQn (Interrupt set-pending bit) 8 9 read-write USB_IRQn USB_IRQn (Interrupt set-pending bit) 21 22 read-write VBUS_IRQn VBUS_IRQn (Interrupt set-pending bit) 25 26 read-write WKUP_GPIO_IRQn WKUP_GPIO_IRQn (Interrupt set-pending bit) 17 18 read-write XTAL16RDY_IRQn XTAL16RDY_IRQn (Interrupt set-pending bit) 30 31 read-write OTPC OTPC registers Peripheral_Registers 0x0 0x0 0x24 registers n AHBADR_REG AHB master start address 0x18 32 read-write n 0x0 0x0 OTPC_AHBADR It is the AHB address used by the AHB master interface of the controller (the bits [15:2]). The bits [1:0] of the address are considered always as equal to zero. The value of the register remains unchanged, by the internal logic of the controller. 2 16 read-write CELADR_REG OTP cell start address 0x1C 32 read-write n 0x0 0x0 OTPC_CELADR Defines a word address inside the OTP cell that will be used during the AREAD mode and the OTP mirroring. 0 13 read-write MODE_REG Mode register 0x0 32 read-write n 0x0 0x0 OTPC_MODE_HT_MARG_EN Defines the temperature condition under which is performed a margin read. It affects only the initial margin read (RINI mode) and the programming verification margin read (PVFY). 0 : Regular temperature condition (less than 85°C) 1 : High temperature condition (85°C or more) The value of this configuration field can be modified only when the controller is in an inactive mode (DSTBY or STBY). The selection will take effect at the next PVFY or RINI mode that will be enabled. The READ mode is not affected by the setting of this configuration bit. 5 6 read-write OTPC_MODE_MODE Defines the mode of operation of the OTPC controller. The encoding of the modes is as follows: 0x0: DSTBY. The OTP memory is in deep standby mode (power supply ON and internal LDO OFF). 0x1: STBY. The OTP memory is powered (power supply ON and internal LDO ON, but is not selected). 0x2: READ. The OTP memory is in the normal read mode. 0x3: PROG. The OTP memory is in programming mode. 0x4: PVFY. The OTP memory is in programming verification mode (margin read after programming). 0x5: RINI. The OTP memory is in initial read mode (initial margin read). 0x6: AREAD. Copying of data from the OTP memory to a system RAM by using the internal DMA. See also the registers OTPC_AHBADR_REG, OTPC_CELADR_REG and OTPC_NWORDS_REG. Whenever the OTPC_MODE_REG[MODE] is changing, the status bit OTPC_STAT_REG[OTPC_STAT_MRDY] gets the value zero. The new mode will be ready for use when the OTPC_STAT_MRDY become again 1. During the mode transition the OTPC_MODE_REG[MODE] become read only. Do not try to use or change any function of the controller until the OTPC_STAT_MRDY bit to become equal to 1. The data transferring that is performed by using the AREAD mode is completed when OTPC_STAT_MRDY becomes again 1. The mode change automatically to DSTBY with the completion of the transfer. 0 3 read-write OTPC_MODE_PRG_SEL Defines the part of the OTP cell that is programmed by the controller during the PROG mode, for each program request that is applied. 0x0 : Both normal and redundancy arrays are programmed. This is the normal way of programming. 0x1 : Only the normal array is programmed. 0x2 : Only the redundancy array is programmed. 0x3 : Reserved The value of this configuration field can be modified only when the controller is in an inactive mode (DSTBY or STBY). The setting will take effect when will be enabled again the PROG mode. 6 8 read-write OTPC_MODE_USE_TST_ROW Selects the memory area of the OTP cell that will be used. 0 - Uses the main memory area of the OTP cell 1 - Uses the test row of the OTP cell The value of this configuration field can be modified only when the controller is in an inactive mode (DSTBY or STBY). The selection will take effect at the next programming or reading mode that will be enabled. 4 5 read-write NWORDS_REG Number of words 0x20 32 read-write n 0x0 0x0 OTPC_NWORDS The number of words (minus one) that will be copied by the AREAD mode. During mirroring, this register reflects the amount of data that will be copied. 0 13 read-write PADDR_REG The address of the word that will be programmed, when the PROG mode is used. 0x8 32 read-write n 0x0 0x0 OTPC_PADDR The OTPC_PADDR_REG and the OTPC_PWORD_REG consist the PBUF buffer that keeps the information that will be programmed in the OTP, by using the PROG mode. The PBUF holds the address (OTPC_PADDR_REG) and the data (OTPC_PWORD_REG) of each of the programming requests that are applied in the OTP memory. The OTPC_PADDR_REG refers to a word address. The OTPC_PADDR_REG has to be writen after the OTP_PWORD_REG and only if the OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY]=1. The register is read only for as long the PBUF is not empty (OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY]=0). A writting to the OTPC_PADDR_REG triggers the controller to start the programming procedure (only if the PROG mode is active). 0 13 read-write PWORD_REG The 32-bit word that will be programmed, when the PROG mode is used. 0xC 32 read-write n 0x0 0x0 OTPC_PWORD The OTPC_PADDR_REG and the OTPC_PWORD_REG consist the PBUF buffer that keeps the information that will be programmed in the OTP memory, by using the PROG mode. The PBUF holds the address (OTPC_PADDR_REG) and the data (OTPC_PWORD_REG) of each of the programming requests that are applied in the OTP memory. The OTP_PWORD_REG must be written before the OTPC_PADDR_REG and only if OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY] = 1. The register is read only for as long the PBUF is not empty (OTPC_STAT_REG[OTPC_STAT_PBUF_EMPTY]=0). 0 32 read-write STAT_REG Status register 0x4 32 read-write n 0x0 0x0 OTPC_STAT_MRDY Indicates the progress of the transition from a mode of operation to a new mode of operation. 0 : There is a transition in progress in a new mode of operation . Wait until the transition to be completed. 1 : The transition to the new mode of operation has been completed. The function that has been enabled by the new mode can be used. A new mode can be applied. This status bit gets the value zero every time where the OTPC_MODE_REG[MODE] is changing. Do not try to use or change any function of the controller until this status bit to become equal to 1. 2 3 read-only OTPC_STAT_PBUF_EMPTY Indicates the status of the programming buffer (PBUF). 0 : The PBUF contains the address and the data of a programming request. The OTPC_PADDR_REG and the OTPC_PWORD_REG should not be written as long as this status bit is zero. 1 : The PBUF is empty and a new programming request can be registered in the PBUF by using the OTPC_PADDR_REG and the OTPC_PWORD_REG registers. This status bit gets the value zero every time where a programming is triggered by the OTPC_PADDR_REG (only if the PROG mode is active). 1 2 read-only OTPC_STAT_PRDY Indicates the state of the programming process. 0: The controller is busy. A programming is in progress. 1: The logic which performs programming is idle. 0 1 read-only TIM1_REG Various timing parameters of the OTP cell. 0x10 32 read-write n 0x0 0x0 OTPC_TIM1_CC_T_1US The number of hclk_c clock periods (minus one) that give a time interval equal to 1us. This setting affects all the timing parameters that refer to microseconds, due to that defines the correspondence of a microsecond to a number of hclk_c clock cycles. 0 7 read-write OTPC_TIM1_CC_T_20NS The number of hclk_c clock periods (minus one) that give a time interval that is at least higher than 20 ns. 8 10 read-write OTPC_TIM1_CC_T_RD The number of hclk_c clock periods (minus one) that give a time interval at least higher than 60ns. This timing parameter refers to the access time of the OTP memory. 12 15 read-write OTPC_TIM1_US_T_CS The number of microseconds (minus one) that are required after the selection of the OTP memory, until to be ready for any kind of read. It must be at least 10us. 20 24 read-write OTPC_TIM1_US_T_CSP The number of microseconds (minus one) that are required after the selection of the OTP memory, until to be ready for programming. It must be : - at least 10us - no more than 100us 24 31 read-write OTPC_TIM1_US_T_PL The number of microseconds (minus one) that are required until to be enabled the LDO of the OTP. It must be at least 10us. 16 20 read-write TIM2_REG Various timing parameters of the OTP cell. 0x14 32 read-write n 0x0 0x0 OTPC_TIM2_US_ADD_CC_EN Adds an additional hclk_c clock cycle at all the time intervals that count in microseconds. 0 : The extra hclk_c clock cycle is not applied 1 : The extra hclk_c clock cycle is applied 31 32 read-write OTPC_TIM2_US_T_PPH The number of microseconds (minus one) that are required after the last programming pulse and before to be disabled the programming mode in the OTP memory. It must be: - at least 5us - no more than 20us 24 29 read-write OTPC_TIM2_US_T_PPR The number of microseconds (minus one) for recovery after a programming sequence. It must be : - at least 5us - no more than 100us 8 15 read-write OTPC_TIM2_US_T_PPS The number of microseconds (minus one) that are required after the enabling of the programming in the OTP memory and before to be applied the first programming pulse. It must be : - at least 5us - no more than 20us 16 21 read-write OTPC_TIM2_US_T_PW The number of microseconds (minus one) that lasts the programming of each bit. It must be : - at least 10us - no more than 20us 0 5 read-write OTPC_TIM2_US_T_PWI The number of microseconds (minus one) between two consecutive programming pulses. It must be : - at least 1us - no more than 5us 5 8 read-write OTPC_TIM2_US_T_SAS The number of microseconds (minus one) that are required after the exit from the deep sleep standby mode and before to become ready to enter in an active mode (reading or programming). It must be at least 2us. 29 31 read-write OTPC_TIM2_US_T_VDS The number of microseconds (minus one) that are required after the enabling of the power supply of the OTP memory and before to become ready for the enabling of the internal LDO. It must be at least 1us. 21 24 read-write PATCH PATCH registers Peripheral_Registers 0x0 0x0 0xD0 registers n ADDR0_REG 0x20 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR10_REG 0x70 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR11_REG 0x78 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR12_REG 0x80 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR13_REG 0x88 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR14_REG 0x90 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR15_REG 0x98 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR16_REG 0xA0 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR17_REG 0xA8 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR18_REG 0xB0 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR19_REG 0xB8 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR1_REG 0x28 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR20_REG 0xC0 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_D 2 18 read-write ADDR21_REG 0xC8 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_D 2 18 read-write ADDR2_REG 0x30 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR3_REG 0x38 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR4_REG 0x40 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR5_REG 0x48 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR6_REG 0x50 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR7_REG 0x58 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR8_REG 0x60 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write ADDR9_REG 0x68 32 read-write n 0x0 0x0 PATCH_ADDR_19 19 20 read-write PATCH_ADDR_C 1 18 read-write DATA20_REG 0xC4 32 read-write n 0x0 0x0 PATCH_DATA 0 32 read-write DATA21_REG 0xCC 32 read-write n 0x0 0x0 PATCH_DATA 0 32 read-write VALID_REG 0x0 32 read-write n 0x0 0x0 PATCH_VALID 0 22 read-write QUADEC QUADEC registers Peripheral_Registers 0x0 0x0 0xE registers n QDEC_CLOCKDIV_REG Clock divider register 0x6 16 read-write n 0x0 0x0 QDEC_CLOCKDIV Contains the number of the input clock cycles minus one, that are required to generate one logic clock cycle. Clock divider is bypassed when system runs at LP_CLK 0 10 read-write QDEC_PRESCALER_EN 0 = no prescaler enabled 1 = in sleep and active mode, quadrature clock is divided by 2 10 11 read-write QDEC_CTRL2_REG Quad Decoder port selection register 0x8 16 read-write n 0x0 0x0 QDEC_CHX_EVENT_MODE 0 = Normal quadrature counting 1 = Counts rising and falling edge of both ports (if both ports change at the same time, counter increases by 1) 9 10 read-write QDEC_CHX_PORT_SEL Defines which GPIOs are mapped on Channel X 0: none 1: P0[2] -> CHX_A, P0[5] -> CHX_B 2: P0[1] -> CHX_A, P0[4] -> CHX_B 3: P0[3] -> CHX_A, P0[10] -> CHX_B 4: P0[6] -> CHX_A, P0[7] -> CHX_B 5: P0[8] -> CHX_A, P0[9] -> CHX_B 6: P0[0] -> CHX_A, P0[11] -> CHX_B 7: none 0 3 read-write QDEC_CHY_EVENT_MODE 0 = Normal quadrature counting 1 = Counts rising and falling edge of both ports (if both ports change at the same time, counter increases by 1) 10 11 read-write QDEC_CHY_PORT_SEL Defines which GPIOs are mapped on Channel Y 0: none 1: P0[2] -> CHY_A, P0[5] -> CHY_B 2: P0[1] -> CHY_A, P0[4] -> CHY_B 3: P0[3] -> CHY_A, P0[10] -> CHY_B 4: P0[6] -> CHY_A, P0[7] -> CHY_B 5: P0[8] -> CHY_A, P0[9] -> CHY_B 6: P0[0] -> CHY_A, P0[11] -> CHY_B 7: none 3 6 read-write QDEC_CHZ_EVENT_MODE 0 = Normal quadrature counting 1 = Counts rising and falling edge of both ports (if both ports change at the same time, counter increases by 1) 11 12 read-write QDEC_CHZ_PORT_SEL Defines which GPIOs are mapped on Channel Z 0: none 1: P0[2] -> CHZ_A, P0[5] -> CHZ_B 2: P0[1] -> CHZ_A, P0[4] -> CHZ_B 3: P0[3] -> CHZ_A, P0[10] -> CHZ_B 4: P0[6] -> CHZ_A, P0[7] -> CHZ_B 5: P0[8] -> CHZ_A, P0[9] -> CHZ_B 6: P0[0] -> CHZ_A, P0[11] -> CHZ_B 7: none 6 9 read-write QDEC_CTRL_REG Quad Decoder control register 0x0 16 read-write n 0x0 0x0 QDEC_EVENT_CNT_CLR Writing 1 QDEC_EVENT_CNT_REG is cleared 1 2 read-write QDEC_IRQ_ENABLE 0 = interrupt is masked 1 = interrupt is enabled 0 1 read-write QDEC_IRQ_STATUS 1 = Interrupt is occured. 0 = No interrupt pending Write 1 will clear the pending interrupt 2 3 read-write QDEC_IRQ_THRES Defines the number of events on either counter (X or Y or Z) that need to be reached before an interrupt is generated. Events are equal to QDEC_IRQ_THRES+1. 3 11 read-write QDEC_EVENT_CNT_REG Event counter register 0xC 16 read-write n 0x0 0x0 QDEC_EVENT_CNT Gives the number of events at all channels. 0 8 read-only QDEC_XCNT_REG Counter value of the X Axis 0x2 16 read-write n 0x0 0x0 QDEC_X_CNT Contains a signed value of the events. Zero when channel is disabled 0 16 read-only QDEC_YCNT_REG Counter value of the Y Axis 0x4 16 read-write n 0x0 0x0 QDEC_Y_CNT Contains a signed value of the events. Zero when channel is disabled 0 16 read-only QDEC_ZCNT_REG Counter value of the Z Axis 0xA 16 read-write n 0x0 0x0 QDEC_Z_CNT Contains a signed value of the events. Zero when channel is disabled 0 16 read-only RFCU RFCU registers Peripheral_Registers 0x0 0x0 0xBC registers n RF_ADCI_DC_OFFSET_REG 0x28 32 read-write n 0x0 0x0 ADC_OFFN_I_RD 9 18 read-only ADC_OFFP_I_RD 0 9 read-only RF_ADCQ_DC_OFFSET_REG 0x2C 32 read-write n 0x0 0x0 ADC_OFFN_Q_RD 9 18 read-only ADC_OFFP_Q_RD 0 9 read-only RF_ADC_CTRL1_REG 0x40 32 read-write n 0x0 0x0 ADC_DC_OFFSET_SEL 0 1 read-write ADC_MUTE 13 14 read-write ADC_SIGN 14 15 read-write RF_ADC_CTRL2_REG 0x44 32 read-write n 0x0 0x0 ADC_OFFN_I_WR 9 18 read-write ADC_OFFP_I_WR 0 9 read-write RF_ADC_CTRL3_REG 0x48 32 read-write n 0x0 0x0 ADC_OFFN_Q_WR 9 18 read-write ADC_OFFP_Q_WR 0 9 read-write RF_ADPLLDIG_CTRL_REG 0xC 32 read-write n 0x0 0x0 OPENLOOP_RDY_SEL 0 1 read-write OPENLOOP_RDY_WR 1 2 read-write PWR_SW_TIM_CTRL 4 7 read-write RF_ADPLLDIG_RFMON_CTRL_REG 0xA0 32 read-write n 0x0 0x0 ADPLLDIG_RFMON_MUX_SEL 1 4 read-write ADPLLDIG_RFMON_SPARE 4 8 read-write ADPLLDIG_SYNC_CLK_INV 0 1 read-write RF_AGC_EXT_LUT_REG 0x10 32 read-write n 0x0 0x0 AGC_EXT_LUT 0 10 read-write RF_ATTR_REG 0x0 32 read-write n 0x0 0x0 IFF_POLARITY 3 4 read-write PA_POWER_SETTING 24 28 read-write RF_BIAS 8 12 read-write TIA_BIAS 12 13 read-write RF_CALSTATE_REG 0x14 32 read-write n 0x0 0x0 CALSTATE 0 4 read-only RF_CAL_CTRL_REG 0x20 32 read-write n 0x0 0x0 DC_OFFSET_CAL_DIS 4 5 read-write EO_CAL 1 2 read-only RF_CAL_CTRL_SPARE 2 3 read-write SO_CAL 0 1 write-only RF_DIAGIRQ_CTRL_REG 0xB0 32 read-write n 0x0 0x0 DIAG_BUS0_BIT_SEL 3 6 read-write DIAG_BUS0_EDGE_SEL 6 7 read-write DIAG_BUS0_IRQ_MASK 0 1 read-write DIAG_BUS0_SEL 1 3 read-write DIAG_BUS1_BIT_SEL 11 14 read-write DIAG_BUS1_EDGE_SEL 14 15 read-write DIAG_BUS1_IRQ_MASK 8 9 read-write DIAG_BUS1_SEL 9 11 read-write DIAG_BUS2_BIT_SEL 19 22 read-write DIAG_BUS2_EDGE_SEL 22 23 read-write DIAG_BUS2_IRQ_MASK 16 17 read-write DIAG_BUS2_SEL 17 19 read-write DIAG_BUS3_BIT_SEL 27 30 read-write DIAG_BUS3_EDGE_SEL 30 31 read-write DIAG_BUS3_IRQ_MASK 24 25 read-write DIAG_BUS3_SEL 25 27 read-write RF_DIAGIRQ_STAT_REG 0xB4 32 read-write n 0x0 0x0 DIAGIRQ_STAT 0 4 read-only RF_IFF_CTRL_REG 0x3C 32 read-write n 0x0 0x0 IFF_COMPLEX_DIS 12 13 read-write IFF_DCOC_DAC_DIS 5 6 read-write IFF_DCOC_DAC_REFCUR_CTRL 13 15 read-write IF_CAL_TRIM 0 2 read-write IF_MUTE 4 5 read-write RF_IFF_CTRL_SPARE 6 12 read-write RF_IO_CTRL_REG 0x74 32 read-write n 0x0 0x0 RFIO_TUNE_CAP_TRIM_RX 0 4 read-write RFIO_TUNE_CAP_TRIM_TX 8 12 read-write RF_IRQ_CTRL_REG 0x24 32 read-write n 0x0 0x0 EO_CAL_CLEAR 0 1 write-only RF_LDO_CTRL_REG 0xB8 32 read-write n 0x0 0x0 LDO_DCO_CONT_ENABLE 11 12 read-write LDO_DCO_HOLD_OVR_EN 29 30 read-write LDO_DCO_HOLD_OVR_VAL 28 29 read-write LDO_DCO_LEVEL 8 11 read-write LDO_DTC_CONT_ENABLE 7 8 read-write LDO_DTC_HOLD_OVR_EN 27 28 read-write LDO_DTC_HOLD_OVR_VAL 26 27 read-write LDO_DTC_LEVEL 4 7 read-write LDO_RADIO_CONT_ENABLE 3 4 read-write LDO_RADIO_HOLD_OVR_EN 25 26 read-write LDO_RADIO_HOLD_OVR_VAL 24 25 read-write LDO_RADIO_LEVEL 0 3 read-write LDO_VREF_SMPL_TIME 16 21 read-write RF_LDO_STATUS_REG 0x8 32 read-write n 0x0 0x0 ADPLLDIG_LDO_EN_RD 2 3 read-only ADPLLDIG_LDO_ZERO_EN_RD 3 4 read-only ldo_dco_en_rd 4 5 read-only ldo_dco_vref_hold_rd 7 8 read-only ldo_dtc_en_rd 5 6 read-only ldo_dtc_vref_hold_rd 8 9 read-only ldo_radio_vref_hold_rd 6 7 read-only RADIO_LDO_EN_RD 0 1 read-only RADIO_LDO_ZERO_EN_RD 1 2 read-only RF_LDO_VREF_SEL_REG 0x58 32 read-write n 0x0 0x0 RF_LDO_DCO_VREF_SEL 2 3 read-write RF_LDO_DTC_VREF_SEL 1 2 read-write RF_LDO_RADIO_VREF_SEL 0 1 read-write RF_LNA_CTRL1_REG 0x78 32 read-write n 0x0 0x0 LNA_TRIM_GAIN0_HP 0 5 read-write LNA_TRIM_GAIN1_HP 5 10 read-write LNA_TRIM_GAIN2_HP 10 15 read-write LNA_TRIM_GAIN3_HP 15 20 read-write LNA_TRIM_GAIN4_HP 20 25 read-write RF_LNA_CTRL2_REG 0x7C 32 read-write n 0x0 0x0 LNA_TRIM_GAIN0_LP 0 5 read-write LNA_TRIM_GAIN1_LP 5 10 read-write LNA_TRIM_GAIN2_LP 10 15 read-write LNA_TRIM_GAIN3_LP 15 20 read-write LNA_TRIM_GAIN4_LP 20 25 read-write RF_LNA_CTRL3_REG 0x80 32 read-write n 0x0 0x0 LNA_MODE_GAIN0_LP 4 6 read-write LNA_MODE_GAIN1_LP 8 10 read-write LNA_MODE_GAIN2_LP 12 14 read-write LNA_MODE_GAIN3_LP 16 18 read-write LNA_MODE_GAIN4_LP 20 22 read-write LNA_SPARE 24 26 read-write LNA_TRIM_CASC 0 3 read-write RF_MIXER_CTRL1_REG 0x64 32 read-write n 0x0 0x0 MIXER_IP2_DAC_I_TRIM 0 9 read-write MIXER_IP2_DAC_Q_TRIM 16 25 read-write RF_MIXER_CTRL2_REG 0x68 32 read-write n 0x0 0x0 MIX_CAL_CAP_WR_1M 0 4 read-write MIX_CAL_CAP_WR_2M 8 12 read-write MIX_CAL_SELECT 16 17 read-write RF_OVERRULE_REG 0xAC 32 read-write n 0x0 0x0 RX_EN_OVR 2 4 read-write TX_EN_OVR 0 2 read-write RF_PA_CTRL_REG 0x4C 32 read-write n 0x0 0x0 PA_RAMP_STEP_SPEED 8 10 read-write TRIM_DUTY_NEG 3 6 read-write TRIM_DUTY_POS 0 3 read-write RF_RADIO_INIT_REG 0x4 32 read-write n 0x0 0x0 ADPLLDIG_HCLK_DIS 17 18 read-write ADPLLDIG_HCLK_EN 9 10 read-write ADPLLDIG_HRESET_N 8 9 read-write ADPLLDIG_LDO_EN_SEL 4 5 read-write ADPLLDIG_LDO_EN_WR 5 6 read-write ADPLLDIG_PWR_SW1_EN 3 4 read-write RADIO_INIT_AUTOCLEAR 24 25 read-write RADIO_LDO_EN 0 1 read-write RADIO_LDO_EN_SEL 1 2 read-write RADIO_LDO_EN_WR 2 3 read-write RADIO_REGS_RDY 16 17 read-write RF_RFCU_CTRL_REG 0xA8 32 read-write n 0x0 0x0 RF_RFCU_CLK_DIV 0 1 read-write RF_SCAN_FEEDBACK_REG 0x18 32 read-write n 0x0 0x0 RF_SPARE_REG 0x30 32 read-write n 0x0 0x0 RF_SPARE_BITS 0 16 read-write RF_SPARE_BITS_HV 16 24 read-write RF_SPARE_IN 24 28 read-only RF_SPARE_IN_EN 28 29 read-write RFCU_POWER RFCU_POWER registers Peripheral_Registers 0x0 0x0 0x190 registers n RF_ALWAYS_EN1_REG 0x180 32 read-write n 0x0 0x0 ALW_EN_ADC_CLK_EN 26 27 read-write ALW_EN_ADC_EN 27 28 read-write ALW_EN_ADPLLDIG_EN 31 32 read-write ALW_EN_ADPLLDIG_LDO_ACTIVERDY 11 12 read-write ALW_EN_ADPLLDIG_LDO_LP 12 13 read-write ALW_EN_ADPLLDIG_RST 30 31 read-write ALW_EN_ADPLL_CLK_EN 29 30 read-write ALW_EN_ADPLL_DCO_EN 28 29 read-write ALW_EN_ADPLL_DCO_LDO_EN 8 9 read-write ALW_EN_ADPLL_DTC_LDO_EN 7 8 read-write ALW_EN_ADPLL_TDC_LDO_EN 6 7 read-write ALW_EN_IFFADC_LDO_EN 5 6 read-write ALW_EN_IFF_BIAS_SH_OPEN 25 26 read-write ALW_EN_IFF_EN 24 25 read-write ALW_EN_IFF_LDO_EN 4 5 read-write ALW_EN_LDO_ZERO_EN 9 10 read-write ALW_EN_LNA_CGM_EN 21 22 read-write ALW_EN_LNA_CORE_EN 20 21 read-write ALW_EN_LNA_LDO_EN 2 3 read-write ALW_EN_LNA_LDO_ZERO 10 11 read-write ALW_EN_MIX_BIAS_SH_OPEN 23 24 read-write ALW_EN_MIX_EN 22 23 read-write ALW_EN_MIX_LDO_EN 3 4 read-write ALW_EN_PA_EN 19 20 read-write ALW_EN_PA_LDO_EN 1 2 read-write ALW_EN_PA_RAMP_EN 18 19 read-write ALW_EN_RFIO_BIAS_EN 16 17 read-write ALW_EN_RFIO_BIAS_SH_OPEN 17 18 read-write ALW_EN_RFIO_LDO_EN 0 1 read-write ALW_EN_RFIO_RX_EN 13 14 read-write ALW_EN_RFIO_TX_EN 14 15 read-write ALW_EN_RFIO_TX_HARM_EN 15 16 read-write RF_ALWAYS_EN2_REG 0x184 32 read-write n 0x0 0x0 ALW_EN_ADPLLDIG_RX_EN 0 1 read-write ALW_EN_ADPLL_LOBUF_PA_EN 2 3 read-write ALW_EN_ADPLL_PAIN_EN 1 2 read-write ALW_EN_ADPLL_RDY_FOR_DIV 9 10 read-write ALW_EN_CAL_EN 3 4 read-write ALW_EN_DEM_AGC_UNFREEZE_EN 6 7 read-write ALW_EN_DEM_DC_PARCAL_EN 5 6 read-write ALW_EN_DEM_EN 4 5 read-write ALW_EN_DEM_SIGDETECT_EN 7 8 read-write ALW_EN_PHY_RDY4BS 8 9 read-write ALW_EN_SPARE1 10 11 read-write ALW_EN_SPARE2 11 12 read-write ALW_EN_SPARE3 12 13 read-write ALW_EN_SPARE4 13 14 read-write ALW_EN_SPARE5 14 15 read-write RF_CNTRL_TIMER_10_REG 0x124 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_11_REG 0x128 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_12_REG 0x12C 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_13_REG 0x130 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_14_REG 0x134 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_15_REG 0x138 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_16_REG 0x13C 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_17_REG 0x140 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_18_REG 0x144 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_19_REG 0x148 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_1_REG 0x100 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_20_REG 0x14C 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_21_REG 0x150 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_22_REG 0x154 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_23_REG 0x158 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_24_REG 0x15C 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_25_REG 0x160 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_26_REG 0x164 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_27_REG 0x168 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_28_REG 0x16C 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_29_REG 0x170 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_2_REG 0x104 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_30_REG 0x174 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_31_REG 0x178 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_3_REG 0x108 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_4_REG 0x10C 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_5_REG 0x110 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_6_REG 0x114 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_7_REG 0x118 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_8_REG 0x11C 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_CNTRL_TIMER_9_REG 0x120 32 read-write n 0x0 0x0 RESET_OFFSET 8 16 read-write SET_OFFSET 0 8 read-write RF_ENABLE_CONFIG0_REG 0x0 32 read-write n 0x0 0x0 RFIO_LDO_EN_DCF_RX 0 5 read-write RFIO_LDO_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG10_REG 0x28 32 read-write n 0x0 0x0 LNA_LDO_ZERO_DCF_RX 0 5 read-write LNA_LDO_ZERO_DCF_TX 5 10 read-write RF_ENABLE_CONFIG11_REG 0x2C 32 read-write n 0x0 0x0 ADPLLDIG_LDO_ACTIVERDY_DCF_RX 0 5 read-write ADPLLDIG_LDO_ACTIVERDY_DCF_TX 5 10 read-write RF_ENABLE_CONFIG12_REG 0x30 32 read-write n 0x0 0x0 ADPLLDIG_LDO_LP_DCF_RX 0 5 read-write ADPLLDIG_LDO_LP_DCF_TX 5 10 read-write RF_ENABLE_CONFIG13_REG 0x34 32 read-write n 0x0 0x0 RFIO_RX_EN_DCF_RX 0 5 read-write RFIO_RX_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG14_REG 0x38 32 read-write n 0x0 0x0 RFIO_TX_EN_DCF_RX 0 5 read-write RFIO_TX_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG15_REG 0x3C 32 read-write n 0x0 0x0 RFIO_TX_HARM_EN_DCF_RX 0 5 read-write RFIO_TX_HARM_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG16_REG 0x40 32 read-write n 0x0 0x0 RFIO_BIAS_EN_DCF_RX 0 5 read-write RFIO_BIAS_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG17_REG 0x44 32 read-write n 0x0 0x0 RFIO_BIAS_SH_OPEN_DCF_RX 0 5 read-write RFIO_BIAS_SH_OPEN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG18_REG 0x48 32 read-write n 0x0 0x0 PA_RAMP_EN_DCF_RX 0 5 read-write PA_RAMP_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG19_REG 0x4C 32 read-write n 0x0 0x0 PA_EN_DCF_RX 0 5 read-write PA_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG1_REG 0x4 32 read-write n 0x0 0x0 PA_LDO_EN_DCF_RX 0 5 read-write PA_LDO_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG20_REG 0x50 32 read-write n 0x0 0x0 LNA_CORE_EN_DCF_RX 0 5 read-write LNA_CORE_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG21_REG 0x54 32 read-write n 0x0 0x0 LNA_CGM_EN_DCF_RX 0 5 read-write LNA_CGM_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG22_REG 0x58 32 read-write n 0x0 0x0 MIX_EN_DCF_RX 0 5 read-write MIX_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG23_REG 0x5C 32 read-write n 0x0 0x0 MIX_BIAS_SH_OPEN_DCF_RX 0 5 read-write MIX_BIAS_SH_OPEN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG24_REG 0x60 32 read-write n 0x0 0x0 IFF_EN_DCF_RX 0 5 read-write IFF_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG25_REG 0x64 32 read-write n 0x0 0x0 IFF_BIAS_SH_OPEN_DCF_RX 0 5 read-write IFF_BIAS_SH_OPEN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG26_REG 0x68 32 read-write n 0x0 0x0 ADC_CLK_EN_DCF_RX 0 5 read-write ADC_CLK_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG27_REG 0x6C 32 read-write n 0x0 0x0 ADC_EN_DCF_RX 0 5 read-write ADC_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG28_REG 0x70 32 read-write n 0x0 0x0 ADPLL_DCO_EN_DCF_RX 0 5 read-write ADPLL_DCO_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG29_REG 0x74 32 read-write n 0x0 0x0 ADPLL_CLK_EN_DCF_RX 0 5 read-write ADPLL_CLK_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG2_REG 0x8 32 read-write n 0x0 0x0 LNA_LDO_EN_DCF_RX 0 5 read-write LNA_LDO_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG30_REG 0x78 32 read-write n 0x0 0x0 ADPLLDIG_RST_DCF_RX 0 5 read-write ADPLLDIG_RST_DCF_TX 5 10 read-write RF_ENABLE_CONFIG31_REG 0x7C 32 read-write n 0x0 0x0 ADPLLDIG_EN_DCF_RX 0 5 read-write ADPLLDIG_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG32_REG 0x80 32 read-write n 0x0 0x0 ADPLLDIG_RX_EN_DCF_RX 0 5 read-write ADPLLDIG_RX_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG33_REG 0x84 32 read-write n 0x0 0x0 ADPLLDIG_PAIN_EN_DCF_RX 0 5 read-write ADPLLDIG_PAIN_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG34_REG 0x88 32 read-write n 0x0 0x0 ADPLL_LOBUF_PA_EN_DCF_RX 0 5 read-write ADPLL_LOBUF_PA_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG35_REG 0x8C 32 read-write n 0x0 0x0 CAL_EN_DCF_RX 0 5 read-write CAL_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG36_REG 0x90 32 read-write n 0x0 0x0 DEM_EN_DCF_RX 0 5 read-write DEM_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG37_REG 0x94 32 read-write n 0x0 0x0 DEM_DC_PARCAL_EN_DCF_RX 0 5 read-write SPARE_DEM_DC_PARCAL_DCF_TX 5 10 read-write RF_ENABLE_CONFIG38_REG 0x98 32 read-write n 0x0 0x0 DEM_AGC_UNFREEZE_EN_DCF_RX 0 5 read-write SPARE_DEM_AGC_UNFREEZE_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG39_REG 0x9C 32 read-write n 0x0 0x0 DEM_SIGDETECT_EN_DCF_RX 0 5 read-write SPARE_DEM_SIGDETECT_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG3_REG 0xC 32 read-write n 0x0 0x0 MIX_LDO_EN_DCF_RX 0 5 read-write MIX_LDO_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG40_REG 0xA0 32 read-write n 0x0 0x0 PHY_RDY4BS_DCF_RX 0 5 read-write PHY_RDY4BS_DCF_TX 5 10 read-write RF_ENABLE_CONFIG41_REG 0xA4 32 read-write n 0x0 0x0 ADPLL_RDY_FOR_DIV_DCF_RX 0 5 read-write ADPLL_RDY_FOR_DIV_DCF_TX 5 10 read-write RF_ENABLE_CONFIG42_REG 0xA8 32 read-write n 0x0 0x0 SPARE1_DCF_RX 0 5 read-write SPARE1_DCF_TX 5 10 read-write RF_ENABLE_CONFIG43_REG 0xAC 32 read-write n 0x0 0x0 SPARE2_DCF_RX 0 5 read-write SPARE2_DCF_TX 5 10 read-write RF_ENABLE_CONFIG44_REG 0xB0 32 read-write n 0x0 0x0 SPARE3_DCF_RX 0 5 read-write SPARE3_DCF_TX 5 10 read-write RF_ENABLE_CONFIG45_REG 0xB4 32 read-write n 0x0 0x0 SPARE4_DCF_RX 0 5 read-write SPARE4_DCF_TX 5 10 read-write RF_ENABLE_CONFIG46_REG 0xB8 32 read-write n 0x0 0x0 SPARE5_DCF_RX 0 5 read-write SPARE5_DCF_TX 5 10 read-write RF_ENABLE_CONFIG4_REG 0x10 32 read-write n 0x0 0x0 IFF_LDO_EN_DCF_RX 0 5 read-write IFF_LDO_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG5_REG 0x14 32 read-write n 0x0 0x0 IFFADC_LDO_EN_DCF_RX 0 5 read-write IFFADC_LDO_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG6_REG 0x18 32 read-write n 0x0 0x0 ADPLL_TDC_LDO_EN_DCF_RX 0 5 read-write ADPLL_TDC_LDO_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG7_REG 0x1C 32 read-write n 0x0 0x0 ADPLL_DTC_LDO_EN_DCF_RX 0 5 read-write ADPLL_DTC_LDO_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG8_REG 0x20 32 read-write n 0x0 0x0 ADPLL_DCO_LDO_EN_DCF_RX 0 5 read-write ADPLL_DCO_LDO_EN_DCF_TX 5 10 read-write RF_ENABLE_CONFIG9_REG 0x24 32 read-write n 0x0 0x0 LDO_ZERO_EN_DCF_RX 0 5 read-write LDO_ZERO_EN_DCF_TX 5 10 read-write RF_PORT_EN_REG 0x188 32 read-write n 0x0 0x0 RF_PORT0_RX 0 1 read-write RF_PORT0_TX 1 2 read-write RF_PORT1_RX 2 3 read-write RF_PORT1_TX 3 4 read-write RF_PORT2_RX 4 5 read-write RF_PORT2_TX 5 6 read-write RF_PORT3_RX 6 7 read-write RF_PORT3_TX 7 8 read-write RF_PORT4_RX 8 9 read-write RF_PORT4_TX 9 10 read-write RF_PORT_POL_REG 0x18C 32 read-write n 0x0 0x0 RF_PORT0_POL 0 1 read-write RF_PORT1_POL 1 2 read-write RF_PORT2_POL 2 3 read-write RF_PORT3_POL 3 4 read-write RF_PORT4_POL 4 5 read-write RFMON RFMON registers Peripheral_Registers 0x0 0x0 0x16 registers n ADDR_REG AHB master start address 0x4 16 read-write n 0x0 0x0 RFMON_ADDR It is the bits [15:2] of base address that is used by the AHB master interface of the controller. Defines the AHB address from where the controller will start to stores data. The bits [1:0] of the address are considered always 0. 2 16 read-write CRV_ADDR_REG AHB master current address 0x10 16 read-write n 0x0 0x0 RFMON_CRV_ADDR It is the bits [15:2] of AHB address that will be used by the controller in the next memory access. The bits [1:0] are always 0. 2 16 read-only CRV_LEN_REG The remaining data to be transferred 0x14 16 read-write n 0x0 0x0 RFMON_CRV_LEN Indicates the number of words (minus 1) that remain to be transfered. 0 14 read-only CTRL_REG Control register 0x0 16 read-write n 0x0 0x0 RFMON_CIRC_EN Write with 1 to enable the circular mode.In circular mode the controller continuously writes data in to the memory until to be disabled by the software. The data are transferred in the circular buffer in the memory, which is defined by the RFMON_ADDR_REG and the RFMON_LEN_REG registers. The disabling of the controller is realized by writing the RFMON_PACK_EN with 0. 1 2 read-write RFMON_PACK_EN Starts the capturing of the data from the test bus 0 : There is no capturing of data. 1 : The controller captures data. Should be written with 1 in order to start the acquisition of data. If the controller is not in circular mode (RFMON_CIRC_EN = 0) and after capturing a predefined number of words (RFMON_LEN), this bit will be auto cleared. In circular mode (RFMON_CIRC_EN = 1) the RFMON_PACK_EN remains 1 until to be cleared by the software. 0 1 read-write LEN_REG Data length register 0x8 16 read-write n 0x0 0x0 RFMON_LEN The number of words (minus one) that should be captured. 0 14 read-write STAT_REG Status register 0xC 16 read-write n 0x0 0x0 RFMON_ACTIVE Indicates the state of the controller. 0 : The controller is idle. 1 : The controller is active. The capturing process and/or the dma activity is in progress. The controller will be activated (RFMON_ACTIVE == 1), when RFMON_PACK_EN will be written with 1. Will return to inactive state, after the end of the capturing process (RFMON_PACK_EN==0) and the completion of the transfer of all of the data to the memory. 0 1 read-only RFMON_OFLOW_STK Indicates that during the transfer of the data, at least one overflow has detected to the fifo. 0 : The transfer completed without overflows. 1 : At least one overflow occured in the fifo. Write 1 to clear this bit. 1 2 read-write RTC RTC registers Peripheral_Registers 0x0 0x0 0x34 registers n ALARM_ENABLE_REG RTC Alarm Enable Register 0x18 32 read-write n 0x0 0x0 RTC_ALARM_DATE_EN Alarm on date enable. Enable to trigger alarm when data specified in Calendar Alarm Register (D_T and D_U) has been reached. 4 5 read-write RTC_ALARM_HOS_EN Alarm on hundredths of a second enable. Enable to trigger alarm when data specified in Time Alarm Register (H_T and H_U) has been reached. 0 1 read-write RTC_ALARM_HOUR_EN Alarm on hour enable. Enable to trigger alarm when data specified in Time Alarm Register (PM, HR_T and HR_U) has been reached. 3 4 read-write RTC_ALARM_MIN_EN Alarm on minute enable. Enable to trigger alarm when data specified in Time Alarm Register (M_T and M_U) has been reached. 2 3 read-write RTC_ALARM_MNTH_EN Alarm on month enable. Enable to trigger alarm when data specified in Calendar Alarm Register (M_T and M_U) has been reached. 5 6 read-write RTC_ALARM_SEC_EN Alarm on second enable. Enable to trigger alarm when data specified in Time Alarm Register (S_T and S_U) has been reached. 1 2 read-write CALENDAR_ALARM_REG RTC Calendar Alram Register 0x14 32 read-write n 0x0 0x0 RTC_CAL_D_T Date tens. Represented in BCD digit (0-3). 12 14 read-write RTC_CAL_D_U Date units. Represented in BCD digit (0-9). 8 12 read-write RTC_CAL_M_T Month tens. Represented in BCD digit (0-1). 7 8 read-write RTC_CAL_M_U Month units. Represented in BCD digit (0-9). 3 7 read-write CALENDAR_REG RTC Calendar Register 0xC 32 read-write n 0x0 0x0 RTC_CAL_CH The value in this register has altered since last read. Read and clear 31 32 read-write RTC_CAL_C_T Century tens. Represented in BCD digit (1-2). 28 30 read-write RTC_CAL_C_U Century units. Represented in BCD digit (0-9). 24 28 read-write RTC_CAL_D_T Date tens. Represented in BCD digit (0-3). 12 14 read-write RTC_CAL_D_U Date units. Represented in BCD digit (0-9). 8 12 read-write RTC_CAL_M_T Month tens. Represented in BCD digit (0-1). 7 8 read-write RTC_CAL_M_U Month units. Represented in BCD digit (0-9). 3 7 read-write RTC_CAL_Y_T Year tens. Represented in BCD digit (0-9). 20 24 read-write RTC_CAL_Y_U Year units. Represented in BCD digit (0-9). 16 20 read-write RTC_DAY Day of the week (arbitrary) units. Represented in BCD digit (0-7). 0 3 read-write CONTROL_REG RTC Control Register 0x0 32 read-write n 0x0 0x0 RTC_CAL_DISABLE When this field is set high the RTC stops incrementing the calendar value. 1 2 read-write RTC_TIME_DISABLE When this field is set high the RTC stops incrementing the time value. 0 1 read-write EVENT_FLAGS_REG RTC Event Flags Register 0x1C 32 read-write n 0x0 0x0 RTC_EVENT_ALRM Alarm event flag. Indicate that alarm event occurred since the last reset. 6 7 read-only RTC_EVENT_DATE Date rolls over event flag. Indicate that date rolls over event occurred since the last reset. 4 5 read-only RTC_EVENT_HOS Hundredths of a second event flag. Indicate that hundredths of a second rolls over event occurred since the last reset. 0 1 read-only RTC_EVENT_HOUR Hour rolls over event flag. Indicate that hour rolls over event occurred since the last reset. 3 4 read-only RTC_EVENT_MIN Minute rolls over event flag. Indicate that minute rolls over event occurred since the last reset. 2 3 read-only RTC_EVENT_MNTH Month rolls over event flag. Indicate that month rolls over event occurred since the last reset. 5 6 read-only RTC_EVENT_SEC Second rolls over event flag. Indicate that second rolls over event occurred since the last reset. 1 2 read-only HOUR_MODE_REG RTC Hour Mode Register 0x4 32 read-write n 0x0 0x0 RTC_HMS When this field is set high the RTC operates in 12 hour clock mode otherwise, times are in 24 hour clock format. 0 1 read-write INTERRUPT_DISABLE_REG RTC Interrupt Disable Register 0x24 32 read-write n 0x0 0x0 RTC_ALRM_INT_DIS Interrupt on alarm disable. Disable to issue the interrupt when alarm event occurred. 6 7 write-only RTC_DATE_INT_DIS Interrupt on date disable. Disable to issue the interrupt when date event occurred. 4 5 write-only RTC_HOS_INT_DIS Interrupt on hundredths of a second disable. Disable to issue the interrupt when hundredths of a second event occurred. 0 1 write-only RTC_HOUR_INT_DIS IInterrupt on hour disable. Disable to issue the interrupt when hour event occurred. 3 4 write-only RTC_MIN_INT_DIS Interrupt on minute disable. Disable to issue the interrupt when minute event occurred. 2 3 write-only RTC_MNTH_INT_DIS Interrupt on month disable. Disable to issue the interrupt when month event occurred. 5 6 write-only RTC_SEC_INT_DIS Interrupt on second disable. Disable to issue the interrupt when second event occurred. 1 2 write-only INTERRUPT_ENABLE_REG RTC Interrupt Enable Register 0x20 32 read-write n 0x0 0x0 RTC_ALRM_INT_EN Interrupt on alarm enable. Enable to issue the interrupt when alarm event occurred. 6 7 write-only RTC_DATE_INT_EN Interrupt on date enable. Enable to issue the interrupt when date event occurred. 4 5 write-only RTC_HOS_INT_EN Interrupt on hundredths of a second enable. Enable to issue the interrupt when hundredths of a second event occurred. 0 1 write-only RTC_HOUR_INT_EN Interrupt on hour enable. Enable to issue the interrupt when hour event occurred. 3 4 write-only RTC_MIN_INT_EN Interrupt on minute enable. Enable to issue the interrupt when minute event occurred. 2 3 write-only RTC_MNTH_INT_EN Interrupt on month enable. Enable to issue the interrupt when month event occurred. 5 6 write-only RTC_SEC_INT_EN Interrupt on second enable. Enable to issue the interrupt when second event occurred. 1 2 write-only INTERRUPT_MASK_REG RTC Interrupt Mask Register 0x28 32 read-write n 0x0 0x0 RTC_ALRM_INT_MSK Mask alarm interrupt. It can be cleared (set) by setting corresponding bit (ALRM) in Interrupt Enable Register (Interrupt Disable Register). 6 7 read-only RTC_DATE_INT_MSK Mask date interrupt. It can be cleared (set) by setting corresponding bit (DATE) in Interrupt Enable Register (Interrupt Disable Register). 4 5 read-only RTC_HOS_INT_MSK Mask hundredths of a second interrupt. It can be cleared (set) by setting corresponding bit (HOS) in Interrupt Enable Register (Interrupt Disable Register). 0 1 read-only RTC_HOUR_INT_MSK IMask hour interrupt. It can be cleared (set) by setting corresponding bit (HOUR) in Interrupt Enable Register (Interrupt Disable Register). 3 4 read-only RTC_MIN_INT_MSK IMask minute interrupt. It can be cleared (set) by setting corresponding bit (MIN) in Interrupt Enable Register (Interrupt Disable Register). 2 3 read-only RTC_MNTH_INT_MSK IMask month interrupt. It can be cleared (set) by setting corresponding bit (MNTH) in Interrupt Enable Register (Interrupt Disable Register). 5 6 read-only RTC_SEC_INT_MSK IMask second interrupt. It can be cleared (set) by setting corresponding bit (SEC) in Interrupt Enable Register (Interrupt Disable Register). 1 2 read-only KEEP_RTC_REG RTC Keep RTC Register 0x30 32 read-write n 0x0 0x0 RTC_KEEP Keep RTC. When high, the time and calendar registers and any other registers which directly affect or are affected by the time and calendar registers are NOT reset when software reset is applied. When low, the software reset will reset every register except the keep RTC and control registers. 0 1 read-write STATUS_REG RTC Status Register 0x2C 32 read-write n 0x0 0x0 RTC_VALID_CAL Valid Calendar. If cleared then indicates that invalid entry occurred when writing to Calendar Register. 1 2 read-only RTC_VALID_CAL_ALM Valid Calendar Alarm. If cleared then indicates that invalid entry occurred when writing to Calendar Alarm Register. 3 4 read-only RTC_VALID_TIME Valid Time. If cleared then indicates that invalid entry occurred when writing to Time Register. 0 1 read-only RTC_VALID_TIME_ALM Valid Time Alarm. If cleared then indicates that invalid entry occurred when writing to Time Alarm Register. 2 3 read-only TIME_ALARM_REG RTC Time Alarm Register 0x10 32 read-write n 0x0 0x0 RTC_TIME_HR_T Hours tens. Represented in BCD digit (0-2). 28 30 read-write RTC_TIME_HR_U Hours units. Represented in BCD digit (0-9). 24 28 read-write RTC_TIME_H_T Hundredths of a second tens. Represented in BCD digit (0-9). 4 8 read-write RTC_TIME_H_U Hundredths of a second units. Represented in BCD digit (0-9). 0 4 read-write RTC_TIME_M_T Minutes tens. Represented in BCD digit (0-5). 20 23 read-write RTC_TIME_M_U Minutes units. Represented in BCD digit (0-9). 16 20 read-write RTC_TIME_PM In 12 hour clock mode, indicates PM when set. 30 31 read-write RTC_TIME_S_T Seconds tens. Represented in BCD digit (0-9). 12 15 read-write RTC_TIME_S_U Seconds units. Represented in BCD digit (0-9). 8 12 read-write TIME_REG RTC Time Register 0x8 32 read-write n 0x0 0x0 RTC_TIME_CH The value in this register has altered since last read. Read and clear. 31 32 read-write RTC_TIME_HR_T Hours tens. Represented in BCD digit (0-2). 28 30 read-write RTC_TIME_HR_U Hours units. Represented in BCD digit (0-9). 24 28 read-write RTC_TIME_H_T Hundredths of a second tens. Represented in BCD digit (0-9). 4 8 read-write RTC_TIME_H_U Hundredths of a second units. Represented in BCD digit (0-9). 0 4 read-write RTC_TIME_M_T Minutes tens. Represented in BCD digit (0-5). 20 23 read-write RTC_TIME_M_U Minutes units. Represented in BCD digit (0-9). 16 20 read-write RTC_TIME_PM In 12 hour clock mode, indicates PM when set. 30 31 read-write RTC_TIME_S_T Seconds tens. Represented in BCD digit (0-9). 12 15 read-write RTC_TIME_S_U Seconds units. Represented in BCD digit (0-9). 8 12 read-write SCB Cortex M0 SCB registers SCB 0x0 0x0 0x29 registers n AIRCR Application interrupt and reset control register 0xC 32 read-only n 0x0 0x0 ENDIANESS Data endianness bit 15 16 read-only SYSRESETREQ System reset request 2 3 read-only VECTCLRACTIVE Reserved for Debug use 1 2 read-only VECTKEY VECTKEY[15:0] bits (Register key) 16 32 read-only VECTRESET Reserved for Debug use 0 1 read-only CCR Configuration and control register 0x14 32 read-write n 0x0 0x0 STKALIGN Configures stack alignment on exception entry 9 10 read-write UNALIGN_TRP Enables unaligned access traps 3 4 read-write CPUID CPUID base register 0x0 32 read-write n 0x0 0x0 CONSTANT CONSTANT[3:0] bits (Reads as 0xF) 16 20 read-only IMPLEMENTER IMPLEMENTER[7:0] bits (Implementer code) 24 32 read-only PARTNO PARTNO[11:0] bits (Part number of the processor core) 4 16 read-only REVISION REVISION[3:0] bits (Revision number) 0 4 read-only VARIANT VARIANT[3:0] bits (Variant number) 20 24 read-only ICSR Interrupt control and state register 0x4 32 read-write n 0x0 0x0 ISRPENDING Interrupt pending flag, excluding NMI and Faults 22 23 read-write NMIPENDSET NMI set-pending bit 31 32 read-write PENDSTCLR SysTick exception clear-pending bit 25 26 read-write PENDSTSET SysTick exception set-pending bit 26 27 read-write PENDSVCLR PendSV clear-pending bit 27 28 read-write PENDSVSET PendSV set-pending bit 28 29 read-write VECTACTIVE VECTACTIVE[5:0] bits (Active vector) 0 6 read-write VECTPENDING VECTPENDING[5:0] bits (Pending vector) 12 18 read-write SCR System control register 0x10 32 read-write n 0x0 0x0 SEVEONPEND Send event on pending bit 4 5 read-write SLEEPDEEP Controls whether the processor uses sleep or deep sleep 2 3 read-write SLEEPONEXIT Configures sleep-on-exit when returning from Handler mode to Thread mode 1 2 read-write SHPR2 System handler priority register 2 0x1C 32 read-write n 0x0 0x0 PRI_11 PRI_11[7:0] bits (Priority of system handler 11, SVCall) 24 32 read-write SHPR3 System handler priority register 3 0x20 32 read-write n 0x0 0x0 PRI_14 PRI_14[7:0] bits (Priority of system handler 14, PendSV) 16 24 read-write PRI_15 PRI_15[7:0] bits (Priority of system handler 15, SysTick exception) 24 32 read-write SPI SPI registers Peripheral_Registers 0x0 0x0 0x32 registers n CLOCK_REG Spi clock register 0x8 16 read-write n 0x0 0x0 SPI_CLK_DIV Applicable only in master mode Defines the spi clock frequency in master only mode SPI_CLK = module_clk / 2*(SPI_CLK_DIV+1) when SPI_CLK_DIV not 0x7F if SPI_CLK_DIV=0x7F then SPI_CLK=module_clk 0 7 read-write SPI_MASTER_CLK_MODE Should be always 1 7 8 read-write CONFIG_REG Spi control register 0x4 16 read-write n 0x0 0x0 SPI_MODE Define the spi mode (CPOL, CPHA) 0 = new data on falling, capture on rising, clk low in idle state 1 = new data on rising, capture on falling, Clk low in idle state 2 = new data on rising, capture on falling, Clk high in idle state 3 = new data on falling, capture on rising Clk high in idle state 0 2 read-write SPI_SLAVE_EN 0 = SPI module master mode 1 = SPI module slave mode 7 8 read-write SPI_WORD_LENGTH Define the spi word length = 1+ SPI_WORD_LENGTH (range 4 to 32) 2 7 read-write CS_CONFIG_REG Spi cs configuration register 0x24 16 read-write n 0x0 0x0 SPI_CS_SELECT Control the cs output in master mode 0 = none slave device selected 1 = selected slave device connected to GPIO with FUNC_MODE=SPI_CS0 2 = selected slave device connected to GPIO with FUNC_MODE=SPI_CS1 4 = selected slave device connected to GPIO with FUNC_MODE=GPIO 0 3 read-write CTRL_REG Spi control register 0x0 16 read-write n 0x0 0x0 SPI_CAPTURE_AT_NEXT_EDGE 0 = SPI captures data at correct clock edge 1 = SPI captures data at next clock edge. (only for Master mode and high clock) 6 7 read-write SPI_DMA_RX_EN applicable only when SPI_RX_EN=1 0 = No DMA request for RX 1 = DMA request when SPI_STATUS_RX_FULL='1' 4 5 read-write SPI_DMA_TX_EN applicable only when SPI_TX_EN=1 0 = No DMA request for TX 1 = DMA request when SPI_STATUS_TX_EMPTY='1' 3 4 read-write SPI_EN 0 = SPI module is disable 1 = SPI module is enable 0 1 read-write SPI_FIFO_RESET 0 = Fifo normal operation 1 = Fifo in reset state 5 6 read-write SPI_RX_EN 0 = RX path is disabled 1 = RX path is enabled Note: if master clk async or spi mode=1 or spi mode=3 readonly is not supported 2 3 read-write SPI_SWAP_BYTES 0 = normal operation 1 = LSB and MSB are swaped in APB interface In case of 8bit spi interface, DMA/SPI can be configured in 16bit mode to off load the bus. Enabling SPI_SWAP_BYTES bytes will read/wrte correctly 7 8 read-write SPI_TX_EN 0 = TX path is disabled 1 = TX path is enabled 1 2 read-write FIFO_CONFIG_REG Spi fifo configuration register 0xC 16 read-write n 0x0 0x0 SPI_RX_TL Receive FIFO threshold level in bytes. Control the level of bytes in fifo that triggers the RX_FULL interrupt. IRQ is occurred when fifo level is more or equal to SPI_RX_TL+1. Fifo level is from 0 to 4 4 8 read-write SPI_TX_TL Transmit FIFO threshold level in bytes. Control the level of bytes in fifo that triggers the TX_EMPTY interrupt. IRQ is occurred when fifo level is less or equal to SPI_TX_TL. Fifo level is from 0 to 4 0 4 read-write FIFO_HIGH_REG Spi TX/RX High 16bit word 0x28 16 read-write n 0x0 0x0 SPI_FIFO_HIGH RX/TX fifo data. 16 MSb when spi word is larger than 16bits This register has to be written before the SPI_FIFO_WRITE_REG This register has to be read after the SPI_FIFO_READ_REG 0 16 read-write FIFO_READ_REG Spi RX fifo read register 0x1C 16 read-write n 0x0 0x0 SPI_FIFO_READ Read from RX fifo. Read access is permit only if SPI_RX_FIFO_EMPTY=0. Returns the 16 LSb 0 16 read-only FIFO_STATUS_REG SPI RX/TX fifo status register 0x18 16 read-write n 0x0 0x0 SPI_RX_FIFO_LEVEL Gives the number of bytes in RX fifo 0 6 read-only SPI_RX_FIFO_OVFL When 1, receive data is not written to fifo because fifo was full and interrupt is generated. It clears with SPI_CTRL_REG.SPI_FIFO_RESET 14 15 read-only SPI_STATUS_RX_EMPTY 0 = RX fifo is not empty 1 = RX fifo is empty 12 13 read-only SPI_STATUS_TX_FULL 0 = TX fifo is not full 1 = TX fifo is full 13 14 read-only SPI_TRANSACTION_ACTIVE In master mode 0 = spi transaction is inactive 1 = spi transaction is active 15 16 read-only SPI_TX_FIFO_LEVEL Gives the number of bytes in TX fifo 6 12 read-only FIFO_WRITE_REG Spi TX fifo wtite register 0x20 16 read-write n 0x0 0x0 SPI_FIFO_WRITE Write to TX fifo. Write access is permit only if SPI_TX_FIFO_FULL is 0 0 16 write-only IRQ_MASK_REG Spi interrupt mask register 0x10 16 read-write n 0x0 0x0 SPI_IRQ_MASK_RX_FULL 0 = FIFO RX full irq is masked 1 = FIFO RX full irq is enabled 1 2 read-write SPI_IRQ_MASK_TX_EMPTY 0 = FIFO TX empty irq is masked 1 = FIFO TX empy irq is enabled 0 1 read-write STATUS_REG Spi status register 0x14 16 read-write n 0x0 0x0 SPI_STATUS_RX_FULL Auto clear 0 = RX fifo level is less than SPI_RX_TL+1 1 = RX fifo level is more or equal to SPI_RX_TL+1 1 2 read-only SPI_STATUS_TX_EMPTY Auto clear 0 = TX fifo level is larger than SPI_TX_TL 1 = TX fifo level is less or equal to SPI_TX_TL 0 1 read-only TXBUFFER_FORCE_H_REG SPI TX buffer force high value 0x30 16 read-write n 0x0 0x0 SPI_TXBUFFER_FORCE_H Write directly the tx buffer (2 MSB). It must to be used only in slave mode. This register has to be written before the SPI_FIFO_WRITE_REG 0 16 write-only TXBUFFER_FORCE_L_REG SPI TX buffer force low value 0x2C 16 read-write n 0x0 0x0 SPI_TXBUFFER_FORCE_L Write directly the tx buffer (2 LSB). It must to be used only in slave mode 0 16 write-only SysTick Cortex M0 SysTick registers SYSTICK 0x0 0x0 0x11 registers n CALIB SysTick Calibration value register 0xC 32 read-only n 0x0 0x0 NOREF Indicates that a separate reference clock is provided 31 32 read-only SKEW Indicates whether the TENMS value is exact 30 31 read-only TENMS TENMS[23:0] bits (Calibration value) 0 24 read-only CTRL SysTick Control and Status register 0x0 32 read-write n 0x0 0x0 CLKSOURCE Clock source selection 2 3 read-write COUNTFLAG Timer counted to 0 since last time this was read 16 17 read-write ENABLE SysTick Counter enable 0 1 read-write TICKINT SysTick exception request enable 1 2 read-write LOAD SysTick Reload value register 0x4 32 read-write n 0x0 0x0 RELOAD RELOAD[23:0] bits (Reload value) 0 24 read-write VAL SysTick Current value register 0x8 32 read-write n 0x0 0x0 CURRENT CURRENT[23:0] bits (Current counter value) 0 24 read-write SYS_WDOG SYS_WDOG registers Peripheral_Registers 0x0 0x0 0x4 registers n WATCHDOG_CTRL_REG Watchdog control register. 0x2 16 read-write n 0x0 0x0 NMI_RST 0 = Watchdog timer generates NMI at value 0, and WDOG (SYS) reset at <=-16. Timer can be frozen /resumed using SET_FREEZE_REG[FRZ_WDOG]/ RESET_FREEZE_REG[FRZ_WDOG]. 1 = Watchdog timer generates a WDOG (SYS) reset at value 0 and can not be frozen by Software. Note that this bit can only be set to 1 by SW and only be reset with a WDOG (SYS) reset or SW reset. The watchdog is always frozen when the Cortex-M0 is halted in DEBUG State. 0 1 read-write WATCHDOG_REG Watchdog timer register. 0x0 16 read-write n 0x0 0x0 WDOG_VAL Write: Watchdog timer reload value. Note that all bits 15-9 must be 0 to reload this register. Read: Actual Watchdog timer value. Decremented by 1 every 10.24 msec. Bit 8 indicates a negative counter value. 2, 1, 0, 1FF16, 1FE16 etc. An NMI or WDOG (SYS) reset is generated under the following conditions: If WATCHDOG_CTRL_REG[NMI_RST] = 0 then If WDOG_VAL = 0 -> NMI (Non Maskable Interrupt) if WDOG_VAL = 1F016 -> WDOG reset -> reload FF16 If WATCHDOG_CTRL_REG[NMI_RST] = 1 then if WDOG_VAL <= 0 -> WDOG reset -> reload FF16 0 8 read-write WDOG_VAL_NEG 0 = Watchdog timer value is positive. 1 = Watchdog timer value is negative. 8 9 read-write WDOG_WEN 0000.000 = Write enable for Watchdog timer else Write disable. This filter prevents unintentional presetting the watchdog with a SW run-away. 9 16 write-only TIMER0 TIMER0 registers Peripheral_Registers 0x0 0x0 0x24 registers n CTRL_REG Timer0 control register 0x0 16 read-write n 0x0 0x0 PWM_MODE 0 = PWM signals are '1' during high time. 1 = PWM signals send out the (fast) clock divided by 2 during high time. So it will be in the range of 1 to 8 MHz. 3 4 read-write TIM0_CLK_DIV 1 = Timer0 uses selected clock frequency as is. 0 = Timer0 uses selected clock frequency divided by 10. Note that this applies only to the ON-counter. 2 3 read-write TIM0_CLK_SEL 1 = Timer0 uses 16, 8, 4 or 2 MHz (fast) clock frequency. 0 = Timer0 uses LP clock 1 2 read-write TIM0_CTRL 0 = Timer0 is off and in reset state. 1 = Timer0 is running. 0 1 read-write ON_REG Timer0 on control register 0x2 16 read-write n 0x0 0x0 TIM0_ON Timer0 On reload value: If read the actual counter value ON_CNTer is returned 0 16 read-write PWM2_END_CYCLE Defines end Cycle for PWM2 0x16 16 read-write n 0x0 0x0 END_CYCLE Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1 0 14 read-write PWM2_START_CYCLE Defines start Cycle for PWM2 0xA 16 read-write n 0x0 0x0 START_CYCLE Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0 0 14 read-write PWM3_END_CYCLE Defines end Cycle for PWM3 0x18 16 read-write n 0x0 0x0 END_CYCLE Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1 0 14 read-write PWM3_START_CYCLE Defines start Cycle for PWM3 0xC 16 read-write n 0x0 0x0 START_CYCLE Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0 0 14 read-write PWM4_END_CYCLE Defines end Cycle for PWM4 0x1A 16 read-write n 0x0 0x0 END_CYCLE Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1 0 14 read-write PWM4_START_CYCLE Defines start Cycle for PWM4 0xE 16 read-write n 0x0 0x0 START_CYCLE Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0 0 14 read-write PWM5_END_CYCLE Defines end Cycle for PWM5 0x1C 16 read-write n 0x0 0x0 END_CYCLE Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1 0 14 read-write PWM5_START_CYCLE Defines start Cycle for PWM5 0x10 16 read-write n 0x0 0x0 START_CYCLE Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0 0 14 read-write PWM6_END_CYCLE Defines end Cycle for PWM6 0x1E 16 read-write n 0x0 0x0 END_CYCLE Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1 0 14 read-write PWM6_START_CYCLE Defines start Cycle for PWM6 0x12 16 read-write n 0x0 0x0 START_CYCLE Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0 0 14 read-write PWM7_END_CYCLE Defines end Cycle for PWM7 0x20 16 read-write n 0x0 0x0 END_CYCLE Defines the cycle in which the PWM becomes low. If end_cycle is larger then freq and start_cycle is not larger then freq, output is always 1 0 14 read-write PWM7_START_CYCLE Defines start Cycle for PWM7 0x14 16 read-write n 0x0 0x0 START_CYCLE Defines the cycle in which the PWM becomes high. if start_cycle is larger than freq or end_cycle is equal to start_cycle, pwm out is always 0 0 14 read-write RELOAD_M_REG 16 bits reload value for Timer0 0x4 16 read-write n 0x0 0x0 TIM0_M Timer0 'high' reload valueIf read the actual counter value T0_CNTer is returned 0 16 read-write RELOAD_N_REG 16 bits reload value for Timer0 0x6 16 read-write n 0x0 0x0 TIM0_N Timer0 'low' reload value: If read the actual counter value T0_CNTer is returned 0 16 read-write TRIPLE_PWM_CTRL_REG PWM 2,3,4,5,6,7 Control 0x22 16 read-write n 0x0 0x0 HW_PAUSE_EN '1' = HW can pause PWM 2,3,4,5,6,7 2 3 read-write SW_PAUSE_EN '1' = PWM 2 3 4 5 6 7 are paused 1 2 read-write TRIPLE_PWM_CLK_SEL 1 = Timer2 uses 16, 8, 4 or 2 MHz (fast) clock frequency. 0 = Timer2 uses LP clock 3 4 read-write TRIPLE_PWM_ENABLE '1' = enable PWM 2 3 4 5 6 7 0 1 read-write TRIPLE_PWM_FREQUENCY Frequency for PWM 2,3,4,5,6 and 7 0x8 16 read-write n 0x0 0x0 PWM_FREQ Defines the frequeancy of PWM 2,3,4,5,,6 and 7. pwm freq = module Frequency / (value+1) module frequency is the LP_CLK when TRIPLE_PWM_CLK_SEL=0 else is the sys_clk divided by TMR_DIV 0 14 read-write TIMER1 TIMER1 registers Peripheral_Registers 0x0 0x0 0x18 registers n CAPCNT1_VALUE_REG Timer1 value for event on GPIO1 0xC 32 read-write n 0x0 0x0 TIMER1_CAPCNT1_RTC_HIGH In Counter mode : Not used In Capture mode: Gives the RTC time stamp (high part) when an IN1 event was occurred 11 22 read-only TIMER1_CAPCNT1_VALUE In Counter mode : Gives the number of timer clock cycles minus 1 which was measured during TIMER1_IN1_PERIOD_MAX periods of IN1 In Capture mode (TIMER1_IN1_STAMP_TYPE=0) : Gives the Counter value when an IN1 event was occurred In Capture mode (TIMER1_IN1_STAMP_TYPE=1) : Gives the RTC time stamp (low part) when an IN1 event was occurred 0 11 read-only CAPCNT2_VALUE_REG Timer1 value for event on GPIO2 0x10 32 read-write n 0x0 0x0 TIMER1_CAPCNT2_RTC_HIGH In Counter mode : Not used In Capture mode: Gives the RTC time stamp (high part) when an IN2 event was occurred 11 22 read-only TIMER1_CAPCNT2_VALUE In Counter mode : Gives the number of timer clock cycles minus 1 which was measured during TIMER1_IN2_PERIOD_MAX periods of IN2 In Capture mode (TIMER1_IN2_STAMP_TYPE=0) : Gives the Counter value when an IN2 event was occurred In Capture mode (TIMER1_IN2_STAMP_TYPE=1) : Gives the RTC time stamp (low part) when an IN2 event was occurred 0 11 read-only CAPTURE_REG Timer1 Capture control register 0x4 32 read-write n 0x0 0x0 TIMER1_GPIO1_CONF 0,13,14,15 = IN1 is not used 1..12 = Defines the P0 pin (0..11) module will use as IN1 0 4 read-write TIMER1_GPIO2_CONF 0,13,14,15 = IN2 is not used 1..12 = Defines the P0 pin (0..11) module will use as IN2 14 18 read-write TIMER1_IN1_COUNT_EN 0 = Capture mode 1 = Count mode 5 6 read-write TIMER1_IN1_EVENT_FALL_EN 0 = Rising edge event 1 = Falling edge event it should be written when TIMER1_GPIO1_CONF=0 to prevent false events 4 5 read-write TIMER1_IN1_IRQ_EN 1 = Interrupt is generated when capture is occurred or was counted TIMER1_IN1_PERIOD_MAX 0 = Interrupt is masked 6 7 read-write TIMER1_IN1_PERIOD_MAX Gives the number of periods +1 of IN1, in which module counts 7 13 read-write TIMER1_IN1_STAMP_TYPE 0 = On each event store the counter value 1 = On each event store the RTC time stamp 13 14 read-write TIMER1_IN2_COUNT_EN 0 = Capture mode 1 = Count mode 19 20 read-write TIMER1_IN2_EVENT_FALL_EN 0 = Rising edge event 1 = Falling edge event it should be written when TIMER1_GPIO2_CONF=0 to prevent false events 18 19 read-write TIMER1_IN2_IRQ_EN 1 = Interrupt is generated when capture is occurred or was counted TIMER1_IN2_PERIOD_MAX 0 = Interrupt is masked 20 21 read-write TIMER1_IN2_PERIOD_MAX Gives the number of periods +1 of IN2, in which module counts 21 27 read-write TIMER1_IN2_STAMP_TYPE 0 = On each event store the counter value 1 = On each event store the RTC time stamp 27 28 read-write CLR_EVENT_REG Clear event register 0x14 32 read-write n 0x0 0x0 TIMER1_CLR_IN1_EVENT Write 1 to clear the TIMER1_IN1_EVENT and TIMER1_IN1_OVRFLW 1 2 read-write TIMER1_CLR_IN2_EVENT Write 1 to clear the TIMER1_IN2_EVENT and TIMER1_IN2_OVRFLW 2 3 read-write TIMER1_CLR_TIMER_EVENT Write 1 to clear the TIMER1_TIMER_EVENT 0 1 read-write CTRL_REG Timer1 control register 0x0 32 read-write n 0x0 0x0 TIMER1_CLK_EN 0 = timer1 clock is disabled 1 = timer1 clock is enabled 16 17 read-write TIMER1_COUNT_DOWN_EN 0 = timer1 counts up 1 = timer1 counts down 12 13 read-write TIMER1_ENABLE 0 = Timer1 disabled 1 = Timer1 enabled 11 12 read-write TIMER1_FREE_RUN_MODE_EN Applicable when timer counts up 1 = timer1 goes to zero when it reaches the max value. 0 = timer1 goes to zero when it reaches the reload value. 14 15 read-write TIMER1_IRQ_EN 0 = timer1 IRQ masked 1 = timer1 IRQ unmasked 13 14 read-write TIMER1_RELOAD Reload or max value in timer mode. Actual delay is the register value plus synchronization time (3 clock cycles) 0 11 read-write TIMER1_USE_SYS_CLK 0 = Timer1 use the clock LP clock 1 = Timer1 use the system clock 15 16 read-write STATUS_REG Timer1 counter value 0x8 32 read-write n 0x0 0x0 TIMER1_IN1_EVENT 1 = Pending Capture 1 interrupt. It has be clear writing 1 to TIMER1_CLR_IN1_EVENT 12 13 read-only TIMER1_IN1_OVRFLW 1 = New IN1 event occurred while Interrupt was pending. TIMER1_CAPCNT1_VALUE_REG gives the time stamp of the first event. 14 15 read-only TIMER1_IN2_EVENT 1 = Pending Capture 2 interrupt. It has be clear writing 1 to TIMER1_CLR_IN2_EVENT 13 14 read-only TIMER1_IN2_OVRFLW 1 = New IN2 event occurred while Interrupt was pending. TIMER1_CAPCNT2_VALUE_REG gives the time stamp of the first event. 15 16 read-only TIMER1_TIMER_EVENT 1 = Pending Timer interrupt. it has be clear writing 1' to TIMER1_CLR_TIMER_EVENT 11 12 read-only TIMER1_TIMER_VALUE Gives the current timer value 0 11 read-only UART UART registers Peripheral_Registers 0x0 0x0 0x100 registers n CTR_HIGH_REG Component Type Register 0xFE 16 read-write n 0x0 0x0 CTR Component Type Register 0 16 read-only CTR_REG Component Type Register 0xFC 16 read-write n 0x0 0x0 CTR Component Type Register 0 16 read-only DLF_REG Divisor Latch Fraction Register 0xC0 16 read-write n 0x0 0x0 UART_DLF The fractional value is added to integer value set by DLH, DLL. Fractional value is equal UART_DLF/16 0 4 read-write DMASA_REG DMA Software Acknowledge 0xA8 16 read-write n 0x0 0x0 DMASA This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This will cause the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. 0 1 write-only FAR_REG FIFO Access Register 0x70 16 read-write n 0x0 0x0 UART_FAR Description: Writes will have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFO's are implemented and enabled. When FIFO's are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty. 0 1 read-only HTX_REG Halt TX 0xA4 16 read-write n 0x0 0x0 UART_HALT_TX This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. 0 1 read-write IER_DLH_REG Interrupt Enable Register/Divisor Latch High 0x4 16 read-write n 0x0 0x0 dlh6_4 Divisor Latch (High): DLH6 to DLH4, Bits 6 to 4 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set, otherwise, this field is reserved. See register UART_RBR_THR_DLL_REG. 4 7 read-write EDSSI_dlh3 Interrupt Enable Register: EDSSI, Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH3, Bit 3 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 3 4 read-write ELSI_dhl2 Interrupt Enable Register: ELSI, Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH2, Bit 2 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 2 3 read-write ERBFI_dlh0 Interrupt Enable Register: ERBFI, Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFO's enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled Divisor Latch (High): DLH0, Bit 0 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 0 1 read-write ETBEI_dlh1 Interrupt Enable Register: ETBEI, Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH1, Bit 1 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 1 2 read-write PTIME_dlh7 Interrupt Enable Register: PTIME, Programmable THRE Interrupt Mode Enable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled. Divisor Latch (High): DLH7, Bit 7 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 7 8 read-write IIR_FCR_REG Interrupt Identification Register/FIFO Control Register 0x8 16 read-write n 0x0 0x0 UART_FIFOSE_RT On read FIFO's Enabled (or FIFOSE): This is used to indicate whether the FIFO's are enabled or disabled. 00 = disabled. 11 = enabled. On write RCVR Trigger (or RT):. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted. It also determines when the dma_rx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO 1/4 full 10 = FIFO 1/2 full 11 = FIFO 2 less than full 6 8 read-write UART_IID0_FIFOE On Read (Bit0) Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. On Write FIFO Enable (or FIFOE): This enables/disables the transmit (XMIT) and receive (RCVR) FIFO's. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFO's will be reset 0 1 read-write UART_IID1_RFIFOE On Read (Bit1) Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. On Write RCVR FIFO Reset (or RFIFOR): This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. 1 2 read-write UART_IID2_XFIFOR On Read (Bit2) Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. On Write XMIT FIFO Reset (or XFIFOR): This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. 2 3 read-write UART_IID3_DMAM On Read (Bit3) Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. On Write DMA Mode (or DMAM): This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 3 4 read-write UART_TET On read reserved On Write TX Empty Trigger (or TET): This is used to select the empty threshold level at which the THRE Interrupts will be generated when the mode is active. It also determines when the dma_tx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO 1/4 full 11 = FIFO 1/2 full 4 6 write-only LCR_REG Line Control Register 0xC 16 read-write n 0x0 0x0 UART_BC Break Control Bit. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. 6 7 read-write UART_DLAB Divisor Latch Access Bit. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. 7 8 read-write UART_DLS Data Length Select. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits 0 2 read-write UART_EPS Even Parity Select. Writeable only when UART is not busy (USR[0] is zero). This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. 4 5 read-write UART_PEN Parity Enable. Writeable only when UART is not busy (USR[0] is zero) This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled 3 4 read-write UART_STOP Number of stop bits. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit 2 3 read-write LSR_REG Line Status Register 0x14 16 read-write n 0x0 0x0 UART_BI Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. 4 5 read-only UART_DR Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. 0 1 read-only UART_FE Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. 3 4 read-only UART_OE Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. 1 2 read-only UART_PE Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. 2 3 read-only UART_RFE Receiver FIFO Error bit. This bit is only relevant when FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. 7 8 read-only UART_TEMT Transmitter Empty bit. If FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. 6 7 read-only UART_THRE Transmit Holding Register Empty bit. If THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. 5 6 read-only MCR_REG Modem Control Register 0x10 16 read-write n 0x0 0x0 UART_AFCE Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in Auto Flow Control . 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled 5 6 read-write UART_LB LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line. 4 5 read-write UART_RTS Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input. 1 2 read-write MSR_REG Modem Status Register 0x18 16 read-write n 0x0 0x0 UART_CTS Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the UART Ctrl. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS). 4 5 read-only RBR_THR_DLL_REG Receive Buffer Register/Transmit Holding Register/Divisor Latch Low 0x0 16 read-write n 0x0 0x0 RBR_THR_DLL Receive Buffer Register: (RBR). This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Transmit Holding Register: (THR) This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Divisor Latch (Low): (DLL) This register makes up the lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set. The output baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor) Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the Divisor Latch is set, at least 8 clock cycles of the slowest UART clock should be allowed to pass before transmitting or receiving data. For the Divisor Latch (High) bits, see register UART_IER_DLH_REG. 0 8 read-write RFL_REG Receive FIFO Level 0x84 16 read-write n 0x0 0x0 UART_RECEIVE_FIFO_LEVEL Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. 0 5 read-only SBCR_REG Shadow Break Control Register 0x90 16 read-write n 0x0 0x0 UART_SHADOW_BREAK_CONTROL Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. 0 1 read-write SCR_REG Scratchpad Register 0x1C 16 read-write n 0x0 0x0 UART_SCRATCH_PAD This register is for programmers to use as a temporary storage space. It has no defined purpose in the UART Ctrl. 0 8 read-write SDMAM_REG Shadow DMA Mode 0x94 16 read-write n 0x0 0x0 UART_SHADOW_DMA_MODE Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 0 1 read-write SFE_REG Shadow FIFO Enable 0x98 16 read-write n 0x0 0x0 UART_SHADOW_FIFO_ENABLE Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. 0 1 read-write SRBR_STHR0_REG Shadow Receive/Transmit Buffer Register 0x30 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR10_REG Shadow Receive/Transmit Buffer Register 0x58 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR11_REG Shadow Receive/Transmit Buffer Register 0x5C 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR12_REG Shadow Receive/Transmit Buffer Register 0x60 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR13_REG Shadow Receive/Transmit Buffer Register 0x64 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR14_REG Shadow Receive/Transmit Buffer Register 0x68 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR15_REG Shadow Receive/Transmit Buffer Register 0x6C 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR1_REG Shadow Receive/Transmit Buffer Register 0x34 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR2_REG Shadow Receive/Transmit Buffer Register 0x38 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR3_REG Shadow Receive/Transmit Buffer Register 0x3C 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR4_REG Shadow Receive/Transmit Buffer Register 0x40 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR5_REG Shadow Receive/Transmit Buffer Register 0x44 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR6_REG Shadow Receive/Transmit Buffer Register 0x48 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR7_REG Shadow Receive/Transmit Buffer Register 0x4C 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR8_REG Shadow Receive/Transmit Buffer Register 0x50 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR9_REG Shadow Receive/Transmit Buffer Register 0x54 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRR_REG Software Reset Register. 0x88 16 read-write n 0x0 0x0 UART_RFR RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. 1 2 write-only UART_UR UART Reset. This asynchronously resets the UART Ctrl and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. 0 1 write-only UART_XFR XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. 2 3 write-only SRTS_REG Shadow Request to Send 0x8C 16 read-write n 0x0 0x0 UART_SHADOW_REQUEST_TO_SEND Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART Ctrl is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] = 1) and FIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input. 0 1 read-write SRT_REG Shadow RCVR Trigger 0x9C 16 read-write n 0x0 0x0 UART_SHADOW_RCVR_TRIGGER Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full 0 2 read-write STET_REG Shadow TX Empty Trigger 0xA0 16 read-write n 0x0 0x0 UART_SHADOW_TX_EMPTY_TRIGGER Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full 0 2 read-write TFL_REG Transmit FIFO Level 0x80 16 read-write n 0x0 0x0 UART_TRANSMIT_FIFO_LEVEL Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. 0 5 read-only UCV_HIGH_REG Component Version 0xFA 16 read-write n 0x0 0x0 UCV Component Version 0 16 read-only UCV_REG Component Version 0xF8 16 read-write n 0x0 0x0 UCV Component Version 0 16 read-only USR_REG UART Status Register 0x7C 16 read-write n 0x0 0x0 UART_BUSY UART Busy. This indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 - DW_apb_uart is idle or inactive 1 - DW_apb_uart is busy (actively transferring data) Note that it is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in the THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled) the assertion of this bit will also be delayed by several cycles of the slower clock. 0 1 read-only UART_RFF Receive FIFO Full. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. 4 5 read-only UART_RFNE Receive FIFO Not Empty. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. 3 4 read-only UART_TFE Transmit FIFO Empty. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. 2 3 read-only UART_TFNF Transmit FIFO Not Full. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. 1 2 read-only UART2 UART2 registers Peripheral_Registers 0x0 0x0 0x100 registers n CTR_HIGH_REG Component Type Register 0xFE 16 read-write n 0x0 0x0 CTR Component Type Register 0 16 read-only CTR_REG Component Type Register 0xFC 16 read-write n 0x0 0x0 CTR Component Type Register 0 16 read-only DLF_REG Divisor Latch Fraction Register 0xC0 16 read-write n 0x0 0x0 UART_DLF The fractional value is added to integer value set by DLH, DLL. Fractional value is equal UART_DLF/16 0 4 read-write DMASA_REG DMA Software Acknowledge 0xA8 16 read-write n 0x0 0x0 DMASA This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This will cause the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. 0 1 write-only FAR_REG FIFO Access Register 0x70 16 read-write n 0x0 0x0 UART_FAR Description: Writes will have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFO's are implemented and enabled. When FIFO's are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty. 0 1 read-only HTX_REG Halt TX 0xA4 16 read-write n 0x0 0x0 UART_HALT_TX This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. 0 1 read-write IER_DLH_REG Interrupt Enable Register/Divisor Latch High 0x4 16 read-write n 0x0 0x0 dlh6_4 Divisor Latch (High): DLH6 to DLH4, Bits 6 to 4 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set, otherwise, this field is reserved. See register UART_RBR_THR_DLL_REG. 4 7 read-write EDSSI_dlh3 Interrupt Enable Register: EDSSI, Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH3, Bit 3 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 3 4 read-write ELSI_dhl2 Interrupt Enable Register: ELSI, Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH2, Bit 2 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 2 3 read-write ERBFI_dlh0 Interrupt Enable Register: ERBFI, Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFO's enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled Divisor Latch (High): DLH0, Bit 0 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 0 1 read-write ETBEI_dlh1 Interrupt Enable Register: ETBEI, Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH1, Bit 1 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 1 2 read-write PTIME_dlh7 Interrupt Enable Register: PTIME, Programmable THRE Interrupt Mode Enable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled. Divisor Latch (High): DLH7, Bit 7 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 7 8 read-write IIR_FCR_REG Interrupt Identification Register/FIFO Control Register 0x8 16 read-write n 0x0 0x0 UART_FIFOSE_RT On read FIFO's Enabled (or FIFOSE): This is used to indicate whether the FIFO's are enabled or disabled. 00 = disabled. 11 = enabled. On write RCVR Trigger (or RT):. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted. It also determines when the dma_rx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO 1/4 full 10 = FIFO 1/2 full 11 = FIFO 2 less than full 6 8 read-write UART_IID0_FIFOE On Read (Bit0) Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. On Write FIFO Enable (or FIFOE): This enables/disables the transmit (XMIT) and receive (RCVR) FIFO's. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFO's will be reset 0 1 read-write UART_IID1_RFIFOE On Read (Bit1) Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. On Write RCVR FIFO Reset (or RFIFOR): This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. 1 2 read-write UART_IID2_XFIFOR On Read (Bit2) Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. On Write XMIT FIFO Reset (or XFIFOR): This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. 2 3 read-write UART_IID3_DMAM On Read (Bit3) Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. On Write DMA Mode (or DMAM): This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 3 4 read-write UART_TET On read reserved On Write TX Empty Trigger (or TET): This is used to select the empty threshold level at which the THRE Interrupts will be generated when the mode is active. It also determines when the dma_tx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO 1/4 full 11 = FIFO 1/2 full 4 6 write-only LCR_REG Line Control Register 0xC 16 read-write n 0x0 0x0 UART_BC Break Control Bit. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. 6 7 read-write UART_DLAB Divisor Latch Access Bit.Writeable only when UART is not busy (USR[0] is zero). This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. 7 8 read-write UART_DLS Data Length Select.Writeable only when UART is not busy (USR[0] is zero). This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits 0 2 read-write UART_EPS Even Parity Select. Writeable only when UART is not busy (USR[0] is zero). This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. 4 5 read-write UART_PEN Parity Enable. Writeable only when UART is not busy (USR[0] is zero) This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled 3 4 read-write UART_STOP Number of stop bits. Writeable only when UART is not busy (USR[0] is zero). This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit 2 3 read-write LSR_REG Line Status Register 0x14 16 read-write n 0x0 0x0 UART_BI Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. 4 5 read-only UART_DR Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. 0 1 read-only UART_FE Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. 3 4 read-only UART_OE Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. 1 2 read-only UART_PE Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. 2 3 read-only UART_RFE Receiver FIFO Error bit. This bit is only relevant when FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. 7 8 read-only UART_TEMT Transmitter Empty bit. If FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If FIFOs are disabled, this bit is set whenever the Transmitter Holding Register(THR) and the Transmitter Shift Register are both empty. 6 7 read-only UART_THRE Transmit Holding Register Empty bit. If THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. 5 6 read-only MCR_REG Modem Control Register 0x10 16 read-write n 0x0 0x0 UART_LB LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line. 4 5 read-write RBR_THR_DLL_REG Receive Buffer Register/Transmit Holding Register/Divisor Latch Low 0x0 16 read-write n 0x0 0x0 RBR_THR_DLL Receive Buffer Register: (RBR). This register contains the data byte received on the serial input port (sin) in UART mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Transmit Holding Register: (THR) This register contains data to be transmitted on the serial output port (sout) in UART mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, 16 number of characters of data may be written to the THR before the FIFO is full. Any attempt to write data when the FIFO is full results in the write data being lost. Divisor Latch (Low): (DLL) This register makes up the lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set. The output baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor) Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the Divisor Latch is set, at least 8 clock cycles of the slowest UART clock should be allowed to pass before transmitting or receiving data. For the Divisor Latch (High) bits, see register UART_IER_DLH_REG. 0 8 read-write RFL_REG Receive FIFO Level 0x84 16 read-write n 0x0 0x0 UART_RECEIVE_FIFO_LEVEL Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. 0 5 read-only SBCR_REG Shadow Break Control Register 0x90 16 read-write n 0x0 0x0 UART_SHADOW_BREAK_CONTROL Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. 0 1 read-write SCR_REG Scratchpad Register 0x1C 16 read-write n 0x0 0x0 UART_SCRATCH_PAD This register is for programmers to use as a temporary storage space. It has no defined purpose in the UART Ctrl. 0 8 read-write SDMAM_REG Shadow DMA Mode 0x94 16 read-write n 0x0 0x0 UART_SHADOW_DMA_MODE Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 0 1 read-write SFE_REG Shadow FIFO Enable 0x98 16 read-write n 0x0 0x0 UART_SHADOW_FIFO_ENABLE Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. 0 1 read-write SRBR_STHR0_REG Shadow Receive/Transmit Buffer Register 0x30 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR10_REG Shadow Receive/Transmit Buffer Register 0x58 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR11_REG Shadow Receive/Transmit Buffer Register 0x5C 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR12_REG Shadow Receive/Transmit Buffer Register 0x60 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR13_REG Shadow Receive/Transmit Buffer Register 0x64 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR14_REG Shadow Receive/Transmit Buffer Register 0x68 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR15_REG Shadow Receive/Transmit Buffer Register 0x6C 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR1_REG Shadow Receive/Transmit Buffer Register 0x34 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR2_REG Shadow Receive/Transmit Buffer Register 0x38 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR3_REG Shadow Receive/Transmit Buffer Register 0x3C 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR4_REG Shadow Receive/Transmit Buffer Register 0x40 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR5_REG Shadow Receive/Transmit Buffer Register 0x44 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR6_REG Shadow Receive/Transmit Buffer Register 0x48 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR7_REG Shadow Receive/Transmit Buffer Register 0x4C 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR8_REG Shadow Receive/Transmit Buffer Register 0x50 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR9_REG Shadow Receive/Transmit Buffer Register 0x54 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRR_REG Software Reset Register. 0x88 16 read-write n 0x0 0x0 UART_RFR RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. 1 2 write-only UART_UR UART Reset. This asynchronously resets the UART Ctrl and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. 0 1 write-only UART_XFR XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. 2 3 write-only SRT_REG Shadow RCVR Trigger 0x9C 16 read-write n 0x0 0x0 UART_SHADOW_RCVR_TRIGGER Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full 0 2 read-write STET_REG Shadow TX Empty Trigger 0xA0 16 read-write n 0x0 0x0 UART_SHADOW_TX_EMPTY_TRIGGER Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full 0 2 read-write TFL_REG Transmit FIFO Level 0x80 16 read-write n 0x0 0x0 UART_TRANSMIT_FIFO_LEVEL Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. 0 5 read-only UCV_HIGH_REG Component Version 0xFA 16 read-write n 0x0 0x0 UCV Component Version 0 16 read-only UCV_REG Component Version 0xF8 16 read-write n 0x0 0x0 UCV Component Version 0 16 read-only USR_REG UART Status Register 0x7C 16 read-write n 0x0 0x0 UART_BUSY UART Busy. This indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 - DW_apb_uart is idle or inactive 1 - DW_apb_uart is busy (actively transferring data) Note that it is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in the THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled) the assertion of this bit will also be delayed by several cycles of the slower clock. 0 1 read-only UART_RFF Receive FIFO Full. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. 4 5 read-only UART_RFNE Receive FIFO Not Empty. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. 3 4 read-only UART_TFE Transmit FIFO Empty. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. 2 3 read-only UART_TFNF Transmit FIFO Not Full. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. 1 2 read-only WKUP WKUP registers Peripheral_Registers 0x0 0x0 0x10 registers n COMPARE_REG Number of events before wakeup interrupt 0x2 16 read-write n 0x0 0x0 WKUP_COMPARE Defines the number of events -1 that have to be counted before the wakeup interrupt will be given. value 0 means one event. 0 8 read-write COUNTER_REG Actual number of events of the wakeup counter 0x6 16 read-write n 0x0 0x0 EVENT2_VALUE This value represents the number of events that have been counted so far. It will be reset by resetting the interrupt. 8 16 read-only EVENT_VALUE This value represents the number of events that have been counted so far. It will be reset by resetting the interrupt. 0 8 read-only CTRL_REG Control register for the wakeup counter 0x0 16 read-write n 0x0 0x0 WKUP2_ENABLE_IRQ 0 = no interrupt will be generated 1 = if the event counter2 reaches the value set by WKUP_COMPARE_REG an IRQ will be generated 8 9 read-write WKUP_DEB_VALUE Keyboard debounce time (N*1 ms with N = 1 to 63). 0x0: no debouncing 0x1 to 0x3F: 1 ms to 63 ms debounce time 0 6 read-write WKUP_ENABLE_IRQ 0 = no interrupt will be generated 1 = if the event counter reaches the value set by WKUP_COMPARE_REG an IRQ will be generated 7 8 read-write WKUP_SFT_KEYHIT 0 = no effect 1 = emulate key hit. The event counter and counter2 will increment by 1 (after debouncing if enabled). First make this bit 0 before any new key hit can be sensed. 6 7 read-write IRQ_STATUS_REG Reset wakeup interrupt 0x4 16 read-write n 0x0 0x0 WKUP2_CNTR_RST writing 1 will reset the event2 counter 3 4 write-only WKUP2_IRQ_STATUS Gives 1 when there is a wkup2 pending IRQ. Writing 1 will reset the interrupt. 1 2 read-write WKUP_CNTR_RST writing 1 will reset the event counter 2 3 write-only WKUP_IRQ_STATUS Gives 1 when there is a wkup pending IRQ. Writing 1 will reset the interrupt. 0 1 read-write POL_GPIO_REG Select the sensitivity polarity for each P0 input 0xC 16 read-write n 0x0 0x0 WKUP_POL_GPIO 0 = the enabled input P0x increments the event counter if that input goes high 1 = the enabled input P0x increments the event counter if that input goes low 0 12 read-write SELECT_GPIO_REG Select which inputs from P0 port can trigger wkup counter 0x8 16 read-write n 0x0 0x0 WKUP_SELECT_GPIO 0 = input P0x is not enabled for wakeup event counter 1 = input P0x is enabled for wakeup event counter 0 12 read-write WKUP2_POL_GPIO_REG Select the sensitivity polarity for each P1 input 0xE 16 read-write n 0x0 0x0 WKUP2_POL_GPIO 0 = the enabled input P0x increments the event2 counter if that input goes high 1 = the enabled input P0x increments the event2 counter if that input goes low 0 12 read-write WKUP2_SELECT_GPIO_REG Select which inputs from P1 port can trigger wkup counter 0xA 16 read-write n 0x0 0x0 WKUP2_SELECT_GPIO 0 = input P0x is not enabled for wakeup event counter 1 = input P0x is enabled for wakeup event counter 0 12 read-write