Dialog
DA14585
2024.04.18
Ultra-Low power Bleutooth 5.0 SoC with audio interface from Dialog Semiconductor
CM0
r1p0
little
true
3
false
8
32
adc580_bif_nl01
adc580_bif_nl01 registers
Peripheral_Registers
0x0
0x0
0x10
registers
n
GP_ADC_CLEAR_INT_REG
General Purpose ADC Clear Interrupt Register
0x8
16
read-write
n
0x0
0x0
GP_ADC_CLR_INT
Writing any value to this register will clear the ADC_INT interrupt. Reading returns 0.
0
16
write-only
GP_ADC_CTRL2_REG
General Purpose ADC Second Control Register
0x2
16
read-write
n
0x0
0x0
GP_ADC_ATTN3X
0 = Input voltages up to 1.2V allowed. 1 = Input voltages up to 3.6V allowed by enabling 3x attenuator.
1
2
read-write
GP_ADC_DELAY_EN
Enables delay function for several signals. This is not auto-cleared. Toggle this bit before every sampling to enable succesive conversions.
0
1
read-write
GP_ADC_I20U
Adds 20uA constant load current at the ADC LDO to minimize ripple on the reference voltage of the ADC.
3
4
read-write
GP_ADC_IDYN
Enables dynamic load current at the ADC LDO to minimize ripple on the reference voltage of the ADC.
2
3
read-write
GP_ADC_CTRL_REG
General Purpose ADC Control Register
0x0
16
read-write
n
0x0
0x0
GP_ADC_CHOP
Takes two samples with opposite GP_ADC_SIGN to cancel the internal offset voltage of the ADC Highly recommended for DC-measurements.
13
14
read-write
GP_ADC_CLK_SEL
0 = Internal high-speed ADC clock used. 1 = Digital clock used.
3
4
read-write
GP_ADC_EN
0 = ADC is disabled and in reset. 1 = ADC is enabled and sampling of input is started.
0
1
read-write
GP_ADC_INT
1 = AD conversion ready and has generated an interrupt. Must be cleared by writing any value to GP_ADC_CLEAR_INT_REG.
4
5
read-only
GP_ADC_LDO_EN
Turns on LDO.
14
15
read-write
GP_ADC_LDO_ZERO
Forces LDO-output to 0V.
15
16
read-write
GP_ADC_MINT
0 = Disable (mask) GP_ADC_INT. 1 = Enable GP_ADC_INT to ICU.
5
6
read-write
GP_ADC_MUTE
Takes sample at mid-scale (to dertermine the internal offset and/or noise of the ADC with regards to VDD_REF which is also sampled by the ADC).
12
13
read-write
GP_ADC_SE
0 = Differential mode 1 = Single ended mode
11
12
read-write
GP_ADC_SEL
ADC input selection which must be set before the GP_ADC_START bit is enabled. If GP_ADC_SE = 1 (single ended mode): 0000 = P0[0] 0001 = P0[1] 0010 = P0[2] 0011 = P0[3] 0100 = AVS 0101 = VDD_REF 0110 = VDD_RTT (=VDD_REF) 0111 = VBAT3V 1000 = VDCDC 1001 = VBAT1V All other combinations are reserved. If GP_ADC_SE = 0 (differential mode): 0000 = P0[0] vs P0[1] All other combinations are P0[2] vs P0[3].
6
10
read-write
GP_ADC_SIGN
0 = Default 1 = Conversion with opposite sign at input and output to cancel out the internal offset of the ADC and low-frequency
10
11
read-write
GP_ADC_START
0 = ADC conversion ready. 1 = If a 1 is written, the ADC starts a conversion. After the conversion this bit will be set to 0 and the GP_ADC_INT bit will be set.
1
2
read-write
GP_ADC_TEST
Reserved, keep 0.
2
3
GP_ADC_DELAY2_REG
General Purpose ADC Second Delay Register
0xE
16
read-write
n
0x0
0x0
DEL_ADC_EN
Defines the delay for the GP_ADC_EN bit. Reset value is 16 µs which is the recommended value to wait after enabling the LDO. This is the second step in bringing up the GP ADC.
0
8
read-write
DEL_ADC_START
Defines the delay for the GP_ADC_START bit. Reset value is 17 µs which is the recommended value to wait before starting the GP ADC. This is the third and last step of bringing up the GP ADC
8
16
read-write
GP_ADC_DELAY_REG
General Purpose ADC Delay Register
0xC
16
read-write
n
0x0
0x0
DEL_LDO_EN
Defines the delay before the LDO enable (GP_ADC_LDO_EN). Reset value is 0 µs since the LDO enable should be the first thing to be programmed in the sequence of bringing the GP ADC up.
0
8
read-write
GP_ADC_OFFN_REG
General Purpose ADC Negative Offset Register
0x6
16
read-write
n
0x0
0x0
GP_ADC_OFFN
Offset adjust of 'negative' array of ADC-network (effective if 'GP_ADC_SE=0', or 'GP_ADC_SE=1 AND GP_ADC_SIGN=1')
0
10
read-write
GP_ADC_OFFP_REG
General Purpose ADC Positive Offset Register
0x4
16
read-write
n
0x0
0x0
GP_ADC_OFFP
Offset adjust of 'positive' array of ADC-network (effective if 'GP_ADC_SE=0', or 'GP_ADC_SE=1 AND GP_ADC_SIGN=0')
0
10
read-write
GP_ADC_RESULT_REG
General Purpose ADC Result Register
0xA
16
read-write
n
0x0
0x0
GP_ADC_VAL
Returns the 10 bits linear value of the last AD conversion.
0
10
read-only
ambacore580_patch_gr00
ambacore580_patch_gr00 registers
Peripheral_Registers
0x0
0x0
0x50
registers
n
PATCH_ADDR0_REG
Patch entry 0: Address field
0x10
32
read-write
n
0x0
0x0
PATCH_ADDR
This is the value which will be compared to the address on the AHB. If a match occurs, the data bus willl be filled with the value in the respective PATCH_DATAx_REG. Bits [1:0] are read-only and always read as '0'. Never use the base address 0x0 for values in PATCH_ADDRx_REG because HW Patch block is located after the Address Remapping block.
0
32
read-write
PATCH_ADDR1_REG
Patch entry 1: Address field
0x18
32
read-write
n
0x0
0x0
PATCH_ADDR
This is the value which will be compared to the address on the AHB. If a match occurs, the data bus willl be filled with the value in the respective PATCH_DATAx_REG. Bits [1:0] are read-only and always read as '0'. Never use the base address 0x0 for values in PATCH_ADDRx_REG because HW Patch block is located after the Address Remapping block.
0
32
read-write
PATCH_ADDR2_REG
Patch entry 2: Address field
0x20
32
read-write
n
0x0
0x0
PATCH_ADDR
This is the value which will be compared to the address on the AHB. If a match occurs, the data bus willl be filled with the value in the respective PATCH_DATAx_REG. Bits [1:0] are read-only and always read as '0'. Never use the base address 0x0 for values in PATCH_ADDRx_REG because HW Patch block is located after the Address Remapping block.
0
32
read-write
PATCH_ADDR3_REG
Patch entry 3: Address field
0x28
32
read-write
n
0x0
0x0
PATCH_ADDR
This is the value which will be compared to the address on the AHB. If a match occurs, the data bus willl be filled with the value in the respective PATCH_DATAx_REG. Bits [1:0] are read-only and always read as '0'. Never use the base address 0x0 for values in PATCH_ADDRx_REG because HW Patch block is located after the Address Remapping block.
0
32
read-write
PATCH_ADDR4_REG
Patch entry 4: Address field
0x30
32
read-write
n
0x0
0x0
PATCH_ADDR
This is the value which will be compared to the address on the AHB. If a match occurs, the data bus willl be filled with the value in the respective PATCH_DATAx_REG. Bits [1:0] are read-only and always read as '0'. Never use the base address 0x0 for values in PATCH_ADDRx_REG because HW Patch block is located after the Address Remapping block.
0
32
read-write
PATCH_ADDR5_REG
Patch entry 5: Address field
0x38
32
read-write
n
0x0
0x0
PATCH_ADDR
This is the value which will be compared to the address on the AHB. If a match occurs, the data bus willl be filled with the value in the respective PATCH_DATAx_REG. Bits [1:0] are read-only and always read as '0'. Never use the base address 0x0 for values in PATCH_ADDRx_REG because HW Patch block is located after the Address Remapping block.
0
32
read-write
PATCH_ADDR6_REG
Patch entry 6: Address field
0x40
32
read-write
n
0x0
0x0
PATCH_ADDR
This is the value which will be compared to the address on the AHB. If a match occurs, the data bus willl be filled with the value in the respective PATCH_DATAx_REG. Bits [1:0] are read-only and always read as '0'. Never use the base address 0x0 for values in PATCH_ADDRx_REG because HW Patch block is located after the Address Remapping block.
0
32
read-write
PATCH_ADDR7_REG
Patch entry 7: Address field
0x48
32
read-write
n
0x0
0x0
PATCH_ADDR
This is the value which will be compared to the address on the AHB. If a match occurs, the data bus willl be filled with the value in the respective PATCH_DATAx_REG. Bits [1:0] are read-only and always read as '0'. Never use the base address 0x0 for values in PATCH_ADDRx_REG because HW Patch block is located after the Address Remapping block.
0
32
read-write
PATCH_DATA0_REG
Patch entry 0: Data field
0x14
32
read-write
n
0x0
0x0
PATCH_DATA
This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG
0
32
read-write
PATCH_DATA1_REG
Patch entry 1: Data field
0x1C
32
read-write
n
0x0
0x0
PATCH_DATA
This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG
0
32
read-write
PATCH_DATA2_REG
Patch entry 2: Data field
0x24
32
read-write
n
0x0
0x0
PATCH_DATA
This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG
0
32
read-write
PATCH_DATA3_REG
Patch entry 3: Data field
0x2C
32
read-write
n
0x0
0x0
PATCH_DATA
This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG
0
32
read-write
PATCH_DATA4_REG
Patch entry 4: Data field
0x34
32
read-write
n
0x0
0x0
PATCH_DATA
This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG
0
32
read-write
PATCH_DATA5_REG
Patch entry 5: Data field
0x3C
32
read-write
n
0x0
0x0
PATCH_DATA
This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG
0
32
read-write
PATCH_DATA6_REG
Patch entry 6: Data field
0x44
32
read-write
n
0x0
0x0
PATCH_DATA
This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG
0
32
read-write
PATCH_DATA7_REG
Patch entry 7: Data field
0x4C
32
read-write
n
0x0
0x0
PATCH_DATA
This is the value which will be injected into the data bus if there is a match on the comparison of the address with the respective PATCH_ADDRx_REG
0
32
read-write
PATCH_VALID_REG
Validity Control Register
0x0
32
read-write
n
0x0
0x0
PATCH_VALID
Indicates which patch entry is valid. For example, when bit 0 is high it indicates that entry 0 is valid, i.e. the values of PATCH_ADDR0_REG / PATCH_DATA0_REG, are effective.
0
8
read-write
PATCH_VALID_RESET_REG
Validity Reset Control Register
0x8
32
read-write
n
0x0
0x0
PATCH_VALID_RESET
Writing a bit with 1 will clear the corresponding bit of PATCH_VALID_REG to 0. Writing a bit with zero is ignored. Read always as 0.
0
8
read-write
PATCH_VALID_SET_REG
Validity Set Control Register
0x4
32
read-write
n
0x0
0x0
PATCH_VALID_SET
Writing a bit with 1 will set the corresponding bit of PATCH_VALID_REG to 1. Writing a bit with 0 is ignored. Read always as 0.
0
8
read-write
anamisc580_nl01
anamisc580_nl01 registers
Peripheral_Registers
0x0
0x0
0x8
registers
n
CLK_REF_CNT_REG
Count value for oscillator calibration
0x2
16
read-write
n
0x0
0x0
REF_CNT_VAL
Indicates the calibration time, with a decrement counter to 1.
0
16
read-write
CLK_REF_SEL_REG
Select clock for oscillator calibration
0x0
16
read-write
n
0x0
0x0
REF_CAL_START
Writing a '1' starts a calibration. This bit is cleared when calibration is finished, and CLK_REF_VAL is ready.
2
3
read-write
REF_CLK_SEL
Select clock input for calibration: 0x0 : RC32K oscillator 0x1 : RC16M oscillator 0x2 : XTAL32K oscillator 0x3 : RCX oscillator
0
2
read-write
CLK_REF_VAL_H_REG
XTAL16M reference cycles, upper 16 bits
0x6
16
read-write
n
0x0
0x0
XTAL_CNT_VAL
Returns the upper 16 bits of XTAL16 clock cycles during the calibration time, defined with REF_CNT_VAL
0
16
read-only
CLK_REF_VAL_L_REG
XTAL16M reference cycles, lower 16 bits
0x4
16
read-write
n
0x0
0x0
XTAL_CNT_VAL
Returns the lower 16 bits of XTAL16 clock cycles during the calibration time, defined with REF_CNT_VAL
0
16
read-only
ble580_gr01
ble580_gr01 registers
Peripheral_Registers
0x0
0x0
0x208
registers
n
BLE_ACTSCANSTAT_REG
Active scan register
0xA4
32
read-write
n
0x0
0x0
BACKOFF
Active scan mode back-off counter initialization value.
16
25
read-write
UPPERLIMIT
Active scan mode upper limit counter value.
0
9
read-write
BLE_ADVCHMAP_REG
Advertising Channel Map
0x90
32
read-write
n
0x0
0x0
ADVCHMAP
Advertising Channel Map, defined as per the advertising connection settings. Contains advertising channels index 37 to 39. If ADVCHMAP[i] equals: 0: Do not use data channel i+37. 1: Use data channel i+37.
0
3
read-write
BLE_ADVTIM_REG
Advertising Packet Interval
0xA0
32
read-write
n
0x0
0x0
ADVINT
Advertising Packet Interval defines the time interval in between two ADV_xxx packet sent. Value is in usec. Value to program depends of the used Advertising Packet type and the device filtering policy. Please refer to Table 3-10 for details about ADVINT programming range.
0
14
read-write
BLE_AESCNTL_REG
Start AES register
0xC0
32
read-write
n
0x0
0x0
AES_START
Writing a 1 starts AES-128 ciphering process. This bit is reset once the process is finished (i.e BLE_CRYPT_IRQ interrupt occurs, even masked)
0
1
read-write
BLE_AESKEY127_96_REG
AES encryption key
0xD0
32
read-write
n
0x0
0x0
AESKEY127_96
AES encryption 128-bit key. Bit 127 down to 96
0
32
read-write
BLE_AESKEY31_0_REG
AES encryption key
0xC4
32
read-write
n
0x0
0x0
AESKEY31_0
AES encryption 128-bit key. Bit 31 down to 0
0
32
read-write
BLE_AESKEY63_32_REG
AES encryption key
0xC8
32
read-write
n
0x0
0x0
AESKEY63_32
AES encryption 128-bit key. Bit 63 down to 32
0
32
read-write
BLE_AESKEY95_64_REG
AES encryption key
0xCC
32
read-write
n
0x0
0x0
AESKEY95_64
AES encryption 128-bit key. Bit 95 down to 64
0
32
read-write
BLE_AESPTR_REG
Pointer to the block to encrypt/decrypt
0xD4
32
read-write
n
0x0
0x0
AESPTR
Pointer to the memory zone where the block to encrypt/decrypt is stored.
0
16
read-write
BLE_BASETIMECNTCORR_REG
Base Time Counter
0x44
32
read-write
n
0x0
0x0
BASETIMECNTCORR
Base Time Counter correction value.
0
27
read-write
BLE_BASETIMECNT_REG
Base time reference counter
0x1C
32
read-write
n
0x0
0x0
BASETIMECNT
Value of the 625us base time reference counter. Updated each time BLE_SAMPLECLK_REG[SAMP] is written. Used by the SW in order to synchronize with the HW.
0
27
read-only
BLE_BDADDRL_REG
BLE device address LSB register
0x24
32
read-write
n
0x0
0x0
BDADDRL
Bluetooth Low Energy Device Address. LSB part.
0
32
read-write
BLE_BDADDRU_REG
BLE device address MSB register
0x28
32
read-write
n
0x0
0x0
BDADDRU
Bluetooth Low Energy Device Address. MSB part.
0
16
read-write
PRIV_NPUB
Bluetooth Low Energy Device Address privacy indicator 0: Public Bluetooth Device Address 1: Private Bluetooth Device Address
16
17
read-write
BLE_CNTL2_REG
BLE Control Register 2
0x200
32
read-write
n
0x0
0x0
BB_ONLY
Keep to 0.
18
19
read-write
BLE_CLK_SEL
BLE Clock Select. Specifies the BLE master clock absolute frequency in MHz. Typical values are 16 and 8. Value depends on the selected XTAL frequency and the value of CLK_RADIO_REG[BLE_DIV] bitfield. For example, if XTAL oscillates at 16MHz and CLK_RADIO_REG[BLE_DIV] = 1 (divide by 2), then BLE master clock frequency is 8MHz and BLE_CLK_SEL should be set to value 8. The selected BLE master clock frequency (affected by BLE_DIV and BLE_CLK_SEL) must be modified and set only during the initialization time, i.e. before setting BLE_RWBTLECNTL_REG[RWBLE_EN] to 1. Refer also to BLE_RWBTLECONF_REG[CLK_SEL].
9
15
read-write
BLE_CLK_STAT
0: BLE uses low power clock 1: BLE uses master clock
6
7
read-only
BLE_RSSI_SEL
0: Select Peak-hold RSSI value (default). 1: Select current Average RSSI value.
21
22
read-write
DIAGPORT_REVERSE
BLE/RADIO Diagnostic Port Reverse order. When this bit is '1', the mapping of the diagnostic bus DIAGPORT[7:0] (controlled by DIAGPORT_SEL) to GPIOs (controlled by Pxy_MODE_REG[PID]) is reversed. The mapping is: If '0' then DIAGPORT[7] is mapped to P0[7], etc. DIAGPORT[4] is mapped to P0[4], DIAGPORT[3] is mapped to P0[3] and P1[3], etc. and DIAGPORT[0] is mapped to P0[0] and P1[0]. If '1' then DIAGPORT[7] is mapped to P0[0] and P1[0], etc. DIAGPORT[4] is mapped to P0[3] and P1[3], DIAGPORT[3] is mapped to P0[4], etc. and DIAGPORT[0] is mapped to P0[7].
5
6
read-write
DIAGPORT_SEL
BLE/RADIO Diagnostic Port Selection. Controls the multiplexing of the internal diagnostic signals towards the 8-bit diagnostic bus DIAGPORT[7:0]. The DIAGPORT[7:0] bit order may or may not be reversed by using the DIAGPORT_REVERSE bitfield and then it will be directed to the GPIOs P0[7:0] and P1[3:0]. (Note that the P1[3:0] diagnostic signals are the same with P0[3:0] signals.) The DIAGPORT[7:0] value, depending on the DIAGPORT_SEL value, is: 00: {BLE_DIAG2[7:5], BLE_DIAG1[4:3], BLE_DIAG0[2:0]} 01: {BLE_DIAG2[7:5], BLE_DIAG1[4:3], BLE_DIAG0[2] , wakeup_lp_irq, deep_sleep_stat_32k} 10: RADIO_DIAG0[7:0] 11: RADIO_DIAG1[7:0]
3
5
read-write
EMACCERRACK
Exchange Memory Access Error Acknowledge. When the SW writes a '1' to this bit then the EMACCERRSTAT bit will be cleared. When the SW writes '0' it will have no affect. The read value is always '0'.
1
2
write-only
EMACCERRMSK
Exchange Memory Access Error Mask: When cleared to '0' the EM_ACC_ERR will not cause an BLE_ERROR_IRQ interrupt. When set to '1' an BLE_ERROR_IRQ will be generated as long as EM_ACC_ERR is '1'.
2
3
read-write
EMACCERRSTAT
Exchange Memory Access Error Status: The bit is read-only and can be cleared only by writing a '1' at EMACCERRACK bitfield. This bit will be set to '1' by the hardware when the controller will access an EM page that is not mapped according to the EM_MAPPING value. When this bit is '1' then the BLE_ERROR_IRQ will be asserted as long as EMACCERRMSK is '1'.
0
1
read-only
MON_LP_CLK
The SW can only write a '0' to this bit. Whenever a positive edge of the low power clock used by the BLE Timers is detected, then the HW will automatically set this bit to '1'. This functionality will not work if BLE Timer is in reset state (refer to CLK_RADIO_REG[BLE_LP_RESET]). This bit can be used for SW synchronization, to debug the low power clock, etc.
7
8
read-write
RADIO_ONLY
Keep to 0.
17
18
read-write
RADIO_PWRDN_ALLOW
This active high signal indicates when it is allowed for the BLE core (embedded in the Radio sub-System power domain) to be powered down. After the assertion of the BLE_DEEPSLCNTL_REG[DEEP_SLEEP_ON] a hardware sequence based on the Low Power clock will cause the assertion of RADIO_PWRDN_ALLOW. The RADIO_PWRDN_ALLOW will be cleared to '0' when the BLE core exits from the sleep state, i.e. when the BLE_SLP_IRQ will be asserted.
8
9
read-only
SW_RPL_SPI
Keep to 0.
19
20
read-write
WAKEUPLPSTAT
The status of the BLE_WAKEUP_LP_IRQ. The Interrupt Service Routine of BLE_WAKEUP_LP_IRQ should return only when the WAKEUPLPSTAT is cleared. Note that BLE_WAKEUP_LP_IRQ is automatically acknowledged after the power up of the Radio Subsystem, plus one Low Power Clock period.
20
21
read-only
BLE_CURRENTRXDESCPTR_REG
Rx Descriptor Pointer for the Receive Buffer Chained List
0x2C
32
read-write
n
0x0
0x0
CURRENTRXDESCPTR
Rx Descriptor Pointer that determines the starting point of the Receive Buffer Chained List.
0
14
read-write
BLE_DEBUGADDMAX_REG
Upper limit for the memory zone
0x58
32
read-write
n
0x0
0x0
ADDMAX
Upper limit for the memory zone.
0
16
read-write
BLE_DEBUGADDMIN_REG
Lower limit for the memory zone
0x5C
32
read-write
n
0x0
0x0
ADDMIN
Lower limit for the memory zone.
0
16
read-write
BLE_DEEPSLCNTL_REG
Deep-Sleep control register
0x30
32
read-write
n
0x0
0x0
DEEP_SLEEP_CORR_EN
625us base time reference integer and fractional part correction. Applies when system has been woken-up from Deep Sleep Mode. It enables Fine Counter and Base Time counter when written with a 1. Always read as 0. No action happens if it is written with 0.
3
4
read-write
DEEP_SLEEP_IRQ_EN
Always set to '3' when DEEP_SLEEP_ON is set to '1'. It controls the generation of BLE_WAKEUP_LP_IRQ.
0
2
read-write
DEEP_SLEEP_ON
0: BLE Core in normal active mode 1: Request BLE Core to switch in deep sleep mode. This bit is reset on DEEP_SLEEP_STAT falling edge.
2
3
read-write
DEEP_SLEEP_STAT
Indicator of current Deep Sleep clock mux status: 0: BLE Core is not yet in Deep Sleep Mode 1: BLE Core is in Deep Sleep Mode (only Low Power Clock is running)
15
16
read-only
EXTWKUPDSB
External Wake-Up disable 0: BLE Core can be woken by external wake-up 1: BLE Core cannot be woken up by external wake-up
31
32
read-write
SOFT_WAKEUP_REQ
Wake Up Request from BLE Software. Applies when system is in Deep Sleep Mode. It wakes up the BLE Core when written with a 1. Always read as 0. No action happens if it is written with 0.
4
5
read-write
BLE_DEEPSLSTAT_REG
Duration of the last deep sleep phase register
0x38
32
read-write
n
0x0
0x0
DEEPSLDUR
Actual duration of the last deep sleep phase measured in Low Power Clock cycles. DEEPSLDUR is set to zero at the beginning of the deep sleep phase, and is incremented at each Low Power Clock cycle until the end of the deep sleep phase.
0
32
read-only
BLE_DEEPSLWKUP_REG
Time (measured in Low Power clock cycles) in Deep Sleep Mode before waking-up the device
0x34
32
read-write
n
0x0
0x0
DEEPSLTIME
Determines the time in Low Power Clock cycles to spend in Deep Sleep Mode before waking-up the device. This ensures a maximum of 37 hours and 16mn sleep mode capabilities at 32kHz. This ensures a maximum of 36 hours and 16mn sleep mode capabilities at 32.768kHz. If DEEPSLTIME is set to zero, the Deep Sleep Time duration is considered as infinite, and only wake up requests can restore active behaviour BLE Software must ensure DEEPSLTIME value to be greater than 2 in order to cope with control resynchronization requirements
0
32
read-write
BLE_DIAGCNTL_REG
Diagnostics Register
0x50
32
read-write
n
0x0
0x0
DIAG0
Only relevant when DIAG0_EN = 1. Selection of the outputs that must be driven to the diagnostic port 0.
0
6
read-write
DIAG0_EN
0: Disable diagnostic port 0 output. All outputs are set to 0. 1: Enable diagnostic port 0 output.
7
8
read-write
DIAG1
Only relevant when DIAG1_EN = 1. Selection of the outputs that must be driven to the diagnostic port 1.
8
14
read-write
DIAG1_EN
0: Disable diagnostic port 1 output. All outputs are set to 0. 1: Enable diagnostic port 1 output.
15
16
read-write
DIAG2
Only relevant when DIAG2_EN = 1. Selection of the outputs that must be driven to the diagnostic port 2.
16
22
read-write
DIAG2_EN
0: Disable diagnostic port 2 output. All outputs are set to 0. 1: Enable diagnostic port 2 output.
23
24
read-write
DIAG3
Only relevant when DIAG3_EN = 1. Selection of the outputs that must be driven to the diagnostic port 3.
24
30
read-write
DIAG3_EN
0: Disable diagnostic port 3 output. All outputs are set to 0. 1: Enable diagnostic port 3 output.
31
32
read-write
BLE_DIAGSTAT_REG
Debug use only
0x54
32
read-write
n
0x0
0x0
DIAG0STAT
Directly connected to ble_dbg0[7:0] output. Debug use only.
0
8
read-only
DIAG1STAT
Directly connected to ble_dbg1[7:0] output. Debug use only.
8
16
read-only
DIAG2STAT
Directly connected to ble_dbg2[7:0] output. Debug use only.
16
24
read-only
DIAG3STAT
Directly connected to ble_dbg3[7:0] output. Debug use only.
24
32
read-only
BLE_ENBPRESET_REG
Time in low power oscillator cycles register
0x3C
32
read-write
n
0x0
0x0
TWEXT
Minimum and recommended value is 'TWIRQ_RESET + 1'. In the case of wake-up due to an external wake-up request, TWEXT specifies the time delay in low power oscillator cycles to deassert BLE_WAKEUP_LP_IRQ. Refer also to GP_CONTROL_REG[BLE_WAKEUP_REQ]. Range is [0...64 ms] for 32kHz [0...62.5 ms] for 32.768kHz
21
32
read-write
TWIRQ_RESET
Recommended value is 1. Time in low power oscillator cycles to reset BLE_WAKEUP_LP_IRQ before the BLE sleep timer expiration. Refer also to BLE_DEEPSLWKUP_REG[DEEPSLTIME]. Range is [0...32 ms] for 32kHz [0...31.25 ms] for 32.768kHz.
0
10
read-write
TWIRQ_SET
Minimum value is 'TWIRQ_RESET + 1'. Time in low power oscillator cycles to set BLE_WAKEUP_LP_IRQ before the BLE sleep timer expiration. Refer also to BLE_DEEPSLWKUP_REG[DEEPSLTIME]. Range is [0...64 ms] for 32kHz [0...62.5 ms] for 32.768kHz
10
21
read-write
BLE_ERRORTYPESTAT_REG
Error Type Status registers
0x60
32
read-write
n
0x0
0x0
APFM_ERROR
Anticipated Pre-Fetch Mechanism error, happens when 3 consecutive Exchange Table entry have been programmed, 0: no error 1: Error occured
3
4
read-only
CSFORMAT_ERROR
Indicates whether CS-FORMAT has been programmed with an invalid value: this is a major software programming failure. 0: No error 1: Error occurred
11
12
read-only
CSTXPTR_ERROR
Indicates whether CS-TXPTR is null, this is a major software programming failure. 0: No error 1: Error occurred
10
11
read-only
IFS_UNDERRUN
Inter Frame Space Under run, occurs if IFS time is not enough to update and read Control Structure/Descriptors, and/or White List parsing is not finished and/or Decryption time is too long to be finished on time 0: No error 1: Error occurred
6
7
read-only
LLCHMAP_ERROR
Link Layer Channel Map error, happens when actual number of CS-LLCHMAP bit set to one is different from CS-NBCHGOOD at the beginning of Frequency Hopping process 0: No error 1: Error occurred
7
8
read-only
PKTCNTL_EMACC_ERROR
Packet Controller Exchange Memory access error, happens when Exchange Memory access are not served in time and Tx/Rx data are corrupted 0: No error 1: Error occurred
1
2
read-only
RADIO_EMACC_ERROR
Radio Controller Exchange Memory access error, happens when Exchange Memory access are not served in time and data are corrupted. 0: No error 1: Error occurred
8
9
read-only
RXCRYPT_ERROR
Real Time Decryption Error, happens when decryption is not finished before IFS time 0: No error 1: Error occurred
5
6
read-only
TXCRYPT_ERROR
Real Time Encryption Error, happens when encryption is not finished before Tx Payload has to be sent 0: No error 1: Error occurred
0
1
read-only
TXDESC_ERROR
Tx Descriptor Error, happens when fetched Tx Descriptor has TXDONE bit not set 0: No error 1: Error occurred
2
3
read-only
WHITELIST_ERROR
White List Timeout Error, occurs if White List parsing is not finished on time 0: No error 1: Error occurred
4
5
read-only
BLE_FINECNTCORR_REG
Phase correction value register
0x40
32
read-write
n
0x0
0x0
FINECNTCORR
Phase correction value for the 625usec reference counter (i.e Fine Counter) in us.
0
10
read-write
BLE_FINETIMECNT_REG
Fine time reference counter
0x20
32
read-write
n
0x0
0x0
FINECNT
Value of the current usec fine time reference counter. Updated each usec. Used by the SW in order to synchronize with the HW, and obtain a more precise sleep duration
0
10
read-only
BLE_FINETIMTGT_REG
Fine Timer Target value
0xF8
32
read-write
n
0x0
0x0
FINETARGET
Fine Timer Target value on which a BLE_FINETGTIM_IRQ must be generated. This timer has a precision of 625us: interrupt is generated only when FINETARGET = BASETIMECNT
0
27
read-write
BLE_GROSSTIMTGT_REG
Gross Timer Target value
0xF4
32
read-write
n
0x0
0x0
GROSSTARGET
Gross Timer Target value on which a BLE_GROSSTGTIM_IRQ must be generated. This timer has a precision of 10ms: interrupt is generated only when GROSSTARGET[15:0] = BASETIMECNT[19:4] and BASETIMECNT[3:0] = 0.
0
16
read-write
BLE_INTACK_REG
Interrupt acknowledge register
0x18
32
read-write
n
0x0
0x0
CRYPTINTACK
Encryption/Decryption interrupt acknowledgement bit Software writing 1 acknowledges the Encryption / Decryption interrupt. This bit resets CRYPTINTSTAT and CRYPTINTRAWSTAT flags.
4
5
write-only
CSCNTINTACK
625us base time reference interrupt acknowledgment bit Software writing 1 acknowledges the CLKN interrupt. This bit resets CLKINTSTAT and CLKINTRAWSTAT flags.
0
1
write-only
ERRORINTACK
Error interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt. This bit resets ERRORINTSTAT and ERRORINTRAWSTAT flags.
5
6
write-only
EVENTINTACK
End of Event interrupt acknowledgment bit Software writing 1 acknowledges the End of Advertising / Scanning / Connection interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags.
3
4
write-only
FINETGTIMINTACK
Fine Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt. This bit resets FINETGTIMINTSTAT and FINETGTIMINTRAWSTAT flags.
7
8
write-only
GROSSTGTIMINTACK
Gross Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt. This bit resets GROSSTGTIMINTSTAT and GROSSTGTIMINTRAWSTAT flags.
6
7
write-only
RADIOCNTLINTACK
Radio Controller interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt. This bit resets RADIOCNTLINTSTAT and RADIOCNTLINTRAWSTAT flags.
8
9
write-only
RXINTACK
Packet Reception interrupt acknowledgment bit Software writing 1 acknowledges the Rx interrupt. This bit resets RXINTSTAT and RXINTRAWSTAT flags.
1
2
write-only
SLPINTACK
End of Deep Sleep interrupt acknowledgment bit Software writing 1 acknowledges the End of Sleep Mode interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags.
2
3
write-only
BLE_INTCNTL_REG
Interrupt controller register
0xC
32
read-write
n
0x0
0x0
CRYPTINTMSK
Encryption / Decryption Interrupt Mask 0: Interrupt not generated 1: Interrupt generated
4
5
read-write
CSCNTDEVMSK
CSCNT interrupt mask during event. This bit allows to enable CSCNT interrupt generation during events (i.e advertising, scanning, initiating, and connection) 0: CSCNT Interrupt not generated during events. 1: CSCNT Interrupt generated during events.
15
16
read-write
CSCNTINTMSK
625usec Base Time Interrupt Mask
0: Interrupt not generated
1: Interrupt generated
0
1
read-write
ERRORINTMSK
Error Interrupt Mask 0: Interrupt not generated 1: Interrupt generated
5
6
read-write
EVENTINTMSK
End of event Interrupt Mask 0: Interrupt not generated 1: Interrupt generated
3
4
read-write
FINETGTIMINTMSK
Fine Target Timer Mask 0: Interrupt not generated 1: Interrupt generated
7
8
read-write
GROSSTGTIMINTMSK
Gross Target Timer Mask 0: Interrupt not generated 1: Interrupt generated
6
7
read-write
INTCSCNTL
Selection of the CS counter that generates an interrupt. For example, if INTCNTL[3] is set, an interrupt is sent each time CS counter equals 3.
16
32
read-write
RADIOCNTLINTMSK
Radio Controller interrupt mask 0: Interrupt not generated 1: Interrupt generated
8
9
read-write
RXINTMSK
Rx Interrupt Mask 0: Interrupt not generated 1: Interrupt generated
1
2
read-write
SLPINTMSK
Sleep Mode Interrupt Mask 0: Interrupt not generated 1: Interrupt generated
2
3
read-write
BLE_INTRAWSTAT_REG
Interrupt raw status register
0x14
32
read-write
n
0x0
0x0
CRYPTINTRAWSTAT
Encryption/Decryption interrupt raw status 0: No Encryption / Decryption interrupt. 1: An Encryption / Decryption interrupt is pending.
4
5
read-only
CSCNTINTRAWSTAT
625us base time reference interrupt raw status 0: No 625us Base Time interrupt. 1: A 625us Base Time interrupt is pending.
0
1
read-only
ERRORINTRAWSTAT
Error interrupt raw status 0: No Error interrupt. 1: An Error interrupt is pending.
5
6
read-only
EVENTINTRAWSTAT
End of Event interrupt raw status 0: No End of Advertising / Scanning / Connection interrupt. 1: An End of Advertising / Scanning / Connection interrupt is pending.
3
4
read-only
FINETGTIMINTRAWSTAT
Fine Target Timer Error interrupt raw status 0: No Fine Target Timer interrupt. 1: A Fine Target Timer interrupt is pending.
7
8
read-only
GROSSTGTIMINTRAWSTAT
Gross Target Timer interrupt raw status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending.
6
7
read-only
RADIOCNTLINTRAWSTAT
Radio Controller interrupt raw status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending.
8
9
read-only
RXINTRAWSTAT
Packet Reception interrupt raw status 0: No Rx interrupt. 1: An Rx interrupt is pending.
1
2
read-only
SLPINTRAWSTAT
Sleep interrupt raw status 0: No End of Sleep Mode interrupt. 1: An End of Sleep Mode interrupt is pending.
2
3
read-only
BLE_INTSTAT_REG
Interrupt status register
0x10
32
read-write
n
0x0
0x0
CRYPTINTSTAT
Masked Encryption/Decryption interrupt status 0: No Encryption / Decryption interrupt. 1: An Encryption / Decryption interrupt is pending.
4
5
read-only
CSCNTINTSTAT
Masked 625us base time reference interrupt status 0: No 625us Base Time interrupt. 1: A 625us Base Time interrupt is pending.
0
1
read-only
ERRORINTSTAT
Masked Error interrupt status 0: No Error interrupt. 1: An Error interrupt is pending.
5
6
read-only
EVENTINTSTAT
Masked End of Event interrupt status 0: No End of Advertising / Scanning / Connection interrupt. 1: An End of Advertising / Scanning / Connection interrupt is pending.
3
4
read-only
FINETGTIMINTSTAT
Masked Fine Target Timer Error interrupt status 0: No Fine Target Timer interrupt. 1: A Fine Target Timer interrupt is pending.
7
8
read-only
GROSSTGTIMINTSTAT
Masked Gross Target Timer interrupt status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending.
6
7
read-only
RADIOCNTLINTSTAT
Radio Controller interrupt status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending.
8
9
read-only
RXINTSTAT
Masked Packet Reception interrupt status 0: No Rx interrupt. 1: An Rx interrupt is pending.
1
2
read-only
SLPINTSTAT
Masked Sleep interrupt status 0: No End of Sleep Mode interrupt. 1: An End of Sleep Mode interrupt is pending.
2
3
read-only
BLE_RADIOCNTL0_REG
Radio interface control register
0x70
32
read-write
n
0x0
0x0
DPCORR_EN
Enable the use of delayed DC compensated data path in Radio Correlator block 1: Enable 0: Disable Must be set to '0'.
22
23
read-write
BLE_RADIOCNTL1_REG
Radio interface control register
0x74
32
read-write
n
0x0
0x0
XRFSEL
Extended radio selection field, Must be set to '00011'.
16
21
read-write
BLE_RADIOPWRUPDN_REG
RX/TX power up/down phase register
0x80
32
read-write
n
0x0
0x0
RTRIP_DELAY
Defines round trip delay value. This value correspond to the addition of data latency in Tx and data latency in Rx. Value is in us.
24
31
read-write
RXPWRUP
This register holds the length in us of the Rx power up phase for the current radio device. Default value is 210 us (reset value). Operating range depends of the selected radio.
16
24
read-write
TXPWRDN
This register extends the length in us of the Tx power down phase for the current radio device. Default value is 3us (reset value). Operating range depends of the selected radio.
8
12
read-write
TXPWRUP
This register holds the length in us of the Tx power up phase for the current radio device. Default value is 210 us (reset value). Operating range depends of the selected radio.
0
8
read-write
BLE_RFTESTCNTL_REG
RF Testing Register
0xE0
32
read-write
n
0x0
0x0
INFINITERX
Applicable for all frame format 0: Normal mode of operation 1: Infinite Rx window
31
32
read-write
INFINITETX
Applicable for all frame format 0: Normal mode of operation. 1: Infinite Tx packet / Normal start of a packet but endless payload In case of infinite Tx payload, and when PRBS source is not selected, then RFTESTCNTL-TXLENGTH field provides the length of the pattern to repeat in the payload.
15
16
read-write
PRBSTYPE
Applicable only in Tx/Rx RF Test mode 0: Tx Packet Payload are PRBS9 type 1: Tx Packet Payload are PRBS15 type PRBS9 is defined as p(x)=1+x5+x9. The LFSR used for the PRBS9 generator must be initialized with 0x1FF value. PRBS15 is defined as p(x)=1+x+x2+x12+x13+x14. The LFSR used for the PRBS15 generator must be initialized with 0x7FFF value.
13
14
read-write
TXLENGTH
Applicable only in Tx/Rx RF Test mode Tx packet length in number of byte
0
9
read-write
TXLENGTHSRC
Applicable only in Tx/Rx RF Test mode 0: Normal mode of operation: TXDESC-TXADVLEN controls the Tx packet payload size 1: Uses RFTESTCNTL-TXLENGTH packet length (can support up to 512 bytes transmit)
14
15
read-write
TXPLDSRC
Applicable only in Tx/Rx RF Test mode 0: Tx Packet Payload source is the Control Structure 1: Tx Packet Payload are PRBS generator
12
13
read-write
BLE_RF_DIAGIRQ_REG
BLE/RF Diagnostic IRQ Control Register
0x204
32
read-write
n
0x0
0x0
DIAGIRQ_BSEL_0
Diagnostic IRQ Bit Select 0 Selects the bit of the 8-bit bus (as selected by the DIAGIRQ_WSEL_0) that will be used for the IRQ generation.
3
6
read-write
DIAGIRQ_BSEL_1
Same as DIAGIRQ_BSEL_0.
11
14
read-write
DIAGIRQ_BSEL_2
Same as DIAGIRQ_BSEL_0.
19
22
read-write
DIAGIRQ_BSEL_3
Same as DIAGIRQ_BSEL_0.
27
30
read-write
DIAGIRQ_EDGE_0
Diagnostic IRQ Edge 0 Selects the edge of the selected bit (refer to DIAGIRQ_BSEL_0) that will trigger the assertion of DIAGIRQ_STAT_0. If '0' then the positive edge is selected, when '1' the negative edge is selected.
6
7
read-write
DIAGIRQ_EDGE_1
Same as DIAGIRQ_EDGE_0.
14
15
read-write
DIAGIRQ_EDGE_2
Same as DIAGIRQ_EDGE_0.
22
23
read-write
DIAGIRQ_EDGE_3
Same as DIAGIRQ_EDGE_0.
30
31
read-write
DIAGIRQ_MASK_0
Diagnostic IRQ Mask 0 When set to '1' a BLE_RF_DIAG_IRQ will be generated on each rise of the DIAGIRQ_STAT_0 bit. When cleared to '0' no IRQ will be generated.
0
1
read-write
DIAGIRQ_MASK_1
Same as DIAGIRQ_MASK_0.
8
9
read-write
DIAGIRQ_MASK_2
Same as DIAGIRQ_MASK_0.
16
17
read-write
DIAGIRQ_MASK_3
Same as DIAGIRQ_MASK_0.
24
25
read-write
DIAGIRQ_STAT_0
Diagnostic IRQ Status 0 This bit is read only. It is automatically cleared to '0' on each read of the BLE_RF_DIAGIRQ_REG register. It is automatically asserted to '1' on each detection of the selected edge, of the selected bit, of the selected word.
7
8
read-only
DIAGIRQ_STAT_1
Same as DIAGIRQ_STAT_0.
15
16
read-only
DIAGIRQ_STAT_2
Same as DIAGIRQ_STAT_0.
23
24
read-only
DIAGIRQ_STAT_3
Same as DIAGIRQ_STAT_0.
31
32
read-only
DIAGIRQ_WSEL_0
Diagnostic IRQ Word Select 0 Selects the 8-bit diagnostic bus that will be used for the IRQ generation. 00: Selects the BLE_DIAG0 01: Selects the BLE_DIAG1 10: Selects the RADIO_DIAG0 11: Selects the RADIO_DIAG1
1
3
read-write
DIAGIRQ_WSEL_1
Same as DIAGIRQ_WSEL_0.
9
11
read-write
DIAGIRQ_WSEL_2
Same as DIAGIRQ_WSEL_0.
17
19
read-write
DIAGIRQ_WSEL_3
Same as DIAGIRQ_WSEL_0.
25
27
read-write
BLE_RWBTLECNTL_REG
BLE Control register
0x0
32
read-write
n
0x0
0x0
ADVERRFILT_EN
Advertising Channels Error Filtering Enable control 0: BLE Core reports all errors to BLE Software 1: BLE Core reports only correctly received packet, without error to BLE Software
10
11
read-write
ADVERT_ABORT
Abort the current Advertising event when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
25
26
read-write
CRC_DSB
0: Normal operation. CRC removed from data stream. 1: CRC stripping disabled on Rx packets, CRC replaced by 0x000 in Tx
17
18
read-write
CRYPT_DSB
0: Normal operation. Encryption / Decryption enabled. 1: Encryption / Decryption disabled. Note that if CS-CRYPT_EN is set, then MIC is generated, and only data encryption is disabled, meaning data sent are plain data.
19
20
read-write
HOP_REMAP_DSB
0: Normal operation. Frequency Hopping Remapping algorithm enabled. 1: Frequency Hopping Remapping algorithm disabled
16
17
read-write
MASTER_SOFT_RST
Reset the complete system except registers and timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
31
32
read-write
MASTER_TGSOFT_RST
Reset the timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
30
31
read-write
MD_DSB
0: Normal operation of MD bits management 1: Allow a single Tx/Rx exchange whatever the MD bits are
22
23
read-write
NESN_DSB
0: Normal operation of Sequence number 1: Sequence Number Management disabled: value forced by SW from Tx Descriptor value ignored in Rx, meaning that no SN error reported.
20
21
read-write
REG_SOFT_RST
Reset the complete register block, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
29
30
read-write
RFTEST_ABORT
Abort the current RF Testing defined as per CS-FORMAT when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Note that when RFTEST_ABORT is requested. 1) In case of infinite Tx, the Packet Controller FSM stops at the end of the current byte in process, and processes accordingly the packet CRC. 2) In case of Infinite Rx, the Packet Controller FSM either stops as the end of the current Packet reception (if Access address has been detected), or simply stop the processing switching off the RF.
26
27
read-write
RWBLE_EN
0: Disable BLE Core Exchange Table pre-fetch mechanism. 1: Enable BLE Core Exchange table pre-fetch mechanism.
8
9
read-write
RXDESCPTRSEL
0: Selects Rx Descriptor Pointer value from Control Structure 1: Selects Rx Descriptor Pointer value from CURRENTRXDESCPTR register
11
12
read-write
RXWINSZDEF
Default Rx Window size in us. Used when device a) is master connected b) performs its second receipt. 0 is not a valid value. Recommended value is 10.
4
8
read-write
SCAN_ABORT
Abort the current scan window when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0.
24
25
read-write
SN_DSB
0: Normal operation of Sequence number 1: Sequence Number Management disabled: value forced by SW from Tx Descriptor value ignored in Rx, meaning that no SN error reported.
21
22
read-write
SYNCERR
Indicates the maximum number of errors allowed to recognize the synchronization word.
0
3
read-write
TXWINOFFSEL
Applicable only if device is in Initiator mode 0: Window Offset field in CONNECT_REQ comes from Tx Data Buffer 1: Window Offset field in CONNECT_REQ comes from Event Controller processing and is replaced in real time by Packet Controller
12
13
read-write
WHIT_DSB
0: Normal operation. Whitening enabled. 1: Whitening disabled.
18
19
read-write
WLSYNC_EN
0: WLAN synchronization pulse generation disabled 1: WLAN synchronization pulse generation enabled
9
10
read-write
BLE_RWBTLECONF_REG
Configuration register
0x8
32
read-write
n
0x0
0x0
ADD_WIDTH
Value of the BLE_ADDRESS_WIDTH parameter converted into binary.
24
30
read-only
BUSWIDTH
Processor bus width: 0: 16 bits 1: 32 bits
0
1
read-only
CLK_SEL
Operating Frequency (in MHz). This field is a copy of the BLE_CNTL2_REG[BLE_CLK_SEL] value.
8
14
read-only
DMMODE
0: BLE Core is used as a standalone BLE device 1: BLE Core is used in a Dual Mode device
5
6
read-only
INTMODE
0: Interrupts are edge level generated, i.e pulse. 1: Interrupts are trigger level generated, i.e stays active at 1 till acknowledgement
4
5
read-only
RFIF
Supported radio interfaces. 0001000: on-chip radio others: reserved
16
23
read-only
USECRYPT
0: Encryption block not present 1: Encryption block present
1
2
read-only
USEDBG
0: Diagnostic port not instantiated 1: Diagnostic port instantiated
2
3
read-only
WLAN
0: WLAN Coexistence mechanism not present 1: WLAN Coexistence mechanism present
3
4
read-only
BLE_RXMICVAL_REG
AES / CCM plain MIC value
0xDC
32
read-write
n
0x0
0x0
RXMICVAL
AES / CCM plain MIC value. Valid on BLE_CRYPT_IRQ interrupt (even masked)
0
32
read-only
BLE_SAMPLECLK_REG
Samples the Base Time Counter
0xFC
32
read-write
n
0x0
0x0
SAMP
Writing a 1 samples the Base Time Counter value in BASETIMECNT register. Resets at 0 when action is performed.
0
1
read-write
BLE_SWPROFILING_REG
Software Profiling register
0x64
32
read-write
n
0x0
0x0
SWPROFVAL
Software Profiling register: used by BLE Software for profiling purpose: this value is copied on Diagnostic port
0
32
read-write
BLE_TIMGENCNTL_REG
Timing Generator Register
0xF0
32
read-write
n
0x0
0x0
PREFTECH_TIME
Defines Exchange Table pre-fetch instant in us
0
8
read-write
BLE_TXMICVAL_REG
AES / CCM plain MIC value
0xD8
32
read-write
n
0x0
0x0
TXMICVAL
AES / CCM plain MIC value. Valid on BLE_CRYPT_IRQ interrupt (even masked)
0
32
read-only
BLE_VERSION_REG
Version register
0x4
32
read-write
n
0x0
0x0
BUILD
BLE Core Build - Build number
0
8
read-only
REL
BLE Core version - Major release number.(Correspond to FS v1.11)
16
24
read-only
TYP
BLE Core Type - 0x6 means BT4.0 (i.e correspond LL version assigned number)
24
32
read-only
UPG
BLE Core upgrade - Upgrade number. (Correspond to FS v1.11)
8
16
read-only
BLE_WLNBDEV_REG
Devices in white list
0xB8
32
read-write
n
0x0
0x0
NBPRIVDEV
Number of private devices in the white list.
8
16
read-write
NBPUBDEV
Number of public devices in the white list.
0
8
read-write
BLE_WLPRIVADDPTR_REG
Start address of private devices list
0xB4
32
read-write
n
0x0
0x0
WLPRIVADDPTR
Start address pointer of the private devices white list.
0
16
read-write
BLE_WLPUBADDPTR_REG
Start address of public devices list
0xB0
32
read-write
n
0x0
0x0
WLPUBADDPTR
Start address pointer of the public devices white list.
0
16
read-write
CHIP_VERSION
CHIP_VERSION registers
Peripheral_Registers
0x0
0x0
0xC
registers
n
CHIP_CONFIG1_REG
Chip configuration register 1.
0x5
8
read-write
n
0x0
0x0
CHIP_CONFIG1
First character of Chip Configuration '0M2' in ASCII.
0
8
read-only
CHIP_CONFIG2_REG
Chip configuration register 2.
0x6
8
read-write
n
0x0
0x0
CHIP_CONFIG2
Second character of Chip Configuration '0M2' in ASCII.
0
8
read-only
CHIP_CONFIG3_REG
Chip configuration register 3.
0x7
8
read-write
n
0x0
0x0
CHIP_CONFIG3
Third character of Chip Configuration '0M2' in ASCII.
0
8
read-only
CHIP_ID1_REG
Chip identification register 1.
0x0
8
read-write
n
0x0
0x0
CHIP_ID1
First character of device type '580' in ASCII.
0
8
read-only
CHIP_ID2_REG
Chip identification register 2.
0x1
8
read-write
n
0x0
0x0
CHIP_ID2
Second character of device type '580' in ASCII.
0
8
read-only
CHIP_ID3_REG
Chip identification register 3.
0x2
8
read-write
n
0x0
0x0
CHIP_ID3
Third character of device type '580' in ASCII.
0
8
read-only
CHIP_REVISION_REG
Chip revision register.
0x4
8
read-write
n
0x0
0x0
REVISION_ID
Chip version, corresponds with type number in ASCII. 0x41 = 'A', 0x42 = 'B'
0
8
read-only
CHIP_SWC_REG
Software compatibility register.
0x3
8
read-write
n
0x0
0x0
CHIP_SWC
SoftWare Compatibility code. Integer (default = 0) which is incremented if a silicon change has impact on the CPU Firmware. Can be used by software developers to write silicon revision dependent code.
0
4
read-only
CHIP_TEST1_REG
Chip test register 1.
0xA
8
read-write
n
0x0
0x0
CHIP_TEST2_REG
Chip test register 2.
0xB
8
read-write
n
0x0
0x0
crg580_dcdc_nl01
crg580_dcdc_nl01 registers
Peripheral_Registers
0x0
0x0
0xC
registers
n
DCDC_CAL1_REG
DCDC first calibration register
0x6
16
read-write
n
0x0
0x0
DCDC_CAL1
When DCDC_AUTO_CAL[0] is '0', this register is used to change the offset of the current sensing comparators in the DCDC-converter. Preferred values will be provided by Dialog.
0
6
read-write
DCDC_CAL2_REG
DCDC second calibration register
0x8
16
read-write
n
0x0
0x0
DCDC_CAL2
When DCDC_AUTO_CAL[1] is '0', this register is used to change the offset of the current sensing comparators in the DCDC-converter. Preferred values will be provided by Dialog.
0
6
read-write
DCDC_CAL3_REG
DCDC thirth calibration register
0xA
16
read-write
n
0x0
0x0
DCDC_CAL3
When DCDC_AUTO_CAL[2] is '0', this register is used to change the offset of the current sensing comparators in the DCDC-converter. Preferred values will be provided by Dialog.
0
6
read-write
DCDC_CTRL2_REG
DCDC second control register
0x2
16
read-write
n
0x0
0x0
DCDC_AUTO_CAL
Control of the automatic calibration of the DCDC-converter. For Buck-mode use 0x1, for Boost-mode use 0x6. Automatic calibration is disabled by setting 0x0
0
3
read-write
DCDC_CUR_LIM
Current limit in the switches of the DCDC-converter (approximate values): N x 10mA
3
7
read-write
DCDC_TON
This defines the minimum on-time of the comparators. For buck-mode use 0x2, for boost-mode use 0x1
7
9
read-write
DCDC_VBAT3V_LEV
Nominal VBAT3V output voltage of the boost converter. 000 ... 011 = 1.8V + N*25mV 100 = 2.4V 101 = 2.5V 110 = 2.62V 111 = 2.76V (Note: MSB is automatically on if the OTP LDO is enabled.)
9
12
read-write
DCDC_VOLT_LEV
Nominal output voltage of the DCDC-converter. VDCDC = 1.2V + N*25mV
12
16
read-write
DCDC_CTRL3_REG
DCDC thirth control register
0x4
16
read-write
n
0x0
0x0
BUCK_ENABLE
Enables the buck converter when the device becomes active and VBAT1V is connected to GND.
0
1
read-write
DCDC_IDLE_CLK
Clock used as trigger for the idle state to check voltage. (Note: when no 16 MHz oscillator is active, the 32 kHz oscillator will be used as trigger independent of the setting below:) 00 = 16 MHz 01 = 4 MHz 10 = 1 MHz 11 = 250 kHz
1
3
read-write
DCDC_TIMEOUT
3
5
read-write
DCDC_CTRL_REG
DCDC control register
0x0
16
read-write
n
0x0
0x0
DCDC_DRIVE_NSW
Drive level of the switch between SWITCH and GROUND. 00 = 100 percent 01 = 66 percent 10 = 33 percent 11 = off
8
10
read-write
DCDC_DRIVE_OSW
Drive level of the switch between SWITCH and VDCDC. 00 = 100 percent 01 = 66 percent 10 = 33 percent 11 = off
12
14
read-write
DCDC_DRIVE_PSW
Drive level of the switch between SWITCH and VBAT3V. 00 = 100 percent 01 = 66 percent 10 = 33 percent 11 = off
10
12
read-write
DCDC_MODE
Testmodes, keep 000.
5
8
read-write
DCDC_TUNE
Tune-bits to compensate for parasitic resistance in the current sense circuit of the DCDC-converter.
14
16
read-write
DCDC_VBAT1V_LEV
If VBAT1V is below this level, the boost converter will be disabled: 110 = 0.6V 101 = 0.8V 011 = 1.0V 111 = 0V (always OK)
1
4
read-write
crg580_nl01
crg580_nl01 registers
Peripheral_Registers
0x0
0x0
0x40
registers
n
ANA_STATUS_REG
Status bit of analog (power management) circuits
0x2A
16
read-write
n
0x0
0x0
BANDGAP_OK
Indicates that BANDGAP is OK
7
8
read-only
BOOST_SELECTED
Indicates that DCDC is in boost mode
9
10
read-only
BOOST_VBAT_OK
Indicates that VBAT is above threshold while in BOOST converter mode.
6
7
read-only
LDO_ANA_OK
Indicates that LDO_ANA is in regulation. This LDO is used for the general-purpose ADC only
5
6
read-only
LDO_OTP_OK
Indicates that LDO_OTP is in regulation
3
4
read-only
LDO_VDD_OK
Indicates that LDO_VDD is in regulation
4
5
read-only
VBAT1V_AVAILABLE
Indicates that VBAT1V is available.
0
1
read-only
VBAT1V_OK
Indicates that VBAT1V is above threshold.
1
2
read-only
VDCDC_OK
Indicates that VDCDC is above threshold.
2
3
read-only
BANDGAP_REG
Bandgap trimming
0x28
16
read-write
n
0x0
0x0
BGR_ITRIM
Current trimming for bias
5
10
read-write
BGR_LOWPOWER
Test-mode, do not use. It disables the bandgap core (voltages will continue for some time, but will slowely drift away)
14
15
read-write
BGR_TRIM
Trim register for bandgap
0
5
read-write
LDO_RET_TRIM
10
14
read-write
CLK_16M_REG
16 MHz RC-oscillator register
0x22
16
read-write
n
0x0
0x0
RC16M_ENABLE
Enables the 16 MHz RC oscillator
0
1
read-write
RC16M_TRIM
Controls the frequency of the RC16M oscillator. 0x0: lowest frequency 0xF: highest frequency
1
5
read-write
XTAL16_BIAS_SH_ENABLE
Enables Ibias sample/hold function in 16 MHz crystal oscillator. This bit should be set when the system wake up and reset before entering deep or extended sleep mode.
8
9
read-write
XTAL16_CUR_SET
Bias current for the 16 MHz XTAL oscillator. 0x0: minimum 0x7: maximum
5
8
read-write
XTAL16_NOISE_FILT_ENABLE
Enables noise flter in 16 MHz crystal oscillator
9
10
read-write
CLK_32K_REG
32 kHz oscillator register
0x20
16
read-write
n
0x0
0x0
RC32K_ENABLE
Enables the 32 kHz RC oscillator
7
8
read-write
RC32K_TRIM
Controls the frequency of the RC32K oscillator. 0x0: lowest frequency 0x7: default 0xF: highest frequency
8
12
read-write
XTAL32K_CUR
Bias current for the 32kHz XTAL oscillator. 0x0: minimum 0x3: default 0xF: maximum For each application there is an optimal setting for which the startup behaviour is optimal.
3
7
read-write
XTAL32K_DISABLE_AMPREG
Setting this bit disables the amplitude regulation of the XTAL32kHz oscillator. Set this bit to '1' for an external clock applied at XTAL32Kp. Keep this bit '0' with a crystal between XTAL32Kp and XTAL32Km.
12
13
read-write
XTAL32K_ENABLE
Enables the 32 kHz XTAL oscillator
0
1
read-write
XTAL32K_RBIAS
Setting for the bias resistor of the 32 kHz XTAL oscillator. 0x0: maximum 0x3: minimum Prefered setting will be provided by Dialog.
1
3
read-write
CLK_AMBA_REG
HCLK, PCLK, divider and clock gates
0x0
16
read-write
n
0x0
0x0
HCLK_DIV
AHB interface and microprocessor clock (HCLK). HCLK is source clock divided by: 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8
0
2
read-write
OTP_ENABLE
Clock enable for OTP controller
7
8
read-write
PCLK_DIV
APB interface clock (PCLK). Divider is cascaded with HCLK_DIV. PCLK is HCLK divided by: 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8
4
6
read-write
CLK_CTRL_REG
Clock control register
0xA
16
read-write
n
0x0
0x0
RUNNING_AT_32K
Indicates that either the RC32k or XTAL32k is being used as clock
5
6
read-only
RUNNING_AT_RC16M
Indicates that the RC16M clock is used as clock
6
7
read-only
RUNNING_AT_XTAL16M
Indicates that the XTAL16M clock is used as clock, and may not be switched off
7
8
read-only
SYS_CLK_SEL
Selects the clock source. 0x0: XTAL16M (check the XTAL16_SETTLED and XTAL16_TRIM_READY bits!!) 0x1: RC16M 0x2/0x3: either RC32k or XTAL32k is used
0
2
read-write
XTAL16M_DISABLE
Setting this bit instantaneously disables the 16 MHz crystal oscillator. Also, after sleep/wakeup cycle, the oscillator will not be enabled. This bit may not be set to '1'when 'RUNNING_AT_XTAL16M is '1' to prevent deadlock. After resetting this bit, wait for XTAL16_SETTLED or XTAL16_TRIM_READY to become '1' before switching to XTAL16 clock source.
2
3
read-write
XTAL16M_SPIKE_FLT_DISABLE
Disable spikefilter in digital clock
3
4
read-write
CLK_FREQ_TRIM_REG
Xtal frequency trimming register
0x2
16
read-write
n
0x0
0x0
COARSE_ADJ
Xtal frequency course trimming register. 0x0: lowest frequency 0x7: highest frequencyIncrement or decrement the binary value with 1. Wait approximately 200 us to allow the adjustment to settle.
8
11
read-write
FINE_ADJ
Xtal frequency fine trimming register. 0x00: lowest frequency 0xFF: highest frequency
0
8
read-write
CLK_PER_REG
Peripheral divider register
0x4
16
read-write
n
0x0
0x0
I2C_ENABLE
Enable I2C clock
5
6
read-write
QUAD_ENABLE
Enable the Quadrature clock
15
16
read-write
SPI_DIV
Division factor for SPI 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8
8
10
read-write
SPI_ENABLE
Enable SPI clock
11
12
read-write
TMR_DIV
Division factor for TIMER0 and TIMER2 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8
0
2
read-write
TMR_ENABLE
Enable TIMER0 and TIMER2 clock
3
4
read-write
UART1_ENABLE
Enable UART1 clock
7
8
read-write
UART2_ENABLE
Enable UART2 clock
6
7
read-write
WAKEUPCT_ENABLE
Enable Wakeup CaptureTimer clock
4
5
read-write
CLK_RADIO_REG
Radio PLL control register
0x8
16
read-write
n
0x0
0x0
BLE_DIV
Division factor for BLE core blocks 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 The programmed frequency should not be lower than 8 MHz and not faster than the programmed CPU clock frequency. Refer also to BLE_CNTL2_REG[BLE_CLK_SEL].
4
6
read-write
BLE_ENABLE
Enable the BLE core clocks
7
8
read-write
BLE_LP_RESET
Reset for the BLE LP timer
6
7
read-write
RFCU_DIV
Division factor for RF Control Unit 0x0: divide by 1 0x1: divide by 2 0x2: divide by 4 0x3: divide by 8 The programmed frequency must be exactly 8 MHz.
0
2
read-write
RFCU_ENABLE
Enable the RF control Unit clock
3
4
read-write
CLK_RCX20K_REG
RCX-oscillator control register
0x24
16
read-write
n
0x0
0x0
RCX20K_BIAS
Bias control
8
10
read-write
RCX20K_ENABLE
Enable the RCX oscillator
11
12
read-write
RCX20K_LOWF
Extra low frequency
10
11
read-write
RCX20K_NTC
Temperature control
4
8
read-write
RCX20K_SELECT
Selects RCX oscillator. 0 : RC32K oscillator 1: RCX oscillator
12
13
read-write
RCX20K_TRIM
Controls the frequency of the RCX oscillator. 0x0: lowest frequency 0x7: default 0xF: highest frequency
0
4
read-write
PMU_CTRL_REG
Power Management Unit control register
0x10
16
read-write
n
0x0
0x0
FORCE_BOOST
Force the DCDC into boost mode at next wakeup. Setting this bit reduces the deepsleep current. FORCE_BOOST has highest priority. When either FORCE_BOOST or FORCE_BUCK have been written, these bits cannot be changed.
7
8
read-write
FORCE_BUCK
Force the DCDC into buck mode at next wakeup. Setting this bit reduces the deepsleep current. FORCE_BOOST has highest priority. When either FORCE_BOOST or FORCE_BUCK have been written, these bits cannot be changed.
6
7
read-write
OTP_COPY_DIV
Sets the HCLK division during OTP mirroring
4
6
read-write
PERIPH_SLEEP
Put all peripherals (I2C, UART, SPI, ADC) in powerdown
1
2
read-write
RADIO_SLEEP
Put the digital part of the radio in powerdown
2
3
read-write
RESET_ON_WAKEUP
Perform a Hardware Reset after waking up. Booter will be started.
0
1
read-write
RETENTION_MODE
Select the retainability of the 4 retention RAM macros. '1' is retainable, '0' is power gated. (3) is RETRAM4 (2) is RETRAM3 (1) is RETRAM2 (0) is RETRAM1
8
12
read-write
RF_IO_CTRL1_REG
(in CRG)
0x30
16
read-write
n
0x0
0x0
RFIO_TRIM1_CAP
Trim the RFIO input capacitance 00: Minimum capacitance 10: Nominal capacitance 1F: Maximal capacitance
0
8
read-write
RF_LNA_CTRL1_REG
(in CRG)
0x32
16
read-write
n
0x0
0x0
LNA_TRIM_CD_HF
Trim the LNA output capacitance for CN > 19 00: Minimum capacitance 10: Nominal capacitance 1F: Maximal capacitance
6
12
read-write
LNA_TRIM_CD_LF
Trim the LNA output capacitance for CN 00: Minimum capacitance 10: Nominal capacitance 1F: Maximal capacitance
0
6
read-write
RF_LNA_CTRL2_REG
(in CRG)
0x34
16
read-write
n
0x0
0x0
LNA_TRIM_GM_HI
Trim the LNA bias resistor for optimum transcunductance (gain) in AGC settings 0 and 1 00: Minimum transconductance 10: Nominal transconductance 1F: Maximal transconductance
0
6
read-write
LNA_TRIM_GM_LO
Trim the LNA bias resistor for optimum transcunductance (gain) in AGC settings 2 and 3 00: Minimum transconductance 10: Nominal transconductance 1F: Maximal transconductance
6
12
read-write
RF_LNA_CTRL3_REG
(in CRG)
0x36
16
read-write
n
0x0
0x0
LNA_TRIM_CGS
Trim the LNA gate-source capacitance 00: Minimum capacitance 10: Nominal capacitance 1F: Maximal capacitance
0
5
read-write
RF_RSSI_COMP_CTRL_REG
(in CRG)
0x38
16
read-write
n
0x0
0x0
RSSI_COMP00
RSSI compensation value for LNA gain setting 00 '0x0': -8 '0x1': -7 '0x2': -6 '0x3': -5 '0x4': -4 '0x5': -3 '0x6': -2 '0x7': -1 '0x8': 0 (reset) '0x9': 1 '0xA': 2 '0xB': 3 '0xC': 4 '0xD': 5 '0xE': 6 '0xF': 7
12
16
read-write
RSSI_COMP01
RSSI compensation value for LNA gain setting 01 relative to 00 '0x0': -4 '0x1': -3 '0x2': -2 '0x3': -1 '0x4': 0 '0x5': 1 '0x6': 2 '0x7': 3 (reset) '0x8': 4 '0x9': 5 '0xA': 6 '0xB': 7 '0xC': 8 '0xD': 9 '0xE': 10 '0xF': 11
0
4
read-write
RSSI_COMP10
RSSI compensation value for LNA gain setting 10 relative to 00 Coding identical to RSSI_COMP01.
4
8
read-write
RSSI_COMP11
RSSI compensation value for LNA gain setting 11 relative to 00 Coding identical to RSSI_COMP01.
8
12
read-write
RF_VCO_CTRL_REG
0x3A
16
read-write
n
0x0
0x0
VCO_AMPL_SET
Set the desired amplitude of the VCO'0': minimum amplitude '4': default amplitude 'F': maximum amplitude
0
4
read-write
SPOTP_TEST_REG
(in CRG)
0x3E
16
read-write
n
0x0
0x0
LDO_OTP_WRITE
Bypass LDO and put VBAT directly on OTP_VDDIO
1
2
read-write
SPOTP_ACTIVE
Enables the SPOTP testmode. Reset by write or PowerOnReset
0
1
read-write
SYS_CTRL_REG
System Control register
0x12
16
read-write
n
0x0
0x0
CLK32_SOURCE
Sets the clock source of the 32 kHz clock 0 = RC-oscillator 1 = 32 kHz crystal oscillator
3
4
read-write
DEBUGGER_ENABLE
Enable the debugger. This bit is set by the booter according to the OTP header. If not set, the SWDIO and SW_CLK can be used as gpio ports.
7
8
read-write
OTPC_RESET_REQ
Reset request for the OTP controller.
6
7
read-write
OTP_COPY
Enables OTP to SysRAM copy action after waking up PD_SYS
4
5
read-write
PAD_LATCH_EN
Latches the control signals of the pads for state retention in powerdown mode. 0: Control signals are retained 1: Latch is transparant, pad can be recontrolled
5
6
read-write
REMAP_ADR0
Controls which memory is located at address 0x0000 for execution. 0x0: ROM 0x1: OTP 0x2: SysRAM 0x3: RetRAM
0
2
read-write
RET_SYSRAM
Sets the development phase mode. If this bit is set, the SysRAM cell will not power gated during sleep (extended sleep). No copy action to SysRAM is done when the system wakes up. For emulating startup time, the OTP_COPY bit still needs to be set.
2
3
read-write
SW_RESET
Writing a '1' to this bit will reset the device, except for: SYS_CTRL_REG CLK_FREQ_TRIM_REG ...
15
16
write-only
TIMEOUT_DISABLE
Disables timeout in Power statemachine. By default, the statemachine continues if after 2 ms the blocks are not started up. This can be read back from ANA_STATUS_REG.
9
10
read-write
SYS_STAT_REG
System status register
0x14
16
read-write
n
0x0
0x0
DBG_IS_DOWN
Indicates that PD_DBG is in power down
4
5
read-only
DBG_IS_UP
Indicates that PD_DBG is functional
5
6
read-only
PER_IS_DOWN
Indicates that PD_PER is in power down
2
3
read-only
PER_IS_UP
Indicates that PD_PER is functional
3
4
read-only
RAD_IS_DOWN
Indicates that PD_RAD is in power down
0
1
read-only
RAD_IS_UP
Indicates that PD_RAD is functional
1
2
read-only
XTAL16_SETTLED
Indicates that XTAL16 has had > 2 ms of settle time
7
8
read-only
XTAL16_TRIM_READY
Indicates that XTAL trimming mechanism is ready, i.e. the trimming equals CLK_FREQ_TRIM_REG.
6
7
read-only
TRIM_CTRL_REG
Control trimming of the XTAL16M
0x16
16
read-write
n
0x0
0x0
SETTLE_TIME
Defines the delay between applying CLK_FREQ_TRIM_REG and XTAL16_SETTLED in steps of 250 us. 0x0: XTAL16_SETTLED is set direcly 0x1: wait between 0 and 250 us 0x2: wait between 250 us and 500 us etc.
0
4
read-write
TRIM_TIME
Defines the delay between XTAL16M enable and applying the CLK_FREQ_TRIM_REG in steps of 250 us. 0x0: apply directly 0x1: wait between 0 and 250 us 0x2: wait between 250 us and 500 us etc.
4
8
read-write
gpio580_ports_nl01
gpio580_ports_nl01 registers
Peripheral_Registers
0x0
0x0
0x100
registers
n
BIST_CTRL_REG
0xFA
16
read-write
n
0x0
0x0
RAMBIST_ENABLE
Enable the RAM bists
3
4
read-write
RAM_BIST_CONFIG
Bist configuration: 00 = Perform all 8 phases 01 = Perform only phase 1 10 = Perform only phase 3 and 4 11 = Perform only phase 6
0
2
read-write
RAM_BIST_PATTERN
Pattern to use for the BIST tests: 00 = Use 0x5555 as test data 01 = Use 0x5A5A as test data 10 = Use 0x0000 as test data 11 = Use 0x0F0F as test data
12
14
read-write
RETRAM_BIST_BUSY
Read version of bist status
8
9
read-only
RETRAM_BIST_FAIL
Read version of bist status
7
8
read-only
RETRAM_BIST_LINE_FAIL
Read version of bist status
6
7
read-only
ROMBIST_ENABLE
Enable the ROM bist
2
3
read-write
ROM_BIST_BUSY
Read version of bist status
5
6
read-only
SHOW_BIST
Map bist results on pins: P0[7] = SYSRAM_BIST_BUSY P0[6] = SYSRAM_BIST_FAIL P0[5] = SYSRAM_BIST_LINE_FAIL P0[4] = RETRAM_BIST_BUSY P0[3] = RETRAM_BIST_FAIL P0[2] = RETRAM_BIST_LINE_FAIL P0[1] = ROM_BIST_BUSY
4
5
read-write
SYSRAM_BIST_BUSY
Read version of bist status
11
12
read-only
SYSRAM_BIST_FAIL
Read version of bist status
10
11
read-only
SYSRAM_BIST_LINE_FAIL
Read version of bist status
9
10
read-only
P00_MODE_REG
P00 Mode Register
0x6
16
read-write
n
0x0
0x0
PID
Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1.
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
8
10
read-write
P01_MODE_REG
P01 Mode Register
0x8
16
read-write
n
0x0
0x0
PID
Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1.
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
8
10
read-write
P01_PADPWR_CTRL_REG
Ports 0 and 1 Output Power Control Register
0x70
16
read-write
n
0x0
0x0
P0_OUT_CTRL
1 = P0_x port output is powered by the 1 V rail 0 = P0_x port output is powered by the 3 V rail bit 0 controls the power of P0[0], bit 7 controls the power of P0[7]
0
8
read-write
P1_OUT_CTRL
1 = P1_x port output is powered by the 1 V rail 0 = P1_x port output is powered by the 3 V rail bit 8 controls the power of P1[0], bit 13 controls the power of P1[5]
8
14
read-write
P02_MODE_REG
P02 Mode Register
0xA
16
read-write
n
0x0
0x0
PID
Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1.
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
8
10
read-write
P03_MODE_REG
P03 Mode Register
0xC
16
read-write
n
0x0
0x0
PID
Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1.
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
8
10
read-write
P04_MODE_REG
P04 Mode Register
0xE
16
read-write
n
0x0
0x0
PID
Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1.
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
8
10
read-write
P05_MODE_REG
P05 Mode Register
0x10
16
read-write
n
0x0
0x0
PID
Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1.
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
8
10
read-write
P06_MODE_REG
P06 Mode Register
0x12
16
read-write
n
0x0
0x0
PID
Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1.
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
8
10
read-write
P07_MODE_REG
P07 Mode Register
0x14
16
read-write
n
0x0
0x0
PID
Function of port 0 = Port function, PUPD as set above 1 = UART1_RX 2 = UART1_TX 3 = UART2_RX 4 = UART2_TX 5 = SPI_DI 6 = SPI_DO 7 = SPI_CLK 8 = SPI_EN 9 = I2C_SCL 10 = I2C_SDA 11 = UART1_IRDA_RX 12 = UART1_IRDA_TX 13 = UART2_IRDA_RX 14 = UART2_IRDA_TX 15 = ADC (only for P0[3:0]) 16 = PWM0 17 = PWM1 18 = BLE_DIAG (only for P0[7:0]) 19 = UART1_CTSN 20 = UART1_RTSN 21 = UART2_CTSN 22 = UART2_RTSN 23 = PWM2 24 = PWM3 25 = PWM4 Note: when a certain input function (like SPI_DI) is selected on more than 1 port pin, the port with the lowest index has the highest priority and P0 has higher priority than P1.
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
8
10
read-write
P0_DATA_REG
P0 Data input / output register
0x0
16
read-write
n
0x0
0x0
P0_DATA
Set P0 output register when written Returns the value of P0 port when read
0
8
read-write
P0_RESET_DATA_REG
P0 Reset port pins register
0x4
16
read-write
n
0x0
0x0
P0_RESET
Writing a 1 to P0[y] sets P0[y] to 0. Writing 0 is discarded Reading returns 0
0
8
read-write
P0_SET_DATA_REG
P0 Set port pins register
0x2
16
read-write
n
0x0
0x0
P0_SET
Writing a 1 to P0[y] sets P0[y] to 1. Writing 0 is discarded Reading returns 0
0
8
read-write
P10_MODE_REG
P10 Mode Register
0x26
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up)
8
10
read-write
P11_MODE_REG
P11 Mode Register
0x28
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up)
8
10
read-write
P12_MODE_REG
P12 Mode Register
0x2A
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up)
8
10
read-write
P13_MODE_REG
P13 Mode Register
0x2C
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up)
8
10
read-write
P14_MODE_REG
P14 Mode Register
0x2E
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up)
8
10
read-write
P15_MODE_REG
P15 Mode Register
0x30
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care P14_MODE_REG and P15_MODE_REG reset value is 1 (i.e. pulled up)
8
10
read-write
P1_DATA_REG
P1 Data input / output register
0x20
16
read-write
n
0x0
0x0
P1_DATA
Set P1 output register when written Returns the value of P1 port when read
0
8
read-write
P1_RESET_DATA_REG
P1 Reset port pins register
0x24
16
read-write
n
0x0
0x0
P1_RESET
Writing a 1 to P1[y] sets P1[y] to 0. Writing 0 is discarded Reading returns 0
0
8
read-write
P1_SET_DATA_REG
P1 Set port pins register
0x22
16
read-write
n
0x0
0x0
P1_SET
Writing a 1 to P1[y] sets P1[y] to 1. Writing 0 is discarded Reading returns 0
0
8
read-write
P20_MODE_REG
P20 Mode Register
0x46
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
8
10
read-write
P21_MODE_REG
P21 Mode Register
0x48
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
8
10
read-write
P22_MODE_REG
P22 Mode Register
0x4A
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
8
10
read-write
P23_MODE_REG
P23 Mode Register
0x4C
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
8
10
read-write
P24_MODE_REG
P24 Mode Register
0x4E
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
8
10
read-write
P25_MODE_REG
P25 Mode Register
0x50
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
8
10
read-write
P26_MODE_REG
P26 Mode Register
0x52
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
8
10
read-write
P27_MODE_REG
P27 Mode Register
0x54
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
8
10
read-write
P28_MODE_REG
P28 Mode Register
0x56
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
8
10
read-write
P29_MODE_REG
P29 Mode Register
0x58
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In analog mode, these bits are don't care
8
10
read-write
P2_DATA_REG
P2 Data input / output register
0x40
16
read-write
n
0x0
0x0
P2_DATA
Set P2 output register when written Returns the value of P2 port when read
0
10
read-write
P2_PADPWR_CTRL_REG
Port 2 Output Power Control Register
0x72
16
read-write
n
0x0
0x0
P2_OUT_CTRL
1 = P2_x port output is powered by the 1 V rail 0 = P2_x port output is powered by the 3 V rail bit 0 controls the power of P2[0], bit 9 controls the power of P2[9],
0
10
read-write
P2_RESET_DATA_REG
P2 Reset port pins register
0x44
16
read-write
n
0x0
0x0
P2_RESET
Writing a 1 to P2[y] sets P2[y] to 0. Writing 0 is discarded Reading returns 0
0
10
read-write
P2_SET_DATA_REG
P2 Set port pins register
0x42
16
read-write
n
0x0
0x0
P2_SET
Writing a 1 to P2[y] sets P2[y] to 1. Writing 0 is discarded Reading returns 0
0
10
read-write
P30_MODE_REG
P30 Mode Register
0x86
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
8
10
read-write
P31_MODE_REG
P31 Mode Register
0x88
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
8
10
read-write
P32_MODE_REG
P32 Mode Register
0x8A
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
8
10
read-write
P33_MODE_REG
P33 Mode Register
0x8C
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
8
10
read-write
P34_MODE_REG
P34 Mode Register
0x8E
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
8
10
read-write
P35_MODE_REG
P35 Mode Register
0x90
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
8
10
read-write
P36_MODE_REG
P36 Mode Register
0x92
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
8
10
read-write
P37_MODE_REG
P37 Mode Register
0x94
16
read-write
n
0x0
0x0
PID
See P0x_MODE_REG[PID]
0
5
read-write
PUPD
00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, Pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
8
10
read-write
P3_DATA_REG
P3 Data input / output register
0x80
16
read-write
n
0x0
0x0
P3_DATA
Set P3 output register when written Returns the value of P3 port when read
0
8
read-write
P3_PADPWR_CTRL_REG
Port 3 Output Power Control Register
0x74
16
read-write
n
0x0
0x0
P3_OUT_CTRL
1 = P3_x port output is powered by the 1 V rail 0 = P3_x port output is powered by the 3 V rail bit 0 controls the power of P3[0], bit 7 controls the power of P3[7],
0
8
read-write
P3_RESET_DATA_REG
P3 Reset port pins register
0x84
16
read-write
n
0x0
0x0
P3_RESET
Writing a 1 to P0[y] sets P0[y] to 0. Writing 0 is discarded Reading returns 0
0
8
write-only
P3_SET_DATA_REG
P3 Set port pins register
0x82
16
read-write
n
0x0
0x0
P3_SET
Writing a 1 to P3[y] sets P3[y] to 1. Writing 0 is discarded Reading returns 0
0
8
write-only
ROMBIST_RESULTH_REG
0xFE
16
read-write
n
0x0
0x0
ROMBIST_RESULTH
Read version of bist status, result[31:16]
0
16
read-only
ROMBIST_RESULTL_REG
0xFC
16
read-write
n
0x0
0x0
ROMBIST_RESULTL
Read version of bist status, result[15:0]
0
16
read-only
TEST_CTRL2_REG
0xF2
16
read-write
n
0x0
0x0
ANA_TESTMUX_CTRL
Control of analog test bus switches: 0: all switches open 1: only switch 1 closed 2: only switch 2 closed 3: only switch 3 closed 4: only switch 4 closed 5: switches 1 and 2 closed 6: switches 1 and 4 closed 7: switches 2 and 3 closed 8: switches 3 and 4 closed
0
4
read-write
RF_IN_TESTMUX_CTRL
CConnect the RF input testbus to pins
8
10
read-write
TEST_CTRL3_REG
0xF4
16
read-write
n
0x0
0x0
RF_TEST_OUT_PARAM
Select which test will be enabled on the block selected by the RF output testbus (see
8
16
read-write
RF_TEST_OUT_SEL
Select a radio block to have its testbus connected to P1[1] and P1[2]. See Table 7 for more information. NOTE: all 0 represent no testmode and the testbusses are shorted to ground to prevent floating busses.
0
6
read-write
TEST_CTRL4_REG
0xF6
16
read-write
n
0x0
0x0
RF_TEST_IN_PARAM
Select which test will be enabled on the block selected by the RF output testbus (see
8
16
read-write
RF_TEST_IN_SEL
Select an RF block to have its test input connected to the input testbus at pins P0[0] and P0[3]. NOTE: all 0 represent no testmode and the testbusses are shorted to ground to prevent floating busses.
0
3
read-write
TEST_CTRL5_REG
0xF8
16
read-write
n
0x0
0x0
DCDC_FORCE_IDLE
Keep the DCDC-converter in the idle state.
15
16
read-write
DCDC_NSW
Close nMOS switch between 'switch' and 'gnd'
12
13
read-write
DCDC_OUTSW
Close pMOS switch between 'switch' and 'vdcdc'
14
15
read-write
DCDC_PSW
Close pMOS switch between 'switch' and 'vbat3v'
13
14
read-write
TEST_OTP_OTA
Output of OTA inside LDO-OTP is mapped on P1[2]. This voltage will slowely rise due to capacitor leakage.
2
3
read-write
TEST_OTP_VDD
VDD_OTP on P1[2], 1uA bias sink on P1[1]
1
2
read-write
TEST_OTP_VSS
VSS_OTP (0V) mapped on P1[2]
3
4
read-write
TEST_STRUCT
4 bits to select which test-structure is mapped on P1[1] 0 : open 1 : VDD (1.2V) 2 : 10uA into 66k = 5/3 x 40k (W/L=0.45/22.33) 3 : 1uA into 700k = 18.5 x 40k (W/L=0.45/22.33) 4 : 1uA(same as going into 700k) 5 : AVS (0V) 6 : 5uA into nMOST (svt) 2x1u/110n 7 : 5uA into nMOST (hvt) 2x1u/110n 8 : 5uA into nMOST (UD18) 2x1u/260n 9 : 5uA into nMOST (OD33) 2x1u/500n a : 7.5uA into nMOST (na25) 4x1u/1.2u b : 5uA into nMOST (0vt) 4x1u/300n c : VDD - 5uA from pMOST (svt) 2x1u/110n d : VDD - 5uA from pMOST (hvt) 2x1u/110n e : VDD - 5uA from pMOST (OD33) 2x1u/400n f : VDD - 5uA from pMOST (UD18) 2x1u/260n
8
12
read-write
TEST_VDD
VDD on P1[1], VDD_REF (=ADC) on P1[2]
0
1
read-write
TEST_CTRL_REG
0xF0
16
read-write
n
0x0
0x0
ENABLE_RFPT
0: normal port function 1: enable the RF Production Test Unit. Used to store RX ADC samples or PLL TDC samples in SRAM. See RFPT_CTRL_REG, RFPT_ADDR_REG and RFPT_LEN_REG for details.
1
2
read-write
PLL_TST_MODE
0: Normal operation 1: Show the PLL test mode signals: P0[0] = RCLK P0[1] = NCLK P0[2] = CP_UP P0[3] = CP_DOWN Notes: - The control signal should go to the radio to enable this test mode.
6
7
read-write
SHOW_CLOCKS
0: normal port function 1: P0[5] = XTAL16M_clk P0[6] = XTAL32K_clk P0[7] = RC16M_clk P1[0] = RC32K_clk P1[1] = RC32K_Low_Jitter_clk
0
1
read-write
SHOW_DC_COMP
0: normal port function 1: show signals to evaluate comparators in DCDC converter: P1[3:1] = dyn_sw_n[2:0]P1[0],P0[7:6] = dyn_sw[2:0]P0[5:3] = cont_sw[2:0] P0[2:0] = dcdc_test_out[2:0] (2=swout, 1=swp, 0=swn)
3
4
read-write
SHOW_DC_STATE
0: normal port function 1: show signals to debug/evaluate the DCDC converter: P1[3] = ldo_dig_okP1[2] = ldo_otp_ok P1[1] = dcdc_idleP1[0] = dcdc_clk P0[7] = boost_vbat_ok P0[6] = vdcdc_okP0[5:0] = dcdc_test_out[5:0] (5=short, 4=bypass, 3=sw1v, 2=swout, 1=swp, 0=swn)
2
3
read-write
SHOW_IF_RO
0: Normal Port function. 1: Show IF filter Reference Oscillator I and Q signals. P0[0] = iff_ro_out_i P0[1] = iff_ro_out_q
5
6
read-write
XTAL16M_CAP_TEST_EN
0: Normal Port function. 1: Show xtal16m_cap_test_outoutput P1[2:1] Notes: - The control signal should go to the radio to enable this test mode. - This register should be zero during scan test!
4
5
read-write
i2c580_nl00
i2c580_nl00 registers
Peripheral_Registers
0x0
0x0
0xA2
registers
n
I2C_ACK_GENERAL_CALL_REG
I2C ACK General Call Register
0x98
16
read-write
n
0x0
0x0
ACK_GEN_CALL
ACK General Call. When set to 1, I2C Ctrl responds with a ACK (by asserting ic_data_oe) when it receives a General Call. When set to 0, the controller does not generate General Call interrupts.
0
1
read-write
I2C_CLR_ACTIVITY_REG
Clear ACTIVITY Interrupt Register
0x5C
16
read-write
n
0x0
0x0
CLR_ACTIVITY
Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register
0
1
read-only
I2C_CLR_GEN_CALL_REG
Clear GEN_CALL Interrupt Register
0x68
16
read-write
n
0x0
0x0
CLR_GEN_CALL
Read this register to clear the GEN_CALL interrupt (bit 11) of I2C_RAW_INTR_STAT register.
0
1
read-only
I2C_CLR_INTR_REG
Clear Combined and Individual Interrupt Register
0x40
16
read-write
n
0x0
0x0
CLR_INTR
Read this register to clear the combined interrupt, all individual interrupts, and the I2C_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing I2C_TX_ABRT_SOURCE
0
1
read-only
I2C_CLR_RD_REQ_REG
Clear RD_REQ Interrupt Register
0x50
16
read-write
n
0x0
0x0
CLR_RD_REQ
Read this register to clear the RD_REQ interrupt (bit 5) of the I2C_RAW_INTR_STAT register.
0
1
read-only
I2C_CLR_RX_DONE_REG
Clear RX_DONE Interrupt Register
0x58
16
read-write
n
0x0
0x0
CLR_RX_DONE
Read this register to clear the RX_DONE interrupt (bit 7) of the I2C_RAW_INTR_STAT register.
0
1
read-only
I2C_CLR_RX_OVER_REG
Clear RX_OVER Interrupt Register
0x48
16
read-write
n
0x0
0x0
CLR_RX_OVER
Read this register to clear the RX_OVER interrupt (bit 1) of the I2C_RAW_INTR_STAT register.
0
1
read-only
I2C_CLR_RX_UNDER_REG
Clear RX_UNDER Interrupt Register
0x44
16
read-write
n
0x0
0x0
CLR_RX_UNDER
Read this register to clear the RX_UNDER interrupt (bit 0) of the I2C_RAW_INTR_STAT register.
0
1
read-only
I2C_CLR_START_DET_REG
Clear START_DET Interrupt Register
0x64
16
read-write
n
0x0
0x0
CLR_START_DET
Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.
0
1
read-only
I2C_CLR_STOP_DET_REG
Clear STOP_DET Interrupt Register
0x60
16
read-write
n
0x0
0x0
CLR_ACTIVITY
Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.
0
1
read-only
I2C_CLR_TX_ABRT_REG
Clear TX_ABRT Interrupt Register
0x54
16
read-write
n
0x0
0x0
CLR_TX_ABRT
Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the I2C_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.
0
1
read-only
I2C_CLR_TX_OVER_REG
Clear TX_OVER Interrupt Register
0x4C
16
read-write
n
0x0
0x0
CLR_TX_OVER
Read this register to clear the TX_OVER interrupt (bit 3) of the I2C_RAW_INTR_STAT register.
0
1
read-only
I2C_CON_REG
I2C Control Register
0x0
16
read-write
n
0x0
0x0
I2C_10BITADDR_MASTER
Controls whether the controller starts its transfers in 7- or 10-bit addressing mode when acting as a master. 0= 7-bit addressing 1= 10-bit addressing
4
5
read-write
I2C_10BITADDR_SLAVE
When acting as a slave, this bit controls whether the controller responds to 7- or 10-bit addresses. 0= 7-bit addressing 1= 10-bit addressing
3
4
read-write
I2C_MASTER_MODE
This bit controls whether the controller master is enabled. 0= master disabled 1= master enabled Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'.
0
1
read-write
I2C_RESTART_EN
Determines whether RESTART conditions may be sent when acting as a master 0= disable 1=enable
5
6
read-write
I2C_SLAVE_DISABLE
Slave enabled or disabled after reset is applied, which means software does not have to configure the slave. 0=slave is enabled 1=slave is disabled Software should ensure that if this bit is written with '0', then bit 0 should also be written with a '0'.
6
7
read-write
I2C_SPEED
These bits control at which speed the controller operates. 1= standard mode (100 kbit/s) 2= fast mode (400 kbit/s)
1
3
read-write
I2C_DATA_CMD_REG
I2C Rx/Tx Data Buffer and Command Register
0x10
16
read-write
n
0x0
0x0
CMD
This bit controls whether a read or a write is performed. This bit does not control the direction when the I2C Ctrl acts as a slave. It controls only the direction when it acts as a master. 1 = Read 0 = Write When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that CPU data is to be transmitted and as DAT or IC_DATA_CMD[7:0]. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the I2C_RAW_INTR_STAT_REG), unless bit 11 (SPECIAL) in the I2C_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. NOTE: It is possible that while attempting a master I2C read transfer on the controller, a RD_REQ interrupt may have occurred simultaneously due to a remote I2C master addressing the controller. In this type of scenario, it ignores the I2C_DATA_CMD write, generates a TX_ABRT interrupt, and waits to service the RD_REQ interrupt
8
9
read-write
DAT
This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the controller. However, when you read this register, these bits return the value of data received on the controller's interface.
0
8
read-write
I2C_ENABLE_REG
I2C Enable Register
0x6C
16
read-write
n
0x0
0x0
CTRL_ENABLE
Controls whether the controller is enabled. 0: Disables the controller (TX and RX FIFOs are held in an erased state) 1: Enables the controller Software can disable the controller while it is active. However, it is important that care be taken to ensure that the controller is disabled properly. When the controller is disabled, the following occurs: * The TX FIFO and RX FIFO get flushed. * Status bits in the IC_INTR_STAT register are still active until the controller goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the controller stops the current transfer at the end of the current byte and does not acknowledge the transfer. There is a two ic_clk delay when enabling or disabling the controller
0
1
read-write
I2C_ENABLE_STATUS_REG
I2C Enable Status Register
0x9C
16
read-write
n
0x0
0x0
IC_EN
ic_en Status. This bit always reflects the value driven on the output port ic_en. When read as 1, the controller is deemed to be in an enabled state. When read as 0, the controller is deemed completely inactive. NOTE: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).
0
1
read-only
SLV_DISABLED_WHILE_BUSY
Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) I2C Ctrl is receiving the address byte of the Slave-Transmitter operation from a remote master OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, the controller is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in I2C Ctrl (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit will also be set to 1. When read as 0, the controller is deemed to have been disabled when there is master activity, or when the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.
1
2
read-only
SLV_RX_DATA_LOST
Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting of IC_ENABLE from 1 to 0. When read as 1, the controller is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit is also set to 1. When read as 0, the controller is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.
2
3
read-only
I2C_FS_SCL_HCNT_REG
Fast Speed I2C Clock SCL High Count Register
0x1C
16
read-write
n
0x0
0x0
IC_FS_SCL_HCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set.
0
16
read-write
I2C_FS_SCL_LCNT_REG
Fast Speed I2C Clock SCL Low Count Register
0x20
16
read-write
n
0x0
0x0
IC_FS_SCL_LCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low-period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the controller. The lower byte must be programmed first. Then the upper byte is programmed.
0
16
read-write
I2C_IC_FS_SPKLEN_REG
I2C SS and FS spike suppression limit Size
0xA0
16
read-write
n
0x0
0x0
IC_FS_SPKLEN
This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 1 hardware prevents values less than this being written, and if attempted results in 1 being set.
0
8
read-write
I2C_INTR_MASK_REG
I2C Interrupt Mask Register
0x30
16
read-write
n
0x0
0x0
M_ACTIVITY
These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
8
9
read-write
M_GEN_CALL
These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
11
12
read-write
M_RD_REQ
These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
5
6
read-write
M_RX_DONE
These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
7
8
read-write
M_RX_FULL
These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
2
3
read-write
M_RX_OVER
These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
1
2
read-write
M_RX_UNDER
These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
0
1
read-write
M_START_DET
These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
10
11
read-write
M_STOP_DET
These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
9
10
read-write
M_TX_ABRT
These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
6
7
read-write
M_TX_EMPTY
These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
4
5
read-write
M_TX_OVER
These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
3
4
read-write
I2C_INTR_STAT_REG
I2C Interrupt Status Register
0x2C
16
read-write
n
0x0
0x0
R_ACTIVITY
This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it: => Disabling the I2C Ctrl => Reading the IC_CLR_ACTIVITY register => Reading the IC_CLR_INTR register => System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus.
8
9
read-only
R_GEN_CALL
Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. The controller stores the received data in the Rx buffer.
11
12
read-only
R_RD_REQ
This bit is set to 1 when the controller is acting as a slave and another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register
5
6
read-only
R_RX_DONE
When the controller is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.
7
8
read-only
R_RX_FULL
Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.
2
3
read-only
R_RX_OVER
Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
1
2
read-only
R_RX_UNDER
Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
0
1
read-only
R_START_DET
Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode.
10
11
read-only
R_STOP_DET
Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode.
9
10
read-only
R_TX_ABRT
This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface.
6
7
read-only
R_TX_EMPTY
This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0.
4
5
read-only
R_TX_OVER
Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared
3
4
read-only
I2C_RAW_INTR_STAT_REG
I2C Raw Interrupt Status Register
0x34
16
read-write
n
0x0
0x0
ACTIVITY
This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it: => Disabling the I2C Ctrl => Reading the IC_CLR_ACTIVITY register => Reading the IC_CLR_INTR register => System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus.
8
9
read-only
GEN_CALL
Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. I2C Ctrl stores the received data in the Rx buffer.
11
12
read-only
RD_REQ
This bit is set to 1 when I2C Ctrl is acting as a slave and another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register
5
6
read-only
RX_DONE
When the controller is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.
7
8
read-only
RX_FULL
Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.
2
3
read-only
RX_OVER
Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
1
2
read-only
RX_UNDER
Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
0
1
read-only
START_DET
Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode.
10
11
read-only
STOP_DET
Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode.
9
10
read-only
TX_ABRT
This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface.
6
7
read-only
TX_EMPTY
This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0.
4
5
read-only
TX_OVER
Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared
3
4
read-only
I2C_RXFLR_REG
I2C Receive FIFO Level Register
0x78
16
read-write
n
0x0
0x0
RXFLR
Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Size is constrained by the RXFLR value
0
6
read-only
I2C_RX_TL_REG
I2C Receive FIFO Threshold Register
0x38
16
read-write
n
0x0
0x0
RX_TL
Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in I2C_RAW_INTR_STAT register). The valid range is 0-31, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 31 sets the threshold for 32 entries.
0
5
read-write
I2C_SAR_REG
I2C Slave Address Register
0x8
16
read-write
n
0x0
0x0
IC_SAR
The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect.
0
10
read-write
I2C_SDA_HOLD_REG
I2C SDA Hold Time Length Register
0x7C
16
read-write
n
0x0
0x0
IC_SDA_HOLD
SDA Hold time
0
16
read-write
I2C_SDA_SETUP_REG
I2C SDA Setup Register
0x94
16
read-write
n
0x0
0x0
SDA_SETUP
SDA Setup. This register controls the amount of time delay (number of I2C clock periods) between the rising edge of SCL and SDA changing by holding SCL low when I2C block services a read request while operating as a slave-transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. It is recommended that if the required delay is 1000ns, then for an I2C frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11.Writes to this register succeed only when IC_ENABLE[0] = 0.
0
8
read-write
I2C_SS_SCL_HCNT_REG
Standard Speed I2C Clock SCL High Count Register
0x14
16
read-write
n
0x0
0x0
IC_SS_SCL_HCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set. NOTE: This register must not be programmed to a value higher than 65525, because the controller uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.
0
16
read-write
I2C_SS_SCL_LCNT_REG
Standard Speed I2C Clock SCL Low Count Register
0x18
16
read-write
n
0x0
0x0
IC_SS_SCL_LCNT
This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted, results in 8 being set.
0
16
read-write
I2C_STATUS_REG
I2C Status Register
0x70
16
read-write
n
0x0
0x0
I2C_ACTIVITY
I2C Activity Status.
0
1
read-only
MST_ACTIVITY
Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. 0: Master FSM is in IDLE state so the Master part of the controller is not Active 1: Master FSM is not in IDLE state so the Master part of the controller is Active
5
6
read-only
RFF
Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0: Receive FIFO is not full 1: Receive FIFO is full
4
5
read-only
RFNE
Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries it is cleared when the receive FIFO is empty. 0: Receive FIFO is empty 1: Receive FIFO is not empty
3
4
read-only
SLV_ACTIVITY
Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. 0: Slave FSM is in IDLE state so the Slave part of the controller is not Active 1: Slave FSM is not in IDLE state so the Slave part of the controller is Active
6
7
read-only
TFE
Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0: Transmit FIFO is not empty 1: Transmit FIFO is empty
2
3
read-only
TFNF
Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0: Transmit FIFO is full 1: Transmit FIFO is not full
1
2
read-only
I2C_TAR_REG
I2C Target Address Register
0x4
16
read-write
n
0x0
0x0
GC_OR_START
If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the controller. 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The controller remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. 1: START BYTE
10
11
read-write
IC_TAR
This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. Note: If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself it can transmit to only a slave
0
10
read-write
SPECIAL
This bit indicates whether software performs a General Call or START BYTE command. 0: ignore bit 10 GC_OR_START and use IC_TAR normally 1: perform special I2C command as specified in GC_OR_START bit
11
12
read-write
I2C_TXFLR_REG
I2C Transmit FIFO Level Register
0x74
16
read-write
n
0x0
0x0
TXFLR
Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Size is constrained by the TXFLR value
0
6
read-only
I2C_TX_ABRT_SOURCE_REG
I2C Transmit Abort Source Register
0x80
16
read-write
n
0x0
0x0
ABRT_10ADDR1_NOACK
1: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.
1
2
read-only
ABRT_10ADDR2_NOACK
1: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave.
2
3
read-only
ABRT_10B_RD_NORSTRT
1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode.
10
11
read-only
ABRT_7B_ADDR_NOACK
1: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.
0
1
read-only
ABRT_GCALL_NOACK
1: the controller in master mode sent a General Call and no slave on the bus acknowledged the General Call.
4
5
read-only
ABRT_GCALL_READ
1: the controller in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).
5
6
read-only
ABRT_HS_ACKDET
1: Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).
6
7
read-only
ABRT_HS_NORSTRT
1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode
8
9
read-only
ABRT_MASTER_DIS
1: User tries to initiate a Master operation with the Master mode disabled.
11
12
read-only
ABRT_SBYTE_ACKDET
1: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).
7
8
read-only
ABRT_SBYTE_NORSTRT
To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first restart must be enabled (I2C_CON[5]=1), the SPECIAL bit must be cleared (I2C_TAR[11]), or the GC_OR_START bit must be cleared (I2C_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets re-asserted. 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to send a START Byte.
9
10
read-only
ABRT_SLVFLUSH_TXFIFO
1: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.
13
14
read-only
ABRT_SLVRD_INTX
1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of 2IC_DATA_CMD register
15
16
read-only
ABRT_SLV_ARBLOST
1: Slave lost the bus while transmitting data to a remote master. I2C_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then the controller no longer own the bus.
14
15
read-only
ABRT_TXDATA_NOACK
1: This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).
3
4
read-only
ARB_LOST
1: Master has lost arbitration, or if I2C_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. Note: I2C can be both master and slave at the same time.
12
13
read-only
I2C_TX_TL_REG
I2C Transmit FIFO Threshold Register
0x3C
16
read-write
n
0x0
0x0
RX_TL
Transmit FIFO Threshold Level Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in I2C_RAW_INTR_STAT register). The valid range is 0-31, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 31 sets the threshold for 32 entries..
0
5
read-write
kbrd580_nl01
kbrd580_nl01 registers
Peripheral_Registers
0x0
0x0
0x18
registers
n
GPIO_DEBOUNCE_REG
debounce counter value for GPIO inputs
0xC
16
read-write
n
0x0
0x0
DEB_ENABLE0
enables the debounce counter for GPIO IRQ0
8
9
read-write
DEB_ENABLE1
enables the debounce counter for GPIO IRQ1
9
10
read-write
DEB_ENABLE2
enables the debounce counter for GPIO IRQ2
10
11
read-write
DEB_ENABLE3
enables the debounce counter for GPIO IRQ3
11
12
read-write
DEB_ENABLE4
enables the debounce counter for GPIO IRQ4
12
13
read-write
DEB_ENABLE_KBRD
enables the debounce counter for the KBRD interface
13
14
read-write
DEB_VALUE
Keyboard debounce time if enabled. Generate KEYB_INT after specified time. Debounce time: N*1 ms. N =0..63
0
6
read-write
GPIO_INT_LEVEL_CTRL_REG
high or low level select for GPIO interrupts
0x10
16
read-write
n
0x0
0x0
EDGE_LEVELn0
0: do not wait for key release after interrupt was reset for GPIO IRQ0, so a new interrupt can be initiated immediately 1: wait for key release after interrupt was reset for IRQ0
8
9
read-write
EDGE_LEVELn1
see EDGE_LEVELn0, but for GPIO IRQ1
9
10
read-write
EDGE_LEVELn2
see EDGE_LEVELn0, but for GPIO IRQ2
10
11
read-write
EDGE_LEVELn3
see EDGE_LEVELn0, but for GPIO IRQ3
11
12
read-write
EDGE_LEVELn4
see EDGE_LEVELn0, but for GPIO IRQ4
12
13
read-write
INPUT_LEVEL0
0 = selected input will generate GPIO IRQ0 if that input is high. 1 = selected input will generate GPIO IRQ0 if that input is low.
0
1
read-write
INPUT_LEVEL1
see INPUT_LEVEL0, but for GPIO IRQ1
1
2
read-write
INPUT_LEVEL2
see INPUT_LEVEL0, but for GPIO IRQ2
2
3
read-write
INPUT_LEVEL3
see INPUT_LEVEL0, but for GPIO IRQ3
3
4
read-write
INPUT_LEVEL4
see INPUT_LEVEL0, but for GPIO IRQ4
4
5
read-write
GPIO_IRQ0_IN_SEL_REG
GPIO interrupt selection for GPIO_IRQ0
0x0
16
read-write
n
0x0
0x0
KBRD_IRQ0_SEL
input selection that can generate a GPIO interrupt 0: no input selected 1: P0[0] is selected 2: P0[1] is selected 3: P0[2] is selected 4: P0[3] is selected 5: P0[4] is selected 6: P0[5] is selected 7: P0[6] is selected 8: P0[7] is selected 9: P1[0] is selected 10: P1[1] is selected 11: P1[2] is selected 12: P1[3] is selected 13: P1[4] is selected 14: P1[5] is selected 15: P2[0] is selected 16: P2[1] is selected 17: P2[2] is selected 18: P2[3] is selected 19: P2[4] is selected 20: P2[5] is selected 21: P2[6] is selected 22: P2[7] is selected 23: P2[8] is selected 24: P2[9] is selected 25: P3[0] is selected 26: P3[1] is selected 27: P3[2] is selected 28: P3[3] is selected 29: P3[4] is selected 30: P3[5] is selected 31: P3[6] is selected 32: P3[7] is selected all others: no input selected
0
6
read-write
GPIO_IRQ1_IN_SEL_REG
GPIO interrupt selection for GPIO_IRQ1
0x2
16
read-write
n
0x0
0x0
KBRD_IRQ1_SEL
see KBRD_IRQ0_SEL
0
6
read-write
GPIO_IRQ2_IN_SEL_REG
GPIO interrupt selection for GPIO_IRQ2
0x4
16
read-write
n
0x0
0x0
KBRD_IRQ2_SEL
see KBRD_IRQ0_SEL
0
6
read-write
GPIO_IRQ3_IN_SEL_REG
GPIO interrupt selection for GPIO_IRQ3
0x6
16
read-write
n
0x0
0x0
KBRD_IRQ3_SEL
see KBRD_IRQ0_SEL
0
6
read-write
GPIO_IRQ4_IN_SEL_REG
GPIO interrupt selection for GPIO_IRQ4
0x8
16
read-write
n
0x0
0x0
KBRD_IRQ4_SEL
see KBRD_IRQ0_SEL
0
6
read-write
GPIO_RESET_IRQ_REG
GPIO interrupt reset register
0xE
16
read-write
n
0x0
0x0
RESET_GPIO0_IRQ
writing a 1 to this bit will reset the GPIO0 IRQ. Reading returns 0.
0
1
write-only
RESET_GPIO1_IRQ
writing a 1 to this bit will reset the GPIO1 IRQ. Reading returns 0.
1
2
write-only
RESET_GPIO2_IRQ
writing a 1 to this bit will reset the GPIO2 IRQ. Reading returns 0.
2
3
write-only
RESET_GPIO3_IRQ
writing a 1 to this bit will reset the GPIO3 IRQ. Reading returns 0.
3
4
write-only
RESET_GPIO4_IRQ
writing a 1 to this bit will reset the GPIO4 IRQ. Reading returns 0.
4
5
write-only
RESET_KBRD_IRQ
writing a 1 to this bit will reset the KBRD IRQ. Reading returns 0.
5
6
write-only
KBRD_IRQ_IN_SEL0_REG
GPIO interrupt selection for KBRD_IRQ for P0
0x12
16
read-write
n
0x0
0x0
KBRD_LEVEL
0 = enabled input will generate KBRD IRQ if that input is high. 1 = enabled input will generate KBRD IRQ if that input is low.
14
15
read-write
KBRD_P00_EN
enable P0[0] for the keyboard interrupt
0
1
read-write
KBRD_P01_EN
enable P0[1] for the keyboard interrupt
1
2
read-write
KBRD_P02_EN
enable P0[2] for the keyboard interrupt
2
3
read-write
KBRD_P03_EN
enable P0[3] for the keyboard interrupt
3
4
read-write
KBRD_P04_EN
enable P0[4] for the keyboard interrupt
4
5
read-write
KBRD_P05_EN
enable P0[5] for the keyboard interrupt
5
6
read-write
KBRD_P06_EN
enable P0[6] for the keyboard interrupt
6
7
read-write
KBRD_P07_EN
enable P0[7] for the keyboard interrupt
7
8
read-write
KBRD_REL
0 = No interrupt on key release 1 = Interrupt also on key release (also debouncing if enabled)
15
16
read-write
KEY_REPEAT
While key is pressed, automatically generate repeating KEYB_INT after specified time unequal to 0. Repeat time: N*1 ms. N =1..63, N=0 disables the timer.
8
14
read-write
KBRD_IRQ_IN_SEL1_REG
GPIO interrupt selection for KBRD_IRQ for P1 and P2
0x14
16
read-write
n
0x0
0x0
KBRD_P10_EN
enable P1[0] for the keyboard interrupt
10
11
read-write
KBRD_P11_EN
enable P1[1] for the keyboard interrupt
11
12
read-write
KBRD_P12_EN
enable P1[2] for the keyboard interrupt
12
13
read-write
KBRD_P13_EN
enable P1[3] for the keyboard interrupt
13
14
read-write
KBRD_P14_EN
enable P1[4] for the keyboard interrupt
14
15
read-write
KBRD_P15_EN
enable P1[5] for the keyboard interrupt
15
16
read-write
KBRD_P20_EN
enable P2[0] for the keyboard interrupt
0
1
read-write
KBRD_P21_EN
enable P2[1] for the keyboard interrupt
1
2
read-write
KBRD_P22_EN
enable P2[2] for the keyboard interrupt
2
3
read-write
KBRD_P23_EN
enable P2[3] for the keyboard interrupt
3
4
read-write
KBRD_P24_EN
enable P2[4] for the keyboard interrupt
4
5
read-write
KBRD_P25_EN
enable P2[5] for the keyboard interrupt
5
6
read-write
KBRD_P26_EN
enable P2[6] for the keyboard interrupt
6
7
read-write
KBRD_P27_EN
enable P2[7] for the keyboard interrupt
7
8
read-write
KBRD_P28_EN
enable P2[8] for the keyboard interrupt
8
9
read-write
KBRD_P29_EN
enable P2[9] for the keyboard interrupt
9
10
read-write
KBRD_IRQ_IN_SEL2_REG
GPIO interrupt selection for KBRD_IRQ for P3
0x16
16
read-write
n
0x0
0x0
KBRD_P30_EN
enable P3[0] for the keyboard interrupt
0
1
read-write
KBRD_P31_EN
enable P3[1] for the keyboard interrupt
1
2
read-write
KBRD_P32_EN
enable P3[2] for the keyboard interrupt
2
3
read-write
KBRD_P33_EN
enable P3[3] for the keyboard interrupt
3
4
read-write
KBRD_P34_EN
enable P3[4] for the keyboard interrupt
4
5
read-write
KBRD_P35_EN
enable P3[5] for the keyboard interrupt
5
6
read-write
KBRD_P36_EN
enable P3[6] for the keyboard interrupt
6
7
read-write
KBRD_P37_EN
enable P3[7] for the keyboard interrupt
7
8
read-write
NVIC
Cortex M0 NVIC registers
NVIC_GROUP
0x0
0x0
0x321
registers
n
ICER
Interrupt clear-enable register
0x80
32
read-write
n
0x0
0x0
ADC_IRQn
ADC_IRQn (Interrupt clear-enable bit)
6
7
read-write
BLE_GEN_IRQn
BLE_GEN_IRQn (Interrupt clear-enable bit)
1
2
read-write
BLE_RF_DIAG_IRQn
BLE baseband or Radio diagnostic (Interrupt clear-enable bit))
8
9
read-write
BLE_WAKEUP_LP_IRQn
BLE_WAKEUP_LP_IRQn (Interrupt clear-enable bit)
0
1
read-write
DMA_IRQn
DMA Interrupt (clear-enable bit)
20
21
read-write
GPIO0_IRQn
GPIO0 interrupt through debounce (Interrupt clear-enable bit)
10
11
read-write
GPIO1_IRQn
GPIO1 interrupt through debounce (Interrupt clear-enable bit)
11
12
read-write
GPIO2_IRQn
GPIO2 interrupt through debounce (Interrupt clear-enable bit)
12
13
read-write
GPIO3_IRQn
IGPIO3 interrupt through debounce (Interrupt clear-enable bit)
13
14
read-write
GPIO4_IRQn
GPIO4 interrupt through debounce (Interrupt clear-enable bit)
14
15
read-write
I2C_IRQn
I2C_IRQn (Interrupt clear-enable bit)
4
5
read-write
KEYBRD_IRQn
KEYBRD_IRQn (Interrupt clear-enable bit)
7
8
read-write
PCM_IRQn
PCM Interrupt (clear-enable bit)
17
18
read-write
RFCAL_IRQn
RFCAL_IRQn (Interrupt clear-enable bit)
9
10
read-write
SPI_IRQn
SPI_IRQn (Interrupt clear-enable bit)
5
6
read-write
SRC_IN_IRQn
Sample rate converter input Interrupt (clear-enable bit)
18
19
read-write
SRC_OUT_IRQn
Sample rate converter output Interrupt (clear-enable bit)
19
20
read-write
SWTIM_IRQn
Software timer Interrupt (clear-enable bit)
15
16
read-write
UART2_IRQn
UART2_IRQn (Interrupt clear-enable bit)
3
4
read-write
UART_IRQn
UART_IRQn (Interrupt clear-enable bit)
2
3
read-write
WKUP_QUADEC_IRQn
Combined Wake up Capture Timer, GPIO and QuadDecoder interrupt (clear-enable bit)
16
17
read-write
ICPR
Interrupt clear-pending register
0x180
32
read-write
n
0x0
0x0
ADC_IRQn
ADC_IRQn (Interrupt clear-pending bit)
6
7
read-write
BLE_GEN_IRQn
BLE_GEN_IRQn (Interrupt clear-pending bit)
1
2
read-write
BLE_RF_DIAG_IRQn
BLE baseband or Radio diagnostic (Interrupt clear-pending bit))
8
9
read-write
BLE_WAKEUP_LP_IRQn
BLE_WAKEUP_LP_IRQn (Interrupt clear-pending bit)
0
1
read-write
DMA_IRQn
DMA Interrupt (clear-pending bit)
20
21
read-write
GPIO0_IRQn
GPIO0 interrupt through debounce (Interrupt clear-pending bit)
10
11
read-write
GPIO1_IRQn
GPIO1 interrupt through debounce (Interrupt clear-pending bit)
11
12
read-write
GPIO2_IRQn
GPIO2 interrupt through debounce (Interrupt clear-pending bit)
12
13
read-write
GPIO3_IRQn
IGPIO3 interrupt through debounce (Interrupt clear-pending bit)
13
14
read-write
GPIO4_IRQn
GPIO4 interrupt through debounce (Interrupt clear-pending bit)
14
15
read-write
I2C_IRQn
I2C_IRQn (Interrupt clear-pending bit)
4
5
read-write
KEYBRD_IRQn
KEYBRD_IRQn (Interrupt clear-pending bit)
7
8
read-write
PCM_IRQn
PCM Interrupt (clear-pending bit)
17
18
read-write
RFCAL_IRQn
RFCAL_IRQn (Interrupt clear-pending bit)
9
10
read-write
SPI_IRQn
SPI_IRQn (Interrupt clear-pending bit)
5
6
read-write
SRC_IN_IRQn
Sample rate converter input Interrupt (clear-pending bit)
18
19
read-write
SRC_OUT_IRQn
Sample rate converter output Interrupt (clear-pending bit)
19
20
read-write
SWTIM_IRQn
Software timer Interrupt (clear-pending bit)
15
16
read-write
UART2_IRQn
UART2_IRQn (Interrupt clear-pending bit)
3
4
read-write
UART_IRQn
UART_IRQn (Interrupt clear-pending bit)
2
3
read-write
WKUP_QUADEC_IRQn
Combined Wake up Capture Timer, GPIO and QuadDecoder interrupt (clear-pending bit)
16
17
read-write
IPR0
Interrupt priority register 0
0x300
32
read-write
n
0x0
0x0
BLE_GEN_IRQn_prio
BLE_GEN_IRQn[7:0] bits (Interrupt priority)
8
16
read-write
BLE_WAKEUP_LP_IRQn_prio
BLE_WAKEUP_LP_IRQn[7:0] bits (Interrupt priority)
0
8
read-write
UART2_IRQn_prio
UART2_IRQn[7:0] bits (Interrupt priority)
24
32
read-write
UART_IRQn_prio
UART_IRQn[7:0] bits (Interrupt priority)
16
24
read-write
IPR1
Interrupt priority register 1
0x304
32
read-write
n
0x0
0x0
ADC_IRQn_prio
ADC_IRQn[7:0] bits (Interrupt priority)
16
24
read-write
I2C_IRQn_prio
I2C_IRQn[7:0] bits (Interrupt priority)
0
8
read-write
KEYBRD_IRQn_prio
KEYBRD_IRQn[7:0] bits (Interrupt priority)
24
32
read-write
SPI_IRQn_prio
SPI_IRQn[7:0] bits (Interrupt priority)
8
16
read-write
IPR2
Interrupt priority register 2
0x308
32
read-write
n
0x0
0x0
BLE_RF_DIAG_IRQn_prio
BLE_RF_DIAG_IRQn[7:0] bits (Interrupt priority)
0
8
read-write
GPIO0_IRQn_prio
GPIO0_IRQn[7:0] bits (Interrupt priority)
16
24
read-write
GPIO1_IRQn_prio
GPIO1_IRQn[7:0] bits (Interrupt priority)
24
32
read-write
RF_CAL_IRQn_prio
RF_CAL_IRQn[7:0] bits (Interrupt priority)
8
16
read-write
IPR3
Interrupt priority register 3
0x30C
32
read-write
n
0x0
0x0
ADC_IRQn_prio
ADC_IRQn[7:0] bits (Interrupt priority)
16
24
read-write
KEYBRD_IRQn_prio
KEYBRD_IRQn[7:0] bits (Interrupt priority)
24
32
read-write
SPI2_IRQn_prio
SPI2_IRQn[7:0] bits (Interrupt priority)
8
16
read-write
SPI_IRQn_prio
SPI_IRQn[7:0] bits (Interrupt priority)
0
8
read-write
IPR4
Interrupt priority register 4
0x310
32
read-write
n
0x0
0x0
GPIO2_IRQn_prio
GPIO2_IRQn[7:0] bits (Interrupt priority)
0
8
read-write
GPIO3_IRQn_prio
GPIO3_IRQn[7:0] bits (Interrupt priority)
8
16
read-write
GPIO4_IRQn_prio
GPIO4_IRQn[7:0] bits (Interrupt priority)
16
24
read-write
SWTIM_IRQn_prio
SWTIM_IRQn[7:0] bits (Interrupt priority)
24
32
read-write
IPR5
Interrupt priority register 5
0x314
32
read-write
n
0x0
0x0
PCM_IRQn_prio
PCM_IRQn[7:0] bits (Interrupt priority)
8
16
read-write
SRC_IN_IRQn_prio
SRC_IN_IRQn[7:0] bits (Interrupt priority)
16
24
read-write
SRC_OUT_IRQn_prio
SRC_OUT_IRQn[7:0] bits (Interrupt priority)
24
32
read-write
WKUP_QUADEC_IRQn_prio
WKUP_QUADEC_IRQn[7:0] bits (Interrupt priority)
0
8
read-write
IPR6
Interrupt priority register 6
0x318
32
read-write
n
0x0
0x0
DMA_IRQn_prio
DMA_IRQn[7:0] bits (Interrupt priority)
0
8
read-write
ISER
Interrupt set-enable register
0x0
32
read-write
n
0x0
0x0
ADC_IRQn
ADC_IRQn (Interrupt set-enable bit)
6
7
read-write
BLE_GEN_IRQn
BLE_GEN_IRQn (Interrupt set-enable bit)
1
2
read-write
BLE_RF_DIAG_IRQn
BLE baseband or Radio diagnostic (Interrupt set-enable bit))
8
9
read-write
BLE_WAKEUP_LP_IRQn
BLE_WAKEUP_LP_IRQn (Interrupt set-enable bit)
0
1
read-write
DMA_IRQn
DMA Interrupt (set-enable bit)
20
21
read-write
GPIO0_IRQn
GPIO0 interrupt through debounce (Interrupt set-enable bit)
10
11
read-write
GPIO1_IRQn
GPIO1 interrupt through debounce (Interrupt set-enable bit)
11
12
read-write
GPIO2_IRQn
GPIO2 interrupt through debounce (Interrupt set-enable bit)
12
13
read-write
GPIO3_IRQn
IGPIO3 interrupt through debounce (Interrupt set-enable bit)
13
14
read-write
GPIO4_IRQn
GPIO4 interrupt through debounce (Interrupt set-enable bit)
14
15
read-write
I2C_IRQn
I2C_IRQn (Interrupt set-enable bit)
4
5
read-write
KEYBRD_IRQn
KEYBRD_IRQn (Interrupt set-enable bit)
7
8
read-write
PCM_IRQn
PCM Interrupt (set-enable bit)
17
18
read-write
RFCAL_IRQn
RFCAL_IRQn (Interrupt set-enable bit)
9
10
read-write
SPI_IRQn
SPI_IRQn (Interrupt set-enable bit)
5
6
read-write
SRC_IN_IRQn
Sample rate converter input Interrupt (set-enable bit)
18
19
read-write
SRC_OUT_IRQn
Sample rate converter output Interrupt (set-enable bit)
19
20
read-write
SWTIM_IRQn
Software timer Interrupt (set-enable bit)
15
16
read-write
UART2_IRQn
UART2_IRQn (Interrupt set-enable bit)
3
4
read-write
UART_IRQn
UART_IRQn (Interrupt set-enable bit)
2
3
read-write
WKUP_QUADEC_IRQn
Combined Wake up Capture Timer, GPIO and QuadDecoder interrupt (set-enable bit)
16
17
read-write
ISPR
Interrupt set-pending register
0x100
32
read-write
n
0x0
0x0
ADC_IRQn
ADC_IRQn (Interrupt set-pending bit)
6
7
read-write
BLE_GEN_IRQn
BLE_GEN_IRQn (Interrupt set-pending bit)
1
2
read-write
BLE_RF_DIAG_IRQn
BLE baseband or Radio diagnostic (Interrupt set-pending bit))
8
9
read-write
BLE_WAKEUP_LP_IRQn
BLE_WAKEUP_LP_IRQn (Interrupt set-pending bit)
0
1
read-write
DMA_IRQn
DMA Interrupt (set-pending bit)
20
21
read-write
GPIO0_IRQn
GPIO0 interrupt through debounce (Interrupt set-pending bit)
10
11
read-write
GPIO1_IRQn
GPIO1 interrupt through debounce (Interrupt set-pending bit)
11
12
read-write
GPIO2_IRQn
GPIO2 interrupt through debounce (Interrupt set-pending bit)
12
13
read-write
GPIO3_IRQn
IGPIO3 interrupt through debounce (Interrupt set-pending bit)
13
14
read-write
GPIO4_IRQn
GPIO4 interrupt through debounce (Interrupt set-pending bit)
14
15
read-write
I2C_IRQn
I2C_IRQn (Interrupt set-pending bit)
4
5
read-write
KEYBRD_IRQn
KEYBRD_IRQn (Interrupt set-pending bit)
7
8
read-write
PCM_IRQn
PCM Interrupt (set-pending bit)
17
18
read-write
RFCAL_IRQn
RFCAL_IRQn (Interrupt set-pending bit)
9
10
read-write
SPI_IRQn
SPI_IRQn (Interrupt set-pending bit)
5
6
read-write
SRC_IN_IRQn
Sample rate converter input Interrupt (set-pending bit)
18
19
read-write
SRC_OUT_IRQn
Sample rate converter output Interrupt (set-pending bit)
19
20
read-write
SWTIM_IRQn
Software timer Interrupt (set-pending bit)
15
16
read-write
UART2_IRQn
UART2_IRQn (Interrupt set-pending bit)
3
4
read-write
UART_IRQn
UART_IRQn (Interrupt set-pending bit)
2
3
read-write
WKUP_QUADEC_IRQn
Combined Wake up Capture Timer, GPIO and QuadDecoder interrupt (set-pending bit)
16
17
read-write
otpc580_gr01
otpc580_gr01 registers
Peripheral_Registers
0x0
0x0
0x20
registers
n
OTPC_AHBADR_REG
AHB master start address
0xC
32
read-write
n
0x0
0x0
OTPC_AHBADR
Tthe AHB address used by the AHB master interface of the controller ( bits [31:2]).
2
32
read-write
OTPC_CELADR_REG
Macrocell start address
0x10
32
read-write
n
0x0
0x0
OTPC_CELADR
Defines a word address inside the macrocell. Used in modes AREAD and APROG and is automatically updated.
0
13
read-write
OTPC_FFPRT_REG
Ports access to fifo logic
0x18
32
read-write
n
0x0
0x0
OTPC_FFPRT
Provides access to the fifo through an access port. Write this register with the corresponding data, when the APROG mode is selected and the DMA is disabled. Read from this register the corresponding data, when the AREAD mode is selected and the DMA is disabled. Check OTPC_STAT_FWORDS register for data/space availability, before accessing the fifo.
0
32
read-write
OTPC_FFRD_REG
Latest read data from the OTPC_FFPRT_REG
0x1C
32
read-write
n
0x0
0x0
OTPC_FFRD
Contains the value read from the fifo, after a read of the OTPC_FFPRT_REG register.
0
32
read-only
OTPC_MODE_REG
Mode register
0x0
32
read-write
n
0x0
0x0
OPTC_MODE_PRG_FAST
Defines the timing that will be used for all the programming activities (APROG, MPROG and TWR) 0 - Selects the normal timing 1 - Selects the fast timing
8
9
read-write
OTPC_MODE_FIFO_FLUSH
Writing 1, removes any content from the FIFO. This bit returns automatically to 0.
5
6
read-write
OTPC_MODE_MODE
Defines the mode of operation of the OTPC controller. The encoding of the modes is as follows: 000 - STBY mode 001 - MREAD mode 010 - MPROG mode 011 - AREAD mode 100 - APROG mode 101 - Test mode. Reserved 110 - Test mode. Reserved 111 - Test mode. Reserved To manually move between modes, always return to STBY mode first.
0
3
read-write
OTPC_MODE_PRG_PORT_MUX
Selects the source that is connected to the prg_port port of the controller. 00 - {16'd0, BANDGAP_REG[15:0]} 01 - {RF_RSSI_COMP_CTRL_REG[15:0], 8'd0, RFIO_CTRL1_REG{7:0]} 10 - {3'd0, RF_LNA_CTRL3_REG[4:0], RF_LNA_CTRL2_REG[11:0], RF_LNA_CTRL1_REG[11:0]} 11 - {28'd0, RF_VCO_CTRL_REG[3:0]} See OTPC_MODE_PRG_PORT_SEL about the use of the prg_port
28
30
read-write
OTPC_MODE_PRG_PORT_SEL
Selects an alternative data source for the programming of the OTP macrocells, when the controller is configured in APROG mode. 0 - The fifo will be used as the data source. The fifo will be filled with a way defined by the register OTPC_MODE_USE_DMA. The number of words that will be programmed is defined by OTPC_NWORDS. 1 - Only one word will programmed. The value of the word is contained in the prg_port port of the controller. The values of the registers OTPC_MODE_USE_DMA, OTPC_NWORDS and the contents of the FIFO will not be used.
7
8
read-write
OTPC_MODE_TWO_CC_ACC
Defines the duration of each read from the OTP macrocells. 0 - Reads 16 bits of data every one clock cycle. 1 - Reads 16 bits of data every two clock cycles.
6
7
read-write
OTPC_MODE_USE_DMA
Selects the use of the dma, when the controller is configured in one of the modes: AREAD or APROG. 0 - DMAis not used. The data should be transfered from/to controller through OTPC_FFPRT_REG 1 - DMA is used. Data transfers from/to controller are performed automatically. The AHB base address should be configured in OTPC_AHBADR_REG before the selection of the mode. If programming of the OTPC_MODE_REG is performed through the serial interface,the OTPC_MODE_USE_DMA will be set to 0 automatically. If the controller is in APROG mode and the OTPC_MODE_PRG_PORT_SEL is enabled, the dma will stay inactive.
4
5
read-write
OTPC_NWORDS_REG
Number of words
0x14
32
read-write
n
0x0
0x0
OTPC_NWORDS
The number of words (minus one) for reading/programming during the AREAD/APROG mode. If in APROG mode, and the OTPC_MODE_PRG_PORT_SEL is enabled (=1), this register will not be used and will stay unchanged. During mirroring, this register reflects the current amount of data that will be copied. It keeps its value until be written by the software with a new value. The number of the words that remaining to be processed by the controller is contained in the field OTPC_STAT_NWORDS.
0
13
read-write
OTPC_PCTRL_REG
Bit-programming control register
0x4
32
read-write
n
0x0
0x0
OTPC_PCTRL_BADRL
Selects the bit inside the Lx (x=0,1) byte, which will be programmed in the lower bank.
16
19
read-write
OTPC_PCTRL_BADRU
Selects the bit inside the Ux (x=0,1) byte, which will be programmed in the upper bank.
20
23
read-write
OTPC_PCTRL_BITL
Defines the value of the selected bit in the lower bank, after the programming sequence.
24
25
read-write
OTPC_PCTRL_BITU
Defines the value of the selected bit in the upper bank, after the programming sequence.
26
27
read-write
OTPC_PCTRL_BSELL
Selects between the L1 and L0 byte for the programming sequence in the lower bank. 0 - Program the L0 byte 1 - Program the L1 byte
19
20
read-write
OTPC_PCTRL_BSELU
Selects between the U1 and U0 byte for the programming sequence in the upper bank. 0 - Program the U0 byte 1 - Program the U1 byte -
23
24
read-write
OTPC_PCTRL_ENL
Enables the programming in the lower bank. 0 - The programming sequence is not applied in the lower bank. 1 -The programming sequence is applied in the lower bank.
25
26
read-write
OTPC_PCTRL_ENU
Enables the programming in the upper bank of the OTP. 0 - Programming sequence is not applied in the upper bank. 1 - Programming sequence is applied in the upper bank.
27
28
read-write
OTPC_PCTRL_WADDR
Defines the address of a 32 bits word {U1,L1,U0,L0} in the macrocells, where one or two bits will be programmed. There are two macrocell banks, with 8 bits each. Each bank contribute with two memory positions for each 32 bits word. The Ux, Lx represent the bytes of the upper and lower bank respectively.
0
13
read-write
OTPC_STAT_REG
Status register
0x8
32
read-write
n
0x0
0x0
OTPC_STAT_ARDY
Monitors the progress of read or programming operations while in the AREAD or APROG modes. 0 - The controller is busy while reading or programming (AREAD or APROG modes). 1 - The controller is not busy in AREAD or APROG mode.
4
5
read-only
OTPC_STAT_FWORDS
Indicates the number of words which contained in the fifo of the controller.
8
12
read-only
OTPC_STAT_NWORDS
Contains the current value of the words to be processed.
16
29
read-only
OTPC_STAT_PERROR
Indicates that an error has occurred during the bit-programming process. 0 - No error during the bit-programming process. 1 - The process of bit-programming failed. When the controller is in MPROG mode, this bit should be checked after the end of the programming process (OTPC_STAT_PRDY= 1). During APROG mode, the value of this field is normal to change periodically. Upon finishing the operation in the APROG mode (OTPC_STAT_ARDY= 1), this field indicates if the programming has failed or ended succesfully.
1
2
read-only
OTPC_STAT_PERR_L
Indicates the lower bank as the source of a programming error. The value is valid when OTPC_STAT_PERROR is valid. 0 - There is no programming error in the lower bank 1 - A programming error has occured in the lower bank
12
13
read-only
OTPC_STAT_PERR_U
Indicates the upper bank as the source of a programming error. The value is valid when OTPC_STAT_PERROR is valid. 0 - There is no programming error in the upper bank 1 - A programming error has occured in the upper bank
13
14
read-only
OTPC_STAT_PRDY
Indicates the state of a bit-programming process. 0 - The controller is busy. A bit-programming is in progress 1 - The logic which performs bit-programming is idle. When the controller is in MPROG mode, this bit should be used to monitor the progress of a programming request. During APROG mode, the value of this field it is normal to changing periodically.
0
1
read-only
OTPC_STAT_TERROR
Indicates the result of a test sequence. Should be checked after the end of a TBLANK, TDEC and TWR mode (OTPC_STAT_TRDY= 1). 0 - The test sequence ends with no error. 1 - The test sequence has failed.
3
4
read-only
OTPC_STAT_TERR_L
Indicates the lower bank as the source of a test error. The value is valid when OTPC_STAT_TERROR is valid. 0 - There is no test error in the lower bank 1 - A test error has occured in the lower bank
14
15
read-only
OTPC_STAT_TERR_U
Indicates the upper bank as the source of a test error. This value is valid when OTPC_STAT_TERROR is valid. 0 - There is no test error in the upper bank 1 - A test error has occured in the upper bank
15
16
read-only
OTPC_STAT_TRDY
Indicates the state of a test mode. Should be used to monitor the progress of the TBLANK, TDEC and TWR modes. 0 - The controller is busy. A test mode is in progress. 1 - There is no active test mode.
2
3
read-only
quadec580_gr01
quadec580_gr01 registers
Peripheral_Registers
0x0
0x0
0xC
registers
n
QDEC_CLOCKDIV_REG
Clock divider register
0x6
16
read-write
n
0x0
0x0
clock_divider
Contains the number of the input clock cycles minus one, that are required to generate one logic clock cycle.
0
10
read-write
QDEC_CTRL2_REG
Quad Decoder control register
0x8
16
read-write
n
0x0
0x0
CHX_PORT_SEL
Defines which GPIOs are mapped on Channel X 0: none 1: P0[0] -> CHX_A, P0[1] -> CHX_B 2: P0[2] -> CHX_A, P0[3] -> CHX_B 3: P0[4] -> CHX_A, P0[5] -> CHX_B 4: P0[6] -> CHX_A, P0[7] -> CHX_B 5: P1[0] -> CHX_A, P1[1] -> CHX_B 6: P1[2] -> CHX_A, P1[3] -> CHX_B 7: P2[3] -> CHX_A, P2[4] -> CHX_B 8: P2[5] -> CHX_A, P2[6] -> CHX_B 9: P2[7] -> CHX_A, P2[8] -> CHX_B 10: P2[9] -> CHX_A, P2[0] -> CHX_B 11..15: None
0
4
read-write
CHY_PORT_SEL
Defines which GPIOs are mapped on Channel Y 0: none 1: P0[0] -> CHY_A, P0[1] -> CHY_B 2: P0[2] -> CHY_A, P0[3] -> CHY_B 3: P0[4] -> CHY_A, P0[5] -> CHY_B 4: P0[6] -> CHY_A, P0[7] -> CHY_B 5: P1[0] -> CHY_A, P1[1] -> CHY_B 6: P1[2] -> CHY_A, P1[3] -> CHY_B 7: P2[3] -> CHY_A, P2[4] -> CHY_B 8: P2[5] -> CHY_A, P2[6] -> CHY_B 9: P2[7] -> CHY_A, P2[8] -> CHY_B 10: P2[9] -> CHY_A, P2[0] -> CHY_B 11..15: None
4
8
read-write
CHZ_PORT_SEL
Defines which GPIOs are mapped on Channel Z 0: none 1: P0[0] -> CHZ_A, P0[1] -> CHZ_B 2: P0[2] -> CHZ_A, P0[3] -> CHZ_B 3: P0[4] -> CHZ_A, P0[5] -> CHZ_B 4: P0[6] -> CHZ_A, P0[7] -> CHZ_B 5: P1[0] -> CHZ_A, P1[1] -> CHZ_B 6: P1[2] -> CHZ_A, P1[3] -> CHZ_B 7: P2[3] -> CHZ_A, P2[4] -> CHZ_B 8: P2[5] -> CHZ_A, P2[6] -> CHZ_B 9: P2[7] -> CHZ_A, P2[8] -> CHZ_B 10: P2[9] -> CHZ_A, P2[0] -> CHZ_B 11..15: None
8
12
read-write
QDEC_CTRL_REG
Quad Decoder control register
0x0
16
read-write
n
0x0
0x0
QD_IRQ_CLR
Writing 1 to this bit clears the interrupt. This bit is autocleared
1
2
read-write
QD_IRQ_MASK
0: interrupt is masked 1: interrupt is enabled
0
1
read-write
QD_IRQ_STATUS
Interrupt Status. If 1 an interrupt has occured.
2
3
read-only
QD_IRQ_THRES
The number of events on either counter (X or Y) that need to be reached before an interrupt is generated. If 0 is written, then threshold is considered to be 1.
3
10
read-write
QDEC_XCNT_REG
Counter value of the X Axis
0x2
16
read-write
n
0x0
0x0
X_counter
Contains a signed value of the events. Zero when channel is disabled
0
16
read-only
QDEC_YCNT_REG
Counter value of the Y Axis
0x4
16
read-write
n
0x0
0x0
Y_counter
Contains a signed value of the events. Zero when channel is disabled
0
16
read-only
QDEC_ZCNT_REG
Z_counter
0xA
16
read-write
n
0x0
0x0
Z_counter
Contains a signed value of the events. Zero when channel is disabled
0
16
read-only
rfpt580_gr01
rfpt580_gr01 registers
Peripheral_Registers
0x0
0x0
0x8
registers
n
RFPT_ADDR_REG
AHB master start address
0x2
16
read-write
n
0x0
0x0
RFPT_ADDR
It is the AHB address used by the AHB-Lite master interface of the controller (the bits [15:2]).
2
16
read-write
RFPT_CTRL_REG
Control register
0x0
16
read-write
n
0x0
0x0
RFPT_PACK_EN
Starts the capturing of the data from the selected source ( RFPT_PACK_SEL ). 0 - There is no capturing of data. The packer of data is idle. 1 - The controller captures data. The packing of the data in words, is in progress. Should be written with 1 in order to start the acquisition of data. After the acquisition of a predefined number of words ( RFPT_LEN ), this bit will be auto cleared.
0
1
read-write
RFPT_PACK_SEL
Selects the source of data that will be captured. 0 - Will capture the output of the two ADC. 1 - Will capture the output of the Phase Detector.
1
2
read-write
RFPT_LEN_REG
Data length register
0x4
16
read-write
n
0x0
0x0
RFPT_LEN
The number of words (minus one) that should be transfered. When the selected source of data is the two ADC ( RFPT_PACK_SEL ==0), will capture 2*( RFPT_LEN + 1) samples from each ADC. Otherwise ( RFPT_PACK_SEL ==1), will capture 4*( RFPT_LEN + 1) samples from the Phase Detector.
0
14
read-write
RFPT_STAT_REG
Status register
0x6
16
read-write
n
0x0
0x0
RFPT_ACTIVE
Indicates the state of the controller. 0 - The controller is idle. 1 - The controller is active. The capturing process and/or the dma activity is in progress. The controller will activated (RFPT_ACTIVE == 1), when RFPT_PACK_EN will be written with 1. Will return to inactive state, after the end of the capturing process (RFPT_PACK_EN==0) and the transfer of all of the data to the memory.
0
1
read-only
RFPT_OFLOW_STK
Indicates that during the transfer of the data, at least one overflow has detected to the fifo. 0 - The transfer completed without overflows. 1 - At least one overflow occured in the fifo. Write 1 to clear this bit.
1
2
read-write
riscutil580_gpreg_nl01
riscutil580_gpreg_nl01 registers
Peripheral_Registers
0x0
0x0
0xA
registers
n
DEBUG_REG
Various debug information register.
0x4
16
read-write
n
0x0
0x0
DEBUGS_FREEZE_EN
Default '1', freezing of the on-chip timers is enabled when the Cortex-M0 is halted in DEBUG State. If '0', freezing of the on-chip timers is depending on FREEZE_REG when the Cortex-M0 is halted in DEBUG State except the watchdog timer. The watchdog timer is always frozen when the Cortex-M0 is halted in DEBUG State.
0
1
read-write
GP_CONTROL_REG
General purpose system control register.
0x8
16
read-write
n
0x0
0x0
BLE_WAKEUP_REQ
If '1', the BLE wakes up. Must be kept high at least for 1 low power clock period. If the BLE is in deep sleep state, then by setting this bit it will cause the wakeup LP IRQ to be asserted with a delay of 3 to 4 low power cycles.
0
1
read-write
EM_MAP
Select the mapping of the Exchange memory pages. 0: EM size 0 kB, SysRAM size 42 kB 1: EM size 2 kB, SysRAM size 48 kB 2: EM size 3 kB, SysRAM size 47 kB 3: EM size 4 kB, SysRAM size 46 kB 4: EM size 5 kB, SysRAM size 45 kB 5: EM size 6 kB, SysRAM size 44 kB 6: EM size 7 kB, SysRAM size 43 kB 7: EM size 8 kB, SysRAM size 42 kB 8: Reserved 9: EM size 4 kB, SysRAM size 40 kB 10: EM size 5 kB, SysRAM size 40 kB 11: EM size 6 kB, SysRAM size 40 kB 12: EM size 7 kB, SysRAM size 40 kB 13: EM size 8 kB, SysRAM size 40 kB 14: EM size 9 kB, SysRAM size 40 kB 15: EM size 10 kB, SysRAM size 40 kB 16: Reserved 17: EM size 6 kB, SysRAM size 38 kB 18: EM size 7 kB, SysRAM size 38 kB 19: EM size 8 kB, SysRAM size 38 kB 20: EM size 9 kB, SysRAM size 38 kB 21: EM size 10 kB, SysRAM size 38 kB 22: EM size 11 kB, SysRAM size 38 kB 23: EM size 12 kB, SysRAM size 38 kB other: Reserved.
1
6
read-write
GP_STATUS_REG
General purpose system status register.
0x6
16
read-write
n
0x0
0x0
CAL_PHASE
If '1', it designates that the chip is in Calibration Phase i.e. the OTP has been initially programmed but no Calibration has occured.
0
1
read-write
RESET_FREEZE_REG
Controls unfreezing of various timers/counters.
0x2
16
read-write
n
0x0
0x0
FRZ_BLETIM
If '1', the the BLE master clock continues, '0' is discarded.
2
3
read-write
FRZ_SWTIM
If '1', the SW Timer (TIMER0) continues, '0' is discarded.
1
2
read-write
FRZ_WDOG
If '1', the watchdog timer continues, '0' is discarded.
3
4
read-write
FRZ_WKUPTIM
If '1', the Wake Up Timer continues, '0' is discarded.
0
1
read-write
SET_FREEZE_REG
Controls freezing of various timers/counters.
0x0
16
read-write
n
0x0
0x0
FRZ_BLETIM
If '1', the BLE master clock is frozen, '0' is discarded.
2
3
read-write
FRZ_SWTIM
If '1', the SW Timer (TIMER0) is frozen, '0' is discarded.
1
2
read-write
FRZ_WDOG
If '1', the watchdog timer is frozen, '0' is discarded. WATCHDOG_CTRL_REG[NMI_RST] must be '0' to allow the freeze function.
3
4
read-write
FRZ_WKUPTIM
If '1', the Wake Up Timer is frozen, '0' is discarded.
0
1
read-write
riscutil580_wdog_nl00
riscutil580_wdog_nl00 registers
Peripheral_Registers
0x0
0x0
0x4
registers
n
WATCHDOG_CTRL_REG
Watchdog control register.
0x2
16
read-write
n
0x0
0x0
NMI_RST
0 = Watchdog timer generates NMI at value 0, and WDOG (SYS) reset at <=-16. Timer can be frozen /resumed using SET_FREEZE_REG[FRZ_WDOG]/ RESET_FREEZE_REG[FRZ_WDOG]. 1 = Watchdog timer generates a WDOG (SYS) reset at value 0 and can not be frozen by Software. Note that this bit can only be set to 1 by SW and only be reset with a WDOG (SYS) reset or SW reset. The watchdog is always frozen when the Cortex-M0 is halted in DEBUG State.
0
1
read-write
WATCHDOG_REG
Watchdog timer register.
0x0
16
read-write
n
0x0
0x0
WDOG_VAL
Write: Watchdog timer reload value. Note that all bits 15-9 must be 0 to reload this register. Read: Actual Watchdog timer value. Decremented by 1 every 10.24 msec. Bit 8 indicates a negative counter value. 2, 1, 0, 1FF16, 1FE16 etc. An NMI or WDOG (SYS) reset is generated under the following conditions: If WATCHDOG_CTRL_REG[NMI_RST] = 0 then If WDOG_VAL = 0 -> NMI (Non Maskable Interrupt) if WDOG_VAL = 1F016 -> WDOG reset -> reload FF16 If WATCHDOG_CTRL_REG[NMI_RST] = 1 then if WDOG_VAL <= 0 -> WDOG reset -> reload FF16
0
8
read-write
WDOG_VAL_NEG
0 = Watchdog timer value is positive. 1 = Watchdog timer value is negative.
8
9
read-write
WDOG_WEN
0000.000 = Write enable for Watchdog timer else Write disable. This filter prevents unintentional presetting the watchdog with a SW run-away.
9
16
write-only
r_rfcu580_nl01
r_rfcu580_nl01 registers
Peripheral_Registers
0x0
0x0
0xC72
registers
n
BIAS_CTRL1_REG
0x600
16
read-write
n
0x0
0x0
CP_BIAS_SET
Tuning of the charge pump bias current
4
8
read-write
IFF_BIAS_SET
Tuning of the IF filter bias current
12
16
read-write
MIX_BIAS_SET
Tuning of the mixer bias current
0
4
read-write
VCO_BIAS_SET
Tuning of the VCO bias current
8
12
read-write
RF_ADCI_DC_OFFSET_REG
Must be Retained
0x310
16
read-write
n
0x0
0x0
ADC_OFFN_I_RD
DC offset compensation in the I path (inverting input) in sign-magnitude notarion (i.e. -31 : 1 : 31 mV)
8
16
read-only
ADC_OFFP_I_RD
DC offset compensation in the I path (non-inverting input) in sign-magnitude notarion (i.e. -31 : 1 : 31 mV)
0
8
read-only
RF_ADCQ_DC_OFFSET_REG
Must be Retained
0x312
16
read-write
n
0x0
0x0
ADC_OFFN_Q_RD
DC offset compensation in the Q path (inverting input) in sign-magnitude notarion (i.e. -31 : 1 : 31 mV)
8
16
read-only
ADC_OFFP_Q_RD
DC offset compensation in the Q path (non-inverting input) in sign-magnitude notarion (i.e. -31 : 1 : 31 mV)
0
8
read-only
RF_ADC_CTRL1_REG
0x830
16
read-write
n
0x0
0x0
ADC_DC_OFFSET_SEL
0: Normal operation (i.e. Use automatically calibrated value) 1: Use ADC_OFFx_y_WR to set the DC offset compensation values in the ADC (x = N or P, y = I or Q
0
1
read-write
ADC_MUTE
0: Normal operation 1: Short the inputs of the ADC (used for DC offset cal)
13
14
read-write
ADC_SIGN
Change polarity of ADC input.
14
15
read-write
RF_ADC_CTRL2_REG
0x832
16
read-write
n
0x0
0x0
ADC_OFFN_I_WR
External value for the DC offset compensation in the I path negative side. With common mode input voltage at Vpwrp/2, this value is 512-ADC_OFFP_Q_WR.
8
16
read-write
ADC_OFFP_I_WR
External value for the DC offset compensation in the I path positive side.
0
8
read-write
RF_ADC_CTRL3_REG
0x834
16
read-write
n
0x0
0x0
ADC_OFFN_Q_WR
External value for the DC offset compensation in the Q path negative side. With common mode input voltage at Vpwrp/2, this value is 512-ADC_OFFP_Q_WR.
8
16
read-write
ADC_OFFP_Q_WR
External value for the DC offset compensation in the Q path positive side.
0
8
read-write
RF_AFC_CTRL_REG
0x864
16
read-write
n
0x0
0x0
AFC_MODE
Choose the method to use for AFC tracking during the slot Description TBD
0
4
read-write
POLE1
Choose the method to use for AFC tracking during the slot Description TBD
4
6
read-write
POLE2
Choose the method to use for AFC tracking during the slot Description TBD
6
8
read-write
RF_AGC_CTRL1_REG
0x860
16
read-write
n
0x0
0x0
AGC_MODE
Choose the method to use for AGC evaluation Description TBD
14
16
read-write
AGC_TH_HIGH
AGC hysteresis high threshold (switch up one AGC_SETTING_R step when exceeding this level)
7
14
read-write
AGC_TH_LOW
AGC hysteresis low threshold (switch down one AGC_SETTING_R step when dropping below this level)
0
7
read-write
RF_AGC_CTRL2_REG
0x862
16
read-write
n
0x0
0x0
AGCSETTING_SEL
LNA, VGA1 and VGA2 gains '0': controlled by AGC'1': provided manually through AGCSETTING_WR
7
8
read-write
AGCSETTING_WR
Fixed AGC setting to be used to configure LNA, VGA1 and VGA2 when AGCSETTING_SEL = 1 0: Highest gain as configured in RF_AGC_LUT_01_REG 1: Lower gain as configured in RF_AGC_LUT_01_REG 2: Still lower gain as configured in RF_AGC_LUT_23_REG ... 9-F: Lowest gain as configured in RF_AGC_LUT_89_REG
8
12
read-write
EN_FRZ_GAIN
'0': AGC always active'1': Freeze gain after Access Address detection
6
7
read-write
RSSI_TH
RSSI threshold for the packet detection
0
6
read-write
SLOW_AGC
Enable the slow AGC mode (no consecutive AGC setting switches)
12
13
read-write
RF_AGC_LUT_01_REG
0x850
16
read-write
n
0x0
0x0
LNA_GAIN0
LNA gain setting while in AGC setting 0
6
8
read-write
LNA_GAIN1
LNA gain setting while in AGC setting 0
14
16
read-write
VGA1_GAIN0
VGA1 gain setting while in AGC setting 0
3
6
read-write
VGA1_GAIN1
VGA1 gain setting while in AGC setting 1
11
14
read-write
VGA2_GAIN0
VGA2 gain setting while in AGC setting 0
0
3
read-write
VGA2_GAIN1
VGA2 gain setting while in AGC setting 1
8
11
read-write
RF_AGC_LUT_23_REG
0x852
16
read-write
n
0x0
0x0
VGA1_GAIN2
VGA1 gain setting while in AGC setting 2
3
6
read-write
VGA1_GAIN3
VGA1 gain setting while in AGC setting 3
11
14
read-write
VGA2_GAIN2
VGA2 gain setting while in AGC setting 2
0
3
read-write
VGA2_GAIN3
VGA2 gain setting while in AGC setting 3
8
11
read-write
RF_AGC_LUT_45_REG
0x854
16
read-write
n
0x0
0x0
LNA_GAIN4
LNA gain setting while in AGC setting 4
6
8
read-write
LNA_GAIN5
LNA gain setting while in AGC setting 5
14
16
read-write
VGA1_GAIN4
VGA1 gain setting while in AGC setting 4
3
6
read-write
VGA1_GAIN5
VGA1 gain setting while in AGC setting 5
11
14
read-write
VGA2_GAIN4
VGA2 gain setting while in AGC setting 4
0
3
read-write
VGA2_GAIN5
VGA2 gain setting while in AGC setting 5
8
11
read-write
RF_AGC_LUT_67_REG
0x856
16
read-write
n
0x0
0x0
LNA_GAIN6
LNA gain setting while in AGC setting 6
6
8
read-write
LNA_GAIN7
LNA gain setting while in AGC setting 7
14
16
read-write
VGA1_GAIN6
VGA1 gain setting while in AGC setting 6
3
6
read-write
VGA1_GAIN7
VGA1 gain setting while in AGC setting 7
11
14
read-write
VGA2_GAIN6
VGA2 gain setting while in AGC setting 6
0
3
read-write
VGA2_GAIN7
VGA2 gain setting while in AGC setting 7
8
11
read-write
RF_AGC_LUT_89_REG
0x858
16
read-write
n
0x0
0x0
LNA_GAIN8
LNA gain setting while in AGC setting 8
6
8
read-write
LNA_GAIN9
LNA gain setting while in AGC setting 9
14
16
read-write
VGA1_GAIN8
VGA1 gain setting while in AGC setting 8
3
6
read-write
VGA1_GAIN9
VGA1 gain setting while in AGC setting 9
11
14
read-write
VGA2_GAIN8
VGA2 gain setting while in AGC setting 8
0
3
read-write
VGA2_GAIN9
VGA2 gain setting while in AGC setting 9
8
11
read-write
RF_AGC_RESULT_REG
0x900
16
read-write
n
0x0
0x0
AFC_RD
Frequency offset estimation (in 2s complement) with a resolution of approximately 5 kHz.
0
8
read-only
AGCSETTING_RD
AGC setting as automatically selected in receive mode to configure LNA, VGA1 and VGA2 0: Highest gain as configured in RF_AGC_LUT_01_REG 1: Lower gain as configured in RF_AGC_LUT_01_REG 2: Still lower gain as configured in RF_AGC_LUT_23_REG ... 9-F: Lowest gain as configured in RF_AGC_LUT_89_REG
8
12
read-only
RF_BMCW_REG
Changed functionality of bits [7:6]
0x0
16
read-write
n
0x0
0x0
CN_SEL
Select between: 1 = use CN_WR as channel number 0 = use BLE Frequency word (normal function).
8
9
read-write
CN_WR
[7:6] = offset to RFCAL_CAP_WR, coarse calibraton LUT [5:0] = channel number
0
8
read-write
RF_CALCAP1_REG
0x60
16
read-write
n
0x0
0x0
VCO_CALCAP_LOW
Lowest 16 bits of vco_calcap
0
16
read-only
RF_CALCAP2_REG
0x62
16
read-write
n
0x0
0x0
VCO_CALCAP_HIGH
Highest 2 bits of vco_calcap.
0
2
read-only
RF_CALSTATE_REG
0x40
16
read-write
n
0x0
0x0
CALSTATE
Value of the calstate state machine
0
4
read-only
RF_CAL_CTRL_REG
0x200
16
read-write
n
0x0
0x0
DC_OFFSET_CAL_DIS
Do not calibrate the VGA2 Offset during Cal cycle
4
5
read-write
EO_CAL
End of calibration trigger. Reading returns the eo_cal status signal which can be cleared by writing to RF_IRQ_CTRL_REG.EO_CAL_CLEAR
1
2
read-only
IFF_CAL_DIS
Do not calibrate the IFF center frequency during Cal cycle
3
4
read-write
MGAIN_CAL_DIS
Do not calibrate the VCO and Modulation Gain during Cal cycle
2
3
read-write
SO_CAL
Start of calibration trigger.Writing a 1 starts calibration.1Reading returns the calibration status (1 = busy calibrating).
0
1
read-write
VCO_CAL_DIS
Do not calibrate the VCO during Cal cycle
5
6
read-write
RF_CNTRL_TIMER_10_REG
0x512
16
read-write
n
0x0
0x0
RESET_OFFSET
Offset w.r.t. end switch instant eo_rx/eo_tx.
8
16
read-write
SET_OFFSET
Offset w.r.t. start switch instant so_rx/eo_tx.
0
8
read-write
RF_CNTRL_TIMER_11_REG
0x514
16
read-write
n
0x0
0x0
RESET_OFFSET
Offset w.r.t. end switch instant eo_tx/eo_tx.
8
16
read-write
SET_OFFSET
Offset w.r.t. start switch instant so_tx/eo_tx.
0
8
read-write
RF_CNTRL_TIMER_12_REG
0x516
16
read-write
n
0x0
0x0
RESET_OFFSET
Offset w.r.t. end switch instant eo_rx/eo_tx.
8
16
read-write
SET_OFFSET
Offset w.r.t. start switch instant so_rx/eo_tx.
0
8
read-write
RF_CNTRL_TIMER_13_REG
0x518
16
read-write
n
0x0
0x0
RESET_OFFSET
Offset w.r.t. end switch instant eo_rx/eo_tx.
8
16
read-write
SET_OFFSET
Offset w.r.t. start switch instant so_rx/eo_tx.
0
8
read-write
RF_CNTRL_TIMER_14_REG
0x51A
16
read-write
n
0x0
0x0
RESET_OFFSET
Offset w.r.t. end switch instant eo_rx/eo_tx.
8
16
read-write
SET_OFFSET
Offset w.r.t. start switch instant so_rx/eo_tx.
0
8
read-write
RF_CNTRL_TIMER_1_REG
0x500
16
read-write
n
0x0
0x0
RESET_OFFSET
Offset w.r.t. end switch instant eo_rx/eo_tx
8
16
read-write
SET_OFFSET
Offset w.r.t. start switch instant so_rx/so_tx.
0
8
read-write
RF_CNTRL_TIMER_2_REG
0x502
16
read-write
n
0x0
0x0
RESET_OFFSET
Offset w.r.t. end switch instant eo_rx/eo_tx.
8
16
read-write
SET_OFFSET
Offset w.r.t. start switch instant so_rx/so_tx.
0
8
read-write
RF_CNTRL_TIMER_3_REG
0x504
16
read-write
n
0x0
0x0
RESET_OFFSET
Offset w.r.t. end switch instant eo_rx/eo_tx.
8
16
read-write
SET_OFFSET
Offset w.r.t. start switch instant so_rx/so_tx.
0
8
read-write
RF_CNTRL_TIMER_4_REG
0x506
16
read-write
n
0x0
0x0
RESET_OFFSET
Offset w.r.t. end switch instant eo_rx/eo_tx.
8
16
read-write
SET_OFFSET
Offset w.r.t. start switch instant so_rx/eo_tx.
0
8
read-write
RF_CNTRL_TIMER_5_REG
0x508
16
read-write
n
0x0
0x0
RESET_OFFSET
Offset w.r.t. end switch instant eo_rx/eo_tx.
8
16
read-write
SET_OFFSET
Offset w.r.t. start switch instant so_rx/eo_tx.
0
8
read-write
RF_CNTRL_TIMER_6_REG
0x50A
16
read-write
n
0x0
0x0
RESET_OFFSET
Offset w.r.t. end switch instant eo_rx/eo_tx.
8
16
read-write
SET_OFFSET
Offset w.r.t. start switch instant so_rx/eo_tx.
0
8
read-write
RF_CNTRL_TIMER_7_REG
0x50C
16
read-write
n
0x0
0x0
RESET_OFFSET
Offset w.r.t. end switch instant eo_tx/eo_tx.
8
16
read-write
SET_OFFSET
Offset w.r.t. start switch instant so_tx/eo_tx.
0
8
read-write
RF_CNTRL_TIMER_8_REG
0x50E
16
read-write
n
0x0
0x0
RESET_OFFSET
Offset w.r.t. end switch instant eo_rx/eo_tx.
8
16
read-write
SET_OFFSET
Offset w.r.t. start switch instant so_rx/eo_tx.
0
8
read-write
RF_CNTRL_TIMER_9_REG
0x510
16
read-write
n
0x0
0x0
RESET_OFFSET
Offset w.r.t. end switch instant eo_rx/eo_tx.
8
16
read-write
SET_OFFSET
Offset w.r.t. start switch instant so_rx/eo_tx.
0
8
read-write
RF_CP_CTRL_REG
0xC50
16
read-write
n
0x0
0x0
CP_CUR_RX
CP current setting during PLL - lock in RX mode same coding as for CP_CUR_TX
8
12
read-write
CP_CUR_SET_RX
Chargepump current setting during PLL settling in RX mode. same coding as for CP_CUR_TX
0
4
read-write
CP_CUR_SET_TX
Chargepump current setting during PLL settling in TX mode same coding as for CP_CUR_TX
4
8
read-write
CP_CUR_TX
CP current setting during PLL - Lock in TX mode 1111: 45 µA (fastest, setting 0) 0111: 15 µA (setting 1) 0011: 7.5 µA (setting 2) 0001: 3.75 µA (slowest, setting 3) Intermediate values are possible (but not recommended). Calculate the effective value with: bit 0: 3.75 µA bit 1: 3.75 µA bit 2: 7.5 µA bit 3: 30 µA
12
16
read-write
RF_DC_OFFSET_CTRL1_REG
0x866
16
read-write
n
0x0
0x0
DCOFFSET_I_WR
DC offset compensation value in I channel valid when DCOFFSET_SEL = 1
0
8
read-write
DCOFFSET_Q_WR
DC offset compensation value in Q channel valid when DCOFFSET_SEL = 1
8
16
read-write
RF_DC_OFFSET_CTRL2_REG
0x868
16
read-write
n
0x0
0x0
DCNGAIN
Number of gain settings for the full DC offset calibration
7
9
read-write
DCNSTEP
Number of the steps per.gain setting for the full or partial DC offset calibrations
4
7
read-write
DCOFFSET_SEL
'0': Normal operation '1': Use the manual DC offset compensation values from RF_DC_OFFSET_CTRL1_REG
0
1
read-write
DCPARCAL_EN
Enable flag for the partial DC offset calibration (executed when the demodulator is enabled).
1
2
read-write
DCPOLE
Selects the pole of the digital high pass fitlers Encoding: TBD
2
4
read-write
RF_DC_OFFSET_CTRL3_REG
0x86A
16
read-write
n
0x0
0x0
DCBETA_I
Inphase feedback gain for the DC offset calibration
0
8
read-write
DCBETA_Q
Quadrature feedback gain for the DC offset calibration
8
16
read-write
RF_DC_OFFSET_CTRL4_REG
0x86C
16
read-write
n
0x0
0x0
DCAGCSETTING_FULL0
AGC setting for last the gain step for the full DC offset calibration
0
4
read-write
DCAGCSETTING_FULL1
AGC setting for second last the gain step for the full DC offset calibration
4
8
read-write
DCAGCSETTING_FULL2
AGC setting for third last the gain step for the full DC offset calibration
8
12
read-write
DCAGCSETTING_FULL3
AGC setting for forth last the gain step for the full DC offset calibration
12
16
read-write
RF_DC_OFFSET_RESULT_REG
Must be Retained
0x314
16
read-write
n
0x0
0x0
DCOFFSET_I_RD
DC offset compensation value in I channel valid when DCOFFSET_SEL = 0.
0
8
read-only
DCOFFSET_Q_RD
DC offset compensation value in Q channel valid when DCOFFSET_SEL = 0
8
16
read-only
RF_DEM_CTRL_REG
0x840
16
read-write
n
0x0
0x0
DEM_HSI_POL
Invert 'frequency' polarity of the demodulator
1
2
read-write
EQUAL_EN
Enable the equalizer in the demodulator
6
7
read-write
MATCH0101_TH
Threshold for the 0101 pattern matching
2
6
read-write
RXDATA_INV
'0': Normal operation '1': Invert the polarity of the received bits
0
1
read-write
RF_ENABLE_CONFIG10_REG
0x412
16
read-write
n
0x0
0x0
adc_en
Timing configuration for enable of the ADC
8
16
read-write
vco_en
Timing configuration for enable of the VCO
0
8
read-write
RF_ENABLE_CONFIG11_REG
0x414
16
read-write
n
0x0
0x0
cp_en
Timing configuration for enable of CP
0
8
read-write
md_lobuf_en
Timing configuration for enable of main divider of the LO buffer
8
16
read-write
RF_ENABLE_CONFIG12_REG
0x416
16
read-write
n
0x0
0x0
gauss_en
Timing configuration for the gauss module
0
8
read-write
pfd_en
Timing configuration for the phase frequency detector
8
16
read-write
RF_ENABLE_CONFIG13_REG
0x418
16
read-write
n
0x0
0x0
lobuf_pa_en
Timing configuration for the PA lobuffer
0
8
read-write
rfio_en
Timing configuration for the rfio
8
16
read-write
RF_ENABLE_CONFIG14_REG
0x41A
16
read-write
n
0x0
0x0
div2_en
Timing configuration for the 2 divider
0
8
read-write
lobuf_rxiq_en
Timing configuration for the rxi lobuffer
8
16
read-write
RF_ENABLE_CONFIG15_REG
0x41C
16
read-write
n
0x0
0x0
cp_bias_sh_open
Timing configuration for the CP bias S/H switch
8
16
read-write
vco_bias_sh_open_en
Timing configuration for the VCO bias S/H switch
0
8
read-write
RF_ENABLE_CONFIG16_REG
0x41E
16
read-write
n
0x0
0x0
gauss_bias_sh_open_en
Timing configuration for gauss bias S/H switch
0
8
read-write
iff_bias_sh_open_en
Timing configuration for iffmix bias S/H switch
8
16
read-write
RF_ENABLE_CONFIG17_REG
0x420
16
read-write
n
0x0
0x0
mix_bias_sh_open_en
Timing configuration for pa bias S/H switch
8
16
read-write
plldig_en
Timing configuration for the plldig
0
8
read-write
RF_ENABLE_CONFIG18_REG
0x422
16
read-write
n
0x0
0x0
dem_en
Timing configuration for demodulator
0
8
read-write
pllclosed_en
Timing configuration for pllclosed
8
16
read-write
RF_ENABLE_CONFIG19_REG
0x424
16
read-write
n
0x0
0x0
cal_en
Timing configuration for calibration slot
0
8
read-write
ldo_zero_en
Timing configuration for radio LDO auto zero enable
8
16
read-write
RF_ENABLE_CONFIG1_REG
0x400
16
read-write
n
0x0
0x0
lna_core_en
Timing configuration for enable of the lna core
0
8
read-write
lna_ldo_en
Timing configuration for enable of the lna ldo
8
16
read-write
RF_ENABLE_CONFIG20_REG
0x426
16
read-write
n
0x0
0x0
ldo_rfio_en
Timing configuration for RFIO LDO
0
8
read-write
tdc_en
Timing configuration for time to digital converter
8
16
read-write
RF_ENABLE_CONFIG21_REG
0x428
16
read-write
n
0x0
0x0
rfio_bias_en
Timing configuration for bias block for RFIO and RFPA
8
16
read-write
rfio_bias_sh_open
Timing configuration for S/H switch of bias block for RFIO/RFPA
0
8
read-write
RF_ENABLE_CONFIG22_REG
0x42A
16
read-write
n
0x0
0x0
adc_clk_en
Timing configuration for the enable of the ADC clock
0
8
read-write
ldo_radio_en
Timing configuration for LDO for the radio IO buffer
8
16
read-write
RF_ENABLE_CONFIG23_REG
0x42C
16
read-write
n
0x0
0x0
spare_en_3
Timing configuration for spare_en_3
0
8
read-write
tr_pwm_off_en
Timing configuration for tr_pwm_off_en
8
16
read-write
RF_ENABLE_CONFIG2_REG
0x402
16
read-write
n
0x0
0x0
lna_cgm_en
Timing configuration for enable of the lna cgm
8
16
read-write
mix_ldo_en
Timing configuration for enable of the mix ldo
0
8
read-write
RF_ENABLE_CONFIG3_REG
0x404
16
read-write
n
0x0
0x0
ifadc_ldo_en
Timing configuration for enable of the ifadc ldo
0
8
read-write
iff_ldo_en
Timing configuration for enable of the iff ldo
8
16
read-write
RF_ENABLE_CONFIG4_REG
0x406
16
read-write
n
0x0
0x0
md_ldo_en
Timing configuration for enable of the md ldo
0
8
read-write
vco_ldo_en
Timing configuration for enable of the vco ldo
8
16
read-write
RF_ENABLE_CONFIG5_REG
0x408
16
read-write
n
0x0
0x0
pa_ldo_en
Timing configuration for enable of the pa ldo
0
8
read-write
pfd_ldo_en
Timing configuration for enable of the pfd ldo
8
16
read-write
RF_ENABLE_CONFIG6_REG
0x40A
16
read-write
n
0x0
0x0
cp_switch_en
Timing configuration for the dynamic CP current switching
8
16
read-write
vco_bias_en
Timing configuration for the VCO bias
0
8
read-write
RF_ENABLE_CONFIG7_REG
0x40C
16
read-write
n
0x0
0x0
cp_bias_en
Timing configuration for enable of the CP bias
8
16
read-write
lna_ldo_zero
autozero control signal of the lna ldo
0
8
read-write
RF_ENABLE_CONFIG8_REG
0x40E
16
read-write
n
0x0
0x0
pa_en
Timing configuration for enable of the PA
0
8
read-write
pa_ramp_en
Timing configuration for enable of the PA ramp
8
16
read-write
RF_ENABLE_CONFIG9_REG
0x410
16
read-write
n
0x0
0x0
iff_en
Timing configuration for enable of the iff
0
8
read-write
mix_en
Timing configuration for enable of the mixer
8
16
read-write
RF_IFF_CTRL1_REG
0x820
16
read-write
n
0x0
0x0
IFF_DCOC_DAC_DIS
Disable the DC offset current DAC
8
9
read-write
IF_CAL_CAP_SEL
'0': use value as determined by IF calibration for IF filter '1': use the value written to IF_CAL_CAP for IF filter.
5
6
read-write
IF_CAL_CAP_WR
External value for IF calibration capacitance
0
5
read-write
IF_MUTE
'0': normal operation '1': Mute IFF by short circuit of VGA1 input. Note: set TGATE_MIXER_IF to '0' for isolation from the IRM
6
7
read-write
RO_TO_PINS
'0': normal operation '1': Enable reference oscillator.
7
8
read-write
RF_IFF_RESULT_REG
Must be Retained
0x300
16
read-write
n
0x0
0x0
IF_CAL_CAP_RD
IF calibration result capacitance.
0
5
read-only
RF_IRQ_CTRL_REG
0x204
16
read-write
n
0x0
0x0
EO_CAL_CLEAR
Writing any value to this bit clears eo_cal interrupt.
0
1
read-only
RF_LF_CTRL_REG
0xC60
16
read-write
n
0x0
0x0
LF_CAL_CAP_SEL
'0': Normal operation: use IF_CAL_CAP_RD (as determined by IF calibration) for the loop filter capacitance '1': use the value written to LF_CAL_CAP_WR
5
6
read-write
LF_CAL_CAP_WR
External value for loop filter calibration capacitance
0
5
read-write
LF_SHORT_R4
'0': R4 in place, '1': R4 shorted, C2 and C4 in parallel.
6
7
read-write
RF_LF_RES_CTRL_REG
LF resistor setting
0xC52
16
read-write
n
0x0
0x0
LF_RES_RX
Loopfilter resistor setting during PLL - Lock in RX mode same coding as for LF_RES_TX
8
12
read-write
LF_RES_SET_RX
Loopfilter resistor setting during PLL settling in RX mode same coding as for LF_RES_TX
0
4
read-write
LF_RES_SET_TX
Loopfilter resistor setting during PLL settling in TX mode same coding as for LF_RES_TX
4
8
read-write
LF_RES_TX
Loopfilter resistor setting during PLL - Lock in TX mode 1xxx: 72 k (fastest, setting 0) 01xx: 120 k (setting 1) 001x: 168 k (setting2) 000x: 240 k (slowest, setting 3)
12
16
read-write
RF_MGAIN_CTRL2_REG
0xC0A
16
read-write
n
0x0
0x0
MGAIN_TRANSMIT_LENGTH
Number of symbols for transmit0 and transmit1 length during mgain calibration.
0
7
read-write
RF_MGAIN_CTRL_REG
0xC08
16
read-write
n
0x0
0x0
GAUSS_GAIN_SEL
0: Normal operation 1: Use GAUSS_GAIN_WR for the modulation gain
8
9
read-write
KMOD_ALPHA
Kmod channel dependent trimming constant. 0: No trimming is activated >0: The modulation gain in the direct path is modified with a factor: 1-SGNx(KMOD_ALPHA+2)x(CN-CN_CAL_RD)/2048
13
16
read-write
MGAIN_AVER
Average over a number of comparator output values 0: 1 value 1: 3 values 2: 5 values 3: 7 values
11
13
read-write
MGAIN_CMP_INV
Invert the output of the modulation gain comparator before usage.
10
11
read-write
MGAIN_DBL_TRANSMIT
Length of a modulation gain calibration step 0: 4 symbol periods 1: 8 symbol periods
9
10
read-write
RF_MGC_CTRL_REG
0xC10
16
read-write
n
0x0
0x0
GAUSS_DAC_CTRL
Reserved bits for Gauss DAC settings
2
4
read-write
MGC_GAIN_SET
Set the desired gain for the mgc calibration amplifier. '0': gain= 15x '1': gain= 10x
0
1
read-write
MGC_POLE_SW
Switch in an aditional pole on the mgc amplifer to have extra filtering of the loopfilter voltage. '0': no pole (bandwidth limited by the opamp) '1': switch in pole to reduce amplifier bandwidth
1
2
read-write
RF_MIXER_CTRL1_REG
0x810
16
read-write
n
0x0
0x0
MIX_SPARE
Spare registers for mixer control
12
16
read-write
MIX_TRIM_GMBIAS
Trim the Mixer bias resistor for optimum transcunductance 0: Minimum transconductance 8: Nominal transconductance F: Maximal transconductance
0
4
read-write
MIX_TRIM_IBIAS
Trim the bias current of the TIA 0: Minimum bias current 8: Nominal bias current F: Maximal bias current
4
8
read-write
MIX_TRIM_VCM
Trim the common mode voltage at the input of the TIA 0: Minimum voltage 8: Nominal voltage F: Maximal voltage
8
12
read-write
RF_MIXER_CTRL2_REG
0x812
16
read-write
n
0x0
0x0
MIX_CAL_CAP_SEL
'0': Normal operation: use IF_CAL_CAP_RD (as determined by IF calibration) for the loop filter capacitance '1': use the value written to MIX_CAL_CAP_WR
5
6
read-write
MIX_CAL_CAP_WR
External value for calibration of mixer pole capacitance
0
5
read-write
RF_OVERRULE_REG
0x20
16
read-write
n
0x0
0x0
RX_DIS_WR
Disable rx_en
2
3
read-write
RX_EN_WR
Enable rx_en
3
4
read-write
TX_DIS_WR
Disable tx_en
0
1
read-write
TX_EN_WR
Enable tx_en
1
2
read-write
RF_PA_CTRL_REG
Removed obsolete values of bits 10:7, pa_pw back to 4
0xA00
16
read-write
n
0x0
0x0
LEVEL_LDO_RFPA
Control for PA supply voltage (output power)
11
15
read-write
PA_GAIN
Sets gain/DC Current setting of the differential to single ended converter '0': smallest current setting (60 uA) '1': current setting 1 (80 uA) '2': default (100 uA) '3': largest current setting (120 uA)
0
2
read-write
PA_PW
Pulse width setting to control HD2 '0': not active '1': 48.8 percent duty cycle '2': 49.4 percent duty cycle '3': 49.7 percent duty cycle '4': 50 percent duty cycle (default) '5': 50.3 percent duty cycle '6': 50.6 percent duty cycle '7': 51.2 percent duty cycle
2
5
read-write
PA_RAMPSPEED
Ramping speed setting of the driver stage: '0x0': slowest (1.25 uA) '0x1': 2x faster (2.5 uA) '0x2': default ramping speed '0x3': fastest
5
7
read-write
RF_PFD_CTRL_REG
0xC40
16
read-write
n
0x0
0x0
FIXED_CUR_EN
Enable manual override of PFD output '0': Normal operation '1': PFD ouput given by FIXED_CUR_SET
2
3
read-write
FIXED_CUR_SET
Set the PFD output in a fixed position such that the CP output current is constant'0': UP = 0, DN = 0 '1': UP = 0, DN = 1 '2': UP = 1, DN = 0 '3': UP = 1, DN = 1
0
2
read-write
PFD_POLARITY
'0': Normal operation (UP: implies RCLK leads NCLK) '1': Inverted operation (UP: implies NCLK leads RCLK)
3
4
read-write
RF_RADIG_SPARE_REG
0x870
16
read-write
n
0x0
0x0
RADIG_SPARE
Spare bits to be defined later
3
16
read-write
RF_REF_OSC_REG
0x202
16
read-write
n
0x0
0x0
CNT_CLK
number of clock pulses corresponding to the value of CNT_RO
6
15
read-write
CNT_RO
number of reference oscillator periods that need to be counted
0
6
read-write
RF_RSSI_RESULT_REG
0x902
16
read-write
n
0x0
0x0
RSSI_AVG_RD
RSSI value measured in averaging mode in continuous RX mode (used for LNA selectivity calibration)
6
16
read-only
RSSI_PH_RD
RSSI value measured in peak-hold mode during the preamble and Access Addres detection
0
6
read-only
RF_SCAN_FEEDBACK_REG
0x80
16
read-write
n
0x0
0x0
CP_CUR
Cp_cur value during scan.
4
8
read-only
LF_RES
Lf_res value during scan.
0
4
read-only
RF_SPARE1_REG
0x602
16
read-write
n
0x0
0x0
IFF_REAL_MODE
Choose the transfer function mode of the IFF 0: Normal operation (complex) 1: Test mode (real, approx. 16 dB less gain at 1 MHz than in complex mode)
0
1
read-write
RF_SPARE1
Spare bits for radio
1
16
read-write
RF_SYNTH_CTRL1_REG
0xC00
16
read-write
n
0x0
0x0
CHANNEL_ZERO
Channel 0 frequency in MHz
0
12
read-write
CS
Channel Spacing 0: 1MHz 1: 2MHz
13
14
read-write
PLL_HSI_POL
High Side Injection polarity 0: LO frequency is lower than the wanted RF frequency 1: LO frequency is higher than the wanted RF frequency
14
15
read-write
SGN
Sign bit for the channel step 0: positive 1: negative
12
13
read-write
RF_SYNTH_CTRL2_REG
0xC02
16
read-write
n
0x0
0x0
BT_SEL
0: BT = 0.5 1: BT = 0.6
12
13
read-write
DELAY
Additional delay in analog signal path in RCLK cycles
6
8
read-write
EO_PACKET_DIS
Disable the end of packet detection 0: End of packet detection enabled 1: End of pakcet detection disabled
11
12
read-write
GAUSS_86
Select the output resolution in the analog signal path 0: 8 bit resolution for the shaping signal 1: 6 bit resolution for the shaping signal
9
10
read-write
GAUSS_INV
Select polarity of the analog modulation path 0: Normal operation 1: Invert the signal in the analog signal path
8
9
read-write
MODINDEX
Modulation Index selection 0:h = 1/2 (Îf = 250 kHz) 1: h = 1/4 (Îf = 125 kHz) 2: h = 17/32 (Îf = 266 kHz) 3: h = 35/64 (Îf = 273 kHz)
4
6
read-write
SD_ORDER_RX
Order of the sigma-delta modulator in RX mode
0
2
read-write
SD_ORDER_TX
Order of the sigma-delta modulator in TX mode
2
4
read-write
TXDATA_INV
Select polarity of the modulation prior to the pulse shaping 0: Normal operation 1: Invert the modulation signal
10
11
read-write
RF_SYNTH_CTRL3_REG
0xC04
16
read-write
n
0x0
0x0
MODVAL_SEL
0: Normal operation 1: Use the externally provided value for the modulation
14
15
read-write
MODVAL_WR
Externally provided modulation value in 2s complement Îf = 16 MHz x MODVAL_WR/16348
0
14
read-write
RF_SYNTH_RESULT2_REG
Must be Retained
0x318
16
read-write
n
0x0
0x0
CN_CAL_RD
Result of the modulation gain calibration (Retained)
8
15
read-only
GAUSS_GAIN_RD
Modulation gain after trimming (Not Retained)
0
8
read-only
RF_SYNTH_RESULT3_REG
0x31A
16
read-write
n
0x0
0x0
MDSTATE_RD
Content of the calibration counter
0
16
read-only
RF_SYNTH_RESULT_REG
Must be Retained
0x316
16
read-write
n
0x0
0x0
GAUSS_GAIN_CAL_RD
Result of the modulation gain calibration (Retained)
0
8
read-only
VCO_FREQTRIM_RD
Result of the VCO calibration (Not Retained)
8
12
read-only
RF_TDC_CTRL_REG
TDC settings
0xC70
16
read-write
n
0x0
0x0
CAL_PH_1
Select calibration option 1 '0': normal operation (pfd measurement or cal mode 2) '1': measure the fast oscillator period (calibration phase 1) ------- Note: CAL_PH_2 must be 0 in this setting
8
9
read-write
CAL_PH_2
Select calibration option 2 '0': normal operation (pfd measurement mode or cal mode 1) '1': measure the slow - fast oscillator period (calibration phase 2) ------- Note CAL_PH_1 must be 0 in this setting
9
10
read-write
CTRL_FAST
Trim the fast oscillator '0': mimimum frequency 'F': maximum frequency
0
4
read-write
CTRL_SLOW
Trim the slow oscillator '0': Minimum frequency (default) 'F': Maximum frequency
4
8
read-write
REF_CTRL
Select how calibration is performed. Phase 1: '0': Count during 1 RCLK period (expect 60-70 as result) '1': Count during 2 RCLK period (expect 120-140 as result) '2': Count during 3 RCLK period (expect 180 -210 as result) '3': not allowed Phase 2, base the resolution measurement on: '0': 1 overlap of fast and slow oscillators (NF=NS+1) '1': 2 overlaps of fast and slow oscillators (NF=NS+2) '2': 1 overlap of fast and slow oscillators (NF=NS+1) '3': Not allowed
10
12
read-write
TDC_CONNECT
'0': Normal Operation (no measurement possible) '1': Connect the PFD inputs also to the TDC inputs
12
13
read-write
RF_VCOCAL_CTRL_REG
0xC06
16
read-write
n
0x0
0x0
VCOCAL_PERIOD
Length of a VCO calibration step 0: 1 us 1: 2 us 2: 3 us 3: 4 us
5
7
read-write
VCO_FREQTRIM_SEL
0: Normal operation 1: Use VCO_FREQTRIM_WR for the VCO calibration
4
5
read-write
VCO_FREQTRIM_WR
Externally provided VCO calibration value
0
4
read-write
RF_VCOVAR_CTRL_REG
0xC20
16
read-write
n
0x0
0x0
MOD_VAR_V0
Bias voltage of the VCO Modulation varactor (low Vmod) 0: low 1: mid 2: nominal 3: high
12
14
read-write
MOD_VAR_V1
Bias voltage of the VCO Modulation varactor (high Vmod) 0: low 1: mid 2: nominal 3: high
14
16
read-write
TUNE_VAR_V0
Bias voltage of the VCO Tuning varactor (low Vtune) Coding identical to TUNE_VAR_V3
0
3
read-write
TUNE_VAR_V1
Bias voltage of the VCO Tuning varactor (low-mid Vtune) Coding identical to TUNE_VAR_V3
3
6
read-write
TUNE_VAR_V2
Bias voltage of the VCO Tuning varactor (high-mid Vtune) Coding identical to TUNE_VAR_V3
6
9
read-write
TUNE_VAR_V3
Bias voltage of the VCO Tuning varactor (high Vtune) 001: low 010: nominal 100: high others: not allowed
9
12
read-write
RF_VCO_CALCAP_BIT14_REG
LUT entry for bit 14 of the VCO calibration capacitance
0xC22
16
read-write
n
0x0
0x0
VCO_CALCAP_BIT14
LUT entry for bit 14 of the VCO calibration capacitance
0
16
read-write
RF_VCO_CALCAP_BIT15_REG
LUT entry for bit 15 of the VCO calibration capacitance
0xC24
16
read-write
n
0x0
0x0
VCO_CALCAP_BIT15
LUT entry for bit 15 of the VCO calibration capacitance
0
16
read-write
SCB
Cortex M0 SCB registers
SCB_GROUP
0x0
0x0
0x29
registers
n
AIRCR
Application interrupt and reset control register
0xC
32
read-only
n
0x0
0x0
ENDIANESS
Data endianness bit
15
16
read-only
SYSRESETREQ
System reset request
2
3
read-only
VECTCLRACTIVE
Reserved for Debug use
1
2
read-only
VECTKEY
VECTKEY[15:0] bits (Register key)
16
32
read-only
VECTRESET
Reserved for Debug use
0
1
read-only
CCR
Configuration and control register
0x14
32
read-write
n
0x0
0x0
STKALIGN
Configures stack alignment on exception entry
9
10
read-write
UNALIGN_TRP
Enables unaligned access traps
3
4
read-write
CPUID
CPUID base register
0x0
32
read-write
n
0x0
0x0
CONSTANT
CONSTANT[3:0] bits (Reads as 0xF)
16
20
read-only
IMPLEMENTER
IMPLEMENTER[7:0] bits (Implementer code)
24
32
read-only
PARTNO
PARTNO[11:0] bits (Part number of the processor core)
4
16
read-only
REVISION
REVISION[3:0] bits (Revision number)
0
4
read-only
VARIANT
VARIANT[3:0] bits (Variant number)
20
24
read-only
ICSR
Interrupt control and state register
0x4
32
read-write
n
0x0
0x0
ISRPENDING
Interrupt pending flag, excluding NMI and Faults
22
23
read-write
NMIPENDSET
NMI set-pending bit
31
32
read-write
PENDSTCLR
SysTick exception clear-pending bit
25
26
read-write
PENDSTSET
SysTick exception set-pending bit
26
27
read-write
PENDSVCLR
PendSV clear-pending bit
27
28
read-write
PENDSVSET
PendSV set-pending bit
28
29
read-write
VECTACTIVE
VECTACTIVE[5:0] bits (Active vector)
0
6
read-write
VECTPENDING
VECTPENDING[5:0] bits (Pending vector)
12
18
read-write
SCR
System control register
0x10
32
read-write
n
0x0
0x0
SEVEONPEND
Send event on pending bit
4
5
read-write
SLEEPDEEP
Controls whether the processor uses sleep or deep sleep
2
3
read-write
SLEEPONEXIT
Configures sleep-on-exit when returning from Handler mode to Thread mode
1
2
read-write
SHPR2
System handler priority register 2
0x1C
32
read-write
n
0x0
0x0
PRI_11
PRI_11[7:0] bits (Priority of system handler 11, SVCall)
24
32
read-write
SHPR3
System handler priority register 3
0x20
32
read-write
n
0x0
0x0
PRI_14
PRI_14[7:0] bits (Priority of system handler 14, PendSV)
16
24
read-write
PRI_15
PRI_15[7:0] bits (Priority of system handler 15, SysTick exception)
24
32
read-write
spi443_nl00
spi443_nl00 registers
Peripheral_Registers
0x0
0x0
0xA
registers
n
SPI_CLEAR_INT_REG
SPI clear interrupt register
0x6
16
read-write
n
0x0
0x0
SPI_CLEAR_INT
Writing any value to this register will clear the SPI_CTRL_REG[SPI_INT_BIT] Reading returns 0.
0
16
write-only
SPI_CTRL_REG
SPI control register 0
0x0
16
read-write
n
0x0
0x0
SPI_CLK
Select SPI_CLK clock frequency in master mode:00 = (XTAL) / (CLK_PER_REG *8) 01 = (XTAL) / (CLK_PER_REG *4) 10 = (XTAL) / (CLK_PER_REG *2) 11 = (XTAL) / (CLK_PER_REG *14)
3
5
read-write
SPI_DI
Returns the actual value of pin SPI_DIN (delayed with two internal SPI clock cycles)
12
13
read-only
SPI_DO
Pin SPI_DO output level when SPI is idle or when SPI_FORCE_DO=1
5
6
read-write
SPI_EN_CTRL
0 = SPI_EN pin disabled in slave mode. Pin SPI_EN is don't care. 1 = SPI_EN pin enabled in slave mode.
15
16
read-write
SPI_FORCE_DO
0 = normal operation 1 = Force SPIDO output level to value of SPI_DO.
10
11
read-write
SPI_INT_BIT
0 = RX Register or FIFO is empty. 1 = SPI interrupt. Data has been transmitted and receivedMust be reset by SW by writing to SPI_CLEAR_INT_REG.
13
14
read-only
SPI_MINT
0 = Disable SPI_INT_BIT to the Interrupt Controller 1 = Enable SPI_INT_BIT to the Interrupt Controller
14
15
read-write
SPI_ON
0 = SPI Module switched off (power saving). Everything is reset except SPI_CTRL_REG0 and SPI_CTRL_REG1. When this bit is cleared the SPI will remain active in master mode until the shift register and holding register are both empty. 1 = SPI Module switched on. Should only be set after all control bits have their desired values. So two writes are needed!
0
1
read-write
SPI_PHA
Select SPI_CLK phase. See functional timing diagrams in SPI chapter
1
2
read-write
SPI_POL
Select SPI_CLK polarity. 0 = SPI_CLK is initially low. 1 = SPI_CLK is initially high.
2
3
read-write
SPI_RST
0 = normal operation 1 = Reset SPI. Same function as SPI_ON except that internal clock remain active.
9
10
read-write
SPI_SMN
Master/slave mode 0 = Master, 1 = Slave(SPI1 only)
6
7
read-write
SPI_TXH
0 = TX-FIFO is not full, data can be written. 1 = TX-FIFO is full, data can not be written.
11
12
read-only
SPI_WORD
00 = 8 bits mode, only SPI_RX_TX_REG0 used 01 = 16 bit mode, only SPI_RX_TX_REG0 used 10 = 32 bits mode, SPI_RX_TX_REG0 and SPI_RX_TX_REG1 used 11 = 9 bits mode. Only valid in master mode.
7
9
read-write
SPI_CTRL_REG1
SPI control register 1
0x8
16
read-write
n
0x0
0x0
SPI_9BIT_VAL
Determines the value of the first bit in 9 bits SPI mode.
4
5
read-write
SPI_BUSY
0 = The SPI is not busy with a transfer. This means that either no TX-data is available or that the transfers have been suspended due to a full RX-FIFO. The SPIx_CTRL_REG0[SPI_INT_BIT] can be used to distinguish between these situations. 1 = The SPI is busy with a transfer.
3
4
read-only
SPI_FIFO_MODE
0: TX-FIFO and RX-FIFO used (Bidirectional mode). 1: RX-FIFO used (Read Only Mode) TX-FIFO single depth, no flow control 2: TX-FIFO used (Write Only Mode), RX-FIFO single depth, no flow control 3: No FIFOs used (backwards compatible mode)
0
2
read-write
SPI_PRIORITY
0 = The SPI has low priority, the DMA request signals are reset after the corresponding acknowledge. 1 = The SPI has high priority, DMA request signals remain active until the FIFOS are filled/emptied, so the DMA holds the AHB bus.
2
3
read-write
SPI_RX_TX_REG0
SPI RX/TX register0
0x2
16
read-write
n
0x0
0x0
SPI_DATA0
Write: SPI_TX_REG0 output register 0 (TX-FIFO) Read: SPI_RX_REG0 input register 0 (RX-FIFO) In 8 or 9 bits mode bits 15 to 8 are not used, they contain old data.
0
16
write-only
SPI_RX_TX_REG1
SPI RX/TX register1
0x4
16
read-write
n
0x0
0x0
SPI_DATA1
Write: SPI_TX_REG1 output register 1 (MSB's of TX-FIFO) Read: SPI_RX_REG1 input register 1 (MSB's of RX-FIFO) In 8 or 9 or 16 bits mode bits this register is not used.
0
16
write-only
SysTick
Cortex M0 SysTick registers
SYSTICK
0x0
0x0
0x11
registers
n
CALIB
SysTick Calibration value register
0xC
32
read-only
n
0x0
0x0
NOREF
Indicates that a separate reference clock is provided
31
32
read-only
SKEW
Indicates whether the TENMS value is exact
30
31
read-only
TENMS
TENMS[23:0] bits (Calibration value)
0
24
read-only
CTRL
SysTick Control and Status register
0x0
32
read-write
n
0x0
0x0
CLKSOURCE
Clock source selection
2
3
read-write
COUNTFLAG
Timer counted to 0 since last time this was read
16
17
read-write
ENABLE
SysTick Counter enable
0
1
read-write
TICKINT
SysTick exception request enable
1
2
read-write
LOAD
SysTick Reload value register
0x4
32
read-write
n
0x0
0x0
RELOAD
RELOAD[23:0] bits (Reload value)
0
24
read-write
VAL
SysTick Current value register
0x8
32
read-write
n
0x0
0x0
CURRENT
CURRENT[23:0] bits (Current counter value)
0
24
read-write
tmr580_nl01
tmr580_nl01 registers
Peripheral_Registers
0x0
0x0
0x12
registers
n
PWM2_DUTY_CYCLE
Duty Cycle for PWM2
0x8
16
read-write
n
0x0
0x0
DUTY_CYCLE
duty cycle for PWM
0
14
read-write
PWM3_DUTY_CYCLE
Duty Cycle for PWM3
0xA
16
read-write
n
0x0
0x0
DUTY_CYCLE
duty cycle for PWM
0
14
read-write
PWM4_DUTY_CYCLE
Duty Cycle for PWM4
0xC
16
read-write
n
0x0
0x0
DUTY_CYCLE
duty cycle for PWM
0
14
read-write
TIMER0_CTRL_REG
Timer0 control register
0x0
16
read-write
n
0x0
0x0
PWM_MODE
0 = PWM signals are '1' during high time. 1 = PWM signals send out the (fast) clock divided by 2 during high time. So it will be in the range of 1 to 8 MHz.
3
4
read-write
TIM0_CLK_DIV
1 = Timer0 uses selected clock frequency as is. 0 = Timer0 uses selected clock frequency divided by 10. Note that this applies only to the ON-counter.
2
3
read-write
TIM0_CLK_SEL
1 = Timer0 uses 16, 8, 4 or 2 MHz (fast) clock frequency. 0 = Timer0 uses 32 kHz (slow) clock frequency.
1
2
read-write
TIM0_CTRL
0 = Timer0 is off and in reset state. 1 = Timer0 is running.
0
1
read-write
TIMER0_ON_REG
Timer0 on control register
0x2
16
read-write
n
0x0
0x0
TIM0_ON
Timer0 On reload value: If read the actual counter value ON_CNTer is returned
0
16
write-only
TIMER0_RELOAD_M_REG
16 bits reload value for Timer0
0x4
16
read-write
n
0x0
0x0
TIM0_M
Timer0 'high' reload valueIf read the actual counter value T0_CNTer is returned
0
16
write-only
TIMER0_RELOAD_N_REG
16 bits reload value for Timer0
0x6
16
read-write
n
0x0
0x0
TIM0_N
Timer0 'low' reload value: If read the actual counter value T0_CNTer is returned
0
16
write-only
TRIPLE_PWM_CTRL_REG
PWM 2 3 4 Control
0x10
16
read-write
n
0x0
0x0
HW_PAUSE_EN
'1' = HW can pause PWM 2,3,4
2
3
read-write
SW_PAUSE_EN
'1' = PWM 2 3 4 is paused
1
2
read-write
TRIPLE_PWM_ENABLE
'1' = PWM 2 3 4 is enabled
0
1
read-write
TRIPLE_PWM_FREQUENCY
Frequency for PWM 2,3 and 4
0xE
16
read-write
n
0x0
0x0
FREQ
Freq for PWM 2 3 4
0
14
read-write
UART1
UART1 registers
Peripheral_Registers
0x0
0x0
0xFE
registers
n
UART_CPR_REG
Component Parameter Register
0xF4
16
read-write
n
0x0
0x0
CPR
Component Parameter Register
0
16
read-only
UART_CTR_REG
Component Type Register
0xFC
16
read-write
n
0x0
0x0
CTR
Component Type Register
0
16
read-only
UART_HTX_REG
Halt TX
0xA4
16
read-write
n
0x0
0x0
UART_HALT_TX
This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation.
0
1
read-write
UART_IER_DLH_REG
Interrupt Enable Register
0x4
16
read-write
n
0x0
0x0
EDSSI_dlh3
Interrupt Enable Register: EDSSI, Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[3] of the 8 bit DLH register
3
4
read-write
ELSI_dhl2
Interrupt Enable Register: ELSI, Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[2] of the 8 bit DLH register.
2
3
read-write
ERBFI_dlh0
Interrupt Enable Register: ERBFI, Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFO's enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled Divisor Latch (High): Bit[0] of the 8 bit DLH register.
0
1
read-write
ETBEI_dlh1
Interrupt Enable Register: ETBEI, Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[1] of the 8 bit DLH register.
1
2
read-write
PTIME_dlh7
Interrupt Enable Register: PTIME, Programmable THRE Interrupt Mode Enable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[7] of the 8 bit DLH register.
7
8
read-write
UART_IIR_FCR_REG
Interrupt Identification Register/FIFO Control Register
0x8
16
read-write
n
0x0
0x0
IIR_FCR
Interrupt Identification Register, reading this register FIFO Control Register, writing to this register. Interrupt Identification Register: Bits[7:6], FIFO's Enabled (or FIFOSE): This is used to indicate whether the FIFO's are enabled or disabled. 00 = disabled. 11 = enabled. Bits[3:0], Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0000 = modem status. 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. Bits[7:6], RCVR Trigger (or RT):. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted. It also determines when the dma_rx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO 1/4 full 10 = FIFO 1/2 full 11 = FIFO 2 less than full Bits[5:4], TX Empty Trigger (or TET): This is used to select the empty threshold level at which the THRE Interrupts will be generated when the mode is active. It also determines when the dma_tx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO 1/4 full 11 = FIFO 1/2 full Bit[3], DMA Mode (or DMAM): This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 Bit[2], XMIT FIFO Reset (or XFIFOR): This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. Bit[1], RCVR FIFO Reset (or RFIFOR): This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. Bit[0], FIFO Enable (or FIFOE): This enables/disables the transmit (XMIT) and receive (RCVR) FIFO's. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFO's will be reset.
0
16
read-write
UART_LCR_REG
Line Control Register
0xC
16
read-write
n
0x0
0x0
UART_BC
Break Control Bit. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low.
6
7
read-write
UART_DLAB
Divisor Latch Access Bit. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers.
7
8
read-write
UART_DLS
Data Length Select. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits
0
2
read-write
UART_EPS
Even Parity Select. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked.
4
5
read-write
UART_PEN
Parity Enable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled
3
4
read-write
UART_STOP
Number of stop bits. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit
2
3
read-write
UART_LPDLH_REG
Low Power Divisor Latch High
0x24
16
read-write
n
0x0
0x0
UART_LPDLH
This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may be accessed only when the DLAB bit (LCR[7]) is set. The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest UART Ctrl clock should be allowed to pass before transmitting or receiving data.
0
8
read-write
UART_LPDLL_REG
Low Power Divisor Latch Low
0x20
16
read-write
n
0x0
0x0
UART_LPDLL
This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may be accessed only when the DLAB bit (LCR[7]) is set. The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest UART Ctrl clock should be allowed to pass before transmitting or receiving data.
0
8
read-write
UART_LSR_REG
Line Status Register
0x14
16
read-write
n
0x0
0x0
UART_B1
Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read.
4
5
read-only
UART_DR
Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode.
0
1
read-only
UART_FE
Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit.
3
4
read-only
UART_OE
Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit.
1
2
read-only
UART_PE
Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit.
2
3
read-only
UART_RFE
Receiver FIFO Error bit. This bit is only relevant when FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO.
7
8
read-only
UART_TEMT
Transmitter Empty bit. If FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty.
6
7
read-only
UART_THRE
Transmit Holding Register Empty bit. If THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting.
5
6
read-only
UART_MCR_REG
Modem Control Register
0x10
16
read-write
n
0x0
0x0
UART_AFCE
Auto Flow Control Enable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, hardware Auto Flow Control is enabled via CTS and RTS. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled
5
6
read-write
UART_LB
LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line.
4
5
read-write
UART_OUT1
OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input.
2
3
read-write
UART_OUT2
OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input.
3
4
read-write
UART_RTS
Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto Flow Control is disabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high. When Auto Flow Control is enabled (MCR[5] set to one) and FIFOs are enabled (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive (high) while the value of this location is internally looped back to an input.
1
2
read-write
UART_SIRE
SIR Mode Enable. This is used to enable/disable the IrDA SIR Mode features as described in 'IrDA 1.0 SIR Protocol' on page 53. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled
6
7
read-write
UART_MSR_REG
Modem Status Register
0x18
16
read-write
n
0x0
0x0
UART_CTS
Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the UART Ctrl. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS).
4
5
read-only
UART_DCD
Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 = dcd_n input is de-asserted (logic 1) 1 = dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2).
7
8
read-only
UART_DCTS
Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on cts_n since last read of MSR 1 = change on cts_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted.
0
1
read-only
UART_DDCD
Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted.
3
4
read-only
UART_R1
Ring Indicator. This is used to indicate the current state of the modem control line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 = ri_n input is de-asserted (logic 1) 1 = ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1).
6
7
read-only
UART_TERI
Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low.
2
3
read-only
UART_RBR_THR_DLL_REG
Receive Buffer Register
0x0
16
read-write
n
0x0
0x0
RBR_THR_DLL
Receive Buffer Register: This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Transmit Holding Register: This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Divisor Latch (Low): This register makes up the lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set. The output baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor) Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data.
0
8
read-write
UART_RFL_REG
Receive FIFO Level.
0x84
16
read-write
n
0x0
0x0
UART_RECEIVE_FIFO_LEVEL
Receive FIFO Level. This is indicates the number of data entries in the receive FIFO.
0
16
read-only
UART_SBCR_REG
Shadow Break Control Register
0x90
16
read-write
n
0x0
0x0
UART_SHADOW_BREAK_CONTROL
Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver.
0
1
read-write
UART_SCR_REG
Scratchpad Register
0x1C
16
read-write
n
0x0
0x0
UART_SCRATCH_PAD
This register is for programmers to use as a temporary storage space. It has no defined purpose in the UART Ctrl.
0
8
read-write
UART_SDMAM_REG
Shadow DMA Mode
0x94
16
read-write
n
0x0
0x0
UART_SHADOW_DMA_MODE
Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1
0
1
read-write
UART_SFE_REG
Shadow FIFO Enable
0x98
16
read-write
n
0x0
0x0
UART_SHADOW_FIFO_ENABLE
Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset.
0
1
read-write
UART_SRBR_STHR0_REG
Shadow Receive/Transmit Buffer Register
0x30
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
UART_SRBR_STHR10_REG
Shadow Receive/Transmit Buffer Register
0x58
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
UART_SRBR_STHR11_REG
Shadow Receive/Transmit Buffer Register
0x5C
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
UART_SRBR_STHR12_REG
Shadow Receive/Transmit Buffer Register
0x60
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
UART_SRBR_STHR13_REG
Shadow Receive/Transmit Buffer Register
0x64
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
UART_SRBR_STHR14_REG
Shadow Receive/Transmit Buffer Register
0x68
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
UART_SRBR_STHR15_REG
Shadow Receive/Transmit Buffer Register
0x6C
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
UART_SRBR_STHR1_REG
Shadow Receive/Transmit Buffer Register
0x34
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
UART_SRBR_STHR2_REG
Shadow Receive/Transmit Buffer Register
0x38
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
UART_SRBR_STHR3_REG
Shadow Receive/Transmit Buffer Register
0x3C
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
UART_SRBR_STHR4_REG
Shadow Receive/Transmit Buffer Register
0x40
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
UART_SRBR_STHR5_REG
Shadow Receive/Transmit Buffer Register
0x44
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
UART_SRBR_STHR6_REG
Shadow Receive/Transmit Buffer Register
0x48
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
UART_SRBR_STHR7_REG
Shadow Receive/Transmit Buffer Register
0x4C
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
UART_SRBR_STHR8_REG
Shadow Receive/Transmit Buffer Register
0x50
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
UART_SRBR_STHR9_REG
Shadow Receive/Transmit Buffer Register
0x54
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
UART_SRR_REG
Software Reset Register.
0x88
16
read-write
n
0x0
0x0
UART_RFR
RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit.
1
2
write-only
UART_UR
UART Reset. This asynchronously resets the UART Ctrl and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset.
0
1
write-only
UART_XFR
XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit.
2
3
write-only
UART_SRTS_REG
Shadow Request to Send
0x8C
16
read-write
n
0x0
0x0
UART_SHADOW_REQUEST_TO_SEND
Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to perform a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART Ctrl is ready to exchange data. When Auto Flow Control is disabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. When Auto Flow Control is enabled (MCR[5] = 1) and FIFOs are enabled (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input.
0
1
read-write
UART_SRT_REG
Shadow RCVR Trigger
0x9C
16
read-write
n
0x0
0x0
UART_SHADOW_RCVR_TRIGGER
Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full
0
2
read-write
UART_STET_REG
Shadow TX Empty Trigger
0xA0
16
read-write
n
0x0
0x0
UART_SHADOW_TX_EMPTY_TRIGGER
Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full
0
2
read-write
UART_TFL_REG
Transmit FIFO Level
0x80
16
read-write
n
0x0
0x0
UART_TRANSMIT_FIFO_LEVEL
Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO.
0
16
read-only
UART_UCV_REG
Component Version
0xF8
16
read-write
n
0x0
0x0
UCV
Component Version
0
16
read-only
UART_USR_REG
UART Status register.
0x7C
16
read-write
n
0x0
0x0
UART_RFF
Receive FIFO Full. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full.
4
5
read-only
UART_RFNE
Receive FIFO Not Empty. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty.
3
4
read-only
UART_TFE
Transmit FIFO Empty. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty.
2
3
read-only
UART_TFNF
Transmit FIFO Not Full. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full.
1
2
read-only
UART2
UART2 registers
Peripheral_Registers
0x0
0x0
0xFE
registers
n
CPR_REG
Component Parameter Register
0xF4
16
read-write
n
0x0
0x0
CPR
Component Parameter Register
0
16
read-only
CTR_REG
Component Type Register
0xFC
16
read-write
n
0x0
0x0
CTR
Component Type Register
0
16
read-only
HTX_REG
Halt TX
0xA4
16
read-write
n
0x0
0x0
UART_HALT_TX
This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation.
0
1
read-write
IER_DLH_REG
Interrupt Enable Register
0x4
16
read-write
n
0x0
0x0
EDSSI_dlh3
Interrupt Enable Register: EDSSI, Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[3] of the 8 bit DLH register
3
4
read-write
ELSI_dhl2
Interrupt Enable Register: ELSI, Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[2] of the 8 bit DLH register.
2
3
read-write
ERBFI_dlh0
Interrupt Enable Register: ERBFI, Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFO's enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled Divisor Latch (High): Bit[0] of the 8 bit DLH register.
0
1
read-write
ETBEI_dlh1
Interrupt Enable Register: ETBEI, Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[1] of the 8 bit DLH register.
1
2
read-write
PTIME_dlh7
Interrupt Enable Register: PTIME, Programmable THRE Interrupt Mode Enable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[7] of the 8 bit DLH register.
7
8
read-write
IIR_FCR_REG
Interrupt Identification Register/FIFO Control Register
0x8
16
read-write
n
0x0
0x0
IIR_FCR
Interrupt Identification Register, reading this register FIFO Control Register, writing to this register. Interrupt Identification Register: Bits[7:6], FIFO's Enabled (or FIFOSE): This is used to indicate whether the FIFO's are enabled or disabled. 00 = disabled. 11 = enabled. Bits[3:0], Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0000 = modem status. 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. Bits[7:6], RCVR Trigger (or RT):. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted. It also determines when the dma_rx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO 1/4 full 10 = FIFO 1/2 full 11 = FIFO 2 less than full Bits[5:4], TX Empty Trigger (or TET): This is used to select the empty threshold level at which the THRE Interrupts will be generated when the mode is active. It also determines when the dma_tx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO 1/4 full 11 = FIFO 1/2 full Bit[3], DMA Mode (or DMAM): This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 Bit[2], XMIT FIFO Reset (or XFIFOR): This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. Bit[1], RCVR FIFO Reset (or RFIFOR): This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. Bit[0], FIFO Enable (or FIFOE): This enables/disables the transmit (XMIT) and receive (RCVR) FIFO's. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFO's will be reset.
0
16
read-write
LCR_REG
Line Control Register
0xC
16
read-write
n
0x0
0x0
UART_BC
Break Control Bit. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low.
6
7
read-write
UART_DLAB
Divisor Latch Access Bit. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers.
7
8
read-write
UART_DLS
Data Length Select. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits
0
2
read-write
UART_EPS
Even Parity Select. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked.
4
5
read-write
UART_PEN
Parity Enable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled
3
4
read-write
UART_STOP
Number of stop bits. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit
2
3
read-write
LPDLH_REG
Low Power Divisor Latch High
0x24
16
read-write
n
0x0
0x0
UART_LPDLH
This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may be accessed only when the DLAB bit (LCR[7]) is set. The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest UART Ctrl clock should be allowed to pass before transmitting or receiving data.
0
8
read-write
LPDLL_REG
Low Power Divisor Latch Low
0x20
16
read-write
n
0x0
0x0
UART_LPDLL
This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may be accessed only when the DLAB bit (LCR[7]) is set. The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest UART Ctrl clock should be allowed to pass before transmitting or receiving data.
0
8
read-write
LSR_REG
Line Status Register
0x14
16
read-write
n
0x0
0x0
UART_B1
Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read.
4
5
read-only
UART_DR
Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode.
0
1
read-only
UART_FE
Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit.
3
4
read-only
UART_OE
Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit.
1
2
read-only
UART_PE
Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit.
2
3
read-only
UART_RFE
Receiver FIFO Error bit. This bit is only relevant when FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO.
7
8
read-only
UART_TEMT
Transmitter Empty bit. If FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty.
6
7
read-only
UART_THRE
Transmit Holding Register Empty bit. If THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting.
5
6
read-only
MCR_REG
Modem Control Register
0x10
16
read-write
n
0x0
0x0
UART_AFCE
Auto Flow Control Enable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, hardware Auto Flow Control is enabled via CTS and RTS. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled
5
6
read-write
UART_LB
LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line.
4
5
read-write
UART_OUT1
OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input.
2
3
read-write
UART_OUT2
OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input.
3
4
read-write
UART_RTS
Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto Flow Control is disabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high. When Auto Flow Control is enabled (MCR[5] set to one) and FIFOs are enabled (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive (high) while the value of this location is internally looped back to an input.
1
2
read-write
UART_SIRE
SIR Mode Enable. This is used to enable or disable the IrDA SIR Mode features as described in 'IrDA 1.0 SIR Protocol' on page 53.
0 = IrDA SIR Mode disabled
1 = IrDA SIR Mode enabled .
6
7
read-write
MSR_REG
Modem Status Register
0x18
16
read-write
n
0x0
0x0
UART_CTS
Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the UART Ctrl. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS).
4
5
read-only
UART_DCD
Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 = dcd_n input is de-asserted (logic 1) 1 = dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2).
7
8
read-only
UART_DCTS
Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on cts_n since last read of MSR 1 = change on cts_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted.
0
1
read-only
UART_DDCD
Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted.
3
4
read-only
UART_R1
Ring Indicator. This is used to indicate the current state of the modem control line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 = ri_n input is de-asserted (logic 1) 1 = ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1).
6
7
read-only
UART_TERI
Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low.
2
3
read-only
RBR_THR_DLL_REG
Receive Buffer Register
0x0
16
read-write
n
0x0
0x0
RBR_THR_DLL
Receive Buffer Register: This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Transmit Holding Register: This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Divisor Latch (Low): This register makes up the lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set. The output baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor) Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data.
0
8
read-write
RFL_REG
Receive FIFO Level.
0x84
16
read-write
n
0x0
0x0
UART_RECEIVE_FIFO_LEVEL
Receive FIFO Level. This is indicates the number of data entries in the receive FIFO.
0
16
read-only
SBCR_REG
Shadow Break Control Register
0x90
16
read-write
n
0x0
0x0
UART_SHADOW_BREAK_CONTROL
Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver.
0
1
read-write
SCR_REG
Scratchpad Register
0x1C
16
read-write
n
0x0
0x0
UART_SCRATCH_PAD
This register is for programmers to use as a temporary storage space. It has no defined purpose in the UART Ctrl.
0
8
read-write
SDMAM_REG
Shadow DMA Mode
0x94
16
read-write
n
0x0
0x0
UART_SHADOW_DMA_MODE
Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1
0
1
read-write
SFE_REG
Shadow FIFO Enable
0x98
16
read-write
n
0x0
0x0
UART_SHADOW_FIFO_ENABLE
Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset.
0
1
read-write
SRBR_STHR0_REG
Shadow Receive/Transmit Buffer Register
0x30
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
SRBR_STHR10_REG
Shadow Receive/Transmit Buffer Register
0x58
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
SRBR_STHR11_REG
Shadow Receive/Transmit Buffer Register
0x5C
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
SRBR_STHR12_REG
Shadow Receive/Transmit Buffer Register
0x60
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
SRBR_STHR13_REG
Shadow Receive/Transmit Buffer Register
0x64
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
SRBR_STHR14_REG
Shadow Receive/Transmit Buffer Register
0x68
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
SRBR_STHR15_REG
Shadow Receive/Transmit Buffer Register
0x6C
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
SRBR_STHR1_REG
Shadow Receive/Transmit Buffer Register
0x34
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
SRBR_STHR2_REG
Shadow Receive/Transmit Buffer Register
0x38
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
SRBR_STHR3_REG
Shadow Receive/Transmit Buffer Register
0x3C
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
SRBR_STHR4_REG
Shadow Receive/Transmit Buffer Register
0x40
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
SRBR_STHR5_REG
Shadow Receive/Transmit Buffer Register
0x44
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
SRBR_STHR6_REG
Shadow Receive/Transmit Buffer Register
0x48
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
SRBR_STHR7_REG
Shadow Receive/Transmit Buffer Register
0x4C
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
SRBR_STHR8_REG
Shadow Receive/Transmit Buffer Register
0x50
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
SRBR_STHR9_REG
Shadow Receive/Transmit Buffer Register
0x54
16
read-write
n
0x0
0x0
SRBR_STHRx
Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.
0
8
read-write
SRR_REG
Software Reset Register.
0x88
16
read-write
n
0x0
0x0
UART_RFR
RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit.
1
2
write-only
UART_UR
UART Reset. This asynchronously resets the UART Ctrl and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset.
0
1
write-only
UART_XFR
XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit.
2
3
write-only
SRTS_REG
Shadow Request to Send
0x8C
16
read-write
n
0x0
0x0
UART_SHADOW_REQUEST_TO_SEND
Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to perform a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART Ctrl is ready to exchange data. When Auto Flow Control is disabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. When Auto Flow Control is enabled (MCR[5] = 1) and FIFOs are enabled (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input.
0
1
read-write
SRT_REG
Shadow RCVR Trigger
0x9C
16
read-write
n
0x0
0x0
UART_SHADOW_RCVR_TRIGGER
Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full
0
2
read-write
STET_REG
Shadow TX Empty Trigger
0xA0
16
read-write
n
0x0
0x0
UART_SHADOW_TX_EMPTY_TRIGGER
Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full
0
2
read-write
TFL_REG
Transmit FIFO Level
0x80
16
read-write
n
0x0
0x0
UART_TRANSMIT_FIFO_LEVEL
Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO.
0
16
read-only
UCV_REG
Component Version
0xF8
16
read-write
n
0x0
0x0
UCV
Component Version
0
16
read-only
USR_REG
UART Status register.
0x7C
16
read-write
n
0x0
0x0
UART_RFF
Receive FIFO Full. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full.
4
5
read-only
UART_RFNE
Receive FIFO Not Empty. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty.
3
4
read-only
UART_TFE
Transmit FIFO Empty. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty.
2
3
read-only
UART_TFNF
Transmit FIFO Not Full. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full.
1
2
read-only
wkup580_nl01
wkup580_nl01 registers
Peripheral_Registers
0x0
0x0
0x1A
registers
n
BLE_WAKEUP_LP
Wake-up from Low Power (Extended Sleep) interrupt from BLE
0
BLE_GEN
BLE Interrupt from various BLE sources.
1
UART
UART interrupt
2
UART2
UART2 interrupt
3
I2C
I2C interrupt
4
SPI
SPI interrupt
5
ADC
Analog-Digital Converter interrupt.
6
KEYBRD
Keyboard interrupt.
7
BLE_RF_DIAG
Baseband or Radio Diagnostics Interrupt
8
RF_CAL
RF Calibration Interrupt
9
GPIO0
GPIO0 interrupt through debounce
10
GPIO1
GPIO1 interrupt through debounce
11
GPIO2
GPIO2 interrupt through debounce
12
GPIO3
GPIO3 interrupt through debounce
13
GPIO4
GPIO4 interrupt through debounce
14
SWTIM
Software Timer interrupt
15
WKUP_QUADEC
Combines the Wake up Capture Timer interrupt, the GPIO interrupt and the QuadDecoder interrupt
16
PCM
PCM interrupt
17
SRC_IN
Sample rate converter input interrupt
18
SRC_OUT
Sample rate converter output interrupt
19
DMA
DMA interrupt
20
WKUP_COMPARE_REG
Number of events before wakeup interrupt
0x2
16
read-write
n
0x0
0x0
COMPARE
The number of events that have to be counted before the wakeup interrupt will be given
0
8
read-write
WKUP_COUNTER_REG
Actual number of events of the wakeup counter
0x6
16
read-write
n
0x0
0x0
EVENT_VALUE
This value represents the number of events that have been counted so far. It will be reset by resetting the interrupt.
0
8
read-only
WKUP_CTRL_REG
Control register for the wakeup counter
0x0
16
read-write
n
0x0
0x0
WKUP_DEB_VALUE
Keyboard debounce time (N*1 ms with N = 1 to 63). 0x0: no debouncing 0x1 to 0x3F: 1 ms to 63 ms debounce time
0
6
read-write
ENUM
WKUP_ENABLE_IRQ
0: no interrupt will be enabled 1: if the event counter reaches the value set by WKUP_COMPARE_REG an IRQ will be generated
7
8
read-write
ENUM
WKUP_SFT_KEYHIT
0: no effect 1: emulate key hit. The event counter will increment by 1 (after debouncing if enabled). First make this bit 0 before any new key hit can be sensed.
6
7
read-write
WKUP_POL_P0_REG
Select the sensitivity polarity for each P0 input
0x12
16
read-write
n
0x0
0x0
WKUP_POL_P0
0: enabled input P0x will increment the event counter if that input goes high 1: enabled input P0x will increment the event counter if that input goes low
0
8
read-write
WKUP_POL_P1_REG
Select the sensitivity polarity for each P1 input
0x14
16
read-write
n
0x0
0x0
WKUP_POL_P1
0: enabled input P1x will increment the event counter if that input goes high 1: enabled input P1x will increment the event counter if that input goes low
0
6
read-write
WKUP_POL_P2_REG
Select the sensitivity polarity for each P2 input
0x16
16
read-write
n
0x0
0x0
WKUP_POL_P2
0: enabled input P2x will increment the event counter if that input goes high 1: enabled input P2x will increment the event counter if that input goes low
0
10
read-write
WKUP_POL_P3_REG
Select the sensitivity polarity for each P3 input
0x18
16
read-write
n
0x0
0x0
WKUP_POL_P3
0: enabled input P3x will increment the event counter if that input goes high 1: enabled input P3x will increment the event counter if that input goes low
0
8
read-write
WKUP_RESET_CNTR_REG
Reset the event counter
0x8
16
read-write
n
0x0
0x0
WKUP_CNTR_RST
writing any value to this register will reset the event counter
0
16
write-only
WKUP_RESET_IRQ_REG
Reset wakeup interrupt
0x4
16
read-write
n
0x0
0x0
WKUP_IRQ_RST
writing any value to this register will reset the interrupt. reading always returns 0.
0
16
write-only
WKUP_SELECT_P0_REG
Select which inputs from P0 port can trigger wkup counter
0xA
16
read-write
n
0x0
0x0
WKUP_SELECT_P0
0: input P0x is not enabled for wakeup event counter 1: input P0x is enabled for wakeup event counter
0
8
read-write
WKUP_SELECT_P1_REG
Select which inputs from P1 port can trigger wkup counter
0xC
16
read-write
n
0x0
0x0
WKUP_SELECT_P1
0: input P1x is not enabled for wakeup event counter 1: input P1x is enabled for wakeup event counter
0
6
read-write
WKUP_SELECT_P2_REG
Select which inputs from P2 port can trigger wkup counter
0xE
16
read-write
n
0x0
0x0
WKUP_SELECT_P2
0: input P2x is not enabled for wakeup event counter 1: input P2x is enabled for wakeup event counter
0
10
read-write
WKUP_SELECT_P3_REG
Select which inputs from P3 port can trigger wkup counter
0x10
16
read-write
n
0x0
0x0
WKUP_SELECT_P3
0: input P3x is not enabled for wakeup event counter 1: input P3x is enabled for wakeup event counter
0
8
read-write