Dialog DA14681 2024.05.05 DA14681 CM0 r1p0 little true 3 false 8 32 AES_HASH AES_HASH registers Peripheral_Registers 0x0 0x0 0x104 registers n CRYPTO_CLRIRQ_REG Crypto Clear interrupt request 0x18 32 read-write n 0x0 0x0 CRYPTO_CLRIRQ Write 1 to clear a pending interrupt request. 0 1 write-only CRYPTO_CTRL_REG Crypto Control register 0x0 32 read-write n 0x0 0x0 CRYPTO_AES_KEXP It forces (active high) the execution of the key expansion process with the starting of the AES encryption/decryption process. The bit will be cleared automatically by the hardware, after the completion of the AES key expansion process. 17 18 read-write CRYPTO_AES_KEY_SZ The size of AES Key 00 - 128 bits AES Key 01 - 192 bits AES Key 10 - 256 bits AES Key 11 - 256 bits AES Key 5 7 read-write CRYPTO_ALG Algorithm selection. When CRYPTO_HASH_SEL = 0 the only available choice is the AES algorithm. 00 - AES 01 - Reserved 10 - Reserved 11 - Reserved When CRYPTO_HASH_SEL = 1, this field selects the desired hash algorithms, with the help of the CRYPTO_ALG_MD field. If CRYPTO_ALG_MD = 00 00 - MD5 01 - SHA-1 10 - SHA-256/224 11 - SHA-256 If CRYPTO_ALG_MD = 01 00 - SHA-384 01 - SHA-512 10 - SHA-512/224 11 - SHA-512/256 0 2 read-write CRYPTO_ALG_MD It defines the mode of operation of the AES algorithm when the controller is configured for an encryption/decryption processing (CRYPTO_HASH_SEL = 0). 00 - ECB 01 - ECB 10 - CTR 11 - CBC When the controller is configured to applies a HASH function, this field selects the desired HASH algorithm with the help of the CRYPTO_ALG. 00 - HASH algorithms that are based on 32 bits operations 01 - HASH algorithms that are based on 64 bits operations 10 - Reserved 11 - Reserved See also the CRYPTO_ALG field. 2 4 read-write CRYPTO_ENCDEC Encryption/Decryption 0 - Decryption 1 - Encryption 7 8 read-write CRYPTO_HASH_OUT_LEN The number of bytes minus one of the hash result which will be saved at the memory by the DMA. In relation with the selected hash algorithm the accepted values are: MD5: 0..15 -> 1-16 bytes SHA-1: 0..19 -> 1-20 bytes SHA-256: 0..31 -> 1 - 32 bytes SHA-256/224: 0..27 -> 1- 28 bytes SHA-384: 0..47 -> 1 - 48 bytes SHA-512: 0..63 -> 1 - 64 bytes SHA-512/224: 0..27 -> 1- 28 bytes SHA-512/256: 0..31 -> 1 - 32 bytes 10 16 read-write CRYPTO_HASH_SEL Selects the type of the algorithm 0 - The encryption algorithm (AES) 1 - A hash algorithm. The exact algorithm is defined by the fileds CRYPTO_ALG and CRYPTO_ALG_MD. 9 10 read-write CRYPTO_IRQ_EN Interrupt Request Enable 0 - The interrupt generation ability is disabled. 1 - The interrupt generation ability is enabled. Generates an interrupt request at the end of operation. 8 9 read-write CRYPTO_MORE_IN 0 - Define that this is the last input block. When the current input is consumed by the crypto engine and the output data is written to the memory, the calculation ends (CRYPTO_INACTIVE goes to one). 1 - The current input data block is not the last. More input data will follow. When the current input is consumed, the engine stops and waits for more data (CRYPTO_WAIT_FOR_IN goes to one). 16 17 read-write CRYPTO_OUT_MD Output Mode. This field makes sense only when the AES algorithm is selected (CRYPTO_HASH_SEL =0) 0 - Write back to memory all the resulting data 1 - Write back to memory only the final block of the resulting data 4 5 read-write CRYPTO_DEST_ADDR_REG Crypto DMA destination memory 0x10 32 read-write n 0x0 0x0 CRYPTO_DEST_ADDR Destination address at where the result of the processing is stored. The value of this register is updated as the calculation proceeds and the output data are written to the memory. 0 32 read-write CRYPTO_FETCH_ADDR_REG Crypto DMA fetch register 0x8 32 read-write n 0x0 0x0 CRYPTO_FETCH_ADDR The memory address from where will be retrieved the data that will be processed. The value of this register is updated as the calculation proceeds and the output data are written to the memory. 0 32 read-write CRYPTO_KEYS_START Crypto First position of the AES keys storage memory 0x100 32 read-write n 0x0 0x0 CRYPTO_KEY_X CRYPTO_KEY_(0-63) This is the AES keys storage memory. This memory is accessible via AHB slave interface, only when the CRYPTO is inactive (CRYPTO_INACTIVE = 1). 0 32 write-only CRYPTO_LEN_REG Crypto Length of the input block in bytes 0xC 32 read-write n 0x0 0x0 CRYPTO_LEN It contains the number of bytes of input data. If this number is not a multiple of a block size, the data is automatically extended with zeros. The value of this register is updated as the calculation proceeds and the output data are written to the memory. 0 24 read-write CRYPTO_MREG0_REG Crypto Mode depended register 0 0x1C 32 read-write n 0x0 0x0 CRYPTO_MREG0 It contains information that are depended by the mode of operation, when is used the AES algorithm: CBC - IV[31:0] CTR - CTRBLK[31:0]. It is the initial value of the 32 bits counter. At any other mode, the contents of this register has no meaning. 0 32 read-write CRYPTO_MREG1_REG Crypto Mode depended register 1 0x20 32 read-write n 0x0 0x0 CRYPTO_MREG1 It contains information that are depended by the mode of operation, when is used the AES algorithm: CBC - IV[63:32] CTR - CTRBLK[63:32] At any other mode, the contents of this register has no meaning. 0 32 read-write CRYPTO_MREG2_REG Crypto Mode depended register 2 0x24 32 read-write n 0x0 0x0 CRYPTO_MREG2 It contains information that are depended by the mode of operation, when is used the AES algorithm: CBC - IV[95:64] CTR - CTRBLK[95:64] At any other mode, the contents of this register has no meaning. 0 32 read-write CRYPTO_MREG3_REG Crypto Mode depended register 3 0x28 32 read-write n 0x0 0x0 CRYPTO_MREG3 It contains information that are depended by the mode of operation, when is used the AES algorithm: CBC - IV[127:96] CTR - CTRBLK[127:96] At any other mode, the contents of this register has no meaning. 0 32 read-write CRYPTO_START_REG Crypto Start calculation 0x4 32 read-write n 0x0 0x0 CRYPTO_START Write 1 to initiate the processing of the input data. This register is auto-cleared. 0 1 write-only CRYPTO_STATUS_REG Crypto Status register 0x14 32 read-write n 0x0 0x0 CRYPTO_INACTIVE 0 - The CRYPTO is active. The processing is in progress. 1 - The CRYPTO is inactive. The processing has finished. 0 1 read-only CRYPTO_IRQ_ST The status of the interrupt request line of the CRYPTO block. 0 - There is no active interrupt request. 1 - An interrupt request is pending. 2 3 read-only CRYPTO_WAIT_FOR_IN Indicates the situation where the engine waits for more input data. This is applicable when the CRYPTO_MORE_IN= 1, so the input data are fragmented in the memory. 0 - The crypto is not waiting for more input data. 1 - The crypto waits for more input data. The CRYPTO_INACTIVE flag remains to zero to indicate that the calculation is not finished. The supervisor of the CRYPTO must program to the CRYPTO_FETCH_ADDR and CRYPTO_LEN a new input data fragment. The calculation will be continued as soon as the CRYPTO_START register will be written with 1. This action will clear the CRYPTO_WAIT_FOR_IN flag. 1 2 read-only ANAMISC ANAMISC registers Peripheral_Registers 0x0 0x0 0x68 registers n CHARGER_CTRL1_REG Charger control register 1 0x8 16 read-write n 0x0 0x0 CHARGE_CUR Constant Current levels (typical values) 0000: 5 mA 0001: 10 mA 0010: 30 mA 0011: 45 mA 0100: 60 mA 0101: 90 mA 0110: 120 mA 0111: 150 mA 1000: 180 mA 1001: 210 mA 1010: 270 mA 1011: 300 mA 1100: 350 mA 1101: 400 mA 8 12 read-write CHARGE_LEVEL Constant Voltage Levels 00000: 3.00V (reset) 00001: 3.40V (e.g. 2xNiMH) 00010: 3.50V 00011: 3.60V (e.g. Li-phosphate) 00100: 3.74V 00101: 3.86V 00110: 4.00V 00111: 4.05V 01000: 4.10V 01001: 4.15V 01010: 4.20V (e.g. Li-Co, Li-Mn, NMC) 01011: 4.25V 01100: 4.30V 01101: 4.35V 01110: 4.40V 01111: 4.50V 10000: 4.60V 10001: 4.90V e.g. 3xNiMH 10010: 5.00V 0 5 read-write CHARGE_ON 0: Charger in powerdown 1: Charger enabled 5 6 read-write DIE_TEMP_DISABLE 0: Die temperature protection enabled: charger will be disabled when die temp exceeds value set in DIE_TEMP_SET 1: Die temperature protection disabled: testmode, use only in agreement with Dialog 14 15 read-write DIE_TEMP_SET Die temperature protection level. Charging will be automatically disabled if set level is exceeded and resumed when temperature has dropped few degrees below set level. 00: 0oC (do not use, for test only) 01: 50oC (do not use, for test only) 10: 80oC (default) 11: 100oC 12 14 read-write NTC_DISABLE 0: Charger NTC protection enabled 1: Charger NTC protection disable 6 7 read-write NTC_LOW_DISABLE 0: Normal operation: voltage level higher than 7/8 VDD_USB will disable the charger 1: NTC low temp limit disabled: use if trickle charging below the minimum temperature is required 7 8 read-write CHARGER_CTRL2_REG Charger control register 2 0xA 16 read-write n 0x0 0x0 CHARGER_TEST Signals are mapped on SPDIF pin. Also set ANA_TEST_REG[ANA_TESTBUS_TO_ADCPIN] = 1 000: normal mode (no test selected) 001: Vptat (temperature sensor) [1.4V max] 010: Vbat_sense after divider [1.2V] 011: Current loop output [0 to vsupply] 100: Voltage loop output [0 to vsupply] 101: Imeas or Iref/10 110: Icharge reduced by 26.6 111: reserved 13 16 read-write CHARGER_VFLOAT_ADJ Independent adjustment for the charge level. Adjust range is +/- 1.8 percent. The 4 bits adjustment is in two's complement. 4 8 read-write CURRENT_GAIN_TRIM do not change, for test purpose only 0 4 read-write CURRENT_OFFSET_TRIM do not change, for test purpose only 8 13 read-write CHARGER_STATUS_REG Charger status and trimming register 0xC 16 read-write n 0x0 0x0 CHARGER_BATTEMP_HIGH 0: Battery pack temperature 'ok' or 'too low' (voltage level on NTC pin above 1/2 VDD_USB) 1: Battery pack temperature 'too high' (voltage level on NTC pin below 1/2 VDD_USB) 5 6 read-only CHARGER_BATTEMP_LOW 0: Battery pack temperature 'ok' or 'too high' (voltage level on NTC pin below 7/8 VDD_USB) 1: Battery pack temperature 'too low' (voltage level on NTC pin above than 7/8 VDD_USB) 3 4 read-only CHARGER_BATTEMP_OK 0: Battery pack temperature 'too low' or 'too high' (voltage level on NTC pin below 1/2 or above 7/8 VDD_USB) 1: Battery pack temperature 'ok' (voltage level on NTC pin between 1/2 and 7/8 VDD_USB) 4 5 read-only CHARGER_CC_MODE 0: current loop not in regulation (or charger is off) 1: constant current mode active, current loop in regulation. 0 1 read-only CHARGER_CV_MODE 0: voltage loop not in regulation (or charger is off) 1: constant voltage mode active, voltage loop in regulation. 1 2 read-only CHARGER_TMODE_PROT 0: Dietemp below DIE_TEMP_SET level. Normal operation 1: Dietemp above DIE_TEMP_SET level. Charging is disabled 6 7 read-only END_OF_CHARGE 0: Actual charge current is between 10...100 percent of set CHARGE_CUR (or CHARGE_ON=0) 1: Actual charge current <10 percent of set CHARGE_CUR 2 3 read-only CLK_REF_CNT_REG Count value for oscillator calibration 0x62 16 read-write n 0x0 0x0 REF_CNT_VAL Indicates the calibration time, with a decrement counter to 1. 0 16 read-write CLK_REF_SEL_REG Select clock for oscillator calibration 0x60 16 read-write n 0x0 0x0 REF_CAL_START Writing a '1' starts a calibration. This bit is cleared when calibration is finished, and CLK_REF_VAL is ready. 2 3 read-write REF_CLK_SEL Select clock input for calibration: 0x0 : RC32K oscillator 0x1 : RC16M oscillator 0x2 : XTAL32K oscillator 0x3 : RCX oscillator 0 2 read-write CLK_REF_VAL_H_REG DIVN reference cycles, upper 16 bits 0x66 16 read-write n 0x0 0x0 XTAL_CNT_VAL Returns the upper 16 bits of DIVN clock cycles counted during the calibration time, defined with REF_CNT_VAL 0 16 read-only CLK_REF_VAL_L_REG DIVN reference cycles, lower 16 bits 0x64 16 read-write n 0x0 0x0 XTAL_CNT_VAL Returns the lower 16 bits of DIVN clock cycles counted during the calibration time, defined with REF_CNT_VAL 0 16 read-only SOC_ADD2CH_REG Fuel Gauge manually add extra charge to SOC_CHARGE_CNTRx_REG 0x46 16 read-write n 0x0 0x0 SOC_ADD2CH Extra charge to be added to the SOC_CHARGE_CNTRx_REG per sample period (9-bit + sign + 6 fractional bits 0 16 read-write SOC_CHARGE_AVG_REG Fuel Gauge Average charge counter 0x50 16 read-write n 0x0 0x0 CHARGE_AVG Average of 'charge' current (9-bit + sign and 6 fractional bits 0 16 read-only SOC_CHARGE_CNTR1_REG Fuel Gauge Charge counter bits 15-0 0x48 16 read-write n 0x0 0x0 CHARGE_CNT1 Sum of the charge-values per sampling period (bits15:0) The absolute full-scale charge value is 6-bits, At full scale charge current it takes 2^26 sampling periods until overflow of the charge_cnt register after a reset_charge event. At fs=144kHz (=default) this will happen after 33 hours At fs=1.152MHz After 10 hours 0 16 read-only SOC_CHARGE_CNTR2_REG Fuel Gauge Charge counter bits 31-16 0x4A 16 read-write n 0x0 0x0 CHARGE_CNT2 Sum of the charge-values per sampling period (bits23:16) 0 16 read-only SOC_CHARGE_CNTR3_REG Fuel Gauge Charge counter bits 39-32 0x4C 16 read-write n 0x0 0x0 CHARGE_CNT3 Sum of the charge-values per sampling period (bits39:24) 0 8 read-only SOC_CTRL1_REG Fuel Gauge Control register 1 0x40 16 read-write n 0x0 0x0 SOC_BIAS Current DAC scaler 0: Ibias = 2 uA 1: Ibias = 1 uA (=default) 2: Ibias = 0.5 uA 3: Ibias = 0.25 uA 12 14 read-write SOC_CINT Integrator capacitor scaler 0: Cint = 1 pF 1: Cint = 2 pF 2: Cint = 4 pF 3: Cint = 8 pF (=default) 14 16 read-write SOC_CLK SOC Sample frequency 0: automatic mode (tbd) 1: fs = 18 kHz 2: fs = 36 kHz 3: fs = 72 kHz 4: fs = 144 kHz (=default) 5: fs = 288 kHz 6: fs = 576 kHz 7: fs = 1152 kHz 9 12 read-write SOC_ENABLE 0: SOC analog circuits off. CHARGE_CNTRx_REG can still be written for a manual update. See SOC_ADD2CH_REG 1: SOC analog circuits enabled 0 1 read-write SOC_GPIO Reserved (not yet implemented): switches the SOC-inputs to the GPIO pins 4 5 read-write SOC_IDAC Scales the current DAC (Ibias: default=1uA) 0: Idac=0.25*Ibias 1: Idac=0.5*Ibias 2: Idac=Ibias (=default) 3: Idac=2*Ibias 6 8 read-write SOC_LPF 0: low-pass filter at integrator inputs disabled 1: Enables a low-pass filter at the integrator inputs 8 9 read-write SOC_MUTE 0: Normal operation 1: Connect the input voltage to 0V 3 4 read-write SOC_RESET_AVG 1: Reset the SOC_CHARGE_AVG_REG to the last value of SOC_CHARGE_CNTRx_REG 2 3 read-write SOC_RESET_CHARGE 1: Reset CHARGE_CNTR_REG 1 2 read-write SOC_SIGN Defines the sign of the charge converter input and output to perform a chopper function to eliminate offset voltage (see also SOC_CHOP and 'sign' on output pin) 0: non-inverted inputs and outputs 1: inverted inputs and outputs 5 6 read-write SOC_CTRL2_REG Fuel Gauge Control register 2 0x42 16 read-write n 0x0 0x0 SOC_CHOP Chopping control 0: 'external' chopping control with 'soc_sign'-input 1: chop each 2^1*scycle fs-periods 2: chop each 2^2*scycle fs-periods .. 7: chop each 2^7*scycle fs-periods. 8 11 read-write SOC_CMIREG_ENABLE SOC_CMIREG enable 11 12 read-write SOC_DCYCLE Cycle the current divider segments of Idac 0: no cycling 1: cycle each scycle fs-periods 5 6 read-write SOC_DYNAVG if HIGH then 'weight' of Moving Average is forced to 1 if the converter detects significant input change (if dcharge > 4*delta_c, or high_limit, or low_limit) 15 16 read-write SOC_ICM adds a common-mode current to Idac to increase the common-mode input-level of the integrator. The common-mode input level is equal to (Idac+Icm)*Rvi 0: Icm=0 1: Icm=1*Ibias (=default) 2: Icm=2*Ibias 3: Icm=4*Ibias 6 8 read-write SOC_MAW Moving Average Weight factor charge_avg(n) = (weight*charge_avg(n-1) + charge(n) ) / (weight+1) where:weight = 2^(soc_maw) 12 15 read-write SOC_RVI Voltage-to-current resistor scaler 0: Rvi = 25 k 1: Rvi = 50 k 2: Rvi = 100 k (= default) 3: Rvi = 200 k 0 2 read-write SOC_SCYCLE Cycle current segments (8 segments) of Idac 0: no cycling 1: cycle each fs-period 2: cycle each 2 fs-periods .. 7: cycle each 7 fs-periods 2 5 read-write SOC_CTRL3_REG Fuel Gauge Control register 3 0x44 16 read-write n 0x0 0x0 SOC_DYNHYS Reserved. (To be implemented) Hysteresis of the comparator which detects if the integrator voltage is rising or falling 3 4 read-write SOC_DYNTARG Reserved. (To be implemented) 0: Vint_target = 0V 1: Vint_target tracks the 2 MSB's of the charge register) 2 3 read-write SOC_VCMI Common Input Voltage target of regulator (see SOC_CMIREG_ENABLE) 0: 50 mV 1: 100 mV 2: 150 mV 3: 200 mV 4 6 read-write SOC_VSAT Trigger level of the high-limit and low-limit comparators. 0: low_limit = -50mV high_limit = +50mV 1: low_limit = -100mV high_limit = +100mV (=default) 2: low_limit = -200mV high_limit = +200mV 3: low_limit = -400mV high_limit = +400mV 0 2 read-write SOC_EXT_IN_REG Fuel Gauge input test register 0x54 16 read-write n 0x0 0x0 SOC_EXT_IDAC_EN 1: Enable 'external' control of Idac 15 16 read-write SOC_EXT_SCYCLE_EN 1: Enable 'external' control of scycle 14 15 read-write SOC_IDAC_SIGN 0: SOC_IDAC_VAL is positive 1: SOC_IDAC_VAL is negative 9 10 read-write SOC_IDAC_VAL Controls the current for the DAC. 0: 0/512*SOC_IDAC N: N/512*SOC_IDAC 0 9 read-write SOC_NR_SCYCLE Number of the scycle 11 14 read-write SOC_RDAC_DIS 0: Disables the resistor divider DAC. The Idac has 6-bits (plus sign) 1: Enables the resistor divider DAC. The Idac has 9-bits (plus sign) 10 11 read-write SOC_EXT_OUT_REG Fuel Gauge output test register 0x56 16 read-write n 0x0 0x0 SOC_CTRL_EVENT Controller event 8 9 read-only SOC_HIGH_LIM High_limit comparator output 0 1 read-only SOC_LOWLIM_COMP Low_limit comparator output 1 2 read-only SOC_POS_COMP Positive comparator output 2 3 read-only SOC_RISING_COMP Rising comparator output 3 4 read-only SOC_STATE Controller state 4 8 read-only SOC_STATUS_REG Fuel Gauge Status register 0x52 16 read-write n 0x0 0x0 SOC_INT_LOCKED 0: Normal Operation 1: Integrator is pushed over high or low limit. Returns to '0' if the converter runs for more than 2 sequential sampling periods in a 'safe' region (dcharge < 2*delta_c) 1 2 read-only SOC_INT_OVERLOAD 0: Normal Operation 1: Integrator exceeds high or low limit with full-scale IDAC (charge) for more than 3 sequential sampling periods 0 1 read-only APU APU registers Peripheral_Registers 0x0 0x0 0x114 registers n COEF0A_SET1_REG SRC coefficient 10 set 1 0x34 32 read-write n 0x0 0x0 SRC_COEF10 coefficient 10 0 16 read-write COEF10_SET1_REG SRC coefficient 1,0 set 1 0x20 32 read-write n 0x0 0x0 SRC_COEF0 coefficient 0 0 16 read-write SRC_COEF1 coefficient 1 16 32 read-write COEF32_SET1_REG SRC coefficient 3,2 set 1 0x24 32 read-write n 0x0 0x0 SRC_COEF2 coefficient 2 0 16 read-write SRC_COEF3 coefficient 3 16 32 read-write COEF54_SET1_REG SRC coefficient 5,4 set 1 0x28 32 read-write n 0x0 0x0 SRC_COEF4 coefficient 4 0 16 read-write SRC_COEF5 coefficient 5 16 32 read-write COEF76_SET1_REG SRC coefficient 7,6 set 1 0x2C 32 read-write n 0x0 0x0 SRC_COEF6 coefficient 6 0 16 read-write SRC_COEF7 coefficient 7 16 32 read-write COEF98_SET1_REG SRC coefficient 9,8 set 1 0x30 32 read-write n 0x0 0x0 SRC_COEF8 coefficient 8 0 16 read-write SRC_COEF9 coefficient 9 16 32 read-write MUX_REG APU mux register 0x1C 32 read-write n 0x0 0x0 PCM1_MUX_IN PCM1 input mux 0 = off 1 = SRC1 output 2 = PCM output registers 3 6 read-write PDM1_MUX_IN PDM1 input mux 0 = SRC1_MUX_IN 1 = PDM input 6 7 read-write SRC1_MUX_IN SRC1 input mux 0 = off 1 = PCM output 2 = SRC1 input registers 0 3 read-write PCM1_CTRL_REG PCM1 Control register 0x100 32 read-write n 0x0 0x0 PCM_CH_DEL Channel delay in multiples of 8 bits 11 16 read-write PCM_CLKINV 0:PCM CLK 1:PCM CLK inverted 8 9 read-write PCM_CLK_BIT 0:One clock cycle per data bit 1:Two cloc cycles per data bit 10 11 read-write PCM_EN 0:PCM interface disabled 1:PCM interface enabled 0 1 read-write PCM_FSCDEL 0:PCM FSC starts one cycle before MSB bit 1:PCM FSC starts at the same time as MSB bit 6 7 read-write PCM_FSCINV 0: PCM FSC 1: PCM FSC inverted 9 10 read-write PCM_FSCLEN 0:PCM FSC length equal to 1 data bit N:PCM FSC length equal to N*8 2 6 read-write PCM_FSC_DIV PCM Framesync divider, Values 7-0xFFF. To divide by N, write N-1. (Minimum value N-1=7 for 8 bits PCM_FSC) Note if PCM_CLK_BIT=1, N must always be even 20 32 read-write PCM_FSC_EDGE 0: shift channels 1, 2, 3, 4, 5, 6, 7, 8 after PCM_FSC edge 1: shift channels 1, 2, 3, 4 after PCM_FSC edge shift channels 5, 6, 7, 8 after opposite PCM_FSC edge 16 17 read-write PCM_MASTER 0:PCM interface in slave mode 1:PCM interface in master mode 1 2 read-write PCM_PPOD 0:PCM DO push pull 1:PCM DO open drain 7 8 read-write PCM1_IN1_REG PCM1 data in 1 0x104 32 read-write n 0x0 0x0 PCM_IN PCM1_IN1 bits 31-0 0 32 read-only PCM1_IN2_REG PCM1 data in 2 0x108 32 read-write n 0x0 0x0 PCM_IN PCM1_IN2 bits 31-0 0 32 read-only PCM1_OUT1_REG PCM1 data out 1 0x10C 32 read-write n 0x0 0x0 PCM_OUT PCM1_OUT1 bits 31-0 0 32 read-write PCM1_OUT2_REG PCM1 data out 2 0x110 32 read-write n 0x0 0x0 PCM_OUT PCM1_OUT2 bits 31-0 0 32 read-write SRC1_CTRL_REG SRC1 control register 0x0 32 read-write n 0x0 0x0 SRC_DITHER_DISABLE Dithering feature 0: Enable 1: Disable 7 8 read-write SRC_EN SRC1_IN and SRC1_OUT enable 0: disabled 1: enabled 0 1 read-write SRC_IN_AMODE SRC1_IN Automatic conversion mode 0: Manual mode 1: Automatic mode 1 2 read-write SRC_IN_CAL_BYPASS SRC1_IN upsampeling filter bypass 0: Do not bypass 1: Bypass filter 2 3 read-write SRC_IN_DS SRC1_IN UpSampling IIR filters setting 00: for sample rates up-to 48kHz 01: for sample rates of 96kHz 10: reserved 11: for sample rates of 192kHz 4 6 read-write SRC_IN_FLOWCLR Writing a 1 clears the SRC1_IN Overflow/underflow bits 21-20. No more over/underflow indications while bit is 1. Keep 1 until the over/under flow bit is cleared 24 25 write-only SRC_IN_OK SRC1_IN status 0: Acquisition in progress 1: Acquisition ready 6 7 read-only SRC_IN_OVFLOW 1 = SRC1_IN Overflow occurred 20 21 read-only SRC_IN_UNFLOW 1 = SRC1_IN Underflow occurred 21 22 read-only SRC_OUT_AMODE SRC1_OUT1 Automatic Conversion mode 0:Manual mode 1:Automatic mode 13 14 read-write SRC_OUT_CAL_BYPASS SRC1_OUT1 upsampiling filter bypass 0:Do not bypass 1:Bypass filter 14 15 read-write SRC_OUT_FLOWCLR Writing a 1 clears the SRC1_OUT Overflow/underflow bits 23-22. No more over/underflow indications while bit is 1. Keep 1 until the over/under flow bit is cleared 25 26 write-only SRC_OUT_OK SRC1_OUT Status 0: acquisition in progress 1: acquisition ready (In manual mode this bit is always 1) 18 19 read-only SRC_OUT_OVFLOW 1 = SRC1_OUT Overflow occurred 22 23 read-only SRC_OUT_UNFLOW 1 = SRC1_OUT Underflow occurred 23 24 read-only SRC_OUT_US SRC1_OUT UpSampling IIR filters setting 00: for sample rates up-to 48kHz 01: for sample rates of 96kHz 10: reserved 11: for sample rates of 192kHz 16 18 read-write SRC_PDM_MODE PDM Output mode selection on PDM_DO1 00: No output 01: Right channel (falling edge of PDM_CLK) 10: Left channel (rising edge of PDM_CLK) 11: Left and Right channel 28 30 read-write SRC1_IN1_REG SRC1 data in 1 0xC 32 read-write n 0x0 0x0 SRC_IN SRC1_IN1 8 32 read-write SRC1_IN2_REG SRC1 data in 2 0x10 32 read-write n 0x0 0x0 SRC_IN SRC1_IN2 8 32 read-write SRC1_IN_FS_REG SRC1 Sample input rate 0x4 32 read-write n 0x0 0x0 SRC_IN_FS SRC_IN Sample rate SRC_IN_FS = 8192*Sample_rate/100 Sample_rate upper limit is 192 kHz. For 96 kHz and 192 kHz SRC_CTRLx_REG[SRC_IN_DS] must be set as shown below: Sample_rate SRC_IN_FS SRC_IN_DS Audio BW 8000 Hz 0xA0000 0 4000 Hz 11025 Hz 0x0DC800 0 5512 Hz 16000 Hz 0x140000 0 8000 Hz 22050 Hz 0x1B9000 0 11025 Hz 32000 Hz 0x280000 0 16000 Hz 44100 Hz 0x372000 0 22050 Hz 48000 Hz 0x3C0000 0 24000 Hz 96000 Hz 0x3C0000 1 24000 Hz 192000 Hz 0x3C0000 3 24000 Hz In manual SRC mode, SRC_IN_FS can be set and adjusted to the desired sample rate at any time. In automatic mode the SRC returns the final sample rate as soon as SRC_IN_OK. Note that SRC_DS is not calculated in automatic mode and must be set manually automatic mode with Sample_rate of 96 kHz and 192 kHz. 0 24 read-write SRC1_OUT1_REG SRC1 data out 1 0x14 32 read-write n 0x0 0x0 SRC_OUT SRC1_OUT1 8 32 read-only SRC1_OUT2_REG SRC1 data out 2 0x18 32 read-write n 0x0 0x0 SRC_OUT SRC1_OUT2 8 32 read-only SRC1_OUT_FS_REG SRC1 Sample output rate 0x8 32 read-write n 0x0 0x0 SRC_OUT_FS SRC_OUT Sample rate SRC_OUT_FS = 8192*Sample_rate/100 Sample_rate upper limit is 192 kHz. For 96 kHz and 192 kHz SRC_CTRLx_REG[SRC_DS] must be set as shown below: Sample_rate SRC_OUT_FS SRC_OUT_DS Audio BW 8000 Hz 0xA0000 0 4000 Hz 11025 Hz 0x0DC800 0 5512 Hz 16000 Hz 0x140000 0 8000 Hz 22050 Hz 0x1B9000 0 11025 Hz 32000 Hz 0x280000 0 16000 Hz 44100 Hz 0x372000 0 22050 Hz 48000 Hz 0x3C0000 0 24000 Hz 96000 Hz 0x3C0000 1 24000 Hz 192000 Hz 0x3C0000 3 24000 Hz In manual SRC mode, SRC_OUT_FS can be set and adjusted to the desired sample rate at any time. In automatic mode the SRC returns the final sample rate as soon as SRC_OUT_OK. Note that SRC_DS is not calculated in automatic mode and must be set manually automatic mode with Sample_rate of 96 kHz and 192 kHz. 0 24 read-write BLE BLE registers Peripheral_Registers 0x0 0x0 0x214 registers n ACTSCANSTAT_REG Active scan register 0xA4 32 read-write n 0x0 0x0 BACKOFF Active scan mode back-off counter initialization value. 16 25 read-only UPPERLIMIT Active scan mode upper limit counter value. 0 9 read-only ADVCHMAP_REG Advertising Channel Map 0x90 32 read-write n 0x0 0x0 ADVCHMAP Advertising Channel Map, defined as per the advertising connection settings. Contains advertising channels index 37 to 39. If ADVCHMAP[i] equals: 0: Do not use data channel i+37. 1: Use data channel i+37. 0 3 read-write ADVTIM_REG Advertising Packet Interval 0xA0 32 read-write n 0x0 0x0 ADVINT Advertising Packet Interval defines the time interval in between two ADV_xxx packet sent. Value is in us. Value to program depends on the used Advertising Packet type and the device filtering policy. 0 14 read-write AESCNTL_REG Start AES register 0xC0 32 read-write n 0x0 0x0 AES_MODE 0: Cipher mode 1: Decipher mode 1 2 read-write AES_START Writing a 1 starts AES-128 ciphering/deciphering process. This bit is reset once the process is finished (i.e. ble_crypt_irq interrupt occurs, even masked) 0 1 write-only AESKEY127_96_REG AES encryption key 0xD0 32 read-write n 0x0 0x0 AESKEY127_96 AES encryption 128-bit key. Bit 127 down to 96 0 32 read-write AESKEY31_0_REG AES encryption key 0xC4 32 read-write n 0x0 0x0 AESKEY31_0 AES encryption 128-bit key. Bit 31 down to 0 0 32 read-write AESKEY63_32_REG AES encryption key 0xC8 32 read-write n 0x0 0x0 AESKEY63_32 AES encryption 128-bit key. Bit 63 down to 32 0 32 read-write AESKEY95_64_REG AES encryption key 0xCC 32 read-write n 0x0 0x0 AESKEY95_64 AES encryption 128-bit key. Bit 95 down to 64 0 32 read-write AESPTR_REG Pointer to the block to encrypt/decrypt 0xD4 32 read-write n 0x0 0x0 AESPTR Pointer to the memory zone where the block to cipher/decipher using AES-128 is stored. 0 16 read-write BASETIMECNTCORR_REG Base Time Counter 0x44 32 read-write n 0x0 0x0 BASETIMECNTCORR Base Time Counter correction value. 0 27 read-write BASETIMECNT_REG Base time reference counter 0x1C 32 read-write n 0x0 0x0 BASETIMECNT Value of the 625us base time reference counter. Updated each time SAMPCLK is written. Used by the SW in order to synchronize with the HW 0 27 read-only BDADDRL_REG BLE device address LSB register 0x24 32 read-write n 0x0 0x0 BDADDRL Bluetooth Low Energy Device Address. LSB part. 0 32 read-write BDADDRU_REG BLE device address MSB register 0x28 32 read-write n 0x0 0x0 BDADDRU Bluetooth Low Energy Device Address. MSB part. 0 16 read-write PRIV_NPUB Bluetooth Low Energy Device Address privacy indicator 0: Public Bluetooth Device Address 1: Private Bluetooth Device Address 16 17 read-write BLEMPRIO0_REG Coexistence interface Priority 0 Register 0x108 32 read-write n 0x0 0x0 BLEM0 Set Priority value for Initiating (Connection Request Response) BLE message 0 4 read-write BLEM1 Set Priority value for LLCP BLE message 4 8 read-write BLEM2 Set Priority value for Data Channel transmission BLE message 8 12 read-write BLEM3 Set Priority value for Initiating (Scanning) BLE message 12 16 read-write BLEM4 Set Priority value for Active Scanning BLE message 16 20 read-write BLEM5 Set Priority value for Connectable Advertising BLE message 20 24 read-write BLEM6 Set Priority value for Non-Connectable Advertising 24 28 read-write BLEM7 Set Priority value for Passive Scanning 28 32 read-write BLEMPRIO1_REG Coexistence interface Priority 1 Register 0x10C 32 read-write n 0x0 0x0 BLEMDEFAULT Set default priority value for other BLE message than those defined above 28 32 read-write BLEPRIOSCHARB_REG Priority Scheduling Arbiter Control Register 0x110 32 read-write n 0x0 0x0 BLEMARGIN Determine the decision instant margin for Priority Scheduling Arbitration. 0 8 read-write BLEPRIOMODE Determine BLE Priority Scheduling Arbitration Mode 0: BLE Decision instant not used 1: BLE Decision instant used 15 16 read-write CNTL2_REG BLE Control Register 2 0x200 32 read-write n 0x0 0x0 BLE_CLK_SEL BLE Clock Select. Specifies the BLE master clock absolute frequency in MHz. Typical values are 16 and 8. Value depends on the selected XTAL frequency and the value of CLK_RADIO_REG[BLE_DIV] bitfield. For example, if XTAL oscillates at 16MHz and CLK_RADIO_REG[BLE_DIV] = 1 (divide by 2), then BLE master clock frequency is 8MHz and BLE_CLK_SEL should be set to value 8. The selected BLE master clock frequency (affected by BLE_DIV and BLE_CLK_SEL) must be modified and set only during the initialization time, i.e. before setting BLE_RWBTLECNTL_REG[RWBLE_EN] to 1. Refer also to BLE_RWBTLECONF_REG[CLK_SEL]. 9 15 read-write BLE_CLK_STAT 0: BLE uses low power clock 1: BLE uses master clock 6 7 read-write BLE_RSSI_SEL 0: Select Peak-hold RSSI value (default). 1: Select current Average RSSI value. 21 22 read-write EMACCERRACK Exchange Memory Access Error Acknowledge. When the SW writes a 1 to this bit then the EMACCERRSTAT bit will be cleared. When the SW writes 0 it will have no affect. The read value is always 0 . 1 2 read-write EMACCERRMSK Exchange Memory Access Error Mask: When cleared to 0 the EM_ACC_ERR will not cause an BLE_ERROR_IRQ interrupt. When set to 1 an BLE_ERROR_IRQ will be generated as long as EM_ACC_ERR is 1 . 2 3 read-write EMACCERRSTAT Exchange Memory Access Error Status: The bit is read-only and can be cleared only by writing a 1 at EMACCERRACK bitfield. This bit will be set to 1 by the hardware when the controller will access an EM page that is not mapped according to the EM_MAPPING value. When this bit is 1 then the BLE_ERROR_IRQ will be asserted as long as EMACCERRMSK is 1 . 0 1 read-write MON_LP_CLK The SW can only write a 0 to this bit. Whenever a positive edge of the low power clock used by the BLE Timers is detected, then the HW will automatically set this bit to 1 . This functionality will not work if BLE Timer is in reset state (refer to CLK_RADIO_REG[BLE_LP_RESET]). This bit can be used for SW synchronization, to debug the low power clock, etc. 7 8 read-write RADIO_PWRDN_ALLOW This active high signal indicates when it is allowed for the BLE core (embedded in the Radio sub-System power domain) to be powered down. After the assertion of the BLE_DEEPSLCNTL_REG[DEEP_SLEEP_ON] a hardware sequence based on the Low Power clock will cause the assertion of RADIO_PWRDN_ALLOW. The RADIO_PWRDN_ALLOW will be cleared to 0 when the BLE core exits from the sleep state, i.e. when the BLE_SLP_IRQ will be asserted. 8 9 read-write SW_RPL_SPI Keep to 0. 19 20 read-write WAKEUPLPSTAT The status of the BLE_WAKEUP_LP_IRQ. The Interrupt Service Routine of BLE_WAKEUP_LP_IRQ should return only when the WAKEUPLPSTAT is cleared. Note that BLE_WAKEUP_LP_IRQ is automatically acknowledged after the power up of the Radio Subsystem, plus one Low Power Clock period. 20 21 read-write COEXIFCNTL0_REG Coexistence interface Control 0 Register 0x100 32 read-write n 0x0 0x0 COEX_EN Enable / Disable control of the MWS/WLAN Coexistence control 0: Coexistence interface disabled 1: Coexistence interface enabled 0 1 read-write SYNCGEN_EN Determines whether ble_sync is generated or not. 0: ble_sync pulse not generated 1: ble_sync pulse generated 1 2 read-write WLANRXMSK Determines how wlan_rx impact BLE Tx and Rx 00: wlan_rx has no impact 01: wlan_rx can stop BLE Tx, no impact on BLE Rx (default mode) 10: wlan_rx can stop BLE Rx, no impact on BLE Tx 11: wlan_rx can stop both BLE Tx and BLE Rx 4 6 read-write WLANTXMSK Determines how wlan_tx impact BLE Tx and Rx 00: wlan_tx has no impact (default mode) 01: wlan_tx can stop BLE Tx, no impact on BLE Rx 10: wlan_tx can stop BLE Rx, no impact on BLE Tx 11: wlan_tx can stop both BLE Tx and BLE Rx 6 8 read-write WLCRXPRIOMODE Defines Bluetooth Low Energy packet ble_rx mode behavior. 00: Rx indication excluding Rx Power up delay (starts when correlator is enabled) 01: Rx indication including Rx Power up delay 10: Rx High priority indicator 11: n/a 20 22 read-write WLCTXPRIOMODE Defines Bluetooth Low Energy packet ble_tx mode behavior 00: Tx indication excluding Tx Power up delay 01: Tx indication including Tx Power up delay 10: Tx High priority indicator 11: n/a 16 18 read-write COEXIFCNTL1_REG Coexistence interface Control 1 Register 0x104 32 read-write n 0x0 0x0 WLCPDELAY Applies on ble_tx if WLCTXPRIOMODE equals 10. Applies on ble_rx if WLCRXPRIOMODE equals 10. Determines the delay (in us) in Tx/Rx enables rises the time Bluetooth Low energy Tx/Rx priority has to be provided . 0 7 read-write WLCPDURATION Applies on ble_tx if WLCTXPRIOMODE equals 10 Applies on ble_rx if WLCRXPRIOMODE equals 10 Determines how many s the priority information must be maintained Note that if WLCPDURATION = 0x00, then Tx/Rx priority levels are maintained till Tx/Rx EN are de-asserted. 8 15 read-write WLCPRXTHR Applies on ble_rx if WLCRXPRIOMODE equals 10 Determines the threshold for Rx priority setting. If ble_pti[3:0] output value is greater than WLCPRXTHR, then Rx Bluetooth Low Energy priority is considered as high, and must be provided to the WLAN coexistence interface 24 29 read-write WLCPTXTHR Applies on ble_tx if WLCTXPRIOMODE equals 10 Determines the threshold for priority setting. If ble_pti[3:0] output value is greater than WLCPTXTHR, then Tx Bluetooth Low Energy priority is considered as high, and must be provided to the WLAN coexistence interface 16 21 read-write CURRENTRXDESCPTR_REG Rx Descriptor Pointer for the Receive Buffer Chained List 0x2C 32 read-write n 0x0 0x0 CURRENTRXDESCPTR Rx Descriptor Pointer that determines the starting point of the Receive Buffer Chained List 0 15 read-write ETPTR Exchange Table Pointer that determines the starting point of the Exchange Table 16 32 read-write DEBUGADDMAX_REG Upper limit for the memory zone 0x58 32 read-write n 0x0 0x0 EM_ADDMAX Upper limit for the Exchange Memory zone indicated by the em_inzone flag 0 16 read-write REG_ADDMAX Upper limit for the Register zone indicated by the reg_inzone flag 16 32 read-write DEBUGADDMIN_REG Lower limit for the memory zone 0x5C 32 read-write n 0x0 0x0 EM_ADDMIN Lower limit for the Exchange Memory zone indicated by the em_inzone flag 0 16 read-write REG_ADDMIN Lower limit for the Register zone indicated by the reg_inzone flag 16 32 read-write DEEPSLCNTL_REG Deep-Sleep control register 0x30 32 read-write n 0x0 0x0 DEEP_SLEEP_CORR_EN 625us base time reference integer and fractional part correction. Applies when system has been woken-up from Deep Sleep Mode. It enables Fine Counter and Base Time counter when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 3 4 write-only DEEP_SLEEP_IRQ_EN Always set to 3 when DEEP_SLEEP_ON is set to 1 . It controls the generation of BLE_WAKEUP_LP_IRQ. 0 2 read-write DEEP_SLEEP_ON 0: RW-BLE Core in normal active mode 1: Request RW-BLE Core to switch in deep sleep mode. This bit is reset on DEEP_SLEEP_STAT falling edge. 2 3 write-only DEEP_SLEEP_STAT Indicator of current Deep Sleep clock mux status: 0: RW-BLE Core is not yet in Deep Sleep Mode 1: RW-BLE Core is in Deep Sleep Mode (only low_power_clk is running) 15 16 read-only EXTWKUPDSB External Wake-Up disable 0: RW-BLE Core can be woken by external wake-up 1: RW-BLE Core cannot be woken up by external wake-up 31 32 read-write SOFT_WAKEUP_REQ Wake Up Request from RW-BLE Software. Applies when system is in Deep Sleep Mode. It wakes up the RW-BLE Core when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 4 5 write-only DEEPSLSTAT_REG Duration of the last deep sleep phase register 0x38 32 read-write n 0x0 0x0 DEEPSLDUR Actual duration of the last deep sleep phase measured in low_power_clk clock cycle. DEEPSLDUR is set to zero at the beginning of the deep sleep phase, and is incremented at each low_power_clk clock cycle until the end of the deep sleep phase. 0 32 read-only DEEPSLWKUP_REG Time (measured in Low Power clock cycles) in Deep Sleep Mode before waking-up the device 0x34 32 read-write n 0x0 0x0 DEEPSLTIME Determines the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device. This ensures a maximum of 37 hours and 16mn sleep mode capabilities at 32kHz. This ensures a maximum of 36 hours and 16mn sleep mode capabilities at 32.768kHz 0 32 read-write DIAGCNTL2_REG Debug use only 0x20C 32 read-write n 0x0 0x0 DIAG4 Only relevant when DIAG4_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG4. 0 6 read-write DIAG4_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 7 8 read-write DIAG5 Only relevant when DIAG5_EN= 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG5. 8 14 read-write DIAG5_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 15 16 read-write DIAG6 Only relevant when DIAG6_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG6. 16 22 read-write DIAG6_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 23 24 read-write DIAG7 Only relevant when DIAG7_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG7. 24 30 read-write DIAG7_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 31 32 read-write DIAGCNTL3_REG Debug use only 0x210 32 read-write n 0x0 0x0 DIAG0_BIT Selects which bit from the DIAG0 word will be forwarded to bit 0 of the BLE DIagnostic Port. 0 3 read-write DIAG0_INV If set, then the specific diagnostic bit will be inverted. 3 4 read-write DIAG1_BIT Selects which bit from the DIAG1 word will be forwarded to bit 1 of the BLE DIagnostic Port. 4 7 read-write DIAG1_INV If set, then the specific diagnostic bit will be inverted. 7 8 read-write DIAG2_BIT Selects which bit from the DIAG2 word will be forwarded to bit 2 of the BLE DIagnostic Port. 8 11 read-write DIAG2_INV If set, then the specific diagnostic bit will be inverted. 11 12 read-write DIAG3_BIT Selects which bit from the DIAG3 word will be forwarded to bit 3 of the BLE DIagnostic Port. 12 15 read-write DIAG3_INV If set, then the specific diagnostic bit will be inverted. 15 16 read-write DIAG4_BIT Selects which bit from the DIAG4 word will be forwarded to bit 4 of the BLE DIagnostic Port. 16 19 read-write DIAG4_INV If set, then the specific diagnostic bit will be inverted. 19 20 read-write DIAG5_BIT Selects which bit from the DIAG5 word will be forwarded to bit 5 of the BLE DIagnostic Port. 20 23 read-write DIAG5_INV If set, then the specific diagnostic bit will be inverted. 23 24 read-write DIAG6_BIT Selects which bit from the DIAG6 word will be forwarded to bit 6 of the BLE DIagnostic Port. 24 27 read-write DIAG6_INV If set, then the specific diagnostic bit will be inverted. 27 28 read-write DIAG7_BIT Selects which bit from the DIAG7 word will be forwarded to bit 7 of the BLE DIagnostic Port. 28 31 read-write DIAG7_INV If set, then the specific diagnostic bit will be inverted. 31 32 read-write DIAGCNTL_REG Diagnostics Register 0x50 32 read-write n 0x0 0x0 DIAG0 Only relevant when DIAG0_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG0. 0 6 read-write DIAG0_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 7 8 read-write DIAG1 Only relevant when DIAG1_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG1. 8 14 read-write DIAG1_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 15 16 read-write DIAG2 Only relevant when DIAG2_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG2. 16 22 read-write DIAG2_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 23 24 read-write DIAG3 Only relevant when DIAG3_EN = 1. Selection of the outputs that must be driven to the diagnostic port BLE_DIAG3. 24 30 read-write DIAG3_EN 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. 31 32 read-write DIAGSTAT_REG Debug use only 0x54 32 read-write n 0x0 0x0 DIAG0STAT Directly connected to ble_dbg0[7:0] output. Debug use only. 0 8 read-only DIAG1STAT Directly connected to ble_dbg1[7:0] output. Debug use only. 8 16 read-only DIAG2STAT Directly connected to ble_dbg2[7:0] output. Debug use only. 16 24 read-only DIAG3STAT Directly connected to ble_dbg3[7:0] output. Debug use only. 24 32 read-only EM_BASE_REG Exchange Memory Base Register 0x208 32 read-write n 0x0 0x0 BLE_EM_BASE_16_10 The physical address on the system memory map of the base of the Exchange Memory. 10 17 read-write ENBPRESET_REG Time in low power oscillator cycles register 0x3C 32 read-write n 0x0 0x0 TWEXT Minimum and recommended value is TWIRQ_RESET + 1 . In the case of wake-up due to an external wake-up request, TWEXT specifies the time delay in low power oscillator cycles to deassert BLE_WAKEUP_LP_IRQ. Refer also to GP_CONTROL_REG[BLE_WAKEUP_REQ]. Range is [0...64 ms] for 32kHz [0...62.5 ms] for 32.768kHz 21 32 read-write TWIRQ_RESET Recommended value is 1. Time in low power oscillator cycles to reset BLE_WAKEUP_LP_IRQ before the BLE sleep timer expiration. Refer also to BLE_DEEPSLWKUP_REG[DEEPSLTIME]. Range is [0...32 ms] for 32kHz [0...31.25 ms] for 32.768kHz. 0 10 read-write TWIRQ_SET Minimum value is TWIRQ_RESET + 1 . Time in low power oscillator cycles to set BLE_WAKEUP_LP_IRQ before the BLE sleep timer expiration. Refer also to BLE_DEEPSLWKUP_REG[DEEPSLTIME]. Range is [0...64 ms] for 32kHz [0...62.5 ms] for 32.768kHz 10 21 read-write ERRORTYPESTAT_REG Error Type Status registers 0x60 32 read-write n 0x0 0x0 ADV_UNDERRUN Indicates Advertising Interval Under run, occurs if time between two consecutive Advertising packet (in Advertising mode) is lower than the expected value. 0: No error 1: Error occurred 10 11 read-only CONCEVTIRQ_ERROR Indicates whether two consecutive and concurrent ble_event_irq have been generated, and not acknowledged in time by the RW-BLE Software. 0: No error 1: Error occurred 17 18 read-write CSFORMAT_ERROR Indicates whether CS-FORMAT has been programmed with an invalid value: this is a major software programming failure. 0: No error 1: Error occurred 12 13 read-only EVT_CNTL_APFM_ERROR Indicates Anticipated Pre-Fetch Mechanism error: happens when 2 consecutive events are programmed, and when the first event is not completely finished while second pre-fetch instant is reached. 0: No error 1: Error occured 7 8 read-only EVT_SCHDL_APFM_ERROR Indicates Anticipated Pre-Fetch Mechanism error: happens when 2 consecutive events are programmed, and when the first event is not completely finished while second pre-fetch instant is reached. 0: No error 1: Error occured 6 7 read-only EVT_SCHDL_EMACC_ERROR Indicates Event Scheduler Exchange Memory access error, happens when Exchange Memory accesses are not served in time, and blocks the Exchange Table entry read 0: No error 1: Error occurred 4 5 read-write EVT_SCHDL_ENTRY_ERROR Indicates Event Scheduler faced Invalid timing programing on two consecutive ET entries (e.g first one with 624s offset and second one with no offset) 0: No error 1: Error occurred 5 6 read-only IFS_UNDERRUN Indicates Inter Frame Space Under run, occurs if IFS time is not enough to update and read Control Structure/Descriptors, and/or White List parsing is not finished and/or Decryption time is too long to be finished on time 0: No error 1: Error occurred 9 10 read-only LLCHMAP_ERROR Indicates Link Layer Channel Map error, happens when actual number of CS-LLCHMAP bit set to one is different from CS-NBCHGOOD at the beginning of Frequency Hopping process 0: No error 1: Error occurred 11 12 read-only PKTCNTL_EMACC_ERROR Indicates Packet Controller Exchange Memory access error, happens when Exchange Memory accesses are not served in time and Tx/Rx data are corrupted 0: No error 1: Error occurred 2 3 read-only RADIO_EMACC_ERROR Indicates Radio Controller Exchange Memory access error, happens when Exchange Memory accesses are not served in time and data are corrupted. 0: No error 1: Error occurred 3 4 read-only RXCRYPT_ERROR Indicates real time decryption error, happens when AES-CCM decryption is too slow compared to Packet Controller requests. A 16-bytes block has to be decrypted prior the next block is received by the Packet Controller 0: No error 1: Error occurred 1 2 read-only RXDATA_PTR_ERROR Indicates whether Rx data buffer pointer value programmed is null: this is a major programming failure. 0: No error 1: Error occurred 16 17 read-only RXDESC_EMPTY_ERROR Indicates whether Rx Descriptor pointer value programmed in register is null: this is a major programming failure. 0: No error 1: Error occurred 14 15 read-only TXCRYPT_ERROR Indicates Real Time encryption error, happens when AES-CCM encryption is too slow compared to Packet Controller requests. A 16-bytes block has to be encrypted and prepared on Packet Controller request, and needs to be ready before the Packet Controller has to send ti 0: No error 1: Error occurred 0 1 read-only TXDATA_PTR_ERROR Indicates whether Tx data buffer pointer value programmed is null during Advertising / Scanning / Initiating events, or during Master / Slave connections with non-null packet length: this is a major programming failure. 0: No error 1: Error occurred 15 16 read-only TXDESC_EMPTY_ERROR Indicates whether Tx Descriptor pointer value programmed in Control Structure is null during Advertising / Scanning / Initiating events: this is a major programming failure. 0: No error 1: Error occurred 13 14 read-only WHITELIST_ERROR Indicates White List Timeout error, occurs if White List parsing is not finished on time 0: No error 1: Error occurred 8 9 read-only FINECNTCORR_REG Phase correction value register 0x40 32 read-write n 0x0 0x0 FINECNTCORR Phase correction value for the 625us reference counter (i.e. Fine Counter) in us. 0 10 read-write FINETIMECNT_REG Fine time reference counter 0x20 32 read-write n 0x0 0x0 FINECNT Value of the current s fine time reference counter. Updated each time SAMPCLK is written. Used by the SW in order to synchronize with the HW, and obtain a more precise sleep duration 0 10 read-only FINETIMTGT_REG Fine Timer Target value 0xF8 32 read-write n 0x0 0x0 FINETARGET Fine Timer Target value on which a ble_finetgtim_irq must be generated. This timer has a precision of 625us: interrupt is generated only when FINETARGET = BASETIMECNT 0 27 read-write GROSSTIMTGT_REG Gross Timer Target value 0xF4 32 read-write n 0x0 0x0 GROSSTARGET Gross Timer Target value on which a ble_grosstgtim_irq must be generated. This timer has a precision of 10ms: interrupt is generated only when GROSSTARGET[22:0] = BASETIMECNT[26:4] and BASETIMECNT[3:0] = 0. 0 23 read-write INTACK_REG Interrupt acknowledge register 0x18 32 read-write n 0x0 0x0 CRYPTINTACK Encryption engine interrupt acknowledgement bit Software writing 1 acknowledges the Encryption engine interrupt. This bit resets CRYPTINTSTAT and CRYPTINTRAWSTAT flags. Resets at 0 when action is performed 4 5 write-only CSCNTINTACK 625us base time reference interrupt acknowledgment bit Software writing 1 acknowledges the CLKN interrupt. This bit resets CLKINTSTAT and CLKINTRAWSTAT flags. Resets at 0 when action is performed 0 1 write-only ERRORINTACK Error interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt. This bit resets ERRORINTSTAT and ERRORINTRAWSTAT flags. Resets at 0 when action is performed 5 6 write-only EVENTAPFAINTACK End of event / Anticipated Pre-Fetch Abort interrupt acknowledgement bit Software writing 1 acknowledges the End of event / Anticipated Pre-Fetch Abort interrupt. This bit resets EVENTAPFAINTSTAT and EVENTAPFAINTRAWSTAT flags. Resets at 0 when action is performed 8 9 write-only EVENTINTACK End of Event interrupt acknowledgment bit Software writing 1 acknowledges the End of Advertising / Scanning / Connection interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags. Resets at 0 when action is performed 3 4 write-only FINETGTIMINTACK Fine Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Fine Timer interrupt. This bit resets FINETGTIMINTSTAT and FINETGTIMINTRAWSTAT flags. Resets at 0 when action is performed 7 8 write-only GROSSTGTIMINTACK Gross Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Gross Timer interrupt. This bit resets GROSSTGTIMINTSTAT and GROSSTGTIMINTRAWSTAT flags. Resets at 0 when action is performed 6 7 write-only RXINTACK Packet Reception interrupt acknowledgment bit Software writing 1 acknowledges the Rx interrupt. This bit resets RXINTSTAT and RXINTRAWSTAT flags. Resets at 0 when action is performed 1 2 write-only SLPINTACK End of Deep Sleep interrupt acknowledgment bit Software writing 1 acknowledges the End of Sleep Mode interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags. Resets at 0 when action is performed 2 3 write-only SWINTACK SW triggered interrupt acknowledgement bit Software writing 1 acknowledges the SW triggered interrupt. This bit resets SWINTSTAT and SWINTRAWSTAT flags. Resets at 0 when action is performed 9 10 write-only INTCNTL_REG Interrupt controller register 0xC 32 read-write n 0x0 0x0 CRYPTINTMSK Encryption engine Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 4 5 read-write CSCNTDEVMSK CSCNT interrupt mask during event. This bit allows to enable CSCNT interrupt generation during events (i.e. advertising, scanning, initiating, and connection) 0: CSCNT Interrupt not generated during events. 1: CSCNT Interrupt generated during events. 15 16 read-write CSCNTINTMSK 625us Base Time Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 0 1 read-write ERRORINTMSK Error Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 5 6 read-write EVENTAPFAINTMSK End of event / anticipated pre-fetch abort interrupt Mask 0: Interrupt not generated 1: Interrupt generated 8 9 read-write EVENTINTMSK End of event Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 3 4 read-write FINETGTIMINTMSK Fine Target Timer Mask 0: Interrupt not generated 1: Interrupt generated 7 8 read-write GROSSTGTIMINTMSK Gross Target Timer Mask 0: Interrupt not generated 1: Interrupt generated 6 7 read-write RXINTMSK Rx Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 1 2 read-write SLPINTMSK Sleep Mode Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 2 3 read-write SWINTMSK SW triggered interrupt Mask 0: Interrupt not generated 1: Interrupt generated 9 10 read-write INTRAWSTAT_REG Interrupt raw status register 0x14 32 read-write n 0x0 0x0 CRYPTINTRAWSTAT Encryption engine interrupt raw status 0: No Encryption / Decryption interrupt. 1: An Encryption / Decryption interrupt is pending. 4 5 read-only CSCNTINTRAWSTAT 625us base time reference interrupt raw status 0: No 625us Base Time interrupt. 1: A 625us Base Time interrupt is pending. 0 1 read-only ERRORINTRAWSTAT Error interrupt raw status 0: No Error interrupt. 1: An Error interrupt is pending. 5 6 read-only EVENTAPFAINTRAWSTAT End of event / Anticipated Pre-Fetch Abort interrupt raw status 0: No End of Event interrupt. 1: An End of Event interrupt is pending. 8 9 read-only EVENTINTRAWSTAT End of Event interrupt raw status 0: No End of Advertising / Scanning / Connection interrupt. 1: An End of Advertising / Scanning / Connection interrupt is pending. 3 4 read-only FINETGTIMINTRAWSTAT Fine Target Timer Error interrupt raw status 0: No Fine Target Timer interrupt. 1: A Fine Target Timer interrupt is pending. 7 8 read-only GROSSTGTIMINTRAWSTAT Gross Target Timer interrupt raw status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending. 6 7 read-only RXINTRAWSTAT Packet Reception interrupt raw status 0: No Rx interrupt. 1: An Rx interrupt is pending. 1 2 read-only SLPINTRAWSTAT Sleep interrupt raw status 0: No End of Sleep Mode interrupt. 1: An End of Sleep Mode interrupt is pending. 2 3 read-only SWINTRAWSTAT SW triggered interrupt raw status 0: No SW triggered interrupt. 1: A SW triggered interrupt is pending. 9 10 read-only INTSTAT_REG Interrupt status register 0x10 32 read-write n 0x0 0x0 CRYPTINTSTAT Masked Encryption engine interrupt status 0: No Encryption / Decryption interrupt. 1: An Encryption / Decryption interrupt is pending. 4 5 read-only CSCNTINTSTAT Masked 625us base time reference interrupt status 0: No 625us Base Time interrupt. 1: A 625us Base Time interrupt is pending. 0 1 read-only ERRORINTSTAT Masked Error interrupt status 0: No Error interrupt. 1: An Error interrupt is pending. 5 6 read-only EVENTAPFAINTSTAT End of event / Anticipated Pre-Fetch Abort interrupt status 0: No End of Event interrupt. 1: An End of Event interrupt is pending. 8 9 read-only EVENTINTSTAT Masked End of Event interrupt status 0: No End of Advertising / Scanning / Connection interrupt. 1: An End of Advertising / Scanning / Connection interrupt is pending. 3 4 read-only FINETGTIMINTSTAT Masked Fine Target Timer Error interrupt status 0: No Fine Target Timer interrupt. 1: A Fine Target Timer interrupt is pending. 7 8 read-only GROSSTGTIMINTSTAT Masked Gross Target Timer interrupt status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending. 6 7 read-only RXINTSTAT Masked Packet Reception interrupt status 0: No Rx interrupt. 1: An Rx interrupt is pending. 1 2 read-only SLPINTSTAT Masked Sleep interrupt status 0: No End of Sleep Mode interrupt. 1: An End of Sleep Mode interrupt is pending. 2 3 read-only SWINTSTAT SW triggered interrupt status 0: No SW triggered interrupt. 1: A SW triggered interrupt is pending 9 10 read-only RADIOCNTL0_REG Radio interface control register 0x70 32 read-write n 0x0 0x0 RADIOCNTL1_REG Radio interface control register 0x74 32 read-write n 0x0 0x0 XRFSEL Extended radio selection field, Must be set to 2 . 16 21 read-write RADIOCNTL2_REG Radio interface control register 0x78 32 read-write n 0x0 0x0 RADIOCNTL3_REG Radio interface control register 0x7C 32 read-write n 0x0 0x0 RADIOPWRUPDN_REG RX/TX power up/down phase register 0x80 32 read-write n 0x0 0x0 RTRIP_DELAY Defines round trip delay value. This value correspond to the addition of data latency in Tx and data latency in Rx. Value is in us 24 31 read-write RXPWRUP This register holds the length in s of the RX power up phase for the current radio device. Default value is 210us (reset value). Operating range depends on the selected radio. 16 24 read-write TXPWRDN This register extends the length in s of the TX power down phase for the current radio device. Default value is 3us (reset value). Operating range depends on the selected radio. 8 12 read-write TXPWRUP This register holds the length in s of the TX power up phase for the current radio device. Default value is 210us (reset value). Operating range depends on the selected radio. 0 8 read-write RFTESTCNTL_REG RF Testing Register 0xE0 32 read-write n 0x0 0x0 INFINITERX Applicable in RF Test Mode only 0: Normal mode of operation 1: Infinite Rx window 31 32 read-write INFINITETX Applicable in RF Test Mode only 0: Normal mode of operation. 1: Infinite Tx packet / Normal start of a packet but endless payload 15 16 read-write PRBSTYPE Applicable only in Tx/Rx RF Test mode 0: Tx Packet Payload are PRBS9 type 1: Tx Packet Payload are PRBS15 type 13 14 read-write RXPKTCNTEN Applicable in RF Test Mode only 0: Rx packet count disabled 1: Rx packet count enabled, and reported in CS-RXCCMPKTCNT and RFTESTRXSTAT-RXPKTCNT on RF abort command 27 28 read-write TXLENGTH Applicable only for Tx/Rx RF Test mode, and valid when RFTESTCNTL-TXLENGTHSRC = 1 Tx packet length in number of byte 0 9 read-write TXLENGTHSRC Applicable only in Tx/Rx RF Test mode 0: Normal mode of operation: TxDESC-TXADVLEN controls the Tx packet payload size 1: Uses RFTESTCNTL-TXLENGTH packet length (can support up to 512 bytes transmit) 14 15 read-write TXPKTCNTEN Applicable in RF Test Mode only 0: Tx packet count disabled 1: Tx packet count enabled, and reported in CS-TXCCMPKTCNT and RFTESTTXSTAT-TXPKTCNT on RF abort command 11 12 read-write TXPLDSRC Applicable only in Tx/Rx RF Test mode 0: Tx Packet Payload source is the Control Structure 1: Tx Packet Payload are PRBS generator 12 13 read-write RFTESTRXSTAT_REG RF Testing Register 0xE8 32 read-write n 0x0 0x0 RXPKTCNT Reports number of correctly received packet during Test Modes (no sync error, no CRC error). Value is valid if RFTESTCNTL-RXPKTCNTEN is set 0 32 read-write RFTESTTXSTAT_REG RF Testing Register 0xE4 32 read-write n 0x0 0x0 TXPKTCNT Reports number of transmitted packet during Test Modes. Value is valid if RFTESTCNTL-TXPKTCNTEN is set 0 32 read-write RWBLECNTL_REG BLE Control register 0x0 32 read-write n 0x0 0x0 ADVERTFILT_EN Advertising Channels Error Filtering Enable control 0: RW-BLE Core reports all errors to RW-BLE Software 1: RW-BLE Core reports only correctly received packet, without error to RW-BLE Software 9 10 read-write ADVERT_ABORT Abort the current Advertising event when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 25 26 write-only CORR_MODE Defines correlation mode 00: Correlates onto Access Address 01: Correlates onto half preamble and Access Address 10: Correlates onto full preamble and Access Address 11: n/a 12 14 read-write CRC_DSB 0: Normal operation. CRC removed from data stream. 1: CRC stripping disabled on Rx packets, CRC replaced by 0x000 in Tx. 17 18 read-write CRYPT_DSB 0: Normal operation. Encryption / Decryption enabled. 1: Encryption / Decryption disabled. Note that if CS-CRYPT_EN is set, then MIC is generated, and only data encryption is disabled, meaning data sent are plain data. 19 20 read-write HOP_REMAP_DSB 0: Normal operation. Frequency Hopping Remapping algorithm enabled. 1: Frequency Hopping Remapping algorithm disabled 16 17 read-write MASTER_SOFT_RST Reset the complete BLE Core except registers and timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 31 32 write-only MASTER_TGSOFT_RST Reset the timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 30 31 write-only MD_DSB 0: Normal operation of MD bits management 1: Allow a single Tx/Rx exchange whatever the MD bits are. - value forced by SW from Tx Descriptor - value just saved in Rx Descriptor during reception 22 23 read-write NESN_DSB 0: Normal operation of Acknowledge 1: Acknowledge scheme disabled: - value forced by SW from Tx Descriptor - value ignored in Rx, where no NESN error reported. 20 21 read-write REG_SOFT_RST Reset the complete register block, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Note that INT STAT will not be cleared, so the user should also write to BLE_INTACK_REG after the SW Reset 29 30 read-write RFTEST_ABORT Abort the current RF Testing defined as per CS-FORMAT when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Note that when RFTEST_ABORT is requested: 1) In case of infinite Tx, the Packet Controller FSM stops at the end of the current byte in process, and processes accordingly the packet CRC. 2) In case of Infinite Rx, the Packet Controller FSM either stops as the end of the current Packet reception (if Access address has been detected), or simply stop the processing switching off the RF. 26 27 write-only RWBLE_EN 0: Disable RW-BLE Core Exchange Table pre-fetch mechanism. 1: Enable RW-BLE Core Exchange table pre-fetch mechanism. 8 9 read-write RXWINSZDEF Default Rx Window size in us. Used when device: is master connectedperforms its second receipt.0 is not a valid value. Recommended value is 10 (in decimal). 4 8 read-write SCAN_ABORT Abort the current scan window when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 24 25 write-only SN_DSB 0: Normal operation of Sequence number 1: Sequence Number Management disabled: - value forced by SW from Tx Descriptor - value ignored in Rx, where no SN error reported. 21 22 read-write SWINT_REQ Forces the generation of ble_sw_irq when written with a 1, and proper masking is set. Resets at 0 when action is performed. No action happens if it is written with 0. 28 29 write-only SYNCERR Indicates the maximum number of errors allowed to recognize the synchronization word. 0 3 read-write WHIT_DSB 0: Normal operation. Whitening enabled. 1: Whitening disabled. 18 19 read-write RWBLECONF_REG Configuration register 0x8 32 read-write n 0x0 0x0 ADD_WIDTH Value of the RW_BLE_ADDRESS_WIDTH parameter concerted into binary. 24 30 read-only BUSWIDTH Processor bus width: 1: 32 bits 0 1 read-only CLK_SEL Operating Frequency (in MHz) 8 14 read-only COEX 1: WLAN Coexistence mechanism present 3 4 read-only DECIPHER 0: AES deciphering not present 6 7 read-write DMMODE 0: RW-BLE Core is used as a standalone BLE device 5 6 read-only INTMODE 1: Interrupts are trigger level generated, i.e. stays active at 1 till acknowledgement 4 5 read-only RFIF Radio Interface ID 16 23 read-only USECRYPT 1: AES-CCM Encryption block present 1 2 read-only USEDBG 1: Diagnostic port instantiated 2 3 read-only RXMICVAL_REG AES / CCM plain MIC value 0xDC 32 read-write n 0x0 0x0 RXMICVAL AES-CCM plain MIC value. Valid on once MIC has been extracted from Rx packet. 0 32 read-only SAMPLECLK_REG Samples the Base Time Counter 0xFC 32 read-write n 0x0 0x0 SAMP Writing a 1 samples the Base Time Counter value in BASETIMECNT register. Resets at 0 when action is performed. 0 1 write-only SWPROFILING_REG Software Profiling register 0x64 32 read-write n 0x0 0x0 SWPROFVAL Software Profiling register: used by RW-BLE Software for profiling purpose: this value is copied on Diagnostic port 0 32 read-write TIMGENCNTL_REG Timing Generator Register 0xF0 32 read-write n 0x0 0x0 APFM_EN Controls the Anticipated pre-Fetch Abort mechanism 0: Disabled 1: Enabled 31 32 read-write PREFETCHABORT_TIME Defines the instant in s at which immediate abort is required after anticipated pre-fetch abort 16 26 read-write PREFETCH_TIME Defines Exchange Table pre-fetch instant in us 0 9 read-write TXMICVAL_REG AES / CCM plain MIC value 0xD8 32 read-write n 0x0 0x0 TXMICVAL AES-CCM plain MIC value. Valid on when MIC has been calculated (in Tx) 0 32 read-only VERSION_REG Version register 0x4 32 read-write n 0x0 0x0 BUILD BLE Core Build Build number. 0 8 read-only REL BLE Core version Major release number. 16 24 read-only TYP BLE Core Type 24 32 read-only UPG BLE Core upgrade Upgrade number. 8 16 read-only WLNBDEV_REG Devices in white list 0xB8 32 read-write n 0x0 0x0 NBPRIVDEV Number of private devices in the white list. 8 16 read-write NBPUBDEV Number of public devices in the white list. 0 8 read-write WLPRIVADDPTR_REG Start address of private devices list 0xB4 32 read-write n 0x0 0x0 WLPRIVADDPTR Start address pointer of the private devices white list. 0 16 read-write WLPUBADDPTR_REG Start address of public devices list 0xB0 32 read-write n 0x0 0x0 WLPUBADDPTR Start address pointer of the public devices white list. 0 16 read-write CACHE CACHE registers Peripheral_Registers 0x0 0x0 0x54 registers n ASSOCCFG_REG Cache associativity configuration register 0x8 32 read-write n 0x0 0x0 CACHE_ASSOC Cache associativity: 0: 1-way (direct mapped) 1: 2-way 2: 4-way 3: reserved. Note: Flush the cache controller before dynamically decreasing the associativity. 0 2 read-write CTRL1_REG Cache control register 1 0x0 32 read-write n 0x0 0x0 CACHE_FLUSH Writing a '1' into this bit, flushes the contents of the tag memories which invalidates the content of the cache memory. The read of this bit is always '0'. Note: The flushing of the cache TAG memory takes 0x100 or 0x200 HCLK cycles for a Cache Data RAM size of 8 KB resp. 16 KB. 0 1 write-only CACHE_RES1 Reserved. Always keep 0. 1 2 read-write CTRL2_REG Cache control register 2 0x20 32 read-write n 0x0 0x0 CACHE_CGEN 0: Cache controller clock gating is not enabled. 1: Cache controller clock gating is enabled (enabling power saving). Note: This bit must be set to '0' (default) when setting the CACHE_FLUSH bit while executing from other than QSPI FLASH cached or OTP cached, e.g. from Booter or SYSRAM. 10 11 read-write CACHE_LEN Length of QSPI FLASH cacheable memory. (N+1)*64kbyte. N=1 to 512 (Max of 32 Mbyte). Setting CACHE_LEN=0 disables the cache. Note 1: The OTP memory is completely cacheable (when enabled). Note 2: The max. size/length of QSPI FLASH cacheable memory is 16 Mbyte when also OTP is cached. 0 9 read-write CACHE_WEN 0: Cache Data and TAG memory read only. 1: Cache Data and TAG memory read/write. The TAG and Data memory are only updated by the cache controller. There is no HW protection to prevent unauthorized access by the ARM. Note: When accessing the memory mapped Cache Data and TAG memory (for debugging purposes) only 32 bits access is allowed to the Cache Data memory and only 16 bits access is allowed to the Cache TAG memory. 9 10 read-write ENABLE_ALSO_OTP_CACHED Enable also the OTP cacheability when remapped to QSPI FLASH (cached). See also the notes at CACHE_LEN . 11 12 read-write ENABLE_ALSO_QSPIFLASH_CACHED Enable also the QSPI FLASH cacheability when remapped to OTP (cached). See also the notes at CACHE_LEN . 12 13 read-write LNSIZECFG_REG Cache line size configuration register 0x4 32 read-write n 0x0 0x0 CACHE_LINE Cache line size: 0: 8 bytes, 1: 16 bytes, 2: 32 bytes, 3: reserved. Note: Flush the cache just after the dynamic (run-time) reconfiguration of the cache with an 8 bytes cache line size: write the value 01 into the cache control register CACHE_CTRL1_REG just after the write of the value 00 into the cache line size configuration register CACHE_LNSIZECFG_REG. 0 2 read-write MRM_CTRL_REG Cache MRM (Miss Rate Monitor) CONTROL register 0x30 32 read-write n 0x0 0x0 MRM_IRQ_MASK 0: Disables interrupt generation. 1: Enables interrupt generation. Note: The Cache MRM generates a pulse-sensitive interrupt towards the ARM processor, 1 2 read-write MRM_IRQ_THRES_STATUS 0: No interrupt is generated. 1: Interrupt (pulse-sensitive) is generated because the number of cache misses reached the programmed threshold (threshold != 0). 3 4 read-write MRM_IRQ_TINT_STATUS 0: No interrupt is generated. 1: Interrupt (pulse-sensitive) is generated because the time interval counter reached the end (time interval != 0). 2 3 read-write MRM_START 0: Freeze the misses/hits counters and reset the time interval counter to the programmed value in CACHE_MRM_TINT_REG. 1: Enables the counters. Note: In case CACHE_MRM_CTRL_REG[MRM_START] is set to '1' and CACHE_MRM_TINT_REG (!=0) is used for the MRM interrupt generation, the time interval counter counts down (on a fixed reference clock of 16 MHz) until it's '0'. At that time CACHE_MRM_CTRL_REG[MRM_START] will be reset automatically to '0' by the MRM hardware and the MRM interrupt will be generated. 0 1 read-write MRM_HITS_REG Cache MRM (Miss Rate Monitor) HITS register 0x28 32 read-write n 0x0 0x0 MRM_HITS Contains the amount of cache hits. 0 19 read-write MRM_MISSES_REG Cache MRM (Miss Rate Monitor) MISSES register 0x2C 32 read-write n 0x0 0x0 MRM_MISSES Contains the amount of cache misses. 0 18 read-write MRM_THRES_REG Cache MRM (Miss Rate Monitor) THRESHOLD register 0x38 32 read-write n 0x0 0x0 MRM_THRES Defines the threshold to trigger the interrupt generation. See also the description of CACHE_MRM_CTRL_REG[MRM_IRQ_THRES_STATUS]. Note: When MRM_THRES=0 (unrealistic value), no interrupt will be generated. 0 18 read-write MRM_TINT_REG Cache MRM (Miss Rate Monitor) TIME INTERVAL register 0x34 32 read-write n 0x0 0x0 MRM_TINT Defines the time interval for the monitoring in 16 MHz clock cycles. See also the description of CACHE_MRM_CTRL_REG[MRM_IRQ_TINT_STATUS]. Note: When MRM_TINT=0 (unrealistic value), no interrupt will be generated. 0 18 read-write SWD_RESET_REG SWD HW reset control register 0x50 32 read-write n 0x0 0x0 SWD_HW_RESET_REQ 0: default. 1: HW reset request without resetting the SWD and DAP controller. The register is automatically reset with a HW_RESET. This bit can only be accessed by the debugger software and not by the application. 0 1 write-only CHIP_VERSION CHIP_VERSION registers Peripheral_Registers 0x0 0x0 0x5 registers n CHIP_ID1_REG Chip identification register 1. 0x0 8 read-write n 0x0 0x0 CHIP_ID1 First character of device type 680 in ASCII. 0 8 read-only CHIP_ID2_REG Chip identification register 2. 0x1 8 read-write n 0x0 0x0 CHIP_ID2 Second character of device type 680 in ASCII. 0 8 read-only CHIP_ID3_REG Chip identification register 3. 0x2 8 read-write n 0x0 0x0 CHIP_ID3 Third character of device type 680 in ASCII. 0 8 read-only CHIP_REVISION_REG Chip revision register. 0x4 8 read-write n 0x0 0x0 REVISION_ID Chip version, corresponds with type number in ASCII. 0x41 = 'A', 0x42 = 'B' 0 8 read-only CHIP_SWC_REG Software compatibility register. 0x3 8 read-write n 0x0 0x0 CHIP_SWC SoftWare Compatibility code. Integer (default = 0) which is incremented if a silicon change has impact on the CPU Firmware. Can be used by software developers to write silicon revision dependent code. 0 4 read-only COEX COEX registers Peripheral_Registers 0x0 0x0 0x34 registers n BLE_PTI_REG COEX BLE PTI Control Register 0x8 16 read-write n 0x0 0x0 COEX_BLE_PTI This value specifies the PTI value that characterizes the next BLE transaction that will be initiated on the following ble_active positive edge. The value should remain constant during the high period of the ble_active signal. 0 3 read-write CTRL_REG COEX Control Register 0x0 16 read-write n 0x0 0x0 IGNORE_BLE If set to 1 then all BLE requests are ignored by masking the internal ble_active signal. Refer also to IGNORE_BLE_STAT. 15 16 read-write IGNORE_EXT If set to 1 then all EXT requests are ignored by masking the internal ext_act signal ( ext_act is the logical OR of ext_act0 and ext_act1 ). Refer also to IGNORE_EXT_STAT. 13 14 read-write IGNORE_FTDF If set to 1 then all FTDF requests are ignored by masking the internal ftdf_active signal. Refer also to IGNORE_FTDF_STAT. 14 15 read-write PRGING_ARBITER If set to 1 then the current BLE transaction will complete normally and after that no further decision will be taken by the arbiter. The SW must keep this bit to 1 as long as it performs write operations on the COEX_PRI*_REG registers. As soon as the update on the priority registers will be completed, the SW should clear this bit. Note: This bit is updated with the COEX_CLK, so depending on the relationship between the PCLK and COEX_CLK periods a write operation to this bit may be effective in more than one PCLK clock cycles, e.g. when the COEX_CLK rate is slower than the PCLK. 0 1 read-write SEL_BLE_RADIO_BUSY Select the logic driving the BLE core input ble.radio_busy : 0: (decision==BLE) AND rfcu.radio_busy. 1: Hold to 0 . 2: (decision==FTDF) OR (decision==EXT) OR rfcu.radio_busy. 3: (decision==FTDF) OR (decision==EXT). Selection 0 is the default, while selection 2 is the recommended value if the BLE SW supports it. 11 13 read-write SEL_BLE_WLAN_TX_RX If set to 1 then the COEX block will drive the WLAN_TX and WLAN_RX inputs of the BLE core. Otherwise both BLE inputs will be forced to 0 . 10 11 read-write SEL_COEX_DIAG The COEX block can provide internal diagnostic signals by overwriting the BLE diagnostic bus, which is forwarded to GPIO multiplexing. There is no need to program the BLE registers, but only this field and the GPIO PID fields. The encoding of this bitfield is: 0: Don't overwrite any BLE diagnostic signal. 1: Overwrite the BLE Diagnostic bits 2 down to 0: P2[2]: closing sub-state P2[1:0]: decision state 2: Overwrite the BLE Diagnostic bits 5 down to 3: P1[2]: closing sub-state P1[1:0]: decision state 3: Reserved.. 5 7 read-write SEL_FTDF_CCA If set to 1 and the COEX decision is different than FTDF , then the CCA_STAT signal going to FTDF (generated from the radio) will be forced to 1 otherwise the FTDF.CCA_STAT will be driven with the signal generated from the radio. Recommended value for SEL_FTDF_CCA is 1 . 7 8 read-write SEL_FTDF_PTI It controls the source of the FTDF PTI value that the COEX Arbiter will use. If 0 then use the COEX_FTDF_PTI_REG. If 1 then use the PTI value provided by the FTDF core. 8 9 read-write SMART_ACT_IMPL Controls the behavior of the SMART_ACT (and SMART_PRI as a consequence). If SMART_ACT_IMPL= 0 then if any BLE or FTDF MAC request is active then SMART_ACT will be asserted. SMART_ACT will actually be the logical OR of ble_active and ftdf_active internal signals. SMART_ACT will be asserted regardless the decision of the Arbiter to allow or disallow the access to the on-chip radio from the active MAC(s). if SMART_ACT_IMPL= 1 then if the Arbiter's decision is to allow EXTernal MAC, then keep SMART_ACT to 0 , otherwise follow the implementation of SMART_ACT_IMPL= 0 . 4 5 read-write DIAG_REG COEX Diagnostic Monitor Register 0xC 16 read-write n 0x0 0x0 COEX_DIAG_MON provides the current value of the diagnostic bus forwarded to the GPIO multiplexing (named PPA). Refer to the Pxy_MODE_REG[PID] value BLE_DIAG. 0 16 read-only FTDF_PTI_REG COEX FTDF PTI Control Register 0xA 16 read-write n 0x0 0x0 COEX_FTDF_PTI This value specifies the PTI value that characterizes the next FTDF transaction that will be initiated on the following ftdf_active positive edge. The value should remain constant during the high period of the ftdf_active signal. Refer also to bitfield COEX_CTRL_REG.SEL_FTDF_PTI. 0 3 read-write INT_MASK_REG COEX Interrupt Mask Register 0x4 16 read-write n 0x0 0x0 COEX_IRQ_MASK If set to 1 then sent an COEX_IRQ event to CPU as long as COEX_INT_STAT_REG[COEX_IRQ_STAT] is 1 . If cleared then don't sent any IRQ event to CPU. 0 1 read-write COEX_IRQ_ON_BLE_ACTIVE_F If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_BLE_ACTIVE_F] will cause COEX_IRQ_STAT to be set also to 1 . 10 11 read-write COEX_IRQ_ON_BLE_ACTIVE_R If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_BLE_ACTIVE_R] will cause COEX_IRQ_STAT to be set also to 1 . 9 10 read-write COEX_IRQ_ON_CLOSING_BRK If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_CLOSING_BRK] will cause COEX_IRQ_STAT to be set also to 1 . 13 14 read-write COEX_IRQ_ON_DECISION_SW If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_DECISION_SW] will cause COEX_IRQ_STAT to be set also to 1 . 15 16 read-write COEX_IRQ_ON_EXT_ACT_F If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_EXT_ACT_F] will cause COEX_IRQ_STAT to be set also to 1 . 6 7 read-write COEX_IRQ_ON_EXT_ACT_R If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_EXT_ACT_R] will cause COEX_IRQ_STAT to be set also to 1 . 5 6 read-write COEX_IRQ_ON_FTDF_ACTIVE_F If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_FTDF_ACTIVE_F] will cause COEX_IRQ_STAT to be set also to 1 . 8 9 read-write COEX_IRQ_ON_FTDF_ACTIVE_R If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_FTDF_ACTIVE_R] will cause COEX_IRQ_STAT to be set also to 1 . 7 8 read-write COEX_IRQ_ON_RADIO_BUSY_F If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_RADIO_BUSY_F] will cause COEX_IRQ_STAT to be set also to 1 . 12 13 read-write COEX_IRQ_ON_RADIO_BUSY_R If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_RADIO_BUSY_R] will cause COEX_IRQ_STAT to be set also to 1 . 11 12 read-write COEX_IRQ_ON_SMART_ACT_F If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_SMART_ACT_F] will cause COEX_IRQ_STAT to be set also to 1 . 2 3 read-write COEX_IRQ_ON_SMART_ACT_R If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_SMART_ACT_R] will cause COEX_IRQ_STAT to be set also to 1 . 1 2 read-write COEX_IRQ_ON_SMART_PRI_F If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_SMART_PRI_F] will cause COEX_IRQ_STAT to be set also to 1 . 4 5 read-write COEX_IRQ_ON_SMART_PRI_R If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_SMART_PRI_R] will cause COEX_IRQ_STAT to be set also to 1 . 3 4 read-write COEX_IRQ_ON_START_MID If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_START_MID] will cause COEX_IRQ_STAT to be set also to 1 . 14 15 read-write INT_STAT_REG COEX Interrupt Status Register 0x6 16 read-write n 0x0 0x0 COEX_IRQ_ON_BLE_ACTIVE_F IRQ event on falling edge of BLE_ACTIVE internal signal. 10 11 read-only COEX_IRQ_ON_BLE_ACTIVE_R IRQ event on rising edge of BLE_ACTIVE internal signal. 9 10 read-only COEX_IRQ_ON_CLOSING_BRK IRQ if while entering into closing sub-state, the TX_EN or RX_EN are active. This event signals a potential break of a transmission or reception. 13 14 read-only COEX_IRQ_ON_DECISION_SW IRQ event when the decision switches to a new MAC. It ignores the intermediate transitions to DECISION==NONE. Note that after a Radio domain reset, the first transition of the decision to any MAC will also trigger this event. 15 16 read-only COEX_IRQ_ON_EXT_ACT_F RQ event on falling edge of EXT_ACT. 6 7 read-only COEX_IRQ_ON_EXT_ACT_R IRQ event on rising edge of EXT_ACT. 5 6 read-only COEX_IRQ_ON_FTDF_ACTIVE_F IRQ event on falling edge of FTDF_ACTIVE internal signal. 8 9 read-only COEX_IRQ_ON_FTDF_ACTIVE_R IRQ event on rising edge of FTDF_ACTIVE internal signal. 7 8 read-only COEX_IRQ_ON_RADIO_BUSY_F IRQ event on falling edge of RADIO_BUSY. 12 13 read-only COEX_IRQ_ON_RADIO_BUSY_R IRQ event on rising edge of RADIO_BUSY. 11 12 read-only COEX_IRQ_ON_SMART_ACT_F IRQ event on falling edge of SMART_ACT. 2 3 read-only COEX_IRQ_ON_SMART_ACT_R IRQ event on rising edge of SMART_ACT. 1 2 read-only COEX_IRQ_ON_SMART_PRI_F IRQ event on falling edge of SMART_PRI. 4 5 read-only COEX_IRQ_ON_SMART_PRI_R IRQ event on rising edge of SMART_PRI. 3 4 read-only COEX_IRQ_ON_START_MID IRQ event when the decision switches to a MAC, while the TX_EN or RX_EN of this MAC are high. This event signals a potential break of a transmission or reception. 14 15 read-only COEX_IRQ_STAT For each COEX_IRQ_ON_* bitfield of COEX_INT_STAT_REG the corresponding mask is applied and afterwards all the intermediate results are combined with a logical OR in order to produce the COEX_IRQ_STAT bitfield. If furthermore the COEX_INT_MASK_REG[COEX_IRQ_MASK] is set to 1 , then a COEX_IRQ signal will be forwarded to the CPU. Note: Each COEX_IRQ_ON_* bitfield of COEX_INT_STAT_REG will be set to 1 on the detection of the corresponding event and will be cleared to 0 on the read of COEX_INT_STAT_REG. The automated clear may delay a couple of PCLK cycles, depending on the relationship between PCLK and COEX_CLK. 0 1 read-only PRI10_REG COEX Priority Register 0x24 16 read-write n 0x0 0x0 COEX_PRI_MAC Refer to COEX_PRI1_REG. 3 5 read-write COEX_PRI_PTI Refer to COEX_PRI1_REG. 0 3 read-write PRI11_REG COEX Priority Register 0x26 16 read-write n 0x0 0x0 COEX_PRI_MAC Refer to COEX_PRI1_REG. 3 5 read-write COEX_PRI_PTI Refer to COEX_PRI1_REG. 0 3 read-write PRI12_REG COEX Priority Register 0x28 16 read-write n 0x0 0x0 COEX_PRI_MAC Refer to COEX_PRI1_REG. 3 5 read-write COEX_PRI_PTI Refer to COEX_PRI1_REG. 0 3 read-write PRI13_REG COEX Priority Register 0x2A 16 read-write n 0x0 0x0 COEX_PRI_MAC Refer to COEX_PRI1_REG. 3 5 read-write COEX_PRI_PTI Refer to COEX_PRI1_REG. 0 3 read-write PRI14_REG COEX Priority Register 0x2C 16 read-write n 0x0 0x0 COEX_PRI_MAC Refer to COEX_PRI1_REG. 3 5 read-write COEX_PRI_PTI Refer to COEX_PRI1_REG. 0 3 read-write PRI15_REG COEX Priority Register 0x2E 16 read-write n 0x0 0x0 COEX_PRI_MAC Refer to COEX_PRI1_REG. 3 5 read-write COEX_PRI_PTI Refer to COEX_PRI1_REG. 0 3 read-write PRI16_REG COEX Priority Register 0x30 16 read-write n 0x0 0x0 COEX_PRI_MAC Refer to COEX_PRI1_REG. 3 5 read-write COEX_PRI_PTI Refer to COEX_PRI1_REG. 0 3 read-write PRI17_REG COEX Priority Register 0x32 16 read-write n 0x0 0x0 COEX_PRI_MAC Refer to COEX_PRI1_REG. 3 5 read-write COEX_PRI_PTI Refer to COEX_PRI1_REG. 0 3 read-write PRI1_REG COEX Priority Register 0x12 16 read-write n 0x0 0x0 COEX_PRI_MAC Specifies the MAC that has been assigned with the specific priority level. The MAC encoding follows the COEX_DECISION bitfield encoding. 3 5 read-write COEX_PRI_PTI The priority level specified by this register will be applied to the packets coming from the MAC specified by the COEX_PRI_MAC bitfield and characterized with the PTI value specified by the COEX_PRI_PTI bitfield. 0 3 read-write PRI2_REG COEX Priority Register 0x14 16 read-write n 0x0 0x0 COEX_PRI_MAC Refer to COEX_PRI1_REG. 3 5 read-write COEX_PRI_PTI Refer to COEX_PRI1_REG. 0 3 read-write PRI3_REG COEX Priority Register 0x16 16 read-write n 0x0 0x0 COEX_PRI_MAC Refer to COEX_PRI1_REG. 3 5 read-write COEX_PRI_PTI Refer to COEX_PRI1_REG. 0 3 read-write PRI4_REG COEX Priority Register 0x18 16 read-write n 0x0 0x0 COEX_PRI_MAC Refer to COEX_PRI1_REG. 3 5 read-write COEX_PRI_PTI Refer to COEX_PRI1_REG. 0 3 read-write PRI5_REG COEX Priority Register 0x1A 16 read-write n 0x0 0x0 COEX_PRI_MAC Refer to COEX_PRI1_REG. 3 5 read-write COEX_PRI_PTI Refer to COEX_PRI1_REG. 0 3 read-write PRI6_REG COEX Priority Register 0x1C 16 read-write n 0x0 0x0 COEX_PRI_MAC Refer to COEX_PRI1_REG. 3 5 read-write COEX_PRI_PTI Refer to COEX_PRI1_REG. 0 3 read-write PRI7_REG COEX Priority Register 0x1E 16 read-write n 0x0 0x0 COEX_PRI_MAC Refer to COEX_PRI1_REG. 3 5 read-write COEX_PRI_PTI Refer to COEX_PRI1_REG. 0 3 read-write PRI8_REG COEX Priority Register 0x20 16 read-write n 0x0 0x0 COEX_PRI_MAC Refer to COEX_PRI1_REG. 3 5 read-write COEX_PRI_PTI Refer to COEX_PRI1_REG. 0 3 read-write PRI9_REG COEX Priority Register 0x22 16 read-write n 0x0 0x0 COEX_PRI_MAC Refer to COEX_PRI1_REG. 3 5 read-write COEX_PRI_PTI Refer to COEX_PRI1_REG. 0 3 read-write STAT_REG COEX Status Register 0x2 16 read-write n 0x0 0x0 COEX_DECISION Decision values: 0: Decision is NONE. 1: Decision is BLE. 2: Decision is FTDF. 3: Decision is EXT. Note: If 0 (i.e. decision is NONE) then no MAC will have access to the on-chip radio. As a consequence, the SMART_PRI signal will stay low, since no on-chip (SMART) MAC will have priority. Note: The decision NONE will be held as long as there is no *_active internal signal from BLE, FTDF or EXT. Also, if in programming state and the last transaction has been finished, then the decision will be held also to NONE. Note: While in programming mode, the COEX_PRIx_REGs are considered as invalid, which means that no new decision can be taken. 5 7 read-only COEX_DECISION_CLOSING Provides the value of the CLOSING substate. 7 8 read-only COEX_DECISION_PTR Provides the number x of the COEX_PRIx_REG that win the last arbitration cycle. If 0 then it is a null pointer, pointing to no COEX_PRIx_REG. 0 5 read-only COEX_RADIO_BUSY Current state of RADIO_BUSY signal generated from RFCU, which is the logical OR among all Radio DCFs. Note that the arbiter will process this value with one COEX clock cycle delay. 12 13 read-only EXT_ACT0 Current state of the pin. 10 11 read-only EXT_ACT1 Current state of the pin. 11 12 read-only IGNORE_BLE_STAT This signal is constantly 1 on FTDF-only chips. If set to 1 then all BLE requests are ignored by masking immediately the request signal from the BLE. In more detail, the internal signal ble_active is the logical AND of this bitfield and the ble.event_in_process . 15 16 read-only IGNORE_EXT_STAT If set to 1 then all EXT requests are ignored by masking immediately the request signal from the external MAC. In more detail, the internal signal ext_active is the logical AND of this bitfield and the ext_act . 13 14 read-only IGNORE_FTDF_STAT This signal is constantly 1 on BLE-only chips. If set to 1 then all FTDF requests are ignored by masking immediately the request signal from the FTDF. In more detail, the internal signal ftdf_active is the logical AND of this bitfield and the ftdf.phy_en . 14 15 read-only SMART_ACT Current state of the pin. 8 9 read-only SMART_PRI Current state of the pin. 9 10 read-only CRG_PER CRG_PER registers Peripheral_Registers 0x0 0x0 0x4C registers n CLK_PER_REG Peripheral divider register 0x4 16 read-write n 0x0 0x0 ADC_CLK_SEL Selects the clock source 1 = DIV1 clock 0 = DIVN clock 11 12 read-write I2C_CLK_SEL Selects the clock source 1 = DIV1 clock 0 = DIVN clock 9 10 read-write I2C_ENABLE Enables the clock 2 3 read-write IR_CLK_ENABLE Enables the clock 4 5 read-write KBSCAN_CLK_SEL Selects the clock source 1 = DIV1 clock 0 = DIVN clock 10 11 read-write KBSCAN_ENABLE Enables the clock 5 6 read-write QUAD_ENABLE Enables the clock 3 4 read-write SPI_CLK_SEL Selects the clock source 1 = DIV1 clock 0 = DIVN clock 8 9 read-write SPI_ENABLE Enables the clock 1 2 read-write UART_ENABLE Enables the clock 0 1 read-write PCM_DIV_REG PCM divider and enables 0x40 16 read-write n 0x0 0x0 CLK_PCM_EN Enable for the internally generated PCM clock The PCM_DIV must be set before or together with CLK_PCM_EN. 12 13 read-write PCM_DIV PCM clock divider 0 12 read-write PCM_SRC_SEL Selects the clock source 1 = DIV1 clock 0 = DIVN clock 13 14 read-write PCM_FDIV_REG PCM fractional division register 0x42 16 read-write n 0x0 0x0 PCM_FDIV These bits define the fractional division part of the PCM clock. The left most '1' defines the denominator, the number of '1' bits define the numerator. E.g. 0x0110 means 2/9, with a distribution of 1.0001.0000 0xfeee means 13/16, with a distribution of 1111.1110.1110.1110 0 16 read-write PDM_DIV_REG PDM divider and enables 0x44 16 read-write n 0x0 0x0 CLK_PDM_EN Enable for the internally generated PDM clock The PDM_DIV must be set before or together with CLK_PDM_EN. 8 9 read-write PDM_DIV PDM clock divider 0 8 read-write PDM_MASTER_MODE Master mode selection 0: slave mode 1: master mode 9 10 read-write SRC_DIV_REG SRC divider and enables 0x46 16 read-write n 0x0 0x0 CLK_SRC_EN Enable for the internally generated SRC clock The SRC_DIV must be set before or together with CLK_SRC_EN. 8 9 read-write SRC_DIV SRC clock divider 0 8 read-write USBPAD_REG USB pads control register 0x4A 16 read-write n 0x0 0x0 USBPAD_EN 0: The power for the USB PHY and USB pads is switched on when the USB is enabled. 1: The power for the USB PHY and USB pads is forced on. 0 1 read-write USBPHY_FORCE_SW1_OFF 0: Pull up resistor SW1 is controlled by the USB controller. It is off when the USB is not enabled. 1: Force the pull up resistor on USBP to be switched off. 1 2 read-write USBPHY_FORCE_SW2_ON 0: Pull up resistor SW2 is controlled by the USB controller. It is off when the USB is not enabled. 1: Force the pull up resistor on USBP to be 2.3Kohm 2 3 read-write CRG_TOP CRG_TOP registers Peripheral_Registers 0x0 0x0 0x52 registers n ANA_STATUS_REG status bit of analog (power management) circuits 0x2A 16 read-write n 0x0 0x0 BANDGAP_OK bandgap = ok 6 7 read-only COMP_1V8_FLASH_HIGH VDD1V8 > 1.7V 14 15 read-only COMP_1V8_PA_HIGH VDD1V8P > 1.7V 15 16 read-only COMP_V33_HIGH V33 > 1.7V 13 14 read-only COMP_VBAT_OK vbat > 1.7V 1 2 read-only COMP_VBUS_HIGH VBUS > 4V 11 12 read-only COMP_VBUS_LOW VBUS > 3.4V 12 13 read-only COMP_VDD_HIGH VDD > 1.13V 7 8 read-only LDO_1V8_FLASH_OK ldo_vdd1v8 = ok 10 11 read-only LDO_1V8_PA_OK ldo_vdd1v8P = ok 9 10 read-only LDO_CORE_OK ldo_core = ok 8 9 read-only LDO_RADIO_OK ldo_radio = ok 0 1 read-only LDO_SUPPLY_USB_OK ldo_supply_usb = ok 5 6 read-only LDO_SUPPLY_VBAT_OK ldo_supply_vbat =ok 4 5 read-only NEWBAT new battery has been detected 3 4 read-only VBUS_AVAILABLE vbus is available (vbus > vbat) 2 3 read-only BANDGAP_REG bandgap trimming 0x28 16 read-write n 0x0 0x0 BGR_ITRIM Current trimming for bias 5 10 read-write BGR_TRIM Trim register for bandgap 0 5 read-write BYPASS_COLD_BOOT_DISABLE 0x1 -> Switch to LDO_SUPPLY_USB on vbus_available and vbus_high and wokenup (SET to 0x1 after boot) 0x0 -> Switch to LDO_SUPPLY_USB on vbus_available 14 15 read-write LDO_SLEEP_TRIM 0x4 --> 1120 mV 0x5 --> 1089 mV 0x6 --> 1058 mV 0x7 --> 1030 mV 0x0 --> 1037 mV 0x1 --> 1005 mV 0x2 --> 978 mV 0x3 --> 946 mV 0x8 --> 952 mV 0x9 --> 918 mV 0xA --> 889 mV 0xB --> 861 mV 0xC --> 862 mV 0xD --> 828 mV 0xE --> 798 mV 0xF --> 770 mV These values are from simulation and vary over corners 10 14 read-write BOD_CTRL2_REG Brown Out Detection control register 0x36 16 read-write n 0x0 0x0 BOD_1V8_FLASH_EN 1V8 Flash BOD Enable 4 5 read-write BOD_1V8_PA_EN 1V8 PA BOD Enable 3 4 read-write BOD_RESET_EN Generate a chip reset on BOD event 0 1 read-write BOD_V33_EN V33 BOD Enable 2 3 read-write BOD_VBAT_EN VBAT BOD Enable 5 6 read-write BOD_VDD_EN VDD BOD Enable 1 2 read-write BOD_CTRL_REG Brown Out Detection control register 0x34 16 read-write n 0x0 0x0 BOD_1V8_FLASH_TRIM 1V8 Flash BOD Trimming bits 2 4 read-write BOD_1V8_PA_TRIM 1V8 PA BOD Trimming bits 4 6 read-write BOD_V33_TRIM V33 BOD Trimming bits 6 8 read-write BOD_VDD_LVL VDD BOD Level 0=700mV 1=700mV 3=800mV 7=1.05V 8 11 read-write BOD_VDD_TRIM VDD BOD Trimming bits 0 2 read-write BOD_STATUS_REG Brown Out Detection status register 0x38 16 read-write n 0x0 0x0 BOD_1V8_FLASH_LOW Indicates V18_Flash > V18_Flash_Trigger 2 3 read-write BOD_1V8_PA_LOW Indicates V18_PA > V18_PA_Trigger 1 2 read-write BOD_V33_LOW Indicates V33 > V33_Trigger 3 4 read-write BOD_VBAT_LOW Indicates VBAT > VBAT_Trigger 4 5 read-write BOD_VDD_LOW Indicates VDD > VDD_Trigger 0 1 read-write CLK_16M_REG 16 MHz RC and xtal oscillator register 0x22 16 read-write n 0x0 0x0 RC16M_ENABLE Enables the 16MHz RC oscillator 0 1 read-write RC16M_STARTUP_DISABLE Gates the RC16M enable from the startup block. The enable from the clksel and CLK_16M_REG[0] are not gated by this bit. 15 16 read-write RC16M_TRIM 0000 = lowest frequency 1111 = highest frequency 1 5 read-write XTAL16_AMP_TRIM sets xtal amplitude, 0 is minimum, 101 is maximum 10 13 read-write XTAL16_CUR_SET start-up current for the 16MHz XTAL oscillator. 000 is minimum, 110 is maximum. 5 8 read-write XTAL16_EXT_CLK_ENABLE Uses the signal on the xtal-p pin as the clock, the xtal-n pin can float. 9 10 read-write XTAL16_HPASS_FLT_EN enables high pass filter 14 15 read-write XTAL16_MAX_CURRENT Uses the maximum current, for testing purpose only. 8 9 read-write XTAL16_SPIKE_FLT_BYPASS bypasses spikefilter 13 14 read-write CLK_32K_REG 32 kHz oscillator register 0x20 16 read-write n 0x0 0x0 RC32K_ENABLE Enables the 32kHz RC oscillator 7 8 read-write RC32K_TRIM 0000 = lowest frequency 0111 = default 1111 = highest frequency 8 12 read-write XTAL32K_CUR Bias current for the 32kHz XTAL oscillator. 0000 is minimum, 1111 is maximum, 0011 is default. For each application there is an optimal setting for which the start-up behavior is optimal 3 7 read-write XTAL32K_DISABLE_AMPREG Setting this bit disables the amplitude regulation of the XTAL32kHz oscillator. Set this bit to '1' for an external clock to XTAL32Kp Keep this bit '0' with a crystal between XTAL32Kp and XTAL32Km 12 13 read-write XTAL32K_ENABLE Enables the 32kHz XTAL oscillator 0 1 read-write XTAL32K_RBIAS Setting for the bias resistor. 00 is maximum, 11 is minimum. Prefered setting will be provided by Dialog 1 3 read-write CLK_AMBA_REG HCLK, PCLK, divider and clock gates 0x0 16 read-write n 0x0 0x0 AES_CLK_ENABLE Clock enable for AES crypto block 6 7 read-write ECC_CLK_ENABLE Clock enable for ECC block 7 8 read-write HCLK_DIV AHB interface and microprocessor clock. Source clock divided by: 000 = divide hclk by 1 001 = divide hclk by 2 010 = divide hclk by 4 011 = divide hclk by 8 1xx = divide hclk by 16 0 3 read-write OTP_ENABLE Clock enable for OTP controller 9 10 read-write PCLK_DIV APB interface clock, Cascaded with HCLK: 00 = divide hclk by 1 01 = divide hclk by 2 10 = divide hclk by 4 11 = divide hclk by 8 4 6 read-write QSPI_DIV QSPI divider 00 = divide by 1 01 = divide by 2 10 = divide by 4 11 = divide by 8 10 12 read-write QSPI_ENABLE Clock enable for QSPI controller 12 13 read-write TRNG_CLK_ENABLE Clock enable for TRNG block 8 9 read-write CLK_CTRL_REG Clock control register 0xA 16 read-write n 0x0 0x0 CLK32K_SOURCE Sets the clock source of the LowerPower clock '00': 32 Khz RC Oscillator '01': RCX Oscillator '10': XTAL32kHz, when using an external crystal i.c.w. the internal oscillator (set P20 and P21 to FUNC_XTAL32) '11': XTAL32kHz, when an external generator or MCU applies a square wave on P20 (set P20 to FUNC_GPIO) 8 10 read-write DIVN_SYNC_LEVEL Level of the RF divider to sync with in case XTAL32_MODE is set. This is used to align the internal DIVN clock XTAL@32MHz divided by 2 with the radio clock 7 8 read-write DIVN_XTAL32M_MODE Enables the DIVN divide-by-2, in case of a 32 MHz crystal (See also XTAL32M_MODE), to keep the DIVN clock at 16 MHz. 6 7 read-write PLL_DIV2 Divides the PLL clock by 2 before being used 5 6 read-write RUNNING_AT_32K Indicates that either the RC32k or XTAL32k is being used as clock 12 13 read-only RUNNING_AT_PLL96M Indicates that the PLL96MHz clock is used as clock, and may not be switched off 15 16 read-only RUNNING_AT_RC16M Indicates that the RC16M clock is used as clock 13 14 read-only RUNNING_AT_XTAL16M Indicates that the XTAL16M clock is used as clock, and may not be switched off 14 15 read-only SYS_CLK_SEL Selects the clock source. 0x0 : XTAL16M (check the XTAL16_TRIM_READY bit!!) 0x1 : RC16M 0x2 : The Low Power clock is used 0x3 : The PLL96Mhz is used 0 2 read-write USB_CLK_SRC Selects the USB source clock 0 : PLL clock, divided by 2 1 : HCLK 4 5 read-write XTAL16M_DISABLE Setting this bit instantaneously disables the 16 MHz crystal oscillator. This bit may not be set to '1' when RUNNING_AT_XTAL16M is '1' to prevent deadlock. After resetting this bit, wait for XTAL16_TRIM_READY to become '1' before switching to XTAL16 clock source. 2 3 read-write XTAL32M_MODE Enables dividers in the XTAL for both the RF and the BB PLL. 3 4 read-write CLK_FREQ_TRIM_REG Xtal frequency trimming register. 0x2 16 read-write n 0x0 0x0 COARSE_ADJ Xtal frequency course trimming register. 0x0 = lowest frequency 0x7 = highest frequencyIncrement or decrement the binary value with 1. Wait approximately 200usec to allow the adjustment to settle. 8 11 read-write FINE_ADJ Xtal frequency fine trimming register.0x00 = lowest frequency 0xFF = highest frequency 0 8 read-write CLK_RADIO_REG Radio PLL control register 0x8 16 read-write n 0x0 0x0 BLE_DIV Division factor for BLE core blocks, having as reference the DIVN clock: 00 = Divide by 1 01 = Divide by 2 10 = Divide by 4 11 = Divide by 8 The programmed frequency should not be lower than 8MHz, not faster than 16MHz and not faster than the programmed CPU clock frequency. Refer also to BLE_CNTL2_REG[BLE_CLK_SEL]. 4 6 read-write BLE_ENABLE Enable the BLE core clocks. When the BLE system clock is disabled, either due to the CLK_RADIO_REG[BLE_ENABLE] or due to the PMU_CTRL_REG[BLE_SLEEP], then any access to the BLE Register file will issue a hard fault to the CPU. 7 8 read-write BLE_LP_RESET Reset for the BLE LP timer 6 7 read-write FTDF_MAC_DIV Division factor for FTCF MAC clock, relative to the DIVN clock 00 = Divide by 1 01 = Divide by 2 10 = Divide by 4 11 = Divide by 8 It should always be set to 00. 8 10 read-write FTDF_MAC_ENABLE Enable the FTDF MAC core clocks 11 12 read-write RFCU_DIV Division factor for RF Control Unit 0x0 = divide by 1 0x1 = divide by 2 0x2 = divide by 4 0x3 = divide by 8 The programmed frequency must be exactly 8MHz. 0 2 read-write RFCU_ENABLE Enable the RF control Unit clock 3 4 read-write CLK_RCX20K_REG RCX-oscillator control register 0x24 16 read-write n 0x0 0x0 RCX20K_BIAS Bias control 8 10 read-write RCX20K_ENABLE Enable the RCX oscillator 11 12 read-write RCX20K_LOWF Extra low frequency 10 11 read-write RCX20K_NTC Temperature control 4 8 read-write RCX20K_TRIM 0000 = lowest frequency 0111 = default 1111 = highest frequency 0 4 read-write CLK_TMR_REG Clock control for the timers 0xC 16 read-write n 0x0 0x0 BREATH_ENABLE Enables the clock 12 13 read-write P06_TMR1_PWM_MODE Maps Timer1_pwm onto P0_6, when DEBUGGER_EN = '0'. This state is preserved during deep sleep, to allow PWM5 output on the pad during deep sleep. 14 15 read-write TMR0_CLK_SEL Selects the clock source 1 = DIV1 clock 0 = DIVN clock 3 4 read-write TMR0_DIV Division factor for Timer 0x0 = divide by 1 0x1 = divide by 2 0x2 = divide by 4 0x3 = divide by 8 0 2 read-write TMR0_ENABLE Enable timer clock 2 3 read-write TMR1_CLK_SEL Selects the clock source 1 = DIV1 clock 0 = DIVN clock 7 8 read-write TMR1_DIV Division factor for Timer 0x0 = divide by 1 0x1 = divide by 2 0x2 = divide by 4 0x3 = divide by 8 4 6 read-write TMR1_ENABLE Enable timer clock 6 7 read-write TMR2_CLK_SEL Selects the clock source 1 = DIV1 clock 0 = DIVN clock 11 12 read-write TMR2_DIV Division factor for Timer 0x0 = divide by 1 0x1 = divide by 2 0x2 = divide by 4 0x3 = divide by 8 8 10 read-write TMR2_ENABLE Enable timer clock 10 11 read-write WAKEUPCT_ENABLE Enables the clock 13 14 read-write LDO_CTRL1_REG LDO control register 0x3A 16 read-write n 0x0 0x0 LDO_CORE_CURLIM Sets the current limit of LDO_CORE 00 = Current limiter disabled 01 = 8 mA 10 = 60 mA 11 = 80 mA 0 2 read-write LDO_CORE_SETVDD Sets the output voltage of LDO_CORE 000 = 1.20 V 001 = 1.15 V 010 = 1.10 V 011 = 1.05 V 1XX = 1.32 V 8 11 read-write LDO_RADIO_ENABLE Enables (1) or disables (0) LDO_RADIO (V14) For fast XTAL startup, this bit may be kept to '1' during deep sleep. The LDO is switched off automatically when in deep sleep, and enabled when waking up. 14 15 read-write LDO_RADIO_SETVDD Sets the output voltage of LDO_RADIO 000 = 1.30 V 001 = 1.35 V 010 = 1.40 V 011 = 1.45 V 1XX = 1.50 V 11 14 read-write LDO_SUPPLY_USB_LEVEL Sets the output voltage of LDO_SUPPLY_USB 00 = 2.40 V 01 = 3.30 V 10 = 3.45 V 11 = 3.60 V 6 8 read-write LDO_SUPPLY_VBAT_LEVEL Sets the output voltage of LDO_SUPPLY_VBAT 00 = 2.40 V 01 = 3.30 V 10 = 3.45 V 11 = 3.60 V 4 6 read-write LDO_VBAT_RET_LEVEL Sets the output voltage of LDO_VBAT_RET 00 = 2.40 V 01 = 3.30 V 10 = 3.45 V 11 = 3.60 V 2 4 read-write LDO_CTRL2_REG LDO control register 0x3C 16 read-write n 0x0 0x0 LDO_1V2_ON Enables (1) or disables (0) LDO_CORE 0 1 read-write LDO_1V8_FLASH_ON Enables (1) or disables (0) LDO_1V8_FLASH 2 3 read-write LDO_1V8_FLASH_RET_DISABLE Disables (1) or enables (0) LDO_1V8_FLASH_RET 5 6 read-write LDO_1V8_PA_ON Enables (1) or disables (0) LDO_1V8_PA 3 4 read-write LDO_1V8_PA_RET_DISABLE Disables (1) or enables (0) LDO_1V8_PA_RET 6 7 read-write LDO_3V3_ON Enables (1) or disables (0) LDO_SUPPLY_VBAT and LDO_SUPPLY_USB 1 2 read-write LDO_VBAT_RET_DISABLE Disables (1) or enables (0) LDO_VBAT_RET 4 5 read-write PMU_CTRL_REG Power Management Unit control register 0x10 16 read-write n 0x0 0x0 BLE_SLEEP Put the BLE in powerdown. When the BLE system clock is disabled, either due to the CLK_RADIO_REG[BLE_ENABLE] or due to the PMU_CTRL_REG[BLE_SLEEP], then any access to the BLE Register file will issue a hard fault to the CPU. 2 3 read-write ENABLE_CLKLESS Selects the clockless sleep mode. Wakeup is done asynchronously. When set to '1', the lp_clk is stopped during deep sleep, until a wakeup event (not debounced) is detected by the WAKUPCT block. When set to '0', the lp_clk continues running, so the MAC counters keep on running. This mode cannot be combined with regulated sleep, so keep SLEEP_TIMER=0 when using ENABLE_CLKLESS. 13 14 read-write FTDF_SLEEP Put the FTDF in powerdown 3 4 read-write OTP_COPY_DIV Sets the HCLK division during OTP mirroring 6 8 read-write PERIPH_SLEEP Put all peripherals (I2C, UART, SPI, ADC) in powerdown 0 1 read-write RADIO_SLEEP Put the digital part of the radio in powerdown 1 2 read-write RESET_ON_WAKEUP Perform a Hardware Reset after waking up. Booter will be started. 5 6 read-write RETAIN_CACHE Selects the retainability of the cache block during deep sleep. '1' is retainable, '0' is power gated 14 15 read-write RETAIN_ECCRAM Selects the retainability of the ECC RAM during deep sleep. '1' is retainable, '0' is power gated 15 16 read-write RETAIN_RAM Select the retainability of the 5 system memory RAM macros during deep sleep. '1' is retainable, '0' is power gated (4) is SYSRAM5 (3) is SYSRAM4 (2) is SYSRAM3 (1) is SYSRAM2 (0) is SYSRAM1 8 13 read-write SLEEP_TIMER_REG Timer for regulated sleep 0x3E 16 read-write n 0x0 0x0 SLEEP_TIMER Defines the amount of ticks of the sleep clock between enabling the bandgap for re-charging the retention LDOs. This value depends on the load and should be calibrated on a per application basis.If set to 0, no recharging cycle will happen at all. Keep this value to 0 (no recharging) when using the clockless sleep. 0 16 read-write SYS_CTRL_REG System Control register 0x12 16 read-write n 0x0 0x0 CACHERAM_MUX Controls accessiblity of Cache RAM: 0: the cache controller is bypassed, the cacheRAM is visible in the memory space next to the DataRAMs 1: the cache controller is enabled, the cacheRAM is not visible anymore in the memory space 10 11 read-write DEBUGGER_ENABLE Enable the debugger. This bit is set by the booter according to the OTP header. If not set, the SWDIO and SW_CLK can be used as gpio ports. 7 8 read-write DEV_PHASE Sets the development phase mode, used in combination with OTP_COPY No copy action to SysRAM is done when the system wakes up. For emulating startup time, the OTP_COPY bit still needs to be set. 11 12 read-write DRA_OFF Disables the DRA mode, and released the ARM reset 8 9 read-write OTPC_RESET_REQ Reset request for the OTP controller. 6 7 read-write OTP_COPY Enables OTP to SysRAM copy action after waking up PD_SYS 13 14 read-write PAD_LATCH_EN Latches the control signals of the pads for state retention in powerdown mode. 0 = Control signals are retained 1 = Latch is transparant, pad can be recontrolled 5 6 read-write QSPI_INIT Enables QSPI initialization after wakeup 12 13 read-write REMAP_ADR0 Controls which memory is located at address 0x0000 for execution. 0x0: ROM 0x1: OTP 0x2: FLASH 0x3: RAMS (for the exact configuration see REMAP_RAMS) 0x4: FLASH un-cached (for verification only) 0x5: OTP un-cached (for verification only) 0x6: Cache Data RAM (CACHERAM_MUX=0, for testing purposes only) Note 1: DWord (64 bits) access is not supported by the Cache Data RAM interface in mirrored mode (only 32, 16 and 8 bits). Note 2: DMA access is not supported by the Cache Data RAM interface when REMAP_ADR0=0x6. 0 3 read-write REMAP_INTVECT 0: normal operation 1: If ARM is in address range 0 to 0xFF then the address is remapped to SYS-RAM 0x07FC.0000 to 0x07FC.00FF. This allows to put the interrupt vector table to be placed in RAM while executing from QSPI 14 15 read-write REMAP_RAMS Defines the sequence of the 3 first DataRAMs in the memory space. DataRAM4, DataRAM5 and potentially CacheRAM, cannot not be reshuffled. 0x0: DataRAM1, DataRAM2, DataRAM3 0x1: DataRAM2, DataRAM1, DataRAM3 0x2: DataRAM3, DataRAM1, DataRAM2 0x3: DataRAM3, DataRAM2, DataRAM1 3 5 read-write SW_RESET Writing a '1' to this bit will generate a SW_RESET. 15 16 write-only TIMEOUT_DISABLE Disables timeout in Power statemachine. By default, the statemachine continues if after 2 ms the blocks are not started up. This can be read back from ANA_STATUS_REG 9 10 read-write SYS_STAT_REG System status register 0x14 16 read-write n 0x0 0x0 BLE_IS_DOWN Indicates that PD_DBG is in power down 8 9 read-only BLE_IS_UP Indicates that PD_DBG is functional 9 10 read-only DBG_IS_ACTIVE Indicates that a debugger is attached. 5 6 read-only FTDF_IS_DOWN Indicates that PD_DBG is in power down 10 11 read-only FTDF_IS_UP Indicates that PD_DBG is functional 11 12 read-only PER_IS_DOWN Indicates that PD_PER is in power down 2 3 read-only PER_IS_UP Indicates that PD_PER is functional 3 4 read-only RAD_IS_DOWN Indicates that PD_RAD is in power down 0 1 read-only RAD_IS_UP Indicates that PD_RAD is functional 1 2 read-only XTAL16_TRIM_READY Indicates that XTAL trimming mechanism is ready, i.e. the trimming equals CLK_FREQ_TRIM_REG. 6 7 read-only VBUS_IRQ_CLEAR_REG Clear pending IRQ register 0x32 16 read-write n 0x0 0x0 VBUS_IRQ_CLEAR Writing any value to this register will reset the VBUS_IRQ line 0 16 read-write VBUS_IRQ_MASK_REG IRQ masking 0x30 16 read-write n 0x0 0x0 VBUS_IRQ_EN_FALL Setting this bit to '1' enables VBUS_IRQ generation when the VBUS starts to fall below threshold 0 1 read-write VBUS_IRQ_EN_RISE Setting this bit to '1' enables VBUS_IRQ generation when the VBUS starts to ramp above threshold 1 2 read-write XTALRDY_CTRL_REG Control register for XTALRDY IRQ 0x50 16 read-write n 0x0 0x0 XTALRDY_CNT Number of LP cycles between the crystal is enabled, and the XTALRDY_IRQ is fired. 0x00: no interrupt 0 8 read-write DCDC DCDC registers Peripheral_Registers 0x0 0x0 0x3A registers n CTRL_0_REG DCDC First Control Register 0x2 16 read-write n 0x0 0x0 DCDC_BROWNOUT_LV_MODE Switches to low voltage settings when battery voltage drops below 2.5 V 13 14 read-write DCDC_FAST_STARTUP Set current limit to maximum during initial startup 14 15 read-write DCDC_FW_ENABLE Freewheel switch enable 2 3 read-write DCDC_IDLE_CLK_DIV Idle Clock Divider 00 = 2 01 = 4 10 = 8 11 = 16 11 13 read-write DCDC_MODE DCDC converter mode 00 = Disabled 01 = Active 10 = Sleep mode 11 = Disabled 0 2 read-write DCDC_PRIORITY Charge priority register (4x 2 bit ID) Charge sequence is [1:0] > [3:2] > [5:4] > [7:6] ID[V14] = 00 ID[V18] = 01 ID[VDD] = 10 ID[V18P] = 11 3 11 read-write CTRL_1_REG DCDC Second Control Register 0x4 16 read-write n 0x0 0x0 DCDC_GLOBAL_MAX_IDLE_TIME Global maximum idle time The current limit of any output that is idle for this long will be downramped faster than normal 0 - 7875 ns, 125 ns step size 5 11 read-write DCDC_STARTUP_DELAY Delay between turning bias on and converter becoming active 0 - 31 us, 1 us step size 11 16 read-write DCDC_TIMEOUT P and N switch timeout, if switch is closed longer than this a timeout is generated and the FSM is forced to the next state 0 - 1937.5 ns, 62.5 ns step size 0 5 read-write CTRL_2_REG DCDC Third Control Register 0x6 16 read-write n 0x0 0x0 DCDC_HSGND_TRIM Trim high side ground V = VBAT - (2.2 V + 200 mV * N) 0 3 read-write DCDC_LSSUP_TRIM Trim low side supply voltage V = 2 V + 100 mV * N 3 6 read-write DCDC_TIMEOUT_IRQ_RES Number of successive non-timed out charge events required to clear timeout event counter 8 12 read-write DCDC_TIMEOUT_IRQ_TRIG Number of timeout events before timeout interrupt is generated 12 16 read-write DCDC_TUNE Trim current sensing circuitry 00 = +0 percent 01 = +4 percent 10 = +8 percent 11 = +12 percent 6 8 read-write IRQ_CLEAR_REG DCDC Interrupt Clear Register 0x36 16 read-write n 0x0 0x0 DCDC_BROWN_OUT_IRQ_CLEAR Clear brown out interrupt 4 5 write-only DCDC_V14_TIMEOUT_IRQ_CLEAR Clear V14 timeout interrupt 0 1 write-only DCDC_V18P_TIMEOUT_IRQ_CLEAR Clear V18P timeout interrupt 3 4 write-only DCDC_V18_TIMEOUT_IRQ_CLEAR Clear V18 timeout interrupt 1 2 write-only DCDC_VDD_TIMEOUT_IRQ_CLEAR Clear VDD timeout interrupt 2 3 write-only IRQ_MASK_REG DCDC Interrupt Clear Register 0x38 16 read-write n 0x0 0x0 DCDC_BROWN_OUT_IRQ_MASK Mask brown out interrupt 4 5 read-write DCDC_V14_TIMEOUT_IRQ_MASK Mask V14 timeout interrupt 0 1 read-write DCDC_V18P_TIMEOUT_IRQ_MASK Mask V18P timeout interrupt 3 4 read-write DCDC_V18_TIMEOUT_IRQ_MASK Mask V18 timeout interrupt 1 2 read-write DCDC_VDD_TIMEOUT_IRQ_MASK Mask VDD timeout interrupt 2 3 read-write IRQ_STATUS_REG DCDC Interrupt Status Register 0x34 16 read-write n 0x0 0x0 DCDC_BROWN_OUT_IRQ_STATUS Brown out detector triggered (battery voltage below 2.5 V) 4 5 read-only DCDC_V14_TIMEOUT_IRQ_STATUS Timeout occured on V14 output 0 1 read-only DCDC_V18P_TIMEOUT_IRQ_STATUS Timeout occured on V18P output 3 4 read-only DCDC_V18_TIMEOUT_IRQ_STATUS Timeout occured on V18 output 1 2 read-only DCDC_VDD_TIMEOUT_IRQ_STATUS Timeout occured on VDD output 2 3 read-only RET_0_REG DCDC First Retention Mode Register 0x18 16 read-write n 0x0 0x0 DCDC_V18P_CUR_LIM_RET V18P output sleep mode current limit I = 30 mA * (1 + N) 8 13 read-write DCDC_V18P_RET_CYCLES Charge cycles for V18P output in sleep mode Cycles = 1 + 2 * N 13 16 read-write DCDC_VDD_CUR_LIM_RET VDD output sleep mode current limit I = 30 mA * (1 + N) 0 5 read-write DCDC_VDD_RET_CYCLES Charge cycles for VDD output in sleep mode Cycles = 1 + 2 * N 5 8 read-write RET_1_REG DCDC Second Retention Mode Register 0x1A 16 read-write n 0x0 0x0 DCDC_V14_CUR_LIM_RET V14 output sleep mode current limit I = 30 mA * (1 + N) 0 5 read-write DCDC_V14_RET_CYCLES Charge cycles for V14 output in sleep mode Cycles = 1 + 2 * N 5 8 read-write DCDC_V18_CUR_LIM_RET V18 output sleep mode current limit I = 30 mA * (1 + N) 8 13 read-write DCDC_V18_RET_CYCLES Charge cycles for V18 output in sleep mode Cycles = 1 + 2 * N 13 16 read-write STATUS_0_REG DCDC First Status Register 0x22 16 read-write n 0x0 0x0 DCDC_CHARGE_REG_0 Charge register position 0 0 3 read-only DCDC_CHARGE_REG_1 Charge register position 1 3 6 read-only DCDC_CHARGE_REG_2 Charge register position 2 6 9 read-only DCDC_CHARGE_REG_3 Charge register position 3 9 12 read-only STATUS_1_REG DCDC Second Status Register 0x24 16 read-write n 0x0 0x0 DCDC_V14_AVAILABLE Indicates whether V14 is available Requires that converter is enabled, output is enabled and V_OK and V_NOK have both occured 8 9 read-only DCDC_V14_NOK NOK output of V14 comparator 0 1 read-only DCDC_V14_OK OK output of V14 comparator 4 5 read-only DCDC_V18P_AVAILABLE Indicates whether V18P is available Requires that converter is enabled, output is enabled and V_OK and V_NOK have both occured 11 12 read-only DCDC_V18P_NOK NOK output of V18P comparator 3 4 read-only DCDC_V18P_OK OK output of V18P comparator 7 8 read-only DCDC_V18_AVAILABLE Indicates whether V18 is available Requires that converter is enabled, output is enabled and V_OK and V_NOK have both occured 9 10 read-only DCDC_V18_NOK NOK output of V18 comparator 1 2 read-only DCDC_V18_OK OK output of V18 comparator 5 6 read-only DCDC_VDD_AVAILABLE Indicates whether VDD is available Requires that converter is enabled, output is enabled and V_OK and V_NOK have both occured 10 11 read-only DCDC_VDD_NOK NOK output of VDD comparator 2 3 read-only DCDC_VDD_OK OK output of VDD comparator 6 7 read-only STATUS_2_REG DCDC Third Status Register 0x26 16 read-write n 0x0 0x0 DCDC_NSW_STATE DCDC state machine NSW output 7 8 read-only DCDC_N_COMP DCDC N side continuous time comparator output 0 1 read-only DCDC_N_COMP_N DCDC N side dynamic comparator N output 2 3 read-only DCDC_N_COMP_P DCDC N side dynamic comparator P output 3 4 read-only DCDC_PSW_STATE DCDC state machine PSW output 6 7 read-only DCDC_P_COMP DCDC P side continuous time comparator output 1 2 read-only DCDC_P_COMP_N DCDC P side dynamic comparator N output 4 5 read-only DCDC_P_COMP_P DCDC P side dynamic comparator P output 5 6 read-only DCDC_V14_SW_STATE DCDC state machine V14 output 8 9 read-only DCDC_V18P_SW_STATE DCDC state machine V18P output 11 12 read-only DCDC_V18_SW_STATE DCDC state machine V18 output 9 10 read-only DCDC_VDD_SW_STATE DCDC state machine VDD output 10 11 read-only STATUS_3_REG DCDC Fourth Status Register 0x28 16 read-write n 0x0 0x0 DCDC_I_LIM_V18P Actual V18P current limit 5 10 read-only DCDC_I_LIM_VDD Actual VDD current limit 0 5 read-only DCDC_LV_MODE Indicates if the converter is in low battery voltage mode 10 11 read-only STATUS_4_REG DCDC Fifth Status Register 0x2A 16 read-write n 0x0 0x0 DCDC_I_LIM_V14 Actual V14 current limit 0 5 read-only DCDC_I_LIM_V18 Actual V18 current limit 5 10 read-only TEST_0_REG DCDC Test Register 0x1E 16 read-write n 0x0 0x0 DCDC_ANA_TEST Analog test bus 000 = None 001 = High side ground 010 = Low side supply 011 = 1.2 V buffer output 100 = None 101 = None 110 = None 111 = None 8 11 read-write DCDC_FORCE_COMP_CLK Disables automatic comparator clock, clock lines values based on DCDC_COMP_CLK 15 16 read-write DCDC_FORCE_CURRENT Force output current setting 14 15 read-write DCDC_FORCE_FW Force FW switch on 2 3 read-write DCDC_FORCE_IDLE Force idle mode 7 8 read-write DCDC_FORCE_NSW Force N switch on 1 2 read-write DCDC_FORCE_PSW Force P switch on 0 1 read-write DCDC_FORCE_V14 Force V14 switch on 3 4 read-write DCDC_FORCE_V18 Force V18 switch on 4 5 read-write DCDC_FORCE_V18P Force V18P switch on 6 7 read-write DCDC_FORCE_VDD Force VDD switch on 5 6 read-write DCDC_OUTPUT_MONITOR Output monitor switch (connect to ADC) 000 = None 001 = V14 010 = V18 011 = VDD 100 = VPA 101 = None 110 = None 111 = None 11 14 read-write TEST_1_REG DCDC Test Register 0x20 16 read-write n 0x0 0x0 DCDC_COMP_CLK Forced clock values for [COMP_VPA, COMP_VDD, COMP_V18, COMP_V14] (requires DCDC_FORCE_COMP_CLK = 1) 9 13 read-write DCDC_TEST_CURRENT Current limit setting when current limit is forced 4 9 read-write DCDC_TEST_REG Determines which register appears on the testbus 0x0 = DCDC_NONE 0x1 = DCDC_STATUS_0 0x2 = DCDC_STATUS_1 0x3 = DCDC_STATUS_2 0x4 = DCDC_STATUS_3 0x5 = DCDC_STATUS_4 0x6 = DCDC_TRIM_0 0x7 = DCDC_TRIM_1 0x8 = DCDC_TRIM_2 0x9 = DCDC_TRIM_3 0xA-0xF = DCDC_NONE 0 4 read-write TRIM_0_REG DCDC V14 Comparator Trim Register 0x2C 16 read-write n 0x0 0x0 DCDC_V14_TRIM_N N comparator trim value when V14 is active Signed magnitude representation 011111 = +13 mV 000000 = 100000 = -22 mV 111111 = -56 mV 0 6 read-only DCDC_V14_TRIM_P P comparator trim value when V14 is active Signed magnitude representation 011111 = +47 mV 000000 = 100000 = +16 mV 111111 = -15 mV 6 12 read-only TRIM_1_REG DCDC V18 Comparator Trim Register 0x2E 16 read-write n 0x0 0x0 DCDC_V18_TRIM_N N comparator trim value when V18 is active Signed magnitude representation 011111 = +13 mV 000000 = 100000 = -22 mV 111111 = -56 mV 0 6 read-only DCDC_V18_TRIM_P P comparator trim value when V18 is active Signed magnitude representation 011111 = +47 mV 000000 = 100000 = +16 mV 111111 = -15 mV 6 12 read-only TRIM_2_REG DCDC VDD Comparator Trim Register 0x30 16 read-write n 0x0 0x0 DCDC_VDD_TRIM_N N comparator trim value when VDD is active Signed magnitude representation 011111 = +13 mV 000000 = 100000 = -22 mV 111111 = -56 mV 0 6 read-only DCDC_VDD_TRIM_P P comparator trim value when VDD is active Signed magnitude representation 011111 = +47 mV 000000 = 100000 = +16 mV 111111 = -15 mV 6 12 read-only TRIM_3_REG DCDC VPA Comparator Trim Register 0x32 16 read-write n 0x0 0x0 DCDC_V18P_TRIM_N N comparator trim value when V18P is active Signed magnitude representation 011111 = +13 mV 000000 = 100000 = -22 mV 111111 = -56 mV 0 6 read-only DCDC_V18P_TRIM_P P comparator trim value when V18P is active Signed magnitude representation 011111 = +47 mV 000000 = 100000 = +16 mV 111111 = -15 mV 6 12 read-only TRIM_REG DCDC Comparator Trim Register 0x1C 16 read-write n 0x0 0x0 DCDC_N_COMP_MAN_TRIM Trim mode for N side comparator 0 = Automatic 1 = Manual 6 7 read-write DCDC_N_COMP_TRIM Manual trim value for N side comparator Signed magnitude representation 011111 = +13 mV 000000 = 100000 = -22 mV 111111 = -56 mV 0 6 read-write DCDC_P_COMP_MAN_TRIM Trim mode for P side comparator 0 = Automatic 1 = Manual 13 14 read-write DCDC_P_COMP_TRIM Manual trim value for P side comparator Signed magnitude representation 011111 = +47 mV 000000 = 100000 = +16 mV 111111 = -15 mV 7 13 read-write V14_0_REG DCDC V14 First Control Register 0x8 16 read-write n 0x0 0x0 DCDC_V14_CUR_LIM_MAX_HV V14 output maximum current limit (high battery voltage mode) I = 30 mA * (1 + N) 5 10 read-write DCDC_V14_CUR_LIM_MIN V14 output minimum current limit I = 30 mA * (1 + N) 0 5 read-write DCDC_V14_FAST_RAMPING V14 output fast current ramping (improves response time at the cost of more ripple) 15 16 read-write DCDC_V14_VOLTAGE V14 output voltage V = 1.2 V + 25 mV * N 10 15 read-write V14_1_REG DCDC V14 Second Control Register 0xA 16 read-write n 0x0 0x0 DCDC_V14_CUR_LIM_MAX_LV V14 output maximum current limit low battery voltage mode) I = 30 mA * (1 + N) 10 14 read-write DCDC_V14_ENABLE_HV V14 output enable (high battery voltage mode) 0 = Disabled 1 = Enabled 15 16 read-write DCDC_V14_ENABLE_LV V14 output enable (low battery voltage mode) 0 = Disabled 1 = Enabled 14 15 read-write DCDC_V14_IDLE_HYST V14 output idle time hysteresis 0 - 3875 ns, 125 ns step size IDLE_MAX = IDLE_MIN + IDLE_HYST Maximum idle time before decreasing CUR_LIM 5 10 read-write DCDC_V14_IDLE_MIN V14 output minimum idle time 0 - 3875 ns, 125 ns step size Minimum idle time, CUR_LIM is increased if this limit is not reached 0 5 read-write V18P_0_REG DCDC VPA First Control Register 0x14 16 read-write n 0x0 0x0 DCDC_V18P_CUR_LIM_MAX_HV V18P output maximum current limit (high battery voltage mode) I = 30 mA * (1 + N) 5 10 read-write DCDC_V18P_CUR_LIM_MIN V18P output minimum current limit I = 30 mA * (1 + N) 0 5 read-write DCDC_V18P_FAST_RAMPING V18P output fast current ramping (improves response time at the cost of more ripple) 15 16 read-write DCDC_V18P_VOLTAGE V18P output voltage V = 1.2 V + 25 mV * N 10 15 read-write V18P_1_REG DCDC VPA Second Control Register 0x16 16 read-write n 0x0 0x0 DCDC_V18P_CUR_LIM_MAX_LV V18P output maximum current limit low battery voltage mode) I = 30 mA * (1 + N) 10 14 read-write DCDC_V18P_ENABLE_HV V18P output enable (high battery voltage mode) 0 = Disabled 1 = Enabled 15 16 read-write DCDC_V18P_ENABLE_LV V18P output enable (low battery voltage mode) 0 = Disabled 1 = Enabled 14 15 read-write DCDC_V18P_IDLE_HYST V18P output idle time hysteresis 0 - 3875 ns, 125 ns step size IDLE_MAX = IDLE_MIN + IDLE_HYST Maximum idle time before decreasing CUR_LIM 5 10 read-write DCDC_V18P_IDLE_MIN V18P output minimum idle time 0 - 3875 ns, 125 ns step size Minimum idle time, CUR_LIM is increased if this limit is not reached 0 5 read-write V18_0_REG DCDC V18 First Control Register 0xC 16 read-write n 0x0 0x0 DCDC_V18_CUR_LIM_MAX_HV V18 output maximum current limit (high battery voltage mode) I = 30 mA * (1 + N) 5 10 read-write DCDC_V18_CUR_LIM_MIN V18 output minimum current limit I = 30 mA * (1 + N) 0 5 read-write DCDC_V18_FAST_RAMPING V18 output fast current ramping (improves response time at the cost of more ripple) 15 16 read-write DCDC_V18_VOLTAGE V18 output voltage V = 1.2 V + 25 mV * N 10 15 read-write V18_1_REG DCDC V18 Second Control Register 0xE 16 read-write n 0x0 0x0 DCDC_V18_CUR_LIM_MAX_LV V18 output maximum current limit low battery voltage mode) I = 30 mA * (1 + N) 10 14 read-write DCDC_V18_ENABLE_HV V18 output enable (high battery voltage mode) 0 = Disabled 1 = Enabled 15 16 read-write DCDC_V18_ENABLE_LV V18 output enable (low battery voltage mode) 0 = Disabled 1 = Enabled 14 15 read-write DCDC_V18_IDLE_HYST V18 output idle time hysteresis 0 - 3875 ns, 125 ns step size IDLE_MAX = IDLE_MIN + IDLE_HYST Maximum idle time before decreasing CUR_LIM 5 10 read-write DCDC_V18_IDLE_MIN V18 output minimum idle time 0 - 3875 ns, 125 ns step size Minimum idle time, CUR_LIM is increased if this limit is not reached 0 5 read-write VDD_0_REG DCDC VDD First Control Register 0x10 16 read-write n 0x0 0x0 DCDC_VDD_CUR_LIM_MAX_HV VDD output maximum current limit (high battery voltage mode) I = 30 mA * (1 + N) 5 10 read-write DCDC_VDD_CUR_LIM_MIN VDD output minimum current limit I = 30 mA * (1 + N) 0 5 read-write DCDC_VDD_FAST_RAMPING VDD output fast current ramping (improves response time at the cost of more ripple) 15 16 read-write DCDC_VDD_VOLTAGE VDD output voltage V = 0.8 V + 25 mV * N 10 15 read-write VDD_1_REG DCDC VDD Second Control Register 0x12 16 read-write n 0x0 0x0 DCDC_VDD_CUR_LIM_MAX_LV VDD output maximum current limit low battery voltage mode) I = 30 mA * (1 + N) 10 14 read-write DCDC_VDD_ENABLE_HV VDD output enable (high battery voltage mode) 0 = Disabled 1 = Enabled 15 16 read-write DCDC_VDD_ENABLE_LV VDD output enable (low battery voltage mode) 0 = Disabled 1 = Enabled 14 15 read-write DCDC_VDD_IDLE_HYST VDD output idle time hysteresis 0 - 3875 ns, 125 ns step size IDLE_MAX = IDLE_MIN + IDLE_HYST Maximum idle time before decreasing CUR_LIM 5 10 read-write DCDC_VDD_IDLE_MIN VDD output minimum idle time 0 - 3875 ns, 125 ns step size Minimum idle time, CUR_LIM is increased if this limit is not reached 0 5 read-write DMA DMA registers Peripheral_Registers 0x0 0x0 0x86 registers n CLEAR_INT_REG DMA clear interrupt register 0x84 16 read-write n 0x0 0x0 DMA_RST_IRQ_CH0 Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 0 writing a 0 will have no effect 0 1 write-only DMA_RST_IRQ_CH1 Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 1 writing a 0 will have no effect 1 2 write-only DMA_RST_IRQ_CH2 Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 2 writing a 0 will have no effect 2 3 write-only DMA_RST_IRQ_CH3 Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 3 writing a 0 will have no effect 3 4 write-only DMA_RST_IRQ_CH4 Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 4 writing a 0 will have no effect 4 5 write-only DMA_RST_IRQ_CH5 Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 5 writing a 0 will have no effect 5 6 write-only DMA_RST_IRQ_CH6 Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 6 writing a 0 will have no effect 6 7 write-only DMA_RST_IRQ_CH7 Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 7 writing a 0 will have no effect 7 8 write-only DMA0_A_STARTH_REG Start address High A of DMA channel 0 0x2 16 read-write n 0x0 0x0 DMA0_A_STARTH Source start address, upper 16 bits 0 16 read-write DMA0_A_STARTL_REG Start address Low A of DMA channel 0 0x0 16 read-write n 0x0 0x0 DMA0_A_STARTL Source start address, lower 16 bits 0 16 read-write DMA0_B_STARTH_REG Start address High B of DMA channel 0 0x6 16 read-write n 0x0 0x0 DMA0_B_STARTH Destination start address, upper 16 bits 0 16 read-write DMA0_B_STARTL_REG Start address Low B of DMA channel 0 0x4 16 read-write n 0x0 0x0 DMA0_B_STARTL Destination start address, lower 16 bits 0 16 read-write DMA0_CTRL_REG Control register for the DMA channel 0 0xC 16 read-write n 0x0 0x0 AINC Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 6 7 read-write BINC Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 5 6 read-write BW Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved 1 3 read-write CIRCULAR 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer. 7 8 read-write DMA_IDLE 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care. 11 12 read-write DMA_INIT 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'. 12 13 read-write DMA_ON 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. 0 1 read-write DMA_PRIO The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus. 8 11 read-write DREQ_MODE 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG) 4 5 read-write IRQ_ENABLE 0 = disables interrupts on this channel 1 = enables interrupts on this channel 3 4 read-write DMA0_IDX_REG Index value of DMA channel 0 0xE 16 read-write n 0x0 0x0 DMA0_IDX This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW. 0 16 read-only DMA0_INT_REG DMA receive interrupt register channel 0 0x8 16 read-write n 0x0 0x0 DMA0_INT Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt. 0 16 read-write DMA0_LEN_REG DMA receive length register channel 0 0xA 16 read-write n 0x0 0x0 DMA0_LEN DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ... 0 16 read-write DMA1_A_STARTH_REG Start address High A of DMA channel 1 0x12 16 read-write n 0x0 0x0 DMA1_A_STARTH Source start address, upper 16 bits 0 16 read-write DMA1_A_STARTL_REG Start address Low A of DMA channel 1 0x10 16 read-write n 0x0 0x0 DMA1_A_STARTL Source start address, lower 16 bits 0 16 read-write DMA1_B_STARTH_REG Start address High B of DMA channel 1 0x16 16 read-write n 0x0 0x0 DMA1_B_STARTH Destination start address, upper 16 bits 0 16 read-write DMA1_B_STARTL_REG Start address Low B of DMA channel 1 0x14 16 read-write n 0x0 0x0 DMA1_B_STARTL Destination start address, lower 16 bits 0 16 read-write DMA1_CTRL_REG Control register for the DMA channel 1 0x1C 16 read-write n 0x0 0x0 AINC Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 6 7 read-write BINC Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 5 6 read-write BW Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved 1 3 read-write CIRCULAR 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer. 7 8 read-write DMA_IDLE 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care. 11 12 read-write DMA_INIT 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'. 12 13 read-write DMA_ON 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. 0 1 read-write DMA_PRIO The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus. 8 11 read-write DREQ_MODE 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG) 4 5 read-write IRQ_ENABLE 0 = disables interrupts on this channel 1 = enables interrupts on this channel 3 4 read-write DMA1_IDX_REG Index value of DMA channel 1 0x1E 16 read-write n 0x0 0x0 DMA1_IDX This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW. 0 16 read-only DMA1_INT_REG DMA receive interrupt register channel 1 0x18 16 read-write n 0x0 0x0 DMA1_INT Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt. 0 16 read-write DMA1_LEN_REG DMA receive length register channel 1 0x1A 16 read-write n 0x0 0x0 DMA1_LEN DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ... 0 16 read-write DMA2_A_STARTH_REG Start address High A of DMA channel 2 0x22 16 read-write n 0x0 0x0 DMA2_A_STARTH Source start address, upper 16 bits 0 16 read-write DMA2_A_STARTL_REG Start address Low A of DMA channel 2 0x20 16 read-write n 0x0 0x0 DMA2_A_STARTL Source start address, lower 16 bits 0 16 read-write DMA2_B_STARTH_REG Start address High B of DMA channel 2 0x26 16 read-write n 0x0 0x0 DMA2_B_STARTH Destination start address, upper 16 bits 0 16 read-write DMA2_B_STARTL_REG Start address Low B of DMA channel 2 0x24 16 read-write n 0x0 0x0 DMA2_B_STARTL Destination start address, lower 16 bits 0 16 read-write DMA2_CTRL_REG Control register for the DMA channel 2 0x2C 16 read-write n 0x0 0x0 AINC Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 6 7 read-write BINC Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 5 6 read-write BW Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved 1 3 read-write CIRCULAR 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer. 7 8 read-write DMA_IDLE 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care. 11 12 read-write DMA_INIT 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'. 12 13 read-write DMA_ON 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. 0 1 read-write DMA_PRIO The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus. 8 11 read-write DREQ_MODE 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG) 4 5 read-write IRQ_ENABLE 0 = disables interrupts on this channel 1 = enables interrupts on this channel 3 4 read-write DMA2_IDX_REG Index value of DMA channel 2 0x2E 16 read-write n 0x0 0x0 DMA2_IDX This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW. 0 16 read-only DMA2_INT_REG DMA receive interrupt register channel 2 0x28 16 read-write n 0x0 0x0 DMA2_INT Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt. 0 16 read-write DMA2_LEN_REG DMA receive length register channel 2 0x2A 16 read-write n 0x0 0x0 DMA2_LEN DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ... 0 16 read-write DMA3_A_STARTH_REG Start address High A of DMA channel 3 0x32 16 read-write n 0x0 0x0 DMA3_A_STARTH Source start address, upper 16 bits 0 16 read-write DMA3_A_STARTL_REG Start address Low A of DMA channel 3 0x30 16 read-write n 0x0 0x0 DMA3_A_STARTL Source start address, lower 16 bits 0 16 read-write DMA3_B_STARTH_REG Start address High B of DMA channel 3 0x36 16 read-write n 0x0 0x0 DMA3_B_STARTH Destination start address, upper 16 bits 0 16 read-write DMA3_B_STARTL_REG Start address Low B of DMA channel 3 0x34 16 read-write n 0x0 0x0 DMA3_B_STARTL Destination start address, lower 16 bits 0 16 read-write DMA3_CTRL_REG Control register for the DMA channel 3 0x3C 16 read-write n 0x0 0x0 AINC Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 6 7 read-write BINC Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 5 6 read-write BW Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved 1 3 read-write CIRCULAR 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer. 7 8 read-write DMA_IDLE 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care. 11 12 read-write DMA_INIT 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'. 12 13 read-write DMA_ON 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. 0 1 read-write DMA_PRIO The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus. 8 11 read-write DREQ_MODE 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG) 4 5 read-write IRQ_ENABLE 0 = disables interrupts on this channel 1 = enables interrupts on this channel 3 4 read-write DMA3_IDX_REG Index value of DMA channel 3 0x3E 16 read-write n 0x0 0x0 DMA3_IDX This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW. 0 16 read-only DMA3_INT_REG DMA receive interrupt register channel 3 0x38 16 read-write n 0x0 0x0 DMA3_INT Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt. 0 16 read-write DMA3_LEN_REG DMA receive length register channel 3 0x3A 16 read-write n 0x0 0x0 DMA3_LEN DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ... 0 16 read-write DMA4_A_STARTH_REG Start address High A of DMA channel 4 0x42 16 read-write n 0x0 0x0 DMA4_A_STARTH Source start address, upper 16 bits 0 16 read-write DMA4_A_STARTL_REG Start address Low A of DMA channel 4 0x40 16 read-write n 0x0 0x0 DMA4_A_STARTL Source start address, lower 16 bits 0 16 read-write DMA4_B_STARTH_REG Start address High B of DMA channel 4 0x46 16 read-write n 0x0 0x0 DMA4_B_STARTH Destination start address, upper 16 bits 0 16 read-write DMA4_B_STARTL_REG Start address Low B of DMA channel 4 0x44 16 read-write n 0x0 0x0 DMA4_B_STARTL Destination start address, lower 16 bits 0 16 read-write DMA4_CTRL_REG Control register for the DMA channel 4 0x4C 16 read-write n 0x0 0x0 AINC Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 6 7 read-write BINC Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 5 6 read-write BW Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved 1 3 read-write CIRCULAR 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer. 7 8 read-write DMA_IDLE 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care. 11 12 read-write DMA_INIT 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'. 12 13 read-write DMA_ON 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. 0 1 read-write DMA_PRIO The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus. 8 11 read-write DREQ_MODE 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG) 4 5 read-write IRQ_ENABLE 0 = disables interrupts on this channel 1 = enables interrupts on this channel 3 4 read-write DMA4_IDX_REG Index value of DMA channel 4 0x4E 16 read-write n 0x0 0x0 DMA4_IDX This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW. 0 16 read-only DMA4_INT_REG DMA receive interrupt register channel 4 0x48 16 read-write n 0x0 0x0 DMA4_INT Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt. 0 16 read-write DMA4_LEN_REG DMA receive length register channel 4 0x4A 16 read-write n 0x0 0x0 DMA4_LEN DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ... 0 16 read-write DMA5_A_STARTH_REG Start address High A of DMA channel 5 0x52 16 read-write n 0x0 0x0 DMA5_A_STARTH Source start address, upper 16 bits 0 16 read-write DMA5_A_STARTL_REG Start address Low A of DMA channel 5 0x50 16 read-write n 0x0 0x0 DMA5_A_STARTL Source start address, lower 16 bits 0 16 read-write DMA5_B_STARTH_REG Start address High B of DMA channel 5 0x56 16 read-write n 0x0 0x0 DMA5_B_STARTH Destination start address, upper 16 bits 0 16 read-write DMA5_B_STARTL_REG Start address Low B of DMA channel 5 0x54 16 read-write n 0x0 0x0 DMA5_B_STARTL Destination start address, lower 16 bits 0 16 read-write DMA5_CTRL_REG Control register for the DMA channel 5 0x5C 16 read-write n 0x0 0x0 AINC Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 6 7 read-write BINC Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 5 6 read-write BW Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved 1 3 read-write CIRCULAR 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer. 7 8 read-write DMA_IDLE 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care. 11 12 read-write DMA_INIT 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'. 12 13 read-write DMA_ON 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. 0 1 read-write DMA_PRIO The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus. 8 11 read-write DREQ_MODE 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG) 4 5 read-write IRQ_ENABLE 0 = disables interrupts on this channel 1 = enables interrupts on this channel 3 4 read-write DMA5_IDX_REG Index value of DMA channel 5 0x5E 16 read-write n 0x0 0x0 DMA5_IDX This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW. 0 16 read-only DMA5_INT_REG DMA receive interrupt register channel 5 0x58 16 read-write n 0x0 0x0 DMA5_INT Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt. 0 16 read-write DMA5_LEN_REG DMA receive length register channel 5 0x5A 16 read-write n 0x0 0x0 DMA5_LEN DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ... 0 16 read-write DMA6_A_STARTH_REG Start address High A of DMA channel 6 0x62 16 read-write n 0x0 0x0 DMA6_A_STARTH Source start address, upper 16 bits 0 16 read-write DMA6_A_STARTL_REG Start address Low A of DMA channel 6 0x60 16 read-write n 0x0 0x0 DMA6_A_STARTL Source start address, lower 16 bits 0 16 read-write DMA6_B_STARTH_REG Start address High B of DMA channel 6 0x66 16 read-write n 0x0 0x0 DMA6_B_STARTH Destination start address, upper 16 bits 0 16 read-write DMA6_B_STARTL_REG Start address Low B of DMA channel 6 0x64 16 read-write n 0x0 0x0 DMA6_B_STARTL Destination start address, lower 16 bits 0 16 read-write DMA6_CTRL_REG Control register for the DMA channel 6 0x6C 16 read-write n 0x0 0x0 AINC Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 6 7 read-write BINC Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 5 6 read-write BW Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved 1 3 read-write CIRCULAR 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer. 7 8 read-write DMA_IDLE 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care. 11 12 read-write DMA_INIT 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'. 12 13 read-write DMA_ON 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. 0 1 read-write DMA_PRIO The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus. 8 11 read-write DREQ_MODE 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG) 4 5 read-write IRQ_ENABLE 0 = disables interrupts on this channel 1 = enables interrupts on this channel 3 4 read-write DMA6_IDX_REG Index value of DMA channel 6 0x6E 16 read-write n 0x0 0x0 DMA6_IDX This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW. 0 16 read-only DMA6_INT_REG DMA receive interrupt register channel 6 0x68 16 read-write n 0x0 0x0 DMA6_INT Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt. 0 16 read-write DMA6_LEN_REG DMA receive length register channel 6 0x6A 16 read-write n 0x0 0x0 DMA6_LEN DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ... 0 16 read-write DMA7_A_STARTH_REG Start address High A of DMA channel 7 0x72 16 read-write n 0x0 0x0 DMA7_A_STARTH Source start address, upper 16 bits 0 16 read-write DMA7_A_STARTL_REG Start address Low A of DMA channel 7 0x70 16 read-write n 0x0 0x0 DMA7_A_STARTL Source start address, lower 16 bits 0 16 read-write DMA7_B_STARTH_REG Start address High B of DMA channel 7 0x76 16 read-write n 0x0 0x0 DMA7_B_STARTH Destination start address, upper 16 bits 0 16 read-write DMA7_B_STARTL_REG Start address Low B of DMA channel 7 0x74 16 read-write n 0x0 0x0 DMA7_B_STARTL Destination start address, lower 16 bits 0 16 read-write DMA7_CTRL_REG Control register for the DMA channel 7 0x7C 16 read-write n 0x0 0x0 AINC Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 6 7 read-write BINC Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 ) 5 6 read-write BW Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved 1 3 read-write CIRCULAR 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer. 7 8 read-write DMA_IDLE 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care. 11 12 read-write DMA_INIT 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'. 12 13 read-write DMA_ON 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. 0 1 read-write DMA_PRIO The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus. 8 11 read-write DREQ_MODE 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG) 4 5 read-write IRQ_ENABLE 0 = disables interrupts on this channel 1 = enables interrupts on this channel 3 4 read-write DMA7_IDX_REG Index value of DMA channel 7 0x7E 16 read-write n 0x0 0x0 DMA7_IDX This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW. 0 16 read-only DMA7_INT_REG DMA receive interrupt register channel 7 0x78 16 read-write n 0x0 0x0 DMA7_INT Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt. 0 16 read-write DMA7_LEN_REG DMA receive length register channel 7 0x7A 16 read-write n 0x0 0x0 DMA7_LEN DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ... 0 16 read-write INT_STATUS_REG DMA interrupt status register 0x82 16 read-write n 0x0 0x0 DMA_IRQ_CH0 0 = IRQ on channel 0 is not set 1 = IRQ on channel 0 is set 0 1 read-only DMA_IRQ_CH1 0 = IRQ on channel 1 is not set 1 = IRQ on channel 1 is set 1 2 read-only DMA_IRQ_CH2 0 = IRQ on channel 2 is not set 1 = IRQ on channel 2 is set 2 3 read-only DMA_IRQ_CH3 0 = IRQ on channel 3 is not set 1 = IRQ on channel 3 is set 3 4 read-only DMA_IRQ_CH4 0 = IRQ on channel 4 is not set 1 = IRQ on channel 4 is set 4 5 read-only DMA_IRQ_CH5 0 = IRQ on channel 5 is not set 1 = IRQ on channel 5 is set 5 6 read-only DMA_IRQ_CH6 0 = IRQ on channel 6 is not set 1 = IRQ on channel 6 is set 6 7 read-only DMA_IRQ_CH7 0 = IRQ on channel 7 is not set 1 = IRQ on channel 7 is set 7 8 read-only REQ_MUX_REG DMA channel assignments 0x80 16 read-write n 0x0 0x0 DMA01_SEL Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels. Here, the first DMA request is mapped on channel 0 and the second on channel 1. 0x0: SPI_rx / SPI_tx 0x1: SPI2_rx / SPI2_tx 0x2: UART_rx / UART_tx 0x3: UART2_rx / UART2_tx 0x4: I2C_rx / I2C_tx 0x5: I2C2_rx / I2C2_tx 0x6: USB_rx / USB_tx 0x7: Reserved 0x8: PCM_rx / PCM_tx 0x9: SRC_rx / SRC_tx (for all the supported conversions) 0xA: FTDF_rx / FTDF_tx 0xB: Reserved 0xC: ADC / - 0xD: Reserved 0xE: Reserved 0xF: Reserved Note: If any of the four available peripheral selector fields (DMA01_SEL, DMA23_SEL, DMA45_SEL, DMA67_SEL) have the same value, the lesser significant selector has higher priority and will control the dma acknowledge. Hence, if DMA01_SEL = DMA23_SEL, the channels 0 and 1 will generate the DMA acknowledge signals for the selected peripheral. Consequently, it is suggested to assign the intended peripheral value to a unique selector field. 0 4 read-write DMA23_SEL Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels. Here, the first DMA request is mapped on channel 2 and the second on channel 3. See DMA01_SEL for the peripherals' mapping. 4 8 read-write DMA45_SEL Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels. Here, the first DMA request is mapped on channel 4 and the second on channel 5. See DMA01_SEL for the peripherals' mapping. 8 12 read-write DMA67_SEL Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels. Here, the first DMA request is mapped on channel 6 and the second on channel 7. See DMA01_SEL for the peripherals' mapping. 12 16 read-write ECC ECC registers Peripheral_Registers 0x0 0x0 0x14 registers n COMMAND_REG Command register 0x4 32 read-write n 0x0 0x0 ECC_CalcR2 This bit indicates if the IP has to calculate R mod N for the next operation. This bit must be set to 1 when a new prime number has been programmed. This bit is automatically cleared when R mod N has been calculated. '0': no effect '1': forces the IP to re-calculate R mod N 31 32 read-write ECC_Field '0': Field is F(p) '1': Field is F(2m) 7 8 read-write ECC_SignA Sign of parameter A in equation y2=x3+Ax+B '0': A is positive '1': A is negative 29 30 read-write ECC_SignB Sign of parameter B in equation y2=x3+Ax+B '0': B is positive '1': B is negative 30 31 read-write ECC_SizeOfOperands This field defines the size (= number of 64-bit double words) of the operands for the current operation. Possible values are limited by the generic parameter g_Log2MaxDataSize that defines the max space allocated or reserved to each operand. Arbitrary Data/Key size from 128 up to 2566 are supported: 0x02 (02d) -> 128-bit Data/Key size 0x03 (02d) -> 256-bit Data/Key size ECC-ECDSA - Prime Field F(p) 0x03 -> 192-bit (Curve P-192) 0x04 -> 256-bit (Curves P-224 and P-256) ECC-ECDSA - Binary Field F(2m) 0x03 -> 192-bit (Curve K-163) 0x04 -> 256-bit (Curve K-233) - 4 Xers: 0x01, 0x02, 0x4, 0x6 -> 64, 128 and multiples of 128 bits 8 16 read-write ECC_TypeOperation Primitive Arithmetic Operations F(p) and F(2m) [6:4] = 0x0 [3:0] = 0x0 -> Reserved 0x1 -> Modular Addition 0x2 -> Modular Subtraction 0x3 -> Modular Multiplication (Odd N) 0x4 -> Modular Reduction (Odd N) 0x5 -> Modular Division (Odd N) 0x6 -> Modular Inversion (Odd N) 0x7 -> Reserved 0x8 -> Multiplication 0x9 -> Modular Inversion (Even N) 0xA -> Modular Reduction (Even N) others -> Reserved C = A + B mod N C = A - B mod N C = A * B mod N C = B mod N C = A/B mod N C = 1/B mod N C = A * B C = 1/B mod N C = B mod N High-level RSA, CRT and DSA Operations - F(p) only ([7] forced to 0) [6:4] = 0x1 [3:0] = 0x0 -> MulModN 0x1 -> MulAddN 0x2 -> ECMQV (part1) others -> Reserved Primitive ECC and Check Point Operations F(p) and F(2m) [6:4] = 0x2 [3:0] = 0x0 -> Point Doubling (Projective Coord.) 0x1 -> ptAdd3 0x2 -> GenSessionKey 0x3 -> Check_AB (ECDSA) 0x4 -> Check_n (ECDSA) 0x5 -> Check single value less than N 0x6 -> Check_Point_On_Curve 0x7-> Reserved 0x8 -> Curve25519 point multiplication 0x9 -> Ed25519 Check point on curve 0xA -> Ed25519 ScalarMult 0xB -> Ed25519 CheckValid others -> Reserved High-level ECC ECDSA Operations F(p) and F(2m) [6:4] = 0x3 [3:0] = 0x0 -> ECMQV (part 2) 0x1 -> Verify ZKP 0x2 -> ECDSA Domain Parameters Validation others -> Reserved [6:4]=0x4, 0x5, 0x6, 0x7 -> Reserved 0 7 read-write CONFIG_REG Configuration register 0x0 32 read-write n 0x0 0x0 ECC_OpPtrA When executing primitive arithmetic operations, this Pointer defines where operand A is located in memory. 0 5 read-write ECC_OpPtrB When executing primitive arithmetic operations, this Pointer defines where operand B is located in memory. 8 13 read-write ECC_OpPtrC When executing primitive arithmetic operations, this pointer defines the location where the result will be stored in Memory. 16 21 read-write CONTROL_REG Control register 0x8 32 read-write n 0x0 0x0 ECC_Start The Start signal is activated when all data and key inputs have been loaded in the external crypto memory and are available for processing. This signal is active high and is sampled on the rising edge of Clk. When this signal goes high, the PK Command present in the PK_CommandReg[] is initiated and executed. The PK_Start signal is ignored when the core is already processing data and is automatically cleared when the operation is finished 0 1 read-write STATUS_REG Status register 0xC 32 read-write n 0x0 0x0 ECC_Busy This Status Signal indicates that the core is processing data. This signal is active high and goes low when the selected algorithm is finished. 16 17 read-only ECC_Couple_NotValid Status signal set to 1 when couple x, y is not valid (i.e. not smaller than the prime). This flag is updated after execution of the command Check_Couple_Less_Prime. 6 7 read-only ECC_Fail_Address Address of the last Point detected as Not On Curve, Not Valid or at the infinity. 0 4 read-only ECC_NotInvertible This flag is set to 1 when executing a modular inversion (PK_CommandReg[3:0] = 0x6 or 0x9) if the operand is not invertible. 11 12 read-only ECC_Param_AB_NotValid Status signal set to 1 when parameters A and B are not valid, i.e 4A+ 27B = 0. This flag is updated after execution of the command Check_AB. 10 11 read-only ECC_Param_n_NotValid Status signal set to 1 when Parameter n is not valid. This flag is updated after execution of the command Check_n. 7 8 read-only ECC_Point_Px_AtInfinity Status signal set to 1 when Point Px is at the infinity. This flag is updated after execution of an ECC operation. 5 6 read-only ECC_Point_Px_NotOnCurve Status signal set to 1 when Point Px is not on the defined EC. This flag is updated after execution of the command Check_Point_OnCurve. 4 5 read-only ECC_PrimalityTestResult After the Miller-Rabin Primality test, this flag is: - set to 0 when the random number under test is probably prime - cleared to 1 when the random number under test is composite 12 13 read-only ECC_Signature_NotValid This flag indicates if the signature can be accepted or must be rejected. This flag is set to 1 when the signature is not valid and is updated after execution of the command ECDSA_Generation, ECDSA_Verification, DSA_Generation, DSA_Verification. 9 10 read-only VERSION_REG Version register 0x10 32 read-write n 0x0 0x0 ECC_HVN Version of IP to be read via CPU interface. 8 16 read-only ECC_SVN Version of Crypto code to be read via CPU interface.Note that this should be read before ECC is used since it corrupts its contents. 0 8 read-only FTDF FTDF registers Peripheral_Registers 0x0 0x0 0x11008 registers n BUILDTIME_0_REG Build time 0x10010 32 read-write n 0x0 0x0 BUILDTIME Build time of device 0 32 read-only BUILDTIME_1_REG Build time 0x10014 32 read-write n 0x0 0x0 BUILDTIME Build time of device 0 32 read-only BUILDTIME_2_REG Build time 0x10018 32 read-write n 0x0 0x0 BUILDTIME Build time of device 0 32 read-only BUILDTIME_3_REG Build time 0x1001C 32 read-write n 0x0 0x0 BUILDTIME Build time of device 0 32 read-only CE_REG Selection register events 0x10250 32 read-write n 0x0 0x0 FTDF_CE Composite serveice request from ftdf macro (see FR0400 in v40.100.2.41.pdf) Bit 0 = unused Bit 1 = rx interrupts Bit 2 = unused Bit 3 = miscelaneous interrupts Bit 4 = tx interrupts Bit 5 = Reserved 0 6 read-only CM_REG Mask selection register events 0x10254 32 read-write n 0x0 0x0 FTDF_CM mask bits for ftf_ce 0 6 read-write DEBUGCONTROL_REG Debug control register 0x10390 32 read-write n 0x0 0x0 DBG_RX_INPUT If set, the Rx debug interface will be selected as input for the Rx pipeline. 8 9 read-write EVENTCURRVAL_REG Value of event generator 0x10058 32 read-write n 0x0 0x0 EVENTCURRVAL Value of captured Event generator 0 32 read-only GLOB_CONTROL_0_REG Global control register 0x10020 32 read-write n 0x0 0x0 ISPANCOORDINATOR Enable/disable receiver check on address fields (0=enabled, 1=disabled) 1 2 read-write MACLEENABLED If set, Low Energy mode is enabled 17 18 read-write MACSIMPLEADDRESS Simple address of the PAN coordinator 8 16 read-write MACTSCHENABLED If set, TSCH mode is enabled 18 19 read-write RX_DMA_REQ Source of the RX_DMA_REQ output of this block. 2 3 read-write TX_DMA_REQ Source of the TX_DMA_REQ output of this block. 3 4 read-write GLOB_CONTROL_1_REG Global control register 0x10024 32 read-write n 0x0 0x0 MACPANID The values 0xFFFF indicates that the device is not associated 0 16 read-write MACSHORTADDRESS The values 0xFFFF and 0xFFFE indicate that no IEEE Short Address is available. The latter one is used if the device i 16 32 read-write GLOB_CONTROL_2_REG Global control register 0x10028 32 read-write n 0x0 0x0 AEXTENDEDADDRESS_L Unique device address, lower 32 bit 0 32 read-write GLOB_CONTROL_3_REG Global control register 0x1002C 32 read-write n 0x0 0x0 AEXTENDEDADDRESS_H Unique device address, higher 16 bit 0 32 read-write LMACRESET_REG Lmax reset register 0x10360 32 read-write n 0x0 0x0 LMACGLOBRESET_COUNT If set, the LMAC performance and traffic counters will be reset. Use this register for functionally reset these counters. 16 17 write-only LMACRESET_AHB LmacReset_ahb: A '1' Resets LMAC ahb interface (for debug and MLME-reset) 3 4 write-only LMACRESET_CONTROL LmacReset_control: A '1' Resets LMAC Controller (for debug and MLME-reset) 0 1 write-only LMACRESET_COUNT LmacReset_count: A '1' Resets LMAC mac counters (for debug and MLME-reset) 9 10 write-only LMACRESET_OREG LmacReset_oreg: A '1' Resets LMAC on_off regmap (for debug and MLME-reset) #$LmacReset_areg@on_off_regmap #LmacReset_areg: A '1' Resets LMAC always_on regmap (for debug and MLME-reset) 4 5 write-only LMACRESET_RX LmacReset_rx: A '1' Resets LMAC rx pipeline (for debug and MLME-reset) 1 2 write-only LMACRESET_SEC LmacReset_sec: A '1' Resets LMAC security (for debug and MLME-reset) #$LmacReset_wutim@on_off_regmap #LmacReset_wutim: A '1' Resets LMAC wake-up timer (for debug and MLME-reset) 7 8 write-only LMACRESET_TIMCTRL LmacReset_count: A '1' Resets LMAC timing control block (for debug and MLME-reset) 10 11 write-only LMACRESET_TSTIM LmacReset_tstim: A '1' Resets LMAC timestamp timer (for debug and MLME-reset) 6 7 write-only LMACRESET_TX LmacReset_tx: A '1' Resets LMAC tx pipeline (for debug and MLME-reset) 2 3 write-only LMAC_CONTROL_0_REG Lmac control register 0x10030 32 read-write n 0x0 0x0 KEEP_PHY_EN When the transmit or receive action is ready (LmacReady4Sleep will is set), the phy_en signal is cleared unless the control register keep_phy_en is set. When the control register keep_phy_en is set, the signal phy_en shall remain being set until the keep_phy_en is cleared. 31 32 read-write PTI Info to arbiter if phy_en is set 27 31 read-write RXALWAYSON If set, the receiver shall be always on if RxEnable is set 25 26 read-write RXONDURATION Time the Rx must be on 1 25 read-write LMAC_CONTROL_10_REG Lmac control register 0x1010C 32 read-write n 0x0 0x0 MACCSLMARGINRZ The UMAC can set the margin for the expected frame by control register macCSLmarginRZ (in 10 sym). So the LMAC will make sure the receiver is ready to receive data this amount of time earlier than to be expected by the received RZ time 16 20 read-write MACRZZEROVAL If the current RZtime is less or Equal to macRZzeroVal an RZtime with value zero is inserted in the wakeup frame 28 32 read-write MACWURZCORRECTION This register shall be used if the Wake-up frame to be transmitted is larger than 15 octets. It shall indicate the amount of extra data in a Wake-up frame after the RZ position in the frame (in 10 sym). 0 8 read-write LMAC_CONTROL_11_REG Lmac control register 0x1006C 32 read-write n 0x0 0x0 MACDISCARXOFFTORZ This switching off and on of the PHY Rx can be disabled whith the control register macDisCaRxOfftoRZ. 0 : Disabled 1 : Enabled 16 17 read-write MACRXTOTALCYCLETIME In order to make it easier to calculate if it is efficient to disable and enable the PHY Rx until the RZ time is reached, a control register indicates the time needed to disable and enable the PHY Rx: macRxTotalCycleTime (resolution in 10 sym) 0 16 read-write LMAC_CONTROL_1_REG Lmac control register 0x10040 32 read-write n 0x0 0x0 PHYRXATTR_CALCAP CalCap value. 8 12 read-write PHYRXATTR_CN Channel Number. 4 8 read-write PHYRXATTR_DEM_PTI DEM packet information. 0 4 read-write PHYRXATTR_HSI HighSide injection. 15 16 read-write PHYRXATTR_RF_GPIO_PINS Slot-basis signals mapped on GPIO via PPA. 12 15 read-write LMAC_CONTROL_2_REG Lmac control register 0x10044 32 read-write n 0x0 0x0 EDSCANDURATION Length of ED scan 8 32 read-write EDSCANENABLE if set, Energy Detect scan will be done 0 1 read-write LMAC_CONTROL_3_REG Lmac control register 0x10048 32 read-write n 0x0 0x0 CCAIDLEWAIT Time to wait after CCA returned and quot medium idle and quot before starting TX-ON (in us). Note: not applicable in TSCH mode since there macTSRxTx shall be used. 16 24 read-write MACMAXFRAMETOTALWAITTIME Max time to wait for a requested Data Frame or an announced broadcast frame 0 16 read-write LMAC_CONTROL_4_REG Lmac control register 0x10060 32 read-write n 0x0 0x0 PHYACKATTR_CALCAP CalCap value. 24 28 read-write PHYACKATTR_CN Channel Number. 20 24 read-write PHYACKATTR_DEM_PTI DEM packet information. 16 20 read-write PHYACKATTR_HSI HighSide injection. 31 32 read-write PHYACKATTR_RF_GPIO_PINS Slot-basis signals mapped on GPIO via PPA. 28 31 read-write PHYSLEEPWAIT Time between negate and assert PHY_EN When the signal phy_en is deasserted, it will not be asserted within the time phySleepWait. This time is indicated by the control register phySleepWait (resolution: ~s). 0 8 read-write RXPIPEPROPDELAY The control register RxPipePropDelay indicates the propagation delay in ~s of the Rx pipeline between the last symbol being captured at the DPHY interface and the and quot data valid and quot indication to the LMAC controller. 8 16 read-write LMAC_CONTROL_5_REG Lmac control register 0x10064 32 read-write n 0x0 0x0 ACK_RESPONSE_DELAY In order to have some flexibility the control register Ack_Response_Delay indicates the Acknowledge response time in ~s. The default value shall is 192 ~s (12 symbols). 0 8 read-write CCASTATWAIT The output CCASTAT is valid after 8 symbols + phyRxStartup. The 8 symbols are programmable by control registerCcaStatWait[4] in symbol timesl. Default value is 8d. 8 12 read-write PHYCSMACAATTR_CALCAP CalCap value. 24 28 read-write PHYCSMACAATTR_CN Channel Number. 20 24 read-write PHYCSMACAATTR_DEM_PTI DEM packet information. 16 20 read-write PHYCSMACAATTR_HSI HighSide injection. 31 32 read-write PHYCSMACAATTR_RF_GPIO_PINS Slot-basis signals mapped on GPIO via PPA. 28 31 read-write LMAC_CONTROL_6_REG Lmac control register 0x10068 32 read-write n 0x0 0x0 LIFSPERIOD The LIFS period is programmable by LifsPeriod (in symbols). The default is 40 symbols (640 ~s), 0 8 read-write SIFSPERIOD The SIFS period is programmable by SifsPeriod (in symbols). The default is 12 symbols (192 ~s). 8 16 read-write WUIFSPERIOD The WakeUp IFS period is programmable by WUifsPeriod (in symbols). The default is 12 symbols (192 ~s). 16 24 read-write LMAC_CONTROL_7_REG Lmac control register 0x10100 32 read-write n 0x0 0x0 MACCSLSAMPLEPERIOD When performing a idle listening, the receiver is enabled for at least macCSLsamplePeriod (in symbols). 16 32 read-write MACWUPERIOD Wake-up duration in symbols. 0 16 read-write LMAC_CONTROL_8_REG Lmac control register 0x10104 32 read-write n 0x0 0x0 MACCSLSTARTSAMPLETIME The control register macCSLstartSampleTime indicates the TimeStamp generator time (in symbols) when to start listening (called and quot idle listening and quot ). 0 32 read-write LMAC_CONTROL_9_REG Lmac control register 0x10108 32 read-write n 0x0 0x0 MACCSLDATAPERIOD After the wake-up sequence a frame is expected, the receiver will be enabled for at least a period of macCSLdataPeriod (in symbols). 0 16 read-write MACCSLFRAMEPENDINGWAITT If a non Wake-up frame with Frame Pending bit = '1' is received, the receiver is enabled for at least an extra period of macCSLFramePendingWaitT (in symbols) after the end of the received frame. The time the Enhanced ACK transmission lasts (if applicable) is included in this time. 16 32 read-write LMAC_CONTROL_DELTA_REG Lmac delta control register 0x10070 32 read-write n 0x0 0x0 GETGENERATORVAL_E Event which indicates the getGeneratorVal request is completed 5 6 read-write LMACREADY4SLEEP_D Delta bit for register and quot LmacReady4sleep and quot 1 2 read-write SYMBOLTIME2THR_E Event that symboltime counter matched SymbolTime2Thr 4 5 read-write SYMBOLTIMETHR_E Event that symboltime counter matched SymbolTimeThr 3 4 read-write SYNCTIMESTAMP_E The SyncTimeStamp_e event is set when the TimeStampgenerator is loaded with SyncTimeStampVal. This occurs at the rising edge of lp_clk when SyncTimeStampEna is set and the value of the Event generator is equal to the value SyncTimestampThr. 2 3 read-write WAKEUPTIMERENABLESTATUS_D Delta which indicates that WakeupTimerEnableStatus has changed 6 7 read-write LMAC_CONTROL_MASK_REG Lmac mask control register 0x10080 32 read-write n 0x0 0x0 GETGENERATORVAL_M Mask for getGeneratorVal_e 5 6 read-write LMACREADY4SLEEP_M Mask bit for delta bit and quot LmacReady4sleep_d and quot 1 2 read-write SYMBOLTIME2THR_M Mask for SymbolTime2Thr_e 4 5 read-write SYMBOLTIMETHR_M Mask for SymbolTimeThr_e 3 4 read-write SYNCTIMESTAMP_M Mask bit for event register SyncTimeStamp_e. 2 3 read-write WAKEUPTIMERENABLESTATUS_M Mask for WakeupTimerEnableStatus_d 6 7 read-write LMAC_CONTROL_OS_REG Lmac control register 0x10050 32 read-write n 0x0 0x0 GETGENERATORVAL If set, the current values of WU gen and TS gen will be captured. 0 1 write-only RXENABLE If set, receiving data may be done 1 2 write-only SINGLECCA If set, a single CCA will be performed. 2 3 write-only LMAC_CONTROL_STATUS_REG Lmac status register 0x10054 32 read-write n 0x0 0x0 CCASTAT Value single CCA when CCAstat_e is set. 2 3 read-only EDSCANVALUE Result of ED scan. 8 16 read-only LMACREADY4SLEEP Indicates that the LMAC is ready to go to sleep. 1 2 read-only WAKEUPTIMERENABLESTATUS Status of WakeupTimerEnable after being clocked by LP_CLK (showing it's effective value). 6 7 read-only LMAC_EVENT_REG Lmac event regsiter 0x10090 32 read-write n 0x0 0x0 CCASTAT_E If set, the single CCA is ready 1 2 read-write EDSCANREADY_E The event EdScanReady_e is set to notify that the ED scan is ready. 0 1 read-write RXTIMEREXPIRED_E Set if one of the timers enabling the RX-ON mode expires without having received any valid frame 2 3 read-write LMAC_MANUAL_1_REG Lmax manual PHY register 0x100A0 32 read-write n 0x0 0x0 LMAC_MANUAL_ED_REQUEST lmac_manual_ed_request controls the ED_REQUEST interface signal when lmac_manual_mode is set 5 6 read-write LMAC_MANUAL_MODE If the control register lmac_manual_mode is set, the LMAC controller control signals should be controlled by the lmac_manual_control registers 0 1 read-write LMAC_MANUAL_PHY_ATTR_CALCAP CalCap value. 24 28 read-write LMAC_MANUAL_PHY_ATTR_CN Channel Number. 20 24 read-write LMAC_MANUAL_PHY_ATTR_DEM_PTI DEM packet information. 16 20 read-write LMAC_MANUAL_PHY_ATTR_HSI HighSide injection. 31 32 read-write LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS Slot-basis signals mapped on GPIO via PPA. 28 31 read-write LMAC_MANUAL_PHY_EN lmac_manual_phy_en controls the PHY_EN interface signal when lmac_manual_mode is set 1 2 read-write LMAC_MANUAL_PTI lmac_manual_pti controls the PTI interface signal when lmac_manual_mode is set 8 12 read-write LMAC_MANUAL_RX_EN lmac_manual_rx_en controls the RX_EN interface signal when lmac_manual_mode is set 3 4 read-write LMAC_MANUAL_RX_PIPE_EN lmac_manual_rx_pipe_en controls the rx_enable signal towards the rx pipeline when lmac_manual_mode is set 4 5 read-write LMAC_MANUAL_TX_EN lmac_manual_tx_en controls the TX_EN interface signal when lmac_manual_mode is set 2 3 read-write LMAC_MANUAL_TX_FRM_NR lmac_manual_tx_frm_nr controls the entry in the tx buffer to be transmitted. 6 8 read-write LMAC_MANUAL_OS_REG One shot register triggers transmission in manual mode 0x100A4 32 read-write n 0x0 0x0 LMAC_MANUAL_TX_START One shot register which triggers the transmission of a frame from the tx buffer in lmac_manual_mode 0 1 write-only LMAC_MANUAL_STATUS_REG Lmac status register in manual mode 0x100A8 32 read-write n 0x0 0x0 LMAC_MANUAL_CCA_STAT lmac_manual_cca_stat shows the status of the CCA_STAT 0 1 read-only LMAC_MANUAL_ED_STAT lmac_manual_ed_stat shows the status of the ED_STAT interface signal. 8 16 read-only LMAC_MASK_REG Lmac mask register 0x10094 32 read-write n 0x0 0x0 CCASTAT_M Mask bit for event and quot CCAstat_e and quot 1 2 read-write EDSCANREADY_M Mask bit for event and quot EdScanReady_e and quot 0 1 read-write RXTIMEREXPIRED_M Mask bit for event and quot RxTimerExpired_e and quot 2 3 read-write MACACKWAITDURATION_REG Maximum time to wait for a ACK 0x10038 32 read-write n 0x0 0x0 MACACKWAITDURATION Max time to wait for a (normal) ACK 0 8 read-write MACENHACKWAITDURATION_REG Maximum time to wait for an enhanced ACK frame 0x1003C 32 read-write n 0x0 0x0 MACENHACKWAITDURATION The maximum time (in s) to wait for an enhanced acknowledgement frame 0 16 read-write MACFCSERRORCOUNT_REG Lmac FCS error register 0x10340 32 read-write n 0x0 0x0 MACFCSERRORCOUNT The number of received frames that were discarded due to an incorrect FCS. 0 32 read-only MACRXADDRFAILFRMCNT_REG Discarded frames register 0x10318 32 read-write n 0x0 0x0 MACRXADDRFAILFRMCNT Frames discarded due to incorrect address or PAN Id 0 32 read-only MACRXSTDACKFRMOKCNT_REG Received acknowledgment frames 0x10314 32 read-write n 0x0 0x0 MACRXSTDACKFRMOKCNT Standard Acknowledgment frames received 0 32 read-only MACRXUNSUPFRMCNT_REG Unsupported frames register 0x1031C 32 read-write n 0x0 0x0 MACRXUNSUPFRMCNT Frames which do pass the checks but are not supported 0 32 read-only MACTSTXACKDELAYVAL_REG Time left until next ACK is sent (us) 0x10078 32 read-write n 0x0 0x0 MACTSTXACKDELAYVAL The time in us left until the ack frame is sent by the lmac 0 16 read-only MACTXSTDACKFRMCNT_REG Transmitted acknowledgment frames 0x10310 32 read-write n 0x0 0x0 MACTXSTDACKFRMCNT Standard Acknowledgment frames transmitted 0 32 read-only PHY_PARAMETERS_0_REG Lmac PHY parameter register 0x10180 32 read-write n 0x0 0x0 RXBITPOS_0 Control rxBitPos(8)(3) controls the position that a bit should have at the DPHY interface. So the default values are rxBitPos_0 = 0, rxBitPos_1 = 1, rxBitPos_2 = 2, etc. Note1 that this is a conversion from rx DPHY interface to the internal data byte So for(n=7 n>=0 n--) rx_data(n) = dphy_bit(tx_BitPos(n)) endfor Note2 that rxBitPos and txBitPos must have inverse functions. 0 3 read-write RXBITPOS_1 See rxBitPos_0 4 7 read-write RXBITPOS_2 See rxBitPos_0 8 11 read-write RXBITPOS_3 See rxBitPos_0 12 15 read-write RXBITPOS_4 See rxBitPos_0 16 19 read-write RXBITPOS_5 See rxBitPos_0 20 23 read-write RXBITPOS_6 See rxBitPos_0 24 27 read-write RXBITPOS_7 See rxBitPos_0 28 31 read-write PHY_PARAMETERS_1_REG Lmac PHY parameter register 0x10184 32 read-write n 0x0 0x0 TXBITPOS_0 Control txBitPos(8)(3) controls the position that a bit should have at the DPHY interface. So the default values are txBitPos_0 = 0, txBitPos_1 = 1, txBitPos_2 = 2, etc. Note1 that this is a conversion from internal data byte to the DPHY interface. So for(n=7 n>=0 n--) tx_dphy_bit(n) = tx_data(tx_BitPos(n)) endfor Note2 that txBitPos and rxBitPos must have inverse functions. 0 3 read-write TXBITPOS_1 See txBitPos_0 4 7 read-write TXBITPOS_2 See txBitPos_0 8 11 read-write TXBITPOS_3 See txBitPos_0 12 15 read-write TXBITPOS_4 See txBitPos_0 16 19 read-write TXBITPOS_5 See txBitPos_0 20 23 read-write TXBITPOS_6 See txBitPos_0 24 27 read-write TXBITPOS_7 See txBitPos_0 28 31 read-write PHY_PARAMETERS_2_REG Lmac PHY parameter register 0x10188 32 read-write n 0x0 0x0 PHYTRXWAIT Phy wait time between TX_EN/RX_EN 24 32 read-write PHYTXFINISH Phy wait time before deasserting TX_EN 16 24 read-write PHYTXLATENCY Phy delay between DPHY i/f and air 8 16 read-write PHYTXSTARTUP Phy wait time before transmission 0 8 read-write PHY_PARAMETERS_3_REG Lmac PHY parameter register 0x1018C 32 read-write n 0x0 0x0 PHYENABLE Asserting the DPHY interface signals TX_EN or RX_EN does not take place within the time phyEnable after asserting the signal phy_en. (resolution: ~s). 16 24 read-write PHYRXLATENCY Phy delay between air and DPHY i/f 8 16 read-write PHYRXSTARTUP Phy wait time before receiving 0 8 read-write REL_NAME_0_REG Name of the release 0x10000 32 read-write n 0x0 0x0 REL_NAME Name of the release 0 32 read-only REL_NAME_1_REG Name of the release 0x10004 32 read-write n 0x0 0x0 REL_NAME Name of the release 0 32 read-only REL_NAME_2_REG Name of the release 0x10008 32 read-write n 0x0 0x0 REL_NAME Name of the release 0 32 read-only REL_NAME_3_REG Name of the release 0x1000C 32 read-write n 0x0 0x0 REL_NAME Name of the release 0 32 read-only RX_CONTROL_0_REG Receive control register 0x10200 32 read-write n 0x0 0x0 DBGRXTRANSPARENTMODE If set, Rx pipe is fully set in transparent mode (for debug purpose). 0 1 read-write DISDATAREQUESTCA When the control register DisDataRequestCa is set, the notification of the received Data Request is disabled. 10 11 read-write DISRXACKRECEIVEDCA If set, the LMAC controller shall ignore all consequent actions upon a set AR bit in the transmitted frame 27 28 read-write DISRXACKREQUESTCA When the control register DisRxAckRequestca is set all consequent actions for a received Acknowledge Request bit are disabled. 8 9 read-write DISRXFRMPENDINGCA Whan the control register DisRxFrmPendingCa is set, the notification of the received FP bit to the LMAC Controller is disabled. 7 8 read-write MACALWAYSPASSBEACONWRONGPANID If the control register macAlwaysPassBeaconWrongPANId is set, the frame is not dropped in case of a mismatch in PAN-ID, irrespective of the setting of RxBeaconOnly. 14 15 read-write MACALWAYSPASSCRCERROR If set, a FCS error will not drop the frame 9 10 read-write MACALWAYSPASSFRMTYPE The control registers macAlwaysPassFrmType[7:0], shall control if this Frame Type shall be dropped. If a bit is set, the Frame Type corresponding with the bit position is not dropped, even in case of a CRC error. Example: if bit 1 is set, Frame Type 1 shall not be dropped. The error shall be reported in the Rx meta data 16 24 read-write MACALWAYSPASSRESFRAMEVERSION If set, a packet with a reserved FrameVersion shall not be dropped 11 12 read-write MACALWAYSPASSTOPANCOORDINATOR When the control register macAlwaysPassToPanCoordinator is set, the frame is not dropped due to a span_coord_error. However, in case of an FCS error, the packet is dropped. 15 16 read-write MACALWAYSPASSWAKEUP If the control register macAlwaysPassWakeUp is set, received Wake- up frames for this device are put into the Rx packet buffer without notifying the LMAC Controller. 24 25 read-write MACALWAYSPASSWRONGDADDR If set, a packet with a wrong DAddr is not dropped 13 14 read-write MACALWAYSPASSWRONGDPANID If register macAlwaysPassWrongDPANId is set, packet with a wrong Destiantion PanID will not be dropped. However, in case of an FCS error, the packet is dropped. 12 13 read-write MACIMPLICITBROADCAST If set, Frame Version 2 frames without Daddr or DPANId shall be accepted. 26 27 read-write MACPASSWAKEUP If set, WakeUp frames will not be reported but will be put into the Rx buffer. 25 26 read-write RXBEACONONLY If set, only Beacons frames are accepted 1 2 read-write RXCOORDREALIGNONLY If set, only Coordinator Realignment frames are accepted 2 3 read-write RX_READ_BUF_PTR Indication where new data will be read All four bits shall be used when using these pointer values (0d - 15d). However, the Receive Packet buffer has a size of 8 entries. So reading the Receive Packet buffer entries shall use the mod8 of the pointer values. 3 7 read-write RX_EVENT_REG Receive event register 0x10204 32 read-write n 0x0 0x0 RXBYTE_E Indicates the first byte of a new packet is received 3 4 read-write RXSOF_E Set when RX_SOF has been detected. 0 1 read-write RX_BUF_AVAIL_E Indicates that a new packet is received 2 3 read-write RX_OVERFLOW_E Indicates that the Rx packet buffer has an overflowl 1 2 read-write RX_FIFO_0_0_REG Address receive fifo 0 0x8000 32 read-write n 0x0 0x0 RX_FIFO Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported. 0 32 read-write RX_FIFO_1_0_REG Address transmit fifo 1 0x8080 32 read-write n 0x0 0x0 RX_FIFO Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported. 0 32 read-write RX_FIFO_2_0_REG Address transmit fifo 2 0x8100 32 read-write n 0x0 0x0 RX_FIFO Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported. 0 32 read-write RX_FIFO_3_0_REG Address transmit fifo 3 0x8180 32 read-write n 0x0 0x0 RX_FIFO Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported. 0 32 read-write RX_FIFO_4_0_REG Address transmit fifo 4 0x8200 32 read-write n 0x0 0x0 RX_FIFO Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported. 0 32 read-write RX_FIFO_5_0_REG Address transmit fifo 5 0x8280 32 read-write n 0x0 0x0 RX_FIFO Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported. 0 32 read-write RX_FIFO_6_0_REG Address transmit fifo 6 0x8300 32 read-write n 0x0 0x0 RX_FIFO Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported. 0 32 read-write RX_FIFO_7_0_REG Address transmit fifo 7 0x8380 32 read-write n 0x0 0x0 RX_FIFO Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported. 0 32 read-write RX_MASK_REG Receive event mask register 0x10208 32 read-write n 0x0 0x0 RXBYTE_M Mask bit for event and quot rxbyte_e and quot . 3 4 read-write RXSOF_M Mask bit for event and quot RxSof_e and quot . 0 1 read-write RX_BUF_AVAIL_M Mask bit for event and quot rx_buf_avail_e and quot . 2 3 read-write RX_OVERFLOW_M Mask bit for event and quot rx_overflow_e and quot . 1 2 read-write RX_META_0_0_REG Receive metadata register 0 0x280 32 read-write n 0x0 0x0 RX_TIMESTAMP Timestamp taken when frame was received 0 32 read-only RX_META_0_1_REG Receive metadata register 1 0x290 32 read-write n 0x0 0x0 RX_TIMESTAMP Timestamp taken when frame was received 0 32 read-only RX_META_0_2_REG Receive metadata register 2 0x2A0 32 read-write n 0x0 0x0 RX_TIMESTAMP Timestamp taken when frame was received 0 32 read-only RX_META_0_3_REG Receive metadata register 3 0x2B0 32 read-write n 0x0 0x0 RX_TIMESTAMP Timestamp taken when frame was received 0 32 read-only RX_META_0_4_REG Receive metadata register 4 0x2C0 32 read-write n 0x0 0x0 RX_TIMESTAMP Timestamp taken when frame was received 0 32 read-only RX_META_0_5_REG Receive metadata register 5 0x2D0 32 read-write n 0x0 0x0 RX_TIMESTAMP Timestamp taken when frame was received 0 32 read-only RX_META_0_6_REG Receive metadata register 6 0x2E0 32 read-write n 0x0 0x0 RX_TIMESTAMP Timestamp taken when frame was received 0 32 read-only RX_META_0_7_REG Receive metadata register 7 0x2F0 32 read-write n 0x0 0x0 RX_TIMESTAMP Timestamp taken when frame was received 0 32 read-only RX_META_1_0_REG Receive metadata register 0 0x284 32 read-write n 0x0 0x0 CRC16_ERROR CRC error, applicable for transparent mode only 0 1 read-only DADDR_ERROR D Address error, applicable when frame is not discarded 5 6 read-only DPANID_ERROR D PAN ID error, applicable when frame is not discarded 4 5 read-only ISPANID_COORD_ERROR Received frame not for PAN coordinator, applicable when frame is not discarded 7 8 read-only QUALITY_INDICATOR Link Quality Indication # $software_scratch@retention_ram # TX ram not used by hardware, can be used by software as scratch ram with retention. 8 16 read-only RES_FRM_TYPE_ERROR Not supported frame type error, applicable when frame is not discarded 2 3 read-only RES_FRM_VERSION_ERROR Not supported frame version error, applicable when frame is not discarded. 3 4 read-only SPANID_ERROR PAN ID error, applicable when frame is not discarded 6 7 read-only RX_META_1_1_REG Receive metadata register 1 0x294 32 read-write n 0x0 0x0 CRC16_ERROR CRC error, applicable for transparent mode only 0 1 read-only DADDR_ERROR D Address error, applicable when frame is not discarded 5 6 read-only DPANID_ERROR D PAN ID error, applicable when frame is not discarded 4 5 read-only ISPANID_COORD_ERROR Received frame not for PAN coordinator, applicable when frame is not discarded 7 8 read-only QUALITY_INDICATOR Link Quality Indication # $software_scratch@retention_ram # TX ram not used by hardware, can be used by software as scratch ram with retention. 8 16 read-only RES_FRM_TYPE_ERROR Not supported frame type error, applicable when frame is not discarded 2 3 read-only RES_FRM_VERSION_ERROR Not supported frame version error, applicable when frame is not discarded. 3 4 read-only SPANID_ERROR PAN ID error, applicable when frame is not discarded 6 7 read-only RX_META_1_2_REG Receive metadata register 2 0x2A4 32 read-write n 0x0 0x0 CRC16_ERROR CRC error, applicable for transparent mode only 0 1 read-only DADDR_ERROR D Address error, applicable when frame is not discarded 5 6 read-only DPANID_ERROR D PAN ID error, applicable when frame is not discarded 4 5 read-only ISPANID_COORD_ERROR Received frame not for PAN coordinator, applicable when frame is not discarded 7 8 read-only QUALITY_INDICATOR Link Quality Indication # $software_scratch@retention_ram # TX ram not used by hardware, can be used by software as scratch ram with retention. 8 16 read-only RES_FRM_TYPE_ERROR Not supported frame type error, applicable when frame is not discarded 2 3 read-only RES_FRM_VERSION_ERROR Not supported frame version error, applicable when frame is not discarded. 3 4 read-only SPANID_ERROR PAN ID error, applicable when frame is not discarded 6 7 read-only RX_META_1_3_REG Receive metadata register 3 0x2B4 32 read-write n 0x0 0x0 CRC16_ERROR CRC error, applicable for transparent mode only 0 1 read-only DADDR_ERROR D Address error, applicable when frame is not discarded 5 6 read-only DPANID_ERROR D PAN ID error, applicable when frame is not discarded 4 5 read-only ISPANID_COORD_ERROR Received frame not for PAN coordinator, applicable when frame is not discarded 7 8 read-only QUALITY_INDICATOR Link Quality Indication # $software_scratch@retention_ram # TX ram not used by hardware, can be used by software as scratch ram with retention. 8 16 read-only RES_FRM_TYPE_ERROR Not supported frame type error, applicable when frame is not discarded 2 3 read-only RES_FRM_VERSION_ERROR Not supported frame version error, applicable when frame is not discarded. 3 4 read-only SPANID_ERROR PAN ID error, applicable when frame is not discarded 6 7 read-only RX_META_1_4_REG Receive metadata register 4 0x2C4 32 read-write n 0x0 0x0 CRC16_ERROR CRC error, applicable for transparent mode only 0 1 read-only DADDR_ERROR D Address error, applicable when frame is not discarded 5 6 read-only DPANID_ERROR D PAN ID error, applicable when frame is not discarded 4 5 read-only ISPANID_COORD_ERROR Received frame not for PAN coordinator, applicable when frame is not discarded 7 8 read-only QUALITY_INDICATOR Link Quality Indication # $software_scratch@retention_ram # TX ram not used by hardware, can be used by software as scratch ram with retention. 8 16 read-only RES_FRM_TYPE_ERROR Not supported frame type error, applicable when frame is not discarded 2 3 read-only RES_FRM_VERSION_ERROR Not supported frame version error, applicable when frame is not discarded. 3 4 read-only SPANID_ERROR PAN ID error, applicable when frame is not discarded 6 7 read-only RX_META_1_5_REG Receive metadata register 5 0x2D4 32 read-write n 0x0 0x0 CRC16_ERROR CRC error, applicable for transparent mode only 0 1 read-only DADDR_ERROR D Address error, applicable when frame is not discarded 5 6 read-only DPANID_ERROR D PAN ID error, applicable when frame is not discarded 4 5 read-only ISPANID_COORD_ERROR Received frame not for PAN coordinator, applicable when frame is not discarded 7 8 read-only QUALITY_INDICATOR Link Quality Indication # $software_scratch@retention_ram # TX ram not used by hardware, can be used by software as scratch ram with retention. 8 16 read-only RES_FRM_TYPE_ERROR Not supported frame type error, applicable when frame is not discarded 2 3 read-only RES_FRM_VERSION_ERROR Not supported frame version error, applicable when frame is not discarded. 3 4 read-only SPANID_ERROR PAN ID error, applicable when frame is not discarded 6 7 read-only RX_META_1_6_REG Receive metadata register 6 0x2E4 32 read-write n 0x0 0x0 CRC16_ERROR CRC error, applicable for transparent mode only 0 1 read-only DADDR_ERROR D Address error, applicable when frame is not discarded 5 6 read-only DPANID_ERROR D PAN ID error, applicable when frame is not discarded 4 5 read-only ISPANID_COORD_ERROR Received frame not for PAN coordinator, applicable when frame is not discarded 7 8 read-only QUALITY_INDICATOR Link Quality Indication # $software_scratch@retention_ram # TX ram not used by hardware, can be used by software as scratch ram with retention. 8 16 read-only RES_FRM_TYPE_ERROR Not supported frame type error, applicable when frame is not discarded 2 3 read-only RES_FRM_VERSION_ERROR Not supported frame version error, applicable when frame is not discarded. 3 4 read-only SPANID_ERROR PAN ID error, applicable when frame is not discarded 6 7 read-only RX_META_1_7_REG Receive metadata register 7 0x2F4 32 read-write n 0x0 0x0 CRC16_ERROR CRC error, applicable for transparent mode only 0 1 read-only DADDR_ERROR D Address error, applicable when frame is not discarded 5 6 read-only DPANID_ERROR D PAN ID error, applicable when frame is not discarded 4 5 read-only ISPANID_COORD_ERROR Received frame not for PAN coordinator, applicable when frame is not discarded 7 8 read-only QUALITY_INDICATOR Link Quality Indication # $software_scratch@retention_ram # TX ram not used by hardware, can be used by software as scratch ram with retention. 8 16 read-only RES_FRM_TYPE_ERROR Not supported frame type error, applicable when frame is not discarded 2 3 read-only RES_FRM_VERSION_ERROR Not supported frame version error, applicable when frame is not discarded. 3 4 read-only SPANID_ERROR PAN ID error, applicable when frame is not discarded 6 7 read-only RX_STATUS_DELTA_REG Receive status delta register 0x10220 32 read-write n 0x0 0x0 RX_BUFF_IS_FULL_D Delta bit of status and quot rx_buff_is_full and quot 0 1 read-write RX_STATUS_MASK_REG Receive status delta mask register 0x10224 32 read-write n 0x0 0x0 RX_BUFF_IS_FULL_M Mask bit of status and quot rx_buff_is_full and quot 0 1 read-write RX_STATUS_REG Receive status register 0x1020C 32 read-write n 0x0 0x0 RX_BUFF_IS_FULL Indicates that the Rx packet buffer is full 0 1 read-only RX_WRITE_BUF_PTR Indication where new data will be written. All four bits shall be used when using these pointer values (0d - 15d). However, the Receive Packet buffer has a size of 8 entries. So reading the Receive Packet buffer entries shall use the mod8 of the pointer values. 1 5 read-only SECKEY_0_REG Seckey register 0x10118 32 read-write n 0x0 0x0 SECKEY_0 Registers secKey[0..3] contain the key to be used. 0 32 read-write SECKEY_1_REG Seckey register 0x1011C 32 read-write n 0x0 0x0 SECKEY_1 See register and quot secKey_0 and quot 0 32 read-write SECKEY_2_REG SecKey register 0x10120 32 read-write n 0x0 0x0 SECKEY_2 See register and quot secKey_0 and quot 0 32 read-write SECKEY_3_REG Seckey register 0x10124 32 read-write n 0x0 0x0 SECKEY_3 See register and quot secKey_0 and quot 0 32 read-write SECNONCE_0_REG Nonce register used for encryption/decryption 0x10128 32 read-write n 0x0 0x0 SECNONCE_0 Register secNonce[0..3] contains the Nonce to be used for encryption/decryption. 0 32 read-write SECNONCE_1_REG Nonce register used for encryption/decryption 0x1012C 32 read-write n 0x0 0x0 SECNONCE_1 See register and quot Nonce_0 and quot 0 32 read-write SECNONCE_2_REG Nonce register used for encryption/decryption 0x10130 32 read-write n 0x0 0x0 SECNONCE_2 See register and quot Nonce_0 and quot 0 32 read-write SECNONCE_3_REG Nonce register used for encryption/decryption 0x10134 32 read-write n 0x0 0x0 SECNONCE_3 See register and quot Nonce_0 and quot 0 8 read-write SECURITY_0_REG Security register 0x10110 32 read-write n 0x0 0x0 SECALENGTH The length of the a_data is indicated by control register secAlength. The end of the a_data is the start point of the m_data. (So secAlength must also be set if security level==4) 16 23 read-write SECENCDECN The control register secEncDecn indicates whether to encrypt ('1') or decrypt ('0') the data. 31 32 read-write SECENTRY The UMAC shall indicate by control registers secEntry and secTxRxn which entry to use and if it's from the Tx or Rx buffer ('1' resp. '0'). 8 12 read-write SECMLENGTH The length of the m_data is indicated by control register secMlength. 24 31 read-write SECTXRXN See register and quot secEntry and quot 1 2 read-write SECURITY_1_REG Security register 0x10114 32 read-write n 0x0 0x0 SECAUTHFLAGS Register secAuthFlags contains the authentication flags fields. bit[7] is '0' bit[6] is and quot A_data present and quot bit[5:3]: 3-bit security level of m_data bit[2:0]: 3-bit security level of a_data. 0 8 read-write SECENCRFLAGS Register secEncrFlags contain the encryption flags field. Bits [2:0] are the 3-bit encoding flags of a_data, the other bits msut be set to '0'. 8 16 read-write SECURITY_EVENTMASK_REG security event mask register 0x10154 32 read-write n 0x0 0x0 SECREADY_M Mask bit for event and quot secReady_e and quot . 0 1 read-write SECURITY_EVENT_REG security event register 0x10150 32 read-write n 0x0 0x0 SECREADY_E The Event bit secReady_e is set when the authentication process is ready (i.e. secBusy is cleared). This Event shall contribute to the gen_irq. 0 1 read-write SECURITY_OS_REG One shot register to start encryption/decryption 0x10138 32 read-write n 0x0 0x0 SECABORT See register and quot Nonce_0 and quot 0 1 write-only SECSTART One_shot register to start the encryption, decryption and authentication support task. 1 2 write-only SECURITY_STATUS_REG Security status register 0x10140 32 read-write n 0x0 0x0 SECAUTHFAIL In case of decryption, the status bit secAuthFail will be set when the authentication has failed. 1 2 read-only SECBUSY Register and quot secBusy and quot indicates if the encryption/decryption process is still running. 0 1 read-only SYMBOLTIME2THR_REG Symboltime threshold register 2 0x10384 32 read-write n 0x0 0x0 SYMBOLTIME2THR Symboltime 2 Threshold to generate a general interrupt 0 32 read-write SYMBOLTIMESNAPSHOTVAL_REG Value timestamp generator 0x10210 32 read-write n 0x0 0x0 SYMBOLTIMESNAPSHOTVAL The Status register SymbolTimeSnapshotVal indicates the actual value of the TimeStamp generator. 0 32 read-only SYMBOLTIMETHR_REG Symboltime threshold register 1 0x10380 32 read-write n 0x0 0x0 SYMBOLTIMETHR Symboltime Threshold to generate a general interrupt 0 32 read-write SYNCTIMESTAMPPHASEVAL_REG Timestamp phase value regsiter 0x10320 32 read-write n 0x0 0x0 SYNCTIMESTAMPPHASEVAL Value to sync TS gen phase within a symbol with. Please note the +1 correction needed for most accurate result (+0.5 is than the average error, resulting is a just too fast clock). 0 8 read-write SYNCTIMESTAMPTHR_REG Threshold timestamp generator 0x10304 32 read-write n 0x0 0x0 SYNCTIMESTAMPTHR Threshold for synchronize TS gen. Note that due to implementation this register may only be written once per two LP_CLK periods. 0 32 read-write SYNCTIMESTAMPVAL_REG Value timestamp generator 0x10308 32 read-write n 0x0 0x0 SYNCTIMESTAMPVAL Value to sync TS gen with. 0 32 read-write TIMER_CONTROL_1_REG Timer control register 0x1030C 32 read-write n 0x0 0x0 SYNCTIMESTAMPENA If set, the TimeStampThr is enabled to generate a sync of the TS gen. 1 2 read-write TIMESTAMPCURRPHASEVAL_REG Value of timestamp generator phase within a symbol 0x10074 32 read-write n 0x0 0x0 TIMESTAMPCURRPHASEVAL Value of captured TS gen phase within a symbol 0 8 read-only TIMESTAMPCURRVAL_REG Value of timestamp generator 0x1005C 32 read-write n 0x0 0x0 TIMESTAMPCURRVAL Value of captured TS gen 0 32 read-only TSCH_CONTROL_0_REG Lmac tsch control register 0x10160 32 read-write n 0x0 0x0 MACTSRXWAIT The times to wait for start of frame 16 32 read-write MACTSTXACKDELAY End of Rx frame to start of Ack 0 16 read-write TSCH_CONTROL_1_REG Lmac tsch control register 0x10164 32 read-write n 0x0 0x0 MACTSRXTX The time between the CCA and the TX of a frame 0 16 read-write TSCH_CONTROL_2_REG Lmac tsch control register 0x10168 32 read-write n 0x0 0x0 MACTSACKWAIT The minimum time to wait for start of an Acknowledgement 16 32 read-write MACTSRXACKDELAY End of frame to when the transmitter shall listen for Acknowledgement 0 16 read-write TXBYTE_E_REG Transmit first byte register 0x10394 32 read-write n 0x0 0x0 TXBYTE_E Indicates the first byte of a frame is transmitted 0 1 read-write TX_LAST_SYMBOL_E Indicates the last symbol of a frame is transmitted 1 2 read-write TXBYTE_M_REG Transmit first byte mask register 0x10398 32 read-write n 0x0 0x0 TXBYTE_M Mask bit for event and quot txbyte_e and quot . 0 1 read-write TX_LAST_SYMBOL_M Mask bit for event and quot tx_last_symbol_e and quot . 1 2 read-write TXPIPEPROPDELAY_REG Prop delay transmit register 0x10034 32 read-write n 0x0 0x0 TXPIPEPROPDELAY Prop delay of tx pipe, start to DPHY 0 8 read-write TX_CLEAR_OS_REG One shot register to clear flag 0x10484 32 read-write n 0x0 0x0 TX_FLAG_CLEAR To clear tx_flag_stat 0 4 write-only TX_CONTROL_0_REG Transmit control register 0x10240 32 read-write n 0x0 0x0 DBGTXTRANSPARENTMODE If 1, the MPDU octets pass transparently through the MAC in the transmit direction (for debug purpose). 0 1 read-write MACMAXBE Maximum Backoff Exponent (range 3-8) 4 8 read-write MACMAXCSMABACKOFFS Maximum number of CSMA-CA backoffs (range 0-5) 12 15 read-write MACMINBE Minimum Backoff Exponent (range 0-macMaxBE) 8 12 read-write TX_FIFO_0_0_REG Address transmit fifo 0 0x0 32 read-write n 0x0 0x0 TX_FIFO Transmit fifo buffer, contains 32 addresses per entry (32b x 32a = 128B). There are 4 entries supported. 0 32 read-write TX_FIFO_1_0_REG Address transmit fifo 1 0x80 32 read-write n 0x0 0x0 TX_FIFO Transmit fifo buffer, contains 32 addresses per entry (32b x 32a = 128B). There are 4 entries supported. 0 32 read-write TX_FIFO_2_0_REG Address transmit fifo 2 0x100 32 read-write n 0x0 0x0 TX_FIFO Transmit fifo buffer, contains 32 addresses per entry (32b x 32a = 128B). There are 4 entries supported. 0 32 read-write TX_FIFO_3_0_REG Address transmit fifo 3 0x180 32 read-write n 0x0 0x0 TX_FIFO Transmit fifo buffer, contains 32 addresses per entry (32b x 32a = 128B). There are 4 entries supported. 0 32 read-write TX_FLAG_CLEAR_E_0_REG Clear flag register 0 0x10404 32 read-write n 0x0 0x0 TX_FLAG_CLEAR_E When the LMAC clears the tx_flag_stat status event bit tx_flag_clear_e is set. 0 1 read-write TX_FLAG_CLEAR_E_1_REG Clear flag register 1 0x10424 32 read-write n 0x0 0x0 TX_FLAG_CLEAR_E When the LMAC clears the tx_flag_stat status event bit tx_flag_clear_e is set. 0 1 read-write TX_FLAG_CLEAR_E_2_REG Clear flag register 2 0x10444 32 read-write n 0x0 0x0 TX_FLAG_CLEAR_E When the LMAC clears the tx_flag_stat status event bit tx_flag_clear_e is set. 0 1 read-write TX_FLAG_CLEAR_E_3_REG Clear flag register 3 0x10464 32 read-write n 0x0 0x0 TX_FLAG_CLEAR_E When the LMAC clears the tx_flag_stat status event bit tx_flag_clear_e is set. 0 1 read-write TX_FLAG_CLEAR_M_0_REG Mask flag register 0 0x10408 32 read-write n 0x0 0x0 TX_FLAG_CLEAR_M Mask bit for event and quot tx_flag_clear_e and quot . 0 1 read-write TX_FLAG_CLEAR_M_1_REG Mask flag register 1 0x10428 32 read-write n 0x0 0x0 TX_FLAG_CLEAR_M Mask bit for event and quot tx_flag_clear_e and quot . 0 1 read-write TX_FLAG_CLEAR_M_2_REG Clear flag register 2 0x10448 32 read-write n 0x0 0x0 TX_FLAG_CLEAR_M Mask bit for event and quot tx_flag_clear_e and quot . 0 1 read-write TX_FLAG_CLEAR_M_3_REG Clear flag register 3 0x10468 32 read-write n 0x0 0x0 TX_FLAG_CLEAR_M Mask bit for event and quot tx_flag_clear_e and quot . 0 1 read-write TX_FLAG_S_0_REG Transmit packet ready for transmission register 0 0x10400 32 read-write n 0x0 0x0 TX_FLAG_STAT Packet is ready for transmission 0 1 read-only TX_FLAG_S_1_REG Transmit packet ready for transmission register 1 0x10420 32 read-write n 0x0 0x0 TX_FLAG_STAT Packet is ready for transmission 0 1 read-only TX_FLAG_S_2_REG Transmit packet ready for transmission register 2 0x10440 32 read-write n 0x0 0x0 TX_FLAG_STAT Packet is ready for transmission 0 1 read-only TX_FLAG_S_3_REG Transmit packet ready for transmission register 3 0x10460 32 read-write n 0x0 0x0 TX_FLAG_STAT Packet is ready for transmission 0 1 read-only TX_META_DATA_0_0_REG Transmit metadata register 0 0x200 32 read-write n 0x0 0x0 ACKREQUEST Indicates whether an acknowledge is expected from the recipient of this packet. 28 29 read-write CRC16_ENA Indicates whether CRC16 insertion must be enabled or not. 0 : No hardware inserted CRC16 1 : Hardware inserts CRC16 30 31 read-write CSMACA_ENA Indicates whether a CSMA-CA is required for the transmission of this packet. 26 27 read-write FRAMETYPE Data/Cmd/Ack etc. Also indicate wakeup frame 23 26 read-write FRAME_LENGTH Frame length 0 7 read-write PHYATTR_CALCAP CalCap value. 15 19 read-write PHYATTR_CN Channel Number. 11 15 read-write PHYATTR_DEM_PTI DEM packet information. 7 11 read-write PHYATTR_HSI HighSide injection. 22 23 read-write PHYATTR_RF_GPIO_PINS Slot-basis signals mapped on GPIO via PPA. 19 22 read-write TX_META_DATA_0_1_REG Transmit metadata register 1 0x210 32 read-write n 0x0 0x0 ACKREQUEST Indicates whether an acknowledge is expected from the recipient of this packet. 28 29 read-write CRC16_ENA Indicates whether CRC16 insertion must be enabled or not. 0 : No hardware inserted CRC16 1 : Hardware inserts CRC16 30 31 read-write CSMACA_ENA Indicates whether a CSMA-CA is required for the transmission of this packet. 26 27 read-write FRAMETYPE Data/Cmd/Ack etc. Also indicate wakeup frame 23 26 read-write FRAME_LENGTH Frame length 0 7 read-write PHYATTR_CALCAP CalCap value. 15 19 read-write PHYATTR_CN Channel Number. 11 15 read-write PHYATTR_DEM_PTI DEM packet information. 7 11 read-write PHYATTR_HSI HighSide injection. 22 23 read-write PHYATTR_RF_GPIO_PINS Slot-basis signals mapped on GPIO via PPA. 19 22 read-write TX_META_DATA_0_2_REG Transmit metadata register 2 0x220 32 read-write n 0x0 0x0 ACKREQUEST Indicates whether an acknowledge is expected from the recipient of this packet. 28 29 read-write CRC16_ENA Indicates whether CRC16 insertion must be enabled or not. 0 : No hardware inserted CRC16 1 : Hardware inserts CRC16 30 31 read-write CSMACA_ENA Indicates whether a CSMA-CA is required for the transmission of this packet. 26 27 read-write FRAMETYPE Data/Cmd/Ack etc. Also indicate wakeup frame 23 26 read-write FRAME_LENGTH Frame length 0 7 read-write PHYATTR_CALCAP CalCap value. 15 19 read-write PHYATTR_CN Channel Number. 11 15 read-write PHYATTR_DEM_PTI DEM packet information. 7 11 read-write PHYATTR_HSI HighSide injection. 22 23 read-write PHYATTR_RF_GPIO_PINS Slot-basis signals mapped on GPIO via PPA. 19 22 read-write TX_META_DATA_0_3_REG Transmit metadata register 3 0x230 32 read-write n 0x0 0x0 ACKREQUEST Indicates whether an acknowledge is expected from the recipient of this packet. 28 29 read-write CRC16_ENA Indicates whether CRC16 insertion must be enabled or not. 0 : No hardware inserted CRC16 1 : Hardware inserts CRC16 30 31 read-write CSMACA_ENA Indicates whether a CSMA-CA is required for the transmission of this packet. 26 27 read-write FRAMETYPE Data/Cmd/Ack etc. Also indicate wakeup frame 23 26 read-write FRAME_LENGTH Frame length 0 7 read-write PHYATTR_CALCAP CalCap value. 15 19 read-write PHYATTR_CN Channel Number. 11 15 read-write PHYATTR_DEM_PTI DEM packet information. 7 11 read-write PHYATTR_HSI HighSide injection. 22 23 read-write PHYATTR_RF_GPIO_PINS Slot-basis signals mapped on GPIO via PPA. 19 22 read-write TX_META_DATA_1_0_REG Transmit metadata register 0 0x204 32 read-write n 0x0 0x0 MACSN Sequence Number of this packet. 0 8 read-write TX_META_DATA_1_1_REG Transmit metadata register 1 0x214 32 read-write n 0x0 0x0 MACSN Sequence Number of this packet. 0 8 read-write TX_META_DATA_1_2_REG Transmit metadata register 2 0x224 32 read-write n 0x0 0x0 MACSN Sequence Number of this packet. 0 8 read-write TX_META_DATA_1_3_REG Transmit metadata register 3 0x234 32 read-write n 0x0 0x0 MACSN Sequence Number of this packet. 0 8 read-write TX_PRIORITY_0_REG Transmit priority register 0 0x10410 32 read-write n 0x0 0x0 ISWAKEUP A basic wake-up frame can be generated by the UMAC in the Tx buffer. The meta data control bit IsWakeUp must be set to indicate that this is a Wake-up frame. 4 5 read-write TX_PRIORITY Priority of packet 0 4 read-write TX_PRIORITY_1_REG Transmit priority register 1 0x10430 32 read-write n 0x0 0x0 ISWAKEUP A basic wake-up frame can be generated by the UMAC in the Tx buffer. The meta data control bit IsWakeUp must be set to indicate that this is a Wake-up frame. 4 5 read-write TX_PRIORITY Priority of packet 0 4 read-write TX_PRIORITY_2_REG Transmit priority register 2 0x10450 32 read-write n 0x0 0x0 ISWAKEUP A basic wake-up frame can be generated by the UMAC in the Tx buffer. The meta data control bit IsWakeUp must be set to indicate that this is a Wake-up frame. 4 5 read-write TX_PRIORITY Priority of packet 0 4 read-write TX_PRIORITY_3_REG Transmit priority register 3 0x10470 32 read-write n 0x0 0x0 ISWAKEUP A basic wake-up frame can be generated by the UMAC in the Tx buffer. The meta data control bit IsWakeUp must be set to indicate that this is a Wake-up frame. 4 5 read-write TX_PRIORITY Priority of packet 0 4 read-write TX_RETURN_STATUS_0_0_REG Transmit status register 0 0x240 32 read-write n 0x0 0x0 TXTIMESTAMP Transmit Timestamp The TimeStamp of the transmitted packet. 0 32 read-only TX_RETURN_STATUS_0_1_REG Transmit status register 1 0x250 32 read-write n 0x0 0x0 TXTIMESTAMP Transmit Timestamp The TimeStamp of the transmitted packet. 0 32 read-only TX_RETURN_STATUS_0_2_REG Transmit status register 2 0x260 32 read-write n 0x0 0x0 TXTIMESTAMP Transmit Timestamp The TimeStamp of the transmitted packet. 0 32 read-only TX_RETURN_STATUS_0_3_REG Transmit status register 3 0x270 32 read-write n 0x0 0x0 TXTIMESTAMP Transmit Timestamp The TimeStamp of the transmitted packet. 0 32 read-only TX_RETURN_STATUS_1_0_REG Transmit status register 0 0x244 32 read-write n 0x0 0x0 ACKFAIL Acknowledgement status 0 : SUCCESS 1 : FAIL 0 1 read-only CSMACAFAIL CSMA-CA status 0 : SUCCESS 1 : FAIL 1 2 read-only CSMACANRRETRIES Number of CSMA-CA retries 2 5 read-only TX_RETURN_STATUS_1_1_REG Transmit status register 1 0x254 32 read-write n 0x0 0x0 ACKFAIL Acknowledgement status 0 : SUCCESS 1 : FAIL 0 1 read-only CSMACAFAIL CSMA-CA status 0 : SUCCESS 1 : FAIL 1 2 read-only CSMACANRRETRIES Number of CSMA-CA retries 2 5 read-only TX_RETURN_STATUS_1_2_REG Transmit status register 2 0x264 32 read-write n 0x0 0x0 ACKFAIL Acknowledgement status 0 : SUCCESS 1 : FAIL 0 1 read-only CSMACAFAIL CSMA-CA status 0 : SUCCESS 1 : FAIL 1 2 read-only CSMACANRRETRIES Number of CSMA-CA retries 2 5 read-only TX_RETURN_STATUS_1_3_REG Transmit status register 3 0x274 32 read-write n 0x0 0x0 ACKFAIL Acknowledgement status 0 : SUCCESS 1 : FAIL 0 1 read-only CSMACAFAIL CSMA-CA status 0 : SUCCESS 1 : FAIL 1 2 read-only CSMACANRRETRIES Number of CSMA-CA retries 2 5 read-only TX_SET_OS_REG One shot register to set flag 0x10480 32 read-write n 0x0 0x0 TX_FLAG_SET To set tx_flag_stat 0 4 write-only WAKEUPINTTHR_REG Treshold value Wakeup timer 0x11000 32 read-write n 0x0 0x0 WAKEUPINTTHR Threshold for wake-up interrupt. 0 32 read-write WAKEUP_CONTROL_REG Wakeup timer vcontrol register 0x11004 32 read-write n 0x0 0x0 WAKEUPENABLE If set, the WakeUpIntThr is enabled to generate an interrupt. 1 2 read-write WAKEUPTIMERENABLE A '1' Enables the wakeup timer. Note that in on_off_regmap, the register WakeupTimerEnableStatus shows the status of this register after being clocked by LP_CLK. Checking this register can be used as indication for software that this bit is effective in the desing. 0 1 read-write GPADC GPADC registers Peripheral_Registers 0x0 0x0 0xE registers n GP_ADC_CLEAR_INT_REG General Purpose ADC Clear Interrupt Register 0xA 16 read-write n 0x0 0x0 GP_ADC_CLR_INT Writing any value to this register will clear the ADC_INT interrupt. Reading returns 0. 0 16 write-only GP_ADC_CTRL2_REG General Purpose ADC Second Control Register 0x2 16 read-write n 0x0 0x0 GP_ADC_ATTN3X 0: Input voltages up to 1.2V allowed. 1: Input voltages up to 3.6V allowed by enabling 3x attenuator. (if ADC_SEL=7 or 8, this bit is automatically set to 1) Enabling the attenuator requires a longer sampling time. 0 1 read-write GP_ADC_CONV_NRS 0: 1 sample is taken or 2 in case ADC_CHOP is active. 1: 2 samples are taken. 2: 4 samples are taken. 7: 128 samples are taken. 5 8 read-write GP_ADC_DMA_EN 0: DMA functionality disabled 1: DMA functionality enabled 3 4 read-write GP_ADC_I20U 1: Adds 20uA constant load current at the ADC LDO to minimize ripple on the reference voltage of the ADC. 2 3 read-write GP_ADC_IDYN 1: Enables dynamic load current at the ADC LDO to minimize ripple on the reference voltage of the ADC. 1 2 read-write GP_ADC_SMPL_TIME 0: The sample time (switch is closed) is one ADC_CLK cycle 1: The sample time is 1*32 ADC_CLK cycles 2: The sample time is 2*32 ADC_CLK cycles 15: The sample time is 15*32 ADC_CLK cycles 8 12 read-write GP_ADC_STORE_DEL 0: Data is stored after handshake synchronisation 1: Data is stored two ADC_CLK cycles after internal start trigger 15: Data is stored sixteen ADC_CLK cycles after internal start trigger 12 16 read-write GP_ADC_CTRL3_REG General Purpose ADC Third Control Register 0x4 16 read-write n 0x0 0x0 GP_ADC_EN_DEL Defines the delay for enabling the ADC after enabling the LDO. 0: Not allowed 1: 32x ADC_CLK period. n: n*32x ADC_CLK period. 0 8 read-write GP_ADC_INTERVAL Defines the interval between two ADC conversions in case GP_ADC_CONT is set. 0: No extra delay between two conversions. 1: 1.024ms interval between two conversions. 2: 2.048ms interval between two conversions. 255: 261.12ms interval between two conversions. 8 16 read-write GP_ADC_CTRL_REG General Purpose ADC Control Register 0x0 16 read-write n 0x0 0x0 GP_ADC_CHOP 0: Chopper mode off 1: Chopper mode enabled. Takes two samples with opposite GP_ADC_SIGN to cancel the internal offset voltage of the ADC Highly recommended for DC-measurements. 14 15 read-write GP_ADC_CLK_SEL 0: Internal high-speed ADC clock used (recommended). 1: Digital clock used (ADC_CLK). 3 4 read-write GP_ADC_CONT 0: Manual ADC mode, a single result will be generated after setting the GP_ADC_START bit. 1: Continuous ADC mode, new ADC results will be constantly stored in GP_ADC_RESULT_REG. Still GP_ADC_START has to be set to start the execution. The time between conversions is configurable with GP_ADC_INTERVAL. 2 3 read-write GP_ADC_EN 0: LDO is off and ADC is disabled.. 1: LDO is turned on and afterwards the ADC is enabled. 0 1 read-write GP_ADC_INT 1: AD conversion ready and has generated an interrupt. Must be cleared by writing any value to GP_ADC_CLEAR_INT_REG. 4 5 read-only GP_ADC_LDO_ZERO 1: Samples and disconnects VREF, should be refreshed frequently. Note that the LDO consumpes power when bit is set. 15 16 read-write GP_ADC_MINT 0: Disable (mask) GP_ADC_INT. 1: Enable GP_ADC_INT to ICU. 5 6 read-write GP_ADC_MUTE 0: Normal operation 1: Mute ADC input. Takes sample at mid-scale (to dertermine the internal offset and/or noise of the ADC with regards to VDD_REF which is also sampled by the ADC). 7 8 read-write GP_ADC_SE 0: Differential mode 1: Single ended mode 6 7 read-write GP_ADC_SEL ADC input selection. If GP_ADC_SE = 1 (single ended mode): 0: P1[2] 1: P1[4] 2: P1[3] 3: P0[7] 4: AVS 5: Internal VDD_REF (used for offset calibration) 6: VDCDC (see DCDC_TEST_0_REG.DCDC_OUTPUT_MONITOR for more information GP_ADC_ATTN3X scaler automatically selected) 7: V33 (GP_ADC_ATTN3X scaler automatically selected) 8: V33 (GP_ADC_ATTN3X scaler automatically selected) 9: VBAT (5V to 1.2V scaler selected) 16: P0[6] 17: P1[0] 18: P1[5] 19: P2[4] All other combinations are reserved. If GP_ADC_SE = 0 (differential mode): 0: P1[2] vs P1[4] All other combinations are P1[3] vs P0[7]. 8 13 read-write GP_ADC_SIGN 0: Default 1: Conversion with opposite sign at input and output to cancel out the internal offset of the ADC and low-frequency 13 14 read-write GP_ADC_START 0: ADC conversion ready. 1: If a 1 is written, the ADC starts a conversion. After the conversion this bit will be set to 0 and the GP_ADC_INT bit will be set. It is not allowed to write this bit while it is not (yet) zero. 1 2 read-write GP_ADC_OFFN_REG General Purpose ADC Negative Offset Register 0x8 16 read-write n 0x0 0x0 GP_ADC_OFFN Offset adjust of 'negative' array of ADC-network (effective if GP_ADC_SE=0 , or GP_ADC_SE=1 AND GP_ADC_SIGN=1 ) 0 10 read-write GP_ADC_OFFP_REG General Purpose ADC Positive Offset Register 0x6 16 read-write n 0x0 0x0 GP_ADC_OFFP Offset adjust of 'positive' array of ADC-network (effective if GP_ADC_SE=0 , or GP_ADC_SE=1 AND GP_ADC_SIGN=0 ) 0 10 read-write GP_ADC_RESULT_REG General Purpose ADC Result Register 0xC 16 read-write n 0x0 0x0 GP_ADC_VAL Returns the 10 up to 16 bits linear value of the last AD conversion. The upper 10 bits are always valid, the lower 6 bits are only valid in case oversampling has been applied. Two samples results in one extra bit and 64 samples results in six extra bits. 0 16 read-only GPIO GPIO registers Peripheral_Registers 0x0 0x0 0xD2 registers n CLK_SEL Select which clock to map on port in PPA 0xD0 16 read-write n 0x0 0x0 FUNC_CLOCK_SEL Select which clock to map when PID = FUNC_CLOCK. 0x0: XTAL32K 0x1: RC32K 0x2: RCX 0x3: XTAL16M 0x4: RC16M 0x5: DIVN 0x6: Reserved 0x7: Reserved 0 3 read-write P00_MODE_REG P00 Mode Register 0x1E 16 read-write n 0x0 0x0 PID Function of port: 0: GPIO, PUPD (see above) 1: UART_RX 2: UART_TX 3: UART_IRDA_RX 4: UART_IRDA_TX 5: UART2_RX 6: UART2_TX 7: UART2_IRDA_RX 8: UART2_IRDA_TX 9: UART2_CTSN 10: UART2_RTSN 11: SPI_DI 12: SPI_DO 13: SPI_CLK 14: SPI_EN 15: SPI2_DI 16: SPI2_DO 17: SPI2_CLK 18: SPI2_EN 19: I2C_SCL 20: I2C_SDA 21: I2C2_SCL 22: I2C2_SDA 23: PWM0 24: PWM1 25: PWM2 26: PWM3 27: PWM4 28: BLE_DIAG (ble_diag_0: P2_0, ble_diag_1: P2_1, ble_diag_2: P2_2, ble_diag_3: P1_0, ble_diag_4: P1_1, ble_diag_5: P1_2, ble_diag_6: P1_3, ble_diag_7: P2_3) 29: FTDF_DIAG (ftdf_diag_0: P1_4, ftdf_diag_1: P1_5, ftdf_diag_2: P1_6, ftdf_diag_3: P1_7, ftdf_diag_4: P0_6, ftdf_diag_5: P0_7, ftdf_diag_6: P1_3, ftdf_diag_7: P2_3) 30: PCM_DI 31: PCM_DO 32: PCM_FSC 33: PCM_CLK 34: PDM_DI 35: PDM_DO 36: PDM_CLK 37: USB_SOF 38: ADC (only for P0[7:6], P1[5:2,0] and P2[4]) 38: USB (only for P2[2] and P1[1]) 38: XTAL32 (only for P2[1:0]) 39: QD_CHA_X 40: QD_CHB_X 41: QD_CHA_Y 42: QD_CHB_Y 43: QD_CHA_Z 44: QD_CHB_Z 45: IR_OUT 46: BREATH 47: KB_ROW 48: COEX_EXT_ACT0 49: COEX_EXT_ACT1 50: COEX_SMART_ACT 51: COEX_SMART_PRI 52: CLOCK 53: ONESHOT 54: PWM5 55: PORT0_DCF 56: PORT1_DCF 57: PORT2_DCF 58: PORT3_DCF 59: PORT4_DCF 60: RF_ANT_TRIM[0] 61: RF_ANT_TRIM[1] 62: RF_ANT_TRIM[2] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P01_MODE_REG P01 Mode Register 0x20 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P02_MODE_REG P02 Mode Register 0x22 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P03_MODE_REG P03 Mode Register 0x24 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P04_MODE_REG P04 Mode Register 0x26 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P05_MODE_REG P05 Mode Register 0x28 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P06_MODE_REG P06 Mode Register 0x2A 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P07_MODE_REG P07 Mode Register 0x2C 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P0_DATA_REG P0 Data input / output Register 0x0 16 read-write n 0x0 0x0 P0_DATA Set P0 output register when written Returns the value of P0 port when read 0 8 read-write P0_PADPWR_CTRL_REG P0 Output Power Control Register 0xC0 16 read-write n 0x0 0x0 P0_OUT_CTRL 1 = P0_x port output is powered by VDD1V8P rail 0 = P0_x port output is powered by V33 rail bit 6 controls the power supply of P0[6], bit 7 controls the power supply of P0[7] 6 8 read-write P0_RESET_DATA_REG P0 Reset port pins Register 0x14 16 read-write n 0x0 0x0 P0_RESET Writing a 1 to P0[y] sets P0[y] to 0. Writing 0 is discarded Reading returns 0 0 8 read-write P0_SET_DATA_REG P0 Set port pins Register 0xA 16 read-write n 0x0 0x0 P0_SET Writing a 1 to P0[y] sets P0[y] to 1. Writing 0 is discarded Reading returns 0 0 8 read-write P10_MODE_REG P10 Mode Register 0x2E 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P11_MODE_REG P11 Mode Register 0x30 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P12_MODE_REG P12 Mode Register 0x32 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P13_MODE_REG P13 Mode Register 0x34 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P14_MODE_REG P14 Mode Register 0x36 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P15_MODE_REG P15 Mode Register 0x38 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P16_MODE_REG P24 Mode Register 0x3A 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P17_MODE_REG P25 Mode Register 0x3C 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P1_DATA_REG P1 Data input / output Register 0x2 16 read-write n 0x0 0x0 P1_DATA Set P1 output register when written Returns the value of P1 port when read 0 8 read-write P1_PADPWR_CTRL_REG P1 Output Power Control Register 0xC2 16 read-write n 0x0 0x0 P1_OUT_CTRL 1 = P1_x port output is powered by VDD1V8P rail 0 = P1_x port output is powered by V33 rail bit x controls the power supply of P1[x] 0 8 read-write P1_RESET_DATA_REG P1 Reset port pins Register 0x16 16 read-write n 0x0 0x0 P1_RESET Writing a 1 to P1[y] sets P1[y] to 0. Writing 0 is discarded Reading returns 0 0 8 read-write P1_SET_DATA_REG P1 Set port pins Register 0xC 16 read-write n 0x0 0x0 P1_SET Writing a 1 to P1[y] sets P1[y] to 1. Writing 0 is discarded Reading returns 0 0 8 read-write P20_MODE_REG P20 Mode Register 0x3E 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P21_MODE_REG P21 Mode Register 0x40 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P22_MODE_REG P22 Mode Register 0x42 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P23_MODE_REG P23 Mode Register 0x44 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P24_MODE_REG P24 Mode Register 0x46 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P2_DATA_REG P2 Data input / output Register 0x4 16 read-write n 0x0 0x0 P2_DATA Set P2 output register when written Returns the value of P2 port when read 0 5 read-write P2_PADPWR_CTRL_REG P2 Output Power Control Register 0xC4 16 read-write n 0x0 0x0 P2_OUT_CTRL 1 = P2_x port output is powered by VDD1V8P rail 0 = P2_x port output is powered by V33 rail bit x controls the power supply of P2[x] 0 5 read-write P2_RESET_DATA_REG P2 Reset port pins Register 0x18 16 read-write n 0x0 0x0 P2_RESET Writing a 1 to P2[y] sets P2[y] to 0. Writing 0 is discarded Reading returns 0 0 5 read-write P2_SET_DATA_REG P2 Set port pins Register 0xE 16 read-write n 0x0 0x0 P2_SET Writing a 1 to P2[y] sets P2[y] to 1. Writing 0 is discarded Reading returns 0 0 5 read-write P30_MODE_REG P30 Mode Register 0x4E 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P31_MODE_REG P31 Mode Register 0x50 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P32_MODE_REG P32 Mode Register 0x52 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P33_MODE_REG P33 Mode Register 0x54 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P34_MODE_REG P34 Mode Register 0x56 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P35_MODE_REG P35 Mode Register 0x58 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P36_MODE_REG P36 Mode Register 0x5A 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P37_MODE_REG P37 Mode Register 0x5C 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P3_DATA_REG P3 Data input / output Register 0x6 16 read-write n 0x0 0x0 P3_DATA Set P3 output register when written Returns the value of P3 port when read 0 8 read-write P3_PADPWR_CTRL_REG P3 Output Power Control Register 0xC6 16 read-write n 0x0 0x0 P3_OUT_CTRL 1 = P3_x port output is powered by VDD1V8P rail 0 = P3_x port output is powered by V33 rail bit x controls the power supply of P3[x] 0 8 read-write P3_RESET_DATA_REG P3 Reset port pins Register 0x1A 16 read-write n 0x0 0x0 P3_RESET Writing a 1 to P3[y] sets P3[y] to 0. Writing 0 is discarded Reading returns 0 0 8 write-only P3_SET_DATA_REG P3 Set port pins Register 0x10 16 read-write n 0x0 0x0 P3_SET Writing a 1 to P3[y] sets P3[y] to 1. Writing 0 is discarded Reading returns 0 0 8 write-only P40_MODE_REG P40 Mode Register 0x5E 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P41_MODE_REG P41 Mode Register 0x60 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P42_MODE_REG P42 Mode Register 0x62 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P43_MODE_REG P43 Mode Register 0x64 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P44_MODE_REG P44 Mode Register 0x66 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P45_MODE_REG P45 Mode Register 0x68 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P46_MODE_REG P46 Mode Register 0x6A 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P47_MODE_REG P47 Mode Register 0x6C 16 read-write n 0x0 0x0 PID See P00_MODE_REG[PID] 0 6 read-write PPOD 0: Push pull 1: Open drain 10 11 read-write PUPD 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care 8 10 read-write P4_DATA_REG P4 Data input / output Register 0x8 16 read-write n 0x0 0x0 P4_DATA Set P4 output register when written Returns the value of P4 port when read 0 8 read-write P4_PADPWR_CTRL_REG P4 Output Power Control Register 0xC8 16 read-write n 0x0 0x0 P4_OUT_CTRL 1 = P4_x port output is powered by VDD1V8P rail 0 = P4_x port output is powered by V33 rail bit x controls the power supply of P4[x] 0 8 read-write P4_RESET_DATA_REG P4 Reset port pins Register 0x1C 16 read-write n 0x0 0x0 P4_RESET Writing a 1 to P4[y] sets P4[y] to 0. Writing 0 is discarded Reading returns 0 0 8 write-only P4_SET_DATA_REG P4 Set port pins Register 0x12 16 read-write n 0x0 0x0 P4_SET Writing a 1 to P4[y] sets P4[y] to 1. Writing 0 is discarded Reading returns 0 0 8 write-only GPREG GPREG registers Peripheral_Registers 0x0 0x0 0x1A registers n DEBUG_REG Various debug information register. 0x4 16 read-write n 0x0 0x0 DEBUGS_FREEZE_EN Default '1', freezing of the on-chip timers is enabled when the Cortex-M0 is halted in DEBUG State. If '0', freezing of the on-chip timers is depending on FREEZE_REG when the Cortex-M0 is halted in DEBUG State except the watchdog timer. The watchdog timer is always frozen when the Cortex-M0 is halted in DEBUG State. Note: This bit is retained. 0 1 read-write ECC_BASE_ADDR_REG Base address of the ECC Crypto memory register. 0xA 16 read-write n 0x0 0x0 ECC_BASE_ADDR Contains the base address of the ECC Crypto memory. Memory allocation is in pages of 1KB and up to 127KB. Since the ECC has an address range of 2KB and the total addressable memory range is 128KB, the maximum value of 0x7F (127KB offset) will result in 1KB at the top of the memory range and the other 1KB at the bottom of the memory range. 0 7 read-write GP_CONTROL_REG General purpose system control register. 0x8 16 read-write n 0x0 0x0 BLE_DEEPSLDUR_MONITOR The 8 LSBs of the current value of the BLE Timer DEEPSLDUR. The value has been sampled by using the CPU clock. 8 16 read-only BLE_H2H_BRIDGE_BYPASS If '1', the AHB-to-AHB bridge is bypassed, needed to access the BLE Register file, only when the system clock source is the XTAL and both hclk and ble_hclk are running at 16MHz, i.e. at the XTAL clock rate. 1 2 read-write BLE_WAKEUP_LP_IRQ The current value of the BLE_WAKEUP_LP_IRQ interrupt request. 2 3 read-only BLE_WAKEUP_REQ If '1', the BLE wakes up. Must be kept high at least for 1 low power clock period. If the BLE is in deep sleep state, then by setting this bit it will cause the wakeup LP IRQ to be asserted with a delay of 3 to 4 low power cycles. 0 1 read-write GP_STATUS_REG General purpose system status register. 0x6 16 read-write n 0x0 0x0 CAL_PHASE If '1', it designates that the chip is in Calibration Phase i.e. the OTP has been initially programmed but no Calibration has occured. 0 1 read-write LED_CONTROL_REG Controls muxing and enabling of the LEDs. 0xC 16 read-write n 0x0 0x0 LED1_EN 0: LED1 disabled, 1: LED1 enabled. 3 4 read-write LED1_SRC_SEL 0: LED1 = PWM2, 1: LED1 = Breathing Timer. Note: The PWM2/3/4 can also be routed to GPIOs using PID 25/26/27 respectively. 0 1 read-write LED2_EN 0: LED2 disabled, 1: LED2 enabled. 4 5 read-write LED2_SRC_SEL 0: LED2 = PWM3, 1: LED2 = Breathing Timer. 1 2 read-write LED3_EN 0: LED3 disabled, 1: LED3 enabled. 5 6 read-write LED3_SRC_SEL 0: LED3 = PWM4, 1: LED3 = Breathing Timer. 2 3 read-write PLL_SYS_CTRL1_REG System PLL control register 1. 0x10 16 read-write n 0x0 0x0 LDO_PLL_ENABLE 0: LDO PLL off, 1: LDO PLL on. 1 2 read-write LDO_PLL_VREF_HOLD 0: indicates that the reference input is tracked, 1: indicates that the reference input is sampled. 2 3 read-write PLL_EN 0: Power down 1: PLL on 0 1 read-write PLL_R_DIV PLL Output dvider R (x means divide by x, 0 means divide by 1) 8 15 read-write PLL_SYS_CTRL2_REG System PLL control register 2. 0x12 16 read-write n 0x0 0x0 PLL_DEL_SEL PLL manual delay value for Phase Frequency Detector. 0: 0.493 1: 0.814 2: 1.13 ns <- default 3: 1.44 ns 12 14 read-write PLL_N_DIV PLL Loop divider N (x means divide by x, 0 means divide by 1) 0 7 read-write PLL_SEL_MIN_CUR_INT 0: VCO current read from min_current <5:0>, 1: VCO current is internally determined with a calibration algoritm. 14 15 read-write PLL_SYS_CTRL3_REG System PLL control register 3. 0x14 16 read-write n 0x0 0x0 PLL_ICP_SEL PLL charge pump current select One LSB is 5uA. 0 5 read-write PLL_RECALIB Recalibrate 15 16 read-write PLL_START_DEL Programmable delay time for the loop filter voltage preset value. After PLL_EN is set, the loopfilter precharge resistors are disabled after this delay time. One LSB is 48 ns 10 15 read-write PLL_SYS_STATUS_REG System PLL status register. 0x16 16 read-write n 0x0 0x0 LDO_PLL_OK 1: Indicates that LDO PLL is in regulation. 1 2 read-only PLL_CALIBR_END Indicates that calibration has finished. 11 12 read-only PLL_LOCK_FINE 1: PLL locked 0 1 read-only PLL_PLL_BEST_MIN_CUR Calibrated VCO frequency band. 5 11 read-only PLL_SYS_TEST_REG System PLL test register. 0x18 16 read-write n 0x0 0x0 PLL_CHANGE 0: normal value 1: reverse charge pump up/down signals 9 10 read-write PLL_DIS_LOOPFILT 1: disable PLL internal loop filter 0 1 read-write PLL_LOCK_DET_RES_CNT Lock measurement time in clock cycle of xx usec. After this period PLL_LOCK_FINE is calculated based on the difference of the M and N counted pulses in that period. If PLL_LOCK_FINE is still 0, the lock state machine restarts until PLL_LOCK_FINE gets 1 0: usec 7: usec 13 16 read-write PLL_MIN_CURRENT VCO current trimming. 1 7 read-write PLL_OPEN_LOOP 1: set to open loop to termine max frequency 8 9 read-write PLL_SEL_N_DIV_TEST Select test mode for loop divider N. Maps PLL_N_DIV input on pins and divider output on pin 10 11 read-write PLL_SEL_R_DIV_TEST Select test mode for output divider R Maps PLL_R_DIV input on pins and divider output on pin 11 12 read-write PLL_TEST_VCTR 1: map loopfilter voltage on external pin 7 8 read-write RESET_FREEZE_REG Controls unfreezing of various timers/counters (incl. DMA and USB). 0x2 16 read-write n 0x0 0x0 FRZ_BLETIM If '1', the BLE master clock continues, '0' is discarded. 2 3 read-write FRZ_DMA If '1', the DMA continues, '0' is discarded. 5 6 read-write FRZ_SWTIM0 If '1', the SW Timer (TIMER0) continues, '0' is discarded. 1 2 read-write FRZ_SWTIM1 If '1', the SW Timer (TIMER1) continues, '0' is discarded. 6 7 read-write FRZ_SWTIM2 If '1', the SW Timer (TIMER2) continues, '0' is discarded. 7 8 read-write FRZ_USB If '1', the USB continues, '0' is discarded. 4 5 read-write FRZ_WDOG If '1', the watchdog timer continues, '0' is discarded. 3 4 read-write FRZ_WKUPTIM If '1', the Wake Up Timer continues, '0' is discarded. 0 1 read-write SET_FREEZE_REG Controls freezing of various timers/counters (incl. DMA and USB). 0x0 16 read-write n 0x0 0x0 FRZ_BLETIM If '1', the BLE master clock is frozen, '0' is discarded. 2 3 read-write FRZ_DMA If '1', the DMA is frozen, '0' is discarded. 5 6 read-write FRZ_SWTIM0 If '1', the SW Timer (TIMER0) is frozen, '0' is discarded. 1 2 read-write FRZ_SWTIM1 If '1', the SW Timer (TIMER1) is frozen, '0' is discarded. 6 7 read-write FRZ_SWTIM2 If '1', the SW Timer (TIMER2) is frozen, '0' is discarded. 7 8 read-write FRZ_USB If '1', the USB is frozen, '0' is discarded. 4 5 read-write FRZ_WDOG If '1', the watchdog timer is frozen, '0' is discarded. WATCHDOG_CTRL_REG[NMI_RST] must be '0' to allow the freeze function. 3 4 read-write FRZ_WKUPTIM If '1', the Wake Up Timer is frozen, '0' is discarded. 0 1 read-write GP_TIMERS GP_TIMERS registers Peripheral_Registers 0x0 0x0 0x20 registers n BREATH_CFG_REG Breath configuration register 0x18 16 read-write n 0x0 0x0 BRTH_DIV Defines the division factor of the system clock to get to the PWM frequency.( = Sys Clock / (value+1) 0 8 read-write BRTH_STEP Defines the number of PWM periods minus 1, duty cycle will be changed 8 16 read-write BREATH_CTRL_REG Breath control register 0x1E 16 read-write n 0x0 0x0 BRTH_EN '1' enable the Breath operation 0 1 read-write BRTH_PWM_POL Define the output polarity. 1 2 read-write BREATH_DUTY_MAX_REG Breath max duty cycle register 0x1A 16 read-write n 0x0 0x0 BRTH_DUTY_MAX Defines the maximum duty cycle of the PWM breath function. Duty cycle = value / (brth_div+1) 0 8 read-write BREATH_DUTY_MIN_REG Breath min duty cycle register 0x1C 16 read-write n 0x0 0x0 BRTH_DUTY_MIN Defines the minimum duty cycle of the PWM breath function. Duty cycle = value / (brth_div+1) 0 8 read-write PWM2_END_CYCLE Defines end Cycle for PWM2 0xE 16 read-write n 0x0 0x0 END_CYCLE Define the cycle in which the PWM becomes low. If end cycle larger then freq pwm and start cycle not larger then freq pwm, output is always 1 0 14 read-write PWM2_START_CYCLE Defines start Cycle for PWM2 0x8 16 read-write n 0x0 0x0 START_CYCLE Define the cycle in which the PWM becomes high. if start_cycle larger than freq or end and start are equal, pwm out is always 0 0 14 read-write PWM3_END_CYCLE Defines end Cycle for PWM3 0x10 16 read-write n 0x0 0x0 END_CYCLE Define the cycle in which the PWM becomes low. If end cycle larger then freq pwm and start cycle not larger then freq pwm, output is always 1 0 14 read-write PWM3_START_CYCLE Defines start Cycle for PWM3 0xA 16 read-write n 0x0 0x0 START_CYCLE Define the cycle in which the PWM becomes high. if start_cycle larger than freq or end and start are equal, pwm out is always 0 0 14 read-write PWM4_END_CYCLE Defines end Cycle for PWM4 0x12 16 read-write n 0x0 0x0 END_CYCLE Define the cycle in which the PWM becomes low. If end cycle larger then freq pwm and start cycle not larger then freq pwm, output is always 1 0 14 read-write PWM4_START_CYCLE Defines start Cycle for PWM4 0xC 16 read-write n 0x0 0x0 START_CYCLE Define the cycle in which the PWM becomes high. if start_cycle larger than freq or end and start are equal, pwm out is always 0 0 14 read-write TIMER0_CTRL_REG Timer0 control register 0x0 16 read-write n 0x0 0x0 PWM_MODE 0 = PWM signals are '1' during high time. 1 = PWM signals send out the (fast) clock divided by 2 during high time. 3 4 read-write TIM0_CLK_DIV 1 = Timer0 uses selected clock frequency as is. 0 = Timer0 uses selected clock frequency divided by 10. Note that this applies only to the ON-counter. 2 3 read-write TIM0_CLK_SEL 1 = Timer0 uses fast clock frequency. 0 = Timer0 uses 32 kHz (slow) clock frequency. 1 2 read-write TIM0_CTRL 0 = Timer0 is off and in reset state. 1 = Timer0 is running. 0 1 read-write TIMER0_ON_REG Timer0 on control register 0x2 16 read-write n 0x0 0x0 TIM0_ON Timer0 On reload value: If read the actual counter value ON_CNTer is returned 0 16 write-only TIMER0_RELOAD_M_REG 16 bits reload value for Timer0 0x4 16 read-write n 0x0 0x0 TIM0_M Timer0 'high' reload valueIf read the actual counter value T0_CNTer is returned 0 16 write-only TIMER0_RELOAD_N_REG 16 bits reload value for Timer0 0x6 16 read-write n 0x0 0x0 TIM0_N Timer0 'low' reload value: If read the actual counter value T0_CNTer is returned 0 16 write-only TRIPLE_PWM_CTRL_REG PWM 2 3 4 Control register 0x16 16 read-write n 0x0 0x0 HW_PAUSE_EN '1' = HW can pause PWM 2,3,4 2 3 read-write SW_PAUSE_EN '1' = PWM 2 3 4 is paused 1 2 read-write TRIPLE_PWM_ENABLE '1' = PWM 2 3 4 is enabled 0 1 read-write TRIPLE_PWM_FREQUENCY Defines the PMW2,3,4 frequency 0x14 16 read-write n 0x0 0x0 FREQ Freq for PWM 2 3 4, period = timer_clk * ( FREQ+1) 0 14 read-write I2C I2C registers Peripheral_Registers 0x0 0x0 0x100 registers n ACK_GENERAL_CALL_REG I2C ACK General Call Register 0x98 16 read-write n 0x0 0x0 ACK_GEN_CALL ACK General Call. When set to 1, I2C Ctrl responds with a ACK (by asserting ic_data_oe) when it receives a General Call. When set to 0, the controller does not generate General Call interrupts. 0 1 read-write CLR_ACTIVITY_REG Clear ACTIVITY Interrupt Register 0x5C 16 read-write n 0x0 0x0 CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register 0 1 read-only CLR_GEN_CALL_REG Clear GEN_CALL Interrupt Register 0x68 16 read-write n 0x0 0x0 CLR_GEN_CALL Read this register to clear the GEN_CALL interrupt (bit 11) of I2C_RAW_INTR_STAT register. 0 1 read-only CLR_INTR_REG Clear Combined and Individual Interrupt Register 0x40 16 read-write n 0x0 0x0 CLR_INTR Read this register to clear the combined interrupt, all individual interrupts, and the I2C_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing I2C_TX_ABRT_SOURCE 0 1 read-only CLR_RD_REQ_REG Clear RD_REQ Interrupt Register 0x50 16 read-write n 0x0 0x0 CLR_RD_REQ Read this register to clear the RD_REQ interrupt (bit 5) of the I2C_RAW_INTR_STAT register. 0 1 read-only CLR_RX_DONE_REG Clear RX_DONE Interrupt Register 0x58 16 read-write n 0x0 0x0 CLR_RX_DONE Read this register to clear the RX_DONE interrupt (bit 7) of the I2C_RAW_INTR_STAT register. 0 1 read-only CLR_RX_OVER_REG Clear RX_OVER Interrupt Register 0x48 16 read-write n 0x0 0x0 CLR_RX_OVER Read this register to clear the RX_OVER interrupt (bit 1) of the I2C_RAW_INTR_STAT register. 0 1 read-only CLR_RX_UNDER_REG Clear RX_UNDER Interrupt Register 0x44 16 read-write n 0x0 0x0 CLR_RX_UNDER Read this register to clear the RX_UNDER interrupt (bit 0) of the I2C_RAW_INTR_STAT register. 0 1 read-only CLR_START_DET_REG Clear START_DET Interrupt Register 0x64 16 read-write n 0x0 0x0 CLR_START_DET Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. 0 1 read-only CLR_STOP_DET_REG Clear STOP_DET Interrupt Register 0x60 16 read-write n 0x0 0x0 CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. 0 1 read-only CLR_TX_ABRT_REG Clear TX_ABRT Interrupt Register 0x54 16 read-write n 0x0 0x0 CLR_TX_ABRT Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the I2C_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. 0 1 read-only CLR_TX_OVER_REG Clear TX_OVER Interrupt Register 0x4C 16 read-write n 0x0 0x0 CLR_TX_OVER Read this register to clear the TX_OVER interrupt (bit 3) of the I2C_RAW_INTR_STAT register. 0 1 read-only COMP2_VERSION I2C Component2 Version Register 0xFA 16 read-write n 0x0 0x0 IC_COMP2_VERSION 0 16 read-only COMP_PARAM1_REG Component Parameter Register 0xF4 16 read-write n 0x0 0x0 IC_COMP_PARAM1 0 16 read-only COMP_PARAM2_REG Component Parameter Register 2 0xF6 16 read-write n 0x0 0x0 IC_COMP_PARAM2 0 16 read-only COMP_TYPE2_REG I2C Component2 Type Register 0xFE 16 read-write n 0x0 0x0 IC_COMP2_TYPE 0 16 read-only COMP_TYPE_REG I2C Component Type Register 0xFC 16 read-write n 0x0 0x0 IC_COMP_TYPE 0 16 read-only COMP_VERSION_REG I2C Component Version Register 0xF8 16 read-write n 0x0 0x0 IC_COMP_VERSION 0 16 read-only CON_REG I2C Control Register 0x0 16 read-write n 0x0 0x0 I2C_10BITADDR_MASTER Controls whether the controller starts its transfers in 7- or 10-bit addressing mode when acting as a master. 0= 7-bit addressing 1= 10-bit addressing 4 5 read-write I2C_10BITADDR_SLAVE When acting as a slave, this bit controls whether the controller responds to 7- or 10-bit addresses. 0= 7-bit addressing 1= 10-bit addressing 3 4 read-write I2C_MASTER_MODE This bit controls whether the controller master is enabled. 0= master disabled 1= master enabled Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. 0 1 read-write I2C_RESTART_EN Determines whether RESTART conditions may be sent when acting as a master 0= disable 1=enable 5 6 read-write I2C_SLAVE_DISABLE Slave enabled or disabled after reset is applied, which means software does not have to configure the slave. 0=slave is enabled 1=slave is disabled Software should ensure that if this bit is written with '0', then bit 0 should also be written with a '0'. 6 7 read-write I2C_SPEED These bits control at which speed the controller operates. 1= standard mode (100 kbit/s) 2= fast mode (400 kbit/s) 1 3 read-write DATA_CMD_REG I2C Rx/Tx Data Buffer and Command Register 0x10 16 read-write n 0x0 0x0 CMD This bit controls whether a read or a write is performed. This bit does not control the direction when the I2C Ctrl acts as a slave. It controls only the direction when it acts as a master. 1 = Read 0 = Write When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a don't care because writes to this register are not required. In slave-transmitter mode, a 0 indicates that CPU data is to be transmitted and as DAT or IC_DATA_CMD[7:0]. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the I2C_RAW_INTR_STAT_REG), unless bit 11 (SPECIAL) in the I2C_TAR register has been cleared. If a 1 is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. NOTE: It is possible that while attempting a master I2C read transfer on the controller, a RD_REQ interrupt may have occurred simultaneously due to a remote I2C master addressing the controller. In this type of scenario, it ignores the I2C_DATA_CMD write, generates a TX_ABRT interrupt, and waits to service the RD_REQ interrupt 8 9 read-write DAT This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the controller. However, when you read this register, these bits return the value of data received on the controller's interface. 0 8 read-write DMA_CR_REG DMA Control Register 0x88 16 read-write n 0x0 0x0 RDMAE Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. 0 = Receive DMA disabled 1 = Receive DMA enabled 0 1 read-write TDMAE Transmit DMA Enable. //This bit enables/disables the transmit FIFO DMA channel. 0 = Transmit DMA disabled 1 = Transmit DMA enabled 1 2 read-write DMA_RDLR_REG I2C Receive Data Level Register 0x90 16 read-write n 0x0 0x0 DMARDL Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1 that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. 0 5 read-write DMA_TDLR_REG DMA Transmit Data Level Register 0x8C 16 read-write n 0x0 0x0 DMATDL Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. 0 5 read-write ENABLE_REG I2C Enable Register 0x6C 16 read-write n 0x0 0x0 CTRL_ENABLE Controls whether the controller is enabled. 0: Disables the controller (TX and RX FIFOs are held in an erased state) 1: Enables the controller Software can disable the controller while it is active. However, it is important that care be taken to ensure that the controller is disabled properly. When the controller is disabled, the following occurs: * The TX FIFO and RX FIFO get flushed. * Status bits in the IC_INTR_STAT register are still active until the controller goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the controller stops the current transfer at the end of the current byte and does not acknowledge the transfer. There is a two ic_clk delay when enabling or disabling the controller 0 1 read-write I2C_ABORT 0= ABORT not initiated or ABORT done 1= ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. 1 2 read-write ENABLE_STATUS_REG I2C Enable Status Register 0x9C 16 read-write n 0x0 0x0 IC_EN ic_en Status. This bit always reflects the value driven on the output port ic_en. When read as 1, the controller is deemed to be in an enabled state. When read as 0, the controller is deemed completely inactive. NOTE: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). 0 1 read-only SLV_DISABLED_WHILE_BUSY Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) I2C Ctrl is receiving the address byte of the Slave-Transmitter operation from a remote master OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, the controller is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in I2C Ctrl (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit will also be set to 1. When read as 0, the controller is deemed to have been disabled when there is master activity, or when the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. 1 2 read-only SLV_RX_DATA_LOST Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting of IC_ENABLE from 1 to 0. When read as 1, the controller is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit is also set to 1. When read as 0, the controller is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. 2 3 read-only FS_SCL_HCNT_REG Fast Speed I2C Clock SCL High Count Register 0x1C 16 read-write n 0x0 0x0 IC_FS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set. 0 16 read-write FS_SCL_LCNT_REG Fast Speed I2C Clock SCL Low Count Register 0x20 16 read-write n 0x0 0x0 IC_FS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low-period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the controller. The lower byte must be programmed first. Then the upper byte is programmed. 0 16 read-write HS_MADDR_REG I2C High Speed Master Mode Code Address Register 0xC 16 read-write n 0x0 0x0 IIC_HS_MAR This bit field holds the value of the I2C HS mode master code. 0 3 read-write IC_FS_SPKLEN_REG I2C SS and FS spike suppression limit Size 0xA0 16 read-write n 0x0 0x0 IC_FS_SPKLEN This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 1 hardware prevents values less than this being written, and if attempted results in 1 being set. 0 8 read-write INTR_MASK_REG I2C Interrupt Mask Register 0x30 16 read-write n 0x0 0x0 M_ACTIVITY These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 8 9 read-write M_GEN_CALL These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 11 12 read-write M_RD_REQ These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 5 6 read-write M_RX_DONE These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 7 8 read-write M_RX_FULL These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 2 3 read-write M_RX_OVER These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 1 2 read-write M_RX_UNDER These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0 1 read-write M_START_DET These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 10 11 read-write M_STOP_DET These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 9 10 read-write M_TX_ABRT These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 6 7 read-write M_TX_EMPTY These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 4 5 read-write M_TX_OVER These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 3 4 read-write INTR_STAT_REG I2C Interrupt Status Register 0x2C 16 read-write n 0x0 0x0 R_ACTIVITY This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it: => Disabling the I2C Ctrl => Reading the IC_CLR_ACTIVITY register => Reading the IC_CLR_INTR register => System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus. 8 9 read-only R_GEN_CALL Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. The controller stores the received data in the Rx buffer. 11 12 read-only R_RD_REQ This bit is set to 1 when the controller is acting as a slave and another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register 5 6 read-only R_RX_DONE When the controller is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. 7 8 read-only R_RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. 2 3 read-only R_RX_OVER Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 1 2 read-only R_RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 0 1 read-only R_START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 10 11 read-only R_STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 9 10 read-only R_TX_ABRT This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a transmit abort . When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface. 6 7 read-only R_TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0. 4 5 read-only R_TX_OVER Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared 3 4 read-only RAW_INTR_STAT_REG I2C Raw Interrupt Status Register 0x34 16 read-write n 0x0 0x0 ACTIVITY This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it: => Disabling the I2C Ctrl => Reading the IC_CLR_ACTIVITY register => Reading the IC_CLR_INTR register => System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus. 8 9 read-only GEN_CALL Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. I2C Ctrl stores the received data in the Rx buffer. 11 12 read-only RD_REQ This bit is set to 1 when I2C Ctrl is acting as a slave and another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register 5 6 read-only RX_DONE When the controller is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. 7 8 read-only RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. 2 3 read-only RX_OVER Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 1 2 read-only RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 0 1 read-only START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 10 11 read-only STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 9 10 read-only TX_ABRT This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a transmit abort . When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface. 6 7 read-only TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0. 4 5 read-only TX_OVER Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared 3 4 read-only RXFLR_REG I2C Receive FIFO Level Register 0x78 16 read-write n 0x0 0x0 RXFLR Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Size is constrained by the RXFLR value 0 6 read-only RX_TL_REG I2C Receive FIFO Threshold Register 0x38 16 read-write n 0x0 0x0 RX_TL Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in I2C_RAW_INTR_STAT register). The valid range is 0-3,a value of 0 sets the threshold for 1 entry, and a value of 3 sets the threshold for 4 entries 0 5 read-write SAR_REG I2C Slave Address Register 0x8 16 read-write n 0x0 0x0 IC_SAR The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. 0 10 read-write SDA_HOLD_REG I2C SDA Hold Time Length Register 0x7C 16 read-write n 0x0 0x0 IC_SDA_HOLD SDA Hold time 0 16 read-write SDA_SETUP_REG I2C SDA Setup Register 0x94 16 read-write n 0x0 0x0 SDA_SETUP SDA Setup. This register controls the amount of time delay (number of I2C clock periods) between the rising edge of SCL and SDA changing by holding SCL low when I2C block services a read request while operating as a slave-transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. It is recommended that if the required delay is 1000ns, then for an I2C frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11.Writes to this register succeed only when IC_ENABLE[0] = 0. 0 8 read-write SS_SCL_HCNT_REG Standard Speed I2C Clock SCL High Count Register 0x14 16 read-write n 0x0 0x0 IC_SS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set. NOTE: This register must not be programmed to a value higher than 65525, because the controller uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. 0 16 read-write SS_SCL_LCNT_REG Standard Speed I2C Clock SCL Low Count Register 0x18 16 read-write n 0x0 0x0 IC_SS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted, results in 8 being set. 0 16 read-write STATUS_REG I2C Status Register 0x70 16 read-write n 0x0 0x0 I2C_ACTIVITY I2C Activity Status. 0 1 read-only MST_ACTIVITY Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. 0: Master FSM is in IDLE state so the Master part of the controller is not Active 1: Master FSM is not in IDLE state so the Master part of the controller is Active 5 6 read-only RFF Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0: Receive FIFO is not full 1: Receive FIFO is full 4 5 read-only RFNE Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries it is cleared when the receive FIFO is empty. 0: Receive FIFO is empty 1: Receive FIFO is not empty 3 4 read-only SLV_ACTIVITY Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. 0: Slave FSM is in IDLE state so the Slave part of the controller is not Active 1: Slave FSM is not in IDLE state so the Slave part of the controller is Active 6 7 read-only TFE Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0: Transmit FIFO is not empty 1: Transmit FIFO is empty 2 3 read-only TFNF Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0: Transmit FIFO is full 1: Transmit FIFO is not full 1 2 read-only TAR_REG I2C Target Address Register 0x4 16 read-write n 0x0 0x0 GC_OR_START If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the controller. 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The controller remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. 1: START BYTE 10 11 read-write IC_TAR This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. Note: If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself it can transmit to only a slave Writes to this register succeed only when IC_ENABLE[0] is set to 0 0 10 read-write SPECIAL This bit indicates whether software performs a General Call or START BYTE command. 0: ignore bit 10 GC_OR_START and use IC_TAR normally 1: perform special I2C command as specified in GC_OR_START bit 11 12 read-write TXFLR_REG I2C Transmit FIFO Level Register 0x74 16 read-write n 0x0 0x0 TXFLR Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Size is constrained by the TXFLR value 0 6 read-only TX_ABRT_SOURCE_REG I2C Transmit Abort Source Register 0x80 16 read-write n 0x0 0x0 ABRT_10ADDR1_NOACK 1: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. 1 2 read-only ABRT_10ADDR2_NOACK 1: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave. 2 3 read-only ABRT_10B_RD_NORSTRT 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode. 10 11 read-only ABRT_7B_ADDR_NOACK 1: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. 0 1 read-only ABRT_GCALL_NOACK 1: the controller in master mode sent a General Call and no slave on the bus acknowledged the General Call. 4 5 read-only ABRT_GCALL_READ 1: the controller in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). 5 6 read-only ABRT_HS_ACKDET 1: Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). 6 7 read-only ABRT_HS_NORSTRT 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode 8 9 read-only ABRT_MASTER_DIS 1: User tries to initiate a Master operation with the Master mode disabled. 11 12 read-only ABRT_SBYTE_ACKDET 1: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). 7 8 read-only ABRT_SBYTE_NORSTRT To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first restart must be enabled (I2C_CON[5]=1), the SPECIAL bit must be cleared (I2C_TAR[11]), or the GC_OR_START bit must be cleared (I2C_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets re-asserted. 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to send a START Byte. 9 10 read-only ABRT_SLVFLUSH_TXFIFO 1: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. 13 14 read-only ABRT_SLVRD_INTX 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of 2IC_DATA_CMD register 15 16 read-only ABRT_SLV_ARBLOST 1: Slave lost the bus while transmitting data to a remote master. I2C_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never owns the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then the controller no longer own the bus. 14 15 read-only ABRT_TXDATA_NOACK 1: This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). 3 4 read-only ARB_LOST 1: Master has lost arbitration, or if I2C_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. Note: I2C can be both master and slave at the same time. 12 13 read-only TX_TL_REG I2C Transmit FIFO Threshold Register 0x3C 16 read-write n 0x0 0x0 TX_TL Transmit FIFO Threshold Level Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in I2C_RAW_INTR_STAT register). The valid range is 0-3, a value of 0 sets the threshold for 0 entries, and a value of 3 sets the threshold for 4 entries.. 0 5 read-write I2C2 I2C2 registers Peripheral_Registers 0x0 0x0 0x100 registers n ACK_GENERAL_CALL_REG I2C ACK General Call Register 0x98 16 read-write n 0x0 0x0 ACK_GEN_CALL ACK General Call. When set to 1, I2C Ctrl responds with a ACK (by asserting ic_data_oe) when it receives a General Call. When set to 0, the controller does not generate General Call interrupts. 0 1 read-write CLR_ACTIVITY_REG Clear ACTIVITY Interrupt Register 0x5C 16 read-write n 0x0 0x0 CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register 0 1 read-only CLR_GEN_CALL_REG Clear GEN_CALL Interrupt Register 0x68 16 read-write n 0x0 0x0 CLR_GEN_CALL Read this register to clear the GEN_CALL interrupt (bit 11) of I2C_RAW_INTR_STAT register. 0 1 read-only CLR_INTR_REG Clear Combined and Individual Interrupt Register 0x40 16 read-write n 0x0 0x0 CLR_INTR Read this register to clear the combined interrupt, all individual interrupts, and the I2C_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing I2C_TX_ABRT_SOURCE 0 1 read-only CLR_RD_REQ_REG Clear RD_REQ Interrupt Register 0x50 16 read-write n 0x0 0x0 CLR_RD_REQ Read this register to clear the RD_REQ interrupt (bit 5) of the I2C_RAW_INTR_STAT register. 0 1 read-only CLR_RX_DONE_REG Clear RX_DONE Interrupt Register 0x58 16 read-write n 0x0 0x0 CLR_RX_DONE Read this register to clear the RX_DONE interrupt (bit 7) of the I2C_RAW_INTR_STAT register. 0 1 read-only CLR_RX_OVER_REG Clear RX_OVER Interrupt Register 0x48 16 read-write n 0x0 0x0 CLR_RX_OVER Read this register to clear the RX_OVER interrupt (bit 1) of the I2C_RAW_INTR_STAT register. 0 1 read-only CLR_RX_UNDER_REG Clear RX_UNDER Interrupt Register 0x44 16 read-write n 0x0 0x0 CLR_RX_UNDER Read this register to clear the RX_UNDER interrupt (bit 0) of the I2C_RAW_INTR_STAT register. 0 1 read-only CLR_START_DET_REG Clear START_DET Interrupt Register 0x64 16 read-write n 0x0 0x0 CLR_START_DET Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. 0 1 read-only CLR_STOP_DET_REG Clear STOP_DET Interrupt Register 0x60 16 read-write n 0x0 0x0 CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. 0 1 read-only CLR_TX_ABRT_REG Clear TX_ABRT Interrupt Register 0x54 16 read-write n 0x0 0x0 CLR_TX_ABRT Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the I2C_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. 0 1 read-only CLR_TX_OVER_REG Clear TX_OVER Interrupt Register 0x4C 16 read-write n 0x0 0x0 CLR_TX_OVER Read this register to clear the TX_OVER interrupt (bit 3) of the I2C_RAW_INTR_STAT register. 0 1 read-only COMP2_VERSION I2C Component2 Version Register 0xFA 16 read-write n 0x0 0x0 IC_COMP2_VERSION 0 16 read-only COMP_PARAM1_REG Component Parameter Register 0xF4 16 read-write n 0x0 0x0 IC_COMP_PARAM1 0 16 read-only COMP_PARAM2_REG Component Parameter Register 2 0xF6 16 read-write n 0x0 0x0 IC_COMP_PARAM2 0 16 read-only COMP_TYPE2_REG I2C Component2 Type Register 0xFE 16 read-write n 0x0 0x0 IC_COMP2_TYPE 0 16 read-only COMP_TYPE_REG I2C Component Type Register 0xFC 16 read-write n 0x0 0x0 IC_COMP_TYPE 0 16 read-only COMP_VERSION_REG I2C Component Version Register 0xF8 16 read-write n 0x0 0x0 IC_COMP_VERSION 0 16 read-only CON_REG I2C Control Register 0x0 16 read-write n 0x0 0x0 I2C_10BITADDR_MASTER Controls whether the controller starts its transfers in 7- or 10-bit addressing mode when acting as a master. 0= 7-bit addressing 1= 10-bit addressing 4 5 read-write I2C_10BITADDR_SLAVE When acting as a slave, this bit controls whether the controller responds to 7- or 10-bit addresses. 0= 7-bit addressing 1= 10-bit addressing 3 4 read-write I2C_MASTER_MODE This bit controls whether the controller master is enabled. 0= master disabled 1= master enabled Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. 0 1 read-write I2C_RESTART_EN Determines whether RESTART conditions may be sent when acting as a master 0= disable 1=enable 5 6 read-write I2C_SLAVE_DISABLE Slave enabled or disabled after reset is applied, which means software does not have to configure the slave. 0=slave is enabled 1=slave is disabled Software should ensure that if this bit is written with '0', then bit 0 should also be written with a '0'. 6 7 read-write I2C_SPEED These bits control at which speed the controller operates. 1= standard mode (100 kbit/s) 2= fast mode (400 kbit/s) 1 3 read-write DATA_CMD_REG I2C Rx/Tx Data Buffer and Command Register 0x10 16 read-write n 0x0 0x0 CMD This bit controls whether a read or a write is performed. This bit does not control the direction when the I2C Ctrl acts as a slave. It controls only the direction when it acts as a master. 1 = Read 0 = Write When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a don't care because writes to this register are not required. In slave-transmitter mode, a 0 indicates that CPU data is to be transmitted and as DAT or IC_DATA_CMD[7:0]. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the I2C_RAW_INTR_STAT_REG), unless bit 11 (SPECIAL) in the I2C_TAR register has been cleared. If a 1 is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. NOTE: It is possible that while attempting a master I2C read transfer on the controller, a RD_REQ interrupt may have occurred simultaneously due to a remote I2C master addressing the controller. In this type of scenario, it ignores the I2C_DATA_CMD write, generates a TX_ABRT interrupt, and waits to service the RD_REQ interrupt 8 9 read-write DAT This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the controller. However, when you read this register, these bits return the value of data received on the controller's interface. 0 8 read-write DMA_CR_REG DMA Control Register 0x88 16 read-write n 0x0 0x0 RDMAE Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. 0 = Receive DMA disabled 1 = Receive DMA enabled 0 1 read-write TDMAE Transmit DMA Enable. //This bit enables/disables the transmit FIFO DMA channel. 0 = Transmit DMA disabled 1 = Transmit DMA enabled 1 2 read-write DMA_RDLR_REG I2C Receive Data Level Register 0x90 16 read-write n 0x0 0x0 DMARDL Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1 that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. 0 5 read-write DMA_TDLR_REG DMA Transmit Data Level Register 0x8C 16 read-write n 0x0 0x0 DMATDL Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. 0 5 read-write ENABLE_REG I2C Enable Register 0x6C 16 read-write n 0x0 0x0 CTRL_ENABLE Controls whether the controller is enabled. 0: Disables the controller (TX and RX FIFOs are held in an erased state) 1: Enables the controller Software can disable the controller while it is active. However, it is important that care be taken to ensure that the controller is disabled properly. When the controller is disabled, the following occurs: * The TX FIFO and RX FIFO get flushed. * Status bits in the IC_INTR_STAT register are still active until the controller goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the controller stops the current transfer at the end of the current byte and does not acknowledge the transfer. There is a two ic_clk delay when enabling or disabling the controller 0 1 read-write I2C_ABORT 0= ABORT not initiated or ABORT done 1= ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. 1 2 read-write ENABLE_STATUS_REG I2C Enable Status Register 0x9C 16 read-write n 0x0 0x0 IC_EN ic_en Status. This bit always reflects the value driven on the output port ic_en. When read as 1, the controller is deemed to be in an enabled state. When read as 0, the controller is deemed completely inactive. NOTE: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). 0 1 read-only SLV_DISABLED_WHILE_BUSY Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) I2C Ctrl is receiving the address byte of the Slave-Transmitter operation from a remote master OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, the controller is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in I2C Ctrl (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit will also be set to 1. When read as 0, the controller is deemed to have been disabled when there is master activity, or when the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. 1 2 read-only SLV_RX_DATA_LOST Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting of IC_ENABLE from 1 to 0. When read as 1, the controller is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit is also set to 1. When read as 0, the controller is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. 2 3 read-only FS_SCL_HCNT_REG Fast Speed I2C Clock SCL High Count Register 0x1C 16 read-write n 0x0 0x0 IC_FS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set. 0 16 read-write FS_SCL_LCNT_REG Fast Speed I2C Clock SCL Low Count Register 0x20 16 read-write n 0x0 0x0 IC_FS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low-period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the controller. The lower byte must be programmed first. Then the upper byte is programmed. 0 16 read-write HS_MADDR_REG I2C High Speed Master Mode Code Address Register 0xC 16 read-write n 0x0 0x0 IIC_HS_MAR This bit field holds the value of the I2C HS mode master code. 0 3 read-write IC_FS_SPKLEN_REG I2C SS and FS spike suppression limit Size 0xA0 16 read-write n 0x0 0x0 IC_FS_SPKLEN This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 1 hardware prevents values less than this being written, and if attempted results in 1 being set. 0 8 read-write INTR_MASK_REG I2C Interrupt Mask Register 0x30 16 read-write n 0x0 0x0 M_ACTIVITY These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 8 9 read-write M_GEN_CALL These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 11 12 read-write M_RD_REQ These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 5 6 read-write M_RX_DONE These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 7 8 read-write M_RX_FULL These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 2 3 read-write M_RX_OVER These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 1 2 read-write M_RX_UNDER These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 0 1 read-write M_START_DET These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 10 11 read-write M_STOP_DET These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 9 10 read-write M_TX_ABRT These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 6 7 read-write M_TX_EMPTY These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 4 5 read-write M_TX_OVER These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register. 3 4 read-write INTR_STAT_REG I2C Interrupt Status Register 0x2C 16 read-write n 0x0 0x0 R_ACTIVITY This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it: => Disabling the I2C Ctrl => Reading the IC_CLR_ACTIVITY register => Reading the IC_CLR_INTR register => System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus. 8 9 read-only R_GEN_CALL Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. The controller stores the received data in the Rx buffer. 11 12 read-only R_RD_REQ This bit is set to 1 when the controller is acting as a slave and another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register 5 6 read-only R_RX_DONE When the controller is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. 7 8 read-only R_RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. 2 3 read-only R_RX_OVER Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 1 2 read-only R_RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 0 1 read-only R_START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 10 11 read-only R_STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 9 10 read-only R_TX_ABRT This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a transmit abort . When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface. 6 7 read-only R_TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0. 4 5 read-only R_TX_OVER Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared 3 4 read-only RAW_INTR_STAT_REG I2C Raw Interrupt Status Register 0x34 16 read-write n 0x0 0x0 ACTIVITY This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it: => Disabling the I2C Ctrl => Reading the IC_CLR_ACTIVITY register => Reading the IC_CLR_INTR register => System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus. 8 9 read-only GEN_CALL Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. I2C Ctrl stores the received data in the Rx buffer. 11 12 read-only RD_REQ This bit is set to 1 when I2C Ctrl is acting as a slave and another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register 5 6 read-only RX_DONE When the controller is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. 7 8 read-only RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. 2 3 read-only RX_OVER Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 1 2 read-only RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. 0 1 read-only START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 10 11 read-only STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode. 9 10 read-only TX_ABRT This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a transmit abort . When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface. 6 7 read-only TX_EMPTY This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0. 4 5 read-only TX_OVER Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared 3 4 read-only RXFLR_REG I2C Receive FIFO Level Register 0x78 16 read-write n 0x0 0x0 RXFLR Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Size is constrained by the RXFLR value 0 6 read-only RX_TL_REG I2C Receive FIFO Threshold Register 0x38 16 read-write n 0x0 0x0 RX_TL Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in I2C_RAW_INTR_STAT register). The valid range is 0-3,a value of 0 sets the threshold for 1 entry, and a value of 3 sets the threshold for 4 entries 0 5 read-write SAR_REG I2C Slave Address Register 0x8 16 read-write n 0x0 0x0 IC_SAR The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. 0 10 read-write SDA_HOLD_REG I2C SDA Hold Time Length Register 0x7C 16 read-write n 0x0 0x0 IC_SDA_HOLD SDA Hold time 0 16 read-write SDA_SETUP_REG I2C SDA Setup Register 0x94 16 read-write n 0x0 0x0 SDA_SETUP SDA Setup. This register controls the amount of time delay (number of I2C clock periods) between the rising edge of SCL and SDA changing by holding SCL low when I2C block services a read request while operating as a slave-transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. It is recommended that if the required delay is 1000ns, then for an I2C frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11.Writes to this register succeed only when IC_ENABLE[0] = 0. 0 8 read-write SS_SCL_HCNT_REG Standard Speed I2C Clock SCL High Count Register 0x14 16 read-write n 0x0 0x0 IC_SS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set. NOTE: This register must not be programmed to a value higher than 65525, because the controller uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. 0 16 read-write SS_SCL_LCNT_REG Standard Speed I2C Clock SCL Low Count Register 0x18 16 read-write n 0x0 0x0 IC_SS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted, results in 8 being set. 0 16 read-write STATUS_REG I2C Status Register 0x70 16 read-write n 0x0 0x0 I2C_ACTIVITY I2C Activity Status. 0 1 read-only MST_ACTIVITY Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. 0: Master FSM is in IDLE state so the Master part of the controller is not Active 1: Master FSM is not in IDLE state so the Master part of the controller is Active 5 6 read-only RFF Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0: Receive FIFO is not full 1: Receive FIFO is full 4 5 read-only RFNE Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries it is cleared when the receive FIFO is empty. 0: Receive FIFO is empty 1: Receive FIFO is not empty 3 4 read-only SLV_ACTIVITY Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. 0: Slave FSM is in IDLE state so the Slave part of the controller is not Active 1: Slave FSM is not in IDLE state so the Slave part of the controller is Active 6 7 read-only TFE Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0: Transmit FIFO is not empty 1: Transmit FIFO is empty 2 3 read-only TFNF Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0: Transmit FIFO is full 1: Transmit FIFO is not full 1 2 read-only TAR_REG I2C Target Address Register 0x4 16 read-write n 0x0 0x0 GC_OR_START If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the controller. 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The controller remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. 1: START BYTE 10 11 read-write IC_TAR This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. Note: If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself it can transmit to only a slave Writes to this register succeed only when IC_ENABLE[0] is set to 0 0 10 read-write SPECIAL This bit indicates whether software performs a General Call or START BYTE command. 0: ignore bit 10 GC_OR_START and use IC_TAR normally 1: perform special I2C command as specified in GC_OR_START bit 11 12 read-write TXFLR_REG I2C Transmit FIFO Level Register 0x74 16 read-write n 0x0 0x0 TXFLR Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Size is constrained by the TXFLR value 0 6 read-only TX_ABRT_SOURCE_REG I2C Transmit Abort Source Register 0x80 16 read-write n 0x0 0x0 ABRT_10ADDR1_NOACK 1: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. 1 2 read-only ABRT_10ADDR2_NOACK 1: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave. 2 3 read-only ABRT_10B_RD_NORSTRT 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode. 10 11 read-only ABRT_7B_ADDR_NOACK 1: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. 0 1 read-only ABRT_GCALL_NOACK 1: the controller in master mode sent a General Call and no slave on the bus acknowledged the General Call. 4 5 read-only ABRT_GCALL_READ 1: the controller in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). 5 6 read-only ABRT_HS_ACKDET 1: Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). 6 7 read-only ABRT_HS_NORSTRT 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode 8 9 read-only ABRT_MASTER_DIS 1: User tries to initiate a Master operation with the Master mode disabled. 11 12 read-only ABRT_SBYTE_ACKDET 1: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). 7 8 read-only ABRT_SBYTE_NORSTRT To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first restart must be enabled (I2C_CON[5]=1), the SPECIAL bit must be cleared (I2C_TAR[11]), or the GC_OR_START bit must be cleared (I2C_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets re-asserted. 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to send a START Byte. 9 10 read-only ABRT_SLVFLUSH_TXFIFO 1: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. 13 14 read-only ABRT_SLVRD_INTX 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of 2IC_DATA_CMD register 15 16 read-only ABRT_SLV_ARBLOST 1: Slave lost the bus while transmitting data to a remote master. I2C_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never owns the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then the controller no longer own the bus. 14 15 read-only ABRT_TXDATA_NOACK 1: This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). 3 4 read-only ARB_LOST 1: Master has lost arbitration, or if I2C_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. Note: I2C can be both master and slave at the same time. 12 13 read-only TX_TL_REG I2C Transmit FIFO Threshold Register 0x3C 16 read-write n 0x0 0x0 TX_TL Transmit FIFO Threshold Level Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in I2C_RAW_INTR_STAT register). The valid range is 0-3, a value of 0 sets the threshold for 0 entries, and a value of 3 sets the threshold for 4 entries.. 0 5 read-write IR IR registers Peripheral_Registers 0x0 0x0 0x14 registers n CTRL_REG IR control register 0x8 16 read-write n 0x0 0x0 IR_CODE_FIFO_RESET 1 = Flush Code FIFO (auto clear) 0 1 write-only IR_ENABLE 1 = IR block is enabled 0 = IR block is disabled and at reset state. This also resets the pointers at the FIFOs 2 3 read-write IR_INVERT_OUTPUT 1 = IR output is inverted 0 = IR output is not inverted 5 6 read-write IR_IRQ_EN 1 = Enables the interrupt generation upon TX completion 0 = masks out the interrupt generation upon TX completion 8 9 read-write IR_LOGIC_ONE_FORMAT 1 = Logic one starts with a Space followed by a Mark 0 = Logic one starts with a Mark followed by a Space 7 8 read-write IR_LOGIC_ZERO_FORMAT 1 = Logic zero starts with a Space followed by a Mark 0 = Logic zero starts with a Mark followed by a Space 6 7 read-write IR_REPEAT_TYPE 1 = repeat command is defined at Repeat FIFO 0 = repeat command is defined at Code FIFO 4 5 read-write IR_REP_FIFO_RESET 1 = Flush Repeat FIFO (auto clear) 1 2 write-only IR_TX_START 1 = IR transmits a command 0 = IR is stopped While this bit is 1 and SW programs it to 0, the code FIFO will be flushed automatically. 3 4 read-write FREQ_CARRIER_OFF_REG Defnes the carrier signal low duration 0x2 16 read-write n 0x0 0x0 IR_FREQ_CARRIER_OFF Defines the carrier signal low duration in IR_clk cycles 0 10 read-write FREQ_CARRIER_ON_REG Defines the carrier signal high duration 0x0 16 read-write n 0x0 0x0 IR_FREQ_CARRIER_ON Defines the carrier signal high duration in IR_clk cycles. 0x0 is not allowed as a value. 0 10 read-write IRQ_STATUS_REG IR interrupt status register 0x12 16 read-write n 0x0 0x0 IR_IRQ_ACK When read Interrupt line is cleared 0 1 read-only LOGIC_ONE_TIME_REG Defines the logic one waveform 0x4 16 read-write n 0x0 0x0 IR_LOGIC_ONE_MARK Defines the mark duration in carrier clock cycles. Must be >0 8 16 read-write IR_LOGIC_ONE_SPACE Defines the space duration in carrier clock cycles. Must be >0 0 8 read-write LOGIC_ZERO_TIME_REG Defines the logic zero wavefrom 0x6 16 read-write n 0x0 0x0 IR_LOGIC_ZERO_MARK Defines the mark duration in carrier clock cycles. Must be >0 8 16 read-write IR_LOGIC_ZERO_SPACE Defines the space duration in carrier clock cycles. Must be >0 0 8 read-write MAIN_FIFO_REG Main fifo write register 0xE 16 read-write n 0x0 0x0 IR_CODE_FIFO_DATA Code FIFO data write port 0 16 write-only REPEAT_FIFO_REG Repeat fifo write register 0x10 16 read-write n 0x0 0x0 IR_REPEAT_FIFO_DATA Repeat FIFO data write port 0 16 write-only REPEAT_TIME_REG Defines the repeat time 0xC 16 read-write n 0x0 0x0 IR_REPEAT_TIME Defines the repeat time in carrier clock cycles. The repeat timer will start counting from the start of the command and will trigger the output of the same command residing in the Code FIFO or the special command residing in the Repeat FIFO as soon as it expires. 0 16 read-write STATUS_REG IR status register 0xA 16 read-write n 0x0 0x0 IR_BUSY 1 = IR generator is busy sending a message 0 = IR generator is idle 10 11 read-only IR_CODE_FIFO_WRDS Contains the amount of words in Code FIFO (updated only on write) 0 6 read-only IR_REP_FIFO_WRDS Contains the amount of words in Repeat FIFO (updated only on write) 6 10 read-only KBSCAN KBSCAN registers Peripheral_Registers 0x0 0x0 0x5C registers n KBSCN_CTRL2_REG Keyboard scanner control 2 register 0x2 16 read-write n 0x0 0x0 KBSCN_ROW_ACTIVE_TIME Define the row active time in keyboard clock cycles 0 16 read-write KBSCN_CTRL_REG Keyboard scanner control register 0x0 16 read-write n 0x0 0x0 KBSCN_CLKDIV Defines keyboard clk. 00 div/1, 01 div/4, 10 div/16, 11 div/64 12 14 read-write KBSCN_EN '1' : Enable keyboard scanner, Auto clear when inactive enable and inactive case 0 1 read-write KBSCN_INACTIVE_EN '1' After inactive time the keyboard scanner stops the key maxtrix scan 11 12 read-write KBSCN_INACTIVE_TIME Defines the inactive time in scan cycles. Value 0 is not allowed 4 11 read-write KBSCN_IRQ_FIFO_MASK '1' Enable IRQ for fifo over and under flow 3 4 read-write KBSCN_IRQ_INACTIVE_MASK '1' : Enable IRQ for inactive 2 3 read-write KBSCN_IRQ_MESSAGE_MASK '1' : Enable IRQ for message 1 2 read-write KBSCN_RESET_FIFO '1' reset fifo, read always '0' 14 15 write-only KBSCN_DEBOUNCE_REG Defines the debounce time for key press and release 0x6 16 read-write n 0x0 0x0 KBSCN_DEBOUNCE_PRESS_TIME Defines the press debounce time in cycles of full matrix scan. One means no debounce, zero is reserved 6 12 read-write KBSCN_DEBOUNCE_RELEASE_TIME Defines the press debounce time in cycles of full matrix scan. One means no debounce, zero is reserved 0 6 read-write KBSCN_MATRIX_SIZE_REG Defines the number of rows and columns of the matrix 0x4 16 read-write n 0x0 0x0 KBSCN_MATRIX_COLUMN Defines the number of the columns of the keyboard matrix minus 1. Zero means number of columns 1 4 9 read-write KBSCN_MATRIX_ROW Defines the number of the rows of the keyboard matrix minus 1. Zero means number of rows 1 0 4 read-write KBSCN_MESSAGE_KEY_REG Returns a key message from the message queue 0xA 16 read-write n 0x0 0x0 KBSCN_KEYID_COLUMN Defines the column id of key 4 9 read-only KBSCN_KEYID_ROW Defines the row id of key 0 4 read-only KBSCN_KEY_STATE '0' : New key state is release '1' : New key state is press 9 10 read-only KBSCN_LAST_ENTRY '1' : this message is the last of the group message, else '0'. When '1' bits 9:0 are all '1' 10 11 read-only KBSCN_P00_MODE_REG Defines the keyboard mode for P00 0xC 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P01_MODE_REG Defines the keyboard mode for P01 0xE 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P02_MODE_REG Defines the keyboard mode for P02 0x10 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P03_MODE_REG Defines the keyboard mode for P03 0x12 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P04_MODE_REG Defines the keyboard mode for P04 0x14 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P05_MODE_REG Defines the keyboard mode for P05 0x16 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P06_MODE_REG Defines the keyboard mode for P06 0x18 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P07_MODE_REG Defines the keyboard mode for P07 0x1A 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P10_MODE_REG Defines the keyboard mode for P10 0x1C 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P11_MODE_REG Defines the keyboard mode for P11 0x1E 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P12_MODE_REG Defines the keyboard mode for P12 0x20 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P13_MODE_REG Defines the keyboard mode for P13 0x22 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P14_MODE_REG Defines the keyboard mode for P14 0x24 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P15_MODE_REG Defines the keyboard mode for P15 0x26 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P16_MODE_REG Defines the keyboard mode for P16 0x28 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P17_MODE_REG Defines the keyboard mode for P17 0x2A 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P20_MODE_REG Defines the keyboard mode for P20 0x2C 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P21_MODE_REG Defines the keyboard mode for P21 0x2E 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P22_MODE_REG Defines the keyboard mode for P22 0x30 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P23_MODE_REG Defines the keyboard mode for P23 0x32 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P24_MODE_REG Defines the keyboard mode for P24 0x34 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P30_MODE_REG Defines the keyboard mode for P30 0x3C 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P31_MODE_REG Defines the keyboard mode for P31 0x3E 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P32_MODE_REG Defines the keyboard mode for P32 0x40 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P33_MODE_REG Defines the keyboard mode for P33 0x42 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P34_MODE_REG Defines the keyboard mode for P34 0x44 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P35_MODE_REG Defines the keyboard mode for P35 0x46 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P36_MODE_REG Defines the keyboard mode for P36 0x48 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P37_MODE_REG Defines the keyboard mode for P37 0x4A 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P40_MODE_REG Defines the keyboard mode for P40 0x4C 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P41_MODE_REG Defines the keyboard mode for P41 0x4E 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P42_MODE_REG Defines the keyboard mode for P42 0x50 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P43_MODE_REG Defines the keyboard mode for P43 0x52 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P44_MODE_REG Defines the keyboard mode for P44 0x54 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P45_MODE_REG Defines the keyboard mode for P45 0x56 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P46_MODE_REG Defines the keyboard mode for P46 0x58 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_P47_MODE_REG Defines the keyboard mode for P47 0x5A 16 read-write n 0x0 0x0 KBSCN_GPIO_EN '1' GPIO is enable for row or column 6 7 read-write KBSCN_MODE Defines the row/column index that has to be connected 0 5 read-write KBSCN_ROW '1' GPIO is row, '0' GPIO is column 5 6 read-write KBSCN_STATUS_REG keyboard scanner Interrupt status register 0x8 16 read-write n 0x0 0x0 KBSCN_FIFO_OVERFL '1' Fifo Overflow occurred 7 8 read-only KBSCN_FIFO_UNDERFL '1' Fifo Underflow occurred 8 9 read-only KBSCN_INACTIVE_IRQ_STATUS There is no keyboard activity for a predefined time 1 2 read-only KBSCN_MES_IRQ_STATUS There is at least one last message in the fifo. 0 1 read-only KBSCN_NUM_MESSAGE Defines how many messages there are in the fifo. 2 7 read-only NVIC Cortex M0 NVIC registers NVIC 0x0 0x0 0x321 registers n ICER Interrupt clear-enable register 0x80 32 read-write n 0x0 0x0 ADC_IRQn ADC_IRQn (Interrupt clear-enable bit) 14 15 read-write BLE_GEN_IRQn BLE_GEN_IRQn (Interrupt clear-enable bit) 1 2 read-write BLE_WAKEUP_LP_IRQn BLE_WAKEUP_LP_IRQn (Interrupt clear-enable bit) 0 1 read-write COEX_IRQn COEX_IRQn (Interrupt clear-enable bit) 5 6 read-write CRYPTO_IRQn CRYPTO_IRQn (Interrupt clear-enable bit) 6 7 read-write DCDC_IRQn DCDC_IRQn (Interrupt clear-enable bit) 29 30 read-write DMA_IRQn DMA_IRQn (Interrupt clear-enable bit) 26 27 read-write FTDF_GEN_IRQn FTDF_GEN_IRQn (Interrupt clear-enable bit) 3 4 read-write FTDF_WAKEUP_IRQn FTDF_WAKEUP_IRQn (Interrupt clear-enable bit) 2 3 read-write I2C2_IRQn I2C2_IRQn (Interrupt clear-enable bit) 11 12 read-write I2C_IRQn I2C_IRQn (Interrupt clear-enable bit) 10 11 read-write IRGEN_IRQn IRGEN_IRQn (Interrupt clear-enable bit) 16 17 read-write KEYBRD_IRQn KEYBRD_IRQn (Interrupt clear-enable bit) 15 16 read-write MRM_IRQn MRM_IRQn (Interrupt clear-enable bit) 7 8 read-write PCM_IRQn PCM_IRQn (Interrupt clear-enable bit) 22 23 read-write QUADEC_IRQn QUADEC_IRQn (Interrupt clear-enable bit) 20 21 read-write RFCAL_IRQn RFCAL_IRQn (Interrupt clear-enable bit) 4 5 read-write RF_DIAG_IRQn RF_DIAG_IRQn (Interrupt clear-enable bit) 27 28 read-write Rsvd__irq__n Rsvd__irq__n (Reserved) 31 32 read-write SPI2_IRQn SPI2_IRQn (Interrupt clear-enable bit) 13 14 read-write SPI_IRQn SPI_IRQn (Interrupt clear-enable bit) 12 13 read-write SRC_IN_IRQn SRC_IN_IRQn (Interrupt clear-enable bit) 23 24 read-write SRC_OUT_IRQn SRC_OUT_IRQn (Interrupt clear-enable bit) 24 25 read-write SWTIM0_IRQn SWTIM0_IRQn (Interrupt clear-enable bit) 18 19 read-write SWTIM1_IRQn SWTIM1_IRQn (Interrupt clear-enable bit) 19 20 read-write TRNG_IRQn TRNG_IRQn (Interrupt clear-enable bit) 28 29 read-write UART2_IRQn UART2_IRQn (Interrupt clear-enable bit) 9 10 read-write UART_IRQn UART_IRQn (Interrupt clear-enable bit) 8 9 read-write USB_IRQn USB_IRQn (Interrupt clear-enable bit) 21 22 read-write VBUS_IRQn VBUS_IRQn (Interrupt clear-enable bit) 25 26 read-write WKUP_GPIO_IRQn WKUP_GPIO_IRQn (Interrupt clear-enable bit) 17 18 read-write XTAL16RDY_IRQn XTAL16RDY_IRQn (Interrupt clear-enable bit) 30 31 read-write ICPR Interrupt clear-pending register 0x180 32 read-write n 0x0 0x0 ADC_IRQn ADC_IRQn (Interrupt clear-pending bit) 14 15 read-write BLE_GEN_IRQn BLE_GEN_IRQn (Interrupt clear-pending bit) 1 2 read-write BLE_WAKEUP_LP_IRQn BLE_WAKEUP_LP_IRQn (Interrupt clear-pending bit) 0 1 read-write COEX_IRQn COEX_IRQn (Interrupt clear-pending bit) 5 6 read-write CRYPTO_IRQn CRYPTO_IRQn (Interrupt clear-pending bit) 6 7 read-write DCDC_IRQn DCDC_IRQn (Interrupt clear-pending bit) 29 30 read-write DMA_IRQn DMA_IRQn (Interrupt clear-pending bit) 26 27 read-write FTDF_GEN_IRQn FTDF_GEN_IRQn (Interrupt clear-pending bit) 3 4 read-write FTDF_WAKEUP_IRQn FTDF_WAKEUP_IRQn (Interrupt clear-pending bit) 2 3 read-write I2C2_IRQn I2C2_IRQn (Interrupt clear-pending bit) 11 12 read-write I2C_IRQn I2C_IRQn (Interrupt clear-pending bit) 10 11 read-write IRGEN_IRQn IRGEN_IRQn (Interrupt clear-pending bit) 16 17 read-write KEYBRD_IRQn KEYBRD_IRQn (Interrupt clear-pending bit) 15 16 read-write MRM_IRQn MRM_IRQn (Interrupt clear-pending bit) 7 8 read-write PCM_IRQn PCM_IRQn (Interrupt clear-pending bit) 22 23 read-write QUADEC_IRQn QUADEC_IRQn (Interrupt clear-pending bit) 20 21 read-write RFCAL_IRQn RFCAL_IRQn (Interrupt clear-pending bit) 4 5 read-write RF_DIAG_IRQn RF_DIAG_IRQn (Interrupt clear-pending bit) 27 28 read-write Rsvd__irq__n Rsvd__irq__n (Reserved) 31 32 read-write SPI2_IRQn SPI2_IRQn (Interrupt clear-pending bit) 13 14 read-write SPI_IRQn SPI_IRQn (Interrupt clear-pending bit) 12 13 read-write SRC_IN_IRQn SRC_IN_IRQn (Interrupt clear-pending bit) 23 24 read-write SRC_OUT_IRQn SRC_OUT_IRQn (Interrupt clear-pending bit) 24 25 read-write SWTIM0_IRQn SWTIM0_IRQn (Interrupt clear-pending bit) 18 19 read-write SWTIM1_IRQn SWTIM1_IRQn (Interrupt clear-pending bit) 19 20 read-write TRNG_IRQn TRNG_IRQn (Interrupt clear-pending bit) 28 29 read-write UART2_IRQn UART2_IRQn (Interrupt clear-pending bit) 9 10 read-write UART_IRQn UART_IRQn (Interrupt clear-pending bit) 8 9 read-write USB_IRQn USB_IRQn (Interrupt clear-pending bit) 21 22 read-write VBUS_IRQn VBUS_IRQn (Interrupt clear-pending bit) 25 26 read-write WKUP_GPIO_IRQn WKUP_GPIO_IRQn (Interrupt clear-pending bit) 17 18 read-write XTAL16RDY_IRQn XTAL16RDY_IRQn (Interrupt clear-pending bit) 30 31 read-write IPR0 Interrupt priority register 0 0x300 32 read-write n 0x0 0x0 BLE_GEN_IRQn_prio BLE_GEN_IRQn[7:0] bits (Interrupt priority) 8 16 read-write BLE_WAKEUP_LP_IRQn_prio BLE_WAKEUP_LP_IRQn[7:0] bits (Interrupt priority) 0 8 read-write FTDF_GEN_IRQn_prio FTDF_GEN_IRQn[7:0] bits (Interrupt priority) 24 32 read-write FTDF_WAKEUP_IRQn_prio FTDF_WAKEUP_IRQn[7:0] bits (Interrupt priority) 16 24 read-write IPR1 Interrupt priority register 1 0x304 32 read-write n 0x0 0x0 COEX_IRQn_prio COEX_IRQn[7:0] bits (Interrupt priority) 8 16 read-write CRYPTO_IRQn_prio CRYPTO_IRQn[7:0] bits (Interrupt priority) 16 24 read-write MRM_IRQn_prio MRM_IRQn[7:0] bits (Interrupt priority) 24 32 read-write RFCAL_IRQn_prio RFCAL_IRQn[7:0] bits (Interrupt priority) 0 8 read-write IPR2 Interrupt priority register 2 0x308 32 read-write n 0x0 0x0 I2C2_IRQn_prio I2C2_IRQn[7:0] bits (Interrupt priority) 24 32 read-write I2C_IRQn_prio I2C_IRQn[7:0] bits (Interrupt priority) 16 24 read-write UART2_IRQn_prio UART2_IRQn[7:0] bits (Interrupt priority) 8 16 read-write UART_IRQn_prio UART_IRQn[7:0] bits (Interrupt priority) 0 8 read-write IPR3 Interrupt priority register 3 0x30C 32 read-write n 0x0 0x0 ADC_IRQn_prio ADC_IRQn[7:0] bits (Interrupt priority) 16 24 read-write KEYBRD_IRQn_prio KEYBRD_IRQn[7:0] bits (Interrupt priority) 24 32 read-write SPI2_IRQn_prio SPI2_IRQn[7:0] bits (Interrupt priority) 8 16 read-write SPI_IRQn_prio SPI_IRQn[7:0] bits (Interrupt priority) 0 8 read-write IPR4 Interrupt priority register 4 0x310 32 read-write n 0x0 0x0 IRGEN_IRQn_prio IRGEN_IRQn[7:0] bits (Interrupt priority) 0 8 read-write SWTIM0_IRQn_prio SWTIM0_IRQn[7:0] bits (Interrupt priority) 16 24 read-write SWTIM1_IRQn_prio SWTIM1_IRQn[7:0] bits (Interrupt priority) 24 32 read-write WKUP_GPIO_IRQn_prio WKUP_GPIO_IRQn[7:0] bits (Interrupt priority) 8 16 read-write IPR5 Interrupt priority register 5 0x314 32 read-write n 0x0 0x0 PCM_IRQn_prio PCM_IRQn[7:0] bits (Interrupt priority) 16 24 read-write QUADEC_IRQn_prio QUADEC_IRQn[7:0] bits (Interrupt priority) 0 8 read-write SRC_IN_IRQn_prio SRC_IN_IRQn[7:0] bits (Interrupt priority) 24 32 read-write USB_IRQn_prio USB_IRQn[7:0] bits (Interrupt priority) 8 16 read-write IPR6 Interrupt priority register 6 0x318 32 read-write n 0x0 0x0 DMA_IRQn_prio DMA_IRQn[7:0] bits (Interrupt priority) 16 24 read-write RF_DIAG_IRQn_prio RF_DIAG_IRQn[7:0] bits (Interrupt priority) 24 32 read-write SRC_OUT_IRQn_prio SRC_OUT_IRQn[7:0] bits (Interrupt priority) 0 8 read-write VBUS_IRQn_prio VBUS_IRQn[7:0] bits (Interrupt priority) 8 16 read-write IPR7 Interrupt priority register 7 0x31C 32 read-write n 0x0 0x0 DCDC_IRQn_prio DCDC_IRQn[7:0] bits (Interrupt priority) 8 16 read-write RESERVED31_IRQn_DONT_USE RESERVED31_IRQn[7:0] bits (Reserved) 24 32 read-write TRNG_IRQn_prio TRNG_IRQn[7:0] bits (Interrupt priority) 0 8 read-write XTAL16RDY_IRQn_prio XTAL16RDY_IRQn[7:0] bits (Interrupt priority) 16 24 read-write ISER Interrupt set-enable register 0x0 32 read-write n 0x0 0x0 ADC_IRQn ADC_IRQn (Interrupt set-enable bit) 14 15 read-write BLE_GEN_IRQn BLE_GEN_IRQn (Interrupt set-enable bit) 1 2 read-write BLE_WAKEUP_LP_IRQn BLE_WAKEUP_LP_IRQn (Interrupt set-enable bit) 0 1 read-write COEX_IRQn COEX_IRQn (Interrupt set-enable bit) 5 6 read-write CRYPTO_IRQn CRYPTO_IRQn (Interrupt set-enable bit) 6 7 read-write DCDC_IRQn DCDC_IRQn (Interrupt set-enable bit) 29 30 read-write DMA_IRQn DMA_IRQn (Interrupt set-enable bit) 26 27 read-write FTDF_GEN_IRQn FTDF_GEN_IRQn (Interrupt set-enable bit) 3 4 read-write FTDF_WAKEUP_IRQn FTDF_WAKEUP_IRQn (Interrupt set-enable bit) 2 3 read-write I2C2_IRQn I2C2_IRQn (Interrupt set-enable bit) 11 12 read-write I2C_IRQn I2C_IRQn (Interrupt set-enable bit) 10 11 read-write IRGEN_IRQn IRGEN_IRQn (Interrupt set-enable bit) 16 17 read-write KEYBRD_IRQn KEYBRD_IRQn (Interrupt set-enable bit) 15 16 read-write MRM_IRQn MRM_IRQn (Interrupt set-enable bit) 7 8 read-write PCM_IRQn PCM_IRQn (Interrupt set-enable bit) 22 23 read-write QUADEC_IRQn QUADEC_IRQn (Interrupt set-enable bit) 20 21 read-write RFCAL_IRQn RFCAL_IRQn (Interrupt set-enable bit) 4 5 read-write RF_DIAG_IRQn RF_DIAG_IRQn (Interrupt set-enable bit) 27 28 read-write Rsvd__irq__n Rsvd__irq__n (Reserved) 31 32 read-write SPI2_IRQn SPI2_IRQn (Interrupt set-enable bit) 13 14 read-write SPI_IRQn SPI_IRQn (Interrupt set-enable bit) 12 13 read-write SRC_IN_IRQn SRC_IN_IRQn (Interrupt set-enable bit) 23 24 read-write SRC_OUT_IRQn SRC_OUT_IRQn (Interrupt set-enable bit) 24 25 read-write SWTIM0_IRQn SWTIM0_IRQn (Interrupt set-enable bit) 18 19 read-write SWTIM1_IRQn SWTIM1_IRQn (Interrupt set-enable bit) 19 20 read-write TRNG_IRQn TRNG_IRQn (Interrupt set-enable bit) 28 29 read-write UART2_IRQn UART2_IRQn (Interrupt set-enable bit) 9 10 read-write UART_IRQn UART_IRQn (Interrupt set-enable bit) 8 9 read-write USB_IRQn USB_IRQn (Interrupt set-enable bit) 21 22 read-write VBUS_IRQn VBUS_IRQn (Interrupt set-enable bit) 25 26 read-write WKUP_GPIO_IRQn WKUP_GPIO_IRQn (Interrupt set-enable bit) 17 18 read-write XTAL16RDY_IRQn XTAL16RDY_IRQn (Interrupt set-enable bit) 30 31 read-write ISPR Interrupt set-pending register 0x100 32 read-write n 0x0 0x0 ADC_IRQn ADC_IRQn (Interrupt set-pending bit) 14 15 read-write BLE_GEN_IRQn BLE_GEN_IRQn (Interrupt set-pending bit) 1 2 read-write BLE_WAKEUP_LP_IRQn BLE_WAKEUP_LP_IRQn (Interrupt set-pending bit) 0 1 read-write COEX_IRQn COEX_IRQn (Interrupt set-pending bit) 5 6 read-write CRYPTO_IRQn CRYPTO_IRQn (Interrupt set-pending bit) 6 7 read-write DCDC_IRQn DCDC_IRQn (Interrupt set-pending bit) 29 30 read-write DMA_IRQn DMA_IRQn (Interrupt set-pending bit) 26 27 read-write FTDF_GEN_IRQn FTDF_GEN_IRQn (Interrupt set-pending bit) 3 4 read-write FTDF_WAKEUP_IRQn FTDF_WAKEUP_IRQn (Interrupt set-pending bit) 2 3 read-write I2C2_IRQn I2C2_IRQn (Interrupt set-pending bit) 11 12 read-write I2C_IRQn I2C_IRQn (Interrupt set-pending bit) 10 11 read-write IRGEN_IRQn IRGEN_IRQn (Interrupt set-pending bit) 16 17 read-write KEYBRD_IRQn KEYBRD_IRQn (Interrupt set-pending bit) 15 16 read-write MRM_IRQn MRM_IRQn (Interrupt set-pending bit) 7 8 read-write PCM_IRQn PCM_IRQn (Interrupt set-pending bit) 22 23 read-write QUADEC_IRQn QUADEC_IRQn (Interrupt set-pending bit) 20 21 read-write RFCAL_IRQn RFCAL_IRQn (Interrupt set-pending bit) 4 5 read-write RF_DIAG_IRQn RF_DIAG_IRQn (Interrupt set-pending bit) 27 28 read-write Rsvd__irq__n Rsvd__irq__n (Reserved) 31 32 read-write SPI2_IRQn SPI2_IRQn (Interrupt set-pending bit) 13 14 read-write SPI_IRQn SPI_IRQn (Interrupt set-pending bit) 12 13 read-write SRC_IN_IRQn SRC_IN_IRQn (Interrupt set-pending bit) 23 24 read-write SRC_OUT_IRQn SRC_OUT_IRQn (Interrupt set-pending bit) 24 25 read-write SWTIM0_IRQn SWTIM0_IRQn (Interrupt set-pending bit) 18 19 read-write SWTIM1_IRQn SWTIM1_IRQn (Interrupt set-pending bit) 19 20 read-write TRNG_IRQn TRNG_IRQn (Interrupt set-pending bit) 28 29 read-write UART2_IRQn UART2_IRQn (Interrupt set-pending bit) 9 10 read-write UART_IRQn UART_IRQn (Interrupt set-pending bit) 8 9 read-write USB_IRQn USB_IRQn (Interrupt set-pending bit) 21 22 read-write VBUS_IRQn VBUS_IRQn (Interrupt set-pending bit) 25 26 read-write WKUP_GPIO_IRQn WKUP_GPIO_IRQn (Interrupt set-pending bit) 17 18 read-write XTAL16RDY_IRQn XTAL16RDY_IRQn (Interrupt set-pending bit) 30 31 read-write OTPC OTPC registers Peripheral_Registers 0x0 0x0 0x30 registers n AHBADR_REG AHB master start address 0xC 32 read-write n 0x0 0x0 OTPC_AHBADR It is the AHB address used by the AHB master interface of the controller (the bits [31:2]). The bits [1:0] of the address are considered always as equal to zero. 2 32 read-write CELADR_REG Macrocell start address 0x10 32 read-write n 0x0 0x0 OTPC_CELADR It represents an OTP address, where the OTP word width should be considered equal to 32-bits. The physical word width of the OTP memory is 72 bits. The 8-bits of them are used for the implementation of an error correcting code and are not available for the application. The remaining 64 bits of the physical word are available for the application. The OTPC_CELADDR can distinguish the upper 32 bits from the lower 32 bits of the available for the application bits of the OTP word. When OTPC_CELADDR[0] = 1 the address refers to the upper 32 bits of the physical OTP address OTPC_CELADDR[14:1]. The register is used during the modes: AREAD and APROG. 0 14 read-write FFPRT_REG Ports access to fifo logic 0x18 32 read-write n 0x0 0x0 OTPC_FFPRT Provides access to the fifo through an access port. Write to this register with the corresponding data, when the APROG mode is selected and the dma is disabled. Read from this register the corresponding data, when the AREAD mode is selected and the dma is disabled. The software should check the OTPCC_STAT_FWORDS register for the availability of data/space, before accessing the fifo. 0 32 read-write FFRD_REG The data which have taken with the latest read from the OTPC_FFPRT_REG 0x1C 32 read-write n 0x0 0x0 OTPC_FFRD Contains the value which taken from the fifo, after a read of the OTPC_FFPRT_REG register. 0 32 read-only MODE_REG Mode register 0x0 32 read-write n 0x0 0x0 OTPC_MODE_ERR_RESP_DIS When is performed a read from the OTP memory in the MREAD mode, a double error is likely be detected during the retrieving of the data from the OTP. This error condition is always indicated in the status bit OTPC_STAT_REG[OTPC_STAT_RERROR]. However, the OTP controller has also the ability to indicates this error condition, by generating an ERROR response in the AHB bus. The generation of the ERROR response can be avoided with the help of this configuration bit. 0 - The OTP controller generates an ERROR response in the AHB bus, when a double error is detected during a reading in MREAD mode. The OTPC_STAT_REG[OTPC_STAT_RERROR] is also updated. The receiving of an ERROR response by the CPU causes a Hard Fault exception in the CPU. 1 - Only the OTPC_STAT_REG[OTPC_STAT_RERROR] is updated in a case of such error. The OTP controller will not generate an ERROR response in the AHB bus. 6 7 read-write OTPC_MODE_FIFO_FLUSH By writing with 1, removes any content from the fifo. This bit returns automatically to value 0. 5 6 read-write OTPC_MODE_MODE Defines the mode of operation of the OTPC controller. The encoding of the modes is as follows: 000 - STBY mode 001 - MREAD mode 010 - MPROG mode 011 - AREAD mode 100 - APROG mode 101 - TBLANK mode 110 - TDEC mode 111 - TWR mode 0 3 read-write OTPC_MODE_RLD_RR_REQ Write with 1 in order to be requested the reloading of the repair records. The reloading of the repair records will be performed at the next enabling of the OTP cell. That means that first the controller should be configured to the STBY mode and after should be activated any other mode. The hardware will clear this register, when the reloading will be performed. The reloading has meaning only if the repair records have been updated manually (MPROG mode). 9 10 read-write OTPC_MODE_USE_DMA Selects the use of the dma, when the controller is configured in one of the modes: AREAD or APROG. 0 - The dma is not used. The data should be transferred from/to controller through the register OTPC_FFPRT_REG. 1 - The dma is used. The data transfers from/to controller are performed automatically, with the help of the internal DMA of the OTP controller. The AHB base address should be configured in register OTPC_AHBADR_REG, before the selection of one of the two modes: AREAD or APROG. 4 5 read-write OTPC_MODE_USE_SP_ROWS Selects the memory area of the OTP cell that will be used. 0 - Uses the normal memory area of the OTP cell 1 - Uses the spare rows of the OTP cell This selection has meaning only if the mode of the controller is not TDEC and TWR. The controller should be in STBY mode, in order to takes into account this bit. The selection will take effect at the next mode that will be enabled. 8 9 read-write NWORDS_REG Number of words 0x14 32 read-write n 0x0 0x0 OTPC_NWORDS The number of words (minus one) for reading /programming during the AREAD/APROG mode. The width of the word should be considered equal to 32-bits. The value of the register remains unchanged, by the internal logic of the controller. During mirroring, this register reflects the current ammount of copied data. 0 14 read-write PCTRL_REG Bit-programming control register 0x4 32 read-write n 0x0 0x0 OTPC_PCTRL_PRETRY It distinguishes the first attempt of a programming of an OTP position, from a retry of programming. 0 - A new value will be programmed in a blank OTP position. The hardware will try to write all the bits that are equal to '1'. 1 - The programming that is applied is not the first attempt, but is a request for reprogramming. Will be processed only the bits that were failed to be programmed during the previous attempt. The hardware knows the bits that were failed during the previous attempt. The registers OTPC_PWORDx_REG should contain the 64 bits of the value that should be programmed, independent of the value of the OTPC_PCTRL_PRETRY bit. Also, the OTPC_PCTRL_WADDR should contain always the required OTP address. A retry of a programming should be requested only if the previous action was the first attempt of programming or a retry of programming. Should not be requested a retry if the first attempt has not been performed. 14 15 read-write OTPC_PCTRL_PSTART Write with '1' to trigger the programming of one OTP word, in the case where the MPROG mode is selected. The bit is cleared automatically. The 64-bits that will be programmed into the OTP memory are contained into the two registers OTPC_PWORDx_REG. This bit should be used when a new programming is initiated, but also when the programming must be retried. The OTPC_PCTRL_WADDR defines the OTP position where will be performed the programming. 15 16 read-write OTPC_PCTRL_WADDR Defines the OTP position where will be programmed the 64-bits that are contained into the registers OTPC_PWORDx_REG. It points to a physical 72 bits OTP word. 0 13 read-write PWORDH_REG The 32 higher bits of the 64-bit word that will be programmed, when the MPROG mode is used. 0x24 32 read-write n 0x0 0x0 OTPC_PWORDH Contains the upper 32 bits that can be programmed with the help of the OTPC_PCTRL_REG, while the controller is in MPROG mode. 0 32 read-write PWORDL_REG The 32 lower bits of the 64-bit word that will be programmed, when the MPROG mode is used. 0x20 32 read-write n 0x0 0x0 OTPC_PWORDL Contains the lower 32 bits that can be programmed with the help of the OTPC_PCTRL_REG, while the controller is in MPROG mode. 0 32 read-write STAT_REG Status register 0x8 32 read-write n 0x0 0x0 OTPC_STAT_ARDY Should be used to monitor the progress of the AREAD and APROG modes. 0 - One of the APROG or AREAD mode is selected. The controller is busy. 1 - The controller is not in an active AREAD or APROG mode. 6 7 read-only OTPC_STAT_FWORDS Indicates the number of words which contained in the fifo of the controller. 8 12 read-only OTPC_STAT_NWORDS It contains the live value of the number of (32 bits) words that remain to be processed by the controller. 16 30 read-only OTPC_STAT_PERR_COR Indicates that a correctable error has been occurred during the word programming process. 0 - There is no correctable error in the word-programming process. 1 - The process of word - programming reported a correctable error. The correctable error occurs when exactly one bit in an OTP position cannot take the required value. This is not a critical failure in the programming process. The data can still be retrieved correctly by the OTP memory, due to that the error correcting algorithm can repair the corrupted bit. When the controller is in MPROG mode, this bit can be checked after the end of the programming process (OTPC_STAT_PRDY = 1). During APROG mode, the value of this field it is normal to changing periodically. After the end of the APROG mode (OTPC_STAT_ARDY = 1), this field indicates that one or more words had a correctable error. 2 3 read-only OTPC_STAT_PERR_UNC Indicates that an uncorrectable error has been occurred during the word programming process. 0 - There is no uncorrectable error in the word-programming process. 1 - The process of word-programming failed due to an uncorrectable error. An uncorrectable error is considered when two or more of the bits in an OTP position cannot take the required values. This is a critical failure in the programming process, which means that the data cannot corrected by the single error correcting algorithm. When the controller is in MPROG mode, this bit should be checked after the end of the programming process (OTPC_STAT_PRDY = 1). During APROG mode, the value of this field it is normal to changing periodically. After the end of the APROG mode (OTPC_STAT_ARDY = 1), this field indicates if the programming was failed or ended successfully. 1 2 read-only OTPC_STAT_PRDY Indicates the state of a bit-programming process. 0 - The controller is busy. A bit-programming is in progress 1 - The logic which performs bit-programming is idle. When the controller is in MPROG mode, this bit should be used to monitor the progress of a programming request. During APROG mode, the value of this field it is normal to changing periodically. 0 1 read-only OTPC_STAT_PZERO Indicates that the programming sequence has been avoided during a programming request, due to that the word that should be programmed is equal to zero. 0 - At least one bit has been programmed into the OTP. 1 - The programming has not been performed. All the bits of the word that should be programmed are equal to zero. When the controller is in MPROG mode, this bit can be checked after the end of the programming process (OTPC_STAT_PRDY = 1). During APROG mode, the value of this field it is normal to changing periodically. After the end of the APROG mode (OTPC_STAT_ARDY = 1), this field indicates that one or more of words that have been processed are equal to zero. 3 4 read-only OTPC_STAT_RERROR Indicates that during a normal reading (MREAD or AREAD) was reported a double error by the SECDED logic. That means that the data are corrupted. 0 - The read data are considered as correct. 1- The SECDED logic detects a double error. This bit can be cleared only with a write with '1'. 7 8 read-write OTPC_STAT_TERROR Indicates the result of a test sequence. Should be checked after the end of a TBLANK, TDEC and TWR mode (OTPC_STAT_TRDY = 1). 0 - The test sequence ends with no error. 1 - The test sequence has failed. 5 6 read-only OTPC_STAT_TRDY Indicates the state of a test mode. Should be used to monitor the progress of the TBLANK, TDEC and TWR modes. 0 - The controller is busy. One of the test modes is in progress. 1 - There is no active test mode. 4 5 read-only TIM1_REG Various timing parameters of the OTP cell. 0x28 32 read-write n 0x0 0x0 OTPC_TIM1_CC_T_1US The number of hclk_c clock periods (minus one) that give a time interval at least higher than 1us. 16 22 read-write OTPC_TIM1_CC_T_200NS The number of hclk_c clock periods (minus one) that give a time interval at least higher than 200ns. 27 31 read-write OTPC_TIM1_CC_T_25NS The number of hclk_c clock periods (minus one) that give a time interval at least higher than 25ns. 31 32 read-write OTPC_TIM1_CC_T_500NS The number of hclk_c clock periods (minus one) that give a time interval at least higher than 500ns 22 27 read-write OTPC_TIM1_CC_T_CADX The number of hclk_c clock periods (minus one) that give a time interval at least higher than 2us.It is used as a wait time each time where the OTP cell is enabled. 0 8 read-write OTPC_TIM1_CC_T_PW The number of hclk_c clock periods (minus one) that give a time interval that is - at least higher than 4.8us - and lower than 5.2 us It is preferred the programmed value to give a time interval equal to 5us. It defines the duration of the programming pulse for every bit that written in the OTP cell. 8 16 read-write TIM2_REG Various timing parameters of the OTP cell. 0x2C 32 read-write n 0x0 0x0 OTPC_TIM2_CC_STBY_THR This register controls a power saving feature, which is applicable only in MREAD mode. The controller monitors the accesses in the OTP cell. If there is no access for more than OTPC_TIM2_CC_STBY_THR hclk_c clock cycles, the OTP cell goes to the standby while the controller itself remains in the MREAD mode. The OTP cell will be enabled again when will be applied a new read request. The enabling of the OTP cell has a cost of 2us (OTPC_TIM1_CC_T_CADX hclk_c clock cycles). When OTPC_TIM2_CC_STBY_THR = 0 the power saving feature is disabled and the OTP cell remains active while the controller is in MREAD mode. 0 10 read-write OTPC_TIM2_CC_T_BCHK The number of hclk_c clock periods (minus one) that give a time interval between 100ns and 200ns. This time interval is used for the reading of the contents of the OTP cell during the TBLANK mode. 16 23 read-write OTPC_TIM2_RDENL_PROT This bit has meaning only when the OTPC_TIM1_CC_T_25NS = 1, otherwise has no functionality. 0 - The minimum number of clock cycles for which the signal read_enable of the OTP memory stays inactive is one clock cycle. This is also applicable if OTPC_TIM1_CC_T_25NS = 0. 1 - The minimum number of clock cycles for which the signal read_enable of the OTP memory stays inactive is two clock cycles. The controller adds one extra wait state in the AHB access , if it is required, in order to achieves this constraint. This setting is applicable only if OTPC_TIM1_CC_T_25NS = 1. 23 24 read-write QSPIC QSPIC registers Peripheral_Registers 0x0 0x0 0x44 registers n BURSTBRK_REG Read break sequence in Auto mode 0x30 32 read-write n 0x0 0x0 QSPIC_BRK_EN Controls the application of a special command (read burst break sequence) that is used in order to force the device to abandon the continuous read mode. 0 - The special command is not applied 1 - The special command is applied This special command is applied by the controller to the external device under the following conditions: - the controller is in Auto mode - the QSPIC_INST_MD = 1 - the previous command that has been applied in the external device was read - the controller want to apply to the external device a command different than the read. 16 17 read-write QSPIC_BRK_SZ The size of Burst Break Sequence 0 - One byte (Send QSPIC_BRK_WRD[15:8]) 1 - Two bytes (Send QSPIC_BRK_WRD[15:0]) 17 18 read-write QSPIC_BRK_TX_MD The mode of the QSPI Bus during the transmission of the burst break sequence. 00 - Single 01 - Dual 10 - Quad 11 - Reserved 18 20 read-write QSPIC_BRK_WRD This is the value of a special command (read burst break sequence) that is applied by the controller to the external memory device, in order to force the memory device to abandon the continuous read mode. 0 16 read-write QSPIC_SEC_HF_DS Disable output during the transmission of the second half (QSPIC_BRK_WRD[3:0]). Setting this bit is only useful if QSPIC_BRK_EN =1 and QSPIC_BRK_SZ= 1. 0 - The controller drives the QSPI bus during the transmission of the QSPIC_BRK_WRD[3:0]. 1 - The controller leaves the QSPI bus in Hi-Z during the transmission of the QSPIC_BRK_WORD[3:0]. 20 21 read-write BURSTCMDA_REG The way of reading in Auto mode (command register A) 0xC 32 read-write n 0x0 0x0 QSPIC_ADR_TX_MD It describes the mode of the SPI bus during the address phase. 00 - Single SPI 01 - Dual 10 - Quad 11 - Reserved 26 28 read-write QSPIC_DMY_TX_MD It describes the mode of the SPI bus during the Dummy bytes phase. 00 - Single SPI 01 - Dual 10 - Quad 11 - Reserved 30 32 read-write QSPIC_EXT_BYTE The value of an extra byte which will be transferred after address (only if QSPIC_EXT_BYTE_EN= 1). Usually this is the Mode Bits in Dual/Quad SPI I/O instructions. 16 24 read-write QSPIC_EXT_TX_MD It describes the mode of the SPI bus during the Extra Byte phase. 00 - Single SPI 01 - Dual 10 - Quad 11 - Reserved 28 30 read-write QSPIC_INST Instruction Value for Incremental Burst or Single read access. This value is the selected instruction at the cases of incremental burst or single read access. Also this value is used when a wrapping burst is not supported (QSPIC_WRAP_MD) 0 8 read-write QSPIC_INST_TX_MD It describes the mode of the SPI bus during the instruction phase. 00 - Single SPI 01 - Dual 10 - Quad 11 - Reserved 24 26 read-write QSPIC_INST_WB Instruction Value for Wrapping Burst. This value is the selected instruction when QSPIC_WRAP_MD is equal to 1 and the access is a wrapping burst of length and size described by the bit fields QSPIC_WRAP_LEN and QSPIC_WRAP_SIZE respectively. 8 16 read-write BURSTCMDB_REG The way of reading in Auto mode (command register B) 0x10 32 read-write n 0x0 0x0 QSPIC_CS_HIGH_MIN Between the transmissions of two different instructions to the flash memory, the SPI bus stays in idle state (QSPI_CS high) for at least this number of QSPI_SCK clock cycles. See the QSPIC_ERS_CS_HI register for some exceptions. 12 15 read-write QSPIC_DAT_RX_MD It describes the mode of the SPI bus during the data phase. 00 - Single SPI 01 - Dual 10 - Quad 11 - Reserved 0 2 read-write QSPIC_DMY_FORCE By setting this bit, the number of dummy bytes is forced to be equal to 3. In this case the QSPIC_DMY_NUM field is overruled and has no function. 0 - The number of dummy bytes is controlled by the QSPIC_DMY_NUM field 1 - Three dummy bytes are used. The QSPIC_DMY_NUM is overruled. 15 16 read-write QSPIC_DMY_NUM Number of Dummy Bytes 00 - Zero Dummy Bytes (Don't Send Dummy Bytes) 01 - Send 1 Dummy Byte 10 - Send 2 Dummy Bytes 11 - Send 4 Dummy Bytes When QSPIC_DMY_FORCE is enabled, the QSPIC_DMY_NUM is overruled. In this case the number of dummy bytes is defined by the QSPIC_DMY_FORCE and is equal to 3, independent of the value of the QSPIC_DMY_NUM. 4 6 read-write QSPIC_EXT_BYTE_EN Extra Byte Enable 0 - Don't Send QSPIC_EXT_BYTE 1 - Send QSPIC_EXT_BYTE 2 3 read-write QSPIC_EXT_HF_DS Extra Half Disable Output 0 - if QSPIC_EXT_BYTE_EN=1, is transmitted the complete QSPIC_EXT_BYTE 1 - if QSPIC_EXT_BYTE_EN=1, the output is disabled (hi-z) during the transmission of bits [3:0] of QSPIC_EXT_BYTE 3 4 read-write QSPIC_INST_MD Instruction mode 0 - Transmit instruction at any burst access. 1 - Transmit instruction only in the first access after the selection of Auto Mode. 6 7 read-write QSPIC_WRAP_LEN It describes the selected length of a wrapping burst (QSPIC_WRAP_MD). 00 - 4 beat wrapping burst 01 - 8 beat wrapping burst 10 - 16 beat wrapping burst 11 - Reserved 8 10 read-write QSPIC_WRAP_MD Wrap mode 0 - The QSPIC_INST is the selected instruction at any access. 1 - The QSPIC_INST_WB is the selected instruction at any wrapping burst access of length and size described by the registers QSPIC_WRAP_LEN and QSPIC_WRAP_SIZE respectively. In all other cases the QSPIC_INST is the selected instruction. Use this feature only when the serial FLASH memory supports a special instruction for wrapping burst access. 7 8 read-write QSPIC_WRAP_SIZE It describes the selected data size of a wrapping burst (QSPIC_WRAP_MD). 00 - byte access (8-bits) 01 - half word access (16 bits) 10 - word access (32-bits) 11 - Reserved 10 12 read-write CHCKERASE_REG Check erase progress in Auto mode 0x38 32 read-write n 0x0 0x0 QSPIC_CHCKERASE Writing any value to this register during erasing, forces the controller to read the flash memory status register. Depending on the value of the Busy bit, it updates the QSPIC_ERASE_EN. 0 32 write-only CTRLBUS_REG SPI Bus control register for the Manual mode 0x0 32 read-write n 0x0 0x0 QSPIC_DIS_CS Write 1 to disable the chip select (active low) when the controller is in Manual mode. 4 5 write-only QSPIC_EN_CS Write 1 to enable the chip select (active low) when the controller is in Manual mode. 3 4 write-only QSPIC_SET_DUAL Write 1 to set the bus mode in Dual mode when the controller is in Manual mode. 1 2 write-only QSPIC_SET_QUAD Write 1 to set the bus mode in Quad mode when the controller is in Manual mode. 2 3 write-only QSPIC_SET_SINGLE Write 1 to set the bus mode in Single SPI mode when the controller is in Manual mode. 0 1 write-only CTRLMODE_REG Mode Control register 0x4 32 read-write n 0x0 0x0 QSPIC_AUTO_MD Mode of operation 0: The Manual Mode is selected. 1: The Auto Mode is selected. During an erasing the QSPIC_AUTO_MD goes in read only mode (see QSPIC_ERASE_EN) 0 1 read-write QSPIC_CLK_MD Mode of the generated QSPI_SCK clock 0: Use Mode 0 for the QSPI_CLK. The QSPI_SCK is low when QSPI_CS is high. 1: Use Mode 3 for the QSPI_CLK. The QSPI_SCK is high when QSPI_CS is high. 1 2 read-write QSPIC_FORCENSEQ_EN Controls the way with which is addressed by the QSPI controller a burst request from the AMBA bus. 0: The controller translates a burst access on the AMBA bus as a burst access on the QSPI bus. That results to the minimum number of command/address phases. 1: The controller will split a burst access on the AMBA bus into a number of single accesses on the QSPI bus. That results to a separate command for each beat of the burst. E.g a 4-beat word incremental AMBA read access will be split into 4 different sequences on the QSPI bus: command/address/extra clock/read data. The QSPI_CS will be low only for the time that is needed for each of these single accesses. This configuration bit is usefull when the clock frequency of the QSPI bus is much higher than the clock of the AMBA bus. In this case the interval for which the CS remains low is minimized, achieving lower power dissipation with respect of the case where the QSPIC_FORCENSEQ_EN=0, at cost of performance. 12 13 read-write QSPIC_HRDY_MD This configuration bit is useful when the frequency of the QSPI clock is much lower than the clock of the AMBA bus, in order to not locks the AMBA bus for a long time. 0: Adds wait states via hready signal when an access is performed on the QSPIC_WRITEDATA, QSPIC_READDATA and QSPIC_DUMMYDATA registers. It is not needed to checked the QSPIC_BUSY of the QSPIC_STATUS_REG. 1: The controller don't adds wait states via the hready signal, when is performed access on the QSPIC_WRITEDATA, QSPIC_READDATA and QSPIC_DUMMYDATA registers. The QSPIC_BUSY bit of the QSPIC_STATUS_REG must be checked in order to be detected the completion of the requested access. It is applicable only when the controller is in Manual mode. In the case of the Auto mode, the controller always adds wait states via the hready signal. 6 7 read-write QSPIC_IO2_DAT The value of QSPI_IO2 pad if QSPI_IO2_OEN is 1 4 5 read-write QSPIC_IO2_OEN QSPI_IO2 output enable. Use this only in SPI or Dual SPI mode to control /WP signal. When the Auto Mode is selected (QSPIC_AUTO_MD = 1) and the QUAD SPI is used, set this bit to zero. 0: The QSPI_IO2 pad is input. 1: The QSPI_IO2 pad is output. 2 3 read-write QSPIC_IO3_DAT The value of QSPI_IO3 pad if QSPI_IO3_OEN is 1 5 6 read-write QSPIC_IO3_OEN QSPI_IO3 output enable. Use this only in SPI or Dual SPI mode to control /HOLD signal. When the Auto Mode is selected (QSPIC_AUTO_MD = 1) and the QUAD SPI is used, set this bit to zero. 0: The QSPI_IO3 pad is input. 1: The QSPI_IO3 pad is output. 3 4 read-write QSPIC_PCLK_MD Read pipe clock delay relative to the falling edge of QSPI_SCK. Refer to QSPI Timing for timing parameters and recommended values: 0 to 7 9 12 read-write QSPIC_RPIPE_EN Controls the use of the data read pipe. 0 = The read pipe is disabled the sampling clock is defined according to the QSPIC_RXD_NEG setting. 1 = The read pipe is enabled. The delay of the sampling clock is defined according to the QSPI_PCLK_MD setting. (Recommended) 8 9 read-write QSPIC_RXD_NEG Defines the clock edge that is used for the capturing of the received data, when the read pipe is not active (QSPIC_RPIPE_EN = 0). 0: Sampling of the received data with the positive edge of the QSPI_SCK 1: Sampling of the received data with the negative edge of the QSPI_SCK The internal QSPI_SCK clock that is used by the controller for the capturing of the received data has a skew in respect of the QSPI_SCK that is received by the external memory device. In order to be improved the timing requirements of the read path, the controller supports a read pipe register with programmable clock delay. See also the QSPIC_RPIPE_EN register. 7 8 read-write QSPIC_USE_32BA Controls the length of the address that the external memory device uses. 0 - The external memory device uses 24 bits address. 1 - The external memory device uses 32 bits address. The controller uses this bit in order to decide the number of the address bytes that has to transfer to the external device during Auto mode. 13 14 read-write DUMMYDATA_REG Send dummy clocks to SPI Bus for the Manual mode 0x20 32 read-write n 0x0 0x0 QSPIC_DUMMYDATA Writing to this register generates a number of clock pulses to the SPI bus. During the last clock of this activity in the SPI bus, the QSPI_IOx data pads are in hi-z state. The data size of the access to this register can be 32-bits / 16-bits/ 8-bits. The number of generated pulses is equal to: (size of AHB bus access) / (size of SPI bus). The size of SPI bus is equal to 1, 2 or 4 for Single, Dual or Quad SPI mode respectively. This register has meaning only when the controller is in Manual mode. 0 32 write-only ERASECMDA_REG The way of erasing in Auto mode (command register A) 0x28 32 read-write n 0x0 0x0 QSPIC_ERS_INST The code value of the erase instruction. 0 8 read-write QSPIC_RES_INST The code value of the erase resume instruction 24 32 read-write QSPIC_SUS_INST The code value of the erase suspend instruction. 16 24 read-write QSPIC_WEN_INST The code value of the write enable instruction 8 16 read-write ERASECMDB_REG The way of erasing in Auto mode (command register B) 0x2C 32 read-write n 0x0 0x0 QSPIC_EAD_TX_MD The mode of the QSPI Bus during the address phase of the erase instruction 00 - Single 01 - Dual 10 - Quad 11 - Reserved 8 10 read-write QSPIC_ERSRES_HLD The controller must stay without flash memory reading requests for this number of AMBA hclk clock cycles, before to perform the command of erase or erase resume 15 - 0 16 20 read-write QSPIC_ERS_CS_HI After the execution of instructions: write enable, erase, erase suspend and erase resume, the QSPI_CS remains high for at least this number of qspi bus clock cycles. 10 15 read-write QSPIC_ERS_TX_MD The mode of the QSPI Bus during the instruction phase of the erase instruction 00 - Single 01 - Dual 10 - Quad 11 - Reserved 0 2 read-write QSPIC_RESSUS_DLY Defines a timer that counts the minimum allowed delay between an erase suspend command and the previous erase resume command (or the initial erase command). 0 = Dont wait. The controller starts immediately to suspend the erase procedure. 1..63 = The controller waits for at least this number of 222kHz clock cycles before the suspension of erasing. Time starts counting after the end of the previous erase resume command (or the initial erase command) 24 30 read-write QSPIC_RES_TX_MD The mode of the QSPI Bus during the transmission of the resume instruction 00 - Single 01 - Dual 10 - Quad 11 - Reserved 6 8 read-write QSPIC_SUS_TX_MD The mode of the QSPI Bus during the transmission of the suspend instruction. 00 - Single 01 - Dual 10 - Quad 11 - Reserved 4 6 read-write QSPIC_WEN_TX_MD The mode of the QSPI Bus during the transmission of the write enable instruction. 00 - Single 01 - Dual 10 - Quad 11 - Reserved 2 4 read-write ERASECTRL_REG QSPI Erase control register 0x24 32 read-write n 0x0 0x0 QSPIC_ERASE_EN During Manual mode (QSPIC_AUTO_MD = 0). This bit is in read only mode. During Auto mode (QSPIC_AUTO_MD = 1). To request the erasing of the block/sector (QSPIC_ERS_ADDR, 12'b0) write 1 to this bit. This bit is cleared automatically with the end of the erasing. Until the end of erasing the QSPIC_ERASE_EN remains in read only mode. During the same period of time the controller remains in Auto Mode (QSPIC_AUTO_MD goes in read only mode). 24 25 read-write QSPIC_ERS_ADDR Defines the address of the block/sector that is requested to be erased. If QSPIC_USE_32BA = 0 (24 bits addressing), bits QSPIC_ERASECTRL_REG[23-12] determine the block/ sector address bits [23-12]. QSPIC_ERASECTRL_REG[11-4] are ignored by the controller. If QSPIC_USE_32BA = 1 (32 bits addressing) bits QSPIC_ERASECTRL_REG[23-4] determine the block / sectors address bits [31:12] 4 24 read-write QSPIC_ERS_STATE It shows the progress of sector/block erasing (read only). 000 = No Erase. 001 = Pending erase request 010 = Erase procedure is running 011 = Suspended Erase procedure 100 = Finishing the Erase procedure 101..111 = Reserved 25 28 read-only GP_REG QSPI General Purpose control register 0x3C 32 read-write n 0x0 0x0 QSPIC_PADS_DRV QSPI pads drive current 0: 4 mA 1: 8 mA 2: 12 mA 3: 16 mA 1 3 read-write QSPIC_PADS_SLEW QSPI pads slew rate control. Indicative values under certain conditions: 0: Rise=1.7 V/ns, Fall=1.9 V/ns (weak) 1: Rise=2.0 V/ns, Fall=2.3 V/ns 2: Rise=2.3 V/ns, Fall=2.6 V/ns 3: Rise=2.4 V/ns, Fall=2.7 V/ns (strong) Conditions: FLASH pin capacitance 6 pF, Vcc=1.8V, T=25C and Idrive=16mA. 3 5 read-write READDATA_REG Read data from SPI Bus for the Manual mode 0x1C 32 read-write n 0x0 0x0 QSPIC_READDATA A read access at this register generates a data transfer from the external memory device to the QSPIC controller. The data is transferred using the selected mode of the SPI bus (SPI, Dual SPI, Quad SPI). The data size of the access to this register can be 32-bits / 16-bits / 8-bits and is equal to the number of the transferred bits. This register has meaning only when the controller is in Manual mode. 0 32 read-only RECVDATA_REG Received data for the Manual mode 0x8 32 read-write n 0x0 0x0 QSPIC_RECVDATA This register contains the received data when the QSPIC_READDATA_REG register is used in Manual mode, in order to be retrieved data from the external memory device and QSPIC_HRDY_MD=1 and and QSPIC_BUSY=0. 0 32 read-only STATUSCMD_REG The way of reading the status of external device in Auto mode 0x34 32 read-write n 0x0 0x0 QSPIC_BUSY_POS It describes who from the bits of status represents the Busy bit (7 - 0). 12 15 read-write QSPIC_BUSY_VAL Defines the value of the Busy bit which means that the flash is busy. 0 - The flash is busy when the Busy bit is equal to 0. 1 - The flash is busy when the Busy bit is equal to 1. 15 16 read-write QSPIC_RESSTS_DLY Defines a timer that counts the minimum required delay between the reading of the status register and of the previous erase or erase resume instruction. 0 - Dont wait. The controller starts to reading the Flash memory status register immediately. 1..63 - The controller waits for at least this number of QSPI_CLK cycles and afterwards it starts to reading the Flash memory status register. The timer starts to count after the end of the previous erase or erase resume command. The actual timer that will be used by the controller before the reading of the Flash memory status register is defined by the QSPIC_STSDLY_SEL. 16 22 read-write QSPIC_RSTAT_INST The code value of the read status instruction. It is transmitted during the instruction phase of the read status instruction. 0 8 read-write QSPIC_RSTAT_RX_MD The mode of the QSPI Bus during the receive status phase of the read status instruction 00 - Single 01 - Dual 10 - Quad 11 - Reserved 10 12 read-write QSPIC_RSTAT_TX_MD The mode of the QSPI Bus during the instruction phase of the read status instruction. 00 - Single 01 - Dual 10 - Quad 11 - Reserved 8 10 read-write QSPIC_STSDLY_SEL Defines the timer which is used to count the delay that it has to wait before to read the FLASH Status Register, after an erase or an erase resume command. 0 - The delay is controlled by the QSPIC_RESSTS_DLY which counts on the qspi clock. 1 - The delay is controlled by the QSPIC_RESSUS_DLY which counts on the 222 kHz clock. 22 23 read-write STATUS_REG The status register of the QSPI controller 0x14 32 read-write n 0x0 0x0 QSPIC_BUSY The status of the SPI Bus. 0 - The SPI Bus is idle 1 - The SPI Bus is active. Read data, write data or dummy data activity is in progress. Has meaning only in Manual mode and only when QSPIC_HRDY_MD = 1. 0 1 read-write UCODE_START QSPIC uCode memory 0x40 32 read-write n 0x0 0x0 QSPIC_UCODE_X The first position of the memory (16 words x 32 bits) where a microcode should be placed ( X = 0 to 15). This microcode describes the initialization process of the external flash device. 0 32 read-write WRITEDATA_REG Write data to SPI Bus for the Manual mode 0x18 32 read-write n 0x0 0x0 QSPIC_WRITEDATA Writing to this register is generating a data transfer from the controller to the external memory device. The data written in this register is then transferred to the memory using the selected mode of the SPI bus (SPI, Dual SPI, Quad SPI). The data size of the access to this register can be 32-bits / 16-bits/ 8-bits and is equal to the number of the transferred bits. This register has meaning only when the controller is in Manual mode. 0 32 write-only QUAD QUAD registers Peripheral_Registers 0x0 0x0 0xA registers n QDEC_CLOCKDIV_REG Quad decoder clock divider register 0x8 16 read-write n 0x0 0x0 clock_divider Contains the number of the input clock cycles minus one, that are required to generate one logic clock cycle. 0 10 read-write QDEC_CTRL_REG Quad decoder control register 0x0 16 read-write n 0x0 0x0 CHX_PORT_EN '1' : Enable channel 10 11 read-write CHY_PORT_EN '1' : Enable channel 11 12 read-write CHZ_PORT_EN '1' : Enable channel 12 13 read-write QD_IRQ_CLR Writing 1 to this bit clears the interrupt. This bit is autocleared 1 2 read-write QD_IRQ_MASK 0: interrupt is masked 1: interrupt is enabled 0 1 read-write QD_IRQ_STATUS Interrupt Status. If 1 an interrupt has occured. 2 3 read-only QD_IRQ_THRES The number of events on either counter (X or Y or Z) that need to be reached before an interrupt is generated. If 0 is written, then threshold is considered to be 1. 3 10 read-write QDEC_XCNT_REG Counter value of the X Axis 0x2 16 read-write n 0x0 0x0 X_counter Contains a signed value of the events. Zero when channel is disabled 0 16 read-only QDEC_YCNT_REG Counter value of the Y Axis 0x4 16 read-write n 0x0 0x0 Y_counter Contains a signed value of the events. Zero when channel is disabled 0 16 read-only QDEC_ZCNT_REG Counter value of the Z Axis 0x6 16 read-write n 0x0 0x0 Z_counter Contains a signed value of the events. Zero when channel is disabled 0 16 read-only SCB Cortex M0 SCB registers SCB 0x0 0x0 0x29 registers n AIRCR Application interrupt and reset control register 0xC 32 read-only n 0x0 0x0 ENDIANESS Data endianness bit 15 16 read-only SYSRESETREQ System reset request 2 3 read-only VECTCLRACTIVE Reserved for Debug use 1 2 read-only VECTKEY VECTKEY[15:0] bits (Register key) 16 32 read-only VECTRESET Reserved for Debug use 0 1 read-only CCR Configuration and control register 0x14 32 read-write n 0x0 0x0 STKALIGN Configures stack alignment on exception entry 9 10 read-write UNALIGN_TRP Enables unaligned access traps 3 4 read-write CPUID CPUID base register 0x0 32 read-write n 0x0 0x0 CONSTANT CONSTANT[3:0] bits (Reads as 0xF) 16 20 read-only IMPLEMENTER IMPLEMENTER[7:0] bits (Implementer code) 24 32 read-only PARTNO PARTNO[11:0] bits (Part number of the processor core) 4 16 read-only REVISION REVISION[3:0] bits (Revision number) 0 4 read-only VARIANT VARIANT[3:0] bits (Variant number) 20 24 read-only ICSR Interrupt control and state register 0x4 32 read-write n 0x0 0x0 ISRPENDING Interrupt pending flag, excluding NMI and Faults 22 23 read-write NMIPENDSET NMI set-pending bit 31 32 read-write PENDSTCLR SysTick exception clear-pending bit 25 26 read-write PENDSTSET SysTick exception set-pending bit 26 27 read-write PENDSVCLR PendSV clear-pending bit 27 28 read-write PENDSVSET PendSV set-pending bit 28 29 read-write VECTACTIVE VECTACTIVE[5:0] bits (Active vector) 0 6 read-write VECTPENDING VECTPENDING[5:0] bits (Pending vector) 12 18 read-write SCR System control register 0x10 32 read-write n 0x0 0x0 SEVEONPEND Send event on pending bit 4 5 read-write SLEEPDEEP Controls whether the processor uses sleep or deep sleep 2 3 read-write SLEEPONEXIT Configures sleep-on-exit when returning from Handler mode to Thread mode 1 2 read-write SHPR2 System handler priority register 2 0x1C 32 read-write n 0x0 0x0 PRI_11 PRI_11[7:0] bits (Priority of system handler 11, SVCall) 24 32 read-write SHPR3 System handler priority register 3 0x20 32 read-write n 0x0 0x0 PRI_14 PRI_14[7:0] bits (Priority of system handler 14, PendSV) 16 24 read-write PRI_15 PRI_15[7:0] bits (Priority of system handler 15, SysTick exception) 24 32 read-write SPI SPI registers Peripheral_Registers 0x0 0x0 0xA registers n CLEAR_INT_REG SPI clear interrupt register 0x6 16 read-write n 0x0 0x0 SPI_CLEAR_INT Writing any value to this register will clear the SPI_CTRL_REG[SPI_INT_BIT] Reading returns 0. 0 16 write-only CTRL_REG SPI control register 0 0x0 16 read-write n 0x0 0x0 SPI_CLK Select SPI_CLK clock output frequency in master mode: 00 = SPI_CLK / 8 01 = SPI_CLK / 4 10 = SPI_CLK / 2 11 = SPI_CLK / 14 3 5 read-write SPI_DI Returns the actual value of pin SPI_DIN (delayed with two internal SPI clock cycles) 12 13 read-only SPI_DO Pin SPI_DO output level when SPI is idle or when SPI_FORCE_DO=1 5 6 read-write SPI_EN_CTRL 0 = SPI_EN pin disabled in slave mode. Pin SPI_EN is don't care. 1 = SPI_EN pin enabled in slave mode. 15 16 read-write SPI_FORCE_DO 0 = normal operation 1 = Force SPIDO output level to value of SPI_DO. 10 11 read-write SPI_INT_BIT 0 = RX Register or FIFO is empty. 1 = SPI interrupt. Data has been transmitted and receivedMust be reset by SW by writing to SPI_CLEAR_INT_REG. 13 14 read-only SPI_MINT 0 = Disable SPI_INT_BIT to ICU 1 = Enable SPI_INT_BIT to ICU. Note that the SPI_INT interrupt is shared with AD_INT interrupt 14 15 read-write SPI_ON 0 = SPI Module switched off (power saving). Everything is reset except SPI_CTRL_REG0 and SPI_CTRL_REG1. When this bit is cleared the SPI will remain active in master mode until the shift register and holding register are both empty. 1 = SPI Module switched on. Should only be set after all control bits have their desired values. So two writes are needed! 0 1 read-write SPI_PHA Select SPI_CLK phase. See functional timing diagrams in SPI chapter 1 2 read-write SPI_POL Select SPI_CLK polarity. 0 = SPI_CLK is initially low. 1 = SPI_CLK is initially high. 2 3 read-write SPI_RST 0 = normal operation 1 = Reset SPI. Same function as SPI_ON except that internal clock remain active. 9 10 read-write SPI_SMN Master/slave mode 0 = Master, 1 = Slave(SPI1 only) 6 7 read-write SPI_TXH 0 = TX-FIFO is not full, data can be written. 1 = TX-FIFO is full, data can not be written. 11 12 read-only SPI_WORD 00 = 8 bits mode, only SPI_RX_TX_REG0 used 01 = 16 bit mode, only SPI_RX_TX_REG0 used 10 = 32 bits mode, SPI_RX_TX_REG0 and SPI_RX_TX_REG1 used 11 = 9 bits mode. Only valid in master mode. 7 9 read-write CTRL_REG1 SPI control register 1 0x8 16 read-write n 0x0 0x0 SPI_9BIT_VAL Determines the value of the first bit in 9 bits SPI mode. 4 5 read-write SPI_BUSY 0 = The SPI is not busy with a transfer. This means that either no TX-data is available or that the transfers have been suspended due to a full RX-FIFO. The SPIx_CTRL_REG0[SPI_INT_BIT] can be used to distinguish between these situations. 1 = The SPI is busy with a transfer. 3 4 read-only SPI_FIFO_MODE 0: TX-FIFO and RX-FIFO used (Bidirectional mode). 1: RX-FIFO used (Read Only Mode) TX-FIFO single depth, no flow control 2: TX-FIFO used (Write Only Mode), RX-FIFO single depth, no flow control 3: No FIFOs used (backwards compatible mode) 0 2 read-write SPI_PRIORITY 0 = The SPI has low priority, the DMA request signals are reset after the corresponding acknowledge. 1 = The SPI has high priority, DMA request signals remain active until the FIFOS are filled/emptied, so the DMA holds the AHB bus. 2 3 read-write RX_TX_REG0 SPI RX/TX register0 0x2 16 read-write n 0x0 0x0 SPI_DATA0 Write: SPI_TX_REG0 output register 0 (TX-FIFO) Read: SPI_RX_REG0 input register 0 (RX-FIFO) In 8 or 9 bits mode bits 15 to 8 are not used, they contain old data. 0 16 write-only RX_TX_REG1 SPI RX/TX register1 0x4 16 read-write n 0x0 0x0 SPI_DATA1 Write: SPI_TX_REG1 output register 1 (MSB's of TX-FIFO) Read: SPI_RX_REG1 input register 1 (MSB's of RX-FIFO) In 8 or 9 or 16 bits mode bits this register is not used. 0 16 write-only SPI2 SPI2 registers Peripheral_Registers 0x0 0x0 0xA registers n CLEAR_INT_REG SPI clear interrupt register 0x6 16 read-write n 0x0 0x0 SPI_CLEAR_INT Writing any value to this register will clear the SPI_CTRL_REG[SPI_INT_BIT] Reading returns 0. 0 16 write-only CTRL_REG SPI control register 0 0x0 16 read-write n 0x0 0x0 SPI_CLK Select SPI_CLK clock output frequency in master mode: 00 = SPI_CLK / 8 01 = SPI_CLK / 4 10 = SPI_CLK / 2 11 = SPI_CLK / 14 3 5 read-write SPI_DI Returns the actual value of pin SPI_DIN (delayed with two internal SPI clock cycles) 12 13 read-only SPI_DO Pin SPI_DO output level when SPI is idle or when SPI_FORCE_DO=1 5 6 read-write SPI_EN_CTRL 0 = SPI_EN pin disabled in slave mode. Pin SPI_EN is don't care. 1 = SPI_EN pin enabled in slave mode. 15 16 read-write SPI_FORCE_DO 0 = normal operation 1 = Force SPIDO output level to value of SPI_DO. 10 11 read-write SPI_INT_BIT 0 = RX Register or FIFO is empty. 1 = SPI interrupt. Data has been transmitted and receivedMust be reset by SW by writing to SPI_CLEAR_INT_REG. 13 14 read-only SPI_MINT 0 = Disable SPI_INT_BIT to ICU 1 = Enable SPI_INT_BIT to ICU. Note that the SPI_INT interrupt is shared with AD_INT interrupt 14 15 read-write SPI_ON 0 = SPI Module switched off (power saving). Everything is reset except SPI_CTRL_REG0 and SPI_CTRL_REG1. When this bit is cleared the SPI will remain active in master mode until the shift register and holding register are both empty. 1 = SPI Module switched on. Should only be set after all control bits have their desired values. So two writes are needed! 0 1 read-write SPI_PHA Select SPI_CLK phase. See functional timing diagrams in SPI chapter 1 2 read-write SPI_POL Select SPI_CLK polarity. 0 = SPI_CLK is initially low. 1 = SPI_CLK is initially high. 2 3 read-write SPI_RST 0 = normal operation 1 = Reset SPI. Same function as SPI_ON except that internal clock remain active. 9 10 read-write SPI_SMN Master/slave mode 0 = Master, 1 = Slave(SPI1 only) 6 7 read-write SPI_TXH 0 = TX-FIFO is not full, data can be written. 1 = TX-FIFO is full, data can not be written. 11 12 read-only SPI_WORD 00 = 8 bits mode, only SPI_RX_TX_REG0 used 01 = 16 bit mode, only SPI_RX_TX_REG0 used 10 = 32 bits mode, SPI_RX_TX_REG0 and SPI_RX_TX_REG1 used 11 = 9 bits mode. Only valid in master mode. 7 9 read-write CTRL_REG1 SPI control register 1 0x8 16 read-write n 0x0 0x0 SPI_9BIT_VAL Determines the value of the first bit in 9 bits SPI mode. 4 5 read-write SPI_BUSY 0 = The SPI is not busy with a transfer. This means that either no TX-data is available or that the transfers have been suspended due to a full RX-FIFO. The SPIx_CTRL_REG0[SPI_INT_BIT] can be used to distinguish between these situations. 1 = The SPI is busy with a transfer. 3 4 read-only SPI_FIFO_MODE 0: TX-FIFO and RX-FIFO used (Bidirectional mode). 1: RX-FIFO used (Read Only Mode) TX-FIFO single depth, no flow control 2: TX-FIFO used (Write Only Mode), RX-FIFO single depth, no flow control 3: No FIFOs used (backwards compatible mode) 0 2 read-write SPI_PRIORITY 0 = The SPI has low priority, the DMA request signals are reset after the corresponding acknowledge. 1 = The SPI has high priority, DMA request signals remain active until the FIFOS are filled/emptied, so the DMA holds the AHB bus. 2 3 read-write RX_TX_REG0 SPI RX/TX register0 0x2 16 read-write n 0x0 0x0 SPI_DATA0 Write: SPI_TX_REG0 output register 0 (TX-FIFO) Read: SPI_RX_REG0 input register 0 (RX-FIFO) In 8 or 9 bits mode bits 15 to 8 are not used, they contain old data. 0 16 write-only RX_TX_REG1 SPI RX/TX register1 0x4 16 read-write n 0x0 0x0 SPI_DATA1 Write: SPI_TX_REG1 output register 1 (MSB's of TX-FIFO) Read: SPI_RX_REG1 input register 1 (MSB's of RX-FIFO) In 8 or 9 or 16 bits mode bits this register is not used. 0 16 write-only SysTick Cortex M0 SysTick registers SYSTICK 0x0 0x0 0x11 registers n CALIB SysTick Calibration value register 0xC 32 read-only n 0x0 0x0 NOREF Indicates that a separate reference clock is provided 31 32 read-only SKEW Indicates whether the TENMS value is exact 30 31 read-only TENMS TENMS[23:0] bits (Calibration value) 0 24 read-only CTRL SysTick Control and Status register 0x0 32 read-write n 0x0 0x0 CLKSOURCE Clock source selection 2 3 read-write COUNTFLAG Timer counted to 0 since last time this was read 16 17 read-write ENABLE SysTick Counter enable 0 1 read-write TICKINT SysTick exception request enable 1 2 read-write LOAD SysTick Reload value register 0x4 32 read-write n 0x0 0x0 RELOAD RELOAD[23:0] bits (Reload value) 0 24 read-write VAL SysTick Current value register 0x8 32 read-write n 0x0 0x0 CURRENT CURRENT[23:0] bits (Current counter value) 0 24 read-write TIMER1 TIMER1 registers Peripheral_Registers 0x0 0x0 0x1A registers n CAPTIM_CAPTURE_GPIO1_REG Capture Timer value for event on GPIO1 0x10 16 read-write n 0x0 0x0 CAPTIM_CAPTURE_GPIO1 Gives the Capture time for event on GPIO1 0 16 read-only CAPTIM_CAPTURE_GPIO2_REG Capture Timer value for event on GPIO2 0x12 16 read-write n 0x0 0x0 CAPTIM_CAPTURE_GPIO2 Gives the Capture time for event on GPIO2 0 16 read-only CAPTIM_CTRL_REG Capture Timer control register 0x0 16 read-write n 0x0 0x0 CAPTIM_COUNT_DOWN_EN '1' when timer counts down, '0' count up 2 3 read-write CAPTIM_EN '1' Capture Timer enabled, else disabled 0 1 read-write CAPTIM_FREE_RUN_MODE_EN Only when timer counts up, if it is '1' timer does not zero when reaches to reload value. it is zero only when it has the max value. 6 7 read-write CAPTIM_IN1_EVENT_FALL_EN '1' When Input2 event type is falling edge, '0' rising edge 3 4 read-write CAPTIM_IN2_EVENT_FALL_EN '1' When Input1 event type is falling edge, '0' rising edge 4 5 read-write CAPTIM_IRQ_EN '1' When Capture timer IRQ unmask, '0' masked 5 6 read-write CAPTIM_ONESHOT_MODE_EN '1' Capture Timer in OneShot mode, '0' Capture/Timer mode 1 2 read-write CAPTIM_SYS_CLK_EN '1' When Capture Timer use the system clock else use the clock 32KHz 7 8 read-write CAPTIM_GPIO1_CONF_REG Capture Timer gpio1 selection 0x6 16 read-write n 0x0 0x0 CAPTIM_GPIO1_CONF Select one of the 37 GPIOs as IN1, Valid value 0-37. 1 for P00 .. 37 for P47. When 0 Disable input 0 6 read-write CAPTIM_GPIO2_CONF_REG Capture Timer gpio2 selection 0x8 16 read-write n 0x0 0x0 CAPTIM_GPIO2_CONF Select one of the 37 GPIOs as IN2, Valid value 0-37. 1 for P00 .. 37 for P47. When 0 Disable input 0 6 read-write CAPTIM_PRESCALER_REG Capture Timer prescaler value 0xE 16 read-write n 0x0 0x0 CAPTIM_PRESCALER Define the timer count frequncy. Freq = Freq_clock / (value+1) 0 16 read-write CAPTIM_PRESCALER_VAL_REG Capture Timer interrupt status register 0x14 16 read-write n 0x0 0x0 CAPTIM_PRESCALER_VAL Gives the current prescaler value 0 16 read-only CAPTIM_PWM_DC_REG Capture Timer pwm dc register 0x18 16 read-write n 0x0 0x0 CAPTIM_PWM_DC Define the PWM duty cyucle = pwm_dc / ( pwm_freq+1) 0 16 read-write CAPTIM_PWM_FREQ_REG Capture Timer pwm frequency register. PWM5 period is defined by the reference clock frequency multiplied by this value. 0x16 16 read-write n 0x0 0x0 CAPTIM_PWM_FREQ Define the PWM frequency. = prescaler frequency / (value+1) 0 16 read-write CAPTIM_RELOAD_REG Capture Timer reload value and Delay in shot mode 0xA 16 read-write n 0x0 0x0 CAPTIM_RELOAD Reload or max value in timer mode, Delay phase duration in oneshot mode. Actual delay is the register value plus synchronization time (3 clock cycles) 0 16 read-write CAPTIM_SHOTWIDTH_REG Capture Timer Shot duration in shot mode 0xC 16 read-write n 0x0 0x0 CAPTIM_SHOTWIDTH Shot phase duration in oneshot mode 0 16 read-write CAPTIM_STATUS_REG Capture Timer status register 0x4 16 read-write n 0x0 0x0 CAPTIM_IN1_STATE Gives the logic level of the IN2 0 1 read-only CAPTIM_IN2_STATE Gives the logic level of the IN1 1 2 read-only CAPTIM_ONESHOT_PHASE 0 : Wait for event, 1 : Delay phase, 2 : Start Shot, 3 : Shot phase 2 4 read-only CAPTIM_TIMER_VAL_REG Capture Timer counter value 0x2 16 read-write n 0x0 0x0 CAPTIM_TIMER_VALUE Gives the current timer value 0 16 read-only TRNG TRNG registers Peripheral_Registers 0x0 0x0 0xC registers n CTRL_REG TRNG control register 0x0 32 read-write n 0x0 0x0 TRNG_ENABLE 0: Disable the TRNG 1: Enable the TRNG this signal is ignored when the FIFO is full 0 1 read-write TRNG_MODE 0: select the TRNG with asynchronous free running oscillators (default) 1: select the pseudo-random generator with synchronous oscillators (for simulation purpose only) 1 2 read-write FIFOLVL_REG TRNG FIFO level register 0x4 32 read-write n 0x0 0x0 TRNG_FIFOFULL 1:FIFO full indication. This bit is cleared if the FIFO is read. 5 6 read-only TRNG_FIFOLVL Number of 32 bit words of random data in the FIFO (max 31) until the FIFO is full. When it is 0 and TRNG_FIFOFULL is 1, it means the FIFO is full. 0 5 read-only VER_REG TRNG Version register 0x8 32 read-write n 0x0 0x0 TRNG_MAJ Major version number 24 32 read-only TRNG_MIN Minor version number 16 24 read-only TRNG_SVN SVN revision number 0 16 read-only UART UART registers Peripheral_Registers 0x0 0x0 0x100 registers n CPR_REG Component Parameter Register 0xF4 16 read-write n 0x0 0x0 CPR Component Parameter Register 0 16 read-only CTR_REG Component Type Register 0xFC 32 read-write n 0x0 0x0 CTR Component Type Register 0 32 read-only DLF_REG Divisor Latch Fraction Register 0xC0 16 read-write n 0x0 0x0 UART_DLF The fractional value is added to integer value set by DLH, DLL. Fractional value is determined by (Divisor Fraction value)/(2^DLF_SIZE). 0 4 read-write DMASA_REG DMA Software Acknowledge 0xA8 16 read-write n 0x0 0x0 DMASA This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This will cause the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. 0 1 write-only IER_DLH_REG Interrupt Enable Register/Divisor Latch High 0x4 16 read-write n 0x0 0x0 dlh6_4 Divisor Latch (High): DLH6 to DLH4, Bits 6 to 4 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set, otherwise, this field is reserved. See register UART_RBR_THR_DLL_REG. 4 7 read-write EDSSI_dlh3 Interrupt Enable Register: EDSSI, Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH3, Bit 3 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 3 4 read-write ELSI_dhl2 Interrupt Enable Register: ELSI, Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH2, Bit 2 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 2 3 read-write ERBFI_dlh0 Interrupt Enable Register: ERBFI, Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFO's enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled Divisor Latch (High): DLH0, Bit 0 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 0 1 read-write ETBEI_dlh1 Interrupt Enable Register: ETBEI, Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH1, Bit 1 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 1 2 read-write PTIME_dlh7 Interrupt Enable Register: PTIME, Programmable THRE Interrupt Mode Enable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled. Divisor Latch (High): DLH7, Bit 7 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 7 8 read-write IIR_FCR_REG Interrupt Identification Register/FIFO Control Register 0x8 16 read-write n 0x0 0x0 IIR_FCR Interrupt Identification Register: Bits[7:6], returns 00. Bits[3:0], Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types: 0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. 0 16 read-only LCR_REG Line Control Register 0xC 16 read-write n 0x0 0x0 UART_BC Break Control Bit. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. 6 7 read-write UART_DLAB Divisor Latch Access Bit. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. 7 8 read-write UART_DLS Data Length Select. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits 0 2 read-write UART_EPS Even Parity Select. Writeable only when UART is not busy (USR[0] is zero). This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. 4 5 read-write UART_PEN Parity Enable. Writeable only when UART is not busy (USR[0] is zero). This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled 3 4 read-write UART_STOP Number of stop bits. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit 2 3 read-write LSR_REG Line Status Register 0x14 16 read-write n 0x0 0x0 UART_BI Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. Reading the LSR clears the BI bit. The BI indication occurs immediately and persists until the LSR is read. 4 5 read-only UART_DR Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read. 0 1 read-only UART_FE Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. 3 4 read-only UART_OE Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. The OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. 1 2 read-only UART_PE Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. 2 3 read-only UART_TEMT Transmitter Empty bit. This bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. 6 7 read-only UART_THRE Transmit Holding Register Empty bit. If THRE mode is disabled (IER[7] set to zero), this bit indicates that the THR. This bit is set whenever data is transferred from the THR to the transmitter shift register and no new data has been written to the THR. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. 5 6 read-only MCR_REG Modem Control Register 0x10 16 read-write n 0x0 0x0 UART_LB LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line. 4 5 read-write UART_OUT1 OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input. 2 3 read-write UART_OUT2 OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input. 3 4 read-write UART_SIRE SIR Mode Enable. This is used to enable/disable the IrDA SIR Mode features as described in IrDA 1.0 SIR Protocol . 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled 6 7 read-write RBR_THR_DLL_REG Receive Buffer Register/Transmit Holding Register/Divisor Latch Low 0x0 16 read-write n 0x0 0x0 RBR_THR_DLL Receive Buffer Register: (RBR). This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Transmit Holding Register: (THR) This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Divisor Latch (Low): (DLL) This register makes up the lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set. The output baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor) Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the Divisor Latch is set, at least 8 clock cycles of the slowest UART clock should be allowed to pass before transmitting or receiving data. For the Divisor Latch (High) bits, see register UART_IER_DLH_REG. 0 8 read-write SBCR_REG Shadow Break Control Register 0x90 16 read-write n 0x0 0x0 UART_SHADOW_BREAK_CONTROL Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. 0 1 read-write SCR_REG Scratchpad Register 0x1C 16 read-write n 0x0 0x0 UART_SCRATCH_PAD This register is for programmers to use as a temporary storage space. It has no defined purpose in the UART Ctrl. 0 8 read-write SRR_REG Software Reset Register. 0x88 16 read-write n 0x0 0x0 UART_UR UART Reset. This asynchronously resets the UART Ctrl and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. 0 1 write-only UCV_REG Component Version 0xF8 32 read-write n 0x0 0x0 UCV Component Version 0 32 read-only USR_REG UART Status register. 0x7C 16 read-write n 0x0 0x0 UART_BUSY UART Busy. This indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 - DW_apb_uart is idle or inactive 1 - DW_apb_uart is busy (actively transferring data) Note that it is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in the THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled) the assertion of this bit will also be delayed by several cycles of the slower clock. 0 1 read-only UART2 UART2 registers Peripheral_Registers 0x0 0x0 0x100 registers n CPR_REG Component Parameter Register 0xF4 16 read-write n 0x0 0x0 CPR Component Parameter Register 0 16 read-only CTR_REG Component Type Register 0xFC 32 read-write n 0x0 0x0 CTR Component Type Register 0 32 read-only DLF_REG Divisor Latch Fraction Register 0xC0 16 read-write n 0x0 0x0 UART_DLF The fractional value is added to integer value set by DLH, DLL. Fractional value is equal UART_DLF/16 0 4 read-write DMASA_REG DMA Software Acknowledge 0xA8 16 read-write n 0x0 0x0 DMASA This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This will cause the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. 0 1 write-only FAR_REG FIFO Access Register 0x70 16 read-write n 0x0 0x0 UART_FAR Description: Writes will have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFO's are implemented and enabled. When FIFO's are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFO's are treated as empty. 0 1 read-only HTX_REG Halt TX 0xA4 16 read-write n 0x0 0x0 UART_HALT_TX This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. 0 1 read-write IER_DLH_REG Interrupt Enable Register/Divisor Latch High 0x4 16 read-write n 0x0 0x0 dlh6_4 Divisor Latch (High): DLH6 to DLH4, Bits 6 to 4 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set, otherwise, this field is reserved. See register UART_RBR_THR_DLL_REG. 4 7 read-write EDSSI_dlh3 Interrupt Enable Register: EDSSI, Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH3, Bit 3 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 3 4 read-write ELSI_dhl2 Interrupt Enable Register: ELSI, Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH2, Bit 2 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 2 3 read-write ERBFI_dlh0 Interrupt Enable Register: ERBFI, Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFO's enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled Divisor Latch (High): DLH0, Bit 0 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 0 1 read-write ETBEI_dlh1 Interrupt Enable Register: ETBEI, Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled Divisor Latch (High): DLH1, Bit 1 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 1 2 read-write PTIME_dlh7 Interrupt Enable Register: PTIME, Programmable THRE Interrupt Mode Enable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled. Divisor Latch (High): DLH7, Bit 7 of the upper part of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. See register UART_RBR_THR_DLL_REG. 7 8 read-write IIR_FCR_REG Interrupt Identification Register/FIFO Control Register 0x8 16 read-write n 0x0 0x0 IIR_FCR Interrupt Identification Register, reading this register FIFO Control Register, writing to this register. Interrupt Identification Register: Bits[7:6], FIFO's Enabled (or FIFOSE): This is used to indicate whether the FIFO's are enabled or disabled. 00 = disabled. 11 = enabled. Bits[3:0], Interrupt ID (or IID): This indicates the highest priority pending interrupt which can be one of the following types:0001 = no interrupt pending. 0010 = THR empty. 0100 = received data available. 0110 = receiver line status. 0111 = busy detect. 1100 = character timeout. FIFO Control Register Bits[7:6], RCVR Trigger (or RT):. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted. It also determines when the dma_rx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO 1/4 full 10 = FIFO 1/2 full 11 = FIFO 2 less than full Bits[5:4], TX Empty Trigger (or TET): This is used to select the empty threshold level at which the THRE Interrupts will be generated when the mode is active. It also determines when the dma_tx_req_n signal will be asserted when in certain modes of operation. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO 1/4 full 11 = FIFO 1/2 full Bit[3], DMA Mode (or DMAM): This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 Bit[2], XMIT FIFO Reset (or XFIFOR): This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. Bit[1], RCVR FIFO Reset (or RFIFOR): This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing' and it is not necessary to clear this bit. Bit[0], FIFO Enable (or FIFOE): This enables/disables the transmit (XMIT) and receive (RCVR) FIFO's. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFO's will be reset. 0 16 read-write LCR_REG Line Control Register 0xC 16 read-write n 0x0 0x0 UART_BC Break Control Bit. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. 6 7 read-write UART_DLAB Divisor Latch Access Bit. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. 7 8 read-write UART_DLS Data Length Select. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits 0 2 read-write UART_EPS Even Parity Select. Writeable only when UART is not busy (USR[0] is zero). This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. 4 5 read-write UART_PEN Parity Enable. Writeable only when UART is not busy (USR[0] is zero) This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled 3 4 read-write UART_STOP Number of stop bits. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit 2 3 read-write LSR_REG Line Status Register 0x14 16 read-write n 0x0 0x0 UART_BI Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. 4 5 read-only UART_DR Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. 0 1 read-only UART_FE Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. 3 4 read-only UART_OE Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. 1 2 read-only UART_PE Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. 2 3 read-only UART_RFE Receiver FIFO Error bit. This bit is only relevant when FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. 7 8 read-only UART_TEMT Transmitter Empty bit. If FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. 6 7 read-only UART_THRE Transmit Holding Register Empty bit. If THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. 5 6 read-only MCR_REG Modem Control Register 0x10 16 read-write n 0x0 0x0 UART_AFCE Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in Auto Flow Control . 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled 5 6 read-write UART_LB LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line. 4 5 read-write UART_OUT1 OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input. 2 3 read-write UART_OUT2 OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input. 3 4 read-write UART_RTS Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input. 1 2 read-write UART_SIRE SIR Mode Enable. This is used to enable/disable the IrDA SIR Mode features as described in IrDA 1.0 SIR Protocol . 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled 6 7 read-write MSR_REG Modem Status Register 0x18 16 read-write n 0x0 0x0 UART_CTS Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the UART Ctrl. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS). 4 5 read-only UART_DCTS Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on cts_n since last read of MSR 1 = change on cts_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted. 0 1 read-only RBR_THR_DLL_REG Receive Buffer Register/Transmit Holding Register/Divisor Latch Low 0x0 16 read-write n 0x0 0x0 RBR_THR_DLL Receive Buffer Register: (RBR). This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Transmit Holding Register: (THR) This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. Divisor Latch (Low): (DLL) This register makes up the lower 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set. The output baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor) Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the Divisor Latch is set, at least 8 clock cycles of the slowest UART clock should be allowed to pass before transmitting or receiving data. For the Divisor Latch (High) bits, see register UART_IER_DLH_REG. 0 8 read-write RFL_REG Receive FIFO Level 0x84 16 read-write n 0x0 0x0 UART_RECEIVE_FIFO_LEVEL Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. 0 16 read-only SBCR_REG Shadow Break Control Register 0x90 16 read-write n 0x0 0x0 UART_SHADOW_BREAK_CONTROL Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. 0 1 read-write SCR_REG Scratchpad Register 0x1C 16 read-write n 0x0 0x0 UART_SCRATCH_PAD This register is for programmers to use as a temporary storage space. It has no defined purpose in the UART Ctrl. 0 8 read-write SDMAM_REG Shadow DMA Mode 0x94 16 read-write n 0x0 0x0 UART_SHADOW_DMA_MODE Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 0 1 read-write SFE_REG Shadow FIFO Enable 0x98 16 read-write n 0x0 0x0 UART_SHADOW_FIFO_ENABLE Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. 0 1 read-write SRBR_STHR0_REG Shadow Receive/Transmit Buffer Register 0x30 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR10_REG Shadow Receive/Transmit Buffer Register 0x58 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR11_REG Shadow Receive/Transmit Buffer Register 0x5C 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR12_REG Shadow Receive/Transmit Buffer Register 0x60 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR13_REG Shadow Receive/Transmit Buffer Register 0x64 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR14_REG Shadow Receive/Transmit Buffer Register 0x68 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR15_REG Shadow Receive/Transmit Buffer Register 0x6C 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR1_REG Shadow Receive/Transmit Buffer Register 0x34 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR2_REG Shadow Receive/Transmit Buffer Register 0x38 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR3_REG Shadow Receive/Transmit Buffer Register 0x3C 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR4_REG Shadow Receive/Transmit Buffer Register 0x40 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR5_REG Shadow Receive/Transmit Buffer Register 0x44 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR6_REG Shadow Receive/Transmit Buffer Register 0x48 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR7_REG Shadow Receive/Transmit Buffer Register 0x4C 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR8_REG Shadow Receive/Transmit Buffer Register 0x50 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRBR_STHR9_REG Shadow Receive/Transmit Buffer Register 0x54 16 read-write n 0x0 0x0 SRBR_STHRx Shadow Receive Buffer Register x: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Shadow Transmit Holding Register 0: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. 0 8 read-write SRR_REG Software Reset Register. 0x88 16 read-write n 0x0 0x0 UART_RFR RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. 1 2 write-only UART_UR UART Reset. This asynchronously resets the UART Ctrl and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. 0 1 write-only UART_XFR XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. 2 3 write-only SRTS_REG Shadow Request to Send 0x8C 16 read-write n 0x0 0x0 UART_SHADOW_REQUEST_TO_SEND Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART Ctrl is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] = 1) and FIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input. 0 1 read-write SRT_REG Shadow RCVR Trigger 0x9C 16 read-write n 0x0 0x0 UART_SHADOW_RCVR_TRIGGER Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full 0 2 read-write STET_REG Shadow TX Empty Trigger 0xA0 16 read-write n 0x0 0x0 UART_SHADOW_TX_EMPTY_TRIGGER Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full 0 2 read-write TFL_REG Transmit FIFO Level 0x80 16 read-write n 0x0 0x0 UART_TRANSMIT_FIFO_LEVEL Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. 0 16 read-only UCV_REG Component Version 0xF8 32 read-write n 0x0 0x0 UCV Component Version 0 32 read-only USR_REG UART Status Register 0x7C 16 read-write n 0x0 0x0 UART_BUSY UART Busy. This indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 - DW_apb_uart is idle or inactive 1 - DW_apb_uart is busy (actively transferring data) Note that it is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in the THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled) the assertion of this bit will also be delayed by several cycles of the slower clock. 0 1 read-only UART_RFF Receive FIFO Full. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. 4 5 read-only UART_RFNE Receive FIFO Not Empty. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. 3 4 read-only UART_TFE Transmit FIFO Empty. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. 2 3 read-only UART_TFNF Transmit FIFO Not Full. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. 1 2 read-only USB USB registers Peripheral_Registers 0x0 0x0 0xD8 registers n ALTEV_REG Alternate Event Register 0x10 16 read-write n 0x0 0x0 USB_EOP End of Packet A valid EOP sequence was been detected on the USB. It is used when this device has initiated a Remote wake-up sequence to indicate that the Resume sequence has been acknowledged and completed by the host. This bit is cleared when the register is read. 3 4 read-write USB_RESET Reset This bit is set to 1, when 2.5 μ s of SEO have been detected on the upstream port. In response, the functional state should be reset (NFS in the NFSR register is set to RESET), where it must remain for at least 100 μ s. The functional state can then return to Operational state. This bit is cleared when the register is read 6 7 read-write USB_RESUME Resume Resume signalling is detected on the USB when the device is in Suspend state (NFS in the NFSR register is set to SUSPEND), and a non IDLE signal is present on the USB, indicating that this device should begin it's wake-up sequence and enter Operational state. This bit is cleared when the register is read. 7 8 read-write USB_SD3 Suspend Detect 3 ms This bit is set to 1 after 3 ms of IDLE have been detected on the upstream port, indicating that the device should be suspended. The suspend occurs under firmware control by writing the suspend value to the Node Functional State (NFSR) register. This bit is cleared when the register is read. 4 5 read-write USB_SD5 Suspend Detect 5 ms This bit is set to 1 after 5 ms of IDLE have been detected on the upstream port, indicating that this device is permitted to perform a remote wake-up operation. The resume may be initiated under firmware control by writing the resume value to the NFSR register. This bit is cleared when the register is read. 5 6 read-write ALTMSK_REG Alternate Mask Register 0x12 16 read-write n 0x0 0x0 USB_M_EOP Same Bit Definition as ALTEV Register 3 4 read-write USB_M_RESET Same Bit Definition as ALTEV Register 6 7 read-write USB_M_RESUME A bit set to 1 in this register enables automatic setting of the ALT bit in the MAEV register when the respective event in the ALTEV register occurs. Otherwise, setting MAEV.ALT bit is disabled. Same Bit Definition as ALTEV Register 7 8 read-write USB_M_SD3 Same Bit Definition as ALTEV Register 4 5 read-write USB_M_SD5 Same Bit Definition as ALTEV Register 5 6 read-write CHARGER_CTRL_REG USB Charger Control Register 0xD4 16 read-write n 0x0 0x0 IDM_SINK_ON 0 = Disable 1 = Enable the Idm_sink to USBm 5 6 read-write IDP_SINK_ON 0 = Disable 1 = Enable the Idp_sink to USBp 4 5 read-write IDP_SRC_ON 0 = Disable 1 = Enable the Idp_src and Rdm_dwn. 1 2 read-write USB_CHARGE_ON 0 = Disable USB charger detect circuit. 1 = Enable USB charger detect circuit. 0 1 read-write VDM_SRC_ON 0 = Disable 1 = Enable Vdm_src to USBm and USB_DCP_DET status bit. 3 4 read-write VDP_SRC_ON 0 = Disable 1 = Enable the Vdp_src to USB_CHG_DET status bit. 2 3 read-write CHARGER_STAT_REG USB Charger Status Register 0xD6 16 read-write n 0x0 0x0 USB_CHG_DET 0 = Standard downstream or nothing connected. 1 = Charging Downstream Port (CDP) or Dedicated Charging. 1 2 read-only USB_DCP_DET 0 = Charging downstream port is detected. 1 = Dedicated charger is detected. Control bit VDM_SRC_ON must be set to validate this status bit. Note: This register shows the actual status. 0 1 read-only USB_DM_VAL 0 = USBm < 0.8V 1 = USBm > 1.5V (PS2 or Proprietary Charger) 3 4 read-only USB_DM_VAL2 0 = USBm <2.3V 1 = USBm >2.5V 5 6 read-only USB_DP_VAL 0 = USBp < 0.8V 1 = USBp > 1.5V 2 3 read-only USB_DP_VAL2 0: USBp < 2.3V 1: USBp > 2.5V 4 5 read-only DMA_CTRL_REG USB DMA control register 0xD0 16 read-write n 0x0 0x0 USB_DMA_EN 0 = USB DMA control off. (Normal operation) 1 = USB_DMA on. DMA channels 0 and 1 are connected by USB Endpoint according bits USB_DMA_TX and USB_DMA_RX 6 7 read-write USB_DMA_RX 000 = DMA channels 0 is connected Rx USB Endpoint 2 001 = DMA channels 0 is connected Rx USB Endpoint 4 010 = DMA channels 0 is connected Rx USB Endpoint 6 100, 1xx = Reserved 0 3 read-write USB_DMA_TX 000 = DMA channels 1 is connected Tx USB Endpoint 1 001 = DMA channels 1 is connected Tx USB Endpoint 3 010 = DMA channels 1 is connected Tx USB Endpoint 5 100, 1xx = Reserved 3 6 read-write EP0_NAK_REG EP0 INNAK and OUTNAK Register 0x48 16 read-write n 0x0 0x0 USB_EP0_INNAK End point 0 IN NAK This bit is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the FAR register is set to 1) in response to an IN token. This bit is cleared when the register is read. 0 1 read-only USB_EP0_OUTNAK End point 0 OUT NAK This bit n is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the FAR register is set to 1) in response to an OUT token. This bit is not set if NAK is generated as result of an overrun condition. It is cleared when the register is read. 1 2 read-only EPC0_REG Endpoint Control 0 Register 0x40 16 read-write n 0x0 0x0 USB_DEF Default Address When set to 1, the device responds to the default address regardless of the contents of FAR6-0/EP03-0 fields. When an IN packet is transmitted for the endpoint, the DEF bit is automatically cleared to 0. This bit aids in the transition from default address to assigned address. The transition from the default address 00000000000b to an address assigned during bus enumeration may not occur in the middle of the SET_ADDRESS control sequence. This is necessary to complete the control sequence. However, the address must change immediately after this sequence finishes in order to avoid errors when another control sequence immediately follows the SET_ADDRESS command. On USB reset, the firmware has 10 ms for set-up, and should write 8016 to the FAR register and 0016 to the EPC0 register. On receipt of a SET_ADDRESS command, the firmware must write 4016 to the EPC0 register and (8016 and quot or and quot ) to the FAR register. It must then queue a zero length IN packet to complete the status phase of the SET_ADDRESS control sequence. 6 7 read-write USB_EP Endpoint Address This field holds the 4-bit Endpoint address. For Endpoint 0, these bits are hardwired to 0000b. Writing a 1 to any of the EP bits is ignored. 0 4 read-only USB_STALL Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: - The transmit FIFO is enabled and an IN token is received. - The receive FIFO is enabled and an OUT token is received. Note: A SETUP token does not cause a STALL handshake to be generated when this bit is set. Upon transmitting the STALL handshake, the RX_LAST and the TX_DONE bits in the respective Receive/Transmit Status registers are set to 1. 7 8 read-write EPC1_REG Endpoint Control Register 1 0x50 16 read-write n 0x0 0x0 USB_EP Endpoint Address This 4-bit field holds the endpoint address. 0 4 read-write USB_EP_EN Endpoint Enable When this bit is set to 1, the EP[3:0] field is used in address comparison, together with the AD[6:0] field in the FAR register. See Section 36.8 for a description. When cleared to 0, the endpoint does not respond to any token on the USB bus. 4 5 read-write USB_ISO Isochronous When this bit is set to 1, the endpoint is isochronous. This implies that no NAK is sent if the endpoint is not ready but enabled i.e. If an IN token is received and no data is available in the FIFO to transmit, or if an OUT token is received and the FIFO is full since there is no USB handshake for isochronous transfers. 5 6 read-write USB_STALL Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: The transmit FIFO is enabled and an IN token is received. The receive FIFO is enabled and an OUT token is received. Setting this bit to 1 does not generate a STALL handshake in response to a SETUP token 7 8 read-write EPC2_REG Endpoint Control Register 2 0x58 16 read-write n 0x0 0x0 USB_EP Endpoint Address This 4-bit field holds the endpoint address. 0 4 read-write USB_EP_EN Endpoint Enable When this bit is set to 1, the EP[3:0] field is used in address comparison, together with the AD[6:0] field in the FAR register. See Section 36.8 for a description. When cleared to 0, the endpoint does not respond to any token on the USB bus. 4 5 read-write USB_ISO Isochronous When this bit is set to 1, the endpoint is isochronous. This implies that no NAK is sent if the endpoint is not ready but enabled i.e. If an IN token is received and no data is available in the FIFO to transmit, or if an OUT token is received and the FIFO is full since there is no USB handshake for isochronous transfers. 5 6 read-write USB_STALL Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: The transmit FIFO is enabled and an IN token is received. The receive FIFO is enabled and an OUT token is received. Setting this bit to 1 does not generate a STALL handshake in response to a SETUP token 7 8 read-write EPC3_REG Endpoint Control Register 3 0x60 16 read-write n 0x0 0x0 USB_EP Endpoint Address This 4-bit field holds the endpoint address. 0 4 read-write USB_EP_EN Endpoint Enable When this bit is set to 1, the EP[3:0] field is used in address comparison, together with the AD[6:0] field in the FAR register. See Section 36.8 for a description. When cleared to 0, the endpoint does not respond to any token on the USB bus. 4 5 read-write USB_ISO Isochronous When this bit is set to 1, the endpoint is isochronous. This implies that no NAK is sent if the endpoint is not ready but enabled i.e. If an IN token is received and no data is available in the FIFO to transmit, or if an OUT token is received and the FIFO is full since there is no USB handshake for isochronous transfers. 5 6 read-write USB_STALL Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: The transmit FIFO is enabled and an IN token is received. The receive FIFO is enabled and an OUT token is received. Setting this bit to 1 does not generate a STALL handshake in response to a SETUP token 7 8 read-write EPC4_REG Endpoint Control Register 4 0x68 16 read-write n 0x0 0x0 USB_EP Endpoint Address This 4-bit field holds the endpoint address. 0 4 read-write USB_EP_EN Endpoint Enable When this bit is set to 1, the EP[3:0] field is used in address comparison, together with the AD[6:0] field in the FAR register. See Section 36.8 for a description. When cleared to 0, the endpoint does not respond to any token on the USB bus. 4 5 read-write USB_ISO Isochronous When this bit is set to 1, the endpoint is isochronous. This implies that no NAK is sent if the endpoint is not ready but enabled i.e. If an IN token is received and no data is available in the FIFO to transmit, or if an OUT token is received and the FIFO is full since there is no USB handshake for isochronous transfers. 5 6 read-write USB_STALL Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: The transmit FIFO is enabled and an IN token is received. The receive FIFO is enabled and an OUT token is received. Setting this bit to 1 does not generate a STALL handshake in response to a SETUP token 7 8 read-write EPC5_REG Endpoint Control Register 5 0x70 16 read-write n 0x0 0x0 USB_EP Endpoint Address This 4-bit field holds the endpoint address. 0 4 read-write USB_EP_EN Endpoint Enable When this bit is set to 1, the EP[3:0] field is used in address comparison, together with the AD[6:0] field in the FAR register. See Section 36.8 for a description. When cleared to 0, the endpoint does not respond to any token on the USB bus. 4 5 read-write USB_ISO Isochronous When this bit is set to 1, the endpoint is isochronous. This implies that no NAK is sent if the endpoint is not ready but enabled i.e. If an IN token is received and no data is available in the FIFO to transmit, or if an OUT token is received and the FIFO is full since there is no USB handshake for isochronous transfers. 5 6 read-write USB_STALL Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: The transmit FIFO is enabled and an IN token is received. The receive FIFO is enabled and an OUT token is received. Setting this bit to 1 does not generate a STALL handshake in response to a SETUP token 7 8 read-write EPC6_REG Endpoint Control Register 6 0x78 16 read-write n 0x0 0x0 USB_EP Endpoint Address This 4-bit field holds the endpoint address. 0 4 read-write USB_EP_EN Endpoint Enable When this bit is set to 1, the EP[3:0] field is used in address comparison, together with the AD[6:0] field in the FAR register. See Section 36.8 for a description. When cleared to 0, the endpoint does not respond to any token on the USB bus. 4 5 read-write USB_ISO Isochronous When this bit is set to 1, the endpoint is isochronous. This implies that no NAK is sent if the endpoint is not ready but enabled i.e. If an IN token is received and no data is available in the FIFO to transmit, or if an OUT token is received and the FIFO is full since there is no USB handshake for isochronous transfers. 5 6 read-write USB_STALL Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: The transmit FIFO is enabled and an IN token is received. The receive FIFO is enabled and an OUT token is received. Setting this bit to 1 does not generate a STALL handshake in response to a SETUP token 7 8 read-write FAR_REG Function Address Register 0x8 16 read-write n 0x0 0x0 USB_AD Address This field holds the 7-bit function address used to transmit and receive all tokens addressed to this device. 0 7 read-write USB_AD_EN Address Enable When set to 1, USB address field bits 6-0 are used in address comparison (see and quot Address detection and quot on page 218 for a description). When cleared to 0, the device does not respond to any token on the USB bus. Note: If the DEF bit in the Endpoint Control 0 register is set, Endpoint 0 responds to the default address. 7 8 read-write FNH_REG Frame Number High Byte Register 0x24 16 read-write n 0x0 0x0 USB_FN_10_8 Frame Number This 3-bit field contains the three most significant bits (MSB) of the current frame number, received in the last SOF packet. If a valid frame number is not received within 12060 bit times (Frame Length Maximum, FLMAX, with tolerance) of the previous change, the frame number is incremented artificially. If two successive frames are missed or are incorrect, the current FN is frozen and loaded with the next frame number from a valid SOF packet. If the frame number low byte was read by firmware before reading the FNH register, the user actually reads the contents of a buffer register which holds the value of the three frame number bits of this register when the low byte was read. Therefore, the correct sequence to read the frame number is: FNL, FNH. Read operations to the FNH register, without first reading the Frame Number Low Byte (FNL) register directly, read the actual value of the three MSBs of the frame number. 0 3 read-only USB_MF Missed SOF Flag This flag is set to 1, when the frame number in a valid received SOF does not match the expected next value, or when an SOF is not received within 12060 bit times. This bit is set by the hardware and is cleared by reading the FNH register. 7 8 read-only USB_RFC Reset Frame Count Writing a 1 to this bit resets the frame number to 00016, after which this bit clears itself to 0 again. This bit always reads 0. 5 6 read-only USB_UL Unlock Flag This bit indicates that at least two frames were received without an expected frame number, or that no valid SOF was received within 12060 bit times. If this bit is set, the frame number from the next valid SOF packet is loaded in FN. This bit is set by the hardware and is cleared by reading the FNH register. 6 7 read-only FNL_REG Frame Number Low Byte Register 0x26 16 read-write n 0x0 0x0 USB_FN The Frame Number Low Byte Register holds the low byte of the frame number. To ensure consistency, reading this low byte causes the three frame number bits in the FNH register to be locked until this register is read. The correct sequence to read the frame number is: FNL, FNH. 0 8 read-only FWEV_REG FIFO Warning Event Register 0x20 16 read-write n 0x0 0x0 USB_RXWARN31 Receive Warning n: 3:1 The bit n is set to 1 when the respective receive endpoint FIFO reaches the warning limit, as specified by the RFWL bits of the respective EPCx register. This bit is cleared when the warning condition is cleared by either reading data from the FIFO or when the FIFO is flushed. 4 7 read-only USB_TXWARN31 Transmit Warning n: 3:1 The bit n is set to 1 when the respective transmit endpoint FIFO reaches the warning limit, as specified by the TFWL bits of the respective TXCn register, and transmission from the respective endpoint is enabled. This bit is cleared when the warning condition is cleared by either writing new data to the FIFO when the FIFO is flushed, or when transmission is done, as indicated by the TX_DONE bit in the TXSn register. 0 3 read-only FWMSK_REG FIFO Warning Mask Register 0x22 16 read-write n 0x0 0x0 USB_M_RXWARN31 The FIFO Warning Mask Register selects, which FWEV bits are reported in the MAEV register. A bit set to 1 and the corresponding bit in the FWEV register is set 1, causes the WARN bit in the MAEV register to be set to 1. When cleared to 0, the corresponding bit in the FWEV register does not cause WARN to be set to 1. Same Bit Definition as FWEV Register 4 7 read-write USB_M_TXWARN31 The FIFO Warning Mask Register selects, which FWEV bits are reported in the MAEV register. A bit set to 1 and the corresponding bit in the FWEV register is set 1, causes the WARN bit in the MAEV register to be set to 1. When cleared to 0, the corresponding bit in the FWEV register does not cause WARN to be set to 1. Same Bit Definition as FWEV Register 0 3 read-write MAEV_REG Main Event Register 0xC 16 read-write n 0x0 0x0 USB_ALT Alternate Event This bit indicates that one of the unmasked ALTEV register bits has been set to 1. This bit is cleared to 0 by reading the ALTEV register. 1 2 read-write USB_CH_EV USB Charger event This bit is set if one of the bits in USB_CHARGER_STAT_REG[2-0] change. This bit is cleared to 0 when if USB_CHARGER_STAT_REG is read. 11 12 read-write USB_EP0_NAK Endpoint 0 NAK Event This bit is an OR of EP0_NAK_REG[EP0_OUTNAK] and EP0_NAK_REG[EP0_INNAK] bits. USB_EP0_NAK is cleared to 0 when EP0_NAK_REG is read. 10 11 read-write USB_EP0_RX Endpoint 0 Receive Event This bit is a copy of the RXS0[RX_LAST] and is cleared to 0 when this RXS0 register is read. Note: Since Endpoint 0 implements a store and forward principle, an overrun condition for FIFO0 cannot occur 9 10 read-write USB_EP0_TX Endpoint 0 Transmit Event This bit is a copy of the TXS0[TX_DONE] bit and is cleared to 0 when the TXS0 register is read. Note: Since Endpoint 0 implements a store and forward principle, an underrun condition for FIFO0 cannot occur. 8 9 read-write USB_FRAME Frame Event This bit is set to 1, if the frame counter is updated with a new value. This can be due to the receipt of a valid SOF packet on the USB or to an artificial update if the frame counter was unlocked or a frame was missed. This bit is cleared to 0 when the register is read. 3 4 read-write USB_INTR Master Interrupt Enable This bit is hardwired to 0 in the Main Event (MAEV) register bit 7 in the Main Mask (MAMSK) register is the Master Interrupt Enable. 7 8 read-write USB_NAK Negative Acknowledge Event This bit indicates that one of the unmasked NAK Event (NAKEV) register bits has been set to 1. This bit is cleared to 0 when the NAKEV register is read. 4 5 read-write USB_RX_EV Receive Event This bit is set to 1 if any of the unmasked bits in the Receive Event (RXEV) register is set to 1. It indicates that a SETUP or OUT transaction has been completed. This bit is cleared to 0 when all of the RX_LAST bits in each Receive Status (RXSn) register and all RXOVRRN bits in the RXEV register are cleared to 0. 6 7 read-write USB_TX_EV Transmit Event This bit is set to 1, if any of the unmasked bits in the Transmit Event (TXEV) register (TXFIFOn or TXUNDRNn) is set to 1. Therefore, it indicates that an IN transaction has been completed. This bit is cleared to 0 when all the TX_DONE bits and the TXUNDRN bits in each Transmit Status (TXSn) register are cleared to 0. 2 3 read-write USB_ULD Unlocked/Locked Detected This bit is set to 1, when the frame timer has either entered unlocked condition from a locked condition, or has re-entered a locked condition from an unlocked condition as determined by the UL bit in the Frame Number (FNH or FNL) register. This bit is cleared to 0 when the register is read. 5 6 read-write USB_WARN Warning Event This bit indicates that one of the unmasked bits in the FIFO Warning Event (FWEV) register has been set to 1. This bit is cleared to 0 by reading the FWEV register. 0 1 read-write MAMSK_REG Main Mask Register 0xE 16 read-write n 0x0 0x0 USB_M_ALT Same Bit Definition as MAEV Register 1 2 read-write USB_M_CH_EV The Main Mask Register masks out events reported in the MAEV registers. A bit set to 1, enables the interrupts for the respective event in the MAEV register. If the corresponding bit is cleared to 0, interrupt generation for this event is disabled. Same Bit Definition as MAEV Register 11 12 read-write USB_M_EP0_NAK Same Bit Definition as MAEV Register 10 11 read-write USB_M_EP0_RX Same Bit Definition as MAEV Register 9 10 read-write USB_M_EP0_TX Same Bit Definition as MAEV Register 8 9 read-write USB_M_FRAME Same Bit Definition as MAEV Register 3 4 read-write USB_M_INTR Same Bit Definition as MAEV Register 7 8 read-write USB_M_NAK Same Bit Definition as MAEV Register 4 5 read-write USB_M_RX_EV Same Bit Definition as MAEV Register 6 7 read-write USB_M_TX_EV Same Bit Definition as MAEV Register 2 3 read-write USB_M_ULD Same Bit Definition as MAEV Register 5 6 read-write USB_M_WARN Same Bit Definition as MAEV Register 0 1 read-write MCTRL_REG Main Control Register) 0x0 16 read-write n 0x0 0x0 LSMODE Low Speed Mode This bit enables USB 1.5 Mbit/s low speed and swaps D+ and D- pull-up resistors. Changing speed may only be done if USBEN is set to 0. Also D+ and D- rise and fall times are adjusted according to the USB specification. 4 5 read-write USBEN USB EnableSetting this bit to 1 enables the Full/Low Speed USB node. If the USBEN bit is cleared to 0, the USB is disabled and the 48 MHz clock within the USB node is stopped. In addition, all USB registers are set to their reset state, except for the mentioned registers in Note 45 . Note that the transceiver forces SE0 on the bus to prevent the hub to detected the USB node, when it is disabled (not attached). The USBEN bit is cleared to 0 after reset 0 1 read-write USB_DBG Debug Mode. When this bit is set, the following registers are writable: Main Event (MAEV), Alternate Event (ALTEV), NAK Event (NAKEV), Transmit Status and Receive Status. Setting the DBG bit forces the node into a locked state. The node states can be read out of the transceiver diagnostic register (XCVDIAG) at location 0xFF6802 by setting the DIAG bit in the Test Control register (UTR). Note: The operation of CoR bits is not effected by entering Debug mode) Note: This bit can only be set is USBEN is '1' 1 2 read-write USB_NAT Node Attached This bit indicates that this node is ready to be detected as attached to USB. When cleared to 0 the transceiver forces SE0 on the USB port to prevent the hub (to which this node is connected to) from detecting an attach event. After reset or when the USB node is disabled, this bit is cleared to 0 to give the device time before it must respond to commands. After this bit has been set to 1, the device no longer drives the USB and should be ready to receive Reset signalling from the hub. Note: This bit can only be set is USBEN is '1' 3 4 read-write NAKEV_REG NAK Event Register 0x1C 16 read-write n 0x0 0x0 USB_IN31 IN n: 3:1 The bit n is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the Function Address, FAR, register is set to 1 and EP_EN in the Endpoint Control, EPCx, register is set to 1) in response to an IN token. This bit is cleared when the register is read. 0 3 read-only USB_OUT31 OUT n: 3:1 The bit n is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the FAR register is set to 1 and EP_EN in the EPCx register is set to 1) in response to an OUT token. This bit is not set if NAK is generated as result of an overrun condition. It is cleared when the register is read. 4 7 read-only NAKMSK_REG NAK Mask Register 0x1E 16 read-write n 0x0 0x0 USB_M_IN31 Same Bit Definition as NAKEV Register 0 3 read-write USB_M_OUT31 When set and the corresponding bit in the NAKEV register is set, the NAK bit in the MAEV register is set. When cleared, the corresponding bit in the NAKEV register does not cause NAK to be set. Same Bit Definition as NAKEV Register 4 7 read-write NFSR_REG Node Functional State Register 0xA 16 read-write n 0x0 0x0 USB_NFS The Node Functional State Register reports and controls the current functional state of the USB node. 00: NodeReset. This is the USB Reset state. This is entered upon a module reset or by software upon detection of a USB Reset. Upon entry, all endpoint pipes are disabled. DEF in the Endpoint Control 0 (EPC0) register and AD_EN in the Function Address (FAR) register should be cleared by software on entry to this state. On exit, DEF should be reset so the device responds to the default address. 01: NodeResume In this state, resume and quot K and quot signalling is generated. This state should be entered by firmware to initiate a remote wake-up sequence by the device. The node must remain in this state for at least 1 ms and no more than 15 ms. 10: NodeOperational This is the normal operational state. In this state the node is configured for operation on the USB bus. 11: NodeSuspend Suspend state should be entered by firmware on detection of a Suspend event while in Operational state. While in Suspend state, the transceivers operate in their low-power suspend mode. All endpoint controllers and the bits TX_EN, LAST and RX_EN are reset, while all other internal states are frozen. On detection of bus activity, the RESUME bit in the ALTEV register is set. In response, software can cause entry to NodeOperational state. 0 2 read-write RXC0_REG Receive Command 0 Register 0x4E 16 read-write n 0x0 0x0 USB_FLUSH Flush Writing a 1 to this bit flushes all data from the control endpoint FIFOs, resets the endpoint to Idle state, clears the FIFO read and write pointer, and then clears itself. If the endpoint is currently using FIFO0 to transfer data on USB, flushing is delayed until after the transfer is done. This bit is cleared to 0 on reset. This bit is equivalent to FLUSH in the TXC0 register. 3 4 read-write USB_IGN_OUT Ignore OUT Tokens When this bit is set to 1, the endpoint ignores any OUT tokens directed to its configured address. 1 2 read-write USB_IGN_SETUP Ignore SETUP Tokens When this bit is set to 1, the endpoint ignores any SETUP tokens directed to its configured address. 2 3 read-write USB_RX_EN Receive Enable OUT packet reception is disabled after every data packet is received, or when a STALL handshake is returned in response to an OUT token. A 1 must be written to this bit to re-enable data reception. Reception of SETUP packets is always enabled. In the case of back-to-back SETUP packets (for a given endpoint) where a valid SETUP packet is received with no other intervening non-SETUP tokens, the Endpoint Controller discards the new SETUP packet and returns an ACK handshake. If any other reasons prevent the Endpoint Controller from accepting the SETUP packet, it must not generate a handshake. This allows recovery from a condition where the ACK of the first SETUP token was lost by the host. 0 1 read-write RXC1_REG Receive Command Register 1 0x5E 16 read-write n 0x0 0x0 USB_FLUSH Flush FIFO Writing a 1 to this bit flushes all data from the corresponding receive FIFO, resets the endpoint to Idle state, and resets both the FIFO read and write pointers. If the MAC is currently using the FIFO to receive data, flushing is delayed until after receiving is completed. 3 4 read-write USB_IGN_SETUP Ignore SETUP Tokens When this bit is set to 1, the endpoint ignores any SETUP tokens directed to its configured address. 2 3 read-write USB_RFWL Receive FIFO Warning Limit These bits specify how many more bytes can be received to the respective FIFO before an overrun condition occurs. If the number of empty bytes remaining in the FIFO is equal to or less than the selected warning limit, the RXWARN bit in the FWEV register is set to 1.RFWL[1:0] : 00: RFWL disabled 01: Less than 5 bytes remaining in FIFO 10: Less than 9 bytes remaining in FIFO 11: Less than 17 bytes remaining in FIFO 5 7 read-write USB_RX_EN Receive Enable OUT packet cannot be received after every data packet is received, or when a STALL handshake is returned in response to an OUT token. This bit must be written with a 1 to re-enable data reception. SETUP packets can always be received. In the case of back-to-back SETUP packets (for a given endpoint) where a valid SETUP packet has been received with no other intervening non-SETUP tokens, the receive state machine discards the new SETUP packet and returns an ACK handshake. If, for any other reason, the receive state machine cannot accept the SETUP packet, no HANDSHAKE should be generated. 0 1 read-write RXC2_REG Receive Command Register 2 0x6E 16 read-write n 0x0 0x0 USB_FLUSH Flush FIFO Writing a 1 to this bit flushes all data from the corresponding receive FIFO, resets the endpoint to Idle state, and resets both the FIFO read and write pointers. If the MAC is currently using the FIFO to receive data, flushing is delayed until after receiving is completed. 3 4 read-write USB_IGN_SETUP Ignore SETUP Tokens When this bit is set to 1, the endpoint ignores any SETUP tokens directed to its configured address. 2 3 read-write USB_RFWL Receive FIFO Warning Limit These bits specify how many more bytes can be received to the respective FIFO before an overrun condition occurs. If the number of empty bytes remaining in the FIFO is equal to or less than the selected warning limit, the RXWARN bit in the FWEV register is set to 1.RFWL[1:0] : 00: RFWL disabled 01: Less than 5 bytes remaining in FIFO 10: Less than 9 bytes remaining in FIFO 11: Less than 17 bytes remaining in FIFO 5 7 read-write USB_RX_EN Receive Enable OUT packet cannot be received after every data packet is received, or when a STALL handshake is returned in response to an OUT token. This bit must be written with a 1 to re-enable data reception. SETUP packets can always be received. In the case of back-to-back SETUP packets (for a given endpoint) where a valid SETUP packet has been received with no other intervening non-SETUP tokens, the receive state machine discards the new SETUP packet and returns an ACK handshake. If, for any other reason, the receive state machine cannot accept the SETUP packet, no HANDSHAKE should be generated. 0 1 read-write RXC3_REG Receive Command Register 3 0x7E 16 read-write n 0x0 0x0 USB_FLUSH Flush FIFO Writing a 1 to this bit flushes all data from the corresponding receive FIFO, resets the endpoint to Idle state, and resets both the FIFO read and write pointers. If the MAC is currently using the FIFO to receive data, flushing is delayed until after receiving is completed. 3 4 read-write USB_IGN_SETUP Ignore SETUP Tokens When this bit is set to 1, the endpoint ignores any SETUP tokens directed to its configured address. 2 3 read-write USB_RFWL Receive FIFO Warning Limit These bits specify how many more bytes can be received to the respective FIFO before an overrun condition occurs. If the number of empty bytes remaining in the FIFO is equal to or less than the selected warning limit, the RXWARN bit in the FWEV register is set to 1.RFWL[1:0] : 00: RFWL disabled 01: Less than 5 bytes remaining in FIFO 10: Less than 9 bytes remaining in FIFO 11: Less than 17 bytes remaining in FIFO 5 7 read-write USB_RX_EN Receive Enable OUT packet cannot be received after every data packet is received, or when a STALL handshake is returned in response to an OUT token. This bit must be written with a 1 to re-enable data reception. SETUP packets can always be received. In the case of back-to-back SETUP packets (for a given endpoint) where a valid SETUP packet has been received with no other intervening non-SETUP tokens, the receive state machine discards the new SETUP packet and returns an ACK handshake. If, for any other reason, the receive state machine cannot accept the SETUP packet, no HANDSHAKE should be generated. 0 1 read-write RXD0_REG Receive Data 0 Register 0x4A 16 read-write n 0x0 0x0 USB_RXFD Receive FIFO Data Byte See and quot Bidirectional Control Endpoint FIFO0 and quot on page 220 for a description of data handling. The firmware should expect to read only the packet payload data. The PID and CRC16 are removed from the incoming data stream automatically. In TEST mode this register allow read/write access. 0 8 read-only RXD1_REG Receive Data Register,1 0x5A 16 read-write n 0x0 0x0 USB_RXFD Receive FIFO Data Byte See and quot Receive Endpoint FIFO and quot on page 223 for a description of Endpoint FIFO data handling.The firmware should expect to read only the packet payload data. The PID and CRC16 are terminated by the receive state machine. In TEST mode this register allow read/write access via the core bus. 0 8 read-only RXD2_REG Receive Data Register 2 0x6A 16 read-write n 0x0 0x0 USB_RXFD Receive FIFO Data Byte See and quot Receive Endpoint FIFO and quot on page 223 for a description of Endpoint FIFO data handling.The firmware should expect to read only the packet payload data. The PID and CRC16 are terminated by the receive state machine. In TEST mode this register allow read/write access via the core bus. 0 8 read-only RXD3_REG Receive Data Register 3 0x7A 16 read-write n 0x0 0x0 USB_RXFD Receive FIFO Data Byte See and quot Receive Endpoint FIFO and quot on page 223 for a description of Endpoint FIFO data handling.The firmware should expect to read only the packet payload data. The PID and CRC16 are terminated by the receive state machine. In TEST mode this register allow read/write access via the core bus. 0 8 read-only RXEV_REG Receive Event Register 0x18 16 read-write n 0x0 0x0 USB_RXFIFO31 Receive FIFO n: 3:1 The bit n is set to 1 whenever either RX_ERR or RX_LAST in the respective Receive Status register (RXSn) is set to 1. Reading the corresponding RXSn register automatically clears these bits.The CoR function is disabled, when the Freeze signal is asserted.The USB node discards all packets for Endpoint 0 received with errors. This is necessary in case of retransmission due to media errors, ensuring that a good copy of a SETUP packet is captured. Otherwise, the FIFO may potentially be tied up, holding corrupted data and unable to receive a retransmission of the same packet. If data streaming is used for the receive endpoints (EP2, EP4 and EP6, EP8) the firmware must check the respective RX_ERR bits to ensure the packets received are not corrupted by errors. 0 3 read-only USB_RXOVRRN31 Receive Overrun n: 3:1 The bit n is set to 1 in the event of an overrun condition in the corresponding receive FIFO n. They are cleared to 0 when the register is read. The firmware must check the respective RX_ERR bits that packets received for the other receive endpoints (EP2, EP4 and EP6, ) are not corrupted by errors, as these endpoints support data streaming (packets which are longer than the actual FIFO depth). 4 7 read-only RXMSK_REG Receive Mask Register 0x1A 16 read-write n 0x0 0x0 USB_M_RXFIFO31 Same Bit Definition as RXEV Register 0 3 read-write USB_M_RXOVRRN31 The Receive Mask Register is used to select the bits of the RXEV registers, which causes the RX_EV bit in the MAEV register to be set to 1. When set to 1 and the corresponding bit in the RXEV register is set to 1, RX_EV bit in the MAEV register is set to1. When cleared to 0, the corresponding bit in the RXEV register does not cause RX_EV to be set to1. Same Bit Definition as RXEV Register 4 7 read-write RXS0_REG Receive Status 0 Register 0x4C 16 read-write n 0x0 0x0 USB_RCOUNT Receive Count This 4-bit field contains the number of bytes presently in the RX FIFO. This number is never larger than 8 for Endpoint 0. 0 4 read-only USB_RX_LAST Receive Last Bytes This bit indicates that an ACK was sent upon completion of a successful receive operation. This bit is unchanged for zero length packets. It is cleared to 0 when this register is read. 4 5 read-only USB_SETUP Setup This bit indicates that the setup packet has been received. This bit is unchanged for zero length packets. It is cleared to 0 when this register is read. 6 7 read-only USB_TOGGLE_RX0 Toggle This bit specified the PID used when receiving the packet. A value of 0 indicates that the last successfully received packet had a DATA0 PID, while a value of 1 indicates that this packet had a DATA1 PID. This bit is unchanged for zero length packets. It is cleared to 0 when this register is read. 5 6 read-only RXS1_REG Receive Status Register 1 0x5C 16 read-write n 0x0 0x0 USB_RCOUNT Receive Counter This 4-bit field contains the number of bytes presently in the endpoint receive FIFO. If this number is greater than 15, a value of 15 is actually reported. 0 4 read-only USB_RX_ERR Receive Error When set to 1, this bit indicates a media error, such as bit-stuffing or CRC. If this bit is set to 1, the firmware must flush the respective FIFO. 7 8 read-only USB_RX_LAST Receive Last This bit indicates that an ACK was sent upon completion of a successful receive operation. This bit is cleared to 0 when this register is read. 4 5 read-only USB_SETUP Setup This bit indicates that the setup packet has been received. It is cleared when this register is read. 6 7 read-only USB_TOGGLE_RX Toggle The function of this bit differs depending on whether ISO (ISO in the EPCn register is set) or non-ISO operation (ISO is reset) is used. For non-ISO operation, a value of 0 indicates that the last successfully received packet had a DATA0 PID, while a value of 1 indicates that this packet had a DATA1 PID. For ISO operation, this bit reflects the LSB of the frame number (FNL0) after a packet was successfully received for this endpoint. This bit is reset to 0 by reading the RXSn register. 5 6 read-only RXS2_REG Receive Status Register 2 0x6C 16 read-write n 0x0 0x0 USB_RCOUNT Receive Counter This 4-bit field contains the number of bytes presently in the endpoint receive FIFO. If this number is greater than 15, a value of 15 is actually reported. 0 4 read-only USB_RX_ERR Receive Error When set to 1, this bit indicates a media error, such as bit-stuffing or CRC. If this bit is set to 1, the firmware must flush the respective FIFO. 7 8 read-only USB_RX_LAST Receive Last This bit indicates that an ACK was sent upon completion of a successful receive operation. This bit is cleared to 0 when this register is read. 4 5 read-only USB_SETUP Setup This bit indicates that the setup packet has been received. It is cleared when this register is read. 6 7 read-only USB_TOGGLE_RX Toggle The function of this bit differs depending on whether ISO (ISO in the EPCn register is set) or non-ISO operation (ISO is reset) is used. For non-ISO operation, a value of 0 indicates that the last successfully received packet had a DATA0 PID, while a value of 1 indicates that this packet had a DATA1 PID. For ISO operation, this bit reflects the LSB of the frame number (FNL0) after a packet was successfully received for this endpoint. This bit is reset to 0 by reading the RXSn register. 5 6 read-only RXS3_REG Receive Status Register 3 0x7C 16 read-write n 0x0 0x0 USB_RCOUNT Receive Counter This 4-bit field contains the number of bytes presently in the endpoint receive FIFO. If this number is greater than 15, a value of 15 is actually reported. 0 4 read-only USB_RX_ERR Receive Error When set to 1, this bit indicates a media error, such as bit-stuffing or CRC. If this bit is set to 1, the firmware must flush the respective FIFO. 7 8 read-only USB_RX_LAST Receive Last This bit indicates that an ACK was sent upon completion of a successful receive operation. This bit is cleared to 0 when this register is read. 4 5 read-only USB_SETUP Setup This bit indicates that the setup packet has been received. It is cleared when this register is read. 6 7 read-only USB_TOGGLE_RX Toggle The function of this bit differs depending on whether ISO (ISO in the EPCn register is set) or non-ISO operation (ISO is reset) is used. For non-ISO operation, a value of 0 indicates that the last successfully received packet had a DATA0 PID, while a value of 1 indicates that this packet had a DATA1 PID. For ISO operation, this bit reflects the LSB of the frame number (FNL0) after a packet was successfully received for this endpoint. This bit is reset to 0 by reading the RXSn register. 5 6 read-only TCR_REG Transceiver configuration Register 0x4 16 read-write n 0x0 0x0 USB_CADJ Transmitter Current Adjust Controls the driver edge rate control current. Shall not be modified unless instructed by Dialog Semiconductor Only enabled if USB_UTR_REG[7] = 1 0 5 read-write USB_VADJ Reference Voltage/ Threshold voltage AdjustControls the single-ended receiver threshold. Shall not be modified unless instructed by Dialog Semiconductor Only enabled if USB_UTR_REG[7] = 1 5 8 read-write TXC0_REG Transmit command 0 Register 0x46 16 read-write n 0x0 0x0 USB_FLUSH Flush FIFO Writing a 1 to this bit flushes all data from the control endpoint FIFOs, resets the endpoint to Idle state, clears the FIFO read and write pointer, and then clears itself. If the endpoint is currently using the FIFO0 to transfer data on USB, flushing is delayed until after the transfer is done. It is equivalent to the FLUSH bit in the RXC0 register. 3 4 read-write USB_IGN_IN Ignore IN Tokens When this bit is set to 1, the endpoint will ignore any IN tokens directed to its configured address. 4 5 read-write USB_TOGGLE_TX0 Toggle This bit specifies the PID used when transmitting the packet. A value of 0 causes a DATA0 PID to be generated, while a value of 1 causes a DATA1 PID to be generated. This bit is not altered by the hardware. 2 3 read-write USB_TX_EN Transmission Enable This bit enables data transmission from the FIFO. It is cleared to 0 by hardware after transmitting a single packet, or a STALL handshake, in response to an IN token. It must be set to 1 by firmware to start packet transmission. The RX_EN bit in the Receive Command 0 (RXC0) register takes precedence over this bit i.e. if RX_EN is set, TX_EN bit is ignored until RX_EN is reset. Zero length packets are indicated by setting this bit without writing any data to the FIFO. 0 1 read-write TXC1_REG Transmit Command Register 1 0x56 16 read-write n 0x0 0x0 USB_FLUSH Flush FIFO Writing a 1 to this bit flushes all data from the corresponding transmit FIFO, resets the endpoint to Idle state, and clears both the FIFO read and write pointers. If the MAC is currently using the FIFO to transmit, data is flushed after the transmission is complete. After data flushing, this bit is cleared to 0 by hardware. 3 4 read-write USB_IGN_ISOMSK Ignore ISO Mask This bit has an effect only if the endpoint is set to be isochronous. If set to 1, this bit disables locking of specific frame numbers with the alternate function of the TOGGLE bit. Thus data is transmitted upon reception of the next IN token. If cleared to 0, data is only transmitted when FNL0 matches TOGGLE. This bit is cleared to 0 after reset. 7 8 read-write USB_LAST Last Byte Setting this bit to 1 indicates that the entire packet has been written into the FIFO. This is used especially for streaming data to the FIFO while the actual transmission occurs. If the LAST bit is not set to 1 and the transmit FIFO becomes empty during a transmission, a stuff error followed by an EOP is forced on the bus. Zero length packets are indicated by setting this bit without writing any data to the FIFO. The transmit state machine transmits the payload data, CRC16 and the EOP signal before clearing this bit. 1 2 read-write USB_RFF Refill FIFO Setting the LAST bit to 1 automatically saves the Transmit Read Pointer (TXRP) to a buffer. When the RFF bit is set to 1, the buffered TXRP is reloaded into the TXRP. This allows the user to repeat the last transaction if no ACK was received from the host. If the MAC is currently using the FIFO to transmit, TXRP is reloaded only after the transmission is complete. After reload, this bit is cleared to 0 by hardware. 4 5 read-write USB_TFWL Transmit FIFO Warning Limit These bits specify how many more bytes can be transmitted from the respective FIFO before an underrun condition occurs. If the number of bytes remaining in the FIFO is equal to or less than the selected warning limit, the TXWARN bit in the FWEV register is set. To avoid interrupts caused by setting this bit while the FIFO is being filled before a transmission begins, TXWARN is only set when transmission from the endpoint is enabled (TX_ENn in the TXCn register is set). TFWL[1:0] : 00: TFWL disabled 01: Less than 5 bytes remaining in FIFO 10: Less than 9 bytes remaining in FIFO 11: Less than 17 bytes remaining in FIFO 5 7 read-write USB_TOGGLE_TX Toggle The function of this bit differs depending on whether ISO (ISO bit in the EPCn register is set to 1) or non-ISO operation (ISO bit is cleared to 0) is used. For non-ISO operation, it specifies the PID used when transmitting the packet. A value of 0 causes a DATA0 PID to be generated, while a value of 1 causes a DATA1 PID to be generated. For ISO operation, this bit and the LSB of the frame counter (FNL0) act as a mask for the TX_EN bit to allow pre-queuing of packets to specific frame numbers I.e. transmission is enabled only if bit 0 in the FNL register is set to TOGGLE. If an IN token is not received while this condition is true, the contents of the FIFO are flushed with the next SOF. If the endpoint is set to ISO, data is always transferred with a DATA0 PID. 2 3 read-write USB_TX_EN Transmission Enable This bit enables data transmission from the FIFO. It is cleared to 0 by hardware after transmitting a single packet or after a STALL handshake in response to an IN token. It must be set to 1 by firmware to start packet transmission. 0 1 read-write TXC2_REG Transmit Command Register 2 0x66 16 read-write n 0x0 0x0 USB_FLUSH Flush FIFO Writing a 1 to this bit flushes all data from the corresponding transmit FIFO, resets the endpoint to Idle state, and clears both the FIFO read and write pointers. If the MAC is currently using the FIFO to transmit, data is flushed after the transmission is complete. After data flushing, this bit is cleared to 0 by hardware. 3 4 read-write USB_IGN_ISOMSK Ignore ISO Mask This bit has an effect only if the endpoint is set to be isochronous. If set to 1, this bit disables locking of specific frame numbers with the alternate function of the TOGGLE bit. Thus data is transmitted upon reception of the next IN token. If cleared to 0, data is only transmitted when FNL0 matches TOGGLE. This bit is cleared to 0 after reset. 7 8 read-write USB_LAST Last Byte Setting this bit to 1 indicates that the entire packet has been written into the FIFO. This is used especially for streaming data to the FIFO while the actual transmission occurs. If the LAST bit is not set to 1 and the transmit FIFO becomes empty during a transmission, a stuff error followed by an EOP is forced on the bus. Zero length packets are indicated by setting this bit without writing any data to the FIFO. The transmit state machine transmits the payload data, CRC16 and the EOP signal before clearing this bit. 1 2 read-write USB_RFF Refill FIFO Setting the LAST bit to 1 automatically saves the Transmit Read Pointer (TXRP) to a buffer. When the RFF bit is set to 1, the buffered TXRP is reloaded into the TXRP. This allows the user to repeat the last transaction if no ACK was received from the host. If the MAC is currently using the FIFO to transmit, TXRP is reloaded only after the transmission is complete. After reload, this bit is cleared to 0 by hardware. 4 5 read-write USB_TFWL Transmit FIFO Warning Limit These bits specify how many more bytes can be transmitted from the respective FIFO before an underrun condition occurs. If the number of bytes remaining in the FIFO is equal to or less than the selected warning limit, the TXWARN bit in the FWEV register is set. To avoid interrupts caused by setting this bit while the FIFO is being filled before a transmission begins, TXWARN is only set when transmission from the endpoint is enabled (TX_ENn in the TXCn register is set). TFWL[1:0] : 00: TFWL disabled 01: Less than 5 bytes remaining in FIFO 10: Less than 9 bytes remaining in FIFO 11: Less than 17 bytes remaining in FIFO 5 7 read-write USB_TOGGLE_TX Toggle The function of this bit differs depending on whether ISO (ISO bit in the EPCn register is set to 1) or non-ISO operation (ISO bit is cleared to 0) is used. For non-ISO operation, it specifies the PID used when transmitting the packet. A value of 0 causes a DATA0 PID to be generated, while a value of 1 causes a DATA1 PID to be generated. For ISO operation, this bit and the LSB of the frame counter (FNL0) act as a mask for the TX_EN bit to allow pre-queuing of packets to specific frame numbers I.e. transmission is enabled only if bit 0 in the FNL register is set to TOGGLE. If an IN token is not received while this condition is true, the contents of the FIFO are flushed with the next SOF. If the endpoint is set to ISO, data is always transferred with a DATA0 PID. 2 3 read-write USB_TX_EN Transmission Enable This bit enables data transmission from the FIFO. It is cleared to 0 by hardware after transmitting a single packet or after a STALL handshake in response to an IN token. It must be set to 1 by firmware to start packet transmission. 0 1 read-write TXC3_REG Transmit Command Register 3 0x76 16 read-write n 0x0 0x0 USB_FLUSH Flush FIFO Writing a 1 to this bit flushes all data from the corresponding transmit FIFO, resets the endpoint to Idle state, and clears both the FIFO read and write pointers. If the MAC is currently using the FIFO to transmit, data is flushed after the transmission is complete. After data flushing, this bit is cleared to 0 by hardware. 3 4 read-write USB_IGN_ISOMSK Ignore ISO Mask This bit has an effect only if the endpoint is set to be isochronous. If set to 1, this bit disables locking of specific frame numbers with the alternate function of the TOGGLE bit. Thus data is transmitted upon reception of the next IN token. If cleared to 0, data is only transmitted when FNL0 matches TOGGLE. This bit is cleared to 0 after reset. 7 8 read-write USB_LAST Last Byte Setting this bit to 1 indicates that the entire packet has been written into the FIFO. This is used especially for streaming data to the FIFO while the actual transmission occurs. If the LAST bit is not set to 1 and the transmit FIFO becomes empty during a transmission, a stuff error followed by an EOP is forced on the bus. Zero length packets are indicated by setting this bit without writing any data to the FIFO. The transmit state machine transmits the payload data, CRC16 and the EOP signal before clearing this bit. 1 2 read-write USB_RFF Refill FIFO Setting the LAST bit to 1 automatically saves the Transmit Read Pointer (TXRP) to a buffer. When the RFF bit is set to 1, the buffered TXRP is reloaded into the TXRP. This allows the user to repeat the last transaction if no ACK was received from the host. If the MAC is currently using the FIFO to transmit, TXRP is reloaded only after the transmission is complete. After reload, this bit is cleared to 0 by hardware. 4 5 read-write USB_TFWL Transmit FIFO Warning Limit These bits specify how many more bytes can be transmitted from the respective FIFO before an underrun condition occurs. If the number of bytes remaining in the FIFO is equal to or less than the selected warning limit, the TXWARN bit in the FWEV register is set. To avoid interrupts caused by setting this bit while the FIFO is being filled before a transmission begins, TXWARN is only set when transmission from the endpoint is enabled (TX_ENn in the TXCn register is set). TFWL[1:0] : 00: TFWL disabled 01: Less than 5 bytes remaining in FIFO 10: Less than 9 bytes remaining in FIFO 11: Less than 17 bytes remaining in FIFO 5 7 read-write USB_TOGGLE_TX Toggle The function of this bit differs depending on whether ISO (ISO bit in the EPCn register is set to 1) or non-ISO operation (ISO bit is cleared to 0) is used. For non-ISO operation, it specifies the PID used when transmitting the packet. A value of 0 causes a DATA0 PID to be generated, while a value of 1 causes a DATA1 PID to be generated. For ISO operation, this bit and the LSB of the frame counter (FNL0) act as a mask for the TX_EN bit to allow pre-queuing of packets to specific frame numbers I.e. transmission is enabled only if bit 0 in the FNL register is set to TOGGLE. If an IN token is not received while this condition is true, the contents of the FIFO are flushed with the next SOF. If the endpoint is set to ISO, data is always transferred with a DATA0 PID. 2 3 read-write USB_TX_EN Transmission Enable This bit enables data transmission from the FIFO. It is cleared to 0 by hardware after transmitting a single packet or after a STALL handshake in response to an IN token. It must be set to 1 by firmware to start packet transmission. 0 1 read-write TXD0_REG Transmit Data 0 Register 0x42 16 read-write n 0x0 0x0 USB_TXFD Transmit FIFO Data Byte See and quot Bidirectional Control Endpoint FIFO0 and quot on page 220 for a description of data handling. The firmware is expected to write only the packet payload data. The PID and CRC16 are created automatically. 0 8 write-only TXD1_REG Transmit Data Register 1 0x52 16 read-write n 0x0 0x0 USB_TXFD Transmit FIFO Data Byte See and quot Transmit Endpoint FIFOs and quot on page 222 for a description of endpoint FIFO data handling. The firmware is expected to write only the packet payload data. PID and CRC16 are inserted automatically in the transmit data stream. In TEST mode this register allow read/write access via the core bus. 0 8 write-only TXD2_REG Transmit Data Register 2 0x62 16 read-write n 0x0 0x0 USB_TXFD Transmit FIFO Data Byte See and quot Transmit Endpoint FIFOs and quot on page 222 for a description of endpoint FIFO data handling. The firmware is expected to write only the packet payload data. PID and CRC16 are inserted automatically in the transmit data stream. In TEST mode this register allow read/write access via the core bus. 0 8 write-only TXD3_REG Transmit Data Register 3 0x72 16 read-write n 0x0 0x0 USB_TXFD Transmit FIFO Data Byte See and quot Transmit Endpoint FIFOs and quot on page 222 for a description of endpoint FIFO data handling. The firmware is expected to write only the packet payload data. PID and CRC16 are inserted automatically in the transmit data stream. In TEST mode this register allow read/write access via the core bus. 0 8 write-only TXEV_REG Transmit Event Register 0x14 16 read-write n 0x0 0x0 USB_TXFIFO31 Transmit FIFO n: 3:1 The bit n is a copy of the TX_DONE bit from the corresponding Transmit Status register (TXSn). A bit is set to 1 when the IN transaction for the corresponding transmit endpoint n has been completed. These bits are cleared to 0 when the corresponding TXSn register is read. 0 3 read-only USB_TXUDRRN31 Transmit Underrun n: 3:1 The bit n is a copy of the respective TX_URUN bit from the corresponding Transmit Status register (TXSn). Whenever any of the Transmit FIFOs underflows, the respective TXUDRRN bit is set to 1. These bits are cleared to 0 when the corresponding Transmit Status register is read 4 7 read-only TXMSK_REG Transmit Mask Register 0x16 16 read-write n 0x0 0x0 USB_M_TXFIFO31 Same Bit Definition as TXEV Register 0 3 read-write USB_M_TXUDRRN31 The Transmit Mask Register is used to select the bits of the TXEV registers, which causes the TX_EV bit in the MAEV register to be set to 1. When a bit is set to 1 and the corresponding bit in the TXEV register is set to 1, the TX_EV bit in the MAEV register is set to1. When cleared to 0, the corresponding bit in the TXEV register does not cause TX_EV to be set to 1. Same Bit Definition as TXEV Register 4 7 read-write TXS0_REG Transmit Status 0 Register 0x44 16 read-write n 0x0 0x0 USB_ACK_STAT Acknowledge Status This bit indicates the status, as received from the host, of the ACK for the packet previously sent. This bit is to be interpreted when TX_DONE is set to 1. It is set to 1, when an ACK is received otherwise, it remains cleared. This bit is also cleared to 0, when this register is read. 6 7 read-only USB_TCOUNT Transmission Count This 5-bit field indicates the number of empty bytes available in the FIFO. This field is never larger than 8 for Endpoint 0. 0 5 read-only USB_TX_DONE Transmission Done When set to 1, this bit indicates that a packet has completed transmission. It is cleared to 0, when this register is read. 5 6 read-only TXS1_REG Transmit Status Register 1 0x54 16 read-write n 0x0 0x0 USB_ACK_STAT Acknowledge Status This bit is interpreted when TX_DONE is set. It's function differs depending on whether ISO (ISO in the EPCx register is set) or non-ISO operation (ISO is reset) is used. For non-ISO operation, this bit indicates the acknowledge status (from the host) about the ACK for the previously sent packet. This bit itself is set to 1, when an ACK is received otherwise, it is cleared to 0. For ISO operation, this bit is set if a frame number LSB match (see and quot IGN_ISOMSK and quot bit in the USB_TXCx_REG) occurs, and data was sent in response to an IN token. Otherwise, this bit is cleared to 0, the FIFO is flushed and TX_DONE is set. This bit is also cleared to 0, when this register is read. 6 7 read-only USB_TCOUNT Transmission Count This 5-bit field holds the number of empty bytes available in the FIFO. If this number is greater than 31, a value of 31 is actually reported. 0 5 read-only USB_TX_DONE Transmission Done When set to 1, this bit indicates that the endpoint responded to a USB packet. Three conditions can cause this bit to be set: A data packet completed transmission in response to an IN token with non-ISO operation. The endpoint sent a STALL handshake in response to an IN token A scheduled ISO frame was transmitted or discarded. This bit is cleared to 0 when this register is read. 5 6 read-only USB_TX_URUN Transmit FIFO Underrun This bit is set to 1, if the transmit FIFO becomes empty during a transmission, and no new data is written to the FIFO. If so, the Media Access Controller (MAC) forces a bit stuff error followed by an EOP. This bit is cleared to 0, when this register is read. 7 8 read-only TXS2_REG Transmit Status Register 2 0x64 16 read-write n 0x0 0x0 USB_ACK_STAT Acknowledge Status This bit is interpreted when TX_DONE is set. It's function differs depending on whether ISO (ISO in the EPCx register is set) or non-ISO operation (ISO is reset) is used. For non-ISO operation, this bit indicates the acknowledge status (from the host) about the ACK for the previously sent packet. This bit itself is set to 1, when an ACK is received otherwise, it is cleared to 0. For ISO operation, this bit is set if a frame number LSB match (see and quot IGN_ISOMSK and quot bit in the USB_TXCx_REG) occurs, and data was sent in response to an IN token. Otherwise, this bit is cleared to 0, the FIFO is flushed and TX_DONE is set. This bit is also cleared to 0, when this register is read. 6 7 read-only USB_TCOUNT Transmission Count This 5-bit field holds the number of empty bytes available in the FIFO. If this number is greater than 31, a value of 31 is actually reported. 0 5 read-only USB_TX_DONE Transmission Done When set to 1, this bit indicates that the endpoint responded to a USB packet. Three conditions can cause this bit to be set: A data packet completed transmission in response to an IN token with non-ISO operation. The endpoint sent a STALL handshake in response to an IN token A scheduled ISO frame was transmitted or discarded. This bit is cleared to 0 when this register is read. 5 6 read-only USB_TX_URUN Transmit FIFO Underrun This bit is set to 1, if the transmit FIFO becomes empty during a transmission, and no new data is written to the FIFO. If so, the Media Access Controller (MAC) forces a bit stuff error followed by an EOP. This bit is cleared to 0, when this register is read. 7 8 read-only TXS3_REG Transmit Status Register 3 0x74 16 read-write n 0x0 0x0 USB_ACK_STAT Acknowledge Status This bit is interpreted when TX_DONE is set. It's function differs depending on whether ISO (ISO in the EPCx register is set) or non-ISO operation (ISO is reset) is used. For non-ISO operation, this bit indicates the acknowledge status (from the host) about the ACK for the previously sent packet. This bit itself is set to 1, when an ACK is received otherwise, it is cleared to 0. For ISO operation, this bit is set if a frame number LSB match (see and quot IGN_ISOMSK and quot bit in the USB_TXCx_REG) occurs, and data was sent in response to an IN token. Otherwise, this bit is cleared to 0, the FIFO is flushed and TX_DONE is set. This bit is also cleared to 0, when this register is read. 6 7 read-only USB_TCOUNT Transmission Count This 5-bit field holds the number of empty bytes available in the FIFO. If this number is greater than 31, a value of 31 is actually reported. 0 5 read-only USB_TX_DONE Transmission Done When set to 1, this bit indicates that the endpoint responded to a USB packet. Three conditions can cause this bit to be set: A data packet completed transmission in response to an IN token with non-ISO operation. The endpoint sent a STALL handshake in response to an IN token A scheduled ISO frame was transmitted or discarded. This bit is cleared to 0 when this register is read. 5 6 read-only USB_TX_URUN Transmit FIFO Underrun This bit is set to 1, if the transmit FIFO becomes empty during a transmission, and no new data is written to the FIFO. If so, the Media Access Controller (MAC) forces a bit stuff error followed by an EOP. This bit is cleared to 0, when this register is read. 7 8 read-only UTR_REG USB test Register (for test purpose only) 0x6 16 read-write n 0x0 0x0 USB_DIAG Diagnostic enable '0': Normal operational. '1': Access to the USB_XCVDIAG_REG and USB_TCR_REG enabled. For diagnostic purposes only 7 8 read-write USB_NCRC No CRC16 When this bit is set to 1, all packets transmitted by the Full/Low Speed USB node are sent without a trailing CRC16. Receive operations are unaffected. This mode is used to check that CRC errors can be detected by other nodes. For diagnostic purposes only 6 7 read-write USB_SF Short Frame Enables the Frame timer to lock and track, short, non-compliant USB frame sizes. The Short Frame bit should not be set during normal operation. For test purposes only 5 6 read-write USB_UTR_RES Reserved. Must be kept to '0' 0 5 read-write UX20CDR_REG Transceiver 2.0 Configuration and Diagnostics Register(for test purpose only) 0x3E 16 read-write n 0x0 0x0 RPU_RCDELAY Test bit, must be kept 0 1 2 read-write RPU_SSPROTEN Test bit, must be kept 0 0 1 read-write RPU_TEST7 Test bit 7 8 read-only RPU_TEST_EN Pull-Up Resistor Test Enable 0: Normal operation 1: Enables the test features controlled by RPU_TEST_SW1, RPU_TEST_SW1DM and RPU_TEST_SW2 (Note 47) 4 5 read-write RPU_TEST_SW1 0: Enable the pull-up resistor on USB_Dp (SW1 closed) 1: Disable the pull-up resistor on USB_Dp (SW1 open) (Independent of the VBus state). (Note 47) 5 6 read-write RPU_TEST_SW1DM 0: Enable the pull-up resistor on USB_Dm (SW1DM closed) 1: Disable the pull-up resistor on USB_Dm (SW1DM open) (Independent of the VBus state). (Note 47) 2 3 read-write RPU_TEST_SW2 0: Closes SW2 switch to reduced pull-up resistor connected to the USB_Dp and USB_Dm. 1: Opens SW2 switch resistor connected to the USB_Dp and USB_Dm (independent of the VBus state). (Note 47) 6 7 read-write XCVDIAG_REG Transceiver diagnostic Register (for test purpose only) 0x2 16 read-write n 0x0 0x0 USB_RCV With Bit0 = 1 this bit shows the differential level of the receive comparator. 5 6 read-only USB_VMIN With Bit0 = 1 this bit shows the level USB_Dm receive data from transceiver i.e. D- <= VSE. 6 7 read-only USB_VPIN With Bit0 = 1 this bit shows the level of the USB_Dp receive data from transceiver i.e. D+ <= VSE. 7 8 read-only USB_XCV_TEST Enable USB_XCVDIAG_REG 0: Normal operation, test bits disabled 1: Enable test bits 7,6,5,3,2,1 (Note 48) 0 1 read-write USB_XCV_TXEN With Bit0 = 1, this bit enables test Bits 2,1. Must be kept to '0' for normal operation 3 4 read-write USB_XCV_TXn With Bit3,0 = 1, this bit sets USB_Dm to a high level, independent of LSMODE selection 2 3 read-write USB_XCV_TXp With Bit3,0 = 1, this bit sets USB_Dp to a high level, independent of LSMODE selection 1 2 read-write WAKEUP WAKEUP registers Peripheral_Registers 0x0 0x0 0x1E registers n WKUP_COMPARE_REG Number of events before wakeup interrupt 0x2 16 read-write n 0x0 0x0 COMPARE The number of events that have to be counted before the wakeup interrupt will be given 0 8 read-write WKUP_COUNTER_REG Actual number of events of the wakeup counter 0x6 16 read-write n 0x0 0x0 EVENT_VALUE This value represents the number of events that have been counted so far. It will be reset by resetting the interrupt. 0 8 read-only WKUP_CTRL_REG Control register for the wakeup counter 0x0 16 read-write n 0x0 0x0 WKUP_DEB_VALUE Keyboard debounce time. If set to 0, no debouncing will be done. Debounce time: N*1 ms. N =1..63 Keyboard Debounce Time 0 6 read-write WKUP_ENABLE_IRQ 0: no interrupt will be enabled 1: if the event counter reaches the value set by WKUP_COMPARE_REG an IRQ will be generated 7 8 read-write WKUP_SFT_KEYHIT 0 = no effect 1 = emulate key hit. The event counter will increment by 1 (after debouncing if enabled). First make this bit 0 before any new key hit can be sensed. 6 7 read-write WKUP_POL_P0_REG select the sesitivity polarity for each P0 input 0x14 16 read-write n 0x0 0x0 WKUP_POL_P0 0: enabled input P0x will increment the event counter if that input goes high 1: enabled input P0x will increment the event counter if that input goes low 0 8 read-write WKUP_POL_P1_REG select the sesitivity polarity for each P1 input 0x16 16 read-write n 0x0 0x0 WKUP_POL_P1 0: enabled input P1x will increment the event counter if that input goes high 1: enabled input P1x will increment the event counter if that input goes low 0 8 read-write WKUP_POL_P2_REG select the sesitivity polarity for each P2 input 0x18 16 read-write n 0x0 0x0 WKUP_POL_P2 0: enabled input P2x will increment the event counter if that input goes high 1: enabled input P2x will increment the event counter if that input goes low 0 5 read-write WKUP_POL_P3_REG select the sesitivity polarity for each P3 input 0x1A 16 read-write n 0x0 0x0 WKUP_POL_P3 0: enabled input P3x will increment the event counter if that input goes high 1: enabled input P3x will increment the event counter if that input goes low 0 8 read-write WKUP_POL_P4_REG select the sesitivity polarity for each P3 input 0x1C 16 read-write n 0x0 0x0 WKUP_POL_P4 0: enabled input P4x will increment the event counter if that input goes high 1: enabled input P4x will increment the event counter if that input goes low 0 8 read-write WKUP_RESET_CNTR_REG Reset the event counter 0x8 16 read-write n 0x0 0x0 WKUP_CNTR_RST writing any value to this register will reset the event counter 0 16 write-only WKUP_RESET_IRQ_REG Reset wakeup interrupt 0x4 16 read-write n 0x0 0x0 WKUP_IRQ_RST writing any value to this register will reset the interrupt. reading always returns 0. 0 16 write-only WKUP_SELECT_P0_REG select which inputs from P0 port can trigger wkup counter 0xA 16 read-write n 0x0 0x0 WKUP_SELECT_P0 0: input P0x is not enabled for wakeup event counter 1: input P0x is enabled for wakeup event counter 0 8 read-write WKUP_SELECT_P1_REG select which inputs from P1 port can trigger wkup counter 0xC 16 read-write n 0x0 0x0 WKUP_SELECT_P1 0: input P1x is not enabled for wakeup event counter 1: input P1x is enabled for wakeup event counter 0 8 read-write WKUP_SELECT_P2_REG select which inputs from P2 port can trigger wkup counter 0xE 16 read-write n 0x0 0x0 WKUP_SELECT_P2 0: input P2x is not enabled for wakeup event counter 1: input P2x is enabled for wakeup event counter 0 5 read-write WKUP_SELECT_P3_REG select which inputs from P3 port can trigger wkup counter 0x10 16 read-write n 0x0 0x0 WKUP_SELECT_P3 0: input P3x is not enabled for wakeup event counter 1: input P3x is enabled for wakeup event counter 0 8 read-write WKUP_SELECT_P4_REG select which inputs from P4 port can trigger wkup counter 0x12 16 read-write n 0x0 0x0 WKUP_SELECT_P4 0: input P4x is not enabled for wakeup event counter 1: input P4x is enabled for wakeup event counter 0 8 read-write WDOG WDOG registers Peripheral_Registers 0x0 0x0 0x4 registers n WATCHDOG_CTRL_REG Watchdog control register. 0x2 16 read-write n 0x0 0x0 NMI_RST 0 = Watchdog timer generates NMI at value 0, and WDOG (SYS) reset at <=-16. Timer can be frozen /resumed using SET_FREEZE_REG[FRZ_WDOG]/ RESET_FREEZE_REG[FRZ_WDOG]. 1 = Watchdog timer generates a WDOG (SYS) reset at value 0 and can not be frozen by Software. Note that this bit can only be set to 1 by SW and only be reset with a WDOG (SYS) reset or SW reset. The watchdog is always frozen when the Cortex-M0 is halted in DEBUG State. 0 1 read-write WATCHDOG_REG Watchdog timer register. 0x0 16 read-write n 0x0 0x0 WDOG_VAL Write: Watchdog timer reload value. Note that all bits 15-9 must be 0 to reload this register. Read: Actual Watchdog timer value. Decremented by 1 every 10.24 msec. Bit 8 indicates a negative counter value. 2, 1, 0, 1FF16, 1FE16 etc. An NMI or WDOG (SYS) reset is generated under the following conditions: If WATCHDOG_CTRL_REG[NMI_RST] = 0 then If WDOG_VAL = 0 -> NMI (Non Maskable Interrupt) if WDOG_VAL = 1F016 -> WDOG reset -> reload FF16 If WATCHDOG_CTRL_REG[NMI_RST] = 1 then if WDOG_VAL <= 0 -> WDOG reset -> reload FF16 0 8 read-write WDOG_VAL_NEG 0 = Watchdog timer value is positive. 1 = Watchdog timer value is negative. 8 9 read-write WDOG_WEN 0000.000 = Write enable for Watchdog timer else Write disable. This filter prevents unintentional presetting the watchdog with a SW run-away. 9 16 write-only