ELAN eWD720 2024.05.05 ELAN eWD720 is ARM 32-bit Cortex-M0+ based device CM0PLUS r0p1 little 2 false 8 32 EINT EINT EINT 0x0 0x0 0x1000 registers n EINT EINT 2 EIESCR External Interrupt Edge Select Control Register 0x8 -1 read-write n 0x0 0x0 EIxESx External Interrupt Edge Select Control Register 0 16 read-write ENCR External Interrupt Enable Control 0x4 -1 read-write n 0x0 0x0 EXIE External Interrupt (INTx pin) Enable Bit (x=7~0) 0 8 read-write FLAG External interrupt status flag 0x0 -1 read-write n 0x0 0x0 EXSF External interrupt status flag 0 8 read-write FLASHCTRL Flash Control FLASHCTRL 0x0 0x0 0x1000 registers n CHIPPT CHIPPT 0x30 -1 read-write n 0x0 0x0 CHIPPT Chip protect level 0 8 read-only FLASH_IAPKEY FLASH_IAPKEY 0x0 -1 read-write n 0x0 0x0 IAPKEY In-Application Programming flash key 0 32 read-write FLASH_IAP_CR0 FLASH_IAP_CR0 0x4 -1 read-write n 0x0 0x0 IAP_CERASE IAP chip erase 8 9 read-write IAP_PERASE IAP page erase 9 10 read-write IAP_PWR IAP page write 0 1 read-write IAP_SERASE IAP sector erase 10 11 read-write IAP_WPROG IAP word program 1 2 read-write FLASH_IAP_CR1 FLASH_IAP_CR1 0x8 -1 read-write n 0x0 0x0 IAP_FINISH IAP finish flag 0 1 read-write IAP_LVD_EN IAP LVD enable 8 9 read-write IAP_LVD_STB IAP LVD stable 15 16 read-write IAP_LVF IAP Low Voltage Flag 9 10 read-write FLASH_IAP_CR2 FLASH_IAP_CR2 0xC -1 read-write n 0x0 0x0 PSAVE signal set-up time 0 1 read-write PSAVE_AUTO_EN Auto set PSAVE in Run mode 1 2 read-write FLASH_IAP_CR3 FLASH_IAP_CR3 0x10 -1 read-write n 0x0 0x0 IAPVFY IAP voltage verify 0 1 read-write FLASH_IAP_CR4 FLASH_IAP_CR4 0x14 -1 read-write n 0x0 0x0 IAPADDR In-Application Programming flash address 0 32 read-write FLASH_IAP_CR5 FLASH_IAP_CR5 0x18 -1 read-write n 0x0 0x0 IAPDATA In-Application Programming flash data 0 32 read-write FLASH_PDKEYR FLASH_PDKEYR 0x20 -1 read-write n 0x0 0x0 FL_PDKEYR Flash power-down key 0 32 read-write FLASH_PD_CSR FLASH_PD_CSR 0x24 -1 read-write n 0x0 0x0 FL_PDCTRL Flash power-down during Run mode and Sleep/Sleep0/Sleep1 mode 0 1 read-write FL_PDTYPE Flash power-down type selection 8 9 read-write FL_STB_F Flash power-on stable flag 10 11 read-only FL_WAKEUP Flash wake up mode selection 1 2 read-write FRDP1 FRDP1 0x34 -1 read-write n 0x0 0x0 FRDPA_EN Flash read protect area A 31 32 read-write FRDPA_SEC Flash read protect section count. 16 21 read-write FRDPA_START Flash read protect start address 0 16 read-write FRDP2 FRDP2 0x38 -1 read-write n 0x0 0x0 FRDPB_EN Flash read protect area B 31 32 read-write FRDPB_SEC Flash read protect section count. 16 21 read-write FRDPB_START Flash read protect start address 0 16 read-write FWRP1 FWRP1 0x3C -1 read-write n 0x0 0x0 FWRPA_EN Flash write protect area A 31 32 read-write FWRPA_SEC Flash write protect section count 16 21 read-write FWRPA_START Flash write protect start address 0 16 read-write FWRP2 FWRP2 0x40 -1 read-write n 0x0 0x0 FWRPB_EN Flash write protect area B 31 32 read-write FWRPB_SEC Flash write protect section count 16 21 read-write FWRPB_START Flash write protect start address 0 16 read-write GPIOA general-purpose I/O GPIO 0x0 0x0 0x1000 registers n GPIOA GPIO A combined interrupt 0 GPIOA_COMBO GPIO A combined interrupt 0 ALTFUNCCLR Alternate function clear Register 0x1C -1 read-write n 0x0 0x0 ALTFUNCSET Alternate function set Register 0x18 -1 read-write n 0x0 0x0 DATA Data Register 0x0 -1 read-write n 0x0 0x0 DATAOUT Data Output Register 0x4 -1 read-write n 0x0 0x0 INTCLEAR Interrupt CLEAR Register GPIOA_INTSTATUS 0x38 -1 write-only n 0x0 0x0 oneToClear INTENCLR Interrupt enable clear Register 0x24 -1 read-write n 0x0 0x0 INTENSET Interrupt enable set Register 0x20 -1 read-write n 0x0 0x0 INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x34 -1 read-write n 0x0 0x0 INTPOLSET Polarity-level, edge interrupt configuration set Register 0x30 -1 read-write n 0x0 0x0 INTSR_INTCLR GPIOA_INTSR_INTCLR 0x38 -1 read-only n 0x0 0x0 INTSR_INTCLR IRQ status clear Register 0 16 read-write INTSTATUS Interrupt Status Register 0x38 -1 read-only n 0x0 0x0 INTTYPECLR Interrupt type clear Register 0x2C -1 read-write n 0x0 0x0 INTTYPESET Interrupt type set Register 0x28 -1 read-write n 0x0 0x0 OUTENCLR Ouptut enable clear Register 0x14 -1 read-write n 0x0 0x0 OUTENSET Ouptut enable set Register 0x10 -1 read-write n 0x0 0x0 GPIOACFG general-purpose I/O configuration GPIOCFG 0x0 0x0 0x100 registers n GPIOA_ANL_AFSELR GPIOA_ANL_AFSELR 0xC -1 read-write n 0x0 0x0 ANL_AFSEL0 Analog alternate function selection for port A pin y 0 2 read-write ANL_AFSEL1 Analog alternate function selection for port A pin y 2 4 read-write ANL_AFSEL10 Analog alternate function selection for port A pin y 20 22 read-write ANL_AFSEL11 Analog alternate function selection for port A pin y 22 24 read-write ANL_AFSEL12 Analog alternate function selection for port A pin y 24 26 read-write ANL_AFSEL13 Analog alternate function selection for port A pin y 26 28 read-write ANL_AFSEL14 Analog alternate function selection for port A pin y 28 30 read-write ANL_AFSEL15 Analog alternate function selection for port A pin y 30 32 read-write ANL_AFSEL2 Analog alternate function selection for port A pin y 4 6 read-write ANL_AFSEL3 Analog alternate function selection for port A pin y 6 8 read-write ANL_AFSEL4 Analog alternate function selection for port A pin y 8 10 read-write ANL_AFSEL5 Analog alternate function selection for port A pin y 10 12 read-write ANL_AFSEL6 Analog alternate function selection for port A pin y 12 14 read-write ANL_AFSEL7 Analog alternate function selection for port A pin y 14 16 read-write ANL_AFSEL8 Analog alternate function selection for port A pin y 16 18 read-write ANL_AFSEL9 Analog alternate function selection for port A pin y 18 20 read-write GPIOA_DG_AFSELRH GPIOA_DG_AFSELRH 0x8 -1 read-write n 0x0 0x0 DG_AFSEL10 Digital alternate function selection for port A pin y 8 12 read-write DG_AFSEL11 Digital alternate function selection for port A pin y 12 16 read-write DG_AFSEL12 Digital alternate function selection for port A pin y 16 20 read-write DG_AFSEL13 Digital alternate function selection for port A pin y 20 24 read-write DG_AFSEL14 Digital alternate function selection for port A pin y 24 28 read-write DG_AFSEL15 Digital alternate function selection for port A pin y 28 32 read-write DG_AFSEL8 Digital alternate function selection for port A pin y 0 4 read-write DG_AFSEL9 Digital alternate function selection for port A pin y 4 8 read-write GPIOA_DG_AFSELRL GPIOA_DG_AFSELRL 0x4 -1 read-write n 0x0 0x0 DG_AFSEL0 Digital alternate function selection for port A pin y 0 4 read-write DG_AFSEL1 Digital alternate function selection for port A pin y 4 8 read-write DG_AFSEL2 Digital alternate function selection for port A pin y 8 12 read-write DG_AFSEL3 Digital alternate function selection for port A pin y 12 16 read-write DG_AFSEL4 Digital alternate function selection for port A pin y 16 20 read-write DG_AFSEL5 Digital alternate function selection for port A pin y 20 24 read-write DG_AFSEL6 Digital alternate function selection for port A pin y 24 28 read-write DG_AFSEL7 Digital alternate function selection for port A pin y 28 32 read-write GPIOA_HDHSR GPIOA_HDHSR 0x1C -1 read-write n 0x0 0x0 HDHSR Port A configuration bits 0 16 read-write GPIOA_IHYSTER GPIOA_IHYSTER 0x20 -1 read-write n 0x0 0x0 IHYSTER Port A configuration bits 0 16 read-write GPIOA_MODER GPIOA_MODER 0x0 -1 read-write n 0x0 0x0 MODER Port A configuration bits 0 16 read-write GPIOA_OTYPER GPIOA_OTYPER 0x10 -1 read-write n 0x0 0x0 OTYPER0 Port A configuration bits 0 2 read-write OTYPER1 Port A configuration bits 2 4 read-write OTYPER10 Port A configuration bits 20 22 read-write OTYPER11 Port A configuration bits 22 24 read-write OTYPER12 Port A configuration bits 24 26 read-write OTYPER13 Port A configuration bits 26 28 read-write OTYPER14 Port A configuration bits 28 30 read-write OTYPER15 Port A configuration bits 30 32 read-write OTYPER2 Port A configuration bits 4 6 read-write OTYPER3 Port A configuration bits 6 8 read-write OTYPER4 Port A configuration bits 8 10 read-write OTYPER5 Port A configuration bits 10 12 read-write OTYPER6 Port A configuration bits 12 14 read-write OTYPER7 Port A configuration bits 14 16 read-write OTYPER8 Port A configuration bits 16 18 read-write OTYPER9 Port A configuration bits 18 20 read-write GPIOA_PDR GPIOA_PDR 0x18 -1 read-write n 0x0 0x0 PDR0 Port A configuration bits 0 2 read-write PDR1 Port A configuration bits 2 4 read-write PDR10 Port A configuration bits 20 22 read-write PDR11 Port A configuration bits 22 24 read-write PDR12 Port A configuration bits 24 26 read-write PDR13 Port A configuration bits 26 28 read-write PDR14 Port A configuration bits 28 30 read-write PDR15 Port A configuration bits 30 32 read-write PDR2 Port A configuration bits 4 6 read-write PDR3 Port A configuration bits 6 8 read-write PDR4 Port A configuration bits 8 10 read-write PDR5 Port A configuration bits 10 12 read-write PDR6 Port A configuration bits 12 14 read-write PDR7 Port A configuration bits 14 16 read-write PDR8 Port A configuration bits 16 18 read-write PDR9 Port A configuration bits 18 20 read-write GPIOA_PUR GPIOA_PUR 0x14 -1 read-write n 0x0 0x0 PUR0 Port A configuration bits 0 2 read-write PUR1 Port A configuration bits 2 4 read-write PUR10 Port A configuration bits 20 22 read-write PUR11 Port A configuration bits 22 24 read-write PUR12 Port A configuration bits 24 26 read-write PUR13 Port A configuration bits 26 28 read-write PUR14 Port A configuration bits 28 30 read-write PUR15 Port A configuration bits 30 32 read-write PUR2 Port A configuration bits 4 6 read-write PUR3 Port A configuration bits 6 8 read-write PUR4 Port A configuration bits 8 10 read-write PUR5 Port A configuration bits 10 12 read-write PUR6 Port A configuration bits 12 14 read-write PUR7 Port A configuration bits 14 16 read-write PUR8 Port A configuration bits 16 18 read-write PUR9 Port A configuration bits 18 20 read-write GPIOB general-purpose I/O GPIO 0x0 0x0 0x1000 registers n GPIOB GPIO B combined interrupt 1 GPIOB_COMBO GPIO B combined interrupt 1 ALTFUNCCLR Alternate function clear Register 0x1C -1 read-write n 0x0 0x0 ALTFUNCSET Alternate function set Register 0x18 -1 read-write n 0x0 0x0 DATA Data Register 0x0 -1 read-write n 0x0 0x0 DATAOUT Data Output Register 0x4 -1 read-write n 0x0 0x0 INTCLEAR Interrupt CLEAR Register GPIOB_INTSTATUS 0x38 -1 write-only n 0x0 0x0 oneToClear INTENCLR Interrupt enable clear Register 0x24 -1 read-write n 0x0 0x0 INTENSET Interrupt enable set Register 0x20 -1 read-write n 0x0 0x0 INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x34 -1 read-write n 0x0 0x0 INTPOLSET Polarity-level, edge interrupt configuration set Register 0x30 -1 read-write n 0x0 0x0 INTSR_INTCLR GPIOB_INTSR_INTCLR 0x38 -1 read-only n 0x0 0x0 INTSR_INTCLR IRQ status clear Register 0 16 read-write INTSTATUS Interrupt Status Register 0x38 -1 read-only n 0x0 0x0 INTTYPECLR Interrupt type clear Register 0x2C -1 read-write n 0x0 0x0 INTTYPESET Interrupt type set Register 0x28 -1 read-write n 0x0 0x0 OUTENCLR Ouptut enable clear Register 0x14 -1 read-write n 0x0 0x0 OUTENSET Ouptut enable set Register 0x10 -1 read-write n 0x0 0x0 GPIOBCFG general-purpose I/O configuration GPIOCFG 0x0 0x0 0x100 registers n GPIOB_ANL_AFSELR GPIOB_ANL_AFSELR 0xC -1 read-write n 0x0 0x0 ANL_AFSEL0 Analog alternate function selection for port B pin y 0 2 read-write ANL_AFSEL1 Analog alternate function selection for port B pin y 2 4 read-write ANL_AFSEL10 Analog alternate function selection for port B pin y 20 22 read-write ANL_AFSEL11 Analog alternate function selection for port B pin y 22 24 read-write ANL_AFSEL12 Analog alternate function selection for port B pin y 24 26 read-write ANL_AFSEL13 Analog alternate function selection for port B pin y 26 28 read-write ANL_AFSEL14 Analog alternate function selection for port B pin y 28 30 read-write ANL_AFSEL15 Analog alternate function selection for port B pin y 30 32 read-write ANL_AFSEL2 Analog alternate function selection for port B pin y 4 6 read-write ANL_AFSEL3 Analog alternate function selection for port B pin y 6 8 read-write ANL_AFSEL4 Analog alternate function selection for port B pin y 8 10 read-write ANL_AFSEL5 Analog alternate function selection for port B pin y 10 12 read-write ANL_AFSEL6 Analog alternate function selection for port B pin y 12 14 read-write ANL_AFSEL7 Analog alternate function selection for port B pin y 14 16 read-write ANL_AFSEL8 Analog alternate function selection for port B pin y 16 18 read-write ANL_AFSEL9 Analog alternate function selection for port B pin y 18 20 read-write GPIOB_DG_AFSELRH GPIOB_DG_AFSELRH 0x8 -1 read-write n 0x0 0x0 DG_AFSEL10 Digital alternate function selection for port B pin y 8 12 read-write DG_AFSEL11 Digital alternate function selection for port B pin y 12 16 read-write DG_AFSEL12 Digital alternate function selection for port B pin y 16 20 read-write DG_AFSEL13 Digital alternate function selection for port B pin y 20 24 read-write DG_AFSEL14 Digital alternate function selection for port B pin y 24 28 read-write DG_AFSEL15 Digital alternate function selection for port B pin y 28 32 read-write DG_AFSEL8 Digital alternate function selection for port B pin y 0 4 read-write DG_AFSEL9 Digital alternate function selection for port B pin y 4 8 read-write GPIOB_DG_AFSELRL GPIOB_DG_AFSELRL 0x4 -1 read-write n 0x0 0x0 DG_AFSEL0 Digital alternate function selection for port B pin y 0 4 read-write DG_AFSEL1 Digital alternate function selection for port B pin y 4 8 read-write DG_AFSEL2 Digital alternate function selection for port B pin y 8 12 read-write DG_AFSEL3 Digital alternate function selection for port B pin y 12 16 read-write DG_AFSEL4 Digital alternate function selection for port B pin y 16 20 read-write DG_AFSEL5 Digital alternate function selection for port B pin y 20 24 read-write DG_AFSEL6 Digital alternate function selection for port B pin y 24 28 read-write DG_AFSEL7 Digital alternate function selection for port B pin y 28 32 read-write GPIOB_HDHSR GPIOB_HDHSR 0x1C -1 read-write n 0x0 0x0 HDHSR Port B configuration bits 0 16 read-write GPIOB_IHYSTER GPIOB_IHYSTER 0x20 -1 read-write n 0x0 0x0 IHYSTER Port B configuration bits 0 16 read-write GPIOB_MODER GPIOB_MODER 0x0 -1 read-write n 0x0 0x0 MODER Port B configuration bits 0 16 read-write GPIOB_OTYPER GPIOB_OTYPER 0x10 -1 read-write n 0x0 0x0 OTYPER0 Port B configuration bits 0 2 read-write OTYPER1 Port B configuration bits 2 4 read-write OTYPER10 Port B configuration bits 20 22 read-write OTYPER11 Port B configuration bits 22 24 read-write OTYPER12 Port B configuration bits 24 26 read-write OTYPER13 Port B configuration bits 26 28 read-write OTYPER14 Port B configuration bits 28 30 read-write OTYPER15 Port B configuration bits 30 32 read-write OTYPER2 Port B configuration bits 4 6 read-write OTYPER3 Port B configuration bits 6 8 read-write OTYPER4 Port B configuration bits 8 10 read-write OTYPER5 Port B configuration bits 10 12 read-write OTYPER6 Port B configuration bits 12 14 read-write OTYPER7 Port B configuration bits 14 16 read-write OTYPER8 Port B configuration bits 16 18 read-write OTYPER9 Port B configuration bits 18 20 read-write GPIOB_PDR GPIOB_PDR 0x18 -1 read-write n 0x0 0x0 PDR0 Port B configuration bits 0 2 read-write PDR1 Port B configuration bits 2 4 read-write PDR10 Port B configuration bits 20 22 read-write PDR11 Port B configuration bits 22 24 read-write PDR12 Port B configuration bits 24 26 read-write PDR13 Port B configuration bits 26 28 read-write PDR14 Port B configuration bits 28 30 read-write PDR15 Port B configuration bits 30 32 read-write PDR2 Port B configuration bits 4 6 read-write PDR3 Port B configuration bits 6 8 read-write PDR4 Port B configuration bits 8 10 read-write PDR5 Port B configuration bits 10 12 read-write PDR6 Port B configuration bits 12 14 read-write PDR7 Port B configuration bits 14 16 read-write PDR8 Port B configuration bits 16 18 read-write PDR9 Port B configuration bits 18 20 read-write GPIOB_PUR GPIOB_PUR 0x14 -1 read-write n 0x0 0x0 PUR0 Port B configuration bits 0 2 read-write PUR1 Port B configuration bits 2 4 read-write PUR10 Port B configuration bits 20 22 read-write PUR11 Port B configuration bits 22 24 read-write PUR12 Port B configuration bits 24 26 read-write PUR13 Port B configuration bits 26 28 read-write PUR14 Port B configuration bits 28 30 read-write PUR15 Port B configuration bits 30 32 read-write PUR2 Port B configuration bits 4 6 read-write PUR3 Port B configuration bits 6 8 read-write PUR4 Port B configuration bits 8 10 read-write PUR5 Port B configuration bits 10 12 read-write PUR6 Port B configuration bits 12 14 read-write PUR7 Port B configuration bits 14 16 read-write PUR8 Port B configuration bits 16 18 read-write PUR9 Port B configuration bits 18 20 read-write GPIOC general-purpose I/O GPIO 0x0 0x0 0x1000 registers n GPIOC GPIO C combined interrupt 15 GPIOC_COMBO GPIO C combined interrupt 15 ALTFUNCCLR Alternate function clear Register 0x1C -1 read-write n 0x0 0x0 ALTFUNCSET Alternate function set Register 0x18 -1 read-write n 0x0 0x0 DATA Data Register 0x0 -1 read-write n 0x0 0x0 DATAOUT Data Output Register 0x4 -1 read-write n 0x0 0x0 INTCLEAR Interrupt CLEAR Register GPIOC_INTSTATUS 0x38 -1 write-only n 0x0 0x0 oneToClear INTENCLR Interrupt enable clear Register 0x24 -1 read-write n 0x0 0x0 INTENSET Interrupt enable set Register 0x20 -1 read-write n 0x0 0x0 INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x34 -1 read-write n 0x0 0x0 INTPOLSET Polarity-level, edge interrupt configuration set Register 0x30 -1 read-write n 0x0 0x0 INTSR_INTCLR GPIOC_INTSR_INTCLR 0x38 -1 read-only n 0x0 0x0 INTSR_INTCLR IRQ status clear Register 0 16 read-write INTSTATUS Interrupt Status Register 0x38 -1 read-only n 0x0 0x0 INTTYPECLR Interrupt type clear Register 0x2C -1 read-write n 0x0 0x0 INTTYPESET Interrupt type set Register 0x28 -1 read-write n 0x0 0x0 OUTENCLR Ouptut enable clear Register 0x14 -1 read-write n 0x0 0x0 OUTENSET Ouptut enable set Register 0x10 -1 read-write n 0x0 0x0 GPIOCCFG general-purpose I/O configuration GPIOCFG 0x0 0x0 0x100 registers n GPIOC_ANL_AFSELR GPIOC_ANL_AFSELR 0xC -1 read-write n 0x0 0x0 ANL_AFSEL0 Analog alternate function selection for port C pin y 0 2 read-write ANL_AFSEL1 Analog alternate function selection for port C pin y 2 4 read-write ANL_AFSEL10 Analog alternate function selection for port C pin y 20 22 read-write ANL_AFSEL11 Analog alternate function selection for port C pin y 22 24 read-write ANL_AFSEL12 Analog alternate function selection for port C pin y 24 26 read-write ANL_AFSEL13 Analog alternate function selection for port C pin y 26 28 read-write ANL_AFSEL14 Analog alternate function selection for port C pin y 28 30 read-write ANL_AFSEL15 Analog alternate function selection for port C pin y 30 32 read-write ANL_AFSEL2 Analog alternate function selection for port C pin y 4 6 read-write ANL_AFSEL3 Analog alternate function selection for port C pin y 6 8 read-write ANL_AFSEL4 Analog alternate function selection for port C pin y 8 10 read-write ANL_AFSEL5 Analog alternate function selection for port C pin y 10 12 read-write ANL_AFSEL6 Analog alternate function selection for port C pin y 12 14 read-write ANL_AFSEL7 Analog alternate function selection for port C pin y 14 16 read-write ANL_AFSEL8 Analog alternate function selection for port C pin y 16 18 read-write ANL_AFSEL9 Analog alternate function selection for port C pin y 18 20 read-write GPIOC_DG_AFSELRH GPIOC_DG_AFSELRH 0x8 -1 read-write n 0x0 0x0 DG_AFSEL10 Digital alternate function selection for port C pin y 8 12 read-write DG_AFSEL11 Digital alternate function selection for port C pin y 12 16 read-write DG_AFSEL12 Digital alternate function selection for port C pin y 16 20 read-write DG_AFSEL13 Digital alternate function selection for port C pin y 20 24 read-write DG_AFSEL14 Digital alternate function selection for port C pin y 24 28 read-write DG_AFSEL15 Digital alternate function selection for port C pin y 28 32 read-write DG_AFSEL8 Digital alternate function selection for port C pin y 0 4 read-write DG_AFSEL9 Digital alternate function selection for port C pin y 4 8 read-write GPIOC_DG_AFSELRL GPIOC_DG_AFSELRL 0x4 -1 read-write n 0x0 0x0 DG_AFSEL0 Digital alternate function selection for port C pin y 0 4 read-write DG_AFSEL1 Digital alternate function selection for port C pin y 4 8 read-write DG_AFSEL2 Digital alternate function selection for port C pin y 8 12 read-write DG_AFSEL3 Digital alternate function selection for port C pin y 12 16 read-write DG_AFSEL4 Digital alternate function selection for port C pin y 16 20 read-write DG_AFSEL5 Digital alternate function selection for port C pin y 20 24 read-write DG_AFSEL6 Digital alternate function selection for port C pin y 24 28 read-write DG_AFSEL7 Digital alternate function selection for port C pin y 28 32 read-write GPIOC_HDHSR GPIOC_HDHSR 0x1C -1 read-write n 0x0 0x0 HDHSR Port C configuration bits 0 16 read-write GPIOC_IHYSTER GPIOC_IHYSTER 0x20 -1 read-write n 0x0 0x0 IHYSTER Port C configuration bits 0 16 read-write GPIOC_MODER GPIOC_MODER 0x0 -1 read-write n 0x0 0x0 MODER Port C configuration bits 0 16 read-write GPIOC_OTYPER GPIOC_OTYPER 0x10 -1 read-write n 0x0 0x0 OTYPER0 Port C configuration bits 0 2 read-write OTYPER1 Port C configuration bits 2 4 read-write OTYPER10 Port C configuration bits 20 22 read-write OTYPER11 Port C configuration bits 22 24 read-write OTYPER12 Port C configuration bits 24 26 read-write OTYPER13 Port C configuration bits 26 28 read-write OTYPER14 Port C configuration bits 28 30 read-write OTYPER15 Port C configuration bits 30 32 read-write OTYPER2 Port C configuration bits 4 6 read-write OTYPER3 Port C configuration bits 6 8 read-write OTYPER4 Port C configuration bits 8 10 read-write OTYPER5 Port C configuration bits 10 12 read-write OTYPER6 Port C configuration bits 12 14 read-write OTYPER7 Port C configuration bits 14 16 read-write OTYPER8 Port C configuration bits 16 18 read-write OTYPER9 Port C configuration bits 18 20 read-write GPIOC_PDR GPIOC_PDR 0x18 -1 read-write n 0x0 0x0 PDR0 Port C configuration bits 0 2 read-write PDR1 Port C configuration bits 2 4 read-write PDR10 Port C configuration bits 20 22 read-write PDR11 Port C configuration bits 22 24 read-write PDR12 Port C configuration bits 24 26 read-write PDR13 Port C configuration bits 26 28 read-write PDR14 Port C configuration bits 28 30 read-write PDR15 Port C configuration bits 30 32 read-write PDR2 Port C configuration bits 4 6 read-write PDR3 Port C configuration bits 6 8 read-write PDR4 Port C configuration bits 8 10 read-write PDR5 Port C configuration bits 10 12 read-write PDR6 Port C configuration bits 12 14 read-write PDR7 Port C configuration bits 14 16 read-write PDR8 Port C configuration bits 16 18 read-write PDR9 Port C configuration bits 18 20 read-write GPIOC_PUR GPIOC_PUR 0x14 -1 read-write n 0x0 0x0 PUR0 Port C configuration bits 0 2 read-write PUR1 Port C configuration bits 2 4 read-write PUR10 Port C configuration bits 20 22 read-write PUR11 Port C configuration bits 22 24 read-write PUR12 Port C configuration bits 24 26 read-write PUR13 Port C configuration bits 26 28 read-write PUR14 Port C configuration bits 28 30 read-write PUR15 Port C configuration bits 30 32 read-write PUR2 Port C configuration bits 4 6 read-write PUR3 Port C configuration bits 6 8 read-write PUR4 Port C configuration bits 8 10 read-write PUR5 Port C configuration bits 10 12 read-write PUR6 Port C configuration bits 12 14 read-write PUR7 Port C configuration bits 14 16 read-write PUR8 Port C configuration bits 16 18 read-write PUR9 Port C configuration bits 18 20 read-write I2C I2C I2C 0x0 0x0 0x1000 registers n I2C_RX I2C Receive Interrupt 11 I2CBUF I2C Data Buffer Register 0xC -1 read-write n 0x0 0x0 BX Transmitting mode 0 8 read-write I2CDAR0 I2C device address register0 0x8 -1 read-write n 0x0 0x0 ADDR This register stores the address of I2C module 0 7 read-write ADDRH This register stores the address of I2C module 8 11 read-write BUSY I2C bus busy 7 8 read-only I2C_PEND_DIS Auto stretch SCL control bit 13 15 read-write 00 auto stretch SCL (until PEND bit is clear) 0 01 auto stretch SCL (256 sys clock, need to clear PEND bit before next byte) 1 10 auto stretch SCL (512 sys clock, need to clear PEND bit before next byte) 2 11 disable auto stretch SCL 3 I2C_STP_IEN STOP interrupt enable bit 12 13 read-write Disable Disabled 0 Enable Enabled 1 I2CDEGLDEL I2C Deglitch and Delay control register 0x3C -1 read-write n 0x0 0x0 SCL_Degitch_En SCL_Degitch_Enable_control 15 16 read-write Disable Disabled 0 Enable Enabled 1 SCL_Degitch_Sel SCL_Degitch_Channel Select 12 15 read-write 000 65ns 0 001 85ns 1 010 100ns 2 SCL_Delay_En SCL_Delay_Enable_control 7 8 read-write Disable Disabled 0 Enable Enabled 1 SCL_Delay_Sel SCL_Delay_Select (according table) Select 4 7 read-write SDA_Degitch_En SDA_Degitch_Enable_control 11 12 read-write Disable Disabled 0 Enable Enabled 1 SDA_Degitch_Sel SDA_Degitch_Channel Select 8 11 read-write 000 65ns 0 001 85ns 1 010 100ns 2 SDA_Delay_En SCL_Delay_Enable_control 3 4 read-write Disable Disabled 0 Enable Enabled 1 SDA_Delay_Sel SDA_Delay_Select (according table) 0 3 read-write I2CDIVCNT I2C Dive count 0x34 -1 read-write n 0x0 0x0 DIVCNT I2C APB divided count 0 8 read-write SBFEN Sleep buffer mode function enable bit. 13 14 read-write Disable Disabled 0 Enable Enabled 1 I2CON I2C control register 0x0 -1 read-write n 0x0 0x0 ACK The ACK condition bit is set to 1 by hardware when the device responds acknowledge (ACK) 2 3 read-only BUF_EN Buffer function enable bit: (only use for buffer based I2C) 9 10 read-write EMPTY Set by hardware when the I2C transmitted buffer register is empty 0 1 read-only FULL Set by hardware when I2C received buffer register is full 1 2 read-only GCEN I2C generate call function enable bit 8 9 read-write I2C_EN I2C controller enable bit 15 16 read-write Disable Disabled 0 Enable Enabled 1 MODE I2C Master/Slave mode select bit. 6 7 read-write Slave Slave 0 Master Master 1 RST_SW_N Software reset bit, low active 14 15 read-write SAR_EMPTY Will set when I2C transmits 1 byte data from I2C Slave 3 4 read-only STOP Stop 4 5 read-write STPIF I2C stop interrupt flag. 10 11 read-only STROBE_PEND It is used as strobe signal to control I2C circuit in sending SCL clock. 7 8 read-write I2CRXLEN I2C receive buffer length 0x1C -1 read-write n 0x0 0x0 FILTER_CNT_LOW Digital filter counter for the high level noise of SCL 9 16 read-write SCL_IN_DEL Select SCL input delay time for hold time requirement 5 7 read-write 00 bypass 0 01 30ns 1 10 200ns 2 11 400ns 3 SDA_IN_DEL Select SDA input delay time for hold time requirement 7 9 read-write 00 bypass 0 01 30ns 1 10 200ns 2 11 400ns 3 I2CRXLEN20 I2C receive buffer length(for eWD720) 0x44 -1 read-write n 0x0 0x0 RX_LEN I2C TX transmission data length (max length = 20) 0 5 read-only I2CRXNACK20 I2C received data number for Non-ack response (for eWD720) 0x48 -1 read-write n 0x0 0x0 RX_NACK I2C TX transmission data length (max length = 20) 0 5 read-write I2CRX_NACK I2C received data number for Non-ack response 0x20 -1 read-write n 0x0 0x0 ACKXNACK Response by ACK or NACK 7 8 read-write NACK NACK response 0 ACK ACK response 1 ADDR_SYNC Chcek address with sync or async SCL/SDA. 15 16 read-write ASYNC Chcek address with async SCL/SDA. 0 SYNC Chcek address with sync SCL/SDA. 1 FILTER_CNT_SCL Digital filter counter for the high / low level noise of SCL 8 15 read-write FILTER_LEVEL_SCL Response by ACK or NACK 6 7 read-write 0 filter noise at Low level on bus 0 1 filter noise at High level on bus 1 FILTER_TYPE_SCL Response by ACK or NACK 5 6 read-write 0 filter noise at High and Low level on bus 0 1 only filter noise at High or Low level on bus 1 I2CSAR I2C slave address register 0x4 -1 read-write n 0x0 0x0 RnW This bit is a Read/Write transaction control bit. 0 1 read-write SAR Applies when I2C module is used as master device for I2C application 1 8 read-write SCL_DEGLITCH_SEL Select SCL deglitch delay time 14 16 read-write 00 50ns 0 01 200ns 1 10 400ns 2 11 Bypass 3 SDA_DEGLITCH_SEL Select SDA deglitch delay time 12 14 read-write 00 50ns 0 01 200ns 1 10 400ns 2 11 Bypass 3 SDA_DEL_NOR Select SDA output delay time for hold time requirement. (normal mode) 10 12 read-write 00 0ns 0 01 100ns 1 10 200ns 2 11 300ns 3 SDA_DEL_SLEEP Select SDA output delay time for hold time requirement 8 10 read-write 00 100ns 0 01 300ns 1 10 400ns 2 11 500ns 3 I2CSDA_FILTER I2C SDA digital filter 0x14 -1 read-write n 0x0 0x0 FILTER_CNT_SDA Digital filter counter for the high / low level noise of SDA 8 15 read-write FILTER_LEVEL_SDA Filter noise at Low or high level on bus 6 7 read-write 0 filter noise at Low level on bus 0 1 filter noise at High level on bus 1 FILTER_TYPE_SDA Filter noise 5 6 read-write 0 filter noise at High and Low level on bus 0 1 only filter noise at High or Low level on bus 1 I2CSTA I2C start/stop timing register 0x10 -1 read-write n 0x0 0x0 STAHD I2C start condition hold time detection 8 16 read-write STASU I2C start condition setup time detection 0 8 read-write I2CTXLEN I2C transmit buffer length 0x18 -1 read-write n 0x0 0x0 AL_DIS Arbitration lost disable. (use in master mode) 5 6 read-write AUTO_CNT High level of SCL counter. (0~511system clocks) 6 15 read-write AUTO_CNT_EN Auto count high level of SCL (ignore noise when counter is not full) 15 16 read-write Disable Disabled 0 Enable Enabled 1 TX_CNT_CLR TX_CNT reset bit: 4 5 read-write 0 reset TX_CNT when I2CTX_IF active 0 1 reset TX_CNT when TX_LEN = TX_CNT 1 I2CTXLEN20 I2C transmit buffer length (for eWD720) 0x40 -1 read-write n 0x0 0x0 TX_LEN I2C TX transmission data length (max length = 20) 0 5 read-write SMbusTO1 SMbus Time Out 1 register 0x24 -1 read-write n 0x0 0x0 TO1EN SMbus time out function enable bit: (standard 35ms) 15 16 read-write Disable Disabled 0 Enable Enabled 1 TO1SF SMbus Time Out 1 status flag. 14 15 read-write NonTrigger Interrupt non-trigger 0 Trigger Interrupt trigger 1 TO1TPRE Timer Pre-scaler Selection for 8-bit 8 11 read-write TO1TR Timer Reload Value 0 8 read-write SMbusTO2 SMbus Time Out 2 register 0x28 -1 read-write n 0x0 0x0 TO2EN SMbus time out function enable bit: (standard 25ms) 15 16 read-write Disable Disabled 0 Enable Enabled 1 TO2SF SMbus Time Out 2 status flag. 14 15 read-write NonTrigger Interrupt non-trigger 0 Trigger Interrupt trigger 1 TO2TPRE Timer Pre-scaler Selection for 8-bit 8 11 read-write TO2TR Timer Reload Value 0 8 read-write SMbusTO3 SMbus Time Out 3 register 0x2C -1 read-write n 0x0 0x0 TO3EN SMbus time out function enable bit: (standard 10ms) 15 16 read-write Disable Disabled 0 Enable Enabled 1 TO3SF SMbus Time Out 3 status flag. 14 15 read-write NonTrigger Interrupt non-trigger 0 Trigger Interrupt trigger 1 TO3TPRE Timer Pre-scaler Selection for 8-bit 8 11 read-write TO3TR Timer Reload Value 0 8 read-write IDWG Watchdog IDWG 0x0 0x0 0x1000 registers n WDOGCONTROL Watchdog Control Register 0x8 -1 read-write n 0x0 0x0 INTEN Enable the interrupt event, WDOGINT 0 1 RESEN Enable watchdog reset output, WDOGRES 1 2 WDOGINTCLR Watchdog Clear Interrupt Register 0xC -1 write-only n 0x0 0x0 WDOGLOAD The WDOGLOAD Register contains the value from which the counter is to decrement. 0x0 -1 read-write n 0x0 0x0 WDOGLOCK Watchdog Lock Register 0xC00 -1 read-write n 0x0 0x0 WDOGMIS Watchdog Interrupt Status Register 0x14 -1 read-only n 0x0 0x0 WDOGRIS Watchdog Raw Interrupt Status Register 0x10 -1 read-only n 0x0 0x0 WDOGVALUE The WDOGVALUE Register gives the current value of the decrementing counter 0x4 -1 read-write n 0x0 0x0 PWM PWM 1 PWM1 0x0 0x0 0x1000 registers n PWM3 PWM 3 Interrupt 17 DT1 PWM1 Duty 0x108 -1 read-write n 0x0 0x0 DT1 PWM1 Duty 0 16 read-write DT2 PWM2 Duty 0x208 -1 read-write n 0x0 0x0 DT2 PWM2 Duty 0 16 read-write DT3 PWM3 Duty 0x308 -1 read-write n 0x0 0x0 DT3 PWM3 Duty 0 16 read-write PRD1 PWM1 Period 0x104 -1 read-write n 0x0 0x0 PRD1 PWM1 Period 0 16 read-write PRD2 PWM2 Period 0x204 -1 read-write n 0x0 0x0 PRD2 PWM2 Period 0 16 read-write PRD3 PWM3 Period 0x304 -1 read-write n 0x0 0x0 PRD3 PWM3 Period 0 16 read-write PWM1CR PWM1 Control Register 0x100 -1 read-write n 0x0 0x0 PWM1A Active level of PWM1 13 14 read-write High Duty duration is logic high 0 Low Duty duration is logic low 1 PWM1DSF Status flag of duty-matching for PWM1. Read only. 16 17 read-only PWM1DSFCL Clear bit of PWM1 period-matching status flag 6 7 PWM1E Compound pin 15 16 read-write Disable Disabled 0 Enable Enabled 1 PWM1OSM One-shot mode of PWM. T1EN would be disable by HW when period match first time. 3 4 PWM1PSF Status flag of period-matching for PWM1. Read only. 17 18 read-only PWM1PSFCL Clear bit of PWM1 duty-matching status flag 7 8 write-only T1P TimerA clock pre-scale option bits 8 11 read-write PWM2CR PWM2 Control Register 0x200 -1 read-write n 0x0 0x0 PWM2A Active level of PWM2 13 14 read-write High Duty duration is logic high 0 Low Duty duration is logic low 1 PWM2DSF Status flag of duty-matching for PWM2. Read only. 16 17 read-only PWM2DSFCL Clear bit of PWM2 period-matching status flag 6 7 PWM2E Compound pin 15 16 read-write Disable Disabled 0 Enable Enabled 1 PWM2OSM One-shot mode of PWM. T2EN would be disable by HW when period match first time. 3 4 PWM2PSF Status flag of period-matching for PWM2. Read only. 17 18 read-only PWM2PSFCL Clear bit of PWM2 duty-matching status flag 7 8 write-only T2P TimerA clock pre-scale option bits 8 11 read-write PWM3CR PWM3 Control Register 0x300 -1 read-write n 0x0 0x0 PWM3A Active level of PWM3 13 14 read-write High Duty duration is logic high 0 Low Duty duration is logic low 1 PWM3DSF Status flag of duty-matching for PWM3. Read only. 16 17 read-only PWM3DSFCL Clear bit of PWM3 period-matching status flag 6 7 PWM3E Compound pin 15 16 read-write Disable Disabled 0 Enable Enabled 1 PWM3OSM One-shot mode of PWM. T3EN would be disable by HW when period match first time. 3 4 PWM3PSF Status flag of period-matching for PWM3. Read only. 17 18 read-only PWM3PSFCL Clear bit of PWM3 duty-matching status flag 7 8 write-only T3P TimerA clock pre-scale option bits 8 11 read-write PWMENCR PWM Enable Register 0x4 -1 read-write n 0x0 0x0 PWM1DTIE Enable 10 11 read-write Disable PWM1 Duty interrup disabled 0 Enable PWM1 Duty interrup enabled 1 PWM1PRDIE Enable 11 12 read-write Disable PWM1 Period interrupt disabled 0 Enable PWM1 Period interrupt enabled 1 PWM2DTIE Enable 12 13 read-write Disable PWM2 Duty interrup disabled 0 Enable PWM2 Duty interrup enabled 1 PWM2PRDIE Enable 13 14 read-write Disable PWM2 Period interrupt disabled 0 Enable PWM2 Period interrupt enabled 1 PWM3DTIE Enable 14 15 read-write Disable PWM3 Duty interrup disabled 0 Enable PWM3 Duty interrup enabled 1 PWM3PRDIE Enable 15 16 read-write Disable PWM3 Period interrupt disabled 0 Enable PWM3 Period interrupt enabled 1 TxEN TMRX enable bit 0 3 TMR1 Timer 1 0x10C -1 read-write n 0x0 0x0 TMR1 Timer 1 0 16 read-only TMR2 Timer 2 0x20C -1 read-write n 0x0 0x0 TMR2 Timer 2 0 16 read-only TMR3 Timer 3 0x30C -1 read-write n 0x0 0x0 TMR3 Timer 3 0 16 read-only SIP System in programming SIP 0x0 0x0 0x1000 registers n HLVDCR HLVDCR 0x0 -1 read-write n 0x0 0x0 HLVDEN High / Low Voltage Detector Enable Bit 7 8 read-write HLVDS High / Low Voltage Detector Level Bits 0 2 read-write HLVDSF Low Voltage Detector status flag 8 9 read-write IRVSF Internal Reference Voltage Stable Flag bit 6 7 read-write LVDWK Low Voltage Detect Wake-up Enable Bit 9 10 read-write VDM Voltage Direction Magnitude Select bit 4 5 read-write VDSB Voltage Detector State Bit.  This is a read only bit. 5 6 read-write LVRCR LVRCR 0x4 -1 read-write n 0x0 0x0 LVR Low voltage Level Bits. 0 2 read-write LVREN LVR Enable bit 7 8 read-write V18CR V18CR 0xC -1 read-write n 0x0 0x0 V18PD 1.8V Regulator power down control bit 1 2 read-write V18PMS 1.8V Regulator power mode section bit 0 1 read-write V18_KEY V18_KEY 0x8 -1 read-write n 0x0 0x0 V18_KEY Enable write access to V18CR register by writing 0x50AF 0 16 read-write SYSCFG SYSCFG SYSCFG 0x0 0x0 0x1000 registers n CFGR SYSCFG_CFGR 0x0 -1 read-write n 0x0 0x0 REMAP_MODER Memory mapping selection bits 0 3 read-write CLK_CALIB_HIRC CLK_CALIB_HIRC 0x194 -1 read-write n 0x0 0x0 HIRC_RT Trim bits of Main frequency IRC 0 8 read-write CLK_CALIB_KEY CLK_CALIB_KEY 0x190 -1 read-write n 0x0 0x0 CLK_CALIB_KEY Clock calibration key 0 16 read-write CLK_CFGR0 CLK_CFGR0 0x100 -1 read-write n 0x0 0x0 HIRC_FREQ_SEL HIRC frequency selection 0 2 read-write CLK_CFGR1 CLK_CFGR1 0x104 -1 read-write n 0x0 0x0 SCLK_SEL High frequency clock source selection 0 2 read-write CLK_CFGR2 CLK_CFGR2 0x108 -1 read-write n 0x0 0x0 HCLK_DIV High frequency clock clock divide 0 3 read-write HIRC_DIV High internal RC oscillator clock divide 8 11 read-write PCLK_DIV Peripherals clock divide 16 17 read-write TPCLK_DIV TP clock divide 24 27 read-write CLK_GATE_CR0 CLK_GATE_CR0 0x134 -1 read-write n 0x0 0x0 CLK_GATE_CLR Set by software to clear all gating clock bits 31 32 read-write CLK_GATE_SET Set by software to set all gating clock bits 30 31 read-write CLK_GATE_CR1 CLK_GATE_CR1 0x138 -1 read-write n 0x0 0x0 HCLKG_GPIOA Gating GPIOA clock 0 1 read-write HCLKG_GPIOB Gating GPIOB clock 1 2 read-write HCLKG_GPIOC Gating GPIOC clock 2 3 read-write PCLKG_AIP Gating AIP clock 16 17 read-write PCLKG_IWDG Gating independent watchdog clock 8 9 read-write PCLKG_TP Gating TP clock 9 10 read-write CLK_GATE_CR2 CLK_GATE_CR2 0x13C -1 read-write n 0x0 0x0 PCLKG_EINT Gating EINT clock 24 25 read-write PCLKG_I2C Gating I2C clock 2 3 read-write PCLKG_PWM1 Gating PWM1 clock 16 17 read-write PCLKG_PWM2 Gating PWM2 clock 17 18 read-write PCLKG_PWM3 Gating PWM3 clock 18 19 read-write PCLKG_TC1 Gating TC1 clock 8 9 read-write PCLKG_TC2 Gating TC2 clock 9 10 read-write PCLKG_UART Gating UART clock 0 1 read-write PCLKG_USART Gating USART clock 1 2 read-write CLK_GATE_KEY CLK_GATE_KEY 0x130 -1 read-write n 0x0 0x0 CLK_GATE_KEY Clock gating key 0 16 read-write CLK_GATE_VFREG_CR CLK_GATE_VFREG_CR 0x15C -1 read-write n 0x0 0x0 VFREG_CLK Gating VERIFYSET register clock 0 1 read-write CLK_OUT_CR CLK_OUT_CR 0x120 -1 read-write n 0x0 0x0 OCLK_DIV1 Output clock divide 1 16 24 read-write OCLK_DIV2 Output clock divide 2 24 32 read-write OCLK_SOURCE1 Output clock source selection for CLKO_1 0 5 read-write OCLK_SOURCE1_EN OCLK_SOURCE1 output control 7 8 read-write OCLK_SOURCE2 Output clock divide 2 8 13 read-write OCLK_SOURCE2_EN OCLK_SOURCE2 output control 15 16 read-write CLK_PP_CR CLK_PP_CR 0x160 -1 read-write n 0x0 0x0 TIMER1CLK_DIV Timer external clock divide 4 7 read-write TIMER1_ECSS External clock source selection 0 2 read-write TIMER2CLK_DIV Timer external clock divide 12 15 read-write TIMER2_ECSS External clock source selection 8 10 read-write DBG_CSR DBG_CSR 0x304 -1 read-write n 0x0 0x0 PWR_MODER_ST Power mode status 8 10 read-write DBG_DEVID DBG_DEVID 0x300 -1 read-write n 0x0 0x0 Marker Marker 24 28 read-write Process Process 16 21 read-write Product_Number Product_Number 0 16 read-write Product_Type Product_Type 28 32 read-write Storage Storage 21 24 read-write DBG_EBKP DBG_EBKP 0x340 -1 read-write n 0x0 0x0 EBKPT_OVF Expand breakpoint register overflow flag 8 9 read-write EBKP_COUNT Expand breakpoint register counter 0 5 read-write PCFGR SYSCFG_PCFGR 0x10 -1 read-write n 0x0 0x0 PWM1_SLEP_RUN PWM1 run control when the CPU enters Sleep0 0 1 read-write PWM2_SLEP_RUN PWM2 run control when the CPU enters Sleep0 1 2 read-write PWM3_SLEP_RUN PWM3 run control when the CPU enters Sleep0 2 3 read-write PWR_CR SYSCFG_PWR_CR 0x4 -1 read-write n 0x0 0x0 SYS_REGMOD_SLEP System regulator mode in sleep0 15 16 read-write Idle System regulator at idle mode when entry sleep0 0 Green System regulator at green mode when entry sleep0 1 RST_COMM_CR RST_COMM_CR 0x208 -1 read-write n 0x0 0x0 I2C_RST I2C reset bit 2 3 read-write UART_RST UART reset bit 0 1 read-write USART_RST USART reset bit 1 2 read-write RST_SYS_CS RST_SYS_CS 0x200 -1 read-write n 0x0 0x0 SW_RST Sofware reset 0 1 read-write RST_SYS_CSR RST_SYS_CSR 0x204 -1 read-write n 0x0 0x0 CHIPPT_RSTF CHIPPT reset flag 8 9 read-write IWDG_RSTF Watchdog reset flag 0 1 read-write LVR_RSTF LVR reset flag 4 5 read-write PIN_RSTF PIN reset flag 3 4 read-write POR_RSTF POR reset flag 2 3 read-write RMVF Remove reset flag 31 32 read-write SFT_RSTF Software reset flag 1 2 read-write SYSHOLD_CSR SYSHOLD_CSR 0xC -1 read-write n 0x0 0x0 SHSF System hold status flag 0 1 read-write TIMER1 Timer 1 TIMER 0x0 0x0 0x1000 registers n TIMER1 Timer 1 Interrupt 3 CTRL Control Register 0x0 -1 read-write n 0x0 0x0 ENABLE Enable 0 1 Disable Timer is disabled 0 Enable Timer is enabled 1 EXTCLK External Clock Enable 2 3 Disable External Clock s disabled 0 Enable External Clock is enabled 1 EXTIN External Input as Enable 1 2 Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 INTEN Interrupt Enable 3 4 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 INTCLEAR Timer Interrupt clear register TIMER1_INTSTATUS 0xC -1 write-only n 0x0 0x0 oneToClear INTSTATUS Timer Interrupt status register 0xC -1 read-only n 0x0 0x0 RELOAD Counter Reload Value 0x8 -1 read-write n 0x0 0x0 VALUE Current Timer Counter Value 0x4 -1 read-write n 0x0 0x0 TIMER2 Timer 2 TIMER 0x0 0x0 0x1000 registers n TIMER2 Timer 2 Interrupt 4 CTRL Control Register 0x0 -1 read-write n 0x0 0x0 ENABLE Enable 0 1 Disable Timer is disabled 0 Enable Timer is enabled 1 EXTCLK External Clock Enable 2 3 Disable External Clock s disabled 0 Enable External Clock is enabled 1 EXTIN External Input as Enable 1 2 Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 INTEN Interrupt Enable 3 4 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 INTCLEAR Timer Interrupt clear register TIMER2_INTSTATUS 0xC -1 write-only n 0x0 0x0 oneToClear INTSTATUS Timer Interrupt status register 0xC -1 read-only n 0x0 0x0 RELOAD Counter Reload Value 0x8 -1 read-write n 0x0 0x0 VALUE Current Timer Counter Value 0x4 -1 read-write n 0x0 0x0 TP TP TP 0x0 0x0 0x1000 registers n TK_IDLE Touch Key idle with scan 31 FFCR1 Find Finger Control Register 1 0x3C -1 read-write n 0x0 0x0 FFEN find finger function enable bit 15 16 read-write FF_FINISH Find finger algorithm finish flag, reset by software 13 14 read-write FF_high_low number of idle scan 12 13 read-write POINTNUM output value when surrounding points greater than 0 4 read-write XLEN length of X axis 8 12 read-write YLEN length of Y axis 4 8 read-write FFCR2 Find Finger Control Register 2 0x40 -1 read-write n 0x0 0x0 NEIGHBORGAP How much is greater than the surrounding points 10 16 read-write NOISEOFFSET noise offset value 0 10 read-write FFDIAR Find Finger Data Input Address Register 0x44 -1 read-write n 0x0 0x0 FFDIAR find finger data address input 0 7 read-write FFDOAR Find Finger Data Output Address Register 0x48 -1 read-write n 0x0 0x0 FFDOAR find finger data address output 0 7 read-write GAPH4DCCR Group A Discharge Current Control Register for phase4 0x10C -1 read-write n 0x0 0x0 GADC Group A Discharge Current Source select bits for phase4 0 5 read-write GBPH4DCCR Group B Discharge Current Control Register for phase4 0x20C -1 read-write n 0x0 0x0 GBDC Group B Discharge Current Source select bits for phase4 0 5 read-write GCPH4DCCR Group C Discharge Current Control Register for phase4 0x30C -1 read-write n 0x0 0x0 GCDC Group C Discharge Current Source select bits for phase4 0 5 read-write GDPH4DCCR Group D Discharge Current Control Register for phase4 0x40C -1 read-write n 0x0 0x0 GDDC Group D Discharge Current Source select bits for phase4 0 5 read-write GEPH4DCCR Group E Discharge Current Control Register for phase4 0x50C -1 read-write n 0x0 0x0 GEDC Group E Discharge Current Source select bits for phase4 0 5 read-write GFPH4DCCR Group F Discharge Current Control Register for phase4 0x60C -1 read-write n 0x0 0x0 GFDC Group F Discharge Current Source select bits for phase4 0 5 read-write SNCR Skip Number Control Register 0x4C -1 read-write n 0x0 0x0 SKIP_NUM Skip number of sample in begin period 0 8 read-write TKAB The Most Significant Byte of A Group Touch Key Buffer 0x110 -1 read-write n 0x0 0x0 TKA The Least Significant Byte of A Group Touch Key Buffer 0 16 read-write TKABDR TK Group A Bounce filter Invalid data recoup Register 0x138 -1 read-write n 0x0 0x0 TKABDR TK Bounce filter Invalid data recoup value set register 0 8 read-write TKABFL TK Group A Bounce Filter Lower limit Register 0x128 -1 read-write n 0x0 0x0 TABL The Bounce filter Lower limit set, below lower limit recoup TxBDR 0 16 read-write TKABFU TK Group A Bounce Filter Upper limit Register 0x124 -1 read-write n 0x0 0x0 TABU The Bounce filter Upper limit set, above upper limit recoup TxBDR 0 16 read-write TKABINR TK Group A Bounce filter Invalid number Register 0x134 -1 read-write n 0x0 0x0 TABINR TK Bounce filter Invalid number for Scan raw data 0 8 read-write TKACSGCR Touch Key of Group A Calculate Step and Gain Control Register 0x108 -1 read-write n 0x0 0x0 GADCS Group A Discharge Current Source select Bits 0 5 read-write GMAC GM gain Control for Group A 8 11 read-write TKAFB TK Group A Filter Buffer 0x120 -1 read-write n 0x0 0x0 TAFB The filter Buffer 0 16 read-write TKAFCR Touch Key of Group A Filter Control Register 0x11C -1 read-write n 0x0 0x0 TKABFEN TK bounce filter Enable bit 7 8 read-write TKADCE TK scan raw data Max./Min. catch Enable bit 1 2 read-write TKAHME TK Histogram mode Enable bit 2 3 read-write TKAHMR TK Group x Histogram mode value set Register 0x13C -1 read-write n 0x0 0x0 TAHMR TK Histogram mode value set register 0 16 read-write TKAKCR Touch Key Group A Loading Capacitor Calibration Control Register 0x104 -1 read-write n 0x0 0x0 TKAMC Touch Key Mutual Load capacitor Calibration Select Bits 8 12 read-write TKASC Touch Key Self Load capacitor Calibration Select Bits 0 4 read-write TKARMN TK Group A Scan raw data Min. Register 0x130 -1 read-write n 0x0 0x0 TARMN TK Scan raw data Min. value 0 16 read-write TKARMX TK Group x Scan raw data Max. Register 0x12C -1 read-write n 0x0 0x0 TARMX TK Scan raw data Max. value 0 16 read-write TKASCR Touch Key Group A Select Control Register 0x100 -1 read-write n 0x0 0x0 DRVA Group A Drive PIN control bit, only for Self type mode 6 7 read-write TKAEN Touch Key Group A Enable Bit 7 8 read-write TKASW Touch Key Group A pin Selected Bits 0 2 read-write TKAWB TK of Group A idle Scan Wakeup Base Register 0x114 -1 read-write n 0x0 0x0 TAWB TK group A idle scan wakeup base set bits 0 16 read-write TKAWR TK of Group A idle Scan Wakeup Range Register 0x118 -1 read-write n 0x0 0x0 TAWR TK group A idle scan wakeup range multiplicand set bits 0 16 read-write TKBB The Most Significant Byte of B Group Touch Key Buffer 0x210 -1 read-write n 0x0 0x0 TKB The Least Significant Byte of B Group Touch Key Buffer 0 16 read-write TKBBDR TK Group B Bounce filter Invalid data recoup Register 0x238 -1 read-write n 0x0 0x0 TKBBDR TK Bounce filter Invalid data recoup value set register 0 8 read-write TKBBFL TK Group B Bounce Filter Lower limit Register 0x228 -1 read-write n 0x0 0x0 TBBL The Bounce filter Lower limit set, below lower limit recoup TxBDR 0 16 read-write TKBBFU TK Group B Bounce Filter Upper limit Register 0x224 -1 read-write n 0x0 0x0 TBBU The Bounce filter Upper limit set, above upper limit recoup TxBDR 0 16 read-write TKBBINR TK Group B Bounce filter Invalid number Register 0x234 -1 read-write n 0x0 0x0 TBBINR TK Bounce filter Invalid number for Scan raw data 0 8 read-write TKBCSGCR Touch Key of Group B Calculate Step and Gain Control Register 0x208 -1 read-write n 0x0 0x0 GBDCS Group B Discharge Current Source select Bits 0 5 read-write GMBC GM gain Control for Group B 8 11 read-write TKBFB TK Group B Filter Buffer 0x220 -1 read-write n 0x0 0x0 TBFB The filter Buffer 0 16 read-write TKBFCR Touch Key of Group B Filter Control Register 0x21C -1 read-write n 0x0 0x0 TKBBFEN TK bounce filter Enable bit 7 8 read-write TKBDCE TK scan raw data Max./Min. catch Enable bit 1 2 read-write TKBHME TK Histogram mode Enable bit 2 3 read-write TKBHMR TK Group x Histogram mode value set Register 0x23C -1 read-write n 0x0 0x0 TBHMR TK Histogram mode value set register 0 16 read-write TKBKCR Touch Key Group B Loading Capacitor Calibration Control Register 0x204 -1 read-write n 0x0 0x0 TKBMC Touch Key Mutual Load capacitor Calibration Select Bits 8 12 read-write TKBSC Touch Key Self Load capacitor Calibration Select Bits 0 4 read-write TKBRMN TK Group B Scan raw data Min. Register 0x230 -1 read-write n 0x0 0x0 TBRMN TK Scan raw data Min. value 0 16 read-write TKBRMX TK Group x Scan raw data Max. Register 0x22C -1 read-write n 0x0 0x0 TBRMX TK Scan raw data Max. value 0 16 read-write TKBSCR Touch Key Group B Select Control Register 0x200 -1 read-write n 0x0 0x0 DRVB Group B Drive PIN control bit, only for Self type mode 6 7 read-write TKBEN Touch Key Group B Enable Bit 7 8 read-write TKBSW Touch Key Group B pin Selected Bits 0 2 read-write TKBWB TK of Group B idle Scan Wakeup Base Register 0x214 -1 read-write n 0x0 0x0 TBWB TK group B idle scan wakeup base set bits 0 16 read-write TKBWR TK of Group B idle Scan Wakeup Range Register 0x218 -1 read-write n 0x0 0x0 TBWR TK group B idle scan wakeup range multiplicand set bits 0 16 read-write TKCB The Most Significant Byte of C Group Touch Key Buffer 0x310 -1 read-write n 0x0 0x0 TKC The Least Significant Byte of C Group Touch Key Buffer 0 16 read-write TKCBDR TK Group C Bounce filter Invalid data recoup Register 0x338 -1 read-write n 0x0 0x0 TKCBDR TK Bounce filter Invalid data recoup value set register 0 8 read-write TKCBFL TK Group C Bounce Filter Lower limit Register 0x328 -1 read-write n 0x0 0x0 TCBL The Bounce filter Lower limit set, below lower limit recoup TxBDR 0 16 read-write TKCBFU TK Group C Bounce Filter Upper limit Register 0x324 -1 read-write n 0x0 0x0 TCBU The Bounce filter Upper limit set, above upper limit recoup TxBDR 0 16 read-write TKCBINR TK Group C Bounce filter Invalid number Register 0x334 -1 read-write n 0x0 0x0 TCBINR TK Bounce filter Invalid number for Scan raw data 0 8 read-write TKCCR Touch Key Calculate Cycle Register 0x14 -1 read-write n 0x0 0x0 TCCY Touch Key Calculate Cycle set bits 0 16 read-write TKCCSGCR Touch Key of Group C Calculate Step and Gain Control Register 0x308 -1 read-write n 0x0 0x0 GCDCS Group C Discharge Current Source select Bits 0 5 read-write GMCC GM gain Control for Group C 8 11 read-write TKCFB TK Group C Filter Buffer 0x320 -1 read-write n 0x0 0x0 TCFB The filter Buffer 0 16 read-write TKCFCR Touch Key of Group C Filter Control Register 0x31C -1 read-write n 0x0 0x0 TKCBFEN TK bounce filter Enable bit 7 8 read-write TKCDCE TK scan raw data Max./Min. catch Enable bit 1 2 read-write TKCHME TK Histogram mode Enable bit 2 3 read-write TKCHMR TK Group x Histogram mode value set Register 0x33C -1 read-write n 0x0 0x0 TCHMR TK Histogram mode value set register 0 16 read-write TKCKCR Touch Key Group C Loading Capacitor Calibration Control Register 0x304 -1 read-write n 0x0 0x0 TKCMC Touch Key Mutual Load capacitor Calibration Select Bits 8 12 read-write TKCSC Touch Key Self Load capacitor Calibration Select Bits 0 4 read-write TKCPC Touch Key Combine Pin Control Register 0x4 -1 read-write n 0x0 0x0 TKCE TKCE23 to TKCE0 0 24 read-write TKCR Touch Key Control Register 0x10 -1 read-write n 0x0 0x0 DCG Discharge current gain control 14 16 read-write ENCAL_MU Mutual calibration enable control bit 19 20 read-write ENCAL_SELF Self calibration enable control Bit 18 19 read-write LDOEN LDO Enable bit, if TK power source form VDD, this bit invalid 6 7 read-write PH4DCG Discharge current gain control for phase 4 12 14 read-write TKIAS TK Inactive pin function select 1 2 read-write TKL TK Self Loading Capacitor multiple set Bits 16 18 read-write TKLS Touch Key Loading capacitor Select Bits 8 10 read-write TKPSB TK power source select bit 5 6 read-write TPMS Touch Key Mode select bit 7 8 read-write TRVS TK Regulator Voltage level Select 2 4 read-write VTRK TK Regulator Voltage track enable bit, When TKPSB=0 action 0 1 read-write TKCRMN TK Group C Scan raw data Min. Register 0x330 -1 read-write n 0x0 0x0 TCRMN TK Scan raw data Min. value 0 16 read-write TKCRMX TK Group x Scan raw data Max. Register 0x32C -1 read-write n 0x0 0x0 TCRMX TK Scan raw data Max. value 0 16 read-write TKCSCR Touch Key Group C Select Control Register 0x300 -1 read-write n 0x0 0x0 DRVC Group C Drive PIN control bit, only for Self type mode 6 7 read-write TKCEN Touch Key Group C Enable Bit 7 8 read-write TKCSW Touch Key Group C pin Selected Bits 0 2 read-write TKCWB TK of Group C idle Scan Wakeup Base Register 0x314 -1 read-write n 0x0 0x0 TCWB TK group C idle scan wakeup base set bits 0 16 read-write TKCWR TK of Group C idle Scan Wakeup Range Register 0x318 -1 read-write n 0x0 0x0 TCWR TK group C idle scan wakeup range multiplicand set bits 0 16 read-write TKDB The Most Significant Byte of D Group Touch Key Buffer 0x410 -1 read-write n 0x0 0x0 TKD The Least Significant Byte of D Group Touch Key Buffer 0 16 read-write TKDBDR TK Group D Bounce filter Invalid data recoup Register 0x438 -1 read-write n 0x0 0x0 TKDBDR TK Bounce filter Invalid data recoup value set register 0 8 read-write TKDBFL TK Group D Bounce Filter Lower limit Register 0x428 -1 read-write n 0x0 0x0 TDBL The Bounce filter Lower limit set, below lower limit recoup TxBDR 0 16 read-write TKDBFU TK Group D Bounce Filter Upper limit Register 0x424 -1 read-write n 0x0 0x0 TDBU The Bounce filter Upper limit set, above upper limit recoup TxBDR 0 16 read-write TKDBINR TK Group D Bounce filter Invalid number Register 0x434 -1 read-write n 0x0 0x0 TDBINR TK Bounce filter Invalid number for Scan raw data 0 8 read-write TKDCR Touch Key Drive Control Register 0x8 -1 read-write n 0x0 0x0 TKCE TPDWO7 to TPDWO0 0 8 read-write TKDCSGCR Touch Key of Group D Calculate Step and Gain Control Register 0x408 -1 read-write n 0x0 0x0 GDDCS Group D Discharge Current Source select Bits 0 5 read-write GMDC GM gain Control for Group D 8 11 read-write TKDCSR TK Scan Raw Data Control Register 0x50 -1 read-write n 0x0 0x0 TKGS TK Groupp select Register for scan data output 0 3 read-write TKTRM TK Scan raw data move to RAM Enable bit 7 8 read-write TKDFB TK Group D Filter Buffer 0x420 -1 read-write n 0x0 0x0 TDFB The filter Buffer 0 16 read-write TKDFCR Touch Key of Group D Filter Control Register 0x41C -1 read-write n 0x0 0x0 TKDBFEN TK bounce filter Enable bit 7 8 read-write TKDDCE TK scan raw data Max./Min. catch Enable bit 1 2 read-write TKDHME TK Histogram mode Enable bit 2 3 read-write TKDHMR TK Group x Histogram mode value set Register 0x43C -1 read-write n 0x0 0x0 TDHMR TK Histogram mode value set register 0 16 read-write TKDKCR Touch Key Group D Loading Capacitor Calibration Control Register 0x404 -1 read-write n 0x0 0x0 TKDMC Touch Key Mutual Load capacitor Calibration Select Bits 8 12 read-write TKDSC Touch Key Self Load capacitor Calibration Select Bits 0 4 read-write TKDOAR TK Scan Raw Data Output Address Register 0x54 -1 read-write n 0x0 0x0 TKDOA TK Scan Raw Data Output Address 0 7 read-write TKDRMN TK Group D Scan raw data Min. Register 0x430 -1 read-write n 0x0 0x0 TDRMN TK Scan raw data Min. value 0 16 read-write TKDRMX TK Group x Scan raw data Max. Register 0x42C -1 read-write n 0x0 0x0 TDRMX TK Scan raw data Max. value 0 16 read-write TKDSCR Touch Key Group D Select Control Register 0x400 -1 read-write n 0x0 0x0 DRVD Group D Drive PIN control bit, only for Self type mode 6 7 read-write TKDEN Touch Key Group D Enable Bit 7 8 read-write TKDSW Touch Key Group D pin Selected Bits 0 2 read-write TKDWB TK of Group D idle Scan Wakeup Base Register 0x414 -1 read-write n 0x0 0x0 TDWB TK group D idle scan wakeup base set bits 0 16 read-write TKDWR TK of Group D idle Scan Wakeup Range Register 0x418 -1 read-write n 0x0 0x0 TDWR TK group D idle scan wakeup range multiplicand set bits 0 16 read-write TKEB The Most Significant Byte of E Group Touch Key Buffer 0x510 -1 read-write n 0x0 0x0 TKE The Least Significant Byte of E Group Touch Key Buffer 0 16 read-write TKEBDR TK Group E Bounce filter Invalid data recoup Register 0x538 -1 read-write n 0x0 0x0 TKEBDR TK Bounce filter Invalid data recoup value set register 0 8 read-write TKEBFL TK Group E Bounce Filter Lower limit Register 0x528 -1 read-write n 0x0 0x0 TEBL The Bounce filter Lower limit set, below lower limit recoup TxBDR 0 16 read-write TKEBFU TK Group E Bounce Filter Upper limit Register 0x524 -1 read-write n 0x0 0x0 TEBU The Bounce filter Upper limit set, above upper limit recoup TxBDR 0 16 read-write TKEBINR TK Group E Bounce filter Invalid number Register 0x534 -1 read-write n 0x0 0x0 TEBINR TK Bounce filter Invalid number for Scan raw data 0 8 read-write TKECSGCR Touch Key of Group E Calculate Step and Gain Control Register 0x508 -1 read-write n 0x0 0x0 GEDCS Group E Discharge Current Source select Bits 0 5 read-write GMEC GM gain Control for Group E 8 11 read-write TKEFB TK Group E Filter Buffer 0x520 -1 read-write n 0x0 0x0 TEFB The filter Buffer 0 16 read-write TKEFCR Touch Key of Group E Filter Control Register 0x51C -1 read-write n 0x0 0x0 TKEBFEN TK bounce filter Enable bit 7 8 read-write TKEDCE TK scan raw data Max./Min. catch Enable bit 1 2 read-write TKEHME TK Histogram mode Enable bit 2 3 read-write TKEHMR TK Group x Histogram mode value set Register 0x53C -1 read-write n 0x0 0x0 TEHMR TK Histogram mode value set register 0 16 read-write TKEKCR Touch Key Group E Loading Capacitor Calibration Control Register 0x504 -1 read-write n 0x0 0x0 TKEMC Touch Key Mutual Load capacitor Calibration Select Bits 8 12 read-write TKESC Touch Key Self Load capacitor Calibration Select Bits 0 4 read-write TKERMN TK Group E Scan raw data Min. Register 0x530 -1 read-write n 0x0 0x0 TERMN TK Scan raw data Min. value 0 16 read-write TKERMX TK Group x Scan raw data Max. Register 0x52C -1 read-write n 0x0 0x0 TERMX TK Scan raw data Max. value 0 16 read-write TKESCR Touch Key Group E Select Control Register 0x500 -1 read-write n 0x0 0x0 DRVE Group E Drive PIN control bit, only for Self type mode 6 7 read-write TKEEN Touch Key Group E Enable Bit 7 8 read-write TKESW Touch Key Group E pin Selected Bits 0 2 read-write TKEWB TK of Group E idle Scan Wakeup Base Register 0x514 -1 read-write n 0x0 0x0 TEWB TK group E idle scan wakeup base set bits 0 16 read-write TKEWR TK of Group E idle Scan Wakeup Range Register 0x518 -1 read-write n 0x0 0x0 TEWR TK group E idle scan wakeup range multiplicand set bits 0 16 read-write TKFB The Most Significant Byte of F Group Touch Key Buffer 0x610 -1 read-write n 0x0 0x0 TKF The Least Significant Byte of F Group Touch Key Buffer 0 16 read-write TKFBDR TK Group F Bounce filter Invalid data recoup Register 0x638 -1 read-write n 0x0 0x0 TKFBDR TK Bounce filter Invalid data recoup value set register 0 8 read-write TKFBFL TK Group F Bounce Filter Lower limit Register 0x628 -1 read-write n 0x0 0x0 TFBL The Bounce filter Lower limit set, below lower limit recoup TxBDR 0 16 read-write TKFBFU TK Group F Bounce Filter Upper limit Register 0x624 -1 read-write n 0x0 0x0 TFBU The Bounce filter Upper limit set, above upper limit recoup TxBDR 0 16 read-write TKFBINR TK Group F Bounce filter Invalid number Register 0x634 -1 read-write n 0x0 0x0 TFBINR TK Bounce filter Invalid number for Scan raw data 0 8 read-write TKFCSGCR Touch Key of Group F Calculate Step and Gain Control Register 0x608 -1 read-write n 0x0 0x0 GFDCS Group F Discharge Current Source select Bits 0 5 read-write GMFC GM gain Control for Group F 8 11 read-write TKFFB TK Group F Filter Buffer 0x620 -1 read-write n 0x0 0x0 TFFB The filter Buffer 0 16 read-write TKFFCR Touch Key of Group F Filter Control Register 0x61C -1 read-write n 0x0 0x0 TKFBFEN TK bounce filter Enable bit 7 8 read-write TKFDCE TK scan raw data Max./Min. catch Enable bit 1 2 read-write TKFHME TK Histogram mode Enable bit 2 3 read-write TKFHMR TK Group x Histogram mode value set Register 0x63C -1 read-write n 0x0 0x0 TFHMR TK Histogram mode value set register 0 16 read-write TKFKCR Touch Key Group F Loading Capacitor Calibration Control Register 0x604 -1 read-write n 0x0 0x0 TKFMC Touch Key Mutual Load capacitor Calibration Select Bits 8 12 read-write TKFSC Touch Key Self Load capacitor Calibration Select Bits 0 4 read-write TKFRMN TK Group F Scan raw data Min. Register 0x630 -1 read-write n 0x0 0x0 TFRMN TK Scan raw data Min. value 0 16 read-write TKFRMX TK Group x Scan raw data Max. Register 0x62C -1 read-write n 0x0 0x0 TFRMX TK Scan raw data Max. value 0 16 read-write TKFSCR Touch Key Group F Select Control Register 0x600 -1 read-write n 0x0 0x0 DRVF Group F Drive PIN control bit, only for Self type mode 6 7 read-write TKFEN Touch Key Group F Enable Bit 7 8 read-write TKFSW Touch Key Group F pin Selected Bits 0 2 read-write TKFWB TK of Group F idle Scan Wakeup Base Register 0x614 -1 read-write n 0x0 0x0 TFWB TK group F idle scan wakeup base set bits 0 16 read-write TKFWR TK of Group F idle Scan Wakeup Range Register 0x618 -1 read-write n 0x0 0x0 TFWR TK group F idle scan wakeup range multiplicand set bits 0 16 read-write TKITOR Touch Key idle scan time out counter Register 0x34 -1 read-write n 0x0 0x0 TKITO TK idle scan mode time out counter set bits 0 16 read-write TKNOSR Touch Key Phase1,2 Non-Overlap Width set Register 0x1C -1 read-write n 0x0 0x0 PH1OV PH1, PH2 non-overlap width set bits 0 16 read-write TKPC Touch Key Pin Control Register 0x0 -1 read-write n 0x0 0x0 TKEP TKEP23 to TKEP0 0 24 read-write TKPH1SR Touch Key Phase1 Width set Register 0x18 -1 read-write n 0x0 0x0 PH1S Phase1 width active set control bits 0 16 read-write TKPH2SR Touch Key Phase2 Width set Register 0x20 -1 read-write n 0x0 0x0 TPH2S Phase2 width active set control bits 0 16 read-write TKPH4LAT Touch Pad Phase 4 Latency time Set Register 0x2C -1 read-write n 0x0 0x0 P4LAT Phase 4 Latency width set buffer 0 8 read-write TKPH4SR Touch Key Phase 4 Width Set Register 0x28 -1 read-write n 0x0 0x0 PH4S Phase 4 active width set buffer 0 16 read-write TKSCR Touch Key idle Scan Control Register 0x30 -1 read-write n 0x0 0x0 TKISE TK idle with scan mode enable bit, for Low consumption application 16 17 read-write TKIWS TK idle with scan mode Wakeup Reference TK Buffer/Filter Buffer select bit 17 18 read-write TKST Touch Key idle scan time setting Bits 0 16 read-write TKSSR Touch Key Start and Status Register 0xC -1 read-write n 0x0 0x0 TKCSF Touch Key Compare status flag 3 4 read-write TKOESF Touch Key Counter Overflow Error status flag 1 2 read-write TKPESF Touch Key Phase 2 Error status flag 2 3 read-write TKS TK Conversion start bit 7 8 read-write TKSF Status flag for Touch Key Conversion 0 1 read-write TKTOSF Touch Key idle with scan mode time out status flag 4 5 read-write TKSWR Touch Key Sensing Window Register 0x24 -1 read-write n 0x0 0x0 TSW Touch Key Sensing Window clock set bits 0 16 read-write TKTCR1 TK Test Control Register 1 0xF04 -1 read-write n 0x0 0x0 MUCALMODE Calibration control 31 32 read-write OPT_IBD Bias control signal 27 28 read-write OPT_ICMP Comparator's current control 29 30 read-write PNEN Pesudo differential sensing enable bit of Mutual TP 30 31 read-write ROPTA GroupB Self option resistance select 0 2 read-write ROPTB GroupB Self option resistance select 2 4 read-write ROPTC GroupC Self option resistance select 4 6 read-write ROPTD GroupD Self option resistance select 6 8 read-write ROPTE GroupE Self option resistance select 8 10 read-write ROPTF GroupF Self option resistance select 10 12 read-write SFRGM TK test control signal default care 26 27 read-write TKIST Touch Key Idle with scan mode, Warm-up stable time setting 25 26 read-write VREF_S Comparator reference voltage selection bit 16 18 read-write VRSELF Self operating reference selection bit 24 25 read-write TKTCR2 TK Test Control Register 2 0xF08 -1 read-write n 0x0 0x0 PHCNTS PHCNT set 7 8 read-write TEST_CNT_EN AFEDO CNT EN 8 9 read-write TPDOS AFEDO fix vaule for test mode 9 10 read-write TPxWTEN TPx write enable 0 6 read-write TP_DEBUG_IO_EN enable TP debug signal to I/O 10 11 read-write TP_TST_CNT_GOAL test mode fix DO width 16 32 read-write TST_SEL select which tp test group delievr I/O 11 16 read-write TK_KEY TK Key for Test 0xF00 -1 read-write n 0x0 0x0 TK_KEY Enable write access to TPNCTRL,TKTCR register by writing 0x65CA 0 16 read-write UART UART UART 0x0 0x0 0x1000 registers n UART1_TX UART Transmit Interrupt 27 BAUDDIV Baudrate Divider 0x10 -1 read-write n 0x0 0x0 CTRL UART Control Register 0x8 -1 read-write n 0x0 0x0 HSTX High Speed Test Mode for TX only 6 7 Disable Disabled 0 Enable Enabled 1 RVOVINT RX Overrun Interrupt Enable 5 6 Disable Disabled 0 Enable Enabled 1 RXEN RX Enable 1 2 Disable Disabled 0 Enable Enabled 1 RXINT RX Interrupt Enable 3 4 Disable Disabled 0 Enable Enabled 1 TXEN TX Enable 0 1 Disable Disabled 0 Enable Enabled 1 TXINT TX Interrupt Enable 2 3 Disable Disabled 0 Enable Enabled 1 TXOVINT TX Overrun Interrupt Enable 4 5 Disable Disabled 0 Enable Enabled 1 DATA Recieve and Transmit Data Value 0x0 8 read-write n 0x0 0x0 INTCLEAR UART Interrupt CLEAR Register INTSTATUS 0xC -1 write-only n 0x0 0x0 RXINT RX Interrupt 1 2 oneToClear RXOV RX Overrun Interrupt 3 4 oneToClear TXINT TX Interrupt 0 1 oneToClear TXOV TX Overrun Interrupt 2 3 oneToClear INTSTATUS UART Interrupt Status Register 0xC -1 read-only n 0x0 0x0 RXINT RX Interrupt 1 2 RXOV RX Overrun Interrupt 3 4 TXINT TX Interrupt 0 1 TXOV TX Overrun Interrupt 2 3 STATE UART Status Register 0x4 -1 read-write n 0x0 0x0 RXBF RX Buffer Full 1 2 read-only RXOV RX Buffer Overrun (write 1 to clear) 3 4 read-write TXBF TX Buffer Full 0 1 read-only TXOV TX Buffer Overrun (write 1 to clear) 2 3 oneToClear USART USART USART 0x0 0x0 0x1000 registers n USART_TX USART Transmit Interrupt 20 USARTBR USART baud rate register 0x14 -1 read-only n 0x0 0x0 USARTCR1 USART control register 1 0x0 -1 read-write n 0x0 0x0 EVEN Select Parity Check Bit 5 6 read-write Odd Odd parity 0 Even Even Parity 1 PRE Enable Parity Addition Bit 4 5 read-write Disable Disabled 0 Enable Enabled 1 RXE Enable Receive Bit 0 1 read-write Disable Disabled 0 Enable Enabled 1 STOP Select Stop Bit 2 3 read-write 1 1 Stop bit 0 2 2 Stop bit 1 TXE Enable Transmission Bit 1 2 read-write Disable Disabled 0 Enable Enabled 1 UMODE USART mode select bit 7 8 read-write 8 8 Data bit 0 9 9 Data bit 1 URDG USART deglitch time select bits 9 11 read-write 00 50ns 0 01 200ns 1 10 400ns 2 11 Bypass 3 URINVEN Enable UART TXD and RXD Port Inverse Output Bit 8 9 read-write Disable Disabled 0 Enable Enabled 1 USARTCR2 USART control register 2 0x4 -1 read-write n 0x0 0x0 CLKEN Clock enable 3 4 read-write Disable Disabled 0 Enable Enabled 1 CPHA Clock phase. 1 2 read-write middle USART_CK toggle starts at the middle of first data bit 0 beginning USART_CK toggle starts at the beginning of first data bit. 1 CPOL Clock polarity 2 3 read-write low UASRT_CK active low 0 high UASRT_CK active high 1 EIE Error interrupt enable (Overrun, Frame, Noise) 4 5 read-write Disable Disabled 0 Enable Enabled 1 PEIE Parity error interrupt enable 5 6 read-write Disable Disabled 0 Enable Enabled 1 RBFIE Receiver buffer full interrupt enable 7 8 read-write Disable Disabled 0 Enable Enabled 1 TBIE Transfer buffer empty interrupt enable 9 10 read-write Disable Disabled 0 Enable Enabled 1 TSFIE Transmit interrupt enable 8 9 read-write Disable Disabled 0 Enable Enabled 1 USARTSR USART status register 0x8 -1 read-only n 0x0 0x0 FMERR Framing Error Flag. 1 2 NERR Noise Error Flag. 0 1 OVERR Running Error Flag. 2 3 PERR Parity Error Flag. 3 4 RBF USART Read Buffer Full Flag. 5 6 TBE USART Transfer Buffer Empty Flag. 7 8 TSF USART transmit status Flag. 6 7 USARTTD USART transmit data buffer register USARTTD 0xC -1 read-only n 0x0 0x0