Espressif
esp8266
2024.04.23
esp8266
Xtensa LX106
1
little
true
3
false
32
DPORT
DPORT
0x0
0x0
0x40
registers
n
CTL
DPORT_CTL
0x14
32
read-write
n
0x0
0x0
DPORT_CTL_DOUBLE_CLK
0
1
read-write
EDGE_INT_ENABLE
EDGE_INT_ENABLE
0x4
32
read-write
n
0x0
0x0
Register
0
32
read-write
timer1_edge_int_enable
Enable the timer1 edge interrupt
1
1
wdt_edge_int_enable
Enable the watchdog timer edge interrupt
0
1
EFUSE
EFUSE
0x0
0x0
0x2C
registers
n
DATA0
EFUSE_DATA0
0x0
32
read-write
n
0x0
0x0
Register
0
32
read-write
DATA1
EFUSE_DATA1
0x4
32
read-write
n
0x0
0x0
Register
0
32
read-write
DATA2
EFUSE_DATA2
0x8
32
read-write
n
0x0
0x0
Register
0
32
read-write
DATA3
EFUSE_DATA3
0xC
32
read-write
n
0x0
0x0
Register
0
32
read-write
GPIO
GPIO
0x0
0x0
0x3A0
registers
n
ENABLE
GPIO_ENABLE
0xC
32
read-write
n
0x0
0x0
GPIO_ENABLE_DATA
The output enable register.
0
16
read-write
GPIO_SDIO_SEL
SDIO-dis selection register
16
6
read-write
ENABLE_W1TC
GPIO_ENABLE_W1TC
0x14
32
read-write
n
0x0
0x0
GPIO_ENABLE_DATA_W1TC
Writing 1 into a bit in this register will clear the related bit in GPIO_ENABLE_DATA
0
16
write-only
ENABLE_W1TS
GPIO_ENABLE_W1TS
0x10
32
read-write
n
0x0
0x0
GPIO_ENABLE_DATA_W1TS
Writing 1 into a bit in this register will set the related bit in GPIO_ENABLE_DATA
0
16
write-only
IN
The values of the strapping pins.
0x18
32
read-write
n
0x0
0x0
GPIO_IN_DATA
The values of the GPIO pins when the GPIO pin is set as input.
0
16
read-write
GPIO_STRAPPING
The values of the strapping pins.
16
16
read-write
OUT
BT-Coexist Selection register
0x0
32
read-write
n
0x0
0x0
GPIO_BT_SEL
BT-Coexist Selection register
16
16
read-write
GPIO_OUT_DATA
The output value when the GPIO pin is set as output.
0
16
read-write
OUT_W1TC
GPIO_OUT_W1TC
0x8
32
read-write
n
0x0
0x0
GPIO_OUT_DATA_W1TC
Writing 1 into a bit in this register will clear the related bit in GPIO_OUT_DATA
0
16
write-only
OUT_W1TS
GPIO_OUT_W1TS
0x4
32
read-write
n
0x0
0x0
GPIO_OUT_DATA_W1TS
Writing 1 into a bit in this register will set the related bit in GPIO_OUT_DATA
0
16
write-only
PIN0
GPIO_PIN0
0x28
32
read-write
n
0x0
0x0
GPIO_PIN0_DRIVER
1: open drain; 0: normal
2
1
read-write
GPIO_PIN0_DRIVER
read-write
open_drain
open drain
0
normal
normal
1
GPIO_PIN0_INT_TYPE
0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level
7
3
read-write
GPIO_PIN0_INT_TYPE
read-write
disabled
interrupt is disabled
0
positive_edge
interrupt is triggered on the positive edge
1
negative_edge
interrupt is triggered on the negative edge
2
both_edges
interrupt is triggered on both edges
3
low_level
interrupt is triggered on the low level
4
high_level
interrupt is triggered on the high level
5
GPIO_PIN0_SOURCE
1: sigma-delta; 0: GPIO_DATA
0
1
read-write
GPIO_PIN0_SOURCE
read-write
sigma_delta
sigma-delta
0
gpio_data
gpio data
1
GPIO_PIN0_WAKEUP_ENABLE
0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5
10
1
read-write
PIN1
GPIO_PIN1
0x2C
32
read-write
n
0x0
0x0
GPIO_PIN1_DRIVER
1: open drain; 0: normal
2
1
read-write
GPIO_PIN1_DRIVER
read-write
open_drain
open drain
0
normal
normal
1
GPIO_PIN1_INT_TYPE
0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level
7
3
read-write
GPIO_PIN1_INT_TYPE
read-write
disabled
interrupt is disabled
0
positive_edge
interrupt is triggered on the positive edge
1
negative_edge
interrupt is triggered on the negative edge
2
both_edges
interrupt is triggered on both edges
3
low_level
interrupt is triggered on the low level
4
high_level
interrupt is triggered on the high level
5
GPIO_PIN1_SOURCE
1: sigma-delta; 0: GPIO_DATA
0
1
read-write
GPIO_PIN1_SOURCE
read-write
sigma_delta
sigma-delta
0
gpio_data
gpio data
1
GPIO_PIN1_WAKEUP_ENABLE
0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5
10
1
read-write
PIN10
GPIO_PIN10
0x50
32
read-write
n
0x0
0x0
GPIO_PIN10_DRIVER
1: open drain; 0: normal
2
1
read-write
GPIO_PIN10_DRIVER
read-write
open_drain
open drain
0
normal
normal
1
GPIO_PIN10_INT_TYPE
0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level
7
3
read-write
GPIO_PIN10_INT_TYPE
read-write
disabled
interrupt is disabled
0
positive_edge
interrupt is triggered on the positive edge
1
negative_edge
interrupt is triggered on the negative edge
2
both_edges
interrupt is triggered on both edges
3
low_level
interrupt is triggered on the low level
4
high_level
interrupt is triggered on the high level
5
GPIO_PIN10_SOURCE
1: sigma-delta; 0: GPIO_DATA
0
1
read-write
GPIO_PIN10_SOURCE
read-write
sigma_delta
sigma-delta
0
gpio_data
gpio data
1
GPIO_PIN10_WAKEUP_ENABLE
0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5
10
1
read-write
PIN11
GPIO_PIN11
0x54
32
read-write
n
0x0
0x0
GPIO_PIN11_DRIVER
1: open drain; 0: normal
2
1
read-write
GPIO_PIN11_DRIVER
read-write
open_drain
open drain
0
normal
normal
1
GPIO_PIN11_INT_TYPE
0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level
7
3
read-write
GPIO_PIN11_INT_TYPE
read-write
disabled
interrupt is disabled
0
positive_edge
interrupt is triggered on the positive edge
1
negative_edge
interrupt is triggered on the negative edge
2
both_edges
interrupt is triggered on both edges
3
low_level
interrupt is triggered on the low level
4
high_level
interrupt is triggered on the high level
5
GPIO_PIN11_SOURCE
1: sigma-delta; 0: GPIO_DATA
0
1
read-write
GPIO_PIN11_SOURCE
read-write
sigma_delta
sigma-delta
0
gpio_data
gpio data
1
GPIO_PIN11_WAKEUP_ENABLE
0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5
10
1
read-write
PIN12
GPIO_PIN12
0x58
32
read-write
n
0x0
0x0
GPIO_PIN12_DRIVER
1: open drain; 0: normal
2
1
read-write
GPIO_PIN12_DRIVER
read-write
open_drain
open drain
0
normal
normal
1
GPIO_PIN12_INT_TYPE
0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level
7
3
read-write
GPIO_PIN12_INT_TYPE
read-write
disabled
interrupt is disabled
0
positive_edge
interrupt is triggered on the positive edge
1
negative_edge
interrupt is triggered on the negative edge
2
both_edges
interrupt is triggered on both edges
3
low_level
interrupt is triggered on the low level
4
high_level
interrupt is triggered on the high level
5
GPIO_PIN12_SOURCE
1: sigma-delta; 0: GPIO_DATA
0
1
read-write
GPIO_PIN12_SOURCE
read-write
sigma_delta
sigma-delta
0
gpio_data
gpio data
1
GPIO_PIN12_WAKEUP_ENABLE
0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5
10
1
read-write
PIN13
GPIO_PIN13
0x5C
32
read-write
n
0x0
0x0
GPIO_PIN13_DRIVER
1: open drain; 0: normal
2
1
read-write
GPIO_PIN13_DRIVER
read-write
open_drain
open drain
0
normal
normal
1
GPIO_PIN13_INT_TYPE
0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level
7
3
read-write
GPIO_PIN13_INT_TYPE
read-write
disabled
interrupt is disabled
0
positive_edge
interrupt is triggered on the positive edge
1
negative_edge
interrupt is triggered on the negative edge
2
both_edges
interrupt is triggered on both edges
3
low_level
interrupt is triggered on the low level
4
high_level
interrupt is triggered on the high level
5
GPIO_PIN13_SOURCE
1: sigma-delta; 0: GPIO_DATA
0
1
read-write
GPIO_PIN13_SOURCE
read-write
sigma_delta
sigma-delta
0
gpio_data
gpio data
1
GPIO_PIN13_WAKEUP_ENABLE
0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5
10
1
read-write
PIN14
GPIO_PIN14
0x60
32
read-write
n
0x0
0x0
GPIO_PIN14_DRIVER
1: open drain; 0: normal
2
1
read-write
GPIO_PIN14_DRIVER
read-write
open_drain
open drain
0
normal
normal
1
GPIO_PIN14_INT_TYPE
0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level
7
3
read-write
GPIO_PIN14_INT_TYPE
read-write
disabled
interrupt is disabled
0
positive_edge
interrupt is triggered on the positive edge
1
negative_edge
interrupt is triggered on the negative edge
2
both_edges
interrupt is triggered on both edges
3
low_level
interrupt is triggered on the low level
4
high_level
interrupt is triggered on the high level
5
GPIO_PIN14_SOURCE
1: sigma-delta; 0: GPIO_DATA
0
1
read-write
GPIO_PIN14_SOURCE
read-write
sigma_delta
sigma-delta
0
gpio_data
gpio data
1
GPIO_PIN14_WAKEUP_ENABLE
0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5
10
1
read-write
PIN15
GPIO_PIN15
0x64
32
read-write
n
0x0
0x0
GPIO_PIN15_DRIVER
1: open drain; 0: normal
2
1
read-write
GPIO_PIN15_DRIVER
read-write
open_drain
open drain
0
normal
normal
1
GPIO_PIN15_INT_TYPE
0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level
7
3
read-write
GPIO_PIN15_INT_TYPE
read-write
disabled
interrupt is disabled
0
positive_edge
interrupt is triggered on the positive edge
1
negative_edge
interrupt is triggered on the negative edge
2
both_edges
interrupt is triggered on both edges
3
low_level
interrupt is triggered on the low level
4
high_level
interrupt is triggered on the high level
5
GPIO_PIN15_SOURCE
1: sigma-delta; 0: GPIO_DATA
0
1
read-write
GPIO_PIN15_SOURCE
read-write
sigma_delta
sigma-delta
0
gpio_data
gpio data
1
GPIO_PIN15_WAKEUP_ENABLE
0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5
10
1
read-write
PIN2
GPIO_PIN2
0x30
32
read-write
n
0x0
0x0
GPIO_PIN2_DRIVER
1: open drain; 0: normal
2
1
read-write
GPIO_PIN2_DRIVER
read-write
open_drain
open drain
0
normal
normal
1
GPIO_PIN2_INT_TYPE
0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level
7
3
read-write
GPIO_PIN2_INT_TYPE
read-write
disabled
interrupt is disabled
0
positive_edge
interrupt is triggered on the positive edge
1
negative_edge
interrupt is triggered on the negative edge
2
both_edges
interrupt is triggered on both edges
3
low_level
interrupt is triggered on the low level
4
high_level
interrupt is triggered on the high level
5
GPIO_PIN2_SOURCE
1: sigma-delta; 0: GPIO_DATA
0
1
read-write
GPIO_PIN2_SOURCE
read-write
sigma_delta
sigma-delta
0
gpio_data
gpio data
1
GPIO_PIN2_WAKEUP_ENABLE
0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5
10
1
read-write
PIN3
GPIO_PIN3
0x34
32
read-write
n
0x0
0x0
GPIO_PIN3_DRIVER
1: open drain; 0: normal
2
1
read-write
GPIO_PIN3_DRIVER
read-write
open_drain
open drain
0
normal
normal
1
GPIO_PIN3_INT_TYPE
0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level
7
3
read-write
GPIO_PIN3_INT_TYPE
read-write
disabled
interrupt is disabled
0
positive_edge
interrupt is triggered on the positive edge
1
negative_edge
interrupt is triggered on the negative edge
2
both_edges
interrupt is triggered on both edges
3
low_level
interrupt is triggered on the low level
4
high_level
interrupt is triggered on the high level
5
GPIO_PIN3_SOURCE
1: sigma-delta; 0: GPIO_DATA
0
1
read-write
GPIO_PIN3_SOURCE
read-write
sigma_delta
sigma-delta
0
gpio_data
gpio data
1
GPIO_PIN3_WAKEUP_ENABLE
0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5
10
1
read-write
PIN4
GPIO_PIN4
0x38
32
read-write
n
0x0
0x0
GPIO_PIN4_DRIVER
1: open drain; 0: normal
2
1
read-write
GPIO_PIN4_DRIVER
read-write
open_drain
open drain
0
normal
normal
1
GPIO_PIN4_INT_TYPE
0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level
7
3
read-write
GPIO_PIN4_INT_TYPE
read-write
disabled
interrupt is disabled
0
positive_edge
interrupt is triggered on the positive edge
1
negative_edge
interrupt is triggered on the negative edge
2
both_edges
interrupt is triggered on both edges
3
low_level
interrupt is triggered on the low level
4
high_level
interrupt is triggered on the high level
5
GPIO_PIN4_SOURCE
1: sigma-delta; 0: GPIO_DATA
0
1
read-write
GPIO_PIN4_SOURCE
read-write
sigma_delta
sigma-delta
0
gpio_data
gpio data
1
GPIO_PIN4_WAKEUP_ENABLE
0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5
10
1
read-write
PIN5
GPIO_PIN5
0x3C
32
read-write
n
0x0
0x0
GPIO_PIN5_DRIVER
1: open drain; 0: normal
2
1
read-write
GPIO_PIN5_DRIVER
read-write
open_drain
open drain
0
normal
normal
1
GPIO_PIN5_INT_TYPE
0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level
7
3
read-write
GPIO_PIN5_INT_TYPE
read-write
disabled
interrupt is disabled
0
positive_edge
interrupt is triggered on the positive edge
1
negative_edge
interrupt is triggered on the negative edge
2
both_edges
interrupt is triggered on both edges
3
low_level
interrupt is triggered on the low level
4
high_level
interrupt is triggered on the high level
5
GPIO_PIN5_SOURCE
1: sigma-delta; 0: GPIO_DATA
0
1
read-write
GPIO_PIN5_SOURCE
read-write
sigma_delta
sigma-delta
0
gpio_data
gpio data
1
GPIO_PIN5_WAKEUP_ENABLE
0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5
10
1
read-write
PIN6
GPIO_PIN6
0x40
32
read-write
n
0x0
0x0
GPIO_PIN6_DRIVER
1: open drain; 0: normal
2
1
read-write
GPIO_PIN6_DRIVER
read-write
open_drain
open drain
0
normal
normal
1
GPIO_PIN6_INT_TYPE
0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level
7
3
read-write
GPIO_PIN6_INT_TYPE
read-write
disabled
interrupt is disabled
0
positive_edge
interrupt is triggered on the positive edge
1
negative_edge
interrupt is triggered on the negative edge
2
both_edges
interrupt is triggered on both edges
3
low_level
interrupt is triggered on the low level
4
high_level
interrupt is triggered on the high level
5
GPIO_PIN6_SOURCE
1: sigma-delta; 0: GPIO_DATA
0
1
read-write
GPIO_PIN6_SOURCE
read-write
sigma_delta
sigma-delta
0
gpio_data
gpio data
1
GPIO_PIN6_WAKEUP_ENABLE
0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5
10
1
read-write
PIN7
GPIO_PIN7
0x44
32
read-write
n
0x0
0x0
GPIO_PIN7_DRIVER
1: open drain; 0: normal
2
1
read-write
GPIO_PIN7_DRIVER
read-write
open_drain
open drain
0
normal
normal
1
GPIO_PIN7_INT_TYPE
0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level
7
3
read-write
GPIO_PIN7_INT_TYPE
read-write
disabled
interrupt is disabled
0
positive_edge
interrupt is triggered on the positive edge
1
negative_edge
interrupt is triggered on the negative edge
2
both_edges
interrupt is triggered on both edges
3
low_level
interrupt is triggered on the low level
4
high_level
interrupt is triggered on the high level
5
GPIO_PIN7_SOURCE
1: sigma-delta; 0: GPIO_DATA
0
1
read-write
GPIO_PIN7_SOURCE
read-write
sigma_delta
sigma-delta
0
gpio_data
gpio data
1
GPIO_PIN7_WAKEUP_ENABLE
0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5
10
1
read-write
PIN8
GPIO_PIN8
0x48
32
read-write
n
0x0
0x0
GPIO_PIN8_DRIVER
1: open drain; 0: normal
2
1
read-write
GPIO_PIN8_DRIVER
read-write
open_drain
open drain
0
normal
normal
1
GPIO_PIN8_INT_TYPE
0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level
7
3
read-write
GPIO_PIN8_INT_TYPE
read-write
disabled
interrupt is disabled
0
positive_edge
interrupt is triggered on the positive edge
1
negative_edge
interrupt is triggered on the negative edge
2
both_edges
interrupt is triggered on both edges
3
low_level
interrupt is triggered on the low level
4
high_level
interrupt is triggered on the high level
5
GPIO_PIN8_SOURCE
1: sigma-delta; 0: GPIO_DATA
0
1
read-write
GPIO_PIN8_SOURCE
read-write
sigma_delta
sigma-delta
0
gpio_data
gpio data
1
GPIO_PIN8_WAKEUP_ENABLE
0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5
10
1
read-write
PIN9
GPIO_PIN9
0x4C
32
read-write
n
0x0
0x0
GPIO_PIN9_DRIVER
1: open drain; 0: normal
2
1
read-write
GPIO_PIN9_DRIVER
read-write
open_drain
open drain
0
normal
normal
1
GPIO_PIN9_INT_TYPE
0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level
7
3
read-write
GPIO_PIN9_INT_TYPE
read-write
disabled
interrupt is disabled
0
positive_edge
interrupt is triggered on the positive edge
1
negative_edge
interrupt is triggered on the negative edge
2
both_edges
interrupt is triggered on both edges
3
low_level
interrupt is triggered on the low level
4
high_level
interrupt is triggered on the high level
5
GPIO_PIN9_SOURCE
1: sigma-delta; 0: GPIO_DATA
0
1
read-write
GPIO_PIN9_SOURCE
read-write
sigma_delta
sigma-delta
0
gpio_data
gpio data
1
GPIO_PIN9_WAKEUP_ENABLE
0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5
10
1
read-write
RTC_CALIB_SYNC
Positvie edge of this bit will trigger the RTC-clock-calibration process.
0x6C
32
read-write
n
0x0
0x0
RTC_CALIB_START
Positvie edge of this bit will trigger the RTC-clock-calibration process.
31
1
read-write
RTC_PERIOD_NUM
The cycle number of RTC-clock during RTC-clock-calibration
0
10
read-write
RTC_CALIB_VALUE
0: during RTC-clock-calibration; 1: RTC-clock-calibration is done
0x70
32
read-write
n
0x0
0x0
RTC_CALIB_RDY
0: during RTC-clock-calibration; 1: RTC-clock-calibration is done
31
1
read-write
RTC_CALIB_RDY_REAL
0: during RTC-clock-calibration; 1: RTC-clock-calibration is done
30
1
read-write
RTC_CALIB_VALUE
The cycle number of clk_xtal (crystal clock) for the RTC_PERIOD_NUM cycles of RTC-clock
0
20
read-write
SIGMA_DELTA
GPIO_SIGMA_DELTA
0x68
32
read-write
n
0x0
0x0
SIGMA_DELTA_ENABLE
1: enable sigma-delta; 0: disable
16
1
read-write
SIGMA_DELTA_PRESCALAR
Clock pre-divider for sigma-delta.
8
8
read-write
SIGMA_DELTA_TARGET
target level of the sigma-delta. It is a signed byte.
0
8
read-write
STATUS
GPIO_STATUS
0x1C
32
read-write
n
0x0
0x0
GPIO_STATUS_INTERRUPT
Interrupt enable register.
0
16
read-write
STATUS_W1TC
GPIO_STATUS_W1TC
0x24
32
read-write
n
0x0
0x0
GPIO_STATUS_INTERRUPT_W1TC
Writing 1 into a bit in this register will clear the related bit in GPIO_STATUS_INTERRUPT
0
16
write-only
STATUS_W1TS
GPIO_STATUS_W1TS
0x20
32
read-write
n
0x0
0x0
GPIO_STATUS_INTERRUPT_W1TS
Writing 1 into a bit in this register will set the related bit in GPIO_STATUS_INTERRUPT
0
16
write-only
I2S
I2S
0x0
0x0
0x160
registers
n
FIFO_CONF
I2S_FIFO_CONF
0x20
32
read-write
n
0x0
0x0
I2S_I2S_DSCR_EN
12
1
read-write
I2S_I2S_RX_DATA_NUM
0
6
read-write
I2S_I2S_RX_FIFO_MOD
16
3
read-write
I2S_I2S_TX_DATA_NUM
6
6
read-write
I2S_I2S_TX_FIFO_MOD
13
3
read-write
I2SCONF
I2SCONF
0x8
32
read-write
n
0x0
0x0
I2S_BCK_DIV_NUM
22
6
read-write
I2S_BITS_MOD
12
4
read-write
I2S_CLKM_DIV_NUM
16
6
read-write
I2S_I2S_RX_FIFO_RESET
3
1
read-write
I2S_I2S_RX_RESET
1
1
read-write
I2S_I2S_RX_START
9
1
read-write
I2S_I2S_TX_FIFO_RESET
2
1
read-write
I2S_I2S_TX_RESET
0
1
read-write
I2S_I2S_TX_START
8
1
read-write
I2S_MSB_RIGHT
7
1
read-write
I2S_RECE_MSB_SHIFT
11
1
read-write
I2S_RECE_SLAVE_MOD
5
1
read-write
I2S_RIGHT_FIRST
6
1
read-write
I2S_TRANS_MSB_SHIFT
10
1
read-write
I2S_TRANS_SLAVE_MOD
4
1
read-write
I2SCONF_SIGLE_DATA
I2SCONF_SIGLE_DATA
0x28
32
read-write
n
0x0
0x0
I2S_I2S_SIGLE_DATA
0
32
read-write
I2SINT_CLR
I2SINT_CLR
0x18
32
read-write
n
0x0
0x0
I2S_I2S_PUT_DATA_INT_CLR
1
1
read-write
I2S_I2S_RX_REMPTY_INT_CLR
3
1
read-write
I2S_I2S_RX_WFULL_INT_CLR
2
1
read-write
I2S_I2S_TAKE_DATA_INT_CLR
0
1
read-write
I2S_I2S_TX_REMPTY_INT_CLR
5
1
read-write
I2S_I2S_TX_WFULL_INT_CLR
4
1
read-write
I2SINT_ENA
I2SINT_ENA
0x14
32
read-write
n
0x0
0x0
I2S_I2S_RX_REMPTY_INT_ENA
3
1
read-write
I2S_I2S_RX_TAKE_DATA_INT_ENA
0
1
read-write
I2S_I2S_RX_WFULL_INT_ENA
2
1
read-write
I2S_I2S_TX_PUT_DATA_INT_ENA
1
1
read-write
I2S_I2S_TX_REMPTY_INT_ENA
5
1
read-write
I2S_I2S_TX_WFULL_INT_ENA
4
1
read-write
I2SINT_RAW
I2SINT_RAW
0xC
32
read-write
n
0x0
0x0
I2S_I2S_RX_REMPTY_INT_RAW
3
1
read-write
I2S_I2S_RX_TAKE_DATA_INT_RAW
0
1
read-write
I2S_I2S_RX_WFULL_INT_RAW
2
1
read-write
I2S_I2S_TX_PUT_DATA_INT_RAW
1
1
read-write
I2S_I2S_TX_REMPTY_INT_RAW
5
1
read-write
I2S_I2S_TX_WFULL_INT_RAW
4
1
read-write
I2SINT_ST
I2SINT_ST
0x10
32
read-write
n
0x0
0x0
I2S_I2S_RX_REMPTY_INT_ST
3
1
read-write
I2S_I2S_RX_TAKE_DATA_INT_ST
0
1
read-write
I2S_I2S_RX_WFULL_INT_ST
2
1
read-write
I2S_I2S_TX_PUT_DATA_INT_ST
1
1
read-write
I2S_I2S_TX_REMPTY_INT_ST
5
1
read-write
I2S_I2S_TX_WFULL_INT_ST
4
1
read-write
I2SRXEOF_NUM
I2SRXEOF_NUM
0x24
32
read-write
n
0x0
0x0
I2S_I2S_RX_EOF_NUM
0
32
read-write
I2SRXFIFO
I2SRXFIFO
0x4
32
read-write
n
0x0
0x0
Register
0
32
read-write
I2STIMING
I2STIMING
0x1C
32
read-write
n
0x0
0x0
I2S_RECE_BCK_IN_DELAY
4
2
read-write
I2S_RECE_BCK_OUT_DELAY
18
2
read-write
I2S_RECE_DSYNC_SW
21
1
read-write
I2S_RECE_SD_IN_DELAY
8
2
read-write
I2S_RECE_WS_IN_DELAY
6
2
read-write
I2S_RECE_WS_OUT_DELAY
16
2
read-write
I2S_TRANS_BCK_IN_DELAY
0
2
read-write
I2S_TRANS_BCK_IN_INV
22
1
read-write
I2S_TRANS_BCK_OUT_DELAY
10
2
read-write
I2S_TRANS_DSYNC_SW
20
1
read-write
I2S_TRANS_SD_OUT_DELAY
14
2
read-write
I2S_TRANS_WS_IN_DELAY
2
2
read-write
I2S_TRANS_WS_OUT_DELAY
12
2
read-write
I2STXFIFO
I2STXFIFO
0x0
32
read-write
n
0x0
0x0
Register
0
32
read-write
IO_MUX
IO_MUX
0x0
0x0
0x220
registers
n
CONF
IO_MUX_CONF
0x0
32
read-write
n
0x0
0x0
SPI0_CLK_EQU_SYS_CLK
8
1
read-write
SPI1_CLK_EQU_SYS_CLK
9
1
read-write
GPIO0
IO_MUX_GPIO0
0x34
32
read-write
n
0x0
0x0
FUNCTION_SELECT_HIGH_BIT
configures IO_MUX function, upper bit
8
1
FUNCTION_SELECT_LOW_BITS
configures IO_MUX function, bottom 2 bits
4
2
PULLUP
configures pull up
7
1
Register
0
32
read-write
SLEEP_ENABLE
configures output enable during sleep mode
0
1
SLEEP_PULLUP
configures pull up during sleep mode
3
1
GPIO2
IO_MUX_GPIO2
0x38
32
read-write
n
0x0
0x0
FUNCTION_SELECT_HIGH_BIT
configures IO_MUX function, upper bit
8
1
FUNCTION_SELECT_LOW_BITS
configures IO_MUX function, bottom 2 bits
4
2
PULLUP
configures pull up
7
1
Register
0
32
read-write
SLEEP_ENABLE
configures output enable during sleep mode
0
1
SLEEP_PULLUP
configures pull up during sleep mode
3
1
GPIO4
IO_MUX_GPIO4
0x3C
32
read-write
n
0x0
0x0
FUNCTION_SELECT_HIGH_BIT
configures IO_MUX function, upper bit
8
1
FUNCTION_SELECT_LOW_BITS
configures IO_MUX function, bottom 2 bits
4
2
PULLUP
configures pull up
7
1
Register
0
32
read-write
SLEEP_ENABLE
configures output enable during sleep mode
0
1
SLEEP_PULLUP
configures pull up during sleep mode
3
1
GPIO5
IO_MUX_GPIO5
0x40
32
read-write
n
0x0
0x0
FUNCTION_SELECT_HIGH_BIT
configures IO_MUX function, upper bit
8
1
FUNCTION_SELECT_LOW_BITS
configures IO_MUX function, bottom 2 bits
4
2
PULLUP
configures pull up
7
1
Register
0
32
read-write
SLEEP_ENABLE
configures output enable during sleep mode
0
1
SLEEP_PULLUP
configures pull up during sleep mode
3
1
MTCK
IO_MUX_MTCK
0x8
32
read-write
n
0x0
0x0
FUNCTION_SELECT_HIGH_BIT
configures IO_MUX function, upper bit
8
1
FUNCTION_SELECT_LOW_BITS
configures IO_MUX function, bottom 2 bits
4
2
PULLUP
configures pull up
7
1
Register
0
32
read-write
SLEEP_ENABLE
configures output enable during sleep mode
0
1
SLEEP_PULLUP
configures pull up during sleep mode
3
1
MTDI
IO_MUX_MTDI
0x4
32
read-write
n
0x0
0x0
FUNCTION_SELECT_HIGH_BIT
configures IO_MUX function, upper bit
8
1
FUNCTION_SELECT_LOW_BITS
configures IO_MUX function, bottom 2 bits
4
2
PULLUP
configures pull up
7
1
Register
0
32
read-write
SLEEP_ENABLE
configures output enable during sleep mode
0
1
SLEEP_PULLUP
configures pull up during sleep mode
3
1
MTDO
IO_MUX_MTDO
0x10
32
read-write
n
0x0
0x0
FUNCTION_SELECT_HIGH_BIT
configures IO_MUX function, upper bit
8
1
FUNCTION_SELECT_LOW_BITS
configures IO_MUX function, bottom 2 bits
4
2
PULLUP
configures pull up
7
1
Register
0
32
read-write
SLEEP_ENABLE
configures output enable during sleep mode
0
1
SLEEP_PULLUP
configures pull up during sleep mode
3
1
MTMS
IO_MUX_MTMS
0xC
32
read-write
n
0x0
0x0
FUNCTION_SELECT_HIGH_BIT
configures IO_MUX function, upper bit
8
1
FUNCTION_SELECT_LOW_BITS
configures IO_MUX function, bottom 2 bits
4
2
PULLUP
configures pull up
7
1
Register
0
32
read-write
SLEEP_ENABLE
configures output enable during sleep mode
0
1
SLEEP_PULLUP
configures pull up during sleep mode
3
1
SD_CLK
IO_MUX_SD_CLK
0x1C
32
read-write
n
0x0
0x0
FUNCTION_SELECT_HIGH_BIT
configures IO_MUX function, upper bit
8
1
FUNCTION_SELECT_LOW_BITS
configures IO_MUX function, bottom 2 bits
4
2
PULLUP
configures pull up
7
1
Register
0
32
read-write
SLEEP_ENABLE
configures output enable during sleep mode
0
1
SLEEP_PULLUP
configures pull up during sleep mode
3
1
SD_CMD
IO_MUX_SD_CMD
0x30
32
read-write
n
0x0
0x0
FUNCTION_SELECT_HIGH_BIT
configures IO_MUX function, upper bit
8
1
FUNCTION_SELECT_LOW_BITS
configures IO_MUX function, bottom 2 bits
4
2
PULLUP
configures pull up
7
1
Register
0
32
read-write
SLEEP_ENABLE
configures output enable during sleep mode
0
1
SLEEP_PULLUP
configures pull up during sleep mode
3
1
SD_DATA0
IO_MUX_SD_DATA0
0x20
32
read-write
n
0x0
0x0
FUNCTION_SELECT_HIGH_BIT
configures IO_MUX function, upper bit
8
1
FUNCTION_SELECT_LOW_BITS
configures IO_MUX function, bottom 2 bits
4
2
PULLUP
configures pull up
7
1
Register
0
32
read-write
SLEEP_ENABLE
configures output enable during sleep mode
0
1
SLEEP_PULLUP
configures pull up during sleep mode
3
1
SD_DATA1
IO_MUX_SD_DATA1
0x24
32
read-write
n
0x0
0x0
FUNCTION_SELECT_HIGH_BIT
configures IO_MUX function, upper bit
8
1
FUNCTION_SELECT_LOW_BITS
configures IO_MUX function, bottom 2 bits
4
2
PULLUP
configures pull up
7
1
Register
0
32
read-write
SLEEP_ENABLE
configures output enable during sleep mode
0
1
SLEEP_PULLUP
configures pull up during sleep mode
3
1
SD_DATA2
IO_MUX_SD_DATA2
0x28
32
read-write
n
0x0
0x0
FUNCTION_SELECT_HIGH_BIT
configures IO_MUX function, upper bit
8
1
FUNCTION_SELECT_LOW_BITS
configures IO_MUX function, bottom 2 bits
4
2
PULLUP
configures pull up
7
1
Register
0
32
read-write
SLEEP_ENABLE
configures output enable during sleep mode
0
1
SLEEP_PULLUP
configures pull up during sleep mode
3
1
SD_DATA3
IO_MUX_SD_DATA3
0x2C
32
read-write
n
0x0
0x0
FUNCTION_SELECT_HIGH_BIT
configures IO_MUX function, upper bit
8
1
FUNCTION_SELECT_LOW_BITS
configures IO_MUX function, bottom 2 bits
4
2
PULLUP
configures pull up
7
1
Register
0
32
read-write
SLEEP_ENABLE
configures output enable during sleep mode
0
1
SLEEP_PULLUP
configures pull up during sleep mode
3
1
U0RXD
IO_MUX_U0RXD
0x14
32
read-write
n
0x0
0x0
FUNCTION_SELECT_HIGH_BIT
configures IO_MUX function, upper bit
8
1
FUNCTION_SELECT_LOW_BITS
configures IO_MUX function, bottom 2 bits
4
2
PULLUP
configures pull up
7
1
Register
0
32
read-write
SLEEP_ENABLE
configures output enable during sleep mode
0
1
SLEEP_PULLUP
configures pull up during sleep mode
3
1
U0TXD
IO_MUX_U0TXD
0x18
32
read-write
n
0x0
0x0
FUNCTION_SELECT_HIGH_BIT
configures IO_MUX function, upper bit
8
1
FUNCTION_SELECT_LOW_BITS
configures IO_MUX function, bottom 2 bits
4
2
PULLUP
configures pull up
7
1
Register
0
32
read-write
SLEEP_ENABLE
configures output enable during sleep mode
0
1
SLEEP_PULLUP
configures pull up during sleep mode
3
1
RNG
RNG register
RNG
0x0
0x0
0x20
RNG register
n
rng
RNG register
0x0
32
read-only
n
0x0
0x0
RTC
RTC
0x0
0x0
0x40
registers
n
STATE1
RTC_STATE1
0x14
32
read-write
n
0x0
0x0
Register
0
32
read-write
STORE0
RTC_STORE0
0x30
32
read-write
n
0x0
0x0
Register
0
32
read-write
SLC
SLC
0x0
0x0
0x400
registers
n
AHB_TEST
SLC_AHB_TEST
0x54
32
read-write
n
0x0
0x0
SLC_AHB_TESTADDR
4
2
read-write
SLC_AHB_TESTMODE
0
3
read-write
BRIDGE_CONF
SLC_BRIDGE_CONF
0x44
32
read-write
n
0x0
0x0
SLC_FIFO_MAP_ENA
8
4
read-write
SLC_TXEOF_ENA
0
6
read-write
SLC_TX_DUMMY_MODE
12
1
read-write
SLC_TX_PUSH_IDLE_NUM
16
16
read-write
CONF0
SLC_CONF0
0x0
32
read-write
n
0x0
0x0
SLC_AHBM_FIFO_RST
2
1
read-write
SLC_AHBM_RST
3
1
read-write
SLC_DATA_BURST_EN
9
1
read-write
SLC_DSCR_BURST_EN
8
1
read-write
SLC_MODE
12
2
read-write
SLC_RXLINK_RST
1
1
read-write
SLC_RX_AUTO_WRBACK
6
1
read-write
SLC_RX_LOOP_TEST
5
1
read-write
SLC_RX_NO_RESTART_CLR
7
1
read-write
SLC_TXLINK_RST
0
1
read-write
SLC_TX_LOOP_TEST
4
1
read-write
CONF1
SLC_CONF1
0x38
32
read-write
n
0x0
0x0
Register
0
32
read-write
DATE
SLC_DATE
0x78
32
read-write
n
0x0
0x0
Register
0
32
read-write
ID
SLC_ID
0x7C
32
read-write
n
0x0
0x0
Register
0
32
read-write
INTVEC_TOHOST
SLC_INTVEC_TOHOST
0x2C
32
read-write
n
0x0
0x0
SLC_TOHOST_INTVEC
0
8
read-write
INT_CLR
SLC_INT_CLR
0x10
32
read-write
n
0x0
0x0
SLC_FRHOST_BIT0_INT_CLR
0
1
read-write
SLC_FRHOST_BIT1_INT_CLR
1
1
read-write
SLC_FRHOST_BIT2_INT_CLR
2
1
read-write
SLC_FRHOST_BIT3_INT_CLR
3
1
read-write
SLC_FRHOST_BIT4_INT_CLR
4
1
read-write
SLC_FRHOST_BIT5_INT_CLR
5
1
read-write
SLC_FRHOST_BIT6_INT_CLR
6
1
read-write
SLC_FRHOST_BIT7_INT_CLR
7
1
read-write
SLC_RX_DONE_INT_CLR
16
1
read-write
SLC_RX_DSCR_ERR_INT_CLR
20
1
read-write
SLC_RX_EOF_INT_CLR
17
1
read-write
SLC_RX_START_INT_CLR
8
1
read-write
SLC_RX_UDF_INT_CLR
10
1
read-write
SLC_TOHOST_INT_CLR
18
1
read-write
SLC_TOKEN0_1TO0_INT_CLR
12
1
read-write
SLC_TOKEN1_1TO0_INT_CLR
13
1
read-write
SLC_TX_DONE_INT_CLR
14
1
read-write
SLC_TX_DSCR_EMPTY_INT_CLR
21
1
read-write
SLC_TX_DSCR_ERR_INT_CLR
19
1
read-write
SLC_TX_EOF_INT_CLR
15
1
read-write
SLC_TX_OVF_INT_CLR
11
1
read-write
SLC_TX_START_INT_CLR
9
1
read-write
INT_ENA
SLC_INT_ENA
0xC
32
read-write
n
0x0
0x0
SLC_FRHOST_BIT0_INT_ENA
0
1
read-write
SLC_FRHOST_BIT1_INT_ENA
1
1
read-write
SLC_FRHOST_BIT2_INT_ENA
2
1
read-write
SLC_FRHOST_BIT3_INT_ENA
3
1
read-write
SLC_FRHOST_BIT4_INT_ENA
4
1
read-write
SLC_FRHOST_BIT5_INT_ENA
5
1
read-write
SLC_FRHOST_BIT6_INT_ENA
6
1
read-write
SLC_FRHOST_BIT7_INT_ENA
7
1
read-write
SLC_RX_DONE_INT_ENA
16
1
read-write
SLC_RX_DSCR_ERR_INT_ENA
20
1
read-write
SLC_RX_EOF_INT_ENA
17
1
read-write
SLC_RX_START_INT_ENA
8
1
read-write
SLC_RX_UDF_INT_ENA
10
1
read-write
SLC_TOHOST_INT_ENA
18
1
read-write
SLC_TOKEN0_1TO0_INT_ENA
12
1
read-write
SLC_TOKEN1_1TO0_INT_ENA
13
1
read-write
SLC_TX_DONE_INT_ENA
14
1
read-write
SLC_TX_DSCR_EMPTY_INT_ENA
21
1
read-write
SLC_TX_DSCR_ERR_INT_ENA
19
1
read-write
SLC_TX_EOF_INT_ENA
15
1
read-write
SLC_TX_OVF_INT_ENA
11
1
read-write
SLC_TX_START_INT_ENA
9
1
read-write
INT_RAW
SLC_INT_RAW
0x4
32
read-write
n
0x0
0x0
SLC_FRHOST_BIT0_INT_RAW
0
1
read-write
SLC_FRHOST_BIT1_INT_RAW
1
1
read-write
SLC_FRHOST_BIT2_INT_RAW
2
1
read-write
SLC_FRHOST_BIT3_INT_RAW
3
1
read-write
SLC_FRHOST_BIT4_INT_RAW
4
1
read-write
SLC_FRHOST_BIT5_INT_RAW
5
1
read-write
SLC_FRHOST_BIT6_INT_RAW
6
1
read-write
SLC_FRHOST_BIT7_INT_RAW
7
1
read-write
SLC_RX_DONE_INT_RAW
16
1
read-write
SLC_RX_DSCR_ERR_INT_RAW
20
1
read-write
SLC_RX_EOF_INT_RAW
17
1
read-write
SLC_RX_START_INT_RAW
8
1
read-write
SLC_RX_UDF_INT_RAW
10
1
read-write
SLC_TOHOST_INT_RAW
18
1
read-write
SLC_TOKEN0_1TO0_INT_RAW
12
1
read-write
SLC_TOKEN1_1TO0_INT_RAW
13
1
read-write
SLC_TX_DONE_INT_RAW
14
1
read-write
SLC_TX_DSCR_EMPTY_INT_RAW
21
1
read-write
SLC_TX_DSCR_ERR_INT_RAW
19
1
read-write
SLC_TX_EOF_INT_RAW
15
1
read-write
SLC_TX_OVF_INT_RAW
11
1
read-write
SLC_TX_START_INT_RAW
9
1
read-write
INT_STATUS
SLC_INT_STATUS
0x8
32
read-write
n
0x0
0x0
SLC_FRHOST_BIT0_INT_ST
0
1
read-write
SLC_FRHOST_BIT1_INT_ST
1
1
read-write
SLC_FRHOST_BIT2_INT_ST
2
1
read-write
SLC_FRHOST_BIT3_INT_ST
3
1
read-write
SLC_FRHOST_BIT4_INT_ST
4
1
read-write
SLC_FRHOST_BIT5_INT_ST
5
1
read-write
SLC_FRHOST_BIT6_INT_ST
6
1
read-write
SLC_FRHOST_BIT7_INT_ST
7
1
read-write
SLC_RX_DONE_INT_ST
16
1
read-write
SLC_RX_DSCR_ERR_INT_ST
20
1
read-write
SLC_RX_EOF_INT_ST
17
1
read-write
SLC_RX_START_INT_ST
8
1
read-write
SLC_RX_UDF_INT_ST
10
1
read-write
SLC_TOHOST_INT_ST
18
1
read-write
SLC_TOKEN0_1TO0_INT_ST
12
1
read-write
SLC_TOKEN1_1TO0_INT_ST
13
1
read-write
SLC_TX_DONE_INT_ST
14
1
read-write
SLC_TX_DSCR_EMPTY_INT_ST
21
1
read-write
SLC_TX_DSCR_ERR_INT_ST
19
1
read-write
SLC_TX_EOF_INT_ST
15
1
read-write
SLC_TX_OVF_INT_ST
11
1
read-write
SLC_TX_START_INT_ST
9
1
read-write
RXLINK_DSCR
SLC_RXLINK_DSCR
0x6C
32
read-write
n
0x0
0x0
Register
0
32
read-write
RXLINK_DSCR_BF0
SLC_RXLINK_DSCR_BF0
0x70
32
read-write
n
0x0
0x0
Register
0
32
read-write
RXLINK_DSCR_BF1
SLC_RXLINK_DSCR_BF1
0x74
32
read-write
n
0x0
0x0
Register
0
32
read-write
RX_DSCR_CONF
SLC_RX_DSCR_CONF
0x5C
32
read-write
n
0x0
0x0
SLC_INFOR_NO_REPLACE
9
1
read-write
SLC_TOKEN_NO_REPLACE
8
1
read-write
RX_EOF_BFR_DES_ADDR
SLC_RX_EOF_BFR_DES_ADDR
0x50
32
read-write
n
0x0
0x0
Register
0
32
read-write
RX_EOF_DES_ADDR
SLC_RX_EOF_DES_ADDR
0x48
32
read-write
n
0x0
0x0
Register
0
32
read-write
RX_FIFO_PUSH
SLC_RX_FIFO_PUSH
0x18
32
read-write
n
0x0
0x0
SLC_RXFIFO_PUSH
16
1
read-write
SLC_RXFIFO_WDATA
0
9
read-write
RX_LINK
SLC_RX_LINK
0x24
32
read-write
n
0x0
0x0
SLC_RXLINK_ADDR
0
20
read-write
SLC_RXLINK_PARK
31
1
read-write
SLC_RXLINK_RESTART
30
1
read-write
SLC_RXLINK_START
29
1
read-write
SLC_RXLINK_STOP
28
1
read-write
RX_STATUS
SLC_RX_STATUS
0x14
32
read-write
n
0x0
0x0
SLC_RX_EMPTY
1
1
read-write
SLC_RX_FULL
0
1
read-write
SDIO_ST
SLC_SDIO_ST
0x58
32
read-write
n
0x0
0x0
SLC_BUS_ST
12
3
read-write
SLC_CMD_ST
0
3
read-write
SLC_FUNC_ST
4
4
read-write
SLC_SDIO_WAKEUP
8
1
read-write
STATE0
SLC_STATE0
0x3C
32
read-write
n
0x0
0x0
Register
0
32
read-write
STATE1
SLC_STATE1
0x40
32
read-write
n
0x0
0x0
Register
0
32
read-write
TOKEN0
SLC_TOKEN0
0x30
32
read-write
n
0x0
0x0
SLC_TOKEN0
16
12
read-write
SLC_TOKEN0_LOCAL_INC
13
1
read-write
SLC_TOKEN0_LOCAL_INC_MORE
14
1
read-write
SLC_TOKEN0_LOCAL_WDATA
0
12
read-write
SLC_TOKEN0_LOCAL_WR
12
1
read-write
TOKEN1
SLC_TOKEN1
0x34
32
read-write
n
0x0
0x0
SLC_TOKEN1
16
12
read-write
SLC_TOKEN1_LOCAL_INC
13
1
read-write
SLC_TOKEN1_LOCAL_INC_MORE
14
1
read-write
SLC_TOKEN1_LOCAL_WDATA
0
12
read-write
SLC_TOKEN1_LOCAL_WR
12
1
read-write
TXLINK_DSCR
SLC_TXLINK_DSCR
0x60
32
read-write
n
0x0
0x0
Register
0
32
read-write
TXLINK_DSCR_BF0
SLC_TXLINK_DSCR_BF0
0x64
32
read-write
n
0x0
0x0
Register
0
32
read-write
TXLINK_DSCR_BF1
SLC_TXLINK_DSCR_BF1
0x68
32
read-write
n
0x0
0x0
Register
0
32
read-write
TX_EOF_DES_ADDR
SLC_TX_EOF_DES_ADDR
0x4C
32
read-write
n
0x0
0x0
Register
0
32
read-write
TX_FIFO_POP
SLC_TX_FIFO_POP
0x20
32
read-write
n
0x0
0x0
SLC_TXFIFO_POP
16
1
read-write
SLC_TXFIFO_RDATA
0
11
read-write
TX_LINK
SLC_TX_LINK
0x28
32
read-write
n
0x0
0x0
SLC_TXLINK_ADDR
0
20
read-write
SLC_TXLINK_PARK
31
1
read-write
SLC_TXLINK_RESTART
30
1
read-write
SLC_TXLINK_START
29
1
read-write
SLC_TXLINK_STOP
28
1
read-write
TX_STATUS
SLC_TX_STATUS
0x1C
32
read-write
n
0x0
0x0
SLC_TX_EMPTY
1
1
read-write
SLC_TX_FULL
0
1
read-write
SPI0
SPI0
0x0
0x0
0x400
registers
n
SPI_ADDR
In the master mode, it is the value of address in "address" phase.
0x4
32
read-write
n
0x0
0x0
address
0
24
iodata_start_addr
In the master mode, it is the value of address in "address" phase.
0
32
read-write
size
24
8
SPI_CLOCK
In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.
0x18
32
read-write
n
0x0
0x0
spi_clkcnt_H
In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0.
6
6
read-write
spi_clkcnt_L
In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0.
0
6
read-write
spi_clkcnt_N
In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)
12
6
read-write
spi_clkdiv_pre
In the master mode, it is pre-divider of spi_clk.
18
13
read-write
spi_clk_equ_sysclk
In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.
31
1
read-write
SPI_CMD
In the master mode, it is the start bit of a single operation. Self-clear by hardware
0x0
32
read-write
n
0x0
0x0
spi_be
23
1
spi_ce
22
1
spi_dp
21
1
spi_hpm
19
1
spi_pp
25
1
spi_read
31
1
spi_read_id
28
1
spi_read_sr
27
1
spi_res
20
1
spi_se
24
1
spi_usr
In the master mode, it is the start bit of a single operation. Self-clear by hardware
18
1
read-write
spi_write_disable
29
1
spi_write_enable
30
1
spi_write_sr
26
1
SPI_CTRL
SPI_CTRL
0x8
32
read-write
n
0x0
0x0
spi_dio_mode
In the read operations, "address" phase and "read-data" phase apply 2 signals
23
1
read-write
spi_dout_mode
In the read operations, "read-data" phase apply 2 signals
14
1
read-write
spi_fastrd_mode
this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and spi_dout_mode
13
1
read-write
spi_qio_mode
In the read operations, "address" phase and "read-data" phase apply 4 signals
24
1
read-write
spi_qout_mode
In the read operations, "read-data" phase apply 4 signals
20
1
read-write
spi_rd_bit_order
In "read-data" (MISO) phase, 1: LSB first; 0: MSB first
25
1
read-write
spi_wr_bit_order
In "command", "address", "write-data" (MOSI) phases, 1: LSB first; 0: MSB first
26
1
read-write
SPI_CTRL1
0xC
32
read-write
n
0x0
0x0
status
In the slave mode, it is the status for master to read out.
0
16
status_ext
In the slave mode,it is the status for master to read out.
24
8
wb_mode
Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.
16
8
SPI_CTRL2
spi_cs signal is delayed by 80MHz clock cycles
0x14
32
read-write
n
0x0
0x0
spi_cs_delay_mode
spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle
26
2
read-write
spi_cs_delay_num
spi_cs signal is delayed by 80MHz clock cycles
28
4
read-write
spi_miso_delay_mode
MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle
16
2
read-write
spi_miso_delay_num
MISO signals are delayed by 80MHz clock cycles
18
3
read-write
spi_mosi_delay_mode
MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle
21
2
read-write
spi_mosi_delay_num
MOSI signals are delayed by 80MHz clock cycles
23
3
read-write
SPI_EXT3
This register is for two SPI masters to share the same cs, clock and data signals.
0xFC
32
read-write
n
0x0
0x0
reg_int_hold_ena
This register is for two SPI masters to share the same cs, clock and data signals.
0
2
read-write
SPI_PIN
1: disable CS2; 0: spi_cs signal is from/to CS2 pin
0x2C
32
read-write
n
0x0
0x0
spi_cs0_dis
1: disable CS0; 0: spi_cs signal is from/to CS0 pin
0
1
read-write
spi_cs1_dis
1: disable CS1; 0: spi_cs signal is from/to CS1 pin
1
1
read-write
spi_cs2_dis
1: disable CS2; 0: spi_cs signal is from/to CS2 pin
2
1
read-write
spi_idle_edge
In the master mode, 1: high when idle; 0: low when idle
29
1
SPI_RD_STATUS
In the slave mode, this register are the status register for the master to read out.
0x10
32
read-write
n
0x0
0x0
slv_rd_status
In the slave mode, this register are the status register for the master to read out.
0
32
read-write
SPI_SLAVE
It is the synchronous reset signal of the module. This bit is self-cleared by hardware.
0x30
32
read-write
n
0x0
0x0
slv_cmd_define
1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as 1: "write-status"; 4: "read-status"; 2: "write-buffer" and 3: "read-buffer".
27
1
read-write
slv_rd_buf_done
The interrupt raw bit for the completement of "read-buffer" operation in the slave mode.
0
1
read-write
slv_rd_sta_done
The interrupt raw bit for the completement of "read-status" operation in the slave mode.
2
1
read-write
slv_wr_buf_done
The interrupt raw bit for the completement of "write-buffer" operation in the slave mode.
1
1
read-write
slv_wr_sta_done
The interrupt raw bit for the completement of "write-status" operation in the slave mode.
3
1
read-write
spi_int_en
Interrupt enable bits for the below 5 sources
5
5
read-write
spi_slave_mode
1: slave mode, 0: master mode.
30
1
read-write
spi_sync_reset
It is the synchronous reset signal of the module. This bit is self-cleared by hardware.
31
1
read-write
spi_trans_cnt
The operations counter in both the master mode and the slave mode.
23
4
read-only
spi_trans_done
The interrupt raw bit for the completement of any operation in both the master mode and the slave mode.
4
1
read-write
SPI_SLAVE1
In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1)
0x34
32
read-write
n
0x0
0x0
slv_buf_bitlen
In the slave mode, it is the length in bits for "write-buffer" and "read-buffer" operations. The register value shallbe (bit_num-1)
16
9
read-write
slv_rdbuf_dummy_en
In the slave mode, it is the enable bit of "dummy" phase for "read-buffer" operations.
0
1
read-write
slv_rdsta_dummy_en
In the slave mode, it is the enable bit of "dummy" phase for "read-status" operations.
2
1
read-write
slv_rd_addr_bitlen
In the slave mode, it is the address length in bits for "read-buffer" operation. The register value shall be(bit_num-1)
10
6
read-write
slv_status_bitlen
In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1)
27
5
read-write
slv_wrbuf_dummy_en
In the slave mode, it is the enable bit of "dummy" phase for "write-buffer" operations.
1
1
read-write
slv_wrsta_dummy_en
In the slave mode, it is the enable bit of "dummy" phase for "write-status" operations.
3
1
read-write
slv_wr_addr_bitlen
In the slave mode, it is the address length in bits for "write-buffer" operation. The register value shall be(bit_num-1)
4
6
read-write
SPI_SLAVE2
In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1)
0x38
32
read-write
n
0x0
0x0
slv_rdbuf_dummy_cyclelen
In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-buffer" operations. The registervalue shall be (cycle_num-1)
16
8
read-write
slv_rdsta_dummy_cyclelen
In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-status" operations. Theregister value shall be (cycle_num-1)
0
8
read-write
slv_wrbuf_dummy_cyclelen
In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1)
24
8
read-write
slv_wrsta_dummy_cyclelen
In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "write-status" operations. Theregister value shall be (cycle_num-1)
8
8
read-write
SPI_SLAVE3
In slave mode, it is the value of "write-status" command
0x3C
32
read-write
n
0x0
0x0
slv_rdbuf_cmd_value
In slave mode, it is the value of "read-buffer" command
0
8
read-write
slv_rdsta_cmd_value
In slave mode, it is the value of "read-status" command
16
8
read-write
slv_wrbuf_cmd_value
In slave mode, it is the value of "write-buffer" command
8
8
read-write
slv_wrsta_cmd_value
In slave mode, it is the value of "write-status" command
24
8
read-write
SPI_USER
This bit enable the "command" phase of an operation.
0x1C
32
read-write
n
0x0
0x0
reg_usr_miso_highpart
1: "read-data" phase only access to high-part of the buffer spi_w8~spi_w15
24
1
read-write
reg_usr_mosi_highpart
1: "write-data" phase only access to high-part of the buffer spi_w8~spi_w15
25
1
read-write
spi_ahb_user_command
reserved
3
1
spi_ahb_user_command_4byte
reserved
1
1
spi_ck_i_edge
In the slave mode, 1: rising-edge; 0: falling-edge
6
1
read-write
spi_ck_o_edge
In the master mode, 1: rising-edge; 0: falling-edge
7
1
spi_cs_hold
spi cs keep low when spi is in done phase. 1: enable 0: disable.
4
1
spi_cs_setup
spi cs is enable when spi is in prepare phase. 1: enable 0: disable.
5
1
spi_duplex
set spi in full duplex mode
0
1
spi_flash_mode
2
1
spi_fwrite_dio
In the write operations, "address" phase and "read-data" phase apply 2 signals
14
1
read-write
spi_fwrite_dual
In the write operations, "read-data" phase apply 2 signals
12
1
read-write
spi_fwrite_qio
In the write operations, "address" phase and "read-data" phase apply 4 signals
15
1
read-write
spi_fwrite_quad
In the write operations, "read-data" phase apply 4 signals
13
1
read-write
spi_rd_byte_order
In "read-data" (MISO) phase, 1: little-endian; 0: big_endian
10
1
read-write
spi_sio
1: mosi and miso signals share the same pin
16
1
read-write
spi_usr_addr
This bit enable the "address" phase of an operation.
30
1
read-write
spi_usr_command
This bit enable the "command" phase of an operation.
31
1
read-write
spi_usr_dummy
This bit enable the "dummy" phase of an operation.
29
1
read-write
spi_usr_miso
This bit enable the "read-data" phase of an operation.
28
1
read-write
spi_usr_mosi
This bit enable the "write-data" phase of an operation.
27
1
read-write
spi_wr_byte_order
In "command", "address", "write-data" (MOSI) phases, 1: little-endian; 0: big_endian
11
1
read-write
SPI_USER1
The length in bits of "address" phase. The register value shall be (bit_num-1)
0x20
32
read-write
n
0x0
0x0
reg_usr_addr_bitlen
The length in bits of "address" phase. The register value shall be (bit_num-1)
26
6
read-write
reg_usr_dummy_cyclelen
The length in spi_clk cycles of "dummy" phase. The register value shall be (cycle_num-1)
0
8
read-write
reg_usr_miso_bitlen
The length in bits of "read-data" phase. The register value shall be (bit_num-1)
8
9
read-write
reg_usr_mosi_bitlen
The length in bits of "write-data" phase. The register value shall be (bit_num-1)
17
9
read-write
SPI_USER2
The length in bits of "command" phase. The register value shall be (bit_num-1)
0x24
32
read-write
n
0x0
0x0
reg_usr_command_bitlen
The length in bits of "command" phase. The register value shall be (bit_num-1)
28
4
read-write
reg_usr_command_value
The value of "command" phase
0
16
read-write
SPI_W0
the data inside the buffer of the SPI module, byte 0
0x40
32
read-write
n
0x0
0x0
spi_w0
the data inside the buffer of the SPI module, byte 0
0
32
read-write
SPI_W1
the data inside the buffer of the SPI module, byte 1
0x60
32
read-write
n
0x0
0x0
spi_w1
the data inside the buffer of the SPI module, byte 1
0
32
read-write
SPI_W10
the data inside the buffer of the SPI module, byte 10
0x180
32
read-write
n
0x0
0x0
spi_w10
the data inside the buffer of the SPI module, byte 10
0
32
read-write
SPI_W11
the data inside the buffer of the SPI module, byte 11
0x1A0
32
read-write
n
0x0
0x0
spi_w11
the data inside the buffer of the SPI module, byte 11
0
32
read-write
SPI_W12
the data inside the buffer of the SPI module, byte 12
0x1C0
32
read-write
n
0x0
0x0
spi_w12
the data inside the buffer of the SPI module, byte 12
0
32
read-write
SPI_W13
the data inside the buffer of the SPI module, byte 13
0x1E0
32
read-write
n
0x0
0x0
spi_w13
the data inside the buffer of the SPI module, byte 13
0
32
read-write
SPI_W14
the data inside the buffer of the SPI module, byte 14
0x200
32
read-write
n
0x0
0x0
spi_w14
the data inside the buffer of the SPI module, byte 14
0
32
read-write
SPI_W15
the data inside the buffer of the SPI module, byte 15
0x220
32
read-write
n
0x0
0x0
spi_w15
the data inside the buffer of the SPI module, byte 15
0
32
read-write
SPI_W2
the data inside the buffer of the SPI module, byte 2
0x80
32
read-write
n
0x0
0x0
spi_w2
the data inside the buffer of the SPI module, byte 2
0
32
read-write
SPI_W3
the data inside the buffer of the SPI module, byte 3
0xA0
32
read-write
n
0x0
0x0
spi_w3
the data inside the buffer of the SPI module, byte 3
0
32
read-write
SPI_W4
the data inside the buffer of the SPI module, byte 4
0xC0
32
read-write
n
0x0
0x0
spi_w4
the data inside the buffer of the SPI module, byte 4
0
32
read-write
SPI_W5
the data inside the buffer of the SPI module, byte 5
0xE0
32
read-write
n
0x0
0x0
spi_w5
the data inside the buffer of the SPI module, byte 5
0
32
read-write
SPI_W6
the data inside the buffer of the SPI module, byte 6
0x100
32
read-write
n
0x0
0x0
spi_w6
the data inside the buffer of the SPI module, byte 6
0
32
read-write
SPI_W7
the data inside the buffer of the SPI module, byte 7
0x120
32
read-write
n
0x0
0x0
spi_w7
the data inside the buffer of the SPI module, byte 7
0
32
read-write
SPI_W8
the data inside the buffer of the SPI module, byte 8
0x140
32
read-write
n
0x0
0x0
spi_w8
the data inside the buffer of the SPI module, byte 8
0
32
read-write
SPI_W9
the data inside the buffer of the SPI module, byte 9
0x160
32
read-write
n
0x0
0x0
spi_w9
the data inside the buffer of the SPI module, byte 9
0
32
read-write
SPI_WR_STATUS
In the slave mode, this register are the status register for the master to write into.
0x28
32
read-write
n
0x0
0x0
slv_wr_status
In the slave mode, this register are the status register for the master to write into.
0
32
read-write
SPI1
SPI1
0x0
0x0
0x400
registers
n
SPI_ADDR
In the master mode, it is the value of address in "address" phase.
0x4
32
read-write
n
0x0
0x0
address
0
24
iodata_start_addr
In the master mode, it is the value of address in "address" phase.
0
32
read-write
size
24
8
SPI_CLOCK
In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.
0x18
32
read-write
n
0x0
0x0
spi_clkcnt_H
In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0.
6
6
read-write
spi_clkcnt_L
In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0.
0
6
read-write
spi_clkcnt_N
In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)
12
6
read-write
spi_clkdiv_pre
In the master mode, it is pre-divider of spi_clk.
18
13
read-write
spi_clk_equ_sysclk
In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.
31
1
read-write
SPI_CMD
In the master mode, it is the start bit of a single operation. Self-clear by hardware
0x0
32
read-write
n
0x0
0x0
spi_be
23
1
spi_ce
22
1
spi_dp
21
1
spi_hpm
19
1
spi_pp
25
1
spi_read
31
1
spi_read_id
28
1
spi_read_sr
27
1
spi_res
20
1
spi_se
24
1
spi_usr
In the master mode, it is the start bit of a single operation. Self-clear by hardware
18
1
read-write
spi_write_disable
29
1
spi_write_enable
30
1
spi_write_sr
26
1
SPI_CTRL
SPI_CTRL
0x8
32
read-write
n
0x0
0x0
spi_dio_mode
In the read operations, "address" phase and "read-data" phase apply 2 signals
23
1
read-write
spi_dout_mode
In the read operations, "read-data" phase apply 2 signals
14
1
read-write
spi_fastrd_mode
this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and spi_dout_mode
13
1
read-write
spi_qio_mode
In the read operations, "address" phase and "read-data" phase apply 4 signals
24
1
read-write
spi_qout_mode
In the read operations, "read-data" phase apply 4 signals
20
1
read-write
spi_rd_bit_order
In "read-data" (MISO) phase, 1: LSB first; 0: MSB first
25
1
read-write
spi_wr_bit_order
In "command", "address", "write-data" (MOSI) phases, 1: LSB first; 0: MSB first
26
1
read-write
SPI_CTRL1
0xC
32
read-write
n
0x0
0x0
status
In the slave mode, it is the status for master to read out.
0
16
status_ext
In the slave mode,it is the status for master to read out.
24
8
wb_mode
Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.
16
8
SPI_CTRL2
spi_cs signal is delayed by 80MHz clock cycles
0x14
32
read-write
n
0x0
0x0
spi_cs_delay_mode
spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle
26
2
read-write
spi_cs_delay_num
spi_cs signal is delayed by 80MHz clock cycles
28
4
read-write
spi_miso_delay_mode
MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle
16
2
read-write
spi_miso_delay_num
MISO signals are delayed by 80MHz clock cycles
18
3
read-write
spi_mosi_delay_mode
MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle
21
2
read-write
spi_mosi_delay_num
MOSI signals are delayed by 80MHz clock cycles
23
3
read-write
SPI_EXT3
This register is for two SPI masters to share the same cs, clock and data signals.
0xFC
32
read-write
n
0x0
0x0
reg_int_hold_ena
This register is for two SPI masters to share the same cs, clock and data signals.
0
2
read-write
SPI_PIN
1: disable CS2; 0: spi_cs signal is from/to CS2 pin
0x2C
32
read-write
n
0x0
0x0
spi_cs0_dis
1: disable CS0; 0: spi_cs signal is from/to CS0 pin
0
1
read-write
spi_cs1_dis
1: disable CS1; 0: spi_cs signal is from/to CS1 pin
1
1
read-write
spi_cs2_dis
1: disable CS2; 0: spi_cs signal is from/to CS2 pin
2
1
read-write
spi_idle_edge
In the master mode, 1: high when idle; 0: low when idle
29
1
SPI_RD_STATUS
In the slave mode, this register are the status register for the master to read out.
0x10
32
read-write
n
0x0
0x0
slv_rd_status
In the slave mode, this register are the status register for the master to read out.
0
32
read-write
SPI_SLAVE
It is the synchronous reset signal of the module. This bit is self-cleared by hardware.
0x30
32
read-write
n
0x0
0x0
slv_cmd_define
1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as 1: "write-status"; 4: "read-status"; 2: "write-buffer" and 3: "read-buffer".
27
1
read-write
slv_rd_buf_done
The interrupt raw bit for the completement of "read-buffer" operation in the slave mode.
0
1
read-write
slv_rd_sta_done
The interrupt raw bit for the completement of "read-status" operation in the slave mode.
2
1
read-write
slv_wr_buf_done
The interrupt raw bit for the completement of "write-buffer" operation in the slave mode.
1
1
read-write
slv_wr_sta_done
The interrupt raw bit for the completement of "write-status" operation in the slave mode.
3
1
read-write
spi_int_en
Interrupt enable bits for the below 5 sources
5
5
read-write
spi_slave_mode
1: slave mode, 0: master mode.
30
1
read-write
spi_sync_reset
It is the synchronous reset signal of the module. This bit is self-cleared by hardware.
31
1
read-write
spi_trans_cnt
The operations counter in both the master mode and the slave mode.
23
4
read-only
spi_trans_done
The interrupt raw bit for the completement of any operation in both the master mode and the slave mode.
4
1
read-write
SPI_SLAVE1
In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1)
0x34
32
read-write
n
0x0
0x0
slv_buf_bitlen
In the slave mode, it is the length in bits for "write-buffer" and "read-buffer" operations. The register value shallbe (bit_num-1)
16
9
read-write
slv_rdbuf_dummy_en
In the slave mode, it is the enable bit of "dummy" phase for "read-buffer" operations.
0
1
read-write
slv_rdsta_dummy_en
In the slave mode, it is the enable bit of "dummy" phase for "read-status" operations.
2
1
read-write
slv_rd_addr_bitlen
In the slave mode, it is the address length in bits for "read-buffer" operation. The register value shall be(bit_num-1)
10
6
read-write
slv_status_bitlen
In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1)
27
5
read-write
slv_wrbuf_dummy_en
In the slave mode, it is the enable bit of "dummy" phase for "write-buffer" operations.
1
1
read-write
slv_wrsta_dummy_en
In the slave mode, it is the enable bit of "dummy" phase for "write-status" operations.
3
1
read-write
slv_wr_addr_bitlen
In the slave mode, it is the address length in bits for "write-buffer" operation. The register value shall be(bit_num-1)
4
6
read-write
SPI_SLAVE2
In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1)
0x38
32
read-write
n
0x0
0x0
slv_rdbuf_dummy_cyclelen
In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-buffer" operations. The registervalue shall be (cycle_num-1)
16
8
read-write
slv_rdsta_dummy_cyclelen
In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-status" operations. Theregister value shall be (cycle_num-1)
0
8
read-write
slv_wrbuf_dummy_cyclelen
In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1)
24
8
read-write
slv_wrsta_dummy_cyclelen
In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "write-status" operations. Theregister value shall be (cycle_num-1)
8
8
read-write
SPI_SLAVE3
In slave mode, it is the value of "write-status" command
0x3C
32
read-write
n
0x0
0x0
slv_rdbuf_cmd_value
In slave mode, it is the value of "read-buffer" command
0
8
read-write
slv_rdsta_cmd_value
In slave mode, it is the value of "read-status" command
16
8
read-write
slv_wrbuf_cmd_value
In slave mode, it is the value of "write-buffer" command
8
8
read-write
slv_wrsta_cmd_value
In slave mode, it is the value of "write-status" command
24
8
read-write
SPI_USER
This bit enable the "command" phase of an operation.
0x1C
32
read-write
n
0x0
0x0
reg_usr_miso_highpart
1: "read-data" phase only access to high-part of the buffer spi_w8~spi_w15
24
1
read-write
reg_usr_mosi_highpart
1: "write-data" phase only access to high-part of the buffer spi_w8~spi_w15
25
1
read-write
spi_ahb_user_command
reserved
3
1
spi_ahb_user_command_4byte
reserved
1
1
spi_ck_i_edge
In the slave mode, 1: rising-edge; 0: falling-edge
6
1
read-write
spi_ck_o_edge
In the master mode, 1: rising-edge; 0: falling-edge
7
1
spi_cs_hold
spi cs keep low when spi is in done phase. 1: enable 0: disable.
4
1
spi_cs_setup
spi cs is enable when spi is in prepare phase. 1: enable 0: disable.
5
1
spi_duplex
set spi in full duplex mode
0
1
spi_flash_mode
2
1
spi_fwrite_dio
In the write operations, "address" phase and "read-data" phase apply 2 signals
14
1
read-write
spi_fwrite_dual
In the write operations, "read-data" phase apply 2 signals
12
1
read-write
spi_fwrite_qio
In the write operations, "address" phase and "read-data" phase apply 4 signals
15
1
read-write
spi_fwrite_quad
In the write operations, "read-data" phase apply 4 signals
13
1
read-write
spi_rd_byte_order
In "read-data" (MISO) phase, 1: little-endian; 0: big_endian
10
1
read-write
spi_sio
1: mosi and miso signals share the same pin
16
1
read-write
spi_usr_addr
This bit enable the "address" phase of an operation.
30
1
read-write
spi_usr_command
This bit enable the "command" phase of an operation.
31
1
read-write
spi_usr_dummy
This bit enable the "dummy" phase of an operation.
29
1
read-write
spi_usr_miso
This bit enable the "read-data" phase of an operation.
28
1
read-write
spi_usr_mosi
This bit enable the "write-data" phase of an operation.
27
1
read-write
spi_wr_byte_order
In "command", "address", "write-data" (MOSI) phases, 1: little-endian; 0: big_endian
11
1
read-write
SPI_USER1
The length in bits of "address" phase. The register value shall be (bit_num-1)
0x20
32
read-write
n
0x0
0x0
reg_usr_addr_bitlen
The length in bits of "address" phase. The register value shall be (bit_num-1)
26
6
read-write
reg_usr_dummy_cyclelen
The length in spi_clk cycles of "dummy" phase. The register value shall be (cycle_num-1)
0
8
read-write
reg_usr_miso_bitlen
The length in bits of "read-data" phase. The register value shall be (bit_num-1)
8
9
read-write
reg_usr_mosi_bitlen
The length in bits of "write-data" phase. The register value shall be (bit_num-1)
17
9
read-write
SPI_USER2
The length in bits of "command" phase. The register value shall be (bit_num-1)
0x24
32
read-write
n
0x0
0x0
reg_usr_command_bitlen
The length in bits of "command" phase. The register value shall be (bit_num-1)
28
4
read-write
reg_usr_command_value
The value of "command" phase
0
16
read-write
SPI_W0
the data inside the buffer of the SPI module, byte 0
0x40
32
read-write
n
0x0
0x0
spi_w0
the data inside the buffer of the SPI module, byte 0
0
32
read-write
SPI_W1
the data inside the buffer of the SPI module, byte 1
0x60
32
read-write
n
0x0
0x0
spi_w1
the data inside the buffer of the SPI module, byte 1
0
32
read-write
SPI_W10
the data inside the buffer of the SPI module, byte 10
0x180
32
read-write
n
0x0
0x0
spi_w10
the data inside the buffer of the SPI module, byte 10
0
32
read-write
SPI_W11
the data inside the buffer of the SPI module, byte 11
0x1A0
32
read-write
n
0x0
0x0
spi_w11
the data inside the buffer of the SPI module, byte 11
0
32
read-write
SPI_W12
the data inside the buffer of the SPI module, byte 12
0x1C0
32
read-write
n
0x0
0x0
spi_w12
the data inside the buffer of the SPI module, byte 12
0
32
read-write
SPI_W13
the data inside the buffer of the SPI module, byte 13
0x1E0
32
read-write
n
0x0
0x0
spi_w13
the data inside the buffer of the SPI module, byte 13
0
32
read-write
SPI_W14
the data inside the buffer of the SPI module, byte 14
0x200
32
read-write
n
0x0
0x0
spi_w14
the data inside the buffer of the SPI module, byte 14
0
32
read-write
SPI_W15
the data inside the buffer of the SPI module, byte 15
0x220
32
read-write
n
0x0
0x0
spi_w15
the data inside the buffer of the SPI module, byte 15
0
32
read-write
SPI_W2
the data inside the buffer of the SPI module, byte 2
0x80
32
read-write
n
0x0
0x0
spi_w2
the data inside the buffer of the SPI module, byte 2
0
32
read-write
SPI_W3
the data inside the buffer of the SPI module, byte 3
0xA0
32
read-write
n
0x0
0x0
spi_w3
the data inside the buffer of the SPI module, byte 3
0
32
read-write
SPI_W4
the data inside the buffer of the SPI module, byte 4
0xC0
32
read-write
n
0x0
0x0
spi_w4
the data inside the buffer of the SPI module, byte 4
0
32
read-write
SPI_W5
the data inside the buffer of the SPI module, byte 5
0xE0
32
read-write
n
0x0
0x0
spi_w5
the data inside the buffer of the SPI module, byte 5
0
32
read-write
SPI_W6
the data inside the buffer of the SPI module, byte 6
0x100
32
read-write
n
0x0
0x0
spi_w6
the data inside the buffer of the SPI module, byte 6
0
32
read-write
SPI_W7
the data inside the buffer of the SPI module, byte 7
0x120
32
read-write
n
0x0
0x0
spi_w7
the data inside the buffer of the SPI module, byte 7
0
32
read-write
SPI_W8
the data inside the buffer of the SPI module, byte 8
0x140
32
read-write
n
0x0
0x0
spi_w8
the data inside the buffer of the SPI module, byte 8
0
32
read-write
SPI_W9
the data inside the buffer of the SPI module, byte 9
0x160
32
read-write
n
0x0
0x0
spi_w9
the data inside the buffer of the SPI module, byte 9
0
32
read-write
SPI_WR_STATUS
In the slave mode, this register are the status register for the master to write into.
0x28
32
read-write
n
0x0
0x0
slv_wr_status
In the slave mode, this register are the status register for the master to write into.
0
32
read-write
TIMER
TIMER
0x0
0x0
0x120
registers
n
FRC1_COUNT
the current value of the counter. It is a decreasingcounter.
0x4
32
read-write
n
0x0
0x0
frc1_count
the current value of the counter. It is a decreasingcounter.
0
23
read-only
FRC1_CTRL
FRC1_CTRL
0x8
32
read-write
n
0x0
0x0
frc1_ctrl
bit[7]: timer enable, bit[6]: automatically reload, when the counter isequal to zero, bit[3:2]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by 256, bit[0]: interrupt type, 0:edge, 1:level
0
8
read-write
frc1_int
the status of the interrupt, when the count isdereased to zero
8
1
read-only
interrupt_type
Configure the interrupt type
0
1
read-write
interrupt_type
read-write
edge
edge
0
level
level
1
prescale_divider
Pre-scale divider for the timer
2
2
read-write
prescale_divider
read-write
devided_by_1
divided by 1
0
devided_by_16
divided by 16
1
devided_by_256
divided by 256
2
rollover
Automatically reload when the counter hits zero
6
1
read-write
timer_enable
Enable or disable the timer
7
1
read-write
FRC1_INT
FRC1_INT
0xC
32
read-write
n
0x0
0x0
frc1_int_clr_mask
write to clear the status of the interrupt, if theinterrupt type is "level"
0
1
read-write
FRC1_LOAD
the load value into the counter
0x0
32
read-write
n
0x0
0x0
frc1_load_value
the load value into the counter
0
23
read-write
FRC2_ALARM
the alarm value for the counter
0x30
32
read-write
n
0x0
0x0
frc2_alarm
the alarm value for the counter
0
32
read-write
FRC2_COUNT
the current value of the counter. It is a increasingcounter.
0x24
32
read-write
n
0x0
0x0
frc2_count
the current value of the counter. It is a increasingcounter.
0
32
read-only
FRC2_CTRL
FRC2_CTRL
0x28
32
read-write
n
0x0
0x0
frc2_ctrl
bit[7]: timer enable, bit[6]: automatically reload, when the counter isequal to zero, bit[3:2]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by 256, bit[0]: interrupt type, 0:edge, 1:level
0
8
read-write
frc2_int
the status of the interrupt, when the count is equal tothe alarm value
8
1
read-only
interrupt_type
Configure the interrupt type
0
1
read-write
interrupt_type
read-write
edge
edge
0
level
level
1
prescale_divider
Pre-scale divider for the timer
2
2
read-write
prescale_divider
read-write
devided_by_1
divided by 1
0
devided_by_16
divided by 16
1
devided_by_256
divided by 256
2
rollover
Automatically reload when the counter hits zero
6
1
read-write
timer_enable
Enable or disable the timer
7
1
read-write
FRC2_INT
FRC2_INT
0x2C
32
read-write
n
0x0
0x0
frc2_int_clr_mask
write to clear the status of the interrupt, if theinterrupt type is "level"
0
1
read-write
FRC2_LOAD
the load value into the counter
0x20
32
read-write
n
0x0
0x0
frc2_load_value
the load value into the counter
0
32
read-write
UART0
UART0
0x0
0x0
0x1E0
registers
n
UART_AUTOBAUD
UART BAUDRATE DETECT REGISTER
0x18
32
read-write
n
0x0
0x0
autobaud_en
Set this bit to enable baudrate detect
0
1
read-write
glitch_filt
8
8
read-write
UART_CLKDIV
UART CLK DIV REGISTER
0x14
32
read-write
n
0x0
0x0
uart_clkdiv
BAUDRATE = UART_CLK_FREQ / UART_CLKDIV
0
20
read-write
UART_CONF0
UART CONFIG0(UART0 and UART1)
0x20
32
read-write
n
0x0
0x0
bit_num
Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits
2
2
read-write
parity
Set parity check: 0:even 1:odd, UART CONFIG1
0
1
read-write
parity_en
Set this bit to enable uart parity check
1
1
read-write
rxfifo_rst
Set this bit to reset uart rx fifo
17
1
read-write
stop_bit_num
Set stop bit: 1:1bit 2:1.5bits 3:2bits
4
2
read-write
sw_dtr
sw dtr
7
1
read-write
sw_rts
sw rts
6
1
read-write
txd_brk
RESERVED, DO NOT CHANGE THIS BIT
8
1
read-write
txfifo_rst
Set this bit to reset uart tx fifo
18
1
read-write
tx_flow_en
Set this bit to enable uart tx hardware flow control
15
1
read-write
uart_cts_inv
Set this bit to inverse uart cts level
20
1
read-write
uart_dsr_inv
Set this bit to inverse uart dsr level
21
1
read-write
uart_dtr_inv
Set this bit to inverse uart dtr level
24
1
read-write
uart_loopback
Set this bit to enable uart loopback test mode
14
1
read-write
uart_rts_inv
Set this bit to inverse uart rts level
23
1
read-write
uart_rxd_inv
Set this bit to inverse uart rxd level
19
1
read-write
uart_txd_inv
Set this bit to inverse uart txd level
22
1
read-write
UART_CONF1
Set this bit to enable rx time-out function
0x24
32
read-write
n
0x0
0x0
rxfifo_full_thrhd
The config bits for rx fifo full threshold,0-127
0
7
read-write
rx_flow_en
Set this bit to enable rx hardware flow control
23
1
read-write
rx_flow_thrhd
The config bits for rx flow control threshold,0-127
16
7
read-write
rx_tout_en
Set this bit to enable rx time-out function
31
1
read-write
rx_tout_thrhd
Config bits for rx time-out threshold,uint: byte,0-127
24
7
read-write
txfifo_empty_thrhd
The config bits for tx fifo empty threshold,0-127
8
7
read-write
UART_DATE
UART HW INFO
0x78
32
read-write
n
0x0
0x0
uart_date
UART HW INFO
0
32
read-write
UART_FIFO
UART FIFO,length 128
0x0
32
read-write
n
0x0
0x0
rxfifo_rd_byte
R/W share the same address
0
8
read-only
rxfifo_write_byte
R/W share the same address
0
8
UART_HIGHPULSE
UART_HIGHPULSE
0x2C
32
read-write
n
0x0
0x0
highpulse_min_cnt
used in baudrate detect
0
20
read-only
UART_ID
UART_ID
0x7C
32
read-write
n
0x0
0x0
uart_id
0
32
read-write
UART_INT_CLR
UART INTERRUPT CLEAR REGISTER
0x10
32
read-write
n
0x0
0x0
brk_det_int_clr
Set this bit to clear the rx byte start interrupt
7
1
write-only
cts_chg_int_clr
Set this bit to clear the CTS changing interrupt
6
1
write-only
dsr_chg_int_clr
Set this bit to clear the DSR changing interrupt
5
1
write-only
frm_err_int_clr
Set this bit to clear other rx error interrupt
3
1
write-only
parity_err_int_clr
Set this bit to clear the parity error interrupt
2
1
write-only
rxfifo_full_int_clr
Set this bit to clear the rx fifo full interrupt
0
1
write-only
rxfifo_ovf_int_clr
Set this bit to clear the rx fifo over-flow interrupt
4
1
write-only
rxfifo_tout_int_clr
Set this bit to clear the rx time-out interrupt
8
1
write-only
txfifo_empty_int_clr
Set this bit to clear the tx fifo empty interrupt
1
1
write-only
UART_INT_ENA
UART INTERRUPT ENABLE REGISTER
0xC
32
read-write
n
0x0
0x0
brk_det_int_ena
The interrupt enable bit for rx byte start error
7
1
read-write
cts_chg_int_ena
The interrupt enable bit for CTS changing level
6
1
read-write
dsr_chg_int_ena
The interrupt enable bit for DSR changing level
5
1
read-write
frm_err_int_ena
The interrupt enable bit for other rx error
3
1
read-write
parity_err_int_ena
The interrupt enable bit for parity error
2
1
read-write
rxfifo_full_int_ena
The interrupt enable bit for rx fifo full event
0
1
read-write
rxfifo_ovf_int_ena
The interrupt enable bit for rx fifo overflow
4
1
read-write
rxfifo_tout_int_ena
The interrupt enable bit for rx time-out interrupt
8
1
read-write
txfifo_empty_int_ena
The interrupt enable bit for tx fifo empty event
1
1
read-write
UART_INT_RAW
UART INTERRUPT RAW STATE
0x4
32
read-write
n
0x0
0x0
brk_det_int_raw
The interrupt raw bit for Rx byte start error
7
1
read-only
cts_chg_int_raw
The interrupt raw bit for CTS changing level
6
1
read-only
dsr_chg_int_raw
The interrupt raw bit for DSR changing level
5
1
read-only
frm_err_int_raw
The interrupt raw bit for other rx error
3
1
read-only
parity_err_int_raw
The interrupt raw bit for parity check error
2
1
read-only
rxfifo_full_int_raw
The interrupt raw bit for rx fifo full interrupt(depands onUART_RXFIFO_FULL_THRHD bits)
0
1
read-only
rxfifo_ovf_int_raw
The interrupt raw bit for rx fifo overflow
4
1
read-only
rxfifo_tout_int_raw
The interrupt raw bit for Rx time-out interrupt(depands on theUART_RX_TOUT_THRHD)
8
1
read-only
txfifo_empty_int_raw
The interrupt raw bit for tx fifo empty interrupt(depands onUART_TXFIFO_EMPTY_THRHD bits)
1
1
read-only
UART_INT_ST
UART INTERRUPT STATEREGISTERUART_INT_RAW and UART_INT_ENA
0x8
32
read-write
n
0x0
0x0
brk_det_int_st
The interrupt state bit for rx byte start error
7
1
read-only
cts_chg_int_st
The interrupt state bit for CTS changing level
6
1
read-only
dsr_chg_int_st
The interrupt state bit for DSR changing level
5
1
read-only
frm_err_int_st
The interrupt state for other rx error
3
1
read-only
parity_err_int_st
The interrupt state bit for rx parity error
2
1
read-only
rxfifo_full_int_st
The interrupt state bit for RX fifo full event
0
1
read-only
rxfifo_ovf_int_st
The interrupt state bit for RX fifo overflow
4
1
read-only
rxfifo_tout_int_st
The interrupt state bit for Rx time-out event
8
1
read-only
txfifo_empty_int_st
The interrupt state bit for TX fifo empty
1
1
read-only
UART_LOWPULSE
UART_LOWPULSE
0x28
32
read-write
n
0x0
0x0
lowpulse_min_cnt
used in baudrate detect
0
20
read-only
UART_RXD_CNT
UART_RXD_CNT
0x30
32
read-write
n
0x0
0x0
rxd_edge_cnt
used in baudrate detect
0
10
read-only
UART_STATUS
UART STATUS REGISTER
0x1C
32
read-write
n
0x0
0x0
ctsn
The level of uart cts pin
14
1
read-only
dsrn
The level of uart dsr pin
13
1
read-only
dtrn
The level of uart dtr pin
29
1
read-only
rtsn
The level of uart rts pin
30
1
read-only
rxd
The level of uart rxd pin
15
1
read-only
rxfifo_cnt
Number of data in uart rx fifo
0
8
read-only
txd
The level of the uart txd pin
31
1
read-only
txfifo_cnt
Number of data in UART TX fifo
16
8
read-only
UART1
UART1
0x0
0x0
0x1E0
registers
n
UART_AUTOBAUD
UART BAUDRATE DETECT REGISTER
0x18
32
read-write
n
0x0
0x0
autobaud_en
Set this bit to enable baudrate detect
0
1
read-write
glitch_filt
8
8
read-write
UART_CLKDIV
UART CLK DIV REGISTER
0x14
32
read-write
n
0x0
0x0
uart_clkdiv
BAUDRATE = UART_CLK_FREQ / UART_CLKDIV
0
20
read-write
UART_CONF0
UART CONFIG0(UART0 and UART1)
0x20
32
read-write
n
0x0
0x0
bit_num
Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits
2
2
read-write
parity
Set parity check: 0:even 1:odd, UART CONFIG1
0
1
read-write
parity_en
Set this bit to enable uart parity check
1
1
read-write
rxfifo_rst
Set this bit to reset uart rx fifo
17
1
read-write
stop_bit_num
Set stop bit: 1:1bit 2:1.5bits 3:2bits
4
2
read-write
sw_dtr
sw dtr
7
1
read-write
sw_rts
sw rts
6
1
read-write
txd_brk
RESERVED, DO NOT CHANGE THIS BIT
8
1
read-write
txfifo_rst
Set this bit to reset uart tx fifo
18
1
read-write
tx_flow_en
Set this bit to enable uart tx hardware flow control
15
1
read-write
uart_cts_inv
Set this bit to inverse uart cts level
20
1
read-write
uart_dsr_inv
Set this bit to inverse uart dsr level
21
1
read-write
uart_dtr_inv
Set this bit to inverse uart dtr level
24
1
read-write
uart_loopback
Set this bit to enable uart loopback test mode
14
1
read-write
uart_rts_inv
Set this bit to inverse uart rts level
23
1
read-write
uart_rxd_inv
Set this bit to inverse uart rxd level
19
1
read-write
uart_txd_inv
Set this bit to inverse uart txd level
22
1
read-write
UART_CONF1
Set this bit to enable rx time-out function
0x24
32
read-write
n
0x0
0x0
rxfifo_full_thrhd
The config bits for rx fifo full threshold,0-127
0
7
read-write
rx_flow_en
Set this bit to enable rx hardware flow control
23
1
read-write
rx_flow_thrhd
The config bits for rx flow control threshold,0-127
16
7
read-write
rx_tout_en
Set this bit to enable rx time-out function
31
1
read-write
rx_tout_thrhd
Config bits for rx time-out threshold,uint: byte,0-127
24
7
read-write
txfifo_empty_thrhd
The config bits for tx fifo empty threshold,0-127
8
7
read-write
UART_DATE
UART HW INFO
0x78
32
read-write
n
0x0
0x0
uart_date
UART HW INFO
0
32
read-write
UART_FIFO
UART FIFO,length 128
0x0
32
read-write
n
0x0
0x0
rxfifo_rd_byte
R/W share the same address
0
8
read-only
rxfifo_write_byte
R/W share the same address
0
8
UART_HIGHPULSE
UART_HIGHPULSE
0x2C
32
read-write
n
0x0
0x0
highpulse_min_cnt
used in baudrate detect
0
20
read-only
UART_ID
UART_ID
0x7C
32
read-write
n
0x0
0x0
uart_id
0
32
read-write
UART_INT_CLR
UART INTERRUPT CLEAR REGISTER
0x10
32
read-write
n
0x0
0x0
brk_det_int_clr
Set this bit to clear the rx byte start interrupt
7
1
write-only
cts_chg_int_clr
Set this bit to clear the CTS changing interrupt
6
1
write-only
dsr_chg_int_clr
Set this bit to clear the DSR changing interrupt
5
1
write-only
frm_err_int_clr
Set this bit to clear other rx error interrupt
3
1
write-only
parity_err_int_clr
Set this bit to clear the parity error interrupt
2
1
write-only
rxfifo_full_int_clr
Set this bit to clear the rx fifo full interrupt
0
1
write-only
rxfifo_ovf_int_clr
Set this bit to clear the rx fifo over-flow interrupt
4
1
write-only
rxfifo_tout_int_clr
Set this bit to clear the rx time-out interrupt
8
1
write-only
txfifo_empty_int_clr
Set this bit to clear the tx fifo empty interrupt
1
1
write-only
UART_INT_ENA
UART INTERRUPT ENABLE REGISTER
0xC
32
read-write
n
0x0
0x0
brk_det_int_ena
The interrupt enable bit for rx byte start error
7
1
read-write
cts_chg_int_ena
The interrupt enable bit for CTS changing level
6
1
read-write
dsr_chg_int_ena
The interrupt enable bit for DSR changing level
5
1
read-write
frm_err_int_ena
The interrupt enable bit for other rx error
3
1
read-write
parity_err_int_ena
The interrupt enable bit for parity error
2
1
read-write
rxfifo_full_int_ena
The interrupt enable bit for rx fifo full event
0
1
read-write
rxfifo_ovf_int_ena
The interrupt enable bit for rx fifo overflow
4
1
read-write
rxfifo_tout_int_ena
The interrupt enable bit for rx time-out interrupt
8
1
read-write
txfifo_empty_int_ena
The interrupt enable bit for tx fifo empty event
1
1
read-write
UART_INT_RAW
UART INTERRUPT RAW STATE
0x4
32
read-write
n
0x0
0x0
brk_det_int_raw
The interrupt raw bit for Rx byte start error
7
1
read-only
cts_chg_int_raw
The interrupt raw bit for CTS changing level
6
1
read-only
dsr_chg_int_raw
The interrupt raw bit for DSR changing level
5
1
read-only
frm_err_int_raw
The interrupt raw bit for other rx error
3
1
read-only
parity_err_int_raw
The interrupt raw bit for parity check error
2
1
read-only
rxfifo_full_int_raw
The interrupt raw bit for rx fifo full interrupt(depands onUART_RXFIFO_FULL_THRHD bits)
0
1
read-only
rxfifo_ovf_int_raw
The interrupt raw bit for rx fifo overflow
4
1
read-only
rxfifo_tout_int_raw
The interrupt raw bit for Rx time-out interrupt(depands on theUART_RX_TOUT_THRHD)
8
1
read-only
txfifo_empty_int_raw
The interrupt raw bit for tx fifo empty interrupt(depands onUART_TXFIFO_EMPTY_THRHD bits)
1
1
read-only
UART_INT_ST
UART INTERRUPT STATEREGISTERUART_INT_RAW and UART_INT_ENA
0x8
32
read-write
n
0x0
0x0
brk_det_int_st
The interrupt state bit for rx byte start error
7
1
read-only
cts_chg_int_st
The interrupt state bit for CTS changing level
6
1
read-only
dsr_chg_int_st
The interrupt state bit for DSR changing level
5
1
read-only
frm_err_int_st
The interrupt state for other rx error
3
1
read-only
parity_err_int_st
The interrupt state bit for rx parity error
2
1
read-only
rxfifo_full_int_st
The interrupt state bit for RX fifo full event
0
1
read-only
rxfifo_ovf_int_st
The interrupt state bit for RX fifo overflow
4
1
read-only
rxfifo_tout_int_st
The interrupt state bit for Rx time-out event
8
1
read-only
txfifo_empty_int_st
The interrupt state bit for TX fifo empty
1
1
read-only
UART_LOWPULSE
UART_LOWPULSE
0x28
32
read-write
n
0x0
0x0
lowpulse_min_cnt
used in baudrate detect
0
20
read-only
UART_RXD_CNT
UART_RXD_CNT
0x30
32
read-write
n
0x0
0x0
rxd_edge_cnt
used in baudrate detect
0
10
read-only
UART_STATUS
UART STATUS REGISTER
0x1C
32
read-write
n
0x0
0x0
ctsn
The level of uart cts pin
14
1
read-only
dsrn
The level of uart dsr pin
13
1
read-only
dtrn
The level of uart dtr pin
29
1
read-only
rtsn
The level of uart rts pin
30
1
read-only
rxd
The level of uart rxd pin
15
1
read-only
rxfifo_cnt
Number of data in uart rx fifo
0
8
read-only
txd
The level of the uart txd pin
31
1
read-only
txfifo_cnt
Number of data in UART TX fifo
16
8
read-only
WATCHDOG
Watchdog registers
WATCHDOG
0x0
0x0
0x18
Watchdog registers
n
count
Watchdog clock cycle count
0xC
32
read-write
n
0x0
0x0
ctl
Watchdog control
0x0
32
read-write
n
0x0
0x0
enable
Enable the watchdog timer.
0
1
stage_1_disable
Set to 1 to disable the stage 1 of the watchdog timer
2
1
stage_1_no_reset
When set to 1, and running in two-stage mode, it turns the watchdog into a single shot timer that doesn't reset the device.
1
1
unknown_3
3
1
unknown_4
4
1
unknown_5
5
1
reload_stage0
Reload value for stage 0
0x4
32
read-write
n
0x0
0x0
reload_stage1
Reload value for stage 1
0x8
32
read-write
n
0x0
0x0
reset
Watchdog reset
0x14
32
read-write
n
0x0
0x0
reset_stage
Watchdog stage reset
0x18
32
read-write
n
0x0
0x0
stage
The current watchdog stage
0x10
32
read-write
n
0x0
0x0
WDT
WDT
0x0
0x0
0x2C
registers
n
CTL
WDT_CTL
0x0
32
read-write
n
0x0
0x0
Register
0
32
read-write
OP
WDT_OP
0x4
32
read-write
n
0x0
0x0
Register
0
32
read-write
OP_ND
WDT_OP_ND
0x8
32
read-write
n
0x0
0x0
Register
0
32
read-write
RST
WDT_RST
0x14
32
read-write
n
0x0
0x0
Register
0
32
read-write