Fujitsu MB9AFAAxM 2024.04.20 MB9AFAAxM 8 32 ADC0 ADC0 Registers ADC0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x4 registers n 0x20 0x1 registers n 0x24 0x1 registers n 0x26 0x2 registers n 0x28 0x2 registers n 0x2C 0x2 registers n 0x30 0x2 registers n 0x34 0x1 registers n 0x38 0x2 registers n 0x3C 0x2 registers n 0x8 0x2 registers n 0xC 0x4 registers n ADC0 24 ADCEN A/D Operation Enable Setup Register 0x3C 16 read-write n 0x0 0x0 ENBL A/D operation enable bit 0 read-write ENBLTIME Basic cycle selection bit 8 7 read-write READY A/D operation enable state bit 1 read-only ADCR A/D Control Register 0x1 8 read-write n 0x0 0x0 CMPIE Conversion result comparison interrupt enable bit 1 read-write CMPIF Conversion result comparison interrupt request bit 5 read-write OVRIE FIFO overrun interrupt enable bit 0 read-write PCIE Priority conversion interrupt enable bit 2 read-write PCIF Priority conversion interrupt request bit 6 read-write SCIE Scan conversion interrupt enable bit 3 read-write SCIF Scan conversion interrupt request bit 7 read-write ADCT Comparison Time Setup Register 0x34 8 read-write n 0x0 0x0 CT Compare clock frequency division ratio setting bits 0 7 read-write ADSR A/D Status Register 0x0 8 read-write n 0x0 0x0 ADSTP A/D conversion forced stop bit 7 read-write FDAS FIFO data placement selection bit 6 read-write PCNS Priority conversion pending flag 2 read-write PCS Priority conversion status flag 1 read-write SCS Scan conversion status flag 0 read-write ADSS0 Sampling Time Selection Register 0 0x2C 8 read-write n 0x0 0x0 TS0 Bit0 of ADSS0 0 read-write TS1 Bit1 of ADSS0 1 read-write TS2 Bit2 of ADSS0 2 read-write TS3 Bit3 of ADSS0 3 read-write TS4 Bit4 of ADSS0 4 read-write TS5 Bit5 of ADSS0 5 read-write TS6 Bit6 of ADSS0 6 read-write TS7 Bit7 of ADSS0 7 read-write ADSS1 Sampling Time Selection Register 1 0x2D 8 read-write n 0x0 0x0 TS10 Bit2 of ADSS1 2 read-write TS11 Bit3 of ADSS1 3 read-write TS12 Bit4 of ADSS1 4 read-write TS13 Bit5 of ADSS1 5 read-write TS14 Bit6 of ADSS1 6 read-write TS15 Bit7 of ADSS1 7 read-write TS8 Bit0 of ADSS1 0 read-write TS9 Bit1 of ADSS1 1 read-write ADSS2 Sampling Time Selection Register 2 0x28 8 read-write n 0x0 0x0 TS16 Bit0 of ADSS2 0 read-write TS17 Bit1 of ADSS2 1 read-write TS18 Bit2 of ADSS2 2 read-write TS19 Bit3 of ADSS2 3 read-write TS20 Bit4 of ADSS2 4 read-write TS21 Bit5 of ADSS2 5 read-write TS22 Bit6 of ADSS2 6 read-write TS23 Bit7 of ADSS2 7 read-write ADSS3 Sampling Time Selection Register 3 0x29 8 read-write n 0x0 0x0 TS24 Bit0 of ADSS3 0 read-write TS25 Bit1 of ADSS3 1 read-write TS26 Bit2 of ADSS3 2 read-write TS27 Bit3 of ADSS3 3 read-write TS28 Bit4 of ADSS3 4 read-write TS29 Bit5 of ADSS3 5 read-write TS30 Bit6 of ADSS3 6 read-write TS31 Bit7 of ADSS3 7 read-write ADST0 Sampling Time Setup Register 0 0x31 8 read-write n 0x0 0x0 ST0 Sampling time setting bits 0 4 read-write STX0 Sampling time N times setting bits 5 2 read-write ADST1 Sampling Time Setup Register 1 0x30 8 read-write n 0x0 0x0 ST1 Sampling time setting bits 0 4 read-write STX1 Sampling time N times setting bits 5 2 read-write CMPCR A/D Comparison Control Register 0x24 8 read-write n 0x0 0x0 CCH Comparison target analog input channel 0 4 read-write CMD0 Comparison mode 0 5 read-write CMD1 Comparison mode 1 6 read-write CMPEN Conversion result comparison function operation enable bit 7 read-write CMPD A/D Comparison Value Setup Register 0x26 16 read-write n 0x0 0x0 CMAD A/D conversion result value setting bits 6 9 read-write PCCR Priority Conversion Control Register 0x19 8 read-write n 0x0 0x0 ESCE External trigger analog input selection bit 3 read-write PEEN Priority conversion external start enable bit 2 read-write PEMP Priority conversion FIFO empty bit 7 read-only PFCLR Priority conversion FIFO clear bit 4 read-write PFUL Priority conversion FIFO full bit 6 read-only PHEN Priority conversion timer start enable bit 1 read-write POVR Priority conversion overrun flag 5 read-write PSTR Priority conversion start bit 0 read-write PCFD Priority Conversion FIFO Data Register 0x1C 32 read-only n 0x0 0x0 INVL A/D conversion result disable bit 12 read-only PC Conversion input channel bits 0 4 read-only PD Priority conversion result 20 11 read-only RS Scan conversion start factor 8 2 read-only PCIS Priority Conversion Input Selection Register 0x20 8 read-write n 0x0 0x0 P1A Priority level 1 analog input selection 0 2 read-write P2A Priority level 2 analog input selection 3 4 read-write PFNS Priority Conversion FIFO Stage Count Setup Register 0x18 8 read-write n 0x0 0x0 PFS Priority conversion FIFO stage count setting bits 0 1 read-write TEST Test bits 4 1 read-only PRTSL Priority Conversion Timer Trigger Selection Register 0x38 8 read-write n 0x0 0x0 PRTSL Priority conversion timer trigger selection bit 0 3 read-write SCCR Scan Conversion Control Register 0x9 8 read-write n 0x0 0x0 RPT Scan conversion repeat bit 2 read-write SEMP Scan conversion FIFO empty bit 7 read-only SFCLR Scan conversion FIFO clear bit 4 read-write SFUL Scan conversion FIFO full bit 6 read-only SHEN Scan conversion timer start enable bit 1 read-write SOVR Scan conversion overrun flag 5 read-write SSTR Scan conversion start bit 0 read-write SCFD Scan Conversion FIFO Data Register 0xC 32 read-only n 0x0 0x0 INVL A/D conversion result disable bit 12 read-only RS Scan conversion start factor 8 1 read-only SC Conversion input channel bits 0 4 read-only SD Scan conversion result 20 11 read-only SCIS0 Scan Conversion Input Selection Register 0 0x14 8 read-write n 0x0 0x0 AN0 Bit0 of SCIS0 0 read-write AN1 Bit1 of SCIS0 1 read-write AN2 Bit2 of SCIS0 2 read-write AN3 Bit3 of SCIS0 3 read-write AN4 Bit4 of SCIS0 4 read-write AN5 Bit5 of SCIS0 5 read-write AN6 Bit6 of SCIS0 6 read-write AN7 Bit7 of SCIS0 7 read-write SCIS1 Scan Conversion Input Selection Register 1 0x15 8 read-write n 0x0 0x0 AN10 Bit2 of SCIS1 2 read-write AN11 Bit3 of SCIS1 3 read-write AN12 Bit4 of SCIS1 4 read-write AN13 Bit5 of SCIS1 5 read-write AN14 Bit6 of SCIS1 6 read-write AN15 Bit7 of SCIS1 7 read-write AN8 Bit0 of SCIS1 0 read-write AN9 Bit1 of SCIS1 1 read-write SCIS2 Scan Conversion Input Selection Register 2 0x10 8 read-write n 0x0 0x0 AN16 Bit0 of SCIS2 0 read-write AN17 Bit1 of SCIS2 1 read-write AN18 Bit2 of SCIS2 2 read-write AN19 Bit3 of SCIS2 3 read-write AN20 Bit4 of SCIS2 4 read-write AN21 Bit5 of SCIS2 5 read-write AN22 Bit6 of SCIS2 6 read-write AN23 Bit7 of SCIS2 7 read-write SCIS3 Scan Conversion Input Selection Register 3 0x11 8 read-write n 0x0 0x0 AN24 Bit0 of SCIS3 0 read-write AN25 Bit1 of SCIS3 1 read-write AN26 Bit2 of SCIS3 2 read-write AN27 Bit3 of SCIS3 3 read-write AN28 Bit4 of SCIS3 4 read-write AN29 Bit5 of SCIS3 5 read-write AN30 Bit6 of SCIS3 6 read-write AN31 Bit7 of SCIS3 7 read-write SCTSL Scan Conversion Timer Trigger Selection Register 0x39 8 read-write n 0x0 0x0 SCTSL Scan conversion timer trigger selection bit 0 3 read-write SFNS Scan Conversion FIFO Stage Count Setup Register 0x8 8 read-write n 0x0 0x0 SFS Scan conversion FIFO stage count setting bit 0 3 read-write BT0 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n BTIM 28 PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT1 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT2 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT3 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT4 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT5 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT6 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT7 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BTIOSEL03 Base Timer I/O Select BTIOSEL03 0x0 0x0 0x2 registers n BTSEL0123 I/O Select Register 0x0 16 read-write n 0x0 0x0 SEL01_ I/O select bits for Ch.0/Ch.1 8 3 read-write SEL23_ I/O select bits for Ch.2/Ch.3 12 3 read-write BTIOSEL47 Base Timer I/O Select BTIOSEL47 0x0 0x0 0x2 registers n BTSEL4567 I/O Select Register 0x0 16 read-write n 0x0 0x0 SEL45_ I/O select bits for Ch.4/Ch.5 8 3 read-write SEL67_ I/O select bits for Ch.6/Ch.7 12 3 read-write CRG Clock Unit Registers CRG 0x0 0x0 0x1 registers n 0x10 0x1 registers n 0x14 0x1 registers n 0x18 0x1 registers n 0x1C 0x1 registers n 0x20 0x1 registers n 0x28 0x1 registers n 0x30 0x1 registers n 0x34 0x1 registers n 0x38 0x1 registers n 0x3C 0x1 registers n 0x4 0x1 registers n 0x40 0x2 registers n 0x44 0x1 registers n 0x48 0x2 registers n 0x4C 0x2 registers n 0x50 0x2 registers n 0x54 0x1 registers n 0x60 0x1 registers n 0x64 0x1 registers n 0x68 0x1 registers n 0x8 0x6 registers n CSV 0 OSC_PLL_RTC 23 APBC0_PSR APB0 Prescaler Register 0x14 8 read-write n 0x0 0x0 APBC0 APB0 bus clock frequency division ratio setting bit 0 1 read-write APBC1_PSR APB1 Prescaler Register 0x18 8 read-write n 0x0 0x0 APBC1 APB1 bus clock frequency division ratio setting bit 0 1 read-write APBC1EN APB1 clock enable bit 7 read-write APBC1RST APB1 bus reset control bit 4 read-write APBC2_PSR APB2 Prescaler Register 0x1C 8 read-write n 0x0 0x0 APBC2 APB2 bus clock frequency division ratio setting bit 0 1 read-write APBC2EN APB2 clock enable bit 7 read-write APBC2RST APB2 bus reset control bit 4 read-write BSC_PSR Base Clock Prescaler Register 0x10 8 read-write n 0x0 0x0 BSR Base clock frequency division ratio setting bit 0 2 read-write CSV_CTL CSV control register 0x40 16 read-write n 0x0 0x0 FCD FCS count cycle setting bits 12 2 read-write FCSDE FCS function enable bit 8 read-write FCSRE FCS reset output enable bit 9 read-write MCSVE Main CSV function enable bit 0 read-write SCSVE Sub CSV function enable bit 1 read-write CSV_STR CSV status register 0x44 8 read-only n 0x0 0x0 MCMF Main clock failure detection flag 0 read-only SCMF Sub clock failure detection flag 1 read-only CSW_TMR Clock Stabilization Wait Time Register 0x30 8 read-write n 0x0 0x0 MOWT Main clock stabilization wait time setup bit 0 3 read-write SOWT Sub clock stabilization wait time setup bit 4 2 read-write DBWDT_CTL Debug Break Watchdog Timer Control Register 0x54 8 read-write n 0x0 0x0 DPHWBE HW-WDG debug mode break bit 7 read-write DPSWBE SW-WDG debug mode break bit 5 read-write FCSWD_CTL Frequency detection counter register 0x50 16 read-only n 0x0 0x0 FCSWH_CTL Frequency detection window setting register 0x48 16 read-write n 0x0 0x0 FCSWL_CTL Frequency detection window setting register 0x4C 16 read-write n 0x0 0x0 INT_CLR Interrupt Clear Register 0x68 8 write-only n 0x0 0x0 FCSC Anomalous frequency detection interrupt cause clear bit 5 write-only MCSC Main oscillation stabilization completion interrupt cause clear bit 0 write-only PCSC PLL oscillation stabilization completion interrupt cause clear bit 2 write-only SCSC Sub oscillation stabilization completion interrupt cause clear bit 1 write-only INT_ENR Interrupt Enable Register 0x60 8 read-write n 0x0 0x0 FCSE Anomalous frequency detection interrupt enable bit 5 read-write MCSE Main oscillation stabilization completion interrupt enable bit 0 read-write PCSE PLL oscillation stabilization completion interrupt enable bit 2 read-write SCSE Sub oscillation stabilization completion interrupt enable bit 1 read-write INT_STR Interrupt Status Register 0x64 8 read-only n 0x0 0x0 FCSI Anomalous frequency detection interrupt status bit 5 read-only MCSI Main oscillation stabilization completion interrupt status bit 0 read-only PCSI PLL oscillation stabilization completion interrupt status bit 2 read-only SCSI Sub oscillation stabilization completion interrupt status bit 1 read-only PLL_CTL1 PLL Control Register 1 0x38 8 read-write n 0x0 0x0 PLLK PLL input clock frequency division ratio setting bit 4 3 read-write PLLM PLL VCO clock frequency division ratio setting bit 0 3 read-write PLL_CTL2 PLL Control Register 2 0x3C 8 read-write n 0x0 0x0 PLLN PLL feedback frequency division ratio setting bit 0 5 read-write PSW_TMR PLL Clock Stabilization Wait Time Setup Register 0x34 8 read-write n 0x0 0x0 PINC PLL input clock select bit 4 read-write POWT PLL clock stabilization wait time setup bit 0 2 read-write RST_STR Reset Cause Register 0xC 16 read-only n 0x0 0x0 CSVR Clock failure detection reset flag 6 read-only FCSR Flag for anomalous frequency detection reset 7 read-only HWDT Hardware watchdog reset flag 5 read-only INITX INITX pin input reset flag 1 read-only LVDH Low-voltage detection reset flag 3 read-only PONR Power-on reset/low-voltage detection reset flag 0 read-only SRST Software reset flag 8 read-only SWDT Software watchdog reset flag 4 read-only SCM_CTL System Clock Mode Control Register 0x0 8 read-write n 0x0 0x0 MOSCE Main clock oscillation enable bit 1 read-write PLLE PLL oscillation enable bit 4 read-write RCS Master clock switch control bits 5 2 read-write SOSCE Sub clock oscillation enable bit 3 read-write SCM_STR System Clock Mode Status Register 0x4 8 read-only n 0x0 0x0 MORDY Main clock oscillation stable bit 1 read-only PLRDY PLL oscillation stable bit 4 read-only RCM Master clock selection bits 5 2 read-only SORDY Sub clock oscillation stable bit 3 read-only STB_CTL Standby Mode Control Register 0x8 32 read-write n 0x0 0x0 DSTM Deep standby mode select bit 2 read-write KEY Standby mode control write control bit 16 15 read-write SPL Standby pin level setting bit 4 read-write STM Standby mode selection bit 0 1 read-write SWC_PSR Software Watchdog Clock Prescaler Register 0x20 8 read-write n 0x0 0x0 SWDS Software watchdog clock frequency division ratio setting bit 0 1 read-write TESTB TEST bit 7 read-write TTC_PSR Trace Clock Prescaler Register 0x28 8 read-write n 0x0 0x0 TTC Trace clock frequency division ratio setting bit 0 1 read-write CRTRIM CR Trimming Registers CRTRIM 0x0 0x0 0x1 registers n 0x4 0x2 registers n 0xC 0x4 registers n MCR_FTRM High-speed CR oscillation Frequency Trimming Register 0x4 16 read-write n 0x0 0x0 TRD Frequency trimming setup bits 0 9 read-write MCR_PSR High-speed CR oscillation Frequency Division Setup Register 0x0 8 read-write n 0x0 0x0 CSR High-speed CR oscillation frequency division ratio setting bits 0 2 read-write MCR_RLR High-Speed CR Oscillation Register Write-Protect Register 0xC 32 read-write n 0x0 0x0 TRMLCK Register write-protect bits 0 31 read-write DAC D/A Converter DAC 0x0 0x0 0x3 registers n 0x4 0x3 registers n DACR0 D/A Control Register 0x2 8 read-write n 0x0 0x0 DAE D/A converter operation enable bit 0 read-write DACR1 D/A Control Register 0x6 8 read-write n 0x0 0x0 DAE D/A converter operation enable bit 0 read-write DADR0 D/A Data Register 0x0 16 read-write n 0x0 0x0 DA0 Bit0 of DADR0 0 read-write DA1 Bit1 of DADR0 1 read-write DA2 Bit2 of DADR0 2 read-write DA3 Bit3 of DADR0 3 read-write DA4 Bit4 of DADR0 4 read-write DA5 Bit5 of DADR0 5 read-write DA6 Bit6 of DADR0 6 read-write DA7 Bit7 of DADR0 7 read-write DA8 Bit8 of DADR0 8 read-write DA9 Bit9 of DADR0 9 read-write DADR1 D/A Data Register 0x4 16 read-write n 0x0 0x0 DA0 Bit0 of DADR1 0 read-write DA1 Bit1 of DADR1 1 read-write DA2 Bit2 of DADR1 2 read-write DA3 Bit3 of DADR1 3 read-write DA4 Bit4 of DADR1 4 read-write DA5 Bit5 of DADR1 5 read-write DA6 Bit6 of DADR1 6 read-write DA7 Bit7 of DADR1 7 read-write DA8 Bit8 of DADR1 8 read-write DA9 Bit9 of DADR1 9 read-write DS Low Power Consumption Mode DS 0x0 0x4 0x1 registers n 0x700 0x1 registers n 0x704 0x1 registers n 0x708 0x2 registers n 0x70C 0x2 registers n 0x710 0x1 registers n 0x800 0x16 registers n BUR01 Backup Registers from 1 0x800 8 read-write n 0x0 0x0 BUR02 Backup Registers from 2 0x801 8 read-write n 0x0 0x0 BUR03 Backup Registers from 3 0x802 8 read-write n 0x0 0x0 BUR04 Backup Registers from 4 0x803 8 read-write n 0x0 0x0 BUR05 Backup Registers from 5 0x804 8 read-write n 0x0 0x0 BUR06 Backup Registers from 6 0x805 8 read-write n 0x0 0x0 BUR07 Backup Registers from 7 0x806 8 read-write n 0x0 0x0 BUR08 Backup Registers from 8 0x807 8 read-write n 0x0 0x0 BUR09 Backup Registers from 9 0x808 8 read-write n 0x0 0x0 BUR10 Backup Registers from 10 0x809 8 read-write n 0x0 0x0 BUR11 Backup Registers from 11 0x80A 8 read-write n 0x0 0x0 BUR12 Backup Registers from 12 0x80B 8 read-write n 0x0 0x0 BUR13 Backup Registers from 13 0x80C 8 read-write n 0x0 0x0 BUR14 Backup Registers from 14 0x80D 8 read-write n 0x0 0x0 BUR15 Backup Registers from 15 0x80E 8 read-write n 0x0 0x0 BUR16 Backup Registers from 16 0x80F 8 read-write n 0x0 0x0 PMD_CTL RTC Mode Control Register 0x700 8 read-write n 0x0 0x0 RTCE RTC mode control bit 0 read-write RCK_CTL Sub Clock Control Register 0x4 8 read-write n 0x0 0x0 CECCKE CEC clock control bit 1 read-write RTCCKE RTC clock control bit 0 read-write WIER Deep Standby Return Enable Register 0x70C 16 read-write n 0x0 0x0 WCEC0E HDMI-CEC/ Remote Control Reception ch.0 interrupt return enable bit 8 read-write WCEC1E HDMI-CEC/ Remote Control Reception ch.1 interrupt return enable bit 9 read-write WLVDE LVD interrupt return enable bit 1 read-write WRTCE RTC interrupt return enable bit 0 read-write WUI1E WKUP pin input return enable bit 1 3 read-write WUI2E WKUP pin input return enable bit 2 4 read-write WUI3E WKUP pin input return enable bit 3 5 read-write WIFSR Deep Standby Return Cause Register 2 0x708 16 read-only n 0x0 0x0 WCEC0I CEC ch.0 interrupt return bit 8 read-only WCEC1I CEC ch.1 interrupt return bit 9 read-only WLVDI LVD interrupt return bit 1 read-only WRTCI RTC interrupt return bit 0 read-only WUI0 WKUP pin input return bit 0 2 read-only WUI1 WKUP pin input return bit 1 3 read-only WUI2 WKUP pin input return bit 2 4 read-only WUI3 WKUP pin input return bit 3 5 read-only WILVR WKUP Pin Input Level Register 0x710 8 read-write n 0x0 0x0 WUI1LV WKUP pin input level select bit 1 0 read-write WUI2LV WKUP pin input level select bit 2 1 read-write WUI3LV WKUP pin input level select bit 3 2 read-write WRFSR Deep Standby Return Cause Register 1 0x704 8 read-write n 0x0 0x0 WINITX INITX pin input reset return bit 0 read-write WLVDH Low-voltage detection reset return bit 1 read-write EXTI External Interrupt and NMI Control EXTI 0x0 0x0 0x2 registers n 0x14 0x1 registers n 0x18 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x4 registers n EXTINT0_7 4 EXTINT8_15 5 EICL External Interrupt Clear Register 0x8 16 read-write n 0x0 0x0 ECL0 Bit0 of EICL 0 read-write ECL1 Bit1 of EICL 1 read-write ECL14 Bit14 of EICL 14 read-write ECL15 Bit15 of EICL 15 read-write ECL2 Bit2 of EICL 2 read-write ECL3 Bit3 of EICL 3 read-write ECL4 Bit4 of EICL 4 read-write ECL5 Bit5 of EICL 5 read-write ECL6 Bit6 of EICL 6 read-write ECL7 Bit7 of EICL 7 read-write ECL8 Bit8 of EICL 8 read-write EIRR External Interrupt Request Register 0x4 16 read-only n 0x0 0x0 ER0 Bit0 of EIRR 0 read-only ER1 Bit1 of EIRR 1 read-only ER14 Bit14 of EIRR 14 read-only ER15 Bit15 of EIRR 15 read-only ER2 Bit2 of EIRR 2 read-only ER3 Bit3 of EIRR 3 read-only ER4 Bit4 of EIRR 4 read-only ER5 Bit5 of EIRR 5 read-only ER6 Bit6 of EIRR 6 read-only ER7 Bit7 of EIRR 7 read-only ER8 Bit8 of EIRR 8 read-only ELVR External Interrupt Level Register 0xC 32 read-write n 0x0 0x0 LA0 Bit0 of ELVR 0 read-write LA1 Bit2 of ELVR 2 read-write LA14 Bit28 of ELVR 28 read-write LA15 Bit30 of ELVR 30 read-write LA2 Bit4 of ELVR 4 read-write LA3 Bit6 of ELVR 6 read-write LA4 Bit8 of ELVR 8 read-write LA5 Bit10 of ELVR 10 read-write LA6 Bit12 of ELVR 12 read-write LA7 Bit14 of ELVR 14 read-write LA8 Bit16 of ELVR 16 read-write LB0 Bit1 of ELVR 1 read-write LB1 Bit3 of ELVR 3 read-write LB14 Bit29 of ELVR 29 read-write LB15 Bit31 of ELVR 31 read-write LB2 Bit5 of ELVR 5 read-write LB3 Bit7 of ELVR 7 read-write LB4 Bit9 of ELVR 9 read-write LB5 Bit11 of ELVR 11 read-write LB6 Bit13 of ELVR 13 read-write LB7 Bit15 of ELVR 15 read-write LB8 Bit17 of ELVR 17 read-write ENIR Enable Interrupt Request Register 0x0 16 read-write n 0x0 0x0 EN0 Bit0 of ENIR 0 read-write EN1 Bit1 of ENIR 1 read-write EN14 Bit14 of ENIR 14 read-write EN15 Bit15 of ENIR 15 read-write EN2 Bit2 of ENIR 2 read-write EN3 Bit3 of ENIR 3 read-write EN4 Bit4 of ENIR 4 read-write EN5 Bit5 of ENIR 5 read-write EN6 Bit6 of ENIR 6 read-write EN7 Bit7 of ENIR 7 read-write EN8 Bit8 of ENIR 8 read-write NMICL Non Maskable Interrupt Clear Register 0x18 8 read-write n 0x0 0x0 NCL NMI interrupt cause clear bit 0 read-write NMIRR Non Maskable Interrupt Request Register 0x14 8 read-only n 0x0 0x0 NR NMI interrupt request detection bit 0 read-only FLASH_IF Flash Memory FLASH_IF 0x0 0x0 0x4 registers n 0x10 0x4 registers n 0x100 0x4 registers n 0x8 0x4 registers n CRTRMM CR Trimming Data Mirror Register 0x100 32 read-only n 0x0 0x0 TRMM CR Trimming Data Mirror 0 9 read-only FASZR Flash Access Size Register 0x0 32 read-write n 0x0 0x0 ASZ Flash Access Size 0 1 read-write FSTR Flash Status Register 0x8 32 read-only n 0x0 0x0 HNG Flash Hang flag 1 read-only RDY Flash Rdy 0 read-only FSYNDN Flash Sync Down Register 0x10 32 read-write n 0x0 0x0 SD Flash Sync 0 2 read-write GPIO General-purpose I/O ports GPIO 0x0 0x0 0x740 registers n ADE Analog input setting register 0x500 32 read-write n 0x0 0x0 AN0 Bit0 of ADE 0 read-write AN1 Bit1 of ADE 1 read-write AN10 Bit10 of ADE 10 read-write AN11 Bit11 of ADE 11 read-write AN2 Bit2 of ADE 2 read-write AN3 Bit3 of ADE 3 read-write AN4 Bit4 of ADE 4 read-write AN5 Bit5 of ADE 5 read-write AN6 Bit6 of ADE 6 read-write AN7 Bit7 of ADE 7 read-write AN8 Bit8 of ADE 8 read-write AN9 Bit9 of ADE 9 read-write DDR0 Port input/output direction setting register 0 0x200 32 read-write n 0x0 0x0 P0 Bit0 of DDR0 0 read-write P1 Bit1 of DDR0 1 read-write P2 Bit2 of DDR0 2 read-write P3 Bit3 of DDR0 3 read-write P4 Bit4 of DDR0 4 read-write P7 Bit7 of DDR0 7 read-write PA Bit10 of DDR0 10 read-write PB Bit11 of DDR0 11 read-write PC Bit12 of DDR0 12 read-write PD Bit13 of DDR0 13 read-write PE Bit14 of DDR0 14 read-write PF Bit15 of DDR0 15 read-write DDR1 Port input/output direction setting register 1 0x204 read-write n 0x0 0x0 DDR2 Port input/output direction setting register 2 0x208 read-write n 0x0 0x0 DDR3 Port input/output direction setting register 3 0x20C read-write n 0x0 0x0 DDR4 Port input/output direction setting register 4 0x210 read-write n 0x0 0x0 DDR5 Port input/output direction setting register 5 0x214 read-write n 0x0 0x0 DDR6 Port input/output direction setting register 6 0x218 read-write n 0x0 0x0 DDR8 Port input/output direction setting register 8 0x220 read-write n 0x0 0x0 DDRE Port input/output direction setting register E 0x238 read-write n 0x0 0x0 EPFR00 Extended pin function setting register 00 0x600 32 read-write n 0x0 0x0 CROUTE Internal high-speed CR oscillation output function select bit 1 1 read-write JTAGEN0B JTAG function select bit0 16 read-write JTAGEN1S JTAG function select bit1 17 read-write NMIS NMIX function select bit 0 read-write RTCCOE RTC clock output select bit 4 1 read-write SUBOUTE Sub clock divide output function select bit 6 1 read-write EPFR01 Extended pin function setting register 01 0x604 32 read-write n 0x0 0x0 DTTI0C DTTIX0 function select bit 12 read-write DTTI0S DTTIX0 input select bit 16 1 read-write FRCK0S FRCK0 input select bit 18 1 read-write IC00S IC00 input select bit 20 2 read-write IC01S IC01 input select bit 23 2 read-write IC02S IC02 input select bit 26 2 read-write IC03S IC03 input select bit 29 2 read-write RTO00E RTO00E output select bit 0 1 read-write RTO01E RTO01E output select bit 2 1 read-write RTO02E RTO02E output select bit 4 1 read-write RTO03E RTO03E output select bit 6 1 read-write RTO04E RTO04E output select bit 8 1 read-write RTO05E RTO05E output select bit 10 1 read-write EPFR04 Extended pin function setting register 04 0x610 32 read-write n 0x0 0x0 TIOA0E TIOA0 output select bit 2 1 read-write TIOA1E TIOA1E output select bit 10 1 read-write TIOA1S TIOA1 input select bit 8 1 read-write TIOA2E TIOA2 output select bit 18 1 read-write TIOA3E TIOA3E output select bit 26 1 read-write TIOA3S TIOA3 input select bit 24 1 read-write TIOB0S TIOB0 input select bit 4 2 read-write TIOB1S TIOB1 input select bit 12 1 read-write TIOB2S TIOB2 input select bit 20 1 read-write TIOB3S TIOB3 input select bit 28 1 read-write EPFR05 Extended pin function setting register 05 0x614 32 read-write n 0x0 0x0 TIOA4E TIOA4 output select bit 2 1 read-write TIOA5E TIOA5E output select bit 10 1 read-write TIOA5S TIOA5 input select bit 8 1 read-write TIOA6E TIOA6 output select bit 18 1 read-write TIOA7E TIOA7E output select bit 26 1 read-write TIOA7S TIOA7 input select bit 24 1 read-write TIOB4S TIOB4 input select bit 4 1 read-write TIOB5S TIOB5 input select bit 12 1 read-write TIOB6S TIOB6 input select bit 20 1 read-write TIOB7S TIOB7 input select Bit 28 1 read-write EPFR06 Extended pin function setting register 06 0x618 32 read-write n 0x0 0x0 EINT00S External interrupt 0 input select bit 0 1 read-write EINT01S External interrupt 1 input select bit 2 1 read-write EINT02S External interrupt 2 input select bit 4 1 read-write EINT03S External interrupt 3 input select bit 6 1 read-write EINT04S External interrupt 4 input select bit 8 1 read-write EINT05S External interrupt 5 input select bit 10 1 read-write EINT06S External interrupt 6 input select bit 12 1 read-write EINT07S External interrupt 7 input select bit 14 1 read-write EINT08S External interrupt 8 input select bit 16 1 read-write EINT14S External interrupt 14 input select bit 28 1 read-write EINT15S External interrupt 15 input select bit 30 1 read-write EPFR07 Extended pin function setting register 07 0x61C 32 read-write n 0x0 0x0 SCK0B SCK0 input/output select bit 8 1 read-write SCK1B SCK1 input/output select bit 14 1 read-write SCK2B SCK2 input/output select bit 20 1 read-write SCK3B SCK3 input/output select bit 26 1 read-write SIN0S SIN0S input select bit 4 1 read-write SIN1S SIN1S input select bit 10 1 read-write SIN2S SIN2S input select bit 16 1 read-write SIN3S SIN3S input select bit 22 1 read-write SOT0B SOT0B input/output select bit 6 1 read-write SOT1B SCK1B input/output select bit 12 1 read-write SOT2B SOT2B input/output select bit 18 1 read-write SOT3B SOT3B input/output select bit 24 1 read-write EPFR08 Extended pin function setting register 08 0x620 32 read-write n 0x0 0x0 CTS4S CTS4S Input Select bits 2 1 read-write RTS4E RTS4E Output Select bits 0 1 read-write SCK4B SCK4 input/output select bit 8 1 read-write SCK5B SCK5 input/output select bit 14 1 read-write SCK6B SCK6 input/output select bit 20 1 read-write SCK7B SCK7 input/output select bit 26 1 read-write SIN4S SIN4S input select bit 4 1 read-write SIN5S SIN5S input select bit 10 1 read-write SIN6S SIN6S input select bit 16 1 read-write SIN7S SIN7S input select bit 22 1 read-write SOT4B SOT4B input/output select bit 6 1 read-write SOT5B SOT5B input/output select bit 12 1 read-write SOT6B SOT6B input/output select bit 18 1 read-write SOT7B SOT7B input/output select bit 24 1 read-write EPFR09 Extended pin function setting register 09 0x624 32 read-write n 0x0 0x0 ADTRG0S ADTRG0 input select bit 12 3 read-write EPFR14 Extended pin function setting register 14 0x638 32 read-write n 0x0 0x0 CEC0B CEC0 Input/Output Select bit 30 read-write CEC1B CEC1 Input/Output Select bit 31 read-write PCR0 Pull-up Setting Register 0 0x100 read-write n 0x0 0x0 PCR1 Pull-up Setting Register 1 0x104 read-write n 0x0 0x0 PCR2 Pull-up Setting Register 2 0x108 read-write n 0x0 0x0 PCR3 Pull-up Setting Register 3 0x10C read-write n 0x0 0x0 PCR4 Pull-up Setting Register 4 0x110 read-write n 0x0 0x0 PCR5 Pull-up Setting Register 5 0x114 read-write n 0x0 0x0 PCR6 Pull-up Setting Register 6 0x118 read-write n 0x0 0x0 PCRE Pull-up Setting Register E 0x138 read-write n 0x0 0x0 PDIR0 Port input data register 0 0x300 read-write n 0x0 0x0 PDIR1 Port input data register 1 0x304 read-write n 0x0 0x0 PDIR2 Port input data register 2 0x308 read-write n 0x0 0x0 PDIR3 Port input data register 3 0x30C read-write n 0x0 0x0 PDIR4 Port input data register 4 0x310 read-write n 0x0 0x0 PDIR5 Port input data register 5 0x314 read-write n 0x0 0x0 PDIR6 Port input data register 6 0x318 read-write n 0x0 0x0 PDIR8 Port input data register 8 0x320 read-write n 0x0 0x0 PDIRE Port input data register E 0x338 read-write n 0x0 0x0 PDOR0 Port output data register 0 0x400 read-write n 0x0 0x0 PDOR1 Port output data register 1 0x404 read-write n 0x0 0x0 PDOR2 Port output data register 2 0x408 read-write n 0x0 0x0 PDOR3 Port output data register 3 0x40C read-write n 0x0 0x0 PDOR4 Port output data register 4 0x410 read-write n 0x0 0x0 PDOR5 Port output data register 5 0x414 read-write n 0x0 0x0 PDOR6 Port output data register 6 0x418 read-write n 0x0 0x0 PDOR8 Port output data register 8 0x420 read-write n 0x0 0x0 PDORE Port output data register E 0x438 read-write n 0x0 0x0 PFR0 Port function setting register 0 0x0 32 read-write n 0x0 0x0 P0 Bit0 of PFR0 0 read-write P1 Bit1 of PFR0 1 read-write P2 Bit2 of PFR0 2 read-write P3 Bit3 of PFR0 3 read-write P4 Bit4 of PFR0 4 read-write P7 Bit7 of PFR0 7 read-write PA Bit10 of PFR0 10 read-write PB Bit11 of PFR0 11 read-write PC Bit12 of PFR0 12 read-write PD Bit13 of PFR0 13 read-write PE Bit14 of PFR0 14 read-write PF Bit15 of PFR0 15 read-write PFR1 Port function setting register 1 0x4 32 read-write n 0x0 0x0 P0 Bit0 of PFR1 0 read-write P1 Bit1 of PFR1 1 read-write P2 Bit2 of PFR1 2 read-write P3 Bit3 of PFR1 3 read-write P4 Bit4 of PFR1 4 read-write P5 Bit5 of PFR1 5 read-write P6 Bit6 of PFR1 6 read-write P7 Bit7 of PFR1 7 read-write P8 Bit8 of PFR1 8 read-write P9 Bit9 of PFR1 9 read-write PA Bit10 of PFR1 10 read-write PB Bit11 of PFR1 11 read-write PFR2 Port function setting register 2 0x8 32 read-write n 0x0 0x0 P0 Bit0 of PFR2 0 read-write P1 Bit1 of PFR2 1 read-write P2 Bit2 of PFR2 2 read-write P3 Bit3 of PFR2 3 read-write PFR3 Port function setting register 3 0xC 32 read-write n 0x0 0x0 P0 Bit0 of PFR3 0 read-write P1 Bit1 of PFR3 1 read-write P2 Bit2 of PFR3 2 read-write P3 Bit3 of PFR3 3 read-write P9 Bit9 of PFR3 9 read-write PA Bit10 of PFR3 10 read-write PB Bit11 of PFR3 11 read-write PC Bit12 of PFR3 12 read-write PD Bit13 of PFR3 13 read-write PE Bit14 of PFR3 14 read-write PF Bit15 of PFR3 15 read-write PFR4 Port function setting register 4 0x10 32 read-write n 0x0 0x0 P4 Bit4 of PFR4 4 read-write P5 Bit5 of PFR4 5 read-write P6 Bit6 of PFR4 6 read-write P7 Bit7 of PFR4 7 read-write P8 Bit8 of PFR4 8 read-write P9 Bit9 of PFR4 9 read-write PA Bit10 of PFR4 10 read-write PB Bit11 of PFR4 11 read-write PC Bit12 of PFR4 12 read-write PD Bit13 of PFR4 13 read-write PE Bit14 of PFR4 14 read-write PFR5 Port function setting register 5 0x14 32 read-write n 0x0 0x0 P0 Bit0 of PFR5 0 read-write P1 Bit1 of PFR5 1 read-write P2 Bit2 of PFR5 2 read-write P3 Bit3 of PFR5 3 read-write P4 Bit4 of PFR5 4 read-write P5 Bit5 of PFR5 5 read-write P6 Bit6 of PFR5 6 read-write PFR6 Port function setting register 6 0x18 32 read-write n 0x0 0x0 P0 Bit0 of PFR6 0 read-write P1 Bit1 of PFR6 1 read-write P2 Bit2 of PFR6 2 read-write P3 Bit3 of PFR6 3 read-write PFR8 Port function setting register 8 0x20 32 read-write n 0x0 0x0 P0 Bit0 of PFR8 0 read-write P1 Bit1 of PFR8 1 read-write P2 Bit2 of PFR8 2 read-write PFRE Port function setting register E 0x38 32 read-write n 0x0 0x0 P0 Bit0 of PFRE 0 read-write P2 Bit1 of PFRE 2 read-write P3 Bit2 of PFRE 3 read-write PZR0 Port Pseudo Open Drain Setting Register 0 0x700 32 read-write n 0x0 0x0 PB Bit11 of PZR0 11 read-write PC Bit12 of PZR0 12 read-write PZR6 Port Pseudo Open Drain Setting Register 6 0x718 32 read-write n 0x0 0x0 P0 Bit0 of PZR6 0 read-write PZR8 Port Pseudo Open Drain Setting Register 8 0x720 32 read-write n 0x0 0x0 P1 Bit1 of PZR8 1 read-write P2 Bit2 of PZR8 2 read-write SPSR Special port setting register 0x580 32 read-write n 0x0 0x0 MAINXC Main clock(oscillation) pin setting bit 2 read-write SUBXC Sub clock(oscillation) pin setting bit 0 read-write HDMICEC0 HDMI-CEC ch.0 HDMICEC0 0x0 0x0 0x1 registers n 0x4 0x1 registers n 0x40 0x2 registers n 0x44 0x2 registers n 0x49 0x1 registers n 0x4C 0x2 registers n 0x50 0x2 registers n 0x54 0x2 registers n 0x58 0x2 registers n 0x5C 0x2 registers n 0x61 0x1 registers n 0x64 0x2 registers n 0x8 0x1 registers n 0xC 0x1 registers n HDMICEC0 30 RCADR1 Device Address Setting Register 1 0x4D 8 read-write n 0x0 0x0 RCADR1 Device Address 1 0 4 read-write RCADR2 Device Address Setting Register 2 0x4C 8 read-write n 0x0 0x0 RCADR2 Device Address 2 0 4 read-write RCCKD Clock Division Setting Register 0x58 16 read-write n 0x0 0x0 CKDIV Operating clock division setting bits 0 11 read-write CKSEL Operating clock selection bit 12 read-write RCCR Reception Control Register 0x41 8 read-write n 0x0 0x0 ADRCE Address comparison enable bit 3 read-write EN Operation enable bit 0 read-write MOD0 Operation mode setting bits 1 read-write MOD1 Operation mode setting bits 2 read-write THSEL Threshold selection bit 7 read-write RCDAHW "H" Width Setting Register A 0x44 8 read-write n 0x0 0x0 RCDAHW "H" Width Setting A 0 7 read-write RCDBHW "H" Width Setting Register B 0x49 8 read-write n 0x0 0x0 RCDBHW "H" Width Setting B 0 7 read-write RCDTHH Data Save Register (High-High) 0x51 8 read-only n 0x0 0x0 RCDTHH RCDTHH 0 7 read-only RCDTHL Data Save Register (High-Low) 0x50 8 read-only n 0x0 0x0 RCDTHL RCDTHL 0 7 read-only RCDTLH Data Save Register (Low-High) 0x55 8 read-only n 0x0 0x0 RCDTLH RCDTLH 0 7 read-only RCDTLL Data Save Register (Low-Low) 0x54 8 read-only n 0x0 0x0 RCDTLL RCDTLL 0 7 read-only RCLE Data Bit Width Violation Control Register 0x61 8 read-write n 0x0 0x0 EPE Error pulse output enable bit 3 read-write LEL Maximum data bit width violation detection flag bit 1 read-write LELE Maximum data bit width violation detection enable bit 5 read-write LELIE Maximum data bit width violation interrupt enable bit 7 read-write LES Minimum data bit width violation detection flag bit 0 read-write LESE Minimum data bit width violation detection enable bit 4 read-write LESIE Minimum data bit width violation interrupt enable bit 6 read-write RCLELW Maximum Data Bit Width Setting Register 0x65 8 read-write n 0x0 0x0 RCLELW Maximum data bit width setting bits 0 7 read-write RCLESW Minimum Data Bit Width Setting Register 0x64 8 read-write n 0x0 0x0 RCLESW Minimum data bit width setting bits 0 7 read-write RCRC Repeat Code Interrupt Control Register 0x5D 8 read-write n 0x0 0x0 RC Repeat code detection flag bit 0 read-write RCIE Repeat Code Interrupt enable bit 4 read-write RCRHW Repeat Code "H" Width Setting Register 0x5C 8 read-write n 0x0 0x0 RCRHW "Repeat code "H" width setting bits" 0 7 read-write RCSHW Start Bit "H" Width Setting Register 0x45 8 read-write n 0x0 0x0 RCSHW Start Bit "H" Width Setting 0 7 read-write RCST Reception Interrupt Control Register 0x40 8 read-write n 0x0 0x0 ACK ACK: ACK detection bit 2 read-write ACKIE ACK interrupt enable bit 6 read-write EOM EOM detection bit 1 read-write OVF Counter overflow detection bit 0 read-write OVFIE Counter overflow interrupt enable bit 5 read-write OVFSEL Counter overflow detection condition setting bit 4 read-write ST Start bit detection bit 3 read-write STIE Start bit interrupt enable bit 7 read-write SFREE Signal Free Time Setting Register 0xC 8 read-write n 0x0 0x0 SFREE Signal free time setting bits 0 3 read-write TXCTRL Transmission Control Register 0x0 8 read-write n 0x0 0x0 EOM EOM setting bit 3 read-write IBREN Bus error detection interrupt enable bit 5 read-write ITSTEN transmission status interrupt enable bit 4 read-write START START setting bit 2 read-write TXEN Transmission operation enable bit 0 read-write TXDATA Transmission Data Register 0x4 8 read-write n 0x0 0x0 TXDATA Transmission Data 0 7 read-write TXSTS Transmission Status Register 0x8 8 read-write n 0x0 0x0 ACKSV ACK cycle value bit 0 read-write IBR Bus error detection interrupt request bit 5 read-write ITST Transmission status interrupt request bit 4 read-write HDMICEC1 HDMI-CEC ch.0 HDMICEC0 0x0 0x0 0x1 registers n 0x4 0x1 registers n 0x40 0x2 registers n 0x44 0x2 registers n 0x49 0x1 registers n 0x4C 0x2 registers n 0x50 0x2 registers n 0x54 0x2 registers n 0x58 0x2 registers n 0x5C 0x2 registers n 0x61 0x1 registers n 0x64 0x2 registers n 0x8 0x1 registers n 0xC 0x1 registers n HDMICEC1 31 RCADR1 Device Address Setting Register 1 0x4D 8 read-write n 0x0 0x0 RCADR1 Device Address 1 0 4 read-write RCADR2 Device Address Setting Register 2 0x4C 8 read-write n 0x0 0x0 RCADR2 Device Address 2 0 4 read-write RCCKD Clock Division Setting Register 0x58 16 read-write n 0x0 0x0 CKDIV Operating clock division setting bits 0 11 read-write CKSEL Operating clock selection bit 12 read-write RCCR Reception Control Register 0x41 8 read-write n 0x0 0x0 ADRCE Address comparison enable bit 3 read-write EN Operation enable bit 0 read-write MOD0 Operation mode setting bits 1 read-write MOD1 Operation mode setting bits 2 read-write THSEL Threshold selection bit 7 read-write RCDAHW "H" Width Setting Register A 0x44 8 read-write n 0x0 0x0 RCDAHW "H" Width Setting A 0 7 read-write RCDBHW "H" Width Setting Register B 0x49 8 read-write n 0x0 0x0 RCDBHW "H" Width Setting B 0 7 read-write RCDTHH Data Save Register (High-High) 0x51 8 read-only n 0x0 0x0 RCDTHH RCDTHH 0 7 read-only RCDTHL Data Save Register (High-Low) 0x50 8 read-only n 0x0 0x0 RCDTHL RCDTHL 0 7 read-only RCDTLH Data Save Register (Low-High) 0x55 8 read-only n 0x0 0x0 RCDTLH RCDTLH 0 7 read-only RCDTLL Data Save Register (Low-Low) 0x54 8 read-only n 0x0 0x0 RCDTLL RCDTLL 0 7 read-only RCLE Data Bit Width Violation Control Register 0x61 8 read-write n 0x0 0x0 EPE Error pulse output enable bit 3 read-write LEL Maximum data bit width violation detection flag bit 1 read-write LELE Maximum data bit width violation detection enable bit 5 read-write LELIE Maximum data bit width violation interrupt enable bit 7 read-write LES Minimum data bit width violation detection flag bit 0 read-write LESE Minimum data bit width violation detection enable bit 4 read-write LESIE Minimum data bit width violation interrupt enable bit 6 read-write RCLELW Maximum Data Bit Width Setting Register 0x65 8 read-write n 0x0 0x0 RCLELW Maximum data bit width setting bits 0 7 read-write RCLESW Minimum Data Bit Width Setting Register 0x64 8 read-write n 0x0 0x0 RCLESW Minimum data bit width setting bits 0 7 read-write RCRC Repeat Code Interrupt Control Register 0x5D 8 read-write n 0x0 0x0 RC Repeat code detection flag bit 0 read-write RCIE Repeat Code Interrupt enable bit 4 read-write RCRHW Repeat Code "H" Width Setting Register 0x5C 8 read-write n 0x0 0x0 RCRHW "Repeat code "H" width setting bits" 0 7 read-write RCSHW Start Bit "H" Width Setting Register 0x45 8 read-write n 0x0 0x0 RCSHW Start Bit "H" Width Setting 0 7 read-write RCST Reception Interrupt Control Register 0x40 8 read-write n 0x0 0x0 ACK ACK: ACK detection bit 2 read-write ACKIE ACK interrupt enable bit 6 read-write EOM EOM detection bit 1 read-write OVF Counter overflow detection bit 0 read-write OVFIE Counter overflow interrupt enable bit 5 read-write OVFSEL Counter overflow detection condition setting bit 4 read-write ST Start bit detection bit 3 read-write STIE Start bit interrupt enable bit 7 read-write SFREE Signal Free Time Setting Register 0xC 8 read-write n 0x0 0x0 SFREE Signal free time setting bits 0 3 read-write TXCTRL Transmission Control Register 0x0 8 read-write n 0x0 0x0 EOM EOM setting bit 3 read-write IBREN Bus error detection interrupt enable bit 5 read-write ITSTEN transmission status interrupt enable bit 4 read-write START START setting bit 2 read-write TXEN Transmission operation enable bit 0 read-write TXDATA Transmission Data Register 0x4 8 read-write n 0x0 0x0 TXDATA Transmission Data 0 7 read-write TXSTS Transmission Status Register 0x8 8 read-write n 0x0 0x0 ACKSV ACK cycle value bit 0 read-write IBR Bus error detection interrupt request bit 5 read-write ITST Transmission status interrupt request bit 4 read-write HWWDT Hardware Watchdog Timer HWWDT 0x0 0x0 0x4 registers n 0x10 0x1 registers n 0x4 0x4 registers n 0x8 0x4 registers n 0xC 0x1 registers n 0xC00 0x4 registers n WDG_CTL Hardware Watchdog Timer Control Register 0x8 8 read-write n 0x0 0x0 INTEN Hardware watchdog interrupt and counter enable bit 0 read-write RESEN Hardware watchdog reset enable bit 1 read-write WDG_ICL Hardware Watchdog Timer Clear Register 0xC 8 read-write n 0x0 0x0 WDG_LCK Hardware Watchdog Timer Lock Register 0xC00 32 read-write n 0x0 0x0 WDG_LDR Hardware Watchdog Timer Load Register 0x0 32 read-write n 0x0 0x0 WDG_RIS Hardware Watchdog Timer Interrupt Status Register 0x10 8 read-only n 0x0 0x0 RIS Hardware watchdog interrupt status bit 0 read-only WDG_VLR Hardware Watchdog Timer Value Register 0x4 32 read-only n 0x0 0x0 INTREQ Interrupts INTREQ 0x0 0x10 0x94 registers n EXC02MON EXC02 batch read register 0x10 32 read-only n 0x0 0x0 HWINT Hardware watchdog timer interrupt request 1 read-only NMI External NMIX pin interrupt request 0 read-only IRQ00MON IRQ00 Batch Read Register 0x14 32 read-only n 0x0 0x0 FCSINT Anomalous frequency detection by CSV interrupt request 0 read-only IRQ01MON IRQ01 Batch Read Register 0x18 32 read-only n 0x0 0x0 SWWDTINT Software watchdog timer interrupt request 0 read-only IRQ02MON IRQ02 Batch Read Register 0x1C 32 read-only n 0x0 0x0 LVDINT Low voltage detection (LVD) interrupt request 0 read-only IRQ03MON IRQ03 Batch Read Register 0x20 32 read-only n 0x0 0x0 WAVE0INT0 DTIF (motor emergency stop) interrupt request in MFT unit 0 0 read-only WAVE0INT1 WFG timer 10 interrupt request in MFT unit 0 1 read-only WAVE0INT2 WFG timer 32 interrupt request in MFT unit 0 2 read-only WAVE0INT3 WFG timer 54 interrupt request in MFT unit 0 3 read-only IRQ04MON IRQ04 Batch Read Register 0x24 32 read-only n 0x0 0x0 EXTINT0 Interrupt request on external interrupt ch.0 0 read-only EXTINT1 Interrupt request on external interrupt ch.1 1 read-only EXTINT2 Interrupt request on external interrupt ch.2 2 read-only EXTINT3 Interrupt request on external interrupt ch.3 3 read-only EXTINT4 Interrupt request on external interrupt ch.4 4 read-only EXTINT5 Interrupt request on external interrupt ch.5 5 read-only EXTINT6 Interrupt request on external interrupt ch.6 6 read-only EXTINT7 Interrupt request on external interrupt ch.7 7 read-only IRQ05MON IRQ05 Batch Read Register 0x28 32 read-only n 0x0 0x0 EXTINT14 Interrupt request on external interrupt ch.14 6 read-only EXTINT15 Interrupt request on external interrupt ch.15 7 read-only EXTINT8 Interrupt request on external interrupt ch.8 0 read-only IRQ06MON IRQ06 Batch Read Register 0x2C 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.0 0 read-only IRQ07MON IRQ07 Batch Read Register 0x30 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.0 0 read-only MFSINT1 Status interrupt request on MFS ch.0 1 read-only IRQ08MON IRQ08 Batch Read Register 0x34 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.1 0 read-only IRQ09MON IRQ9 Batch Read Register 0x38 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.1 0 read-only MFSINT1 Status interrupt request on MFS ch.1 1 read-only IRQ10MON IRQ10 Batch Read Register 0x3C 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.2 0 read-only IRQ11MON IRQ11 Batch Read Register 0x40 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.2 0 read-only MFSINT1 Status interrupt request on MFS ch.2 1 read-only IRQ12MON IRQ12 Batch Read Register 0x44 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.3 0 read-only IRQ13MON IRQ13 Batch Read Register 0x48 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.3 0 read-only MFSINT1 Status interrupt request on MFS ch.3 1 read-only IRQ14MON IRQ14 Batch Read Register 0x4C 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.4 0 read-only IRQ15MON IRQ15 Batch Read Register 0x50 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.4 0 read-only MFSINT1 Status interrupt request on MFS ch.4 1 read-only IRQ16MON IRQ16 Batch Read Register 0x54 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.5 0 read-only IRQ17MON IRQ17 Batch Read Register 0x58 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.5 0 read-only MFSINT1 Status interrupt request on MFS ch.5 1 read-only IRQ18MON IRQ18 Batch Read Register 0x5C 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.6 0 read-only IRQ19MON IRQ19 Batch Read Register 0x60 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.6 0 read-only MFSINT1 Status interrupt request on MFS ch.6 1 read-only IRQ20MON IRQ20 Batch Read Register 0x64 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.7 0 read-only IRQ21MON IRQ21 Batch Read Register 0x68 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.7 0 read-only MFSINT1 Status interrupt request on MFS ch.7 1 read-only IRQ22MON IRQ22 Batch Read Register 0x6C 32 read-only n 0x0 0x0 PPGINT0 Interrupt request on PPG ch.0 0 read-only PPGINT1 Interrupt request on PPG ch.2 1 read-only PPGINT2 Interrupt request on PPG ch.4 2 read-only IRQ23MON IRQ23 Batch Read Register 0x70 32 read-only n 0x0 0x0 MOSCINT Stabilization wait completion interrupt request for main clock oscillation 0 read-only MPLLINT Stabilization wait completion interrupt request for main PLL oscillation 2 read-only RTCINT RTC interrupt request 5 read-only SOSCINT Stabilization wait completion interrupt request for sub-clock oscillation 1 read-only IRQ24MON IRQ24 Batch Read Register 0x74 32 read-only n 0x0 0x0 ADCINT0 Priority conversion interrupt request in the corresponding A/D unit 0. 0 read-only ADCINT1 Scan conversion interrupt request in the corresponding A/D unit 0. 1 read-only ADCINT2 FIFO overrun interrupt request in the corresponding A/D unit 0. 2 read-only ADCINT3 Conversion result comparison interrupt request in the corresponding A/D unit 0. 3 read-only IRQ25MON IRQ25 Batch Read Register 0x78 32 read-only n 0x0 0x0 FRT0INT0 Peak value detection interrupt request on the free run timer ch.0 in the MFT unit 0 0 read-only FRT0INT1 Peak value detection interrupt request on the free run timer ch.1 in the MFT unit 0 1 read-only FRT0INT2 Peak value detection interrupt request on the free run timer ch.2 in the MFT unit 0 2 read-only FRT0INT3 Zero detection interrupt request on the free run timer ch.0 in the MFT unit 0 3 read-only FRT0INT4 Zero detection interrupt request on the free run timer ch.1 in the MFT unit 0 4 read-only FRT0INT5 Zero detection interrupt request on the free run timer ch.2 in the MFT unit 0 5 read-only IRQ26MON IRQ26 Batch Read Register 0x7C 32 read-only n 0x0 0x0 ICU0INT0 Interrupt request on the input capture ch.0 in the MFT unit 0 0 read-only ICU0INT1 Interrupt request on the input capture ch.1 in the MFT unit 0 1 read-only ICU0INT2 Interrupt request on the input capture ch.2 in the MFT unit 0 2 read-only ICU0INT3 Interrupt request on the input capture ch.3 in the MFT unit 0 3 read-only IRQ27MON IRQ27 Batch Read Register 0x80 32 read-only n 0x0 0x0 OCU0INT0 Interrupt request on the output compare ch.0 in the MFT unit 0 0 read-only OCU0INT1 Interrupt request on the output compare ch.1 in the MFT unit 0 1 read-only OCU0INT2 Interrupt request on the output compare ch.2 in the MFT unit 0 2 read-only OCU0INT3 Interrupt request on the output compare ch.3 in the MFT unit 0 3 read-only OCU0INT4 Interrupt request on the output compare ch.4 in the MFT unit 0 4 read-only OCU0INT5 Interrupt request on the output compare ch.5 in the MFT unit 0 5 read-only IRQ28MON IRQ28 Batch Read Register 0x84 32 read-write n 0x0 0x0 BTINT0 IRQ0 interrupt request on the base timer ch.0 0 read-only BTINT1 IRQ1 interrupt request on the base timer ch.0 1 read-only BTINT10 IRQ0 interrupt request on the base timer ch.5 10 read-only BTINT11 IRQ1 interrupt request on the base timer ch.5 11 read-only BTINT12 IRQ0 interrupt request on the base timer ch.6 12 read-only BTINT13 IRQ1 interrupt request on the base timer ch.6 13 read-only BTINT14 IRQ0 interrupt request on the base timer ch.7 14 read-only BTINT15 IRQ1 interrupt request on the base timer ch.7 15 read-only BTINT2 IRQ0 interrupt request on the base timer ch.1 2 read-only BTINT3 IRQ1 interrupt request on the base timer ch.1 3 read-only BTINT4 IRQ0 interrupt request on the base timer ch.2 4 read-only BTINT5 IRQ1 interrupt request on the base timer ch.2 5 read-only BTINT6 IRQ0 interrupt request on the base timer ch.3 6 read-only BTINT7 IRQ1 interrupt request on the base timer ch.3 7 read-only BTINT8 IRQ0 interrupt request on the base timer ch.4 8 read-only BTINT9 IRQ1 interrupt request on the base timer ch.4 9 read-only IRQ29MON IRQ29 Batch Read Register 0x88 32 read-write n 0x0 0x0 LCDCINT LCDC interrupt request for LCD controller 4 read-only IRQ30MON IRQ30 Batch Read Register 0x8C 32 read-write n 0x0 0x0 RCEC0INT Interrupt request for HDMI-CEC/Remote Control Reception ch.0 5 read-only IRQ31MON IRQ31 Batch Read Register 0x90 32 read-write n 0x0 0x0 RCEC1INT Interrupt request for HDMI-CEC/Remote Control Reception ch.1 6 read-only LCDC LCD Controller LCDC 0x0 0x0 0x3 registers n 0x10 0x1 registers n 0x14 0x2 registers n 0x1C 0x28 registers n 0x4 0x4 registers n 0x8 0x1 registers n 0xC 0x4 registers n LCDC 29 BLINK LCDC Blink Setting Register 0x14 16 read-write n 0x0 0x0 BLD00 Blink operation control bit 0 0 read-write BLD01 Blink operation control bit 1 1 read-write BLD02 Blink operation control bit 2 2 read-write BLD03 Blink operation control bit 3 3 read-write BLD04 Blink operation control bit 4 4 read-write BLD05 Blink operation control bit 5 5 read-write BLD06 Blink operation control bit 6 6 read-write BLD07 Blink operation control bit 7 7 read-write BLD08 Blink operation control bit 8 8 read-write BLD09 Blink operation control bit 9 9 read-write BLD10 Blink operation control bit 10 10 read-write BLD11 Blink operation control bit 11 11 read-write BLD12 Blink operation control bit 12 12 read-write BLD13 Blink operation control bit 13 13 read-write BLD14 Blink operation control bit 14 14 read-write BLD15 Blink operation control bit 15 15 read-write COMEN LCDC COM Output Enable Register 0x8 8 read-write n 0x0 0x0 COM0 Dual purpose COM port control bit 0 read-write COM1 Dual purpose COM port control bit 1 read-write COM2 Dual purpose COM port control bit 2 read-write COM3 Dual purpose COM port control bit 3 read-write COM4 Dual purpose COM/SEG port control bits 4 read-write COM5 Dual purpose COM/SEG port control bits 5 read-write COM6 Dual purpose COM/SEG port control bits 6 read-write COM7 Dual purpose COM/SEG port control bits 7 read-write LCDCC1 LCDC Control Register 1 0x0 8 read-write n 0x0 0x0 LCDEN Timer mode operation enable bit 6 read-write MS LCD controller display mode selection bits 2 2 read-write VSEL LCD drive power control bit 5 read-write LCDCC2 LCDC Control Register 2 0x1 8 read-write n 0x0 0x0 BK Blank display control bit 2 read-write BLS8 8 COM mode bias selection bit 4 read-write INV Reverse display control bit 3 read-write LCDIEN Interrupt enable bit 1 read-write LCDIF Interrupt request detection bit 0 read-write RSEL Divider resistor value selection bit 5 read-write LCDCC3 LCDC Control Register 3 0x2 8 read-write n 0x0 0x0 BLSEL Blink interval selection bit 6 read-write PICTL I/O port input control bit 7 read-write VE0 VV0 selection bit 1 read-write VE1 VV1 selection bit 2 read-write VE2 VV2 selection bit 3 read-write VE3 VV3 selection bit 4 read-write VE4 VV4 selection bit 5 read-write LCDRAM00 Display Data Memory Register 00 0x1C 8 read-write n 0x0 0x0 LCDRAM Display Data 00 0 7 read-write LCDRAM01 Display Data Memory Register 01 0x1D 8 read-write n 0x0 0x0 LCDRAM Display Data 01 0 7 read-write LCDRAM02 Display Data Memory Register 02 0x1E 8 read-write n 0x0 0x0 LCDRAM Display Data 02 0 7 read-write LCDRAM03 Display Data Memory Register 03 0x1F 8 read-write n 0x0 0x0 LCDRAM Display Data 03 0 7 read-write LCDRAM04 Display Data Memory Register 04 0x20 8 read-write n 0x0 0x0 LCDRAM Display Data 04 0 7 read-write LCDRAM05 Display Data Memory Register 05 0x21 8 read-write n 0x0 0x0 LCDRAM Display Data 05 0 7 read-write LCDRAM06 Display Data Memory Register 06 0x22 8 read-write n 0x0 0x0 LCDRAM Display Data 06 0 7 read-write LCDRAM07 Display Data Memory Register 07 0x23 8 read-write n 0x0 0x0 LCDRAM Display Data 07 0 7 read-write LCDRAM08 Display Data Memory Register 08 0x24 8 read-write n 0x0 0x0 LCDRAM Display Data 08 0 7 read-write LCDRAM09 Display Data Memory Register 09 0x25 8 read-write n 0x0 0x0 LCDRAM Display Data 09 0 7 read-write LCDRAM10 Display Data Memory Register 10 0x26 8 read-write n 0x0 0x0 LCDRAM Display Data 10 0 7 read-write LCDRAM11 Display Data Memory Register 11 0x27 8 read-write n 0x0 0x0 LCDRAM Display Data 11 0 7 read-write LCDRAM12 Display Data Memory Register 12 0x28 8 read-write n 0x0 0x0 LCDRAM Display Data 12 0 7 read-write LCDRAM13 Display Data Memory Register 13 0x29 8 read-write n 0x0 0x0 LCDRAM Display Data 13 0 7 read-write LCDRAM14 Display Data Memory Register 14 0x2A 8 read-write n 0x0 0x0 LCDRAM Display Data 14 0 7 read-write LCDRAM15 Display Data Memory Register 15 0x2B 8 read-write n 0x0 0x0 LCDRAM Display Data 15 0 7 read-write LCDRAM16 Display Data Memory Register 16 0x2C 8 read-write n 0x0 0x0 LCDRAM Display Data 16 0 7 read-write LCDRAM17 Display Data Memory Register 17 0x2D 8 read-write n 0x0 0x0 LCDRAM Display Data 17 0 7 read-write LCDRAM18 Display Data Memory Register 18 0x2E 8 read-write n 0x0 0x0 LCDRAM Display Data 18 0 7 read-write LCDRAM19 Display Data Memory Register 19 0x2F 8 read-write n 0x0 0x0 LCDRAM Display Data 19 0 7 read-write LCDRAM20 Display Data Memory Register 20 0x30 8 read-write n 0x0 0x0 LCDRAM Display Data 20 0 7 read-write LCDRAM21 Display Data Memory Register 21 0x31 8 read-write n 0x0 0x0 LCDRAM Display Data 21 0 7 read-write LCDRAM22 Display Data Memory Register 22 0x32 8 read-write n 0x0 0x0 LCDRAM Display Data 22 0 7 read-write LCDRAM23 Display Data Memory Register 23 0x33 8 read-write n 0x0 0x0 LCDRAM Display Data 23 0 7 read-write LCDRAM24 Display Data Memory Register 24 0x34 8 read-write n 0x0 0x0 LCDRAM Display Data 24 0 7 read-write LCDRAM25 Display Data Memory Register 25 0x35 8 read-write n 0x0 0x0 LCDRAM Display Data 25 0 7 read-write LCDRAM26 Display Data Memory Register 26 0x36 8 read-write n 0x0 0x0 LCDRAM Display Data 26 0 7 read-write LCDRAM27 Display Data Memory Register 27 0x37 8 read-write n 0x0 0x0 LCDRAM Display Data 27 0 7 read-write LCDRAM28 Display Data Memory Register 28 0x38 8 read-write n 0x0 0x0 LCDRAM Display Data 28 0 7 read-write LCDRAM29 Display Data Memory Register 29 0x39 8 read-write n 0x0 0x0 LCDRAM Display Data 29 0 7 read-write LCDRAM30 Display Data Memory Register 30 0x3A 8 read-write n 0x0 0x0 LCDRAM Display Data 30 0 7 read-write LCDRAM31 Display Data Memory Register 31 0x3B 8 read-write n 0x0 0x0 LCDRAM Display Data 31 0 7 read-write LCDRAM32 Display Data Memory Register 32 0x3C 8 read-write n 0x0 0x0 LCDRAM Display Data 32 0 7 read-write LCDRAM33 Display Data Memory Register 33 0x3D 8 read-write n 0x0 0x0 LCDRAM Display Data 33 0 7 read-write LCDRAM34 Display Data Memory Register 34 0x3E 8 read-write n 0x0 0x0 LCDRAM Display Data 34 0 7 read-write LCDRAM35 Display Data Memory Register 35 0x3F 8 read-write n 0x0 0x0 LCDRAM Display Data 35 0 7 read-write LCDRAM36 Display Data Memory Register 36 0x40 8 read-write n 0x0 0x0 LCDRAM Display Data 36 0 7 read-write LCDRAM37 Display Data Memory Register 37 0x41 8 read-write n 0x0 0x0 LCDRAM Display Data 37 0 7 read-write LCDRAM38 Display Data Memory Register 38 0x42 8 read-write n 0x0 0x0 LCDRAM Display Data 38 0 7 read-write LCDRAM39 Display Data Memory Register 39 0x43 8 read-write n 0x0 0x0 LCDRAM Display Data 39 0 7 read-write PSR LCDC Clock Prescaler Register 0x4 32 read-write n 0x0 0x0 CLKDIV LCDC clock division ratio setting bit 0 21 read-write CLKSEL Source clock selection bit 22 read-write SEGEN1 LCDC SEG Output Enable Register 1 0xC 32 read-write n 0x0 0x0 SEG00 Segment 0 0 read-write SEG01 Segment 1 1 read-write SEG02 Segment 2 2 read-write SEG03 Segment 3 3 read-write SEG04 Segment 4 4 read-write SEG07 Segment 7 7 read-write SEG10 Segment 10 10 read-write SEG11 Segment 11 11 read-write SEG12 Segment 12 12 read-write SEG13 Segment 13 13 read-write SEG17 Segment 17 17 read-write SEG18 Segment 18 18 read-write SEG19 Segment 19 19 read-write SEG20 Segment 20 20 read-write SEG21 Segment 21 21 read-write SEG22 Segment 22 22 read-write SEG23 Segment 23 23 read-write SEG24 Segment 24 24 read-write SEG25 Segment 25 25 read-write SEG26 Segment 26 26 read-write SEG27 Segment 27 27 read-write SEG28 Segment 28 28 read-write SEG29 Segment 29 29 read-write SEG30 Segment 30 30 read-write SEG31 Segment 31 31 read-write SEGEN2 LCDC SEG Output Enable Register 2 0x10 8 read-write n 0x0 0x0 SEG32 Segment 32 0 read-write SEG33 Segment 33 1 read-write SEG34 Segment 34 2 read-write SEG35 Segment 35 3 read-write SEG36 Segment 36 4 read-write SEG37 Segment 37 5 read-write SEG38 Segment 38 6 read-write SEG39 Segment 39 7 read-write LVD Low-voltage Detection LVD 0x0 0x0 0x2 registers n 0x4 0x1 registers n 0x8 0x1 registers n 0xC 0x5 registers n LVD 2 CLR Low-voltage Detection Interrupt Clear Register 0x8 8 read-write n 0x0 0x0 LVDCL Low-voltage detection interrupt clear bit 7 read-write CTL Low-voltage Detection Voltage Control Register 0x0 16 read-write n 0x0 0x0 LVDIE Low-voltage detection interrupt enable bit 7 read-write LVDIM Low-voltage detection interrupt low power mode select bit 1 read-write LVDRE Low-voltage detection reset operation enable bit 15 read-write SVHI Low-voltage detection interrupt voltage setting bits 2 3 read-write SVHR Low-voltage detection reset voltage setting bits 10 3 read-write RLR Low-voltage Detection Voltage Protection Register 0xC 32 read-write n 0x0 0x0 LVDLCK Low-voltage Detection Voltage Control Register protection bits 0 31 read-write STR Low-voltage Detection Interrupt Register 0x4 8 read-only n 0x0 0x0 LVDIR Low-voltage detection interrupt bit 7 read-only STR2 Low-voltage Detection Circuit Status Register 0x10 8 read-only n 0x0 0x0 LVDIRDY Low-voltage detection interrupt status flag 7 read-only LVDRRDY Low-voltage detection reset status flag 6 read-only MFS0 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x1D 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS0RX 6 MFS0TX 7 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write n 0x0 0x0 BEC Bus error control bit 0 read-write SCLC SCL output control bit 2 read-write SCLS SCL status bit 4 read-write SDAC SDA output control bit 3 read-write SDAS SDA status bit 5 read-write SOCE Serial output enabled bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS1 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x1D 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS1RX 8 MFS1TX 9 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write n 0x0 0x0 BEC Bus error control bit 0 read-write SCLC SCL output control bit 2 read-write SCLS SCL status bit 4 read-write SDAC SDA output control bit 3 read-write SDAS SDA status bit 5 read-write SOCE Serial output enabled bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS2 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x1D 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS2RX 10 MFS2TX 11 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write n 0x0 0x0 BEC Bus error control bit 0 read-write SCLC SCL output control bit 2 read-write SCLS SCL status bit 4 read-write SDAC SDA output control bit 3 read-write SDAS SDA status bit 5 read-write SOCE Serial output enabled bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS3 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x1D 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS3RX 12 MFS3TX 13 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write n 0x0 0x0 BEC Bus error control bit 0 read-write SCLC SCL output control bit 2 read-write SCLS SCL status bit 4 read-write SDAC SDA output control bit 3 read-write SDAS SDA status bit 5 read-write SOCE Serial output enabled bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS4 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x1D 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS4RX 14 MFS4TX 15 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write n 0x0 0x0 BEC Bus error control bit 0 read-write SCLC SCL output control bit 2 read-write SCLS SCL status bit 4 read-write SDAC SDA output control bit 3 read-write SDAS SDA status bit 5 read-write SOCE Serial output enabled bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS5 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x1D 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS5RX 16 MFS5TX 17 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write n 0x0 0x0 BEC Bus error control bit 0 read-write SCLC SCL output control bit 2 read-write SCLS SCL status bit 4 read-write SDAC SDA output control bit 3 read-write SDAS SDA status bit 5 read-write SOCE Serial output enabled bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS6 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x1D 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS6RX 18 MFS6TX 19 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write n 0x0 0x0 BEC Bus error control bit 0 read-write SCLC SCL output control bit 2 read-write SCLS SCL status bit 4 read-write SDAC SDA output control bit 3 read-write SDAS SDA status bit 5 read-write SOCE Serial output enabled bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS7 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x1D 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS7RX 20 MFS7TX 21 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write n 0x0 0x0 BEC Bus error control bit 0 read-write SCLC SCL output control bit 2 read-write SCLS SCL status bit 4 read-write SDAC SDA output control bit 3 read-write SDAS SDA status bit 5 read-write SOCE Serial output enabled bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFT0 Multifunction Timer 0 MFT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x2 registers n 0x20 0x2 registers n 0x24 0x2 registers n 0x28 0x2 registers n 0x2C 0x2 registers n 0x30 0x2 registers n 0x34 0x2 registers n 0x38 0x2 registers n 0x3C 0x2 registers n 0x4 0x2 registers n 0x40 0x2 registers n 0x44 0x2 registers n 0x48 0x2 registers n 0x4C 0x2 registers n 0x50 0x2 registers n 0x54 0x2 registers n 0x58 0x2 registers n 0x5C 0x1 registers n 0x60 0x2 registers n 0x68 0x2 registers n 0x6C 0x2 registers n 0x70 0x2 registers n 0x74 0x2 registers n 0x78 0x2 registers n 0x7C 0x2 registers n 0x8 0x2 registers n 0x80 0x2 registers n 0x84 0x2 registers n 0x88 0x2 registers n 0x8C 0x2 registers n 0x90 0x2 registers n 0x94 0x2 registers n 0x98 0x2 registers n 0x9C 0x2 registers n 0xA0 0x2 registers n 0xA4 0x2 registers n 0xA8 0x2 registers n 0xAC 0x2 registers n 0xB0 0x2 registers n 0xB4 0x2 registers n 0xB8 0x1 registers n 0xBC 0x2 registers n 0xC 0x2 registers n 0xC0 0x2 registers n WFG 3 FRTIM 25 INCAP 26 OUTCOMP 27 ADCMP_ACCP0 ADCMP ch.0 Compare Value Store Register 0xA0 16 read-write n 0x0 0x0 ADCMP_ACCP1 ADCMP ch.1 Compare Value Store Register 0xA8 read-write n 0x0 0x0 ADCMP_ACCP2 ADCMP ch.2 Compare Value Store Register 0xB0 read-write n 0x0 0x0 ADCMP_ACCPDN0 ADCMP ch.0 Compare Value Store Register 0xA4 16 read-write n 0x0 0x0 ADCMP_ACCPDN1 ADCMP ch.1 Compare Value Store Register 0xAC read-write n 0x0 0x0 ADCMP_ACCPDN2 ADCMP ch.2 Compare Value Store Register 0xB4 read-write n 0x0 0x0 ADCMP_ACSA ADCMP Control Register A 0xBC 16 read-write n 0x0 0x0 CE0 enable or disable the operation of ADCMP-ch.0 and select the FRT to be connected 0 1 read-write CE1 enable or disable the operation of ADCMP-ch.1 and select the FRT to be connected 2 1 read-write CE2 enable or disable the operation of ADCMP-ch.2 and select the FRT to be connected 4 1 read-write SEL0 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.0 8 1 read-write SEL1 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.1 10 1 read-write SEL2 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.2 12 1 read-write ADCMP_ACSB ADCMP Control Register B 0xB8 8 read-write n 0x0 0x0 BDIS0 Disables the buffer function of the ACCP0 and ACCPDN0 registers 0 read-write BDIS1 Disables the buffer function of the ACCP1 and ACCPDN1 registers 1 read-write BDIS2 Disables the buffer function of the ACCP2 and ACCPDN2 registers 2 read-write BTS0 Performs buffer transfer of the ACCP0 and ACCPDN0 registers upon Peak value detection by FRT 4 read-write BTS1 Performs buffer transfer of the ACCP1 and ACCPDN1 registers upon Peak value detection by FRT 5 read-write BTS2 Performs buffer transfer of the ACCP2 and ACCPDN2 registers upon Peak value detection by FRT 6 read-write ADCMP_ATSA ADC Start Trigger Select Register 0xC0 16 read-write n 0x0 0x0 AD0P selects the start signal to be used to start priority conversion of ADC unit0 8 1 read-write AD0S selects the start signal to be used to start the scan conversion of ADC unit0 0 1 read-write AD1P selects the start signal to be used to start priority conversion of ADC unit1 10 1 read-write AD1S selects the start signal to be used to start the scan conversion of ADC unit1 2 1 read-write AD2P selects the start signal to be used to start priority conversion of ADC unit2 12 1 read-write AD2S selects the start signal to be used to start the scan conversion of ADC unit2 4 1 read-write FRT_TCCP0 FRT-ch.0 Cycle Setting Register 0x28 16 read-write n 0x0 0x0 FRT_TCCP1 FRT-ch.1 Cycle Setting Register 0x38 read-write n 0x0 0x0 FRT_TCCP2 FRT-ch.2 Cycle Setting Register 0x48 read-write n 0x0 0x0 FRT_TCDT0 FRT-ch.0 Count Value Register 0x2C 16 read-write n 0x0 0x0 FRT_TCDT1 FRT-ch.1 Count Value Register 0x3C read-write n 0x0 0x0 FRT_TCDT2 FRT-ch.2 Count Value Register 0x4C read-write n 0x0 0x0 FRT_TCSA0 FRT-ch.0 Control Register A 0x30 16 read-write n 0x0 0x0 BFE Enables TCCP's buffer function 7 read-write CLK FRT clock cycle 0 3 read-write ECKE Uses an external input clock (FRCK) as FRT's count clock 15 read-write ICLR interrupt flag 9 read-write ICRE "Generates interrupt when ""1"" is set to TCSA.ICLR" 8 read-write IRQZE "Generates interrupt, when ""1"" is set to TCSA.IRQZF" 13 read-write IRQZF zero interrupt flag 14 read-write MODE FRT's count mode 5 read-write SCLR FRT operation state initialization request 4 write-only STOP Puts FRT in stopping state 6 read-write FRT_TCSA1 FRT-ch.1 Control Register A 0x40 read-write n 0x0 0x0 FRT_TCSA2 FRT-ch.2 Control Register A 0x50 read-write n 0x0 0x0 FRT_TCSB0 FRT-ch.0 Control Register B 0x34 16 read-write n 0x0 0x0 AD0E Outputs AD conversion start signal to ADCunit0 upon Zero value detection by FRT 0 read-write AD1E Outputs AD conversion start signal to ADCunit1 upon Zero value detection by FRT 1 read-write AD2E Outputs AD conversion start signal to ADCunit2 upon Zero value detection by FRT 2 read-write FRT_TCSB1 FRT-ch.1 Control Register B 0x44 read-write n 0x0 0x0 FRT_TCSB2 FRT-ch.2 Control Register B 0x54 read-write n 0x0 0x0 ICU_ICCP0 ICU ch.0 Capture value store register 0x68 16 read-only n 0x0 0x0 ICU_ICCP1 ICU ch.1 Capture value store register 0x6C read-write n 0x0 0x0 ICU_ICCP2 ICU ch.2 Capture value store register 0x70 read-write n 0x0 0x0 ICU_ICCP3 ICU ch.3 Capture value store register 0x74 read-write n 0x0 0x0 ICU_ICFS10 "ICU ch.1,0 Connecting FRT Select Register" 0x60 8 read-write n 0x0 0x0 FSI0 Connects FRT ch.x to ICU ch.(0) 0 3 read-write FSI1 Connects FRT ch.x to ICU ch.(1) 4 3 read-write ICU_ICFS32 "ICU ch.3,2 Connecting FRT Select Register" 0x61 read-write n 0x0 0x0 ICU_ICSA10 "ICU ch.1,0 Control Register A" 0x78 8 read-write n 0x0 0x0 EG0 enables/disables the operation of ICU-ch.(0) and selects a valid edge(s) 0 1 read-write EG1 enables/disables the operation of ICU-ch.(1) and selects a valid edge(s) 2 1 read-write ICE0 "Generates interrupt, when ""1"" is set to ICSA.ICP0." 4 read-write ICE1 "Generates interrupt, when ""1"" is set to ICSA.ICP1." 5 read-write ICP0 Indicates that a valid edge has been detected at ICU ch.(0) and the capture operation has been performed 6 read-write ICP1 Indicates that a valid edge has been detected at ICU ch.(1) and the capture operation has been performed 7 read-write ICU_ICSA32 "ICU ch.3,2 Control Register A" 0x7C read-write n 0x0 0x0 ICU_ICSB10 "ICU ch.1,0 Control Register B" 0x79 8 read-only n 0x0 0x0 IEI0 indicates the latest valid edge of ICU-ch.(0) 0 read-only IEI1 indicates the latest valid edge of ICU-ch.(1) 1 read-only ICU_ICSB32 "ICU ch.3,2 Control Register B" 0x7D read-write n 0x0 0x0 OCU_OCCP0 OCU ch.0 Compare Value Store Register 0x0 16 read-write n 0x0 0x0 OCU_OCCP1 OCU ch.1 Compare Value Store Register 0x4 read-write n 0x0 0x0 OCU_OCCP2 OCU ch.2 Compare Value Store Register 0x8 read-write n 0x0 0x0 OCU_OCCP3 OCU ch.3 Compare Value Store Register 0xC read-write n 0x0 0x0 OCU_OCCP4 OCU ch.4 Compare Value Store Register 0x10 read-write n 0x0 0x0 OCU_OCCP5 OCU ch.5 Compare Value Store Register 0x14 read-write n 0x0 0x0 OCU_OCFS10 "OCU ch.1,0 Connecting FRT Select Register" 0x58 8 read-write n 0x0 0x0 FSO0 Connects FRT ch.x to OCU ch.0 0 3 read-write FSO1 Connects FRT ch.x to OCU ch.1 4 3 read-write OCU_OCFS32 "OCU ch.3,2 Connecting FRT Select Register" 0x59 read-write n 0x0 0x0 OCU_OCFS54 "OCU ch.5,4 Connecting FRT Select Register" 0x5C read-write n 0x0 0x0 OCU_OCSA10 "OCU ch.1,0 Control Register A" 0x18 8 read-write n 0x0 0x0 BDIS0 Disables the buffer function of the OCCP(0) register 2 read-write BDIS1 Disables the buffer function of the OCCP(1) register 3 read-write CST0 Enables the operation of OCU ch.(0) 0 read-write CST1 Enables the operation of OCU ch.(1) 1 read-write IOE0 "Generates interrupt, when ""1"" is set to OCSA.IOP0" 4 read-write IOE1 "Generates interrupt, when ""1"" is set to OCSA.IOP1" 5 read-write IOP0 Indicates that a match has already been detected between FRT's count value and OCCP(0) value at OCU ch.(0). 6 read-write IOP1 Indicates that a match has already been detected between FRT's count value and OCCP(1) value at OCU ch.(1). 7 read-write OCU_OCSA32 "OCU ch.3,2 Control Register A" 0x1C read-write n 0x0 0x0 OCU_OCSA54 "OCU ch.5,4 Control Register A" 0x20 read-write n 0x0 0x0 OCU_OCSB10 "OCU ch.1,0 Control Register B" 0x19 8 read-write n 0x0 0x0 BTS0 Performs buffer transfer of the OCCP(0) register upon Peak value detection by FRT 5 read-write BTS1 Performs buffer transfer of the OCCP(1) register upon Peak value detection by FRT 6 read-write CMOD selects OCU's operation mode in combination with OCSC.MOD0 to MOD5 4 read-write OTD0 Indicates that the RT(0) output pin is in the High-level output state. 0 read-write OTD1 Indicates that the RT(1) output pin is in the High-level output state. 1 read-write OCU_OCSB32 "OCU ch.3,2 Control Register B" 0x1D read-write n 0x0 0x0 OCU_OCSB54 "OCU ch.5,4 Control Register B" 0x21 read-write n 0x0 0x0 OCU_OCSC OCU Control Register C 0x24 16 read-write n 0x0 0x0 MOD0 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 8 read-write MOD1 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 9 read-write MOD2 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 10 read-write MOD3 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 11 read-write MOD4 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 12 read-write MOD5 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 13 read-write WFG_NZCL NZCL Control Register 0x9C 16 read-write n 0x0 0x0 DTIE DTIF interrupt enable 0 read-write NWS noise-canceling width of the noise-canceller for the DTTIX pin 1 2 read-write SDTI Forcibly generates DTIF interrupt 4 write-only WFG_WFIR WFG Interrupt Control Register 0x98 16 read-write n 0x0 0x0 DTIC Clears WFIR.DTIF and deasserts the DTIF interrupt signal. 1 write-only DTIF Indicates that DTIF interrupt has been generated. 0 read-only TMIC10 Clears WFIR.TMIF10 and deasserts the WFG10 timer interrupt signal. 5 write-only TMIC32 Clears WFIR.TMIF32 and deasserts the WFG32 timer interrupt signal. 9 write-only TMIC54 Clears WFIR.TMIF54 and deasserts the WFG54 timer interrupt signal. 13 write-only TMIE10 Starts the WFG10 timer 6 read-write TMIE32 Starts the WFG32 timer 10 read-write TMIE54 Starts the WFG54 timer 14 read-write TMIF10 Indicates that WFG10 timer interrupt has been generated. 4 read-only TMIF32 Indicates that WFG32 timer interrupt has been generated. 8 read-only TMIF54 Indicates that WFG54 timer interrupt has been generated. 12 read-only TMIS10 Stops the WFG10 timer 7 write-only TMIS32 Stops the WFG32 timer 11 write-only TMIS54 Stops the WFG54 timer 15 write-only WFG_WFSA10 WFG ch.10 Control Register A 0x8C 16 read-write n 0x0 0x0 DCK clock cycle of the WFG timer 0 2 read-write DMOD specifies which polarity will be used to output the non-overlap signal 12 read-write GTEN the CH_GATE signal for each channel of WFG 6 1 read-write PGEN specifies how to reflect the CH_PPG signal that is input to each channel of WFG on WFG output 10 1 read-write PSEL the PPG timer unit to be used at each channel of WFG 8 1 read-write TMD WFG's operation mode 3 2 read-write WFG_WFSA32 WFG ch.32 Control Register A 0x90 read-write n 0x0 0x0 WFG_WFSA54 WFG ch.54 Control Register A 0x94 read-write n 0x0 0x0 WFG_WFTM10 WFG ch.10 Timer Value Register 0x80 16 read-write n 0x0 0x0 WFG_WFTM32 WFG ch.32 Timer Value Register 0x84 read-write n 0x0 0x0 WFG_WFTM54 WFG ch.54 Timer Value Register 0x88 read-write n 0x0 0x0 MFT_PPG PPG Configuration MFT_PPG 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x100 0x2 registers n 0x104 0x2 registers n 0x14 0x1 registers n 0x200 0x2 registers n 0x204 0x2 registers n 0x208 0x2 registers n 0x20C 0x2 registers n 0x210 0x2 registers n 0x214 0x2 registers n 0x218 0x1 registers n 0x240 0x2 registers n 0x244 0x2 registers n 0x248 0x2 registers n 0x24C 0x2 registers n 0x250 0x2 registers n 0x254 0x2 registers n 0x258 0x1 registers n 0x380 0x1 registers n 0x8 0x2 registers n 0xC 0x1 registers n PPG 22 COMP0 PPG Compare Register 0 0x8 16 read-write n 0x0 0x0 COMP2 PPG Compare Register 2 0xC 8 read-write n 0x0 0x0 COMP4 PPG Compare Register 4 0x10 read-write n 0x0 0x0 COMP6 PPG Compare Register 6 0x14 read-write n 0x0 0x0 GATEC0 PPG Gate Function Control Registers 0 0x218 8 read-write n 0x0 0x0 EDGE0 Select Start Effective Level for PPG0 0 read-write EDGE2 Select Start Effective Level for PPG2 4 read-write STRG0 Select a trigger for PPG0 1 read-write STRG2 Select a trigger for PPG2 5 read-write GATEC4 PPG Gate Function Control Registers 4 0x258 8 read-write n 0x0 0x0 EDGE4 Select Start Effective Level for PPG4 0 read-write EDGE6 Select Start Effective Level for PPG6 4 read-write STRG4 Select a trigger for PPG4 1 read-write STRG6 Select a trigger for PPG6 5 read-write IGBTC IGBT Mode Control Register 0x380 8 read-write n 0x0 0x0 IGATIH Stop prohibition mode selection in output active bit 7 read-write IGBTMD IGBT mode selection bit 0 read-write IGNFW Noise filter width selection bit 4 2 read-write IGOSEL Output level selection bit 2 1 read-write IGTRGLV Trigger input level selection bit 1 read-write PPGC0 PPG Operation Mode Control Register 0 0x201 8 read-write n 0x0 0x0 INTM Interrupt Mode Select bit 5 read-write MD PPG Operation Mode Set bits 1 1 read-write PCS PPG DOWN Counter Operation Clock Select bits 3 1 read-write PIE PPG Interrupt Enable bit 7 read-write PUF PPG Counter Underflow bit 6 read-write TTRG PPG start trigger select bit 0 read-write PPGC1 PPG Operation Mode Control Register 1 0x200 read-write n 0x0 0x0 PPGC2 PPG Operation Mode Control Register 2 0x205 read-write n 0x0 0x0 PPGC3 PPG Operation Mode Control Register 3 0x204 read-write n 0x0 0x0 PPGC4 PPG Operation Mode Control Register 4 0x241 read-write n 0x0 0x0 PPGC5 PPG Operation Mode Control Register 5 0x240 read-write n 0x0 0x0 PPGC6 PPG Operation Mode Control Register 6 0x245 read-write n 0x0 0x0 PPGC7 PPG Operation Mode Control Register 7 0x244 read-write n 0x0 0x0 PRLH0 PPG0 Reload Registers High 0x209 8 read-write n 0x0 0x0 PRLH Reload Registers High 0 7 read-write PRLH1 PPG1 Reload Registers High 0x20D read-write n 0x0 0x0 PRLH2 PPG2 Reload Registers High 0x211 read-write n 0x0 0x0 PRLH3 PPG3 Reload Registers High 0x215 read-write n 0x0 0x0 PRLH4 PPG4 Reload Registers High 0x249 read-write n 0x0 0x0 PRLH5 PPG5 Reload Registers High 0x24D read-write n 0x0 0x0 PRLH6 PPG6 Reload Registers High 0x251 read-write n 0x0 0x0 PRLH7 PPG7 Reload Registers High 0x255 read-write n 0x0 0x0 PRLL0 PPG0 Reload Registers Low 0x208 8 read-write n 0x0 0x0 PRLL Reload Registers Low 0 7 read-write PRLL1 PPG1 Reload Registers Low 0x20C read-write n 0x0 0x0 PRLL2 PPG2 Reload Registers Low 0x210 read-write n 0x0 0x0 PRLL3 PPG3 Reload Registers Low 0x214 read-write n 0x0 0x0 PRLL4 PPG4 Reload Registers Low 0x248 read-write n 0x0 0x0 PRLL5 PPG5 Reload Registers Low 0x24C read-write n 0x0 0x0 PRLL6 PPG6 Reload Registers Low 0x250 read-write n 0x0 0x0 PRLL7 PPG7 Reload Registers Low 0x254 read-write n 0x0 0x0 REVC Output Reverse Register 0 0x104 16 read-write n 0x0 0x0 REV00 PPG0 Output Reverse Enable bit 0 read-write REV01 PPG1 Output Reverse Enable bit 1 read-write REV02 PPG2 Output Reverse Enable bit 2 read-write REV03 PPG3 Output Reverse Enable bit 3 read-write REV04 PPG4 Output Reverse Enable bit 4 read-write REV05 PPG5 Output Reverse Enable bit 5 read-write REV06 PPG6 Output Reverse Enable bit 6 read-write REV07 PPG7 Output Reverse Enable bit 7 read-write TRG PPG Start Register 0 0x100 16 read-write n 0x0 0x0 PEN00 PPG0 Start Trigger bit 0 read-write PEN01 PPG1 Start Trigger bit 1 read-write PEN02 PPG2 Start Trigger bit 2 read-write PEN03 PPG3 Start Trigger bit 3 read-write PEN04 PPG4 Start Trigger bit 4 read-write PEN05 PPG5 Start Trigger bit 5 read-write PEN06 PPG6 Start Trigger bit 6 read-write PEN07 PPG7 Start Trigger bit 7 read-write TTCR0 PPG Start Trigger Control Register 0 0x0 16 read-write n 0x0 0x0 CS0 8-bit UP counter clock select bits for comparison 10 1 read-write MONI0 8-bit UP counter operation state monitor bit for comparison 9 read-only STR0 8-bit UP counter operation enable bit for comparison 8 read-write TRG0O PPG0 trigger stop bit 12 read-write TRG2O PPG2 trigger stop bit 13 read-write TRG4O PPG4 trigger stop bit 14 read-write TRG6O PPG6 trigger stop bit 15 read-write RTC REAL-TIME CLOCK RTC 0x0 0x0 0x13 registers n 0x15 0x3 registers n 0x19 0x2 registers n 0x1C 0x4 registers n 0x20 0x2 registers n 0x24 0x3 registers n 0x28 0x2 registers n 0x2C 0x1 registers n 0x30 0x1 registers n ALDR Alarm Date Register 0x17 8 read-write n 0x0 0x0 AD the first digit of the alarm-set date 0 3 read-write TAD the second digit of the alarm-set date 4 1 read-write ALHR Alarm Hour Register 0x16 8 read-write n 0x0 0x0 AH the first digit of the alarm-set hour 0 3 read-write TAH the second digit of the alarm-set hour 4 1 read-write ALMIR Alarm Minute Register 0x15 8 read-write n 0x0 0x0 AMI the first digit of the alarm-set minute 0 3 read-write TAMI the second digit of the alarm-set minute 4 2 read-write ALMOR Alarm Month Register 0x19 8 read-write n 0x0 0x0 AMO the first digit of the alarm-set month 0 3 read-write TAMO0 the second digit of the alarm-set month 4 read-write ALYR Alarm Years Register 0x1A 8 read-write n 0x0 0x0 AY the first digit of the alarm-set year 0 3 read-write TAY the second digit of the alarm-set year 4 3 read-write WTBR Counter Cycle Setting Register 0x8 32 read-write n 0x0 0x0 BR0 Bit0 of WTBR 0 read-write BR1 Bit1 of WTBR 1 read-write BR10 Bit10 of WTBR 10 read-write BR11 Bit11 of WTBR 11 read-write BR12 Bit12 of WTBR 12 read-write BR13 Bit13 of WTBR 13 read-write BR14 Bit14 of WTBR 14 read-write BR15 Bit15 of WTBR 15 read-write BR16 Bit16 of WTBR 16 read-write BR17 Bit17 of WTBR 17 read-write BR18 Bit18 of WTBR 18 read-write BR19 Bit19 of WTBR 19 read-write BR2 Bit2 of WTBR 2 read-write BR20 Bit20 of WTBR 20 read-write BR21 Bit21 of WTBR 21 read-write BR22 Bit22 of WTBR 22 read-write BR23 Bit23 of WTBR 23 read-write BR3 Bit3 of WTBR 3 read-write BR4 Bit4 of WTBR 4 read-write BR5 Bit5 of WTBR 5 read-write BR6 Bit6 of WTBR 6 read-write BR7 Bit7 of WTBR 7 read-write BR8 Bit8 of WTBR 8 read-write BR9 Bit9 of WTBR 9 read-write WTCAL Frequency Correction Value Setting Register 0x24 16 read-write n 0x0 0x0 WTCAL Frequency correction value 0 9 read-write WTCALEN Frequency Correction Enable Register 0x26 8 read-write n 0x0 0x0 WTCALEN Frequency correction enable bit 0 read-write WTCALPRD Frequency Correction Cycle Setting Register 0x2C 8 read-write n 0x0 0x0 WTCALPRD frequency correction value 0 5 read-write WTCLKM Selection Clock Status Register 0x21 8 read-only n 0x0 0x0 WTCLKM Clock selection status bit 0 1 read-only WTCLKS Clock Selection Register 0x20 8 read-write n 0x0 0x0 WTCLKS Input clock selection bit 0 read-write WTCOSEL RTCCO Output Selection Register 0x30 8 read-write n 0x0 0x0 WTCOSEL RTCCO output selection bit 0 read-write WTCR1 Control Register 1 0x0 32 read-write n 0x0 0x0 BUSY Busy bit 6 read-only DEN Alarm date register enable bit 10 read-write HEN Alarm hour register enable bit 9 read-write INTALI Alarm interrupt flag bit 21 read-write INTALIE Alarm interrupt enable bit 29 read-write INTCRI Year/month/date/hour/minute/second/day of the week counter value read completion interrupt flag bit 23 read-write INTCRIE Year/month/date/hour/minute/second/day of the week counter value read completion interrupt enable bit 31 read-write INTERI Time rewrite error interrupt flag bit 22 read-write INTERIE Time rewrite error interrupt enable bit 30 read-write INTHI 1-hour interrupt flag bit 19 read-write INTHIE 1-hour interrupt enable bit 27 read-write INTMI 1-minute interrupt flag bit 18 read-write INTMIE 1-minute interrupt enable bit 26 read-write INTSI 1-second interrupt flag bit 17 read-write INTSIE 1-second interrupt enable bit 25 read-write INTSSI 0.5-second interrupt flag bit 16 read-write INTSSIE 0.5-second interrupt enable bit 24 read-write INTTMI Timer interrupt flag bit 20 read-write INTTMIE Timer interrupt enable bit 28 read-write MIEN Alarm minute register enable bit 8 read-write MOEN Alarm month register enable bit 11 read-write RUN RTC count block operation bit 2 read-only SCRST Sub second generation/1-second generation counter reset bit 5 read-write SCST 1-second clock output stop bit 4 read-write SRST RTC reset bit 3 read-write ST Start bit 0 read-write YEN Alarm year register enable bit 12 read-write WTCR2 Control Register 2 0x4 32 read-write n 0x0 0x0 CREAD Year/month/date/hour/minute/second/day of the week counter value read control bit 0 read-write TMEN Timer counter control bit 9 read-write TMRUN Timer counter operation bit 10 read-only TMST Timer counter start bit 8 read-write WTDIV Divider Ratio Setting Register 0x28 8 read-write n 0x0 0x0 WTDIV Divider ratio 0 3 read-write WTDIVEN Divider Output Enable Register 0x29 8 read-write n 0x0 0x0 WTDIVEN Divider enable bit 0 read-write WTDIVRDY Divider status bit 1 read-only WTDR Date Register 0xF 8 read-write n 0x0 0x0 D the first digit of the date 0 3 read-write TD the second digit of the date 4 1 read-write WTDW Day of the Week Register 0x10 8 read-write n 0x0 0x0 DW Day of the week 0 2 read-write WTHR Hour register 0xE 8 read-write n 0x0 0x0 H the first digit of the hour 0 3 read-write TH the second digit of the hour 4 1 read-write WTMIR Minute Register 0xD 8 read-write n 0x0 0x0 MI the first digit of the minute 0 3 read-write TMI the second digit of the minute 4 2 read-write WTMOR Month Register 0x11 8 read-write n 0x0 0x0 MO the first digit of the month 0 3 read-write TMO0 the second digit in the month 4 read-write WTSR Second Register 0xC 8 read-write n 0x0 0x0 S the first digit of the second 0 3 read-write TS the second digit of the second 4 2 read-write WTTR Timer Setting Register 0x1C 32 read-write n 0x0 0x0 TM0 Bit0 of WTTR 0 read-write TM1 Bit1 of WTTR 1 read-write TM10 Bit10 of WTTR 10 read-write TM11 Bit11 of WTTR 11 read-write TM12 Bit12 of WTTR 12 read-write TM13 Bit13 of WTTR 13 read-write TM14 Bit14 of WTTR 14 read-write TM15 Bit15 of WTTR 15 read-write TM16 Bit16 of WTTR 16 read-write TM17 Bit17 of WTTR 17 read-write TM2 Bit2 of WTTR 2 read-write TM3 Bit3 of WTTR 3 read-write TM4 Bit4 of WTTR 4 read-write TM5 Bit5 of WTTR 5 read-write TM6 Bit6 of WTTR 6 read-write TM7 Bit7 of WTTR 7 read-write TM8 Bit8 of WTTR 8 read-write TM9 Bit9 of WTTR 9 read-write WTYR Year Register 0x12 8 read-write n 0x0 0x0 TY the second digit of the year 4 3 read-write Y the first digit of the year 0 3 read-write SBSSR Software-based Simultaneous Startup Register SBSSR 0x0 0xFC 0x2 registers n BTSSSR Software-based Simultaneous Startup Register 0xFC 16 write-only n 0x0 0x0 SSSR0 Bit0 of BTSSSR 0 write-only SSSR1 Bit1 of BTSSSR 1 write-only SSSR10 Bit10 of BTSSSR 10 write-only SSSR11 Bit11 of BTSSSR 11 write-only SSSR12 Bit12 of BTSSSR 12 write-only SSSR13 Bit13 of BTSSSR 13 write-only SSSR14 Bit14 of BTSSSR 14 write-only SSSR15 Bit15 of BTSSSR 15 write-only SSSR2 Bit2 of BTSSSR 2 write-only SSSR3 Bit3 of BTSSSR 3 write-only SSSR4 Bit4 of BTSSSR 4 write-only SSSR5 Bit5 of BTSSSR 5 write-only SSSR6 Bit6 of BTSSSR 6 write-only SSSR7 Bit7 of BTSSSR 7 write-only SSSR8 Bit8 of BTSSSR 8 write-only SSSR9 Bit9 of BTSSSR 9 write-only SWWDT Software Watchdog Timer SWWDT 0x0 0x0 0x4 registers n 0x10 0x1 registers n 0x4 0x4 registers n 0x8 0x1 registers n 0xC 0x4 registers n 0xC00 0x4 registers n SWDT 1 WDOGCONTROL Software Watchdog Timer Control Register 0x8 8 read-write n 0x0 0x0 INTEN Interrupt and counter enable bit of the software watchdog 0 read-write RESEN Reset enable bit of the software watchdog 1 read-write WDOGINTCLR Software Watchdog Timer Clear Register 0xC 32 read-write n 0x0 0x0 WDOGLOAD Software Watchdog Timer Load Register 0x0 32 read-write n 0x0 0x0 WDOGLOCK Software Watchdog Timer Lock Register 0xC00 32 read-write n 0x0 0x0 WDOGRIS Software Watchdog Timer Interrupt Status Register 0x10 8 read-only n 0x0 0x0 RIS Software watchdog interrupt status bit 0 read-only WDOGVALUE Software Watchdog Timer Value Register 0x4 32 read-only n 0x0 0x0