GigaDevice
GD32F10x_HD
2024.04.27
GD32F10x ARM 32-bit Cortex-M3 Microcontroller based device
CM3
r2p1
little
true
4
false
8
32
ADC0
Analog to digital converter
ADC
0x0
0x0
0x400
registers
n
ADC0_1
18
CTL0
CTL0
control register 0
0x4
32
read-write
n
0x0
0x0
DISIC
Discontinuous mode on inserted channels
12
1
DISNUM
Number of conversions in discontinuous mode
13
3
DISRC
Discontinuous mode on regular channels
11
1
EOCIE
Interrupt enable for EOC
5
1
EOICIE
Interrupt enable for EOIC
7
1
ICA
Inserted channel group convert automatically
10
1
IWDEN
Inserted channel analog watchdog enable
22
1
RWDEN
Regular channel analog watchdog enable
23
1
SM
Scan mode
8
1
SYNCM
sync mode selection
16
3
WDCHSEL
Analog watchdog channel select
0
5
WDEIE
Interrupt enable for WDE
6
1
WDSC
When in scan mode, analog watchdog is effective on a single channel
9
1
CTL1
CTL1
control register 1
0x8
32
read-write
n
0x0
0x0
ADCON
ADC on
0
1
CLB
ADC calibration
2
1
CTN
Continuous mode
1
1
DAL
Data alignment
11
1
DMA
DMA request enable
8
1
ETEIC
External trigger select for inserted channel
15
1
ETERC
External trigger enable for regular channel
20
1
ETSIC
External trigger select for inserted channel
12
3
ETSRC
External trigger select for regular channel
17
3
RSTCLB
Reset calibration
3
1
SWICST
Start on inserted channel
21
1
SWRCST
Start on regular channel
22
1
TSVREN
Channel 16 and 17 enable of ADC0
23
1
IDATA0
IDATA0
Inserted data register 0
0x3C
32
read-only
n
0x0
0x0
IDATAn
Inserted number n conversion data
0
16
IDATA1
IDATA1
Inserted data register 1
0x40
32
read-only
n
0x0
0x0
IDATAn
Inserted number n conversion data
0
16
IDATA2
IDATA2
Inserted data register 2
0x44
32
read-only
n
0x0
0x0
IDATAn
Inserted number n conversion data
0
16
IDATA3
IDATA3
Inserted data register 3
0x48
32
read-only
n
0x0
0x0
IDATAn
Inserted number n conversion data
0
16
IOFF0
IOFF0
Inserted channel data offset register 0
0x14
32
read-write
n
0x0
0x0
IOFF
Data offset for inserted channel 0
0
12
IOFF1
IOFF1
Inserted channel data offset register 1
0x18
32
read-write
n
0x0
0x0
IOFF
Data offset for inserted channel 1
0
12
IOFF2
IOFF2
Inserted channel data offset register 2
0x1C
32
read-write
n
0x0
0x0
IOFF
Data offset for inserted channel 2
0
12
IOFF3
IOFF3
Inserted channel data offset register 3
0x20
32
read-write
n
0x0
0x0
IOFF
Data offset for inserted channel 3
0
12
ISQ
ISQ
Inserted sequence register
0x38
32
read-write
n
0x0
0x0
IL
Inserted channel group length
20
2
ISQ0
1st conversion in inserted sequence
0
5
ISQ1
2nd conversion in inserted sequence
5
5
ISQ2
3rd conversion in inserted sequence
10
5
ISQ3
4th conversion in inserted sequence
15
5
RDATA
RDATA
regular data register
0x4C
32
read-only
n
0x0
0x0
ADC1RDTR
ADCegular channel data
16
16
RDATA
Regular channel data
0
16
RSQ0
RSQ0
regular sequence register 0
0x2C
32
read-write
n
0x0
0x0
RL
Regular channel group length
20
4
RSQ12
13th conversion in regular sequence
0
5
RSQ13
14th conversion in regular sequence
5
5
RSQ14
15th conversion in regular sequence
10
5
RSQ15
16th conversion in regular sequence
15
5
RSQ1
RSQ1
regular sequence register 1
0x30
32
read-write
n
0x0
0x0
RSQ10
11th conversion in regular sequence
20
5
RSQ11
12th conversion in regular sequence
25
5
RSQ6
7th conversion in regular sequence
0
5
RSQ7
8th conversion in regular sequence
5
5
RSQ8
9th conversion in regular sequence
10
5
RSQ9
10th conversion in regular sequence
15
5
RSQ2
RSQ2
regular sequence register 2
0x34
32
read-write
n
0x0
0x0
RSQ0
1st conversion in regular sequence
0
5
RSQ1
2nd conversion in regular sequence
5
5
RSQ2
3rd conversion in regular sequence
10
5
RSQ3
4th conversion in regular sequence
15
5
RSQ4
5th conversion in regular sequence
20
5
RSQ5
6th conversion in regular sequence
25
5
SAMPT0
SAMPT0
Sample time register 0
0xC
32
read-write
n
0x0
0x0
SPT10
Channel 10 sample time selection
0
3
SPT11
Channel 11 sample time selection
3
3
SPT12
Channel 12 sample time selection
6
3
SPT13
Channel 13 sample time selection
9
3
SPT14
Channel 14 sample time selection
12
3
SPT15
Channel 15 sample time selection
15
3
SPT16
Channel 16 sample time selection
18
3
SPT17
Channel 17 sample time selection
21
3
SAMPT1
SAMPT1
Sample time register 1
0x10
32
read-write
n
0x0
0x0
SPT0
Channel 0 sample time selection
0
3
SPT1
Channel 1 sample time selection
3
3
SPT2
Channel 2 sample time selection
6
3
SPT3
Channel 3 sample time selection
9
3
SPT4
Channel 4 sample time selection
12
3
SPT5
Channel 5 sample time selection
15
3
SPT6
Channel 6 sample time selection
18
3
SPT7
Channel 7 sample time selection
21
3
SPT8
Channel 8 sample time selection
24
3
SPT9
Channel 9 sample time selection
27
3
STAT
STAT
status register
0x0
32
read-write
n
0x0
0x0
EOC
End of group conversion flag
1
1
EOIC
End of inserted group conversion flag
2
1
STIC
Start flag of inserted channel group
3
1
STRC
Start flag of regular channel group
4
1
WDE
Analog watchdog event flag
0
1
WDHT
WDHT
watchdog higher threshold register
0x24
32
read-write
n
0x0
0x0
WDHT
Analog watchdog higher threshold
0
12
WDLT
WDLT
watchdog lower threshold register
0x28
32
read-write
n
0x0
0x0
WDLT
Analog watchdog lower threshold
0
12
ADC1
Analog to digital converter
ADC
0x0
0x0
0x400
registers
n
ADC0_1
18
CTL0
CTL0
control register 0
0x4
32
read-write
n
0x0
0x0
DISIC
Discontinuous mode on inserted channels
12
1
DISNUM
Number of conversions in discontinuous mode
13
3
DISRC
Discontinuous mode on regular channels
11
1
EOCIE
Interrupt enable for EOC
5
1
EOICIE
Interrupt enable for EOIC
7
1
ICA
Inserted channel group convert automatically
10
1
IWDEN
Inserted channel analog watchdog enable
22
1
RWDEN
Regular channel analog watchdog enable
23
1
SM
Scan mode
8
1
SYNCM
sync mode selection
16
3
WDCHSEL
Analog watchdog channel select
0
5
WDEIE
Interrupt enable for WDE
6
1
WDSC
When in scan mode, analog watchdog is effective on a single channel
9
1
CTL1
CTL1
control register 1
0x8
32
read-write
n
0x0
0x0
ADCON
ADC on
0
1
CLB
ADC calibration
2
1
CTN
Continuous mode
1
1
DAL
Data alignment
11
1
DMA
DMA request enable
8
1
ETEIC
External trigger enable for inserted channel
15
1
ETERC
External trigger enable for regular channel
20
1
ETSIC
External trigger select for inserted channel
12
3
ETSRC
External trigger select for regular channel
17
3
RSTCLB
Reset calibration
3
1
SWICST
Start on inserted channel
21
1
SWRCST
Start on regular channel
22
1
IDATA0
IDATA0
Inserted data register 0
0x3C
32
read-only
n
0x0
0x0
IDATAn
Inserted number n conversion data
0
16
IDATA1
IDATA1
Inserted data register 1
0x40
32
read-only
n
0x0
0x0
IDATAn
Inserted number n conversion data
0
16
IDATA2
IDATA2
Inserted data register 2
0x44
32
read-only
n
0x0
0x0
IDATAn
Inserted number n conversion data
0
16
IDATA3
IDATA3
Inserted data register 3
0x48
32
read-only
n
0x0
0x0
IDATAn
Inserted number n conversion data
0
16
IOFF0
IOFF0
Inserted channel data offset register 0
0x14
32
read-write
n
0x0
0x0
IOFF
Data offset for inserted channel 0
0
12
IOFF1
IOFF1
Inserted channel data offset register 1
0x18
32
read-write
n
0x0
0x0
IOFF
Data offset for inserted channel 1
0
12
IOFF2
IOFF2
Inserted channel data offset register 2
0x1C
32
read-write
n
0x0
0x0
IOFF
Data offset for inserted channel 2
0
12
IOFF3
IOFF3
Inserted channel data offset register 3
0x20
32
read-write
n
0x0
0x0
IOFF
Data offset for inserted channel 3
0
12
ISQ
ISQ
Inserted sequence register
0x38
32
read-write
n
0x0
0x0
IL
Inserted channel group length
20
2
ISQ0
1st conversion in inserted sequence
0
5
ISQ1
2nd conversion in inserted sequence
5
5
ISQ2
3rd conversion in inserted sequence
10
5
ISQ3
4th conversion in inserted sequence
15
5
RDATA
RDATA
regular data register
0x4C
32
read-only
n
0x0
0x0
RDATA
Regular channel data
0
16
RSQ0
RSQ0
regular sequence register 0
0x2C
32
read-write
n
0x0
0x0
RL
Regular channel group length
20
4
RSQ12
13th conversion in regular sequence
0
5
RSQ13
14th conversion in regular sequence
5
5
RSQ14
15th conversion in regular sequence
10
5
RSQ15
16th conversion in regular sequence
15
5
RSQ1
RSQ1
regular sequence register 1
0x30
32
read-write
n
0x0
0x0
RSQ10
11th conversion in regular sequence
20
5
RSQ11
12th conversion in regular sequence
25
5
RSQ6
7th conversion in regular sequence
0
5
RSQ7
8th conversion in regular sequence
5
5
RSQ8
9th conversion in regular sequence
10
5
RSQ9
10th conversion in regular sequence
15
5
RSQ2
RSQ2
regular sequence register 2
0x34
32
read-write
n
0x0
0x0
RSQ0
1st conversion in regular sequence
0
5
RSQ1
2nd conversion in regular sequence
5
5
RSQ2
3rd conversion in regular sequence
10
5
RSQ3
4th conversion in regular sequence
15
5
RSQ4
5th conversion in regular sequence
20
5
RSQ5
6th conversion in regular sequence
25
5
SAMPT0
SAMPT0
Sample time register 0
0xC
32
read-write
n
0x0
0x0
SPT10
Channel 10 sample time selection
0
3
SPT11
Channel 11 sample time selection
3
3
SPT12
Channel 12 sample time selection
6
3
SPT13
Channel 13 sample time selection
9
3
SPT14
Channel 14 sample time selection
12
3
SPT15
Channel 15 sample time selection
15
3
SPT16
Channel 16 sample time selection
18
3
SPT17
Channel 17 sample time selection
21
3
SAMPT1
SAMPT1
Sample time register 1
0x10
32
read-write
n
0x0
0x0
SPT0
Channel 0 sample time selection
0
3
SPT1
Channel 1 sample time selection
3
3
SPT2
Channel 2 sample time selection
6
3
SPT3
Channel 3 sample time selection
9
3
SPT4
Channel 4 sample time selection
12
3
SPT5
Channel 5 sample time selection
15
3
SPT6
Channel 6 sample time selection
18
3
SPT7
Channel 7 sample time selection
21
3
SPT8
Channel 8 sample time selection
24
3
SPT9
Channel 9 sample time selection
27
3
STAT
STAT
status register
0x0
32
read-write
n
0x0
0x0
EOC
End of group conversion flag
1
1
EOIC
End of inserted group conversion flag
2
1
STIC
Start flag of inserted channel group
3
1
STRC
Start flag of regular channel group
4
1
WDE
Analog watchdog event flag
0
1
WDHT
WDHT
watchdog higher threshold register
0x24
32
read-write
n
0x0
0x0
WDHT
Analog watchdog higher threshold
0
12
WDLT
WDLT
watchdog lower threshold register
0x28
32
read-write
n
0x0
0x0
WDLT
Analog watchdog lower threshold
0
12
ADC2
Analog to digital converter
ADC
0x0
0x0
0x400
registers
n
ADC2
47
CTL0
CTL0
control register 0
0x4
32
read-write
n
0x0
0x0
DISIC
Discontinuous mode on inserted channels
12
1
DISNUM
Number of conversions in discontinuous mode
13
3
DISRC
Discontinuous mode on regular channels
11
1
EOCIE
Interrupt enable for EOC
5
1
EOICIE
Interrupt enable for EOIC
7
1
ICA
Inserted channel group convert automatically
10
1
IWDEN
Inserted channel analog watchdog enable
22
1
RWDEN
Regular channel analog watchdog enable
23
1
SM
Scan mode
8
1
SYNCM
sync mode selection
16
3
WDCHSEL
Analog watchdog channel select
0
5
WDEIE
Interrupt enable for WDE
6
1
WDSC
When in scan mode, analog watchdog is effective on a single channel
9
1
CTL1
CTL1
control register 1
0x8
32
read-write
n
0x0
0x0
ADCON
ADC on
0
1
CLB
ADC calibration
2
1
CTN
Continuous mode
1
1
DAL
Data alignment
11
1
DMA
DMA request enable
8
1
ETEIC
External trigger enable for inserted channel
15
1
ETERC
External trigger enable for regular channel
20
1
ETSIC
External trigger select for inserted channel
12
3
ETSRC
External trigger select for regular channel
17
3
RSTCLB
Reset calibration
3
1
SWICST
Start on inserted channel
21
1
SWRCST
Start on regular channel
22
1
IDATA0
IDATA0
Inserted data register 0
0x3C
32
read-only
n
0x0
0x0
IDATAn
Inserted number n conversion data
0
16
IDATA1
IDATA1
Inserted data register 1
0x40
32
read-only
n
0x0
0x0
IDATAn
Inserted number n conversion data
0
16
IDATA2
IDATA2
Inserted data register 2
0x44
32
read-only
n
0x0
0x0
IDATAn
Inserted number n conversion data
0
16
IDATA3
IDATA3
Inserted data register 3
0x48
32
read-only
n
0x0
0x0
IDATAn
Inserted number n conversion data
0
16
IOFF0
IOFF0
Inserted channel data offset register 0
0x14
32
read-write
n
0x0
0x0
IOFF
Data offset for inserted channel 0
0
12
IOFF1
IOFF1
Inserted channel data offset register 1
0x18
32
read-write
n
0x0
0x0
IOFF
Data offset for inserted channel 1
0
12
IOFF2
IOFF2
Inserted channel data offset register 2
0x1C
32
read-write
n
0x0
0x0
IOFF
Data offset for inserted channel 2
0
12
IOFF3
IOFF3
Inserted channel data offset register 3
0x20
32
read-write
n
0x0
0x0
IOFF
Data offset for inserted channel 3
0
12
ISQ
ISQ
Inserted sequence register
0x38
32
read-write
n
0x0
0x0
IL
Inserted channel group length
20
2
ISQ0
1st conversion in inserted sequence
0
5
ISQ1
2nd conversion in inserted sequence
5
5
ISQ2
3rd conversion in inserted sequence
10
5
ISQ3
4th conversion in inserted sequence
15
5
RDATA
RDATA
regular data register
0x4C
32
read-only
n
0x0
0x0
RDATA
Regular channel data
0
16
RSQ0
RSQ0
regular sequence register 0
0x2C
32
read-write
n
0x0
0x0
RL
Regular channel group length
20
4
RSQ12
13th conversion in regular sequence
0
5
RSQ13
14th conversion in regular sequence
5
5
RSQ14
15th conversion in regular sequence
10
5
RSQ15
16th conversion in regular sequence
15
5
RSQ1
RSQ1
regular sequence register 1
0x30
32
read-write
n
0x0
0x0
RSQ10
11th conversion in regular sequence
20
5
RSQ11
12th conversion in regular sequence
25
5
RSQ6
7th conversion in regular sequence
0
5
RSQ7
8th conversion in regular sequence
5
5
RSQ8
9th conversion in regular sequence
10
5
RSQ9
10th conversion in regular sequence
15
5
RSQ2
RSQ2
regular sequence register 2
0x34
32
read-write
n
0x0
0x0
RSQ0
1st conversion in regular sequence
0
5
RSQ1
2nd conversion in regular sequence
5
5
RSQ2
3rd conversion in regular sequence
10
5
RSQ3
4th conversion in regular sequence
15
5
RSQ4
5th conversion in regular sequence
20
5
RSQ5
6th conversion in regular sequence
25
5
SAMPT0
SAMPT0
Sample time register 0
0xC
32
read-write
n
0x0
0x0
SPT10
Channel 10 sample time selection
0
3
SPT11
Channel 11 sample time selection
3
3
SPT12
Channel 12 sample time selection
6
3
SPT13
Channel 13 sample time selection
9
3
SPT14
Channel 14 sample time selection
12
3
SPT15
Channel 15 sample time selection
15
3
SPT16
Channel 16 sample time selection
18
3
SPT17
Channel 17 sample time selection
21
3
SAMPT1
SAMPT1
Sample time register 1
0x10
32
read-write
n
0x0
0x0
SPT0
Channel 0 sample time selection
0
3
SPT1
Channel 1 sample time selection
3
3
SPT2
Channel 2 sample time selection
6
3
SPT3
Channel 3 sample time selection
9
3
SPT4
Channel 4 sample time selection
12
3
SPT5
Channel 5 sample time selection
15
3
SPT6
Channel 6 sample time selection
18
3
SPT7
Channel 7 sample time selection
21
3
SPT8
Channel 8 sample time selection
24
3
SPT9
Channel 9 sample time selection
27
3
STAT
STAT
status register
0x0
32
read-write
n
0x0
0x0
EOC
End of group conversion flag
1
1
EOIC
End of inserted group conversion flag
2
1
STIC
Start flag of inserted channel group
3
1
STRC
Start flag of regular channel group
4
1
WDE
Analog watchdog event flag
0
1
WDHT
WDHT
watchdog higher threshold register
0x24
32
read-write
n
0x0
0x0
WDHT
Analog watchdog higher threshold
0
12
WDLT
WDLT
watchdog lower threshold register
0x28
32
read-write
n
0x0
0x0
WDLT
Analog watchdog lower threshold
0
12
AFIO
Alternate-function I/Os
AFIO
0x0
0x0
0x400
registers
n
EC
EC
Event control register
0x0
32
read-write
n
0x0
0x0
EOE
Event output enable
7
1
PIN
Event output pin selection
0
4
PORT
Event output port selection
4
3
EXTISS0
EXTISS0
EXTI sources selection register 0
0x8
32
read-write
n
0x0
0x0
EXTI0_SS
EXTI 0 sources selection
0
4
EXTI1_SS
EXTI 1 sources selection
4
4
EXTI2_SS
EXTI 2 sources selection
8
4
EXTI3_SS
EXTI 3 sources selection
12
4
EXTISS1
EXTISS1
EXTI sources selection register 1
0xC
32
read-write
n
0x0
0x0
EXTI4_SS
EXTI 4 sources selection
0
4
EXTI5_SS
EXTI 5 sources selection
4
4
EXTI6_SS
EXTI 6 sources selection
8
4
EXTI7_SS
EXTI 7 sources selection
12
4
EXTISS2
EXTISS2
EXTI sources selection register 2
0x10
32
read-write
n
0x0
0x0
EXTI10_SS
EXTI 10 sources selection
8
4
EXTI11_SS
EXTI 11 sources selection
12
4
EXTI8_SS
EXTI 8 sources selection
0
4
EXTI9_SS
EXTI 9 sources selection
4
4
EXTISS3
EXTISS3
EXTI sources selection register 3
0x14
32
read-write
n
0x0
0x0
EXTI12_SS
EXTI 12 sources selection
0
4
EXTI13_SS
EXTI 13 sources selection
4
4
EXTI14_SS
EXTI 14 sources selection
8
4
EXTI15_SS
EXTI 15 sources selection
12
4
PCF0
PCF0
AFIO port configuration register 0
0x4
32
read-write
n
0x0
0x0
ADC0_ETRGINS_REMAP
ADC0 external trigger inserted conversion remapping
17
1
ADC0_ETRGREG_REMAP
ADC0 external trigger regular conversion remapping
18
1
ADC1_ETRGINS_REMAP
ADC1 external trigger inserted conversion remapping
19
1
ADC1_ETRGREG_REMAP
ADC1 external trigger regular conversion remapping
20
1
CAN_REMAP
CAN alternate interface remapping
13
2
I2C0_REMAP
I2C0 remapping
1
1
PD01_REMAP
Port D0/Port D1 mapping on OSC_IN/OSC_OUT
15
1
SPI0_REMAP
SPI0 remapping
0
1
SWJ_CFG
Serial wire JTAG configuration
24
3
TIMER0_REMAP
TIMER0 remapping
6
2
TIMER1_REMAP
TIMER1 remapping
8
2
TIMER2_REMAP
TIMER2 remapping
10
2
TIMER3_REMAP
TIMER3 remapping
12
1
TIMER4CH3_IREMAP
TIMER4 channel3 internal remapping
16
1
USART0_REMAP
USART0 remapping
2
1
USART1_REMAP
USART1 remapping
3
1
USART2_REMAP
USART2 remapping
4
2
PCF1
PCF1
AFIO port configuration register 1
0x1C
32
read-write
n
0x0
0x0
FSMC_NADV
FSMC_NADV connect/disconnect
10
1
TIMER10_REMAP
TIMER10 remapping
7
1
TIMER12_REMAP
TIMER12 remapping
8
1
TIMER13_REMAP
TIMER13 remapping
9
1
TIMER8_REMAP
TIMER8 remapping
5
1
TIMER9_REMAP
TIMER9 remapping
6
1
BKP
Backup registers
BKP
0x0
0x0
0x400
registers
n
Tamper
2
DATA0
DATA0
Backup data register 0
0x4
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA1
DATA1
Backup data register 1
0x8
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA10
DATA10
Backup data register 10
0x40
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA11
DATA11
Backup data register 11
0x44
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA12
DATA12
Backup data register 12
0x48
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA13
DATA13
Backup data register 13
0x4C
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA14
DATA14
Backup data register 14
0x50
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA15
DATA15
Backup data register 15
0x54
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA16
DATA16
Backup data register 16
0x58
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA17
DATA17
Backup data register 17
0x5C
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA18
DATA18
Backup data register 18
0x60
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA19
DATA19
Backup data register 19
0x64
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA2
DATA2
Backup data register 2
0xC
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA20
DATA20
Backup data register 20
0x68
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA21
DATA21
Backup data register 21
0x6C
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA22
DATA22
Backup data register 22
0x70
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA23
DATA23
Backup data register 23
0x74
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA24
DATA24
Backup data register 24
0x78
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA25
DATA25
Backup data register 25
0x7C
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA26
DATA26
Backup data register 26
0x80
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA27
DATA27
Backup data register 27
0x84
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA28
DATA28
Backup data register 28
0x88
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA29
DATA29
Backup data register 29
0x8C
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA3
DATA3
Backup data register 3
0x10
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA30
DATA30
Backup data register 30
0x90
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA31
DATA31
Backup data register 31
0x94
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA32
DATA32
Backup data register 32
0x98
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA33
DATA33
Backup data register 33
0x9C
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA34
DATA34
Backup data register 34
0xA0
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA35
DATA35
Backup data register 35
0xA4
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA36
DATA36
Backup data register 36
0xA8
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA37
DATA37
Backup data register 37
0xAC
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA38
DATA38
Backup data register 38
0xB0
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA39
DATA39
Backup data register 39
0xB4
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA4
DATA4
Backup data register 4
0x14
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA40
DATA40
Backup data register 40
0xB8
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA41
DATA41
Backup data register 41
0xBC
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA5
DATA5
Backup data register 5
0x18
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA6
DATA6
Backup data register 6
0x1C
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA7
DATA7
Backup data register 7
0x20
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA8
DATA8
Backup data register 8
0x24
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
DATA9
DATA9
Backup data register 9
0x28
32
read-write
n
0x0
0x0
DATA
Backup data
0
16
OCTL
OCTL
RTC signal output control register
0x2C
32
read-write
n
0x0
0x0
ASOEN
RTC alarm or second signal output enable
8
1
COEN
RTC clock calibration output enable
7
1
RCCV
RTC clock calibration value
0
7
ROSEL
RTC output selection
9
1
TPCS
TPCS
Tamper control and status register
0x34
32
read-write
n
0x0
0x0
TEF
Tamper event flag
8
1
TER
Tamper event reset
0
1
TIF
Tamper interrupt flag
9
1
TIR
Tamper interrupt reset
1
1
TPIE
Tamper interrupt enable
2
1
TPCTL
TPCTL
Tamper pin control register
0x30
32
read-write
n
0x0
0x0
TPAL
TAMPER pin active level
1
1
TPEN
TAMPER detection enable
0
1
CAN
Controller area network
CAN
0x0
0x0
0x400
registers
n
CAN0_RX1
21
CAN0_EWMC
22
BT
BT
Bit timing register
0x1C
32
read-write
n
0x0
0x0
BAUDPSC
Baud rate prescaler
0
10
BS1
Bit segment 1
16
4
BS2
Bit segment 2
20
3
LCMOD
Loopback communication mode
30
1
SCMOD
Silent communication mode
31
1
SJW
Resynchronization jump width
24
2
CTL
CTL
Control register
0x0
32
read-write
n
0x0
0x0
ABOR
Automatic bus-off recovery
6
1
ARD
Automatic retransmission disable
4
1
AWU
Automatic wakeup
5
1
DFZ
Debug freeze
16
1
IWMOD
Initial working mode
0
1
RFOD
Receive FIFO overwrite disable
3
1
SLPWMOD
Sleep working mode
1
1
SWRST
Software reset
15
1
TFO
Transmit FIFO order
2
1
TTC
Time-triggered communication
7
1
ERR
ERR
Error register
0x18
32
read-write
n
0x0
0x0
BOERR
Bus-off error
2
1
read-only
ERRN
Error number
4
3
read-write
PERR
Passive error
1
1
read-only
RECNT
Receive Error Count defined by the CAN standard
24
8
read-only
TECNT
Transmit Error Count defined by the CAN standard
16
8
read-only
WERR
Warning error
0
1
read-only
F0DATA0
F0DATA0
Filter 0 data 0 register
0x240
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F0DATA1
F0DATA1
Filter 0 data 1 register
0x244
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F10DATA0
F10DATA0
Filter 10 data 0 register
0x290
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F10DATA1
F10DATA1
Filter 10 data 1 register
0x294
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F11DATA0
F11DATA0
Filter 11 data 0 register
0x298
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F11DATA1
F11DATA1
Filter 11 data 1 register
0x29C
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F12DATA0
F12DATA0
Filter 12 data 0 register
0x2A0
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F12DATA1
F12DATA1
Filter 12 data 1 register
0x2A4
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F13DATA0
F13DATA0
Filter 13 data 0 register
0x2A8
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F13DATA1
F13DATA1
Filter 13 data 1 register
0x2AC
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F14DATA0
F14DATA0
Filter 14 data 0 register
0x2B0
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F14DATA1
F14DATA1
Filter 14 data 1 register
0x2B4
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F15DATA0
F15DATA0
Filter 15 data 0 register
0x2B8
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F15DATA1
F15DATA1
Filter 15 data 1 register
0x2BC
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F16DATA0
F16DATA0
Filter 16 data 0 register
0x2C0
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F16DATA1
F16DATA1
Filter 16 data 1 register
0x2C4
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F17DATA0
F17DATA0
Filter 17 data 0 register
0x2C8
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F17DATA1
F17DATA1
Filter 17 data 1 register
0x2CC
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F18DATA0
F18DATA0
Filter 18 data 0 register
0x2D0
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F18DATA1
F18DATA1
Filter 18 data 1 register
0x2D4
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F19DATA0
F19DATA0
Filter 19 data 0 register
0x2D8
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F19DATA1
F19DATA1
Filter 19 data 1 register
0x2DC
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F1DATA0
F1DATA0
Filter 1 data 0 register
0x248
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F1DATA1
F1DATA1
Filter 1 data 1 register
0x24C
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F20DATA0
F20DATA0
Filter 20 data 0 register
0x2E0
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F20DATA1
F20DATA1
Filter 20 data 1 register
0x2E4
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F21DATA0
F21DATA0
Filter 21 data 0 register
0x2E8
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F21DATA1
F21DATA1
Filter 21 data 1 register
0x2EC
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F22DATA0
F22DATA0
Filter 22 data 0 register
0x2F0
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F22DATA1
F22DATA1
Filter 22 data 1 register
0x2F4
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F23DATA0
F23DATA0
Filter 23 data 0 register
0x2F8
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F23DATA1
F23DATA1
Filter 23 data 1 register
0x2FC
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F24DATA0
F24DATA0
Filter 24 data 0 register
0x300
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F24DATA1
F24DATA1
Filter 24 data 1 register
0x304
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F25DATA0
F25DATA0
Filter 25 data 0 register
0x308
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F25DATA1
F25DATA1
Filter 25 data 1 register
0x30C
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F26DATA0
F26DATA0
Filter 26 data 0 register
0x310
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F26DATA1
F26DATA1
Filter 26 data 1 register
0x314
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F27DATA0
F27DATA0
Filter 27 data 0 register
0x318
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F27DATA1
F27DATA1
Filter 27 data 1 register
0x31C
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F2DATA0
F2DATA0
Filter 2 data 0 register
0x250
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F2DATA1
F2DATA1
Filter 2 data 1 register
0x254
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F3DATA0
F3DATA0
Filter 3 data 0 register
0x258
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F3DATA1
F3DATA1
Filter 3 data 1 register
0x25C
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F4DATA0
F4DATA0
Filter 4 data 0 register
0x260
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F4DATA1
F4DATA1
Filter 4 data 1 register
0x264
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F5DATA0
F5DATA0
Filter 5 data 0 register
0x268
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F5DATA1
F5DATA1
Filter 5 data 1 register
0x26C
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F6DATA0
F6DATA0
Filter 6 data 0 register
0x270
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F6DATA1
F6DATA1
Filter 6 data 1 register
0x274
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F7DATA0
F7DATA0
Filter 7 data 0 register
0x278
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F7DATA1
F7DATA1
Filter 7 data 1 register
0x27C
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F8DATA0
F8DATA0
Filter 8 data 0 register
0x280
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F8DATA1
F8DATA1
Filter 8 data 1 register
0x284
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F9DATA0
F9DATA0
Filter 9 data 0 register
0x288
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
F9DATA1
F9DATA1
Filter 9 data 1 register
0x28C
32
read-write
n
0x0
0x0
FD0
Filter bits
0
1
FD1
Filter bits
1
1
FD10
Filter bits
10
1
FD11
Filter bits
11
1
FD12
Filter bits
12
1
FD13
Filter bits
13
1
FD14
Filter bits
14
1
FD15
Filter bits
15
1
FD16
Filter bits
16
1
FD17
Filter bits
17
1
FD18
Filter bits
18
1
FD19
Filter bits
19
1
FD2
Filter bits
2
1
FD20
Filter bits
20
1
FD21
Filter bits
21
1
FD22
Filter bits
22
1
FD23
Filter bits
23
1
FD24
Filter bits
24
1
FD25
Filter bits
25
1
FD26
Filter bits
26
1
FD27
Filter bits
27
1
FD28
Filter bits
28
1
FD29
Filter bits
29
1
FD3
Filter bits
3
1
FD30
Filter bits
30
1
FD31
Filter bits
31
1
FD4
Filter bits
4
1
FD5
Filter bits
5
1
FD6
Filter bits
6
1
FD7
Filter bits
7
1
FD8
Filter bits
8
1
FD9
Filter bits
9
1
FAFIFO
FAFIFO
Filter associated FIFO register
0x214
32
read-write
n
0x0
0x0
FAF0
Filter 0 associated with FIFO
0
1
FAF1
Filter 1 associated with FIFO
1
1
FAF10
Filter 10 associated with FIFO
10
1
FAF11
Filter 11 associated with FIFO
11
1
FAF12
Filter 12 associated with FIFO
12
1
FAF13
Filter 13 associated with FIFO
13
1
FAF14
Filter 14 associated with FIFO
14
1
FAF15
Filter 15 associated with FIFO
15
1
FAF16
Filter 16 associated with FIFO
16
1
FAF17
Filter 17 associated with FIFO
17
1
FAF18
Filter 18 associated with FIFO
18
1
FAF19
Filter 19 associated with FIFO
19
1
FAF2
Filter 2 associated with FIFO
2
1
FAF20
Filter 20 associated with FIFO
20
1
FAF21
Filter 21 associated with FIFO
21
1
FAF22
Filter 22 associated with FIFO
22
1
FAF23
Filter 23 associated with FIFO
23
1
FAF24
Filter 24 associated with FIFO
24
1
FAF25
Filter 25 associated with FIFO
25
1
FAF26
Filter 26 associated with FIFO
26
1
FAF27
Filter 27 associated with FIFO
27
1
FAF3
Filter 3 associated with FIFO
3
1
FAF4
Filter 4 associated with FIFO
4
1
FAF5
Filter 5 associated with FIFO
5
1
FAF6
Filter 6 associated with FIFO
6
1
FAF7
Filter 7 associated with FIFO
7
1
FAF8
Filter 8 associated with FIFO
8
1
FAF9
Filter 9 associated with FIFO
9
1
FCTL
FCTL
Filter control register
0x200
32
read-write
n
0x0
0x0
FLD
Filter lock disable
0
1
FMCFG
FMCFG
Filter mode configuration register
0x204
32
read-write
n
0x0
0x0
FMOD0
Filter mode
0
1
FMOD1
Filter mode
1
1
FMOD10
Filter mode
10
1
FMOD11
Filter mode
11
1
FMOD12
Filter mode
12
1
FMOD13
Filter mode
13
1
FMOD14
Filter mode
14
1
FMOD15
Filter mode
15
1
FMOD16
Filter mode
16
1
FMOD17
Filter mode
17
1
FMOD18
Filter mode
18
1
FMOD19
Filter mode
19
1
FMOD2
Filter mode
2
1
FMOD20
Filter mode
20
1
FMOD21
Filter mode
21
1
FMOD22
Filter mode
22
1
FMOD23
Filter mode
23
1
FMOD24
Filter mode
24
1
FMOD25
Filter mode
25
1
FMOD26
Filter mode
26
1
FMOD27
Filter mode
27
1
FMOD3
Filter mode
3
1
FMOD4
Filter mode
4
1
FMOD5
Filter mode
5
1
FMOD6
Filter mode
6
1
FMOD7
Filter mode
7
1
FMOD8
Filter mode
8
1
FMOD9
Filter mode
9
1
FSCFG
FSCFG
Filter scale configuration register
0x20C
32
read-write
n
0x0
0x0
FS0
Filter scale configuration
0
1
FS1
Filter scale configuration
1
1
FS10
Filter scale configuration
10
1
FS11
Filter scale configuration
11
1
FS12
Filter scale configuration
12
1
FS13
Filter scale configuration
13
1
FS14
Filter scale configuration
14
1
FS15
Filter scale configuration
15
1
FS16
Filter scale configuration
16
1
FS17
Filter scale configuration
17
1
FS18
Filter scale configuration
18
1
FS19
Filter scale configuration
19
1
FS2
Filter scale configuration
2
1
FS20
Filter scale configuration
20
1
FS21
Filter scale configuration
21
1
FS22
Filter scale configuration
22
1
FS23
Filter scale configuration
23
1
FS24
Filter scale configuration
24
1
FS25
Filter scale configuration
25
1
FS26
Filter scale configuration
26
1
FS27
Filter scale configuration
27
1
FS3
Filter scale configuration
3
1
FS4
Filter scale configuration
4
1
FS5
Filter scale configuration
5
1
FS6
Filter scale configuration
6
1
FS7
Filter scale configuration
7
1
FS8
Filter scale configuration
8
1
FS9
Filter scale configuration
9
1
FW
FW
Filter working register
0x21C
32
read-write
n
0x0
0x0
FW0
Filter working
0
1
FW1
Filter working
1
1
FW10
Filter working
10
1
FW11
Filter working
11
1
FW12
Filter working
12
1
FW13
Filter working
13
1
FW14
Filter working
14
1
FW15
Filter working
15
1
FW16
Filter working
16
1
FW17
Filter working
17
1
FW18
Filter working
18
1
FW19
Filter working
19
1
FW2
Filter working
2
1
FW20
Filter working
20
1
FW21
Filter working
21
1
FW22
Filter working
22
1
FW23
Filter working
23
1
FW24
Filter working
24
1
FW25
Filter working
25
1
FW26
Filter working
26
1
FW27
Filter working
27
1
FW3
Filter working
3
1
FW4
Filter working
4
1
FW5
Filter working
5
1
FW6
Filter working
6
1
FW7
Filter working
7
1
FW8
Filter working
8
1
FW9
Filter working
9
1
INTEN
INTEN
Interrupt enable register
0x14
32
read-write
n
0x0
0x0
BOIE
Bus-off interrupt enable
10
1
ERRIE
Error interrupt enable
15
1
ERRNIE
Error number interrupt enable
11
1
PERRIE
Passive error interrupt enable
9
1
RFFIE0
Receive FIFO0 full interrupt enable
2
1
RFFIE1
Receive FIFO1 full interrupt enable
5
1
RFNEIE0
Receive FIFO0 not empty interrupt enable
1
1
RFNEIE1
Receive FIFO1 not empty interrupt enable
4
1
RFOIE0
Receive FIFO0 overfull interrupt enable
3
1
RFOIE1
Receive FIFO1 overfull interrupt enable
6
1
SLPWIE
Sleep working interrupt enable
17
1
TMEIE
Transmit mailbox empty interrupt enable
0
1
WERRIE
Warning error interrupt enable
8
1
WIE
Wakeup interrupt enable
16
1
RFIFO0
RFIFO0
Receive message FIFO0 register
0xC
32
read-write
n
0x0
0x0
RFD0
Receive FIFO0 dequeue
5
1
read-write
RFF0
Receive FIFO0 full
3
1
read-write
RFL0
Receive FIFO0 length
0
2
read-only
RFO0
Receive FIFO0 overfull
4
1
read-write
RFIFO1
RFIFO1
Receive message FIFO1 register
0x10
32
read-write
n
0x0
0x0
RFD1
Receive FIFO1 dequeue
5
1
read-write
RFF1
Receive FIFO1 full
3
1
read-write
RFL1
Receive FIFO1 length
0
2
read-only
RFO1
Receive FIFO1 overfull
4
1
read-write
RFIFOMDATA00
RFIFOMDATA00
Receive FIFO0 mailbox data0 register
0x1B8
32
read-only
n
0x0
0x0
DB0
Data byte 0
0
8
DB1
Data byte 1
8
8
DB2
Data byte 2
16
8
DB3
Data byte 3
24
8
RFIFOMDATA01
RFIFOMDATA01
Receive FIFO1 mailbox data0 register
0x1C8
32
read-only
n
0x0
0x0
DB0
Data byte 0
0
8
DB1
Data byte 1
8
8
DB2
Data byte 2
16
8
DB3
Data byte 3
24
8
RFIFOMDATA10
RFIFOMDATA10
Receive FIFO0 mailbox data1 register
0x1BC
32
read-only
n
0x0
0x0
DB4
Data byte 4
0
8
DB5
Data byte 5
8
8
DB6
Data byte 6
16
8
DB7
Data byte 7
24
8
RFIFOMDATA11
RFIFOMDATA11
Receive FIFO1 mailbox data1 register
0x1CC
32
read-only
n
0x0
0x0
DB4
Data byte 4
0
8
DB5
Data byte 5
8
8
DB6
Data byte 6
16
8
DB7
Data byte 7
24
8
RFIFOMI0
RFIFOMI0
Receive FIFO mailbox identifier register
0x1B0
32
read-only
n
0x0
0x0
EFID
The frame identifier
3
18
FF
Frame format
2
1
FT
Frame type
1
1
SFID_EFID
The frame identifier
21
11
RFIFOMI1
RFIFOMI1
Receive FIFO1 mailbox identifier register
0x1C0
32
read-only
n
0x0
0x0
EFID
The frame identifier
3
18
FF
Frame format
2
1
FT
Frame type
1
1
SFID_EFID
The frame identifier
21
11
RFIFOMP0
RFIFOMP0
Receive FIFO0 mailbox property register
0x1B4
32
read-only
n
0x0
0x0
DLENC
Data length code
0
4
FI
Filtering index
8
8
TS
Time stamp
16
16
RFIFOMP1
RFIFOMP1
Receive FIFO1 mailbox property register
0x1C4
32
read-only
n
0x0
0x0
DLENC
Data length code
0
4
FI
Filtering index
8
8
TS
Time stamp
16
16
STAT
STAT
Status register
0x4
32
read-write
n
0x0
0x0
ERRIF
Error interrupt flag
2
1
read-write
IWS
Initial working state
0
1
read-only
LASTRX
Last sample value of RX pin
10
1
read-only
RS
Receiving state
9
1
read-only
RXL
RX level
11
1
read-only
SLPIF
Status change interrupt flag of sleep working mode entering
4
1
read-write
SLPWS
Sleep working state
1
1
read-only
TS
Transmitting state
8
1
read-only
WUIF
Status change interrupt flag of wakeup from sleep working mode
3
1
read-write
TMDATA00
TMDATA00
Transmit mailbox data0 register
0x188
32
read-write
n
0x0
0x0
DB0
Data byte 0
0
8
DB1
Data byte 1
8
8
DB2
Data byte 2
16
8
DB3
Data byte 3
24
8
TMDATA01
TMDATA01
Transmit mailbox data0 register
0x198
32
read-write
n
0x0
0x0
DB0
Data byte 0
0
8
DB1
Data byte 1
8
8
DB2
Data byte 2
16
8
DB3
Data byte 3
24
8
TMDATA02
TMDATA02
Transmit mailbox data0 register
0x1A8
32
read-write
n
0x0
0x0
DB0
Data byte 0
0
8
DB1
Data byte 1
8
8
DB2
Data byte 2
16
8
DB3
Data byte 3
24
8
TMDATA10
TMDATA10
Transmit mailbox data1 register
0x18C
32
read-write
n
0x0
0x0
DB4
Data byte 4
0
8
DB5
Data byte 5
8
8
DB6
Data byte 6
16
8
DB7
Data byte 7
24
8
TMDATA11
TMDATA11
Transmit mailbox data1 register
0x19C
32
read-write
n
0x0
0x0
DB4
Data byte 4
0
8
DB5
Data byte 5
8
8
DB6
Data byte 6
16
8
DB7
Data byte 7
24
8
TMDATA12
TMDATA12
Transmit mailbox data1 register
0x1AC
32
read-write
n
0x0
0x0
DB4
Data byte 4
0
8
DB5
Data byte 5
8
8
DB6
Data byte 6
16
8
DB7
Data byte 7
24
8
TMI0
TMI0
Transmit mailbox identifier register 0
0x180
32
read-write
n
0x0
0x0
EFID
The frame identifier
3
18
FF
Frame format
2
1
FT
Frame type
1
1
SFID_EFID
The frame identifier
21
11
TEN
Transmit enable
0
1
TMI1
TMI1
Transmit mailbox identifier register 1
0x190
32
read-write
n
0x0
0x0
EFID
The frame identifier
3
18
FF
Frame format
2
1
FT
Frame type
1
1
SFID_EFID
The frame identifier
21
11
TEN
Transmit enable
0
1
TMI2
TMI2
Transmit mailbox identifier register 2
0x1A0
32
read-write
n
0x0
0x0
EFID
The frame identifier
3
18
FF
Frame format
2
1
FT
Frame type
1
1
SFID_EFID
The frame identifier
21
11
TEN
Transmit enable
0
1
TMP0
TMP0
Transmit mailbox property register 0
0x184
32
read-write
n
0x0
0x0
DLENC
Data length code
0
4
TS
Time stamp
16
16
TSEN
Time stamp enable
8
1
TMP1
TMP1
Transmit mailbox property register 1
0x194
32
read-write
n
0x0
0x0
DLENC
Data length code
0
4
TS
Time stamp
16
16
TSEN
Time stamp enable
8
1
TMP2
TMP2
Transmit mailbox property register 2
0x1A4
32
read-write
n
0x0
0x0
DLENC
Data length code
0
4
TS
Time stamp
16
16
TSEN
Time stamp enable
8
1
TSTAT
TSTAT
Transmit status register
0x8
32
read-write
n
0x0
0x0
MAL0
Mailbox 0 arbitration lost
2
1
read-write
MAL1
Mailbox 1 arbitration lost
10
1
read-write
MAL2
Mailbox 2 arbitration lost
18
1
read-write
MST0
Mailbox 0 stop transmitting
7
1
read-write
MST1
Mailbox 1 stop transmitting
15
1
read-write
MST2
Mailbox 2 stop transmitting
23
1
read-write
MTE0
Mailbox 0 transmit error
3
1
read-write
MTE1
Mailbox 1 transmit error
11
1
read-write
MTE2
Mailbox 2 transmit error
19
1
read-write
MTF0
Mailbox 0 transmit finished
0
1
read-write
MTF1
Mailbox 1 transmit finished
8
1
read-write
MTF2
Mailbox 2 transmit finished
16
1
read-write
MTFNERR0
Mailbox 0 transmit finished and no error
1
1
read-write
MTFNERR1
Mailbox 1 transmit finished and no error
9
1
read-write
MTFNERR2
Mailbox 2 transmit finished and no error
17
1
read-write
NUM
number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty
24
2
read-only
TME0
Transmit mailbox 0 empty
26
1
read-only
TME1
Transmit mailbox 1 empty
27
1
read-only
TME2
Transmit mailbox 2 empty
28
1
read-only
TMLS0
Transmit mailbox 0 last sending in transmit FIFO
29
1
read-only
TMLS1
Transmit mailbox 1 last sending in transmit FIFO
30
1
read-only
TMLS2
Transmit mailbox 2 last sending in transmit FIFO
31
1
read-only
CRC
cyclic redundancy check calculation unit
CRC
0x0
0x0
0x400
registers
n
CTL
CTL
Control register
0x8
32
read-write
n
0x0
0x0
RST
reset bit
0
1
DATA
DATA
Data register
0x0
32
read-write
n
0x0
0x0
DATA
CRC calculation result bits
0
32
FDATA
FDATA
Free data register
0x4
32
read-write
n
0x0
0x0
FDATA
Free Data Register bits
0
8
DAC
Digital-to-analog converter
DAC
0x0
0x0
0x400
registers
n
CTL
CTL
control register
0x0
32
read-write
n
0x0
0x0
DBOFF0
DAC0 output buffer turn off
1
1
DBOFF1
DAC1 output buffer turn off
17
1
DDMAEN0
DAC0 DMA enable
12
1
DDMAEN1
DAC1 DMA enable
28
1
DEN0
DAC0 enable
0
1
DEN1
DAC1 enable
16
1
DTEN0
DAC0 trigger enable
2
1
DTEN1
DAC1 trigger enable
18
1
DTSEL0
DAC0 trigger selection
3
3
DTSEL1
DAC1 trigger selection
19
3
DWBW0
DAC0 noise wave bit width
8
4
DWBW1
DAC1 noise wave bit width
24
4
DWM0
DAC0 noise wave mode
6
2
DWM1
DAC1 noise wave mode
22
2
DAC0_DO
DAC0_DO
DAC0 data output register
0x2C
32
read-only
n
0x0
0x0
DAC0_DO
DAC0 data output
0
12
DAC0_L12DH
DAC0_L12DH
DAC0 12-bit left-aligned data holding register
0xC
32
read-write
n
0x0
0x0
DAC0_DH
DAC0 12-bit left-aligned data
4
12
DAC0_R12DH
DAC0_R12DH
DAC0 12-bit right-aligned data holding register
0x8
32
read-write
n
0x0
0x0
DAC0_DH
DAC0 12-bit right-aligned data
0
12
DAC0_R8DH
DAC0_R8DH
DAC0 8-bit right aligned data holding register
0x10
32
read-write
n
0x0
0x0
DAC0_DH
DAC0 8-bit right-aligned data
0
8
DAC1_DO
DAC1_DO
DAC1 data output register
0x30
32
read-only
n
0x0
0x0
DAC1_DO
DAC1 data output
0
12
DAC1_L12DH
DAC1_L12DH
DAC1 12-bit left aligned data holding register
0x18
32
read-write
n
0x0
0x0
DAC1_DH
DAC1 12-bit left-aligned data
4
12
DAC1_R12DH
DAC1_R12DH
DAC1 12-bit right-aligned data holding register
0x14
32
read-write
n
0x0
0x0
DAC1_DH
DAC1 12-bit right-aligned data
0
12
DAC1_R8DH
DAC1_R8DH
DAC1 8-bit right aligned data holding register
0x1C
32
read-write
n
0x0
0x0
DAC1_DH
DAC1 8-bit right-aligned data
0
8
DACC_L12DH
DACC_L12DH
DAC concurrent mode 12-bit left aligned data holding register
0x24
32
read-write
n
0x0
0x0
DAC0_DH
DAC0 12-bit left-aligned data
4
12
DAC1_DH
DAC1 12-bit left-aligned data
20
12
DACC_R12DH
DACC_R12DH
DAC concurrent mode 12-bit right-aligned data holding register
0x20
32
read-write
n
0x0
0x0
DAC0_DH
DAC0 12-bit right-aligned data
0
12
DAC1_DH
DAC1 12-bit right-aligned data
16
12
DACC_R8DH
DACC_R8DH
DAC concurrent mode 8-bit right aligned data holding register
0x28
32
read-write
n
0x0
0x0
DAC0_DH
DAC0 8-bit right-aligned data
0
8
DAC1_DH
DAC1 8-bit right-aligned data
8
8
SWT
SWT
software trigger register
0x4
32
write-only
n
0x0
0x0
SWTR0
DAC0 software trigger
0
1
SWTR1
DAC1 software trigger
1
1
DBG
Debug support
DBG
0x0
0x0
0x400
registers
n
CTL
CTL
Control register 0
0x4
32
read-write
n
0x0
0x0
CAN0_HOLD
CAN0 hold bit
14
1
CAN1_HOLD
CAN1 hold bit
21
1
DSLP_HOLD
Deep-sleep mode hold register
1
1
FWDGT_HOLD
FWDGT hold bit
8
1
I2C0_HOLD
I2C0 hold bit
15
1
I2C1_HOLD
I2C1 hold bit
16
1
SLP_HOLD
Sleep mode hold register
0
1
STB_HOLD
Standby mode hold register
2
1
TIMER0_HOLD
TIMER 0 hold bit
10
1
TIMER10_HOLD
TIMER 10 hold bit
30
1
TIMER11_HOLD
TIMER 11 hold bit
25
1
TIMER12_HOLD
TIMER 12 hold bit
26
1
TIMER13_HOLD
TIMER 13 hold bit
27
1
TIMER1_HOLD
TIMER 1 hold bit
11
1
TIMER2_HOLD
TIMER 2 hold bit
12
1
TIMER3_HOLD
TIMER 23 hold bit
13
1
TIMER4_HOLD
TIMER4_HOLD
17
1
TIMER5_HOLD
TIMER 5 hold bit
18
1
TIMER6_HOLD
TIMER 6 hold bit
19
1
TIMER7_HOLD
TIMER 7 hold bit
20
1
TIMER8_HOLD
TIMER 8 hold bit
28
1
TIMER9_HOLD
TIMER 9 hold bit
29
1
TRACE_IOEN
Trace pin allocation enable
5
1
TRACE_MODE
Trace pin allocation mode
6
2
WWDGT_HOLD
WWDGT hold bit
9
1
ID
ID
ID code register
0x0
32
read-only
n
0x0
0x0
ID_CODE
DBG ID code register
0
32
DMA0
DMA controller
DMA
0x0
0x0
0x400
registers
n
DMA0_Channel0
11
DMA0_Channel1
12
DMA0_Channel2
13
DMA0_Channel3
14
DMA0_Channel4
15
DMA0_Channel5
16
DMA0_Channel6
17
CH0CNT
CH0CNT
Channel 0 counter register
0xC
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH0CTL
CH0CTL
Channel 0 control register
0x8
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Enable bit for channel error interrupt
3
1
FTFIE
Enable bit for channel full transfer finish interrupt
1
1
HTFIE
Enable bit for channel half transfer finish interrupt
2
1
M2M
Memory to Memory Mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority level
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH0MADDR
CH0MADDR
Channel 0 memory base address register
0x14
32
read-write
n
0x0
0x0
MADDR
Memory base address
0
32
CH0PADDR
CH0PADDR
Channel 0 peripheral base address register
0x10
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
CH1CNT
CH1CNT
Channel 1 counter register
0x20
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH1CTL
CH1CTL
Channel 1 control register
0x1C
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Enable bit for channel error interrupt
3
1
FTFIE
Enable bit for channel full transfer finish interrupt
1
1
HTFIE
Enable bit for channel half transfer finish interrupt
2
1
M2M
Memory to Memory Mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority level
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH1MADDR
CH1MADDR
Channel 1 memory base address register
0x28
32
read-write
n
0x0
0x0
MADDR
Memory base address
0
32
CH1PADDR
CH1PADDR
Channel 1 peripheral base address register
0x24
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
CH2CNT
CH2CNT
Channel 2 counter register
0x34
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH2CTL
CH2CTL
Channel 2 control register
0x30
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Enable bit for channel error interrupt
3
1
FTFIE
Enable bit for channel full transfer finish interrupt
1
1
HTFIE
Enable bit for channel half transfer finish interrupt
2
1
M2M
Memory to Memory Mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority level
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH2MADDR
CH2MADDR
Channel 2 memory base address register
0x3C
32
read-write
n
0x0
0x0
MADDR
Memory base address
0
32
CH2PADDR
CH2PADDR
Channel 2 peripheral base address register
0x38
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
CH3CNT
CH3CNT
Channel 3 counter register
0x48
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH3CTL
CH3CTL
Channel 3 control register
0x44
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Enable bit for channel error interrupt
3
1
FTFIE
Enable bit for channel full transfer finish interrupt
1
1
HTFIE
Enable bit for channel half transfer finish interrupt
2
1
M2M
Memory to Memory Mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority level
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH3MADDR
CH3MADDR
Channel 3 memory base address register
0x50
32
read-write
n
0x0
0x0
MADDR
Memory base address
0
32
CH3PADDR
CH3PADDR
Channel 3 peripheral base address register
0x4C
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
CH4CNT
CH4CNT
Channel 4 counter register
0x5C
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH4CTL
CH4CTL
Channel 4 control register
0x58
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Enable bit for channel error interrupt
3
1
FTFIE
Enable bit for channel full transfer finish interrupt
1
1
HTFIE
Enable bit for channel half transfer finish interrupt
2
1
M2M
Memory to Memory Mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority level
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH4MADDR
CH4MADDR
Channel 4 memory base address register
0x64
32
read-write
n
0x0
0x0
MADDR
Memory base address
0
32
CH4PADDR
CH4PADDR
Channel 4 peripheral base address register
0x60
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
CH5CNT
CH5CNT
Channel 5 counter register
0x70
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH5CTL
CH5CTL
Channel 5 control register
0x6C
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Enable bit for channel error interrupt
3
1
FTFIE
Enable bit for channel full transfer finish interrupt
1
1
HTFIE
Enable bit for channel half transfer finish interrupt
2
1
M2M
Memory to Memory Mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority level
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH5MADDR
CH5MADDR
Channel 5 memory base address register
0x78
32
read-write
n
0x0
0x0
MADDR
Memory base address
0
32
CH5PADDR
CH5PADDR
Channel 5 peripheral base address register
0x74
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
CH6CNT
CH6CNT
Channel 6 counter register
0x84
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH6CTL
CH6CTL
Channel 6 control register
0x80
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Enable bit for channel error interrupt
3
1
FTFIE
Enable bit for channel full transfer finish interrupt
1
1
HTFIE
Enable bit for channel half transfer finish interrupt
2
1
M2M
Memory to Memory Mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority level
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH6MADDR
CH6MADDR
Channel 6 memory base address register
0x8C
32
read-write
n
0x0
0x0
MADDR
Memory base address
0
32
CH6PADDR
CH6PADDR
Channel 6 peripheral base address register
0x88
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
INTC
INTC
Interrupt flag clear register
0x4
32
write-only
n
0x0
0x0
ERRIFC0
Clear bit for error flag of channel 0
3
1
ERRIFC1
Clear bit for error flag of channel 1
7
1
ERRIFC2
Clear bit for error flag of channel 2
11
1
ERRIFC3
Clear bit for error flag of channel 3
15
1
ERRIFC4
Clear bit for error flag of channel 4
19
1
ERRIFC5
Clear bit for error flag of channel 5
23
1
ERRIFC6
Clear bit for error flag of channel 6
27
1
FTFIFC0
Clear bit for full transfer finish flag of channel 0
1
1
FTFIFC1
Clear bit for full transfer finish flag of channel 1
5
1
FTFIFC2
Clear bit for full transfer finish flag of channel 2
9
1
FTFIFC3
Clear bit for full transfer finish flag of channel 3
13
1
FTFIFC4
Clear bit for full transfer finish flag of channel 4
17
1
FTFIFC5
Clear bit for full transfer finish flag of channel 5
21
1
FTFIFC6
Clear bit for full transfer finish flag of channel 6
25
1
GIFC0
Clear global interrupt flag of channel 0
0
1
GIFC1
Clear global interrupt flag of channel 1
4
1
GIFC2
Clear global interrupt flag of channel 2
8
1
GIFC3
Clear global interrupt flag of channel 3
12
1
GIFC4
Clear global interrupt flag of channel 4
16
1
GIFC5
Clear global interrupt flag of channel 5
20
1
GIFC6
Clear global interrupt flag of channel 6
24
1
HTFIFC0
Clear bit for half transfer finish flag of channel 0
2
1
HTFIFC1
Clear bit for half transfer finish flag of channel 1
6
1
HTFIFC2
Clear bit for half transfer finish flag of channel 2
10
1
HTFIFC3
Clear bit for half transfer finish flag of channel 3
14
1
HTFIFC4
Clear bit for half transfer finish flag of channel 4
18
1
HTFIFC5
Clear bit for half transfer finish flag of channel 5
22
1
HTFIFC6
Clear bit for half transfer finish flag of channel 6
26
1
INTF
INTF
Interrupt flag register
0x0
32
read-only
n
0x0
0x0
ERRIF0
Error flag of channel 0
3
1
ERRIF1
Error flag of channel 1
7
1
ERRIF2
Error flag of channel 2
11
1
ERRIF3
Error flag of channel 3
15
1
ERRIF4
Error flag of channel 4
19
1
ERRIF5
Error flag of channel 5
23
1
ERRIF6
Error flag of channel 6
27
1
FTFIF0
Full Transfer finish flag of channe 0
1
1
FTFIF1
Full Transfer finish flag of channe 1
5
1
FTFIF2
Full Transfer finish flag of channe 2
9
1
FTFIF3
Full Transfer finish flag of channe 3
13
1
FTFIF4
Full Transfer finish flag of channe 4
17
1
FTFIF5
Full Transfer finish flag of channe 5
21
1
FTFIF6
Full Transfer finish flag of channe 6
25
1
GIF0
Global interrupt flag of channel 0
0
1
GIF1
Global interrupt flag of channel 1
4
1
GIF2
Global interrupt flag of channel 2
8
1
GIF3
Global interrupt flag of channel 3
12
1
GIF4
Global interrupt flag of channel 4
16
1
GIF5
Global interrupt flag of channel 5
20
1
GIF6
Global interrupt flag of channel 6
24
1
HTFIF0
Half transfer finish flag of channel 0
2
1
HTFIF1
Half transfer finish flag of channel 1
6
1
HTFIF2
Half transfer finish flag of channel 2
10
1
HTFIF3
Half transfer finish flag of channel 3
14
1
HTFIF4
Half transfer finish flag of channel 4
18
1
HTFIF5
Half transfer finish flag of channel 5
22
1
HTFIF6
Half transfer finish flag of channel 6
26
1
DMA1
Direct memory access controller
DMA
0x0
0x0
0x400
registers
n
DMA1_Channel0
56
DMA1_Channel1
57
DMA1_Channel2
58
DMA1_Channel3_4
59
CH0CNT
CH0CNT
Channel 0 counter register
0xC
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH0CTL
CH0CTL
Channel 0 control register
0x8
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Enable bit for channel error interrupt
3
1
FTFIE
Enable bit for channel full transfer finish interrupt
1
1
HTFIE
Enable bit for channel half transfer finish interrupt
2
1
M2M
Memory to Memory Mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority level
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH0MADDR
CH0MADDR
Channel 0 memory base address register
0x14
32
read-write
n
0x0
0x0
MADDR
Memory base address
0
32
CH0PADDR
CH0PADDR
Channel 0 peripheral base address register
0x10
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
CH1CNT
CH1CNT
Channel 1 counter register
0x20
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH1CTL
CH1CTL
Channel 1 control register
0x1C
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Enable bit for channel error interrupt
3
1
FTFIE
Enable bit for channel full transfer finish interrupt
1
1
HTFIE
Enable bit for channel half transfer finish interrupt
2
1
M2M
Memory to Memory Mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority level
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH1MADDR
CH1MADDR
Channel 1 memory base address register
0x28
32
read-write
n
0x0
0x0
MADDR
Memory base address
0
32
CH1PADDR
CH1PADDR
Channel 1 peripheral base address register
0x24
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
CH2CNT
CH2CNT
Channel 2 counter register
0x34
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH2CTL
CH2CTL
Channel 2 control register
0x30
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Enable bit for channel error interrupt
3
1
FTFIE
Enable bit for channel full transfer finish interrupt
1
1
HTFIE
Enable bit for channel half transfer finish interrupt
2
1
M2M
Memory to Memory Mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority level
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH2MADDR
CH2MADDR
Channel 2 memory base address register
0x3C
32
read-write
n
0x0
0x0
MADDR
Memory base address
0
32
CH2PADDR
CH2PADDR
Channel 2 peripheral base address register
0x38
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
CH3CNT
CH3CNT
Channel 3 counter register
0x48
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH3CTL
CH3CTL
Channel 3 control register
0x44
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Enable bit for channel error interrupt
3
1
FTFIE
Enable bit for channel full transfer finish interrupt
1
1
HTFIE
Enable bit for channel half transfer finish interrupt
2
1
M2M
Memory to Memory Mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority level
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH3MADDR
CH3MADDR
Channel 3 memory base address register
0x50
32
read-write
n
0x0
0x0
MADDR
Memory base address
0
32
CH3PADDR
CH3PADDR
Channel 3 peripheral base address register
0x4C
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
CH4CNT
CH4CNT
Channel 4 counter register
0x5C
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH4CTL
CH4CTL
Channel 4 control register
0x58
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Enable bit for channel error interrupt
3
1
FTFIE
Enable bit for channel full transfer finish interrupt
1
1
HTFIE
Enable bit for channel half transfer finish interrupt
2
1
M2M
Memory to Memory Mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority level
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH4MADDR
CH4MADDR
Channel 4 memory base address register
0x64
32
read-write
n
0x0
0x0
MADDR
Memory base address
0
32
CH4PADDR
CH4PADDR
Channel 4 peripheral base address register
0x60
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
INTC
INTC
Interrupt flag clear register
0x4
32
write-only
n
0x0
0x0
ERRIFC0
Clear bit for error flag of channel 0
3
1
ERRIFC1
Clear bit for error flag of channel 1
7
1
ERRIFC2
Clear bit for error flag of channel 2
11
1
ERRIFC3
Clear bit for error flag of channel 3
15
1
ERRIFC4
Clear bit for error flag of channel 4
19
1
ERRIFC5
Clear bit for error flag of channel 5
23
1
ERRIFC6
Clear bit for error flag of channel 6
27
1
FTFIFC0
Clear bit for full transfer finish flag of channel 0
1
1
FTFIFC1
Clear bit for full transfer finish flag of channel 1
5
1
FTFIFC2
Clear bit for full transfer finish flag of channel 2
9
1
FTFIFC3
Clear bit for full transfer finish flag of channel 3
13
1
FTFIFC4
Clear bit for full transfer finish flag of channel 4
17
1
FTFIFC5
Clear bit for full transfer finish flag of channel 5
21
1
FTFIFC6
Clear bit for full transfer finish flag of channel 6
25
1
GIFC0
Clear global interrupt flag of channel 0
0
1
GIFC1
Clear global interrupt flag of channel 1
4
1
GIFC2
Clear global interrupt flag of channel 2
8
1
GIFC3
Clear global interrupt flag of channel 3
12
1
GIFC4
Clear global interrupt flag of channel 4
16
1
GIFC5
Clear global interrupt flag of channel 5
20
1
GIFC6
Clear global interrupt flag of channel 6
24
1
HTFIFC0
Clear bit for half transfer finish flag of channel 0
2
1
HTFIFC1
Clear bit for half transfer finish flag of channel 1
6
1
HTFIFC2
Clear bit for half transfer finish flag of channel 2
10
1
HTFIFC3
Clear bit for half transfer finish flag of channel 3
14
1
HTFIFC4
Clear bit for half transfer finish flag of channel 4
18
1
HTFIFC5
Clear bit for half transfer finish flag of channel 5
22
1
HTFIFC6
Clear bit for half transfer finish flag of channel 6
26
1
INTF
INTF
Interrupt flag register
0x0
32
read-only
n
0x0
0x0
ERRIF0
Error flag of channel 0
3
1
ERRIF1
Error flag of channel 1
7
1
ERRIF2
Error flag of channel 2
11
1
ERRIF3
Error flag of channel 3
15
1
ERRIF4
Error flag of channel 4
19
1
ERRIF5
Error flag of channel 5
23
1
ERRIF6
Error flag of channel 6
27
1
FTFIF0
Full Transfer finish flag of channe 0
1
1
FTFIF1
Full Transfer finish flag of channe 1
5
1
FTFIF2
Full Transfer finish flag of channe 2
9
1
FTFIF3
Full Transfer finish flag of channe 3
13
1
FTFIF4
Full Transfer finish flag of channe 4
17
1
FTFIF5
Full Transfer finish flag of channe 5
21
1
FTFIF6
Full Transfer finish flag of channe 6
25
1
GIF0
Global interrupt flag of channel 0
0
1
GIF1
Global interrupt flag of channel 1
4
1
GIF2
Global interrupt flag of channel 2
8
1
GIF3
Global interrupt flag of channel 3
12
1
GIF4
Global interrupt flag of channel 4
16
1
GIF5
Global interrupt flag of channel 5
20
1
GIF6
Global interrupt flag of channel 6
24
1
HTFIF0
Half transfer finish flag of channel 0
2
1
HTFIF1
Half transfer finish flag of channel 1
6
1
HTFIF2
Half transfer finish flag of channel 2
10
1
HTFIF3
Half transfer finish flag of channel 3
14
1
HTFIF4
Half transfer finish flag of channel 4
18
1
HTFIF5
Half transfer finish flag of channel 5
22
1
HTFIF6
Half transfer finish flag of channel 6
26
1
EXMC
External memory controller
EXMC
0x0
0x0
0x1000
registers
n
EXMC
48
NECC1
NECC1
NAND flash ECC register 1
0x74
32
read-write
n
0x0
0x0
ECC
ECC result
0
32
read-only
NECC2
NECC2
NAND flash ECC register 2
0x94
32
read-write
n
0x0
0x0
ECC
ECC result
0
32
read-only
NPATCFG1
NPATCFG1
NAND flash/PC card attribute space timing configuration register 1
0x6C
32
read-write
n
0x0
0x0
ATTHIZ
Attribute memory data bus HiZ time
24
8
ATTHLD
Attribute memory hold time
16
8
ATTSET
Attribute memory setup time
0
8
ATTWAIT
Attribute memory wait time
8
8
NPATCFG2
NPATCFG2
NAND flash/PC card attribute space timing configuration register 2
0x8C
32
read-write
n
0x0
0x0
ATTHIZ
Attribute memory data bus HiZ time
24
8
ATTHLD
Attribute memory hold time
16
8
ATTSET
Attribute memory setup time
0
8
ATTWAIT
Attribute memory wait time
8
8
NPATCFG3
NPATCFG3
NAND flash/PC card attribute space timing configuration register 3
0xAC
32
read-write
n
0x0
0x0
ATTHIZ
Attribute memory data bus HiZ time
24
8
ATTHLD
Attribute memory hold time
16
8
ATTSET
Attribute memory setup time
0
8
ATTWAIT
Attribute memory wait time
8
8
NPCTCFG1
NPCTCFG1
NAND flash/PC card common space timing configuration register 1
0x68
32
read-write
n
0x0
0x0
COMHIZ
Common memory data bus HiZ time
24
8
COMHLD
Common memory hold time
16
8
COMSET
Common memory setup time
0
8
COMWAIT
Common memory wait time
8
8
NPCTCFG2
NPCTCFG2
NAND flash/PC card common space timing configuration register 2
0x88
32
read-write
n
0x0
0x0
COMHIZ
Common memory data bus HiZ time
24
8
COMHLD
Common memory hold time
16
8
COMSET
Common memory setup time
0
8
COMWAIT
Common memory wait time
8
8
NPCTCFG3
NPCTCFG3
NAND flash/PC card common space timing configuration register 3
0xA8
32
read-write
n
0x0
0x0
COMHIZ
Common memory data bus HiZ time
24
8
COMHLD
Common memory hold time
16
8
COMSET
Common memory setup time
0
8
COMWAIT
Common memory wait time
8
8
NPCTL1
NPCTL1
NAND flash/PC card control register 1
0x60
32
read-write
n
0x0
0x0
ATR
ALE to RE delay
13
4
CTR
CLE to RE delay
9
4
ECCEN
ECC enable
6
1
ECCSZ
ECC size
17
3
NDBKEN
NAND bank enable
2
1
NDTP
NAND bank memory type
3
1
NDW
NAND bank memory data bus width
4
2
NDWTEN
Wait feature enable
1
1
NPCTL2
NPCTL2
NAND flash/PC card control register 2
0x80
32
read-write
n
0x0
0x0
ATR
ALE to RE delay
13
4
CTR
CLE to RE delay
9
4
ECCEN
ECC enable
6
1
ECCSZ
ECC size
17
3
NDBKEN
NAND bank enable
2
1
NDTP
NAND bank memory type
3
1
NDW
NAND bank memory data bus width
4
2
NDWTEN
Wait feature enable
1
1
NPCTL3
NPCTL3
NAND flash/PC card control register 3
0xA0
32
read-write
n
0x0
0x0
ATR
ALE to RE delay
13
4
CTR
CLE to RE delay
9
4
ECCEN
ECC enable
6
1
ECCSZ
ECC size
17
3
NDBKEN
NAND bank enable
2
1
NDTP
NAND bank memory type
3
1
NDW
NAND bank memory data bus width
4
2
NDWTEN
Wait feature enable
1
1
NPINTEN1
NPINTEN1
NAND flash/PC card interrupt enable register 1
0x64
32
read-write
n
0x0
0x0
FFEPT
FIFO empty flag
6
1
INTFEN
Interrupt falling edge detection enable
5
1
INTFS
Interrupt falling edge status
2
1
INTHEN
Interrupt high-level detection enable
4
1
INTHS
Interrupt high-level status
1
1
INTREN
Interrupt rising edge detection enable bit
3
1
INTRS
Interrupt rising edge status
0
1
NPINTEN2
NPINTEN2
NAND flash/PC card interrupt enable register 2
0x84
32
read-write
n
0x0
0x0
FFEPT
FIFO empty flag
6
1
INTFEN
Interrupt falling edge detection enable
5
1
INTFS
Interrupt falling edge status
2
1
INTHEN
Interrupt high-level detection enable
4
1
INTHS
Interrupt high-level status
1
1
INTREN
Interrupt rising edge detection enable bit
3
1
INTRS
Interrupt rising edge status
0
1
NPINTEN3
NPINTEN3
NAND flash/PC card interrupt enable register 3
0xA4
32
read-write
n
0x0
0x0
FFEPT
FIFO empty flag
6
1
INTFEN
Interrupt falling edge detection enable
5
1
INTFS
Interrupt falling edge status
2
1
INTHEN
Interrupt high-level detection enable
4
1
INTHS
Interrupt high-level status
1
1
INTREN
Interrupt rising edge detection enable bit
3
1
INTRS
Interrupt rising edge status
0
1
PIOTCFG3
PIOTCFG3
PC card I/O space timing configuration register
0xB0
32
read-write
n
0x0
0x0
IOHIZ
IO space data bus HiZ time
24
8
IOHLD
IO space hold time
16
8
IOSET
IO space setup time
0
8
IOWAIT
IO space wait time
8
8
SNCTL0
SNCTL0
SRAM/NOR flash control register 0
0x0
32
read-write
n
0x0
0x0
ASYNCWAIT
Asynchronous wait
15
1
EXMODEN
Extended mode enable
14
1
NRBKEN
NOR bank enable
0
1
NREN
NOR Flash access enable
6
1
NRMUX
NOR bank memory address/data multiplexing
1
1
NRTP
NOR bank memory type
2
2
NRW
NOR bank memory data bus width
4
2
NRWTCFG
NWAIT signal configuration, only work in synchronous mode
11
1
NRWTEN
NWAIT signal enable
13
1
NRWTPOL
NWAIT signal polarity
9
1
SBRSTEN
Synchronous burst enable
8
1
SYNCWR
Synchronous write
19
1
WRAPEN
Wrapped burst mode enable
10
1
WREN
Write enable
12
1
SNCTL1
SNCTL1
SRAM/NOR flash control register 1
0x8
32
read-write
n
0x0
0x0
ASYNCWAIT
Asynchronous wait
15
1
CPS
CRAM page size
16
3
EXMODEN
Extended mode enable
14
1
NRBKEN
NOR bank enable
0
1
NREN
NOR Flash access enable
6
1
NRMUX
NOR bank memory address/data multiplexing
1
1
NRTP
NOR bank memory type
2
2
NRW
NOR bank memory data bus width
4
2
NRWTCFG
NWAIT signal configuration, only work in synchronous mode
11
1
NRWTEN
NWAIT signal enable
13
1
NRWTPOL
NWAIT signal polarity
9
1
SBRSTEN
Synchronous burst enable
8
1
SYNCWR
Synchronous write
19
1
WRAPEN
Wrapped burst mode enable
10
1
WREN
Write enable
12
1
SNCTL2
SNCTL2
SRAM/NOR flash control register 2
0x10
32
read-write
n
0x0
0x0
ASYNCWAIT
Asynchronous wait
15
1
CPS
CRAM page size
16
3
EXMODEN
Extended mode enable
14
1
NRBKEN
NOR bank enable
0
1
NREN
NOR Flash access enable
6
1
NRMUX
NOR bank memory address/data multiplexing
1
1
NRTP
NOR bank memory type
2
2
NRW
NOR bank memory data bus width
4
2
NRWTCFG
NWAIT signal configuration, only work in synchronous mode
11
1
NRWTEN
NWAIT signal enable
13
1
NRWTPOL
NWAIT signal polarity
9
1
SBRSTEN
Synchronous burst enable
8
1
SYNCWR
Synchronous write
19
1
WRAPEN
Wrapped burst mode enable
10
1
WREN
Write enable
12
1
SNCTL3
SNCTL3
SRAM/NOR flash control register 3
0x18
32
read-write
n
0x0
0x0
ASYNCWAIT
Asynchronous wait
15
1
CPS
CRAM page size
16
3
EXMODEN
Extended mode enable
14
1
NRBKEN
NOR bank enable
0
1
NREN
NOR Flash access enable
6
1
NRMUX
NOR bank memory address/data multiplexing
1
1
NRTP
NOR bank memory type
2
2
NRW
NOR bank memory data bus width
4
2
NRWTCFG
NWAIT signal configuration, only work in synchronous mode
11
1
NRWTEN
NWAIT signal enable
13
1
NRWTPOL
NWAIT signal polarity
9
1
SBRSTEN
Synchronous burst enable
8
1
SYNCWR
Synchronous write
19
1
WRAPEN
Wrapped burst mode enable
10
1
WREN
Write enable
12
1
SNTCFG0
SNTCFG0
SRAM/NOR flash timing configuration register 0
0x4
32
read-write
n
0x0
0x0
AHLD
Address hold time
4
4
ASET
Address setup time
0
4
ASYNCMOD
Asynchronous access mode
28
2
BUSLAT
Bus latency
16
4
CKDIV
Synchronous clock divide ratio
20
4
DLAT
Data latency for NOR Flash
24
4
DSET
Data setup time
8
8
SNTCFG1
SNTCFG1
SRAM/NOR flash timing configuration register 1
0xC
32
read-write
n
0x0
0x0
AHLD
Address hold time
4
4
ASET
Address setup time
0
4
ASYNCMOD
Asynchronous access mode
28
2
BUSLAT
Bus latency
16
4
CKDIV
Synchronous clock divide ratio
20
4
DLAT
Data latency for NOR Flash
24
4
DSET
Data setup time
8
8
SNTCFG2
SNTCFG2
SRAM/NOR flash timing configuration register 2
0x14
32
read-write
n
0x0
0x0
AHLD
Address hold time
4
4
ASET
Address setup time
0
4
ASYNCMOD
Asynchronous access mode
28
2
BUSLAT
Bus latency
16
4
CKDIV
Synchronous clock divide ratio
20
4
DLAT
Data latency for NOR Flash
24
4
DSET
Data setup time
8
8
SNTCFG3
SNTCFG3
SRAM/NOR flash timing configuration register 3
0x1C
32
read-write
n
0x0
0x0
AHLD
Address hold time
4
4
ASET
Address setup time
0
4
ASYNCMOD
Asynchronous access mode
28
2
BUSLAT
Bus latency
16
4
CKDIV
Synchronous clock divide ratio
20
4
DLAT
Data latency for NOR Flash
24
4
DSET
Data setup time
8
8
SNWTCFG0
SNWTCFG0
SRAM/NOR flash write timing configuration register 0
0x104
32
read-write
n
0x0
0x0
CKDIV
Synchronous clock divide ratio
20
4
DLAT
Data latency for NOR flash
24
4
WAHLD
Address hold time
4
4
WASET
Address setup time
0
4
WASYNCMOD
Asynchronous access mode
28
2
WDSET
Data setup time
8
8
SNWTCFG1
SNWTCFG1
SRAM/NOR flash write timing configuration register 1
0x10C
32
read-write
n
0x0
0x0
CKDIV
Synchronous clock divide ratio
20
4
DLAT
Data latency for NOR flash
24
4
WAHLD
Address hold time
4
4
WASET
Address setup time
0
4
WASYNCMOD
Asynchronous access mode
28
2
WDSET
Data setup time
8
8
SNWTCFG2
SNWTCFG2
SRAM/NOR flash write timing configuration register 2
0x114
32
read-write
n
0x0
0x0
CKDIV
Synchronous clock divide ratio
20
4
DLAT
Data latency for NOR flash
24
4
WAHLD
Address hold time
4
4
WASET
Address setup time
0
4
WASYNCMOD
Asynchronous access mode
28
2
WDSET
Data setup time
8
8
SNWTCFG3
SNWTCFG3
SRAM/NOR flash write timing configuration register 3
0x11C
32
read-write
n
0x0
0x0
CKDIV
Synchronous clock divide ratio
20
4
DLAT
Data latency for NOR flash
24
4
WAHLD
Address hold time
4
4
WASET
Address setup time
0
4
WASYNCMOD
Asynchronous access mode
28
2
WDSET
Data setup time
8
8
EXTI
External interrupt/event controller
EXTI
0x0
0x0
0x400
registers
n
EXTI_Line0
6
EXTI_Line1
7
EXTI_Line2
8
EXTI_Line3
9
EXTI_Line4
10
EXTI_line9_5
23
EXTI_line15_10
40
EVEN
EVEN
Event enable register (EXTI_EVEN)
0x4
32
read-write
n
0x0
0x0
EVEN0
Enable Event on line 0
0
1
EVEN1
Enable Event on line 1
1
1
EVEN10
Enable Event on line 10
10
1
EVEN11
Enable Event on line 11
11
1
EVEN12
Enable Event on line 12
12
1
EVEN13
Enable Event on line 13
13
1
EVEN14
Enable Event on line 14
14
1
EVEN15
Enable Event on line 15
15
1
EVEN16
Enable Event on line 16
16
1
EVEN17
Enable Event on line 17
17
1
EVEN18
Enable Event on line 18
18
1
EVEN19
Enable Event on line 19
19
1
EVEN2
Enable Event on line 2
2
1
EVEN3
Enable Event on line 3
3
1
EVEN4
Enable Event on line 4
4
1
EVEN5
Enable Event on line 5
5
1
EVEN6
Enable Event on line 6
6
1
EVEN7
Enable Event on line 7
7
1
EVEN8
Enable Event on line 8
8
1
EVEN9
Enable Event on line 9
9
1
FTEN
FTEN
Falling Egde Trigger Enable register (EXTI_FTEN)
0xC
32
read-write
n
0x0
0x0
FTEN0
Falling edge trigger enable of line 0
0
1
FTEN1
Falling edge trigger enable of line 1
1
1
FTEN10
Falling edge trigger enable of line 10
10
1
FTEN11
Falling edge trigger enable of line 11
11
1
FTEN12
Falling edge trigger enable of line 12
12
1
FTEN13
Falling edge trigger enable of line 13
13
1
FTEN14
Falling edge trigger enable of line 14
14
1
FTEN15
Falling edge trigger enable of line 15
15
1
FTEN16
Falling edge trigger enable of line 16
16
1
FTEN17
Falling edge trigger enable of line 17
17
1
FTEN18
Falling edge trigger enable of line 18
18
1
FTEN19
Falling edge trigger enable of line 19
19
1
FTEN2
Falling edge trigger enable of line 2
2
1
FTEN3
Falling edge trigger enable of line 3
3
1
FTEN4
Falling edge trigger enable of line 4
4
1
FTEN5
Falling edge trigger enable of line 5
5
1
FTEN6
Falling edge trigger enable of line 6
6
1
FTEN7
Falling edge trigger enable of line 7
7
1
FTEN8
Falling edge trigger enable of line 8
8
1
FTEN9
Falling edge trigger enable of line 9
9
1
INTEN
INTEN
Interrupt enable register (EXTI_INTEN)
0x0
32
read-write
n
0x0
0x0
INTEN0
Enable Interrupt on line 0
0
1
INTEN1
Enable Interrupt on line 1
1
1
INTEN10
Enable Interrupt on line 10
10
1
INTEN11
Enable Interrupt on line 11
11
1
INTEN12
Enable Interrupt on line 12
12
1
INTEN13
Enable Interrupt on line 13
13
1
INTEN14
Enable Interrupt on line 14
14
1
INTEN15
Enable Interrupt on line 15
15
1
INTEN16
Enable Interrupt on line 16
16
1
INTEN17
Enable Interrupt on line 17
17
1
INTEN18
Enable Interrupt on line 18
18
1
INTEN19
Enable Interrupt on line 19
19
1
INTEN2
Enable Interrupt on line 2
2
1
INTEN3
Enable Interrupt on line 3
3
1
INTEN4
Enable Interrupt on line 4
4
1
INTEN5
Enable Interrupt on line 5
5
1
INTEN6
Enable Interrupt on line 6
6
1
INTEN7
Enable Interrupt on line 7
7
1
INTEN8
Enable Interrupt on line 8
8
1
INTEN9
Enable Interrupt on line 9
9
1
PD
PD
Pending register (EXTI_PD)
0x14
32
read-write
n
0x0
0x0
PD0
Interrupt pending status of line 0
0
1
PD1
Interrupt pending status of line 1
1
1
PD10
Interrupt pending status of line 10
10
1
PD11
Interrupt pending status of line 11
11
1
PD12
Interrupt pending status of line 12
12
1
PD13
Interrupt pending status of line 13
13
1
PD14
Interrupt pending status of line 14
14
1
PD15
Interrupt pending status of line 15
15
1
PD16
Interrupt pending status of line 16
16
1
PD17
Interrupt pending status of line 17
17
1
PD18
Interrupt pending status of line 18
18
1
PD19
Interrupt pending status of line 19
19
1
PD2
Interrupt pending status of line 2
2
1
PD3
Interrupt pending status of line 3
3
1
PD4
Interrupt pending status of line 4
4
1
PD5
Interrupt pending status of line 5
5
1
PD6
Interrupt pending status of line 6
6
1
PD7
Interrupt pending status of line 7
7
1
PD8
Interrupt pending status of line 8
8
1
PD9
Interrupt pending status of line 9
9
1
RTEN
RTEN
Rising Edge Trigger Enable register (EXTI_RTEN)
0x8
32
read-write
n
0x0
0x0
RTEN0
Rising edge trigger enable of line 0
0
1
RTEN1
Rising edge trigger enable of line 1
1
1
RTEN10
Rising edge trigger enable of line 10
10
1
RTEN11
Rising edge trigger enable of line 11
11
1
RTEN12
Rising edge trigger enable of line 12
12
1
RTEN13
Rising edge trigger enable of line 13
13
1
RTEN14
Rising edge trigger enable of line 14
14
1
RTEN15
Rising edge trigger enable of line 15
15
1
RTEN16
Rising edge trigger enable of line 16
16
1
RTEN17
Rising edge trigger enable of line 17
17
1
RTEN18
Rising edge trigger enable of line 18
18
1
RTEN19
Rising edge trigger enable of line 19
19
1
RTEN2
Rising edge trigger enable of line 2
2
1
RTEN3
Rising edge trigger enable of line 3
3
1
RTEN4
Rising edge trigger enable of line 4
4
1
RTEN5
Rising edge trigger enable of line 5
5
1
RTEN6
Rising edge trigger enable of line 6
6
1
RTEN7
Rising edge trigger enable of line 7
7
1
RTEN8
Rising edge trigger enable of line 8
8
1
RTEN9
Rising edge trigger enable of line 9
9
1
SWIEV
SWIEV
Software interrupt event register (EXTI_SWIEV)
0x10
32
read-write
n
0x0
0x0
SWIEV0
Interrupt/Event software trigger on line 0
0
1
SWIEV1
Interrupt/Event software trigger on line 1
1
1
SWIEV10
Interrupt/Event software trigger on line 10
10
1
SWIEV11
Interrupt/Event software trigger on line 11
11
1
SWIEV12
Interrupt/Event software trigger on line 12
12
1
SWIEV13
Interrupt/Event software trigger on line 13
13
1
SWIEV14
Interrupt/Event software trigger on line 14
14
1
SWIEV15
Interrupt/Event software trigger on line 15
15
1
SWIEV16
Interrupt/Event software trigger on line 16
16
1
SWIEV17
Interrupt/Event software trigger on line 17
17
1
SWIEV18
Interrupt/Event software trigger on line 18
18
1
SWIEV19
Interrupt/Event software trigger on line 19
19
1
SWIEV2
Interrupt/Event software trigger on line 2
2
1
SWIEV3
Interrupt/Event software trigger on line 3
3
1
SWIEV4
Interrupt/Event software trigger on line 4
4
1
SWIEV5
Interrupt/Event software trigger on line 5
5
1
SWIEV6
Interrupt/Event software trigger on line 6
6
1
SWIEV7
Interrupt/Event software trigger on line 7
7
1
SWIEV8
Interrupt/Event software trigger on line 8
8
1
SWIEV9
Interrupt/Event software trigger on line 9
9
1
FMC
FMC
FMC
0x0
0x0
0x400
registers
n
FMC
4
ADDR0
ADDR0
Address register 0
0x14
32
write-only
n
0x0
0x0
ADDR
Flash erase/program command address bits
0
32
ADDR1
ADDR1
Address register 1
0x54
32
write-only
n
0x0
0x0
ADDR
Flash erase/program command address bits
0
32
CTL0
CTL0
Control register 0
0x10
32
read-write
n
0x0
0x0
ENDIE
End of operation interrupt enable bit
12
1
ERRIE
Error interrupt enable bit
10
1
LK
FMC_CTL0 lock bit
7
1
MER
Main flash mass erase for bank0 command bit
2
1
OBER
Option bytes erase command bit
5
1
OBPG
Option bytes program command bit
4
1
OBWEN
Option byte erase/program enable bit
9
1
PER
Main flash page erase for bank0 command bit
1
1
PG
Main flash program for bank0 command bit
0
1
START
Send erase command to FMC bit
6
1
CTL1
CTL1
Control register 1
0x50
32
read-write
n
0x0
0x0
ENDIE
End of operation interrupt enable bit
12
1
ERRIE
Error interrupt enable bit
10
1
LK
FMC_CTL1 lock bit
7
1
MER
Main flash mass erase for bank1 command bit
2
1
PER
Main flash page erase for bank1 command bit
1
1
PG
Main flash program for bank1 command bit
0
1
START
Send erase command to FMC bit
6
1
KEY0
KEY0
Unlock key register 0
0x4
32
write-only
n
0x0
0x0
KEY
FMC_CTL0 unlock key
0
32
KEY1
KEY1
Unlock key register 1
0x44
32
write-only
n
0x0
0x0
KEY
FMC_CTL1 unlock register
0
32
OBKEY
OBKEY
Option byte unlock key register
0x8
32
write-only
n
0x0
0x0
OBKEY
FMC_ CTL0 option byte operation unlock register
0
32
OBSTAT
OBSTAT
Option byte status register
0x1C
32
read-only
n
0x0
0x0
DATA
Store DATA[15:0] of option bytes block after system reset
10
16
OBERR
Option bytes read error bit
0
1
SPC
Option bytes security protection code
1
1
USER
Store USER of option bytes block after system reset
2
8
PID
PID
Product ID register
0x100
32
read-only
n
0x0
0x0
PID
Product reserved ID code register
0
32
STAT0
STAT0
Status register 0
0xC
32
read-write
n
0x0
0x0
BUSY
The flash is busy bit
0
1
read-only
ENDF
End of operation flag bit
5
1
read-write
PGERR
Program error flag bit
2
1
read-write
WPERR
Erase/Program protection error flag bit
4
1
read-write
STAT1
STAT1
Status register 1
0x4C
32
read-write
n
0x0
0x0
BUSY
The flash is busy bit
0
1
read-only
ENDF
End of operation flag bit
5
1
read-write
PGERR
Program error flag bit
2
1
read-write
WPERR
Erase/Program protection error flag bit
4
1
read-write
WP
WP
Erase/Program Protection register
0x20
32
read-only
n
0x0
0x0
WP
Store WP[31:0] of option bytes block after system reset
0
32
WS
WS
wait state counter register
0x0
32
read-write
n
0x0
0x0
WSCNT
wait state counter register
0
3
WSEN
WSEN
Wait state enable register
0xFC
32
read-write
n
0x0
0x0
WSEN
FMC wait state enable register
0
1
FWDGT
free watchdog timer
FWDGT
0x0
0x0
0x400
registers
n
CTL
CTL
Control register
0x0
32
write-only
n
0x0
0x0
CMD
Key value
0
16
PSC
PSC
Prescaler register
0x4
32
read-write
n
0x0
0x0
PSC
Free watchdog timer prescaler selection
0
3
RLD
RLD
Reload register
0x8
32
read-write
n
0x0
0x0
RLD
Free watchdog timer counter reload value
0
12
STAT
STAT
Status register
0xC
32
read-only
n
0x0
0x0
PUD
Free watchdog timer prescaler value update
0
1
RUD
Free watchdog timer counter reload value update
1
1
GPIOA
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
BC
BC
Port bit clear register
0x14
32
write-only
n
0x0
0x0
CR0
Port 0 Clear bit
0
1
CR1
Port 1 Clear bit
1
1
CR10
Port 10 Clear bit
10
1
CR11
Port 11 Clear bit
11
1
CR12
Port 12 Clear bit
12
1
CR13
Port 13 Clear bit
13
1
CR14
Port 14 Clear bit
14
1
CR15
Port 15 Clear bit
15
1
CR2
Port 2 Clear bit
2
1
CR3
Port 3 Clear bit
3
1
CR4
Port 4 Clear bit
4
1
CR5
Port 5 Clear bit
5
1
CR6
Port 6 Clear bit
6
1
CR7
Port 7 Clear bit
7
1
CR8
Port 8 Clear bit
8
1
CR9
Port 9 Clear bit
9
1
BOP
BOP
Port bit operate register
0x10
32
write-only
n
0x0
0x0
BOP0
Port 0 Set bit
0
1
BOP1
Port 1 Set bit
1
1
BOP10
Port 10 Set bit
10
1
BOP11
Port 11 Set bit
11
1
BOP12
Port 12 Set bit
12
1
BOP13
Port 13 Set bit
13
1
BOP14
Port 14 Set bit
14
1
BOP15
Port 15 Set bit
15
1
BOP2
Port 2 Set bit
2
1
BOP3
Port 3 Set bit
3
1
BOP4
Port 4 Set bit
4
1
BOP5
Port 5 Set bit
5
1
BOP6
Port 6 Set bit
6
1
BOP7
Port 7 Set bit
7
1
BOP8
Port 8 Set bit
8
1
BOP9
Port 9 Set bit
9
1
CR0
Port 0 Clear bit
16
1
CR1
Port 1 Clear bit
17
1
CR10
Port 10 Clear bit
26
1
CR11
Port 11 Clear bit
27
1
CR12
Port 12 Clear bit
28
1
CR13
Port 13 Clear bit
29
1
CR14
Port 14 Clear bit
30
1
CR15
Port 15 Clear bit
31
1
CR2
Port 2 Clear bit
18
1
CR3
Port 3 Clear bit
19
1
CR4
Port 4 Clear bit
20
1
CR5
Port 5 Clear bit
21
1
CR6
Port 6 Clear bit
22
1
CR7
Port 7 Clear bit
23
1
CR8
Port 8 Clear bit
24
1
CR9
Port 9 Clear bit
25
1
CTL0
CTL0
port control register 0
0x0
32
read-write
n
0x0
0x0
CTL0
Port x configuration bits (x = 0)
2
2
CTL1
Port x configuration bits (x = 1)
6
2
CTL2
Port x configuration bits (x = 2)
10
2
CTL3
Port x configuration bits (x = 3)
14
2
CTL4
Port x configuration bits (x = 4)
18
2
CTL5
Port x configuration bits (x = 5)
22
2
CTL6
Port x configuration bits (x = 6)
26
2
CTL7
Port x configuration bits (x = 7)
30
2
MD0
Port x mode bits (x = 0)
0
2
MD1
Port x mode bits (x = 1)
4
2
MD2
Port x mode bits (x = 2 )
8
2
MD3
Port x mode bits (x = 3 )
12
2
MD4
Port x mode bits (x = 4)
16
2
MD5
Port x mode bits (x = 5)
20
2
MD6
Port x mode bits (x = 6)
24
2
MD7
Port x mode bits (x = 7)
28
2
CTL1
CTL1
port control register 1
0x4
32
read-write
n
0x0
0x0
CTL10
Port x configuration bits (x = 10)
10
2
CTL11
Port x configuration bits (x = 11)
14
2
CTL12
Port x configuration bits (x = 12)
18
2
CTL13
Port x configuration bits (x = 13)
22
2
CTL14
Port x configuration bits (x = 14)
26
2
CTL15
Port x configuration bits (x = 15)
30
2
CTL8
Port x configuration bits (x = 8)
2
2
CTL9
Port x configuration bits (x = 9)
6
2
MD10
Port x mode bits (x = 10 )
8
2
MD11
Port x mode bits (x = 11 )
12
2
MD12
Port x mode bits (x = 12)
16
2
MD13
Port x mode bits (x = 13)
20
2
MD14
Port x mode bits (x = 14)
24
2
MD15
Port x mode bits (x = 15)
28
2
MD8
Port x mode bits (x = 8)
0
2
MD9
Port x mode bits (x = 9)
4
2
ISTAT
ISTAT
Port input status register
0x8
32
read-only
n
0x0
0x0
ISTAT0
Port input status
0
1
ISTAT1
Port input status
1
1
ISTAT10
Port input status
10
1
ISTAT11
Port input status
11
1
ISTAT12
Port input status
12
1
ISTAT13
Port input status
13
1
ISTAT14
Port input status
14
1
ISTAT15
Port input status
15
1
ISTAT2
Port input status
2
1
ISTAT3
Port input status
3
1
ISTAT4
Port input status
4
1
ISTAT5
Port input status
5
1
ISTAT6
Port input status
6
1
ISTAT7
Port input status
7
1
ISTAT8
Port input status
8
1
ISTAT9
Port input status
9
1
LOCK
LOCK
GPIO port configuration lock register
0x18
32
read-write
n
0x0
0x0
LK0
Port Lock bit 0
0
1
LK1
Port Lock bit 1
1
1
LK10
Port Lock bit 10
10
1
LK11
Port Lock bit 11
11
1
LK12
Port Lock bit 12
12
1
LK13
Port Lock bit 13
13
1
LK14
Port Lock bit 14
14
1
LK15
Port Lock bit 15
15
1
LK2
Port Lock bit 2
2
1
LK3
Port Lock bit 3
3
1
LK4
Port Lock bit 4
4
1
LK5
Port Lock bit 5
5
1
LK6
Port Lock bit 6
6
1
LK7
Port Lock bit 7
7
1
LK8
Port Lock bit 8
8
1
LK9
Port Lock bit 9
9
1
LKK
Lock sequence key
16
1
OCTL
OCTL
Port output control register
0xC
32
read-write
n
0x0
0x0
OCTL0
Port output control
0
1
OCTL1
Port output control
1
1
OCTL10
Port output control
10
1
OCTL11
Port output control
11
1
OCTL12
Port output control
12
1
OCTL13
Port output control
13
1
OCTL14
Port output control
14
1
OCTL15
Port output control
15
1
OCTL2
Port output control
2
1
OCTL3
Port output control
3
1
OCTL4
Port output control
4
1
OCTL5
Port output control
5
1
OCTL6
Port output control
6
1
OCTL7
Port output control
7
1
OCTL8
Port output control
8
1
OCTL9
Port output control
9
1
GPIOB
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
BC
BC
Port bit clear register
0x14
32
write-only
n
0x0
0x0
CR0
Port 0 Clear bit
0
1
CR1
Port 1 Clear bit
1
1
CR10
Port 10 Clear bit
10
1
CR11
Port 11 Clear bit
11
1
CR12
Port 12 Clear bit
12
1
CR13
Port 13 Clear bit
13
1
CR14
Port 14 Clear bit
14
1
CR15
Port 15 Clear bit
15
1
CR2
Port 2 Clear bit
2
1
CR3
Port 3 Clear bit
3
1
CR4
Port 4 Clear bit
4
1
CR5
Port 5 Clear bit
5
1
CR6
Port 6 Clear bit
6
1
CR7
Port 7 Clear bit
7
1
CR8
Port 8 Clear bit
8
1
CR9
Port 9 Clear bit
9
1
BOP
BOP
Port bit operate register
0x10
32
write-only
n
0x0
0x0
BOP0
Port 0 Set bit
0
1
BOP1
Port 1 Set bit
1
1
BOP10
Port 10 Set bit
10
1
BOP11
Port 11 Set bit
11
1
BOP12
Port 12 Set bit
12
1
BOP13
Port 13 Set bit
13
1
BOP14
Port 14 Set bit
14
1
BOP15
Port 15 Set bit
15
1
BOP2
Port 2 Set bit
2
1
BOP3
Port 3 Set bit
3
1
BOP4
Port 4 Set bit
4
1
BOP5
Port 5 Set bit
5
1
BOP6
Port 6 Set bit
6
1
BOP7
Port 7 Set bit
7
1
BOP8
Port 8 Set bit
8
1
BOP9
Port 9 Set bit
9
1
CR0
Port 0 Clear bit
16
1
CR1
Port 1 Clear bit
17
1
CR10
Port 10 Clear bit
26
1
CR11
Port 11 Clear bit
27
1
CR12
Port 12 Clear bit
28
1
CR13
Port 13 Clear bit
29
1
CR14
Port 14 Clear bit
30
1
CR15
Port 15 Clear bit
31
1
CR2
Port 2 Clear bit
18
1
CR3
Port 3 Clear bit
19
1
CR4
Port 4 Clear bit
20
1
CR5
Port 5 Clear bit
21
1
CR6
Port 6 Clear bit
22
1
CR7
Port 7 Clear bit
23
1
CR8
Port 8 Clear bit
24
1
CR9
Port 9 Clear bit
25
1
CTL0
CTL0
port control register 0
0x0
32
read-write
n
0x0
0x0
CTL0
Port x configuration bits (x = 0)
2
2
CTL1
Port x configuration bits (x = 1)
6
2
CTL2
Port x configuration bits (x = 2)
10
2
CTL3
Port x configuration bits (x = 3)
14
2
CTL4
Port x configuration bits (x = 4)
18
2
CTL5
Port x configuration bits (x = 5)
22
2
CTL6
Port x configuration bits (x = 6)
26
2
CTL7
Port x configuration bits (x = 7)
30
2
MD0
Port x mode bits (x = 0)
0
2
MD1
Port x mode bits (x = 1)
4
2
MD2
Port x mode bits (x = 2 )
8
2
MD3
Port x mode bits (x = 3 )
12
2
MD4
Port x mode bits (x = 4)
16
2
MD5
Port x mode bits (x = 5)
20
2
MD6
Port x mode bits (x = 6)
24
2
MD7
Port x mode bits (x = 7)
28
2
CTL1
CTL1
port control register 1
0x4
32
read-write
n
0x0
0x0
CTL10
Port x configuration bits (x = 10)
10
2
CTL11
Port x configuration bits (x = 11)
14
2
CTL12
Port x configuration bits (x = 12)
18
2
CTL13
Port x configuration bits (x = 13)
22
2
CTL14
Port x configuration bits (x = 14)
26
2
CTL15
Port x configuration bits (x = 15)
30
2
CTL8
Port x configuration bits (x = 8)
2
2
CTL9
Port x configuration bits (x = 9)
6
2
MD10
Port x mode bits (x = 10 )
8
2
MD11
Port x mode bits (x = 11 )
12
2
MD12
Port x mode bits (x = 12)
16
2
MD13
Port x mode bits (x = 13)
20
2
MD14
Port x mode bits (x = 14)
24
2
MD15
Port x mode bits (x = 15)
28
2
MD8
Port x mode bits (x = 8)
0
2
MD9
Port x mode bits (x = 9)
4
2
ISTAT
ISTAT
Port input status register
0x8
32
read-only
n
0x0
0x0
ISTAT0
Port input status
0
1
ISTAT1
Port input status
1
1
ISTAT10
Port input status
10
1
ISTAT11
Port input status
11
1
ISTAT12
Port input status
12
1
ISTAT13
Port input status
13
1
ISTAT14
Port input status
14
1
ISTAT15
Port input status
15
1
ISTAT2
Port input status
2
1
ISTAT3
Port input status
3
1
ISTAT4
Port input status
4
1
ISTAT5
Port input status
5
1
ISTAT6
Port input status
6
1
ISTAT7
Port input status
7
1
ISTAT8
Port input status
8
1
ISTAT9
Port input status
9
1
LOCK
LOCK
GPIO port configuration lock register
0x18
32
read-write
n
0x0
0x0
LK0
Port Lock bit 0
0
1
LK1
Port Lock bit 1
1
1
LK10
Port Lock bit 10
10
1
LK11
Port Lock bit 11
11
1
LK12
Port Lock bit 12
12
1
LK13
Port Lock bit 13
13
1
LK14
Port Lock bit 14
14
1
LK15
Port Lock bit 15
15
1
LK2
Port Lock bit 2
2
1
LK3
Port Lock bit 3
3
1
LK4
Port Lock bit 4
4
1
LK5
Port Lock bit 5
5
1
LK6
Port Lock bit 6
6
1
LK7
Port Lock bit 7
7
1
LK8
Port Lock bit 8
8
1
LK9
Port Lock bit 9
9
1
LKK
Lock sequence key
16
1
OCTL
OCTL
Port output control register
0xC
32
read-write
n
0x0
0x0
OCTL0
Port output control
0
1
OCTL1
Port output control
1
1
OCTL10
Port output control
10
1
OCTL11
Port output control
11
1
OCTL12
Port output control
12
1
OCTL13
Port output control
13
1
OCTL14
Port output control
14
1
OCTL15
Port output control
15
1
OCTL2
Port output control
2
1
OCTL3
Port output control
3
1
OCTL4
Port output control
4
1
OCTL5
Port output control
5
1
OCTL6
Port output control
6
1
OCTL7
Port output control
7
1
OCTL8
Port output control
8
1
OCTL9
Port output control
9
1
GPIOC
GPIO
0x0
0x0
0x400
registers
n
BC
BC
Port bit clear register
0x14
32
write-only
n
0x0
0x0
CR0
Port 0 Clear bit
0
1
CR1
Port 1 Clear bit
1
1
CR10
Port 10 Clear bit
10
1
CR11
Port 11 Clear bit
11
1
CR12
Port 12 Clear bit
12
1
CR13
Port 13 Clear bit
13
1
CR14
Port 14 Clear bit
14
1
CR15
Port 15 Clear bit
15
1
CR2
Port 2 Clear bit
2
1
CR3
Port 3 Clear bit
3
1
CR4
Port 4 Clear bit
4
1
CR5
Port 5 Clear bit
5
1
CR6
Port 6 Clear bit
6
1
CR7
Port 7 Clear bit
7
1
CR8
Port 8 Clear bit
8
1
CR9
Port 9 Clear bit
9
1
BOP
BOP
Port bit operate register
0x10
32
write-only
n
0x0
0x0
BOP0
Port 0 Set bit
0
1
BOP1
Port 1 Set bit
1
1
BOP10
Port 10 Set bit
10
1
BOP11
Port 11 Set bit
11
1
BOP12
Port 12 Set bit
12
1
BOP13
Port 13 Set bit
13
1
BOP14
Port 14 Set bit
14
1
BOP15
Port 15 Set bit
15
1
BOP2
Port 2 Set bit
2
1
BOP3
Port 3 Set bit
3
1
BOP4
Port 4 Set bit
4
1
BOP5
Port 5 Set bit
5
1
BOP6
Port 6 Set bit
6
1
BOP7
Port 7 Set bit
7
1
BOP8
Port 8 Set bit
8
1
BOP9
Port 9 Set bit
9
1
CR0
Port 0 Clear bit
16
1
CR1
Port 1 Clear bit
17
1
CR10
Port 10 Clear bit
26
1
CR11
Port 11 Clear bit
27
1
CR12
Port 12 Clear bit
28
1
CR13
Port 13 Clear bit
29
1
CR14
Port 14 Clear bit
30
1
CR15
Port 15 Clear bit
31
1
CR2
Port 2 Clear bit
18
1
CR3
Port 3 Clear bit
19
1
CR4
Port 4 Clear bit
20
1
CR5
Port 5 Clear bit
21
1
CR6
Port 6 Clear bit
22
1
CR7
Port 7 Clear bit
23
1
CR8
Port 8 Clear bit
24
1
CR9
Port 9 Clear bit
25
1
CTL0
CTL0
port control register 0
0x0
32
read-write
n
0x0
0x0
CTL0
Port x configuration bits (x = 0)
2
2
CTL1
Port x configuration bits (x = 1)
6
2
CTL2
Port x configuration bits (x = 2)
10
2
CTL3
Port x configuration bits (x = 3)
14
2
CTL4
Port x configuration bits (x = 4)
18
2
CTL5
Port x configuration bits (x = 5)
22
2
CTL6
Port x configuration bits (x = 6)
26
2
CTL7
Port x configuration bits (x = 7)
30
2
MD0
Port x mode bits (x = 0)
0
2
MD1
Port x mode bits (x = 1)
4
2
MD2
Port x mode bits (x = 2 )
8
2
MD3
Port x mode bits (x = 3 )
12
2
MD4
Port x mode bits (x = 4)
16
2
MD5
Port x mode bits (x = 5)
20
2
MD6
Port x mode bits (x = 6)
24
2
MD7
Port x mode bits (x = 7)
28
2
CTL1
CTL1
port control register 1
0x4
32
read-write
n
0x0
0x0
CTL10
Port x configuration bits (x = 10)
10
2
CTL11
Port x configuration bits (x = 11)
14
2
CTL12
Port x configuration bits (x = 12)
18
2
CTL13
Port x configuration bits (x = 13)
22
2
CTL14
Port x configuration bits (x = 14)
26
2
CTL15
Port x configuration bits (x = 15)
30
2
CTL8
Port x configuration bits (x = 8)
2
2
CTL9
Port x configuration bits (x = 9)
6
2
MD10
Port x mode bits (x = 10 )
8
2
MD11
Port x mode bits (x = 11 )
12
2
MD12
Port x mode bits (x = 12)
16
2
MD13
Port x mode bits (x = 13)
20
2
MD14
Port x mode bits (x = 14)
24
2
MD15
Port x mode bits (x = 15)
28
2
MD8
Port x mode bits (x = 8)
0
2
MD9
Port x mode bits (x = 9)
4
2
ISTAT
ISTAT
Port input status register
0x8
32
read-only
n
0x0
0x0
ISTAT0
Port input status
0
1
ISTAT1
Port input status
1
1
ISTAT10
Port input status
10
1
ISTAT11
Port input status
11
1
ISTAT12
Port input status
12
1
ISTAT13
Port input status
13
1
ISTAT14
Port input status
14
1
ISTAT15
Port input status
15
1
ISTAT2
Port input status
2
1
ISTAT3
Port input status
3
1
ISTAT4
Port input status
4
1
ISTAT5
Port input status
5
1
ISTAT6
Port input status
6
1
ISTAT7
Port input status
7
1
ISTAT8
Port input status
8
1
ISTAT9
Port input status
9
1
LOCK
LOCK
GPIO port configuration lock register
0x18
32
read-write
n
0x0
0x0
LK0
Port Lock bit 0
0
1
LK1
Port Lock bit 1
1
1
LK10
Port Lock bit 10
10
1
LK11
Port Lock bit 11
11
1
LK12
Port Lock bit 12
12
1
LK13
Port Lock bit 13
13
1
LK14
Port Lock bit 14
14
1
LK15
Port Lock bit 15
15
1
LK2
Port Lock bit 2
2
1
LK3
Port Lock bit 3
3
1
LK4
Port Lock bit 4
4
1
LK5
Port Lock bit 5
5
1
LK6
Port Lock bit 6
6
1
LK7
Port Lock bit 7
7
1
LK8
Port Lock bit 8
8
1
LK9
Port Lock bit 9
9
1
LKK
Lock sequence key
16
1
OCTL
OCTL
Port output control register
0xC
32
read-write
n
0x0
0x0
OCTL0
Port output control
0
1
OCTL1
Port output control
1
1
OCTL10
Port output control
10
1
OCTL11
Port output control
11
1
OCTL12
Port output control
12
1
OCTL13
Port output control
13
1
OCTL14
Port output control
14
1
OCTL15
Port output control
15
1
OCTL2
Port output control
2
1
OCTL3
Port output control
3
1
OCTL4
Port output control
4
1
OCTL5
Port output control
5
1
OCTL6
Port output control
6
1
OCTL7
Port output control
7
1
OCTL8
Port output control
8
1
OCTL9
Port output control
9
1
GPIOD
GPIO
0x0
0x0
0x400
registers
n
BC
BC
Port bit clear register
0x14
32
write-only
n
0x0
0x0
CR0
Port 0 Clear bit
0
1
CR1
Port 1 Clear bit
1
1
CR10
Port 10 Clear bit
10
1
CR11
Port 11 Clear bit
11
1
CR12
Port 12 Clear bit
12
1
CR13
Port 13 Clear bit
13
1
CR14
Port 14 Clear bit
14
1
CR15
Port 15 Clear bit
15
1
CR2
Port 2 Clear bit
2
1
CR3
Port 3 Clear bit
3
1
CR4
Port 4 Clear bit
4
1
CR5
Port 5 Clear bit
5
1
CR6
Port 6 Clear bit
6
1
CR7
Port 7 Clear bit
7
1
CR8
Port 8 Clear bit
8
1
CR9
Port 9 Clear bit
9
1
BOP
BOP
Port bit operate register
0x10
32
write-only
n
0x0
0x0
BOP0
Port 0 Set bit
0
1
BOP1
Port 1 Set bit
1
1
BOP10
Port 10 Set bit
10
1
BOP11
Port 11 Set bit
11
1
BOP12
Port 12 Set bit
12
1
BOP13
Port 13 Set bit
13
1
BOP14
Port 14 Set bit
14
1
BOP15
Port 15 Set bit
15
1
BOP2
Port 2 Set bit
2
1
BOP3
Port 3 Set bit
3
1
BOP4
Port 4 Set bit
4
1
BOP5
Port 5 Set bit
5
1
BOP6
Port 6 Set bit
6
1
BOP7
Port 7 Set bit
7
1
BOP8
Port 8 Set bit
8
1
BOP9
Port 9 Set bit
9
1
CR0
Port 0 Clear bit
16
1
CR1
Port 1 Clear bit
17
1
CR10
Port 10 Clear bit
26
1
CR11
Port 11 Clear bit
27
1
CR12
Port 12 Clear bit
28
1
CR13
Port 13 Clear bit
29
1
CR14
Port 14 Clear bit
30
1
CR15
Port 15 Clear bit
31
1
CR2
Port 2 Clear bit
18
1
CR3
Port 3 Clear bit
19
1
CR4
Port 4 Clear bit
20
1
CR5
Port 5 Clear bit
21
1
CR6
Port 6 Clear bit
22
1
CR7
Port 7 Clear bit
23
1
CR8
Port 8 Clear bit
24
1
CR9
Port 9 Clear bit
25
1
CTL0
CTL0
port control register 0
0x0
32
read-write
n
0x0
0x0
CTL0
Port x configuration bits (x = 0)
2
2
CTL1
Port x configuration bits (x = 1)
6
2
CTL2
Port x configuration bits (x = 2)
10
2
CTL3
Port x configuration bits (x = 3)
14
2
CTL4
Port x configuration bits (x = 4)
18
2
CTL5
Port x configuration bits (x = 5)
22
2
CTL6
Port x configuration bits (x = 6)
26
2
CTL7
Port x configuration bits (x = 7)
30
2
MD0
Port x mode bits (x = 0)
0
2
MD1
Port x mode bits (x = 1)
4
2
MD2
Port x mode bits (x = 2 )
8
2
MD3
Port x mode bits (x = 3 )
12
2
MD4
Port x mode bits (x = 4)
16
2
MD5
Port x mode bits (x = 5)
20
2
MD6
Port x mode bits (x = 6)
24
2
MD7
Port x mode bits (x = 7)
28
2
CTL1
CTL1
port control register 1
0x4
32
read-write
n
0x0
0x0
CTL10
Port x configuration bits (x = 10)
10
2
CTL11
Port x configuration bits (x = 11)
14
2
CTL12
Port x configuration bits (x = 12)
18
2
CTL13
Port x configuration bits (x = 13)
22
2
CTL14
Port x configuration bits (x = 14)
26
2
CTL15
Port x configuration bits (x = 15)
30
2
CTL8
Port x configuration bits (x = 8)
2
2
CTL9
Port x configuration bits (x = 9)
6
2
MD10
Port x mode bits (x = 10 )
8
2
MD11
Port x mode bits (x = 11 )
12
2
MD12
Port x mode bits (x = 12)
16
2
MD13
Port x mode bits (x = 13)
20
2
MD14
Port x mode bits (x = 14)
24
2
MD15
Port x mode bits (x = 15)
28
2
MD8
Port x mode bits (x = 8)
0
2
MD9
Port x mode bits (x = 9)
4
2
ISTAT
ISTAT
Port input status register
0x8
32
read-only
n
0x0
0x0
ISTAT0
Port input status
0
1
ISTAT1
Port input status
1
1
ISTAT10
Port input status
10
1
ISTAT11
Port input status
11
1
ISTAT12
Port input status
12
1
ISTAT13
Port input status
13
1
ISTAT14
Port input status
14
1
ISTAT15
Port input status
15
1
ISTAT2
Port input status
2
1
ISTAT3
Port input status
3
1
ISTAT4
Port input status
4
1
ISTAT5
Port input status
5
1
ISTAT6
Port input status
6
1
ISTAT7
Port input status
7
1
ISTAT8
Port input status
8
1
ISTAT9
Port input status
9
1
LOCK
LOCK
GPIO port configuration lock register
0x18
32
read-write
n
0x0
0x0
LK0
Port Lock bit 0
0
1
LK1
Port Lock bit 1
1
1
LK10
Port Lock bit 10
10
1
LK11
Port Lock bit 11
11
1
LK12
Port Lock bit 12
12
1
LK13
Port Lock bit 13
13
1
LK14
Port Lock bit 14
14
1
LK15
Port Lock bit 15
15
1
LK2
Port Lock bit 2
2
1
LK3
Port Lock bit 3
3
1
LK4
Port Lock bit 4
4
1
LK5
Port Lock bit 5
5
1
LK6
Port Lock bit 6
6
1
LK7
Port Lock bit 7
7
1
LK8
Port Lock bit 8
8
1
LK9
Port Lock bit 9
9
1
LKK
Lock sequence key
16
1
OCTL
OCTL
Port output control register
0xC
32
read-write
n
0x0
0x0
OCTL0
Port output control
0
1
OCTL1
Port output control
1
1
OCTL10
Port output control
10
1
OCTL11
Port output control
11
1
OCTL12
Port output control
12
1
OCTL13
Port output control
13
1
OCTL14
Port output control
14
1
OCTL15
Port output control
15
1
OCTL2
Port output control
2
1
OCTL3
Port output control
3
1
OCTL4
Port output control
4
1
OCTL5
Port output control
5
1
OCTL6
Port output control
6
1
OCTL7
Port output control
7
1
OCTL8
Port output control
8
1
OCTL9
Port output control
9
1
GPIOE
GPIO
0x0
0x0
0x400
registers
n
BC
BC
Port bit clear register
0x14
32
write-only
n
0x0
0x0
CR0
Port 0 Clear bit
0
1
CR1
Port 1 Clear bit
1
1
CR10
Port 10 Clear bit
10
1
CR11
Port 11 Clear bit
11
1
CR12
Port 12 Clear bit
12
1
CR13
Port 13 Clear bit
13
1
CR14
Port 14 Clear bit
14
1
CR15
Port 15 Clear bit
15
1
CR2
Port 2 Clear bit
2
1
CR3
Port 3 Clear bit
3
1
CR4
Port 4 Clear bit
4
1
CR5
Port 5 Clear bit
5
1
CR6
Port 6 Clear bit
6
1
CR7
Port 7 Clear bit
7
1
CR8
Port 8 Clear bit
8
1
CR9
Port 9 Clear bit
9
1
BOP
BOP
Port bit operate register
0x10
32
write-only
n
0x0
0x0
BOP0
Port 0 Set bit
0
1
BOP1
Port 1 Set bit
1
1
BOP10
Port 10 Set bit
10
1
BOP11
Port 11 Set bit
11
1
BOP12
Port 12 Set bit
12
1
BOP13
Port 13 Set bit
13
1
BOP14
Port 14 Set bit
14
1
BOP15
Port 15 Set bit
15
1
BOP2
Port 2 Set bit
2
1
BOP3
Port 3 Set bit
3
1
BOP4
Port 4 Set bit
4
1
BOP5
Port 5 Set bit
5
1
BOP6
Port 6 Set bit
6
1
BOP7
Port 7 Set bit
7
1
BOP8
Port 8 Set bit
8
1
BOP9
Port 9 Set bit
9
1
CR0
Port 0 Clear bit
16
1
CR1
Port 1 Clear bit
17
1
CR10
Port 10 Clear bit
26
1
CR11
Port 11 Clear bit
27
1
CR12
Port 12 Clear bit
28
1
CR13
Port 13 Clear bit
29
1
CR14
Port 14 Clear bit
30
1
CR15
Port 15 Clear bit
31
1
CR2
Port 2 Clear bit
18
1
CR3
Port 3 Clear bit
19
1
CR4
Port 4 Clear bit
20
1
CR5
Port 5 Clear bit
21
1
CR6
Port 6 Clear bit
22
1
CR7
Port 7 Clear bit
23
1
CR8
Port 8 Clear bit
24
1
CR9
Port 9 Clear bit
25
1
CTL0
CTL0
port control register 0
0x0
32
read-write
n
0x0
0x0
CTL0
Port x configuration bits (x = 0)
2
2
CTL1
Port x configuration bits (x = 1)
6
2
CTL2
Port x configuration bits (x = 2)
10
2
CTL3
Port x configuration bits (x = 3)
14
2
CTL4
Port x configuration bits (x = 4)
18
2
CTL5
Port x configuration bits (x = 5)
22
2
CTL6
Port x configuration bits (x = 6)
26
2
CTL7
Port x configuration bits (x = 7)
30
2
MD0
Port x mode bits (x = 0)
0
2
MD1
Port x mode bits (x = 1)
4
2
MD2
Port x mode bits (x = 2 )
8
2
MD3
Port x mode bits (x = 3 )
12
2
MD4
Port x mode bits (x = 4)
16
2
MD5
Port x mode bits (x = 5)
20
2
MD6
Port x mode bits (x = 6)
24
2
MD7
Port x mode bits (x = 7)
28
2
CTL1
CTL1
port control register 1
0x4
32
read-write
n
0x0
0x0
CTL10
Port x configuration bits (x = 10)
10
2
CTL11
Port x configuration bits (x = 11)
14
2
CTL12
Port x configuration bits (x = 12)
18
2
CTL13
Port x configuration bits (x = 13)
22
2
CTL14
Port x configuration bits (x = 14)
26
2
CTL15
Port x configuration bits (x = 15)
30
2
CTL8
Port x configuration bits (x = 8)
2
2
CTL9
Port x configuration bits (x = 9)
6
2
MD10
Port x mode bits (x = 10 )
8
2
MD11
Port x mode bits (x = 11 )
12
2
MD12
Port x mode bits (x = 12)
16
2
MD13
Port x mode bits (x = 13)
20
2
MD14
Port x mode bits (x = 14)
24
2
MD15
Port x mode bits (x = 15)
28
2
MD8
Port x mode bits (x = 8)
0
2
MD9
Port x mode bits (x = 9)
4
2
ISTAT
ISTAT
Port input status register
0x8
32
read-only
n
0x0
0x0
ISTAT0
Port input status
0
1
ISTAT1
Port input status
1
1
ISTAT10
Port input status
10
1
ISTAT11
Port input status
11
1
ISTAT12
Port input status
12
1
ISTAT13
Port input status
13
1
ISTAT14
Port input status
14
1
ISTAT15
Port input status
15
1
ISTAT2
Port input status
2
1
ISTAT3
Port input status
3
1
ISTAT4
Port input status
4
1
ISTAT5
Port input status
5
1
ISTAT6
Port input status
6
1
ISTAT7
Port input status
7
1
ISTAT8
Port input status
8
1
ISTAT9
Port input status
9
1
LOCK
LOCK
GPIO port configuration lock register
0x18
32
read-write
n
0x0
0x0
LK0
Port Lock bit 0
0
1
LK1
Port Lock bit 1
1
1
LK10
Port Lock bit 10
10
1
LK11
Port Lock bit 11
11
1
LK12
Port Lock bit 12
12
1
LK13
Port Lock bit 13
13
1
LK14
Port Lock bit 14
14
1
LK15
Port Lock bit 15
15
1
LK2
Port Lock bit 2
2
1
LK3
Port Lock bit 3
3
1
LK4
Port Lock bit 4
4
1
LK5
Port Lock bit 5
5
1
LK6
Port Lock bit 6
6
1
LK7
Port Lock bit 7
7
1
LK8
Port Lock bit 8
8
1
LK9
Port Lock bit 9
9
1
LKK
Lock sequence key
16
1
OCTL
OCTL
Port output control register
0xC
32
read-write
n
0x0
0x0
OCTL0
Port output control
0
1
OCTL1
Port output control
1
1
OCTL10
Port output control
10
1
OCTL11
Port output control
11
1
OCTL12
Port output control
12
1
OCTL13
Port output control
13
1
OCTL14
Port output control
14
1
OCTL15
Port output control
15
1
OCTL2
Port output control
2
1
OCTL3
Port output control
3
1
OCTL4
Port output control
4
1
OCTL5
Port output control
5
1
OCTL6
Port output control
6
1
OCTL7
Port output control
7
1
OCTL8
Port output control
8
1
OCTL9
Port output control
9
1
GPIOF
GPIO
0x0
0x0
0x400
registers
n
BC
BC
Port bit clear register
0x14
32
write-only
n
0x0
0x0
CR0
Port 0 Clear bit
0
1
CR1
Port 1 Clear bit
1
1
CR10
Port 10 Clear bit
10
1
CR11
Port 11 Clear bit
11
1
CR12
Port 12 Clear bit
12
1
CR13
Port 13 Clear bit
13
1
CR14
Port 14 Clear bit
14
1
CR15
Port 15 Clear bit
15
1
CR2
Port 2 Clear bit
2
1
CR3
Port 3 Clear bit
3
1
CR4
Port 4 Clear bit
4
1
CR5
Port 5 Clear bit
5
1
CR6
Port 6 Clear bit
6
1
CR7
Port 7 Clear bit
7
1
CR8
Port 8 Clear bit
8
1
CR9
Port 9 Clear bit
9
1
BOP
BOP
Port bit operate register
0x10
32
write-only
n
0x0
0x0
BOP0
Port 0 Set bit
0
1
BOP1
Port 1 Set bit
1
1
BOP10
Port 10 Set bit
10
1
BOP11
Port 11 Set bit
11
1
BOP12
Port 12 Set bit
12
1
BOP13
Port 13 Set bit
13
1
BOP14
Port 14 Set bit
14
1
BOP15
Port 15 Set bit
15
1
BOP2
Port 2 Set bit
2
1
BOP3
Port 3 Set bit
3
1
BOP4
Port 4 Set bit
4
1
BOP5
Port 5 Set bit
5
1
BOP6
Port 6 Set bit
6
1
BOP7
Port 7 Set bit
7
1
BOP8
Port 8 Set bit
8
1
BOP9
Port 9 Set bit
9
1
CR0
Port 0 Clear bit
16
1
CR1
Port 1 Clear bit
17
1
CR10
Port 10 Clear bit
26
1
CR11
Port 11 Clear bit
27
1
CR12
Port 12 Clear bit
28
1
CR13
Port 13 Clear bit
29
1
CR14
Port 14 Clear bit
30
1
CR15
Port 15 Clear bit
31
1
CR2
Port 2 Clear bit
18
1
CR3
Port 3 Clear bit
19
1
CR4
Port 4 Clear bit
20
1
CR5
Port 5 Clear bit
21
1
CR6
Port 6 Clear bit
22
1
CR7
Port 7 Clear bit
23
1
CR8
Port 8 Clear bit
24
1
CR9
Port 9 Clear bit
25
1
CTL0
CTL0
port control register 0
0x0
32
read-write
n
0x0
0x0
CTL0
Port x configuration bits (x = 0)
2
2
CTL1
Port x configuration bits (x = 1)
6
2
CTL2
Port x configuration bits (x = 2)
10
2
CTL3
Port x configuration bits (x = 3)
14
2
CTL4
Port x configuration bits (x = 4)
18
2
CTL5
Port x configuration bits (x = 5)
22
2
CTL6
Port x configuration bits (x = 6)
26
2
CTL7
Port x configuration bits (x = 7)
30
2
MD0
Port x mode bits (x = 0)
0
2
MD1
Port x mode bits (x = 1)
4
2
MD2
Port x mode bits (x = 2 )
8
2
MD3
Port x mode bits (x = 3 )
12
2
MD4
Port x mode bits (x = 4)
16
2
MD5
Port x mode bits (x = 5)
20
2
MD6
Port x mode bits (x = 6)
24
2
MD7
Port x mode bits (x = 7)
28
2
CTL1
CTL1
port control register 1
0x4
32
read-write
n
0x0
0x0
CTL10
Port x configuration bits (x = 10)
10
2
CTL11
Port x configuration bits (x = 11)
14
2
CTL12
Port x configuration bits (x = 12)
18
2
CTL13
Port x configuration bits (x = 13)
22
2
CTL14
Port x configuration bits (x = 14)
26
2
CTL15
Port x configuration bits (x = 15)
30
2
CTL8
Port x configuration bits (x = 8)
2
2
CTL9
Port x configuration bits (x = 9)
6
2
MD10
Port x mode bits (x = 10 )
8
2
MD11
Port x mode bits (x = 11 )
12
2
MD12
Port x mode bits (x = 12)
16
2
MD13
Port x mode bits (x = 13)
20
2
MD14
Port x mode bits (x = 14)
24
2
MD15
Port x mode bits (x = 15)
28
2
MD8
Port x mode bits (x = 8)
0
2
MD9
Port x mode bits (x = 9)
4
2
ISTAT
ISTAT
Port input status register
0x8
32
read-only
n
0x0
0x0
ISTAT0
Port input status
0
1
ISTAT1
Port input status
1
1
ISTAT10
Port input status
10
1
ISTAT11
Port input status
11
1
ISTAT12
Port input status
12
1
ISTAT13
Port input status
13
1
ISTAT14
Port input status
14
1
ISTAT15
Port input status
15
1
ISTAT2
Port input status
2
1
ISTAT3
Port input status
3
1
ISTAT4
Port input status
4
1
ISTAT5
Port input status
5
1
ISTAT6
Port input status
6
1
ISTAT7
Port input status
7
1
ISTAT8
Port input status
8
1
ISTAT9
Port input status
9
1
LOCK
LOCK
GPIO port configuration lock register
0x18
32
read-write
n
0x0
0x0
LK0
Port Lock bit 0
0
1
LK1
Port Lock bit 1
1
1
LK10
Port Lock bit 10
10
1
LK11
Port Lock bit 11
11
1
LK12
Port Lock bit 12
12
1
LK13
Port Lock bit 13
13
1
LK14
Port Lock bit 14
14
1
LK15
Port Lock bit 15
15
1
LK2
Port Lock bit 2
2
1
LK3
Port Lock bit 3
3
1
LK4
Port Lock bit 4
4
1
LK5
Port Lock bit 5
5
1
LK6
Port Lock bit 6
6
1
LK7
Port Lock bit 7
7
1
LK8
Port Lock bit 8
8
1
LK9
Port Lock bit 9
9
1
LKK
Lock sequence key
16
1
OCTL
OCTL
Port output control register
0xC
32
read-write
n
0x0
0x0
OCTL0
Port output control
0
1
OCTL1
Port output control
1
1
OCTL10
Port output control
10
1
OCTL11
Port output control
11
1
OCTL12
Port output control
12
1
OCTL13
Port output control
13
1
OCTL14
Port output control
14
1
OCTL15
Port output control
15
1
OCTL2
Port output control
2
1
OCTL3
Port output control
3
1
OCTL4
Port output control
4
1
OCTL5
Port output control
5
1
OCTL6
Port output control
6
1
OCTL7
Port output control
7
1
OCTL8
Port output control
8
1
OCTL9
Port output control
9
1
GPIOG
GPIO
0x0
0x0
0x400
registers
n
BC
BC
Port bit clear register
0x14
32
write-only
n
0x0
0x0
CR0
Port 0 Clear bit
0
1
CR1
Port 1 Clear bit
1
1
CR10
Port 10 Clear bit
10
1
CR11
Port 11 Clear bit
11
1
CR12
Port 12 Clear bit
12
1
CR13
Port 13 Clear bit
13
1
CR14
Port 14 Clear bit
14
1
CR15
Port 15 Clear bit
15
1
CR2
Port 2 Clear bit
2
1
CR3
Port 3 Clear bit
3
1
CR4
Port 4 Clear bit
4
1
CR5
Port 5 Clear bit
5
1
CR6
Port 6 Clear bit
6
1
CR7
Port 7 Clear bit
7
1
CR8
Port 8 Clear bit
8
1
CR9
Port 9 Clear bit
9
1
BOP
BOP
Port bit operate register
0x10
32
write-only
n
0x0
0x0
BOP0
Port 0 Set bit
0
1
BOP1
Port 1 Set bit
1
1
BOP10
Port 10 Set bit
10
1
BOP11
Port 11 Set bit
11
1
BOP12
Port 12 Set bit
12
1
BOP13
Port 13 Set bit
13
1
BOP14
Port 14 Set bit
14
1
BOP15
Port 15 Set bit
15
1
BOP2
Port 2 Set bit
2
1
BOP3
Port 3 Set bit
3
1
BOP4
Port 4 Set bit
4
1
BOP5
Port 5 Set bit
5
1
BOP6
Port 6 Set bit
6
1
BOP7
Port 7 Set bit
7
1
BOP8
Port 8 Set bit
8
1
BOP9
Port 9 Set bit
9
1
CR0
Port 0 Clear bit
16
1
CR1
Port 1 Clear bit
17
1
CR10
Port 10 Clear bit
26
1
CR11
Port 11 Clear bit
27
1
CR12
Port 12 Clear bit
28
1
CR13
Port 13 Clear bit
29
1
CR14
Port 14 Clear bit
30
1
CR15
Port 15 Clear bit
31
1
CR2
Port 2 Clear bit
18
1
CR3
Port 3 Clear bit
19
1
CR4
Port 4 Clear bit
20
1
CR5
Port 5 Clear bit
21
1
CR6
Port 6 Clear bit
22
1
CR7
Port 7 Clear bit
23
1
CR8
Port 8 Clear bit
24
1
CR9
Port 9 Clear bit
25
1
CTL0
CTL0
port control register 0
0x0
32
read-write
n
0x0
0x0
CTL0
Port x configuration bits (x = 0)
2
2
CTL1
Port x configuration bits (x = 1)
6
2
CTL2
Port x configuration bits (x = 2)
10
2
CTL3
Port x configuration bits (x = 3)
14
2
CTL4
Port x configuration bits (x = 4)
18
2
CTL5
Port x configuration bits (x = 5)
22
2
CTL6
Port x configuration bits (x = 6)
26
2
CTL7
Port x configuration bits (x = 7)
30
2
MD0
Port x mode bits (x = 0)
0
2
MD1
Port x mode bits (x = 1)
4
2
MD2
Port x mode bits (x = 2 )
8
2
MD3
Port x mode bits (x = 3 )
12
2
MD4
Port x mode bits (x = 4)
16
2
MD5
Port x mode bits (x = 5)
20
2
MD6
Port x mode bits (x = 6)
24
2
MD7
Port x mode bits (x = 7)
28
2
CTL1
CTL1
port control register 1
0x4
32
read-write
n
0x0
0x0
CTL10
Port x configuration bits (x = 10)
10
2
CTL11
Port x configuration bits (x = 11)
14
2
CTL12
Port x configuration bits (x = 12)
18
2
CTL13
Port x configuration bits (x = 13)
22
2
CTL14
Port x configuration bits (x = 14)
26
2
CTL15
Port x configuration bits (x = 15)
30
2
CTL8
Port x configuration bits (x = 8)
2
2
CTL9
Port x configuration bits (x = 9)
6
2
MD10
Port x mode bits (x = 10 )
8
2
MD11
Port x mode bits (x = 11 )
12
2
MD12
Port x mode bits (x = 12)
16
2
MD13
Port x mode bits (x = 13)
20
2
MD14
Port x mode bits (x = 14)
24
2
MD15
Port x mode bits (x = 15)
28
2
MD8
Port x mode bits (x = 8)
0
2
MD9
Port x mode bits (x = 9)
4
2
ISTAT
ISTAT
Port input status register
0x8
32
read-only
n
0x0
0x0
ISTAT0
Port input status
0
1
ISTAT1
Port input status
1
1
ISTAT10
Port input status
10
1
ISTAT11
Port input status
11
1
ISTAT12
Port input status
12
1
ISTAT13
Port input status
13
1
ISTAT14
Port input status
14
1
ISTAT15
Port input status
15
1
ISTAT2
Port input status
2
1
ISTAT3
Port input status
3
1
ISTAT4
Port input status
4
1
ISTAT5
Port input status
5
1
ISTAT6
Port input status
6
1
ISTAT7
Port input status
7
1
ISTAT8
Port input status
8
1
ISTAT9
Port input status
9
1
LOCK
LOCK
GPIO port configuration lock register
0x18
32
read-write
n
0x0
0x0
LK0
Port Lock bit 0
0
1
LK1
Port Lock bit 1
1
1
LK10
Port Lock bit 10
10
1
LK11
Port Lock bit 11
11
1
LK12
Port Lock bit 12
12
1
LK13
Port Lock bit 13
13
1
LK14
Port Lock bit 14
14
1
LK15
Port Lock bit 15
15
1
LK2
Port Lock bit 2
2
1
LK3
Port Lock bit 3
3
1
LK4
Port Lock bit 4
4
1
LK5
Port Lock bit 5
5
1
LK6
Port Lock bit 6
6
1
LK7
Port Lock bit 7
7
1
LK8
Port Lock bit 8
8
1
LK9
Port Lock bit 9
9
1
LKK
Lock sequence key
16
1
OCTL
OCTL
Port output control register
0xC
32
read-write
n
0x0
0x0
OCTL0
Port output control
0
1
OCTL1
Port output control
1
1
OCTL10
Port output control
10
1
OCTL11
Port output control
11
1
OCTL12
Port output control
12
1
OCTL13
Port output control
13
1
OCTL14
Port output control
14
1
OCTL15
Port output control
15
1
OCTL2
Port output control
2
1
OCTL3
Port output control
3
1
OCTL4
Port output control
4
1
OCTL5
Port output control
5
1
OCTL6
Port output control
6
1
OCTL7
Port output control
7
1
OCTL8
Port output control
8
1
OCTL9
Port output control
9
1
I2C0
Inter integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C0_EV
31
I2C0_ER
32
CKCFG
CKCFG
Clock configure register
0x1C
32
read-write
n
0x0
0x0
CLKC
I2C Clock control in master mode
0
12
DTCY
Duty cycle in fast mode
14
1
FAST
I2C speed selection in master mode
15
1
CTL0
CTL0
Control register 0
0x0
32
read-write
n
0x0
0x0
ACKEN
Whether or not to send an ACK
10
1
ARPEN
ARP protocol in SMBus switch
4
1
DISSTRC
Whether to stretch SCL low when data is not ready in slave mode
7
1
GCEN
Whether or not to response to a General Call (0x00)
6
1
I2CEN
I2C peripheral enable
0
1
PECEN
PEC Calculation Switch
5
1
PECTRANS
PEC Transfer
12
1
POAP
Position of ACK and PEC when receiving
11
1
SALT
SMBus alert
13
1
SMBEN
SMBus/I2C mode switch
1
1
SMBSEL
SMBusType Selection
3
1
SRESET
Software reset
15
1
START
Generate a START condition on I2C bus
8
1
STOP
Generate a STOP condition on I2C bus
9
1
CTL1
CTL1
Control register 1
0x4
32
read-write
n
0x0
0x0
BUFIE
Buffer interrupt enable
10
1
DMALST
Flag indicating DMA last transfer
12
1
DMAON
DMA mode switch
11
1
ERRIE
Error interrupt enable
8
1
EVIE
Event interrupt enable
9
1
I2CCLK
I2C Peripheral clock frequency
0
6
DATA
DATA
Transfer buffer register
0x10
32
read-write
n
0x0
0x0
TRB
Transmission or reception data buffer register
0
8
RT
RT
Rise time register
0x20
32
read-write
n
0x0
0x0
RISETIME
Maximum rise time in master mode
0
6
SADDR0
SADDR0
Slave address register 0
0x8
32
read-write
n
0x0
0x0
ADDFORMAT
Address mode for the I2C slave
15
1
ADDRESS0
Bit 0 of a 10-bit address
0
1
ADDRESS7_1
7-bit address or bits 7:1 of a 10-bit address
1
7
ADDRESS9_8
Highest two bits of a 10-bit address
8
2
SADDR1
SADDR1
Slave address register 1
0xC
32
read-write
n
0x0
0x0
ADDRESS2
Second I2C address for the slave in Dual-Address mode
1
7
DUADEN
Dual-Address mode switch
0
1
STAT0
STAT0
Transfer status register 0
0x14
32
read-write
n
0x0
0x0
ADD10SEND
Header of 10-bit address is sent in master mode
3
1
read-only
ADDSEND
Address is sent in master mode or received and matches in slave mode
1
1
read-only
AERR
Acknowledge error
10
1
read-write
BERR
A bus error occurs indication a unexpected START or STOP condition on I2C bus
8
1
read-write
BTC
Byte transmission completed
2
1
read-only
LOSTARB
Arbitration Lost in master mode
9
1
read-write
OUERR
Over-run or under-run situation occurs in slave mode
11
1
read-write
PECERR
PEC error when receiving data
12
1
read-write
RBNE
I2C_DATA is not Empty during receiving
6
1
read-only
SBSEND
START condition sent out in master mode
0
1
read-only
SMBALT
SMBus Alert status
15
1
read-write
SMBTO
Timeout signal in SMBus mode
14
1
read-write
STPDET
STOP condition detected in slave mode
4
1
read-only
TBE
I2C_DATA is Empty during transmitting
7
1
read-only
STAT1
STAT1
Transfer status register 1
0x18
32
read-only
n
0x0
0x0
DEFSMB
Default address of SMBusDevice
5
1
DUMODF
Dual Flag in slave mode
7
1
ECV
Packet Error Checking Value that calculated by hardware when PEC is enabled
8
8
HSTSMB
SMBus Host Header detected in slave mode
6
1
I2CBSY
Busy flag
1
1
MASTER
A flag indicating whether I2C block is in master or slave mode
0
1
RXGC
General call address (00h) received
4
1
TRS
Whether the I2C is a transmitter or a receiver
2
1
I2C1
Inter integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C1_EV
33
I2C1_ER
34
CKCFG
CKCFG
Clock configure register
0x1C
32
read-write
n
0x0
0x0
CLKC
I2C Clock control in master mode
0
12
DTCY
Duty cycle in fast mode
14
1
FAST
I2C speed selection in master mode
15
1
CTL0
CTL0
Control register 0
0x0
32
read-write
n
0x0
0x0
ACKEN
Whether or not to send an ACK
10
1
ARPEN
ARP protocol in SMBus switch
4
1
DISSTRC
Whether to stretch SCL low when data is not ready in slave mode
7
1
GCEN
Whether or not to response to a General Call (0x00)
6
1
I2CEN
I2C peripheral enable
0
1
PECEN
PEC Calculation Switch
5
1
PECTRANS
PEC Transfer
12
1
POAP
Position of ACK and PEC when receiving
11
1
SALT
SMBus alert
13
1
SMBEN
SMBus/I2C mode switch
1
1
SMBSEL
SMBusType Selection
3
1
SRESET
Software reset
15
1
START
Generate a START condition on I2C bus
8
1
STOP
Generate a STOP condition on I2C bus
9
1
CTL1
CTL1
Control register 1
0x4
32
read-write
n
0x0
0x0
BUFIE
Buffer interrupt enable
10
1
DMALST
Flag indicating DMA last transfer
12
1
DMAON
DMA mode switch
11
1
ERRIE
Error interrupt enable
8
1
EVIE
Event interrupt enable
9
1
I2CCLK
I2C Peripheral clock frequency
0
6
DATA
DATA
Transfer buffer register
0x10
32
read-write
n
0x0
0x0
TRB
Transmission or reception data buffer register
0
8
RT
RT
Rise time register
0x20
32
read-write
n
0x0
0x0
RISETIME
Maximum rise time in master mode
0
6
SADDR0
SADDR0
Slave address register 0
0x8
32
read-write
n
0x0
0x0
ADDFORMAT
Address mode for the I2C slave
15
1
ADDRESS0
Bit 0 of a 10-bit address
0
1
ADDRESS7_1
7-bit address or bits 7:1 of a 10-bit address
1
7
ADDRESS9_8
Highest two bits of a 10-bit address
8
2
SADDR1
SADDR1
Slave address register 1
0xC
32
read-write
n
0x0
0x0
ADDRESS2
Second I2C address for the slave in Dual-Address mode
1
7
DUADEN
Dual-Address mode switch
0
1
STAT0
STAT0
Transfer status register 0
0x14
32
read-write
n
0x0
0x0
ADD10SEND
Header of 10-bit address is sent in master mode
3
1
read-only
ADDSEND
Address is sent in master mode or received and matches in slave mode
1
1
read-only
AERR
Acknowledge error
10
1
read-write
BERR
A bus error occurs indication a unexpected START or STOP condition on I2C bus
8
1
read-write
BTC
Byte transmission completed
2
1
read-only
LOSTARB
Arbitration Lost in master mode
9
1
read-write
OUERR
Over-run or under-run situation occurs in slave mode
11
1
read-write
PECERR
PEC error when receiving data
12
1
read-write
RBNE
I2C_DATA is not Empty during receiving
6
1
read-only
SBSEND
START condition sent out in master mode
0
1
read-only
SMBALT
SMBus Alert status
15
1
read-write
SMBTO
Timeout signal in SMBus mode
14
1
read-write
STPDET
STOP condition detected in slave mode
4
1
read-only
TBE
I2C_DATA is Empty during transmitting
7
1
read-only
STAT1
STAT1
Transfer status register 1
0x18
32
read-only
n
0x0
0x0
DEFSMB
Default address of SMBusDevice
5
1
DUMODF
Dual Flag in slave mode
7
1
ECV
Packet Error Checking Value that calculated by hardware when PEC is enabled
8
8
HSTSMB
SMBus Host Header detected in slave mode
6
1
I2CBSY
Busy flag
1
1
MASTER
A flag indicating whether I2C block is in master or slave mode
0
1
RXGC
General call address (00h) received
4
1
TRS
Whether the I2C is a transmitter or a receiver
2
1
NVIC
Nested Vectored Interrupt Controller
NVIC
0x0
0x0
0xF00
registers
n
0x33D
0xC3
reserved
n
IABR
IABR
Interrupt Active bit Register
0x200
32
read-write
n
0x0
0x0
IABR
IABR
0
32
ICER
ICER
Interrupt Clear Enable Register
0x80
32
read-write
n
0x0
0x0
CLRENA
CLRENA
0
32
ICPR
ICPR
Interrupt Clear-Pending Register
0x180
32
read-write
n
0x0
0x0
CLRPEND
CLRPEND
0
32
IPR0
IPR0
Interrupt Priority Register 0
0x300
8
read-write
n
0x0
0x0
PRI_00
PRI_00
0
8
IPR1
IPR1
Interrupt Priority Register 1
0x301
8
read-write
n
0x0
0x0
PRI_01
PRI_01
0
8
IPR10
IPR10
Interrupt Priority Register 10
0x30A
8
read-write
n
0x0
0x0
PRI_10
PRI_10
0
8
IPR11
IPR11
Interrupt Priority Register 11
0x30B
8
read-write
n
0x0
0x0
PRI_11
PRI_11
0
8
IPR12
IPR12
Interrupt Priority Register 12
0x30C
8
read-write
n
0x0
0x0
PRI_12
PRI_12
0
8
IPR13
IPR13
Interrupt Priority Register 13
0x30D
8
read-write
n
0x0
0x0
PRI_13
PRI_13
0
8
IPR14
IPR14
Interrupt Priority Register 14
0x30E
8
read-write
n
0x0
0x0
PRI_14
PRI_14
0
8
IPR15
IPR15
Interrupt Priority Register 15
0x30F
8
read-write
n
0x0
0x0
PRI_15
PRI_15
0
8
IPR16
IPR16
Interrupt Priority Register 16
0x310
8
read-write
n
0x0
0x0
PRI_16
PRI_16
0
8
IPR17
IPR17
Interrupt Priority Register 17
0x311
8
read-write
n
0x0
0x0
PRI_17
PRI_17
0
8
IPR18
IPR18
Interrupt Priority Register 18
0x312
8
read-write
n
0x0
0x0
PRI_18
PRI_18
0
8
IPR19
IPR19
Interrupt Priority Register 19
0x313
8
read-write
n
0x0
0x0
PRI_19
PRI_19
0
8
IPR2
IPR2
Interrupt Priority Register 2
0x302
8
read-write
n
0x0
0x0
PRI_02
PRI_02
0
8
IPR20
IPR20
Interrupt Priority Register 20
0x314
8
read-write
n
0x0
0x0
PRI_20
PRI_20
0
8
IPR21
IPR21
Interrupt Priority Register 21
0x315
8
read-write
n
0x0
0x0
PRI_21
PRI_21
0
8
IPR22
IPR22
Interrupt Priority Register 22
0x316
8
read-write
n
0x0
0x0
PRI_22
PRI_22
0
8
IPR23
IPR23
Interrupt Priority Register 23
0x317
8
read-write
n
0x0
0x0
PRI_23
PRI_23
0
8
IPR24
IPR24
Interrupt Priority Register 24
0x318
8
read-write
n
0x0
0x0
PRI_24
PRI_24
0
8
IPR25
IPR25
Interrupt Priority Register 25
0x319
8
read-write
n
0x0
0x0
PRI_25
PRI_25
0
8
IPR26
IPR26
Interrupt Priority Register 26
0x31A
8
read-write
n
0x0
0x0
PRI_26
PRI_26
0
8
IPR27
IPR27
Interrupt Priority Register 27
0x31B
8
read-write
n
0x0
0x0
PRI_27
PRI_27
0
8
IPR28
IPR28
Interrupt Priority Register 28
0x31C
8
read-write
n
0x0
0x0
PRI_28
PRI_28
0
8
IPR29
IPR29
Interrupt Priority Register 29
0x31D
8
read-write
n
0x0
0x0
PRI_29
PRI_29
0
8
IPR3
IPR3
Interrupt Priority Register 3
0x303
8
read-write
n
0x0
0x0
PRI_03
PRI_03
0
8
IPR30
IPR30
Interrupt Priority Register 30
0x31E
8
read-write
n
0x0
0x0
PRI_30
PRI_30
0
8
IPR31
IPR31
Interrupt Priority Register 31
0x31F
8
read-write
n
0x0
0x0
PRI_31
PRI_31
0
8
IPR32
IPR32
Interrupt Priority Register 32
0x320
8
read-write
n
0x0
0x0
PRI_32
PRI_32
0
8
IPR33
IPR33
Interrupt Priority Register 33
0x321
8
read-write
n
0x0
0x0
PRI_33
PRI_33
0
8
IPR34
IPR34
Interrupt Priority Register 34
0x322
8
read-write
n
0x0
0x0
PRI_34
PRI_34
0
8
IPR35
IPR35
Interrupt Priority Register 35
0x323
8
read-write
n
0x0
0x0
PRI_35
PRI_35
0
8
IPR36
IPR36
Interrupt Priority Register 36
0x324
8
read-write
n
0x0
0x0
PRI_36
PRI_36
0
8
IPR37
IPR37
Interrupt Priority Register 37
0x325
8
read-write
n
0x0
0x0
PRI_37
PRI_37
0
8
IPR38
IPR38
Interrupt Priority Register 38
0x326
8
read-write
n
0x0
0x0
PRI_38
PRI_38
0
8
IPR39
IPR39
Interrupt Priority Register 39
0x327
8
read-write
n
0x0
0x0
PRI_39
PRI_39
0
8
IPR4
IPR4
Interrupt Priority Register 4
0x304
8
read-write
n
0x0
0x0
PRI_04
PRI_04
0
8
IPR40
IPR40
Interrupt Priority Register 40
0x328
8
read-write
n
0x0
0x0
PRI_40
PRI_40
0
8
IPR41
IPR41
Interrupt Priority Register 41
0x329
8
read-write
n
0x0
0x0
PRI_41
PRI_41
0
8
IPR42
IPR42
Interrupt Priority Register 42
0x32A
8
read-write
n
0x0
0x0
PRI_42
PRI_42
0
8
IPR43
IPR43
Interrupt Priority Register 43
0x32B
8
read-write
n
0x0
0x0
PRI_43
PRI_43
0
8
IPR44
IPR44
Interrupt Priority Register 44
0x32C
8
read-write
n
0x0
0x0
PRI_44
PRI_44
0
8
IPR45
IPR45
Interrupt Priority Register 45
0x32D
8
read-write
n
0x0
0x0
PRI_45
PRI_45
0
8
IPR46
IPR46
Interrupt Priority Register 46
0x32E
8
read-write
n
0x0
0x0
PRI_46
PRI_46
0
8
IPR47
IPR47
Interrupt Priority Register 47
0x32F
8
read-write
n
0x0
0x0
PRI_47
PRI_47
0
8
IPR48
IPR48
Interrupt Priority Register 48
0x330
8
read-write
n
0x0
0x0
PRI_48
PRI_48
0
8
IPR49
IPR49
Interrupt Priority Register 49
0x331
8
read-write
n
0x0
0x0
PRI_49
PRI_49
0
8
IPR5
IPR5
Interrupt Priority Register 5
0x305
8
read-write
n
0x0
0x0
PRI_05
PRI_05
0
8
IPR50
IPR50
Interrupt Priority Register 50
0x332
8
read-write
n
0x0
0x0
PRI_50
PRI_50
0
8
IPR51
IPR51
Interrupt Priority Register 51
0x333
8
read-write
n
0x0
0x0
PRI_51
PRI_51
0
8
IPR52
IPR52
Interrupt Priority Register 52
0x334
8
read-write
n
0x0
0x0
PRI_52
PRI_52
0
8
IPR53
IPR53
Interrupt Priority Register 53
0x335
8
read-write
n
0x0
0x0
PRI_53
PRI_53
0
8
IPR54
IPR54
Interrupt Priority Register 54
0x336
8
read-write
n
0x0
0x0
PRI_54
PRI_54
0
8
IPR55
IPR55
Interrupt Priority Register 55
0x337
8
read-write
n
0x0
0x0
PRI_55
PRI_55
0
8
IPR56
IPR56
Interrupt Priority Register 56
0x338
8
read-write
n
0x0
0x0
PRI_56
PRI_56
0
8
IPR57
IPR57
Interrupt Priority Register 57
0x339
8
read-write
n
0x0
0x0
PRI_57
PRI_57
0
8
IPR58
IPR58
Interrupt Priority Register 58
0x33A
8
read-write
n
0x0
0x0
PRI_58
PRI_58
0
8
IPR59
IPR59
Interrupt Priority Register 59
0x33B
8
read-write
n
0x0
0x0
PRI_59
PRI_59
0
8
IPR6
IPR6
Interrupt Priority Register 6
0x306
8
read-write
n
0x0
0x0
PRI_06
PRI_06
0
8
IPR60
IPR60
Interrupt Priority Register 60
0x33C
8
read-write
n
0x0
0x0
PRI_60
PRI_60
0
8
IPR61
IPR61
Interrupt Priority Register 61
0x33D
8
read-write
n
0x0
0x0
PRI_61
PRI_61
0
8
IPR62
IPR62
Interrupt Priority Register 62
0x33E
8
read-write
n
0x0
0x0
PRI_62
PRI_62
0
8
IPR63
IPR63
Interrupt Priority Register 63
0x33F
8
read-write
n
0x0
0x0
PRI_63
PRI_63
0
8
IPR64
IPR64
Interrupt Priority Register 64
0x340
8
read-write
n
0x0
0x0
PRI_64
PRI_64
0
8
IPR65
IPR65
Interrupt Priority Register 65
0x341
8
read-write
n
0x0
0x0
PRI_65
PRI_65
0
8
IPR66
IPR66
Interrupt Priority Register 66
0x342
8
read-write
n
0x0
0x0
PRI_66
PRI_66
0
8
IPR67
IPR67
Interrupt Priority Register 67
0x343
8
read-write
n
0x0
0x0
PRI_67
PRI_67
0
8
IPR7
IPR7
Interrupt Priority Register 7
0x307
8
read-write
n
0x0
0x0
PRI_07
PRI_07
0
8
IPR8
IPR8
Interrupt Priority Register 8
0x308
8
read-write
n
0x0
0x0
PRI_08
PRI_08
0
8
IPR9
IPR9
Interrupt Priority Register 9
0x309
8
read-write
n
0x0
0x0
PRI_09
PRI_09
0
8
ISER
ISER
Interrupt Set Enable Register
0x0
32
read-write
n
0x0
0x0
SETENA
SETENA
0
32
ISPR
ISPR
Interrupt Set-Pending Register
0x100
32
read-write
n
0x0
0x0
SETPEND
SETPEND
0
32
STIR
STIR
Software Trigger Interrupt Register
0xE00
32
write-only
n
0x0
0x0
STIR
STIR
0
32
PMU
Power management unit
PMU
0x0
0x0
0x400
registers
n
CS
CS
power control/status register
0x4
32
read-write
n
0x0
0x0
LVDF
Low Voltage Detector Status Flag
2
1
read-only
STBF
Standby flag
1
1
read-only
WUF
Wakeup flag
0
1
read-only
WUPEN
Enable WKUP pin
8
1
read-write
CTL
CTL
power control register
0x0
32
read-write
n
0x0
0x0
BKPWEN
Backup Domain Write Enable
8
1
LDOLP
LDO Low Power Mode
0
1
LVDEN
Low Voltage Detector Enable
4
1
LVDT
Low Voltage Detector Threshold
5
3
STBMOD
Standby Mode
1
1
STBRST
Standby Flag Reset
3
1
WURST
Wakeup Flag Reset
2
1
RCU
Reset and clock unit
RCU
0x0
0x0
0x400
registers
n
RCU
5
AHBEN
AHBEN
AHB enable register
0x14
32
read-write
n
0x0
0x0
CRCEN
CRC clock enable
6
1
DMA0EN
DMA0 clock enable
0
1
DMA1EN
DMA1 clock enable
1
1
EXMCEN
EXMC clock enable
8
1
FMCSPEN
FMC clock enable when sleep mode
4
1
SDIOEN
SDIO clock enable
10
1
SRAMSPEN
SRAM interface clock enable when sleep mode
2
1
APB1EN
APB1EN
APB1 clock enable register (RCU_APB1EN)
0x1C
32
read-write
n
0x0
0x0
BKPIEN
Backup interface clock enable
27
1
CAN0EN
CAN0 clock enable
25
1
DACEN
DAC clock enable
29
1
I2C0EN
I2C0 clock enable
21
1
I2C1EN
I2C1 clock enable
22
1
PMUEN
Power control clock enable
28
1
SPI1EN
SPI1 clock enable
14
1
SPI2EN
SPI2 clock enable
15
1
TIMER11EN
TIMER11 timer clock enable
6
1
TIMER12EN
TIMER12 timer clock enable
7
1
TIMER13EN
TIMER13 timer clock enable
8
1
TIMER1EN
TIMER1 timer clock enable
0
1
TIMER2EN
TIMER2 timer clock enable
1
1
TIMER3EN
TIMER3 timer clock enable
2
1
TIMER4EN
TIMER4 timer clock enable
3
1
TIMER5EN
TIMER5 timer clock enable
4
1
TIMER6EN
TIMER6 timer clock enable
5
1
UART3EN
UART3 clock enable
19
1
UART4EN
UART4 clock enable
20
1
USART1EN
USART1 clock enable
17
1
USART2EN
USART2 clock enable
18
1
USBDEN
USBD clock enable
23
1
WWDGTEN
Window watchdog timer clock enable
11
1
APB1RST
APB1RST
APB1 reset register (RCU_APB1RST)
0x10
32
read-write
n
0x0
0x0
BKPIRST
Backup interface reset
27
1
CAN0RST
CAN0 reset
25
1
DACRST
DAC reset
29
1
I2C0RST
I2C0 reset
21
1
I2C1RST
I2C1 reset
22
1
PMURST
Power control reset
28
1
SPI1RST
SPI1 reset
14
1
SPI2RST
SPI2 reset
15
1
TIMER11RST
TIMER11 timer reset
6
1
TIMER12RST
TIMER12 timer reset
7
1
TIMER13RST
TIMER13 timer reset
8
1
TIMER1RST
TIMER1 timer reset
0
1
TIMER2RST
TIMER2 timer reset
1
1
TIMER3RST
TIMER3 timer reset
2
1
TIMER4RST
TIMER4 timer reset
3
1
TIMER5RST
TIMER5 timer reset
4
1
TIMER6RST
TIMER6 timer reset
5
1
UART3RST
UART3 reset
19
1
UART4RST
UART4 reset
20
1
USART1RST
USART1 reset
17
1
USART2RST
USART2 reset
18
1
USBDRST
USBD reset
23
1
WWDGTRST
Window watchdog timer reset
11
1
APB2EN
APB2EN
APB2 clock enable register (RCU_APB2EN)
0x18
32
read-write
n
0x0
0x0
ADC0EN
ADC0 clock enable
9
1
ADC1EN
ADC1 clock enable
10
1
ADC2EN
ADC2 clock enable
15
1
AFEN
Alternate function IO clock enable
0
1
PAEN
GPIO port A clock enable
2
1
PBEN
GPIO port B clock enable
3
1
PCEN
GPIO port C clock enable
4
1
PDEN
GPIO port D clock enable
5
1
PEEN
GPIO port E clock enable
6
1
PFEN
GPIO port F clock enable
7
1
PGEN
GPIO port G clock enable
8
1
SPI0EN
SPI0 clock enable
12
1
TIMER0EN
TIMER0 clock enable
11
1
TIMER10EN
TIMER10 clock enable
21
1
TIMER7EN
TIMER7 clock enable
13
1
TIMER8EN
TIMER8 clock enable
19
1
TIMER9EN
TIMER9 clock enable
20
1
USART0EN
USART0 clock enable
14
1
APB2RST
APB2RST
APB2 reset register (RCU_APB2RST)
0xC
32
read-write
n
0x0
0x0
ADC0RST
ADC0 reset
9
1
ADC1RST
ADC1 reset
10
1
ADC2RST
ADC2 Reset
15
1
AFRST
Alternate function I/O reset
0
1
PARST
GPIO port A reset
2
1
PBRST
GPIO port B reset
3
1
PCRST
GPIO port C reset
4
1
PDRST
GPIO port D reset
5
1
PERST
GPIO port E reset
6
1
PFRST
GPIO portF reset
7
1
PGRST
GPIO port G reset
8
1
SPI0RST
SPI0 reset
12
1
TIMER0RST
Timer 0 reset
11
1
TIMER10RST
TIMER10 Reset
21
1
TIMER7RST
Timer 7 reset
13
1
TIMER8RST
TIMER8 Reset
19
1
TIMER9RST
TIMER9 Reset
20
1
USART0RST
USART0 Reset
14
1
BDCTL
BDCTL
Backup domain control register (RCU_BDCTL)
0x20
32
read-write
n
0x0
0x0
BKPRST
Backup domain reset
16
1
read-write
LXTALBPS
LXTAL bypass mode enable
2
1
read-write
LXTALEN
LXTAL enable
0
1
read-write
LXTALSTB
External low-speed oscillator stabilization
1
1
read-only
RTCEN
RTC clock enable
15
1
read-write
RTCSRC
RTC clock entry selection
8
2
read-write
CFG0
CFG0
Clock configuration register 0 (RCU_CFG0)
0x4
32
read-write
n
0x0
0x0
ADCPSC_1_0
ADC clock prescaler selection
14
2
read-write
ADCPSC_2
Bit 2 of ADCPSC
28
1
read-write
AHBPSC
AHB prescaler selection
4
4
read-write
APB1PSC
APB1 prescaler selection
8
3
read-write
APB2PSC
APB2 prescaler selection
11
3
read-write
CKOUT0SEL
CKOUT0 Clock Source Selection
24
3
read-write
PLLMF_3_0
The PLL clock multiplication factor
18
4
read-write
PLLMF_4
Bit 4 of PLLMF
27
1
read-write
PLLSEL
PLL Clock Source Selection
16
1
read-write
PREDV0
PREDV0 division factor
17
1
read-write
SCS
System clock switch
0
2
read-write
SCSS
System clock switch status
2
2
read-only
USBDPSC
USBFS clock prescaler selection
22
2
read-write
CTL
CTL
Control register
0x0
32
read-write
n
0x0
0x0
CKMEN
HXTAL Clock Monitor Enable
19
1
read-write
HXTALBPS
External crystal oscillator (HXTAL) clock bypass mode enable
18
1
read-write
HXTALEN
External High Speed oscillator Enable
16
1
read-write
HXTALSTB
External crystal oscillator (HXTAL) clock stabilization flag
17
1
read-only
IRC8MADJ
Internal 8MHz RC Oscillator clock trim adjust value
3
5
read-write
IRC8MCALIB
Internal 8MHz RC Oscillator calibration value register
8
8
read-only
IRC8MEN
Internal 8MHz RC oscillator Enable
0
1
read-write
IRC8MSTB
IRC8M Internal 8MHz RC Oscillator stabilization Flag
1
1
read-only
PLLEN
PLL enable
24
1
read-write
PLLSTB
PLL Clock Stabilization Flag
25
1
read-only
DSV
DSV
Deep sleep mode Voltage register
0x34
32
read-write
n
0x0
0x0
DSLPVS
Deep-sleep mode voltage select
0
3
read-write
INT
INT
Clock interrupt register (RCU_INT)
0x8
32
read-write
n
0x0
0x0
CKMIC
HXTAL Clock Stuck Interrupt Clear
23
1
write-only
CKMIF
HXTAL Clock Stuck Interrupt Flag
7
1
read-only
HXTALSTBIC
HXTAL Stabilization Interrupt Clear
19
1
write-only
HXTALSTBIE
HXTAL Stabilization Interrupt Enable
11
1
read-write
HXTALSTBIF
HXTAL stabilization interrupt flag
3
1
read-only
IRC40KSTBIC
IRC40K Stabilization Interrupt Clear
16
1
write-only
IRC40KSTBIE
IRC40K Stabilization interrupt enable
8
1
read-write
IRC40KSTBIF
IRC40K stabilization interrupt flag
0
1
read-only
IRC8MSTBIC
IRC8M Stabilization Interrupt Clear
18
1
write-only
IRC8MSTBIE
IRC8M Stabilization Interrupt Enable
10
1
read-write
IRC8MSTBIF
IRC8M stabilization interrupt flag
2
1
read-only
LXTALSTBIC
LXTAL Stabilization Interrupt Clear
17
1
write-only
LXTALSTBIE
LXTAL Stabilization Interrupt Enable
9
1
read-write
LXTALSTBIF
LXTAL stabilization interrupt flag
1
1
read-only
PLLSTBIC
PLL stabilization Interrupt Clear
20
1
write-only
PLLSTBIE
PLL Stabilization Interrupt Enable
12
1
read-write
PLLSTBIF
PLL stabilization interrupt flag
4
1
read-only
RSTSCK
RSTSCK
Reset source /clock register (RCU_RSTSCK)
0x24
32
read-write
n
0x0
0x0
EPRSTF
External PIN reset flag
26
1
read-only
FWDGTRSTF
Free Watchdog timer reset flag
29
1
read-only
IRC40KEN
IRC40K enable
0
1
read-write
IRC40KSTB
IRC40K stabilization
1
1
read-only
LPRSTF
Low-power reset flag
31
1
read-only
PORRSTF
Power reset flag
27
1
read-only
RSTFC
Reset flag clear
24
1
read-write
SWRSTF
Software reset flag
28
1
read-only
WWDGTRSTF
Window watchdog timer reset flag
30
1
read-only
RTC
Real-time clock
RTC
0x0
0x0
0x400
registers
n
RTC
3
RTC_Alarm
41
ALRMH
ALRMH
Alarm high register
0x20
32
write-only
n
0x0
0x0
ALRM
Alarm value high
0
16
ALRML
ALRML
RTC alarm low register
0x24
32
write-only
n
0x0
0x0
ALRM
alarm value low
0
16
CNTH
CNTH
RTC counter high register
0x18
32
read-write
n
0x0
0x0
CNT
RTC counter value high
0
16
CNTL
CNTL
RTC counter low register
0x1C
32
read-write
n
0x0
0x0
CNT
RTC counter value low
0
16
CTL
CTL
control register
0x4
32
read-write
n
0x0
0x0
ALRMIF
Alarm interrupt flag
1
1
CMF
Configuration mode flag
4
1
LWOFF
Last write operation finished flag
5
1
OVIF
Overflow interrupt flag
2
1
RSYNF
Registers synchronized flag
3
1
SCIF
Sencond interrupt flag
0
1
DIVH
DIVH
RTC divider high register
0x10
32
read-only
n
0x0
0x0
DIV
RTC divider value high
0
4
DIVL
DIVL
RTC divider low register
0x14
32
read-only
n
0x0
0x0
DIV
RTC divider value low
0
16
INTEN
INTEN
RTC interrupt enable register
0x0
32
read-write
n
0x0
0x0
ALRMIE
Alarm interrupt enable
1
1
OVIE
Overflow interrupt enable
2
1
SCIE
Second interrupt
0
1
PSCH
PSCH
RTC prescaler high register
0x8
32
read-write
n
0x0
0x0
PSC
RTC prescaler value high
0
4
write
PSCL
PSCL
RTC prescaler low register
0xC
32
read-write
n
0x0
0x0
PSC
RTC prescaler value low
0
16
write
SDIO
Secure digital input/output interface
SDIO
0x0
0x0
0x400
registers
n
SDIO
49
CLKCTL
CLKCTL
Clock control register
0x4
32
read-write
n
0x0
0x0
BUSMODE
SDIO card bus mode control bit
11
2
CLKBYP
Clock bypass enable bit
10
1
CLKEDGE
SDIO_CLK clock edge selection bit
13
1
CLKEN
SDIO_CLK clock output enable bit
8
1
CLKPWRSAV
SDIO_CLK clock dynamic switch on/off for power saving
9
1
DIV
Clock division
0
8
HWCLKEN
Hardware Clock Control enable bit
14
1
CMDAGMT
CMDAGMT
Command argument register
0x8
32
read-write
n
0x0
0x0
CMDAGMT
SDIO card command argument
0
32
CMDCTL
CMDCTL
Command control register
0xC
32
read-write
n
0x0
0x0
ATAEN
CE-ATA command enable(CE-ATA only)
14
1
CMDIDX
Command index
0
6
CMDRESP
Command response type bits
6
2
CSMEN
Command state machine (CSM) enable bit
10
1
ENCMDC
CMD completion signal enabled (CE-ATA only)
12
1
INTWAIT
Interrupt wait instead of timeout
8
1
NINTEN
No CE-ATA Interrupt (CE-ATA only)
13
1
SUSPEND
SD I/O suspend command(SD I/O only)
11
1
WAITDEND
Waits for ends of data transfer
9
1
DATACNT
DATACNT
Data counter register
0x30
32
read-only
n
0x0
0x0
DATACNT
Data count value
0
25
DATACTL
DATACTL
Data control register
0x2C
32
read-write
n
0x0
0x0
BLKSZ
Data block size
4
4
DATADIR
Data transfer direction
1
1
DATAEN
Data transfer enabled bit
0
1
DMAEN
DMA enable bit
3
1
IOEN
SD I/O specific function enable
11
1
RWEN
Read wait mode enabled
8
1
RWSTOP
Read wait stop
9
1
RWTYPE
Read wait type
10
1
TRANSMOD
Data transfer mode
2
1
DATALEN
DATALEN
Data length register
0x28
32
read-write
n
0x0
0x0
DATALEN
Data transfer length
0
25
DATATO
DATATO
Data timeout register
0x24
32
read-write
n
0x0
0x0
DATATO
Data timeout period
0
32
FIFO
FIFO
FIFO data register
0x80
32
read-write
n
0x0
0x0
FIFODT
Receive FIFO data or transmit FIFO data
0
32
FIFOCNT
FIFOCNT
FIFO counter register
0x48
32
read-only
n
0x0
0x0
FIFOCNT
FIFO counter
0
24
INTC
INTC
Interrupt clear register
0x38
32
write-only
n
0x0
0x0
ATAENDC
ATAEND flag clear bit
23
1
CCRCERRC
CCRCERR flag clear bit
0
1
CMDRECVC
CMDRECV flag clear bit
6
1
CMDSENDC
CMDSEND flag clear bit
7
1
CMDTMOUTC
CMDTMOUT flag clear bit
2
1
DTBLKENDC
DTBLKEND flag clear bit
10
1
DTCRCERRC
DTCRCERR flag clear bit
1
1
DTENDC
DTEND flag clear bit
8
1
DTTMOUTC
DTTMOUT flag clear bit
3
1
RXOREC
RXORE flag clear bit
5
1
SDIOINTC
SDIOINT flag clear bit
22
1
STBITEC
STBITE flag clear bit
9
1
TXUREC
TXURE flag clear bit
4
1
INTEN
INTEN
Interrupt enable register
0x3C
32
read-write
n
0x0
0x0
ATAENDIE
CE-ATA command completion signal received interrupt enable
23
1
CCRCERRIE
Command response CRC fail interrupt enable
0
1
CMDRECVIE
Command response received interrupt enable
6
1
CMDRUNIE
Command transmission interrupt enable
11
1
CMDSENDIE
Command sent interrupt enable
7
1
CMDTMOUTIE
Command response timeout interrupt enable
2
1
DTBLKENDIE
Data block end interrupt enable
10
1
DTCRCERRIE
Data CRC fail interrupt enable
1
1
DTENDIE
Data end interrupt enable
8
1
DTTMOUTIE
Data timeout interrupt enable
3
1
RFEIE
Receive FIFO empty interrupt enable
19
1
RFFIE
Receive FIFO full interrupt enable
17
1
RFHIE
Receive FIFO half full interrupt enable
15
1
RXDTVALIE
Data valid in receive FIFO interrupt enable
21
1
RXOREIE
Received FIFO overrun error interrupt enable
5
1
RXRUNIE
Data reception interrupt enable
13
1
SDIOINTIE
SD I/O interrupt received interrupt enable
22
1
STBITEIE
Start bit error interrupt enable
9
1
TFEIE
Transmit FIFO empty interrupt enable
18
1
TFFIE
Transmit FIFO full interrupt enable
16
1
TFHIE
Transmit FIFO half empty interrupt enable
14
1
TXDTVALIE
Data valid in transmit FIFO interrupt enable
20
1
TXRUNIE
Data transmission interrupt enable
12
1
TXUREIE
Transmit FIFO underrun error interrupt enable
4
1
PWRCTL
PWRCTL
Power control register
0x0
32
read-write
n
0x0
0x0
PWRCTL
SDIO power control bits
0
2
RESP0
RESP0
Response register 0
0x14
32
read-only
n
0x0
0x0
RESP0
Card state
0
32
RESP1
RESP1
Response register 1
0x18
32
read-only
n
0x0
0x0
RESP1
Card state
0
32
RESP2
RESP2
Response register 2
0x1C
32
read-only
n
0x0
0x0
RESP2
Card state
0
32
RESP3
RESP3
Response register 3
0x20
32
read-only
n
0x0
0x0
RESP3
Response register 3
0
32
RSPCMDIDX
RSPCMDIDX
Command index response register
0x10
32
read-only
n
0x0
0x0
RSPCMDIDX
Last response command index
0
6
STAT
STAT
Status register
0x34
32
read-only
n
0x0
0x0
ATAEND
CE-ATA command completion signal received
23
1
CCRCERR
Command response received
0
1
CMDRECV
Command response received
6
1
CMDRUN
Command transmission in progress
11
1
CMDSEND
Command sent
7
1
CMDTMOUT
Command response timeout
2
1
DTBLKEND
Data block sent/received
10
1
DTCRCERR
Data block sent/received
1
1
DTEND
Data end
8
1
DTTMOUT
Data timeout
3
1
RFE
Receive FIFO is empty
19
1
RFF
Receive FIFO is full
17
1
RFH
Receive FIFO is half full
15
1
RXDTVAL
Data is valid in receive FIFO
21
1
RXORE
Received FIFO overrun error occurs
5
1
RXRUN
Data reception in progress
13
1
SDIOINT
SD I/O interrupt received
22
1
STBITE
Start bit error in the bus
9
1
TFE
Transmit FIFO is empty
18
1
TFF
Transmit FIFO is full
16
1
TFH
Transmit FIFO is half empty
14
1
TXDTVAL
Data is valid in transmit FIFO
20
1
TXRUN
Data transmission in progress
12
1
TXURE
Transmit FIFO underrun error occurs
4
1
SPI0
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI0
35
CRCPOLY
CRCPOLY
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CPR
CRC polynomial register
0
16
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
BDEN
Bidirectional enable
15
1
BDOEN
Bidirectional Transmit output enable
14
1
CKPH
Clock Phase Selection
0
1
CKPL
Clock polarity Selection
1
1
CRCEN
CRC Calculation Enable
13
1
CRCNT
CRC Next Transfer
12
1
FF16
Data frame format
11
1
LF
LSB First Mode
7
1
MSTMOD
Master Mode Enable
2
1
PSC
Master Clock Prescaler Selection
3
3
RO
Receive only
10
1
SPIEN
SPI enable
6
1
SWNSS
NSS Pin Selection In NSS Software Mode
8
1
SWNSSEN
NSS Software Mode Selection
9
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
DMAREN
Rx buffer DMA enable
0
1
DMATEN
Transmit Buffer DMA Enable
1
1
ERRIE
Error interrupt enable
5
1
NSSDRV
Drive NSS Output
2
1
RBNEIE
RX buffer not empty interrupt enable
6
1
TBEIE
Tx buffer empty interrupt enable
7
1
DATA
DATA
data register
0xC
32
read-write
n
0x0
0x0
SPI_DATA
Data transfer register
0
16
I2SCTL
I2SCTL
I2S control register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPL
Idle state clock polarity
3
1
DTLEN
Data length
1
2
I2SEN
I2S Enable
10
1
I2SOPMOD
I2S operation mode
8
2
I2SSEL
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSMOD
PCM frame synchronization mode
7
1
I2SPSC
I2SPSC
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
DIV
Dividing factor for the prescaler
0
8
MCKOEN
I2S_MCK output enable
9
1
OF
Odd factor for the prescaler
8
1
RCRC
RCRC
RX CRC register
0x14
32
read-only
n
0x0
0x0
RCR
RX CRC register
0
16
STAT
STAT
status register
0x8
32
read-write
n
0x0
0x0
CONFERR
SPI Configuration error
5
1
read-only
CRCERR
SPI CRC Error Bit
4
1
read-write
I2SCH
I2S channel side
2
1
read-only
RBNE
Receive Buffer Not Empty
0
1
read-only
RXORERR
Reception Overrun Error Bit
6
1
read-only
TBE
Transmit Buffer Empty
1
1
read-only
TRANS
Transmitting On-going Bit
7
1
read-only
TXURERR
Transmission underrun error bit
3
1
read-only
TCRC
TCRC
TX CRC register
0x18
32
read-only
n
0x0
0x0
TCR
Tx CRC register
0
16
SPI1
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI1
36
CRCPOLY
CRCPOLY
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CPR
CRC polynomial register
0
16
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
BDEN
Bidirectional enable
15
1
BDOEN
Bidirectional Transmit output enable
14
1
CKPH
Clock Phase Selection
0
1
CKPL
Clock polarity Selection
1
1
CRCEN
CRC Calculation Enable
13
1
CRCNT
CRC Next Transfer
12
1
FF16
Data frame format
11
1
LF
LSB First Mode
7
1
MSTMOD
Master Mode Enable
2
1
PSC
Master Clock Prescaler Selection
3
3
RO
Receive only
10
1
SPIEN
SPI enable
6
1
SWNSS
NSS Pin Selection In NSS Software Mode
8
1
SWNSSEN
NSS Software Mode Selection
9
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
DMAREN
Rx buffer DMA enable
0
1
DMATEN
Transmit Buffer DMA Enable
1
1
ERRIE
Error interrupt enable
5
1
NSSDRV
Drive NSS Output
2
1
RBNEIE
RX buffer not empty interrupt enable
6
1
TBEIE
Tx buffer empty interrupt enable
7
1
DATA
DATA
data register
0xC
32
read-write
n
0x0
0x0
SPI_DATA
Data transfer register
0
16
I2SCTL
I2SCTL
I2S control register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPL
Idle state clock polarity
3
1
DTLEN
Data length
1
2
I2SEN
I2S Enable
10
1
I2SOPMOD
I2S operation mode
8
2
I2SSEL
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSMOD
PCM frame synchronization mode
7
1
I2SPSC
I2SPSC
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
DIV
Dividing factor for the prescaler
0
8
MCKOEN
I2S_MCK output enable
9
1
OF
Odd factor for the prescaler
8
1
RCRC
RCRC
RX CRC register
0x14
32
read-only
n
0x0
0x0
RCR
RX CRC register
0
16
STAT
STAT
status register
0x8
32
read-write
n
0x0
0x0
CONFERR
SPI Configuration error
5
1
read-only
CRCERR
SPI CRC Error Bit
4
1
read-write
I2SCH
I2S channel side
2
1
read-only
RBNE
Receive Buffer Not Empty
0
1
read-only
RXORERR
Reception Overrun Error Bit
6
1
read-only
TBE
Transmit Buffer Empty
1
1
read-only
TRANS
Transmitting On-going Bit
7
1
read-only
TXURERR
Transmission underrun error bit
3
1
read-only
TCRC
TCRC
TX CRC register
0x18
32
read-only
n
0x0
0x0
TCR
Tx CRC register
0
16
SPI2
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI2
51
CRCPOLY
CRCPOLY
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CPR
CRC polynomial register
0
16
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
BDEN
Bidirectional enable
15
1
BDOEN
Bidirectional Transmit output enable
14
1
CKPH
Clock Phase Selection
0
1
CKPL
Clock polarity Selection
1
1
CRCEN
CRC Calculation Enable
13
1
CRCNT
CRC Next Transfer
12
1
FF16
Data frame format
11
1
LF
LSB First Mode
7
1
MSTMOD
Master Mode Enable
2
1
PSC
Master Clock Prescaler Selection
3
3
RO
Receive only
10
1
SPIEN
SPI enable
6
1
SWNSS
NSS Pin Selection In NSS Software Mode
8
1
SWNSSEN
NSS Software Mode Selection
9
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
DMAREN
Rx buffer DMA enable
0
1
DMATEN
Transmit Buffer DMA Enable
1
1
ERRIE
Error interrupt enable
5
1
NSSDRV
Drive NSS Output
2
1
RBNEIE
RX buffer not empty interrupt enable
6
1
TBEIE
Tx buffer empty interrupt enable
7
1
DATA
DATA
data register
0xC
32
read-write
n
0x0
0x0
SPI_DATA
Data transfer register
0
16
I2SCTL
I2SCTL
I2S control register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPL
Idle state clock polarity
3
1
DTLEN
Data length
1
2
I2SEN
I2S Enable
10
1
I2SOPMOD
I2S operation mode
8
2
I2SSEL
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSMOD
PCM frame synchronization mode
7
1
I2SPSC
I2SPSC
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
DIV
Dividing factor for the prescaler
0
8
MCKOEN
I2S_MCK output enable
9
1
OF
Odd factor for the prescaler
8
1
RCRC
RCRC
RX CRC register
0x14
32
read-only
n
0x0
0x0
RCR
RX CRC register
0
16
STAT
STAT
status register
0x8
32
read-write
n
0x0
0x0
CONFERR
SPI Configuration error
5
1
read-only
CRCERR
SPI CRC Error Bit
4
1
read-write
I2SCH
I2S channel side
2
1
read-only
RBNE
Receive Buffer Not Empty
0
1
read-only
RXORERR
Reception Overrun Error Bit
6
1
read-only
TBE
Transmit Buffer Empty
1
1
read-only
TRANS
Transmitting On-going Bit
7
1
read-only
TXURERR
Transmission underrun error bit
3
1
read-only
TCRC
TCRC
TX CRC register
0x18
32
read-only
n
0x0
0x0
TCR
Tx CRC register
0
16
TIMER0
Advanced-timers
TIMER
0x0
0x0
0x400
registers
n
TIMER0_BRK
24
TIMER0_UP
25
TIMER0_TRG_CMT
26
TIMER0_Channel
27
CAR
CAR
Counter auto reload register
0x2C
32
read-write
n
0x0
0x0
CARL
Counter auto reload value
0
16
CCHP
CCHP
channel complementary protection register
0x44
32
read-write
n
0x0
0x0
BRKEN
Break enable
12
1
BRKP
Break polarity
13
1
DTCFG
Dead time configure
0
8
IOS
Idle mode off-state configure
10
1
OAEN
Output automatic enable
14
1
POEN
Primary output enable
15
1
PROT
Complementary register protect control
8
2
ROS
Run mode off-state configure
11
1
CH0CV
CH0CV
Channel 0 capture/compare value register
0x34
32
read-write
n
0x0
0x0
CH0VAL
Capture or compare value of channel0
0
16
CH1CV
CH1CV
Channel 1 capture/compare value register
0x38
32
read-write
n
0x0
0x0
CH1VAL
Capture or compare value of channel1
0
16
CH2CV
CH2CV
Channel 2 capture/compare value register
0x3C
32
read-write
n
0x0
0x0
CH2VAL
Capture or compare value of channel 2
0
16
CH3CV
CH3CV
Channel 3 capture/compare value register
0x40
32
read-write
n
0x0
0x0
CH3VAL
Capture or compare value of channel 3
0
16
CHCTL0_Input
CHCTL0_Input
Channel control register 0 (input mode)
CHCTL0_Output
0x18
32
read-write
n
0x0
0x0
CH0CAPFLT
Channel 0 input capture filter control
4
4
CH0CAPPSC
Channel 0 input capture prescaler
2
2
CH0MS
Channel 0 mode selection
0
2
CH1CAPFLT
Channel 1 input capture filter control
12
4
CH1CAPPSC
Channel 1 input capture prescaler
10
2
CH1MS
Channel 1 mode selection
8
2
CHCTL0_Output
CHCTL0_Output
Channel control register 0 (output mode)
0x18
32
read-write
n
0x0
0x0
CH0COMCEN
Channel 0 output compare clear enable
7
1
CH0COMCTL
Channel 0 compare output control
4
3
CH0COMFEN
Channel 0 output compare fast enable
2
1
CH0COMSEN
Channel 0 compare output shadow enable
3
1
CH0MS
Channel 0 I/O mode selection
0
2
CH1COMCEN
Channel 1 output compare clear enable
15
1
CH1COMCTL
Channel 1 compare output control
12
3
CH1COMFEN
Channel 1 output compare fast enable
10
1
CH1COMSEN
Channel 1 output compare shadow enable
11
1
CH1MS
Channel 1 mode selection
8
2
CHCTL1_Input
CHCTL1_Input
Channel control register 1 (input mode)
CHCTL1_Output
0x1C
32
read-write
n
0x0
0x0
CH2CAPFLT
Channel 2 input capture filter control
4
4
CH2CAPPSC
Channel 2 input capture prescaler
2
2
CH2MS
Channel 2 mode selection
0
2
CH3CAPFLT
Channel 3 input capture filter control
12
4
CH3CAPPSC
Channel 3 input capture prescaler
10
2
CH3MS
Channel 3 mode selection
8
2
CHCTL1_Output
CHCTL1_Output
Channel control register 1 (output mode)
0x1C
32
read-write
n
0x0
0x0
CH2COMCEN
Channel 2 output compare clear enable
7
1
CH2COMCTL
Channel 2 compare output control
4
3
CH2COMFEN
Channel 2 output compare fast enable
2
1
CH2COMSEN
Channel 2 compare output shadow enable
3
1
CH2MS
Channel 2 I/O mode selection
0
2
CH3COMCEN
Channel 3 output compare clear enable
15
1
CH3COMCTL
Channel 3 compare output control
12
3
CH3COMFEN
Channel 3 output compare fast enable
10
1
CH3COMSEN
Channel 3 output compare shadow enable
11
1
CH3MS
Channel 3 mode selection
8
2
CHCTL2
CHCTL2
Channel control register 2
0x20
32
read-write
n
0x0
0x0
CH0EN
Channel 0 capture/compare function enable
0
1
CH0NEN
Channel 0 complementary output enable
2
1
CH0NP
Channel 0 complementary output polarity
3
1
CH0P
Channel 0 capture/compare function polarity
1
1
CH1EN
Channel 1 capture/compare function enable
4
1
CH1NEN
Channel 1 complementary output enable
6
1
CH1NP
Channel 1 complementary output polarity
7
1
CH1P
Channel 1 capture/compare function polarity
5
1
CH2EN
Channel 2 capture/compare function enable
8
1
CH2NEN
Channel 2 complementary output enable
10
1
CH2NP
Channel 2 complementary output polarity
11
1
CH2P
Channel 2 capture/compare function polarity
9
1
CH3EN
Channel 3 capture/compare function enable
12
1
CH3P
Channel 3 capture/compare function polarity
13
1
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
current counter value
0
16
CREP
CREP
Counter repetition register
0x30
32
read-write
n
0x0
0x0
CREP
Counter repetition value
0
8
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
ARSE
Auto-reload shadow enable
7
1
CAM
Counter aligns mode selection
5
2
CEN
Counter enable
0
1
CKDIV
Clock division
8
2
DIR
Direction
4
1
SPM
Single pulse mode
3
1
UPDIS
Update disable
1
1
UPS
Update source
2
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
CCSE
Commutation control shadow enable
0
1
CCUC
Commutation control shadow register update control
2
1
DMAS
DMA request source selection
3
1
ISO0
Idle state of channel 0 output
8
1
ISO0N
Idle state of channel 0 complementary output
9
1
ISO1
Idle state of channel 1 output
10
1
ISO1N
Idle state of channel 1 complementary output
11
1
ISO2
Idle state of channel 2 output
12
1
ISO2N
Idle state of channel 2 complementary output
13
1
ISO3
Idle state of channel 3 output
14
1
MMC
Master mode control
4
3
TI0S
Channel 0 trigger input selection
7
1
DMACFG
DMACFG
DMA configuration register
0x48
32
read-write
n
0x0
0x0
DMATA
DMA transfer access start address
0
5
DMATC
DMA transfer count
8
5
DMAINTEN
DMAINTEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BRKIE
Break interrupt enable
7
1
CH0DEN
Channel 0 capture/compare DMA request enable
9
1
CH0IE
Channel 0 capture/compare interrupt enable
1
1
CH1DEN
Channel 1 capture/compare DMA request enable
10
1
CH1IE
Channel 1 capture/compare interrupt enable
2
1
CH2DEN
Channel 2 capture/compare DMA request enable
11
1
CH2IE
Channel 2 capture/compare interrupt enable
3
1
CH3DEN
Channel 3 capture/compare DMA request enable
12
1
CH3IE
Channel 3 capture/compare interrupt enable
4
1
CMTDEN
Commutation DMA request enable
13
1
CMTIE
commutation interrupt enable
5
1
TRGDEN
Trigger DMA request enable
14
1
TRGIE
Trigger interrupt enable
6
1
UPDEN
Update DMA request enable
8
1
UPIE
Update interrupt enable
0
1
DMATB
DMATB
DMA transfer buffer register
0x4C
32
read-write
n
0x0
0x0
DMATB
DMA transfer buffer
0
16
INTF
INTF
Interrupt flag register
0x10
32
read-write
n
0x0
0x0
BRKIF
Break interrupt flag
7
1
CH0IF
Channel 0 capture/compare interrupt flag
1
1
CH0OF
Channel 0 over capture flag
9
1
CH1IF
Channel 1 capture/compare interrupt flag
2
1
CH1OF
Channel 1 over capture flag
10
1
CH2IF
Channel 2 capture/compare interrupt flag
3
1
CH2OF
Channel 2 over capture flag
11
1
CH3IF
Channel 3 capture/compare interrupt flag
4
1
CH3OF
Channel 3 over capture flag
12
1
CMTIF
Channel commutation interrupt flag
5
1
TRGIF
Trigger interrupt flag
6
1
UPIF
Update interrupt flag
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value of the counter clock
0
16
SMCFG
SMCFG
slave mode configuration register
0x8
32
read-write
n
0x0
0x0
ETFC
External trigger filter control
8
4
ETP
External trigger polarity
15
1
ETPSC
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMC
Slave mode selection
0
3
SMC1
Part of SMC for enable External clock mode1
14
1
TRGS
Trigger selection
4
3
SWEVG
SWEVG
Software event generation register
0x14
32
write-only
n
0x0
0x0
BRKG
Break event generation
7
1
CH0G
Channel 0 capture or compare event generation
1
1
CH1G
Channel 1 capture or compare event generation
2
1
CH2G
Channel 2 capture or compare event generation
3
1
CH3G
Channel 3 capture or compare event generation
4
1
CMTG
Channel commutation event generation
5
1
TRGG
Trigger event generation
6
1
UPG
Update event generation
0
1
TIMER1
General-purpose-timers
TIMER
0x0
0x0
0x400
registers
n
TIMER1
28
CAR
CAR
Counter auto reload register
0x2C
32
read-write
n
0x0
0x0
CARL
Counter auto reload value
0
16
CH0CV
CH0CV
Channel 0 capture/compare value register
0x34
32
read-write
n
0x0
0x0
CH0VAL
Capture or compare value of channel 0
0
16
CH1CV
CH1CV
Channel 1 capture/compare value register
0x38
32
read-write
n
0x0
0x0
CH1VAL
Capture or compare value of channel1
0
16
CH2CV
CH2CV
Channel 2 capture/compare value register
0x3C
32
read-write
n
0x0
0x0
CH2VAL
Capture or compare value of channel 2
0
16
CH3CV
CH3CV
Channel 3 capture/compare value register
0x40
32
read-write
n
0x0
0x0
CH3VAL
Capture or compare value of channel 3
0
16
CHCTL0_Input
CHCTL0_Input
Channel control register 0 (input mode)
CHCTL0_Output
0x18
32
read-write
n
0x0
0x0
CH0CAPFLT
Channel 0 input capture filter control
4
4
CH0CAPPSC
Channel 0 input capture prescaler
2
2
CH0MS
Channel 0 mode selection
0
2
CH1CAPFLT
Channel 1 input capture filter control
12
4
CH1CAPPSC
Channel 1 input capture prescaler
10
2
CH1MS
Channel 1 mode selection
8
2
CHCTL0_Output
CHCTL0_Output
Channel control register 0 (output mode)
0x18
32
read-write
n
0x0
0x0
CH0COMCEN
Channel 0 output compare clear enable
7
1
CH0COMCTL
Channel 0 compare output control
4
3
CH0COMFEN
Channel 0 output compare fast enable
2
1
CH0COMSEN
Channel 0 compare output shadow enable
3
1
CH0MS
Channel 0 I/O mode selection
0
2
CH1COMCEN
Channel 1 output compare clear enable
15
1
CH1COMCTL
Channel 1 compare output control
12
3
CH1COMFEN
Channel 1 output compare fast enable
10
1
CH1COMSEN
Channel 1 output compare shadow enable
11
1
CH1MS
Channel 1 mode selection
8
2
CHCTL1_Input
CHCTL1_Input
Channel control register 1 (input mode)
CHCTL1_Output
0x1C
32
read-write
n
0x0
0x0
CH2CAPFLT
Channel 2 input capture filter control
4
4
CH2CAPPSC
Channel 2 input capture prescaler
2
2
CH2MS
Channel 2 mode selection
0
2
CH3CAPFLT
Channel 3 input capture filter control
12
4
CH3CAPPSC
Channel 3 input capture prescaler
10
2
CH3MS
Channel 3 mode selection
8
2
CHCTL1_Output
CHCTL1_Output
Channel control register 1 (output mode)
0x1C
32
read-write
n
0x0
0x0
CH2COMCEN
Channel 2 output compare clear enable
7
1
CH2COMCTL
Channel 2 compare output control
4
3
CH2COMFEN
Channel 2 output compare fast enable
2
1
CH2COMSEN
Channel 2 compare output shadow enable
3
1
CH2MS
Channel 2 I/O mode selection
0
2
CH3COMCEN
Channel 3 output compare clear enable
15
1
CH3COMCTL
Channel 3 compare output control
12
3
CH3COMFEN
Channel 3 output compare fast enable
10
1
CH3COMSEN
Channel 3 output compare shadow enable
11
1
CH3MS
Channel 3 mode selection
8
2
CHCTL2
CHCTL2
Channel control register 2
0x20
32
read-write
n
0x0
0x0
CH0EN
Channel 0 capture/compare function enable
0
1
CH0P
Channel 0 capture/compare function polarity
1
1
CH1EN
Channel 1 capture/compare function enable
4
1
CH1P
Channel 1 capture/compare function polarity
5
1
CH2EN
Channel 2 capture/compare function enable
8
1
CH2P
Channel 2 capture/compare function polarity
9
1
CH3EN
Channel 3 capture/compare function enable
12
1
CH3P
Channel 3 capture/compare function polarity
13
1
CNT
CNT
Counter register
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
ARSE
Auto-reload shadow enable
7
1
CAM
Counter aligns mode selection
5
2
CEN
Counter enable
0
1
CKDIV
Clock division
8
2
DIR
Direction
4
1
SPM
Single pulse mode
3
1
UPDIS
Update disable
1
1
UPS
Update source
2
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
DMAS
DMA request source selection
3
1
MMC
Master mode control
4
3
TI0S
Channel 0 trigger input selection
7
1
DMACFG
DMACFG
DMA configuration register
0x48
32
read-write
n
0x0
0x0
DMATA
DMA transfer access start address
0
5
DMATC
DMA transfer count
8
5
DMAINTEN
DMAINTEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CH0DEN
Channel 0 capture/compare DMA request enable
9
1
CH0IE
Channel 0 capture/compare interrupt enable
1
1
CH1DEN
Channel 1 capture/compare DMA request enable
10
1
CH1IE
Channel 1 capture/compare interrupt enable
2
1
CH2DEN
Channel 2 capture/compare DMA request enable
11
1
CH2IE
Channel 2 capture/compare interrupt enable
3
1
CH3DEN
Channel 3 capture/compare DMA request enable
12
1
CH3IE
Channel 3 capture/compare interrupt enable
4
1
TRGDEN
Trigger DMA request enable
14
1
TRGIE
Trigger interrupt enable
6
1
UPDEN
Update DMA request enable
8
1
UPIE
Update interrupt enable
0
1
DMATB
DMATB
DMA transfer buffer register
0x4C
32
read-write
n
0x0
0x0
DMATB
DMA transfer buffer
0
16
INTF
INTF
interrupt flag register
0x10
32
read-write
n
0x0
0x0
CH0IF
Channel 0 capture/compare interrupt flag
1
1
CH0OF
Channel 0 over capture flag
9
1
CH1IF
Channel 1 capture/compare interrupt flag
2
1
CH1OF
Channel 1 over capture flag
10
1
CH2IF
Channel 2 capture/compare interrupt enable
3
1
CH2OF
Channel 2 over capture flag
11
1
CH3IF
Channel 3 capture/compare interrupt enable
4
1
CH3OF
Channel 3 over capture flag
12
1
TRGIF
Trigger interrupt flag
6
1
UPIF
Update interrupt flag
0
1
PSC
PSC
Prescaler register
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value of the counter clock
0
16
SMCFG
SMCFG
slave mode control register
0x8
32
read-write
n
0x0
0x0
ETFC
External trigger filter control
8
4
ETP
External trigger polarity
15
1
ETPSC
External trigger prescaler
12
2
MSM
Master-slave mode
7
1
SMC
Slave mode control
0
3
SMC1
Part of SMC for enable External clock mode1
14
1
TRGS
Trigger selection
4
3
SWEVG
SWEVG
event generation register
0x14
32
write-only
n
0x0
0x0
CH0G
Channel 0 capture or compare event generation
1
1
CH1G
Channel 1 capture or compare event generation
2
1
CH2G
Channel 2 capture or compare event generation
3
1
CH3G
Channel 3 capture or compare event generation
4
1
TRGG
Trigger event generation
6
1
UPG
Update generation
0
1
TIMER2
General-purpose-timers
TIMER
0x0
0x0
0x400
registers
n
TIMER2
29
CAR
CAR
Counter auto reload register
0x2C
32
read-write
n
0x0
0x0
CARL
Counter auto reload value
0
16
CH0CV
CH0CV
Channel 0 capture/compare value register
0x34
32
read-write
n
0x0
0x0
CH0VAL
Capture or compare value of channel 0
0
16
CH1CV
CH1CV
Channel 1 capture/compare value register
0x38
32
read-write
n
0x0
0x0
CH1VAL
Capture or compare value of channel1
0
16
CH2CV
CH2CV
Channel 2 capture/compare value register
0x3C
32
read-write
n
0x0
0x0
CH2VAL
Capture or compare value of channel 2
0
16
CH3CV
CH3CV
Channel 3 capture/compare value register
0x40
32
read-write
n
0x0
0x0
CH3VAL
Capture or compare value of channel 3
0
16
CHCTL0_Input
CHCTL0_Input
Channel control register 0 (input mode)
CHCTL0_Output
0x18
32
read-write
n
0x0
0x0
CH0CAPFLT
Channel 0 input capture filter control
4
4
CH0CAPPSC
Channel 0 input capture prescaler
2
2
CH0MS
Channel 0 mode selection
0
2
CH1CAPFLT
Channel 1 input capture filter control
12
4
CH1CAPPSC
Channel 1 input capture prescaler
10
2
CH1MS
Channel 1 mode selection
8
2
CHCTL0_Output
CHCTL0_Output
Channel control register 0 (output mode)
0x18
32
read-write
n
0x0
0x0
CH0COMCEN
Channel 0 output compare clear enable
7
1
CH0COMCTL
Channel 0 compare output control
4
3
CH0COMFEN
Channel 0 output compare fast enable
2
1
CH0COMSEN
Channel 0 compare output shadow enable
3
1
CH0MS
Channel 0 I/O mode selection
0
2
CH1COMCEN
Channel 1 output compare clear enable
15
1
CH1COMCTL
Channel 1 compare output control
12
3
CH1COMFEN
Channel 1 output compare fast enable
10
1
CH1COMSEN
Channel 1 output compare shadow enable
11
1
CH1MS
Channel 1 mode selection
8
2
CHCTL1_Input
CHCTL1_Input
Channel control register 1 (input mode)
CHCTL1_Output
0x1C
32
read-write
n
0x0
0x0
CH2CAPFLT
Channel 2 input capture filter control
4
4
CH2CAPPSC
Channel 2 input capture prescaler
2
2
CH2MS
Channel 2 mode selection
0
2
CH3CAPFLT
Channel 3 input capture filter control
12
4
CH3CAPPSC
Channel 3 input capture prescaler
10
2
CH3MS
Channel 3 mode selection
8
2
CHCTL1_Output
CHCTL1_Output
Channel control register 1 (output mode)
0x1C
32
read-write
n
0x0
0x0
CH2COMCEN
Channel 2 output compare clear enable
7
1
CH2COMCTL
Channel 2 compare output control
4
3
CH2COMFEN
Channel 2 output compare fast enable
2
1
CH2COMSEN
Channel 2 compare output shadow enable
3
1
CH2MS
Channel 2 I/O mode selection
0
2
CH3COMCEN
Channel 3 output compare clear enable
15
1
CH3COMCTL
Channel 3 compare output control
12
3
CH3COMFEN
Channel 3 output compare fast enable
10
1
CH3COMSEN
Channel 3 output compare shadow enable
11
1
CH3MS
Channel 3 mode selection
8
2
CHCTL2
CHCTL2
Channel control register 2
0x20
32
read-write
n
0x0
0x0
CH0EN
Channel 0 capture/compare function enable
0
1
CH0P
Channel 0 capture/compare function polarity
1
1
CH1EN
Channel 1 capture/compare function enable
4
1
CH1P
Channel 1 capture/compare function polarity
5
1
CH2EN
Channel 2 capture/compare function enable
8
1
CH2P
Channel 2 capture/compare function polarity
9
1
CH3EN
Channel 3 capture/compare function enable
12
1
CH3P
Channel 3 capture/compare function polarity
13
1
CNT
CNT
Counter register
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
ARSE
Auto-reload shadow enable
7
1
CAM
Counter aligns mode selection
5
2
CEN
Counter enable
0
1
CKDIV
Clock division
8
2
DIR
Direction
4
1
SPM
Single pulse mode
3
1
UPDIS
Update disable
1
1
UPS
Update source
2
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
DMAS
DMA request source selection
3
1
MMC
Master mode control
4
3
TI0S
Channel 0 trigger input selection
7
1
DMACFG
DMACFG
DMA configuration register
0x48
32
read-write
n
0x0
0x0
DMATA
DMA transfer access start address
0
5
DMATC
DMA transfer count
8
5
DMAINTEN
DMAINTEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CH0DEN
Channel 0 capture/compare DMA request enable
9
1
CH0IE
Channel 0 capture/compare interrupt enable
1
1
CH1DEN
Channel 1 capture/compare DMA request enable
10
1
CH1IE
Channel 1 capture/compare interrupt enable
2
1
CH2DEN
Channel 2 capture/compare DMA request enable
11
1
CH2IE
Channel 2 capture/compare interrupt enable
3
1
CH3DEN
Channel 3 capture/compare DMA request enable
12
1
CH3IE
Channel 3 capture/compare interrupt enable
4
1
TRGDEN
Trigger DMA request enable
14
1
TRGIE
Trigger interrupt enable
6
1
UPDEN
Update DMA request enable
8
1
UPIE
Update interrupt enable
0
1
DMATB
DMATB
DMA transfer buffer register
0x4C
32
read-write
n
0x0
0x0
DMATB
DMA transfer buffer
0
16
INTF
INTF
interrupt flag register
0x10
32
read-write
n
0x0
0x0
CH0IF
Channel 0 capture/compare interrupt flag
1
1
CH0OF
Channel 0 over capture flag
9
1
CH1IF
Channel 1 capture/compare interrupt flag
2
1
CH1OF
Channel 1 over capture flag
10
1
CH2IF
Channel 2 capture/compare interrupt enable
3
1
CH2OF
Channel 2 over capture flag
11
1
CH3IF
Channel 3 capture/compare interrupt enable
4
1
CH3OF
Channel 3 over capture flag
12
1
TRGIF
Trigger interrupt flag
6
1
UPIF
Update interrupt flag
0
1
PSC
PSC
Prescaler register
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value of the counter clock
0
16
SMCFG
SMCFG
slave mode control register
0x8
32
read-write
n
0x0
0x0
ETFC
External trigger filter control
8
4
ETP
External trigger polarity
15
1
ETPSC
External trigger prescaler
12
2
MSM
Master-slave mode
7
1
SMC
Slave mode control
0
3
SMC1
Part of SMC for enable External clock mode1
14
1
TRGS
Trigger selection
4
3
SWEVG
SWEVG
event generation register
0x14
32
write-only
n
0x0
0x0
CH0G
Channel 0 capture or compare event generation
1
1
CH1G
Channel 1 capture or compare event generation
2
1
CH2G
Channel 2 capture or compare event generation
3
1
CH3G
Channel 3 capture or compare event generation
4
1
TRGG
Trigger event generation
6
1
UPG
Update generation
0
1
TIMER3
General-purpose-timers
TIMER
0x0
0x0
0x400
registers
n
TIMER3
30
CAR
CAR
Counter auto reload register
0x2C
32
read-write
n
0x0
0x0
CARL
Counter auto reload value
0
16
CH0CV
CH0CV
Channel 0 capture/compare value register
0x34
32
read-write
n
0x0
0x0
CH0VAL
Capture or compare value of channel 0
0
16
CH1CV
CH1CV
Channel 1 capture/compare value register
0x38
32
read-write
n
0x0
0x0
CH1VAL
Capture or compare value of channel1
0
16
CH2CV
CH2CV
Channel 2 capture/compare value register
0x3C
32
read-write
n
0x0
0x0
CH2VAL
Capture or compare value of channel 2
0
16
CH3CV
CH3CV
Channel 3 capture/compare value register
0x40
32
read-write
n
0x0
0x0
CH3VAL
Capture or compare value of channel 3
0
16
CHCTL0_Input
CHCTL0_Input
Channel control register 0 (input mode)
CHCTL0_Output
0x18
32
read-write
n
0x0
0x0
CH0CAPFLT
Channel 0 input capture filter control
4
4
CH0CAPPSC
Channel 0 input capture prescaler
2
2
CH0MS
Channel 0 mode selection
0
2
CH1CAPFLT
Channel 1 input capture filter control
12
4
CH1CAPPSC
Channel 1 input capture prescaler
10
2
CH1MS
Channel 1 mode selection
8
2
CHCTL0_Output
CHCTL0_Output
Channel control register 0 (output mode)
0x18
32
read-write
n
0x0
0x0
CH0COMCEN
Channel 0 output compare clear enable
7
1
CH0COMCTL
Channel 0 compare output control
4
3
CH0COMFEN
Channel 0 output compare fast enable
2
1
CH0COMSEN
Channel 0 compare output shadow enable
3
1
CH0MS
Channel 0 I/O mode selection
0
2
CH1COMCEN
Channel 1 output compare clear enable
15
1
CH1COMCTL
Channel 1 compare output control
12
3
CH1COMFEN
Channel 1 output compare fast enable
10
1
CH1COMSEN
Channel 1 output compare shadow enable
11
1
CH1MS
Channel 1 mode selection
8
2
CHCTL1_Input
CHCTL1_Input
Channel control register 1 (input mode)
CHCTL1_Output
0x1C
32
read-write
n
0x0
0x0
CH2CAPFLT
Channel 2 input capture filter control
4
4
CH2CAPPSC
Channel 2 input capture prescaler
2
2
CH2MS
Channel 2 mode selection
0
2
CH3CAPFLT
Channel 3 input capture filter control
12
4
CH3CAPPSC
Channel 3 input capture prescaler
10
2
CH3MS
Channel 3 mode selection
8
2
CHCTL1_Output
CHCTL1_Output
Channel control register 1 (output mode)
0x1C
32
read-write
n
0x0
0x0
CH2COMCEN
Channel 2 output compare clear enable
7
1
CH2COMCTL
Channel 2 compare output control
4
3
CH2COMFEN
Channel 2 output compare fast enable
2
1
CH2COMSEN
Channel 2 compare output shadow enable
3
1
CH2MS
Channel 2 I/O mode selection
0
2
CH3COMCEN
Channel 3 output compare clear enable
15
1
CH3COMCTL
Channel 3 compare output control
12
3
CH3COMFEN
Channel 3 output compare fast enable
10
1
CH3COMSEN
Channel 3 output compare shadow enable
11
1
CH3MS
Channel 3 mode selection
8
2
CHCTL2
CHCTL2
Channel control register 2
0x20
32
read-write
n
0x0
0x0
CH0EN
Channel 0 capture/compare function enable
0
1
CH0P
Channel 0 capture/compare function polarity
1
1
CH1EN
Channel 1 capture/compare function enable
4
1
CH1P
Channel 1 capture/compare function polarity
5
1
CH2EN
Channel 2 capture/compare function enable
8
1
CH2P
Channel 2 capture/compare function polarity
9
1
CH3EN
Channel 3 capture/compare function enable
12
1
CH3P
Channel 3 capture/compare function polarity
13
1
CNT
CNT
Counter register
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
ARSE
Auto-reload shadow enable
7
1
CAM
Counter aligns mode selection
5
2
CEN
Counter enable
0
1
CKDIV
Clock division
8
2
DIR
Direction
4
1
SPM
Single pulse mode
3
1
UPDIS
Update disable
1
1
UPS
Update source
2
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
DMAS
DMA request source selection
3
1
MMC
Master mode control
4
3
TI0S
Channel 0 trigger input selection
7
1
DMACFG
DMACFG
DMA configuration register
0x48
32
read-write
n
0x0
0x0
DMATA
DMA transfer access start address
0
5
DMATC
DMA transfer count
8
5
DMAINTEN
DMAINTEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CH0DEN
Channel 0 capture/compare DMA request enable
9
1
CH0IE
Channel 0 capture/compare interrupt enable
1
1
CH1DEN
Channel 1 capture/compare DMA request enable
10
1
CH1IE
Channel 1 capture/compare interrupt enable
2
1
CH2DEN
Channel 2 capture/compare DMA request enable
11
1
CH2IE
Channel 2 capture/compare interrupt enable
3
1
CH3DEN
Channel 3 capture/compare DMA request enable
12
1
CH3IE
Channel 3 capture/compare interrupt enable
4
1
TRGDEN
Trigger DMA request enable
14
1
TRGIE
Trigger interrupt enable
6
1
UPDEN
Update DMA request enable
8
1
UPIE
Update interrupt enable
0
1
DMATB
DMATB
DMA transfer buffer register
0x4C
32
read-write
n
0x0
0x0
DMATB
DMA transfer buffer
0
16
INTF
INTF
interrupt flag register
0x10
32
read-write
n
0x0
0x0
CH0IF
Channel 0 capture/compare interrupt flag
1
1
CH0OF
Channel 0 over capture flag
9
1
CH1IF
Channel 1 capture/compare interrupt flag
2
1
CH1OF
Channel 1 over capture flag
10
1
CH2IF
Channel 2 capture/compare interrupt enable
3
1
CH2OF
Channel 2 over capture flag
11
1
CH3IF
Channel 3 capture/compare interrupt enable
4
1
CH3OF
Channel 3 over capture flag
12
1
TRGIF
Trigger interrupt flag
6
1
UPIF
Update interrupt flag
0
1
PSC
PSC
Prescaler register
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value of the counter clock
0
16
SMCFG
SMCFG
slave mode control register
0x8
32
read-write
n
0x0
0x0
ETFC
External trigger filter control
8
4
ETP
External trigger polarity
15
1
ETPSC
External trigger prescaler
12
2
MSM
Master-slave mode
7
1
SMC
Slave mode control
0
3
SMC1
Part of SMC for enable External clock mode1
14
1
TRGS
Trigger selection
4
3
SWEVG
SWEVG
event generation register
0x14
32
write-only
n
0x0
0x0
CH0G
Channel 0 capture or compare event generation
1
1
CH1G
Channel 1 capture or compare event generation
2
1
CH2G
Channel 2 capture or compare event generation
3
1
CH3G
Channel 3 capture or compare event generation
4
1
TRGG
Trigger event generation
6
1
UPG
Update generation
0
1
TIMER4
General-purpose-timers
TIMER
0x0
0x0
0x400
registers
n
TIMER4
50
CAR
CAR
Counter auto reload register
0x2C
32
read-write
n
0x0
0x0
CARL
Counter auto reload value
0
16
CH0CV
CH0CV
Channel 0 capture/compare value register
0x34
32
read-write
n
0x0
0x0
CH0VAL
Capture or compare value of channel 0
0
16
CH1CV
CH1CV
Channel 1 capture/compare value register
0x38
32
read-write
n
0x0
0x0
CH1VAL
Capture or compare value of channel1
0
16
CH2CV
CH2CV
Channel 2 capture/compare value register
0x3C
32
read-write
n
0x0
0x0
CH2VAL
Capture or compare value of channel 2
0
16
CH3CV
CH3CV
Channel 3 capture/compare value register
0x40
32
read-write
n
0x0
0x0
CH3VAL
Capture or compare value of channel 3
0
16
CHCTL0_Input
CHCTL0_Input
Channel control register 0 (input mode)
CHCTL0_Output
0x18
32
read-write
n
0x0
0x0
CH0CAPFLT
Channel 0 input capture filter control
4
4
CH0CAPPSC
Channel 0 input capture prescaler
2
2
CH0MS
Channel 0 mode selection
0
2
CH1CAPFLT
Channel 1 input capture filter control
12
4
CH1CAPPSC
Channel 1 input capture prescaler
10
2
CH1MS
Channel 1 mode selection
8
2
CHCTL0_Output
CHCTL0_Output
Channel control register 0 (output mode)
0x18
32
read-write
n
0x0
0x0
CH0COMCEN
Channel 0 output compare clear enable
7
1
CH0COMCTL
Channel 0 compare output control
4
3
CH0COMFEN
Channel 0 output compare fast enable
2
1
CH0COMSEN
Channel 0 compare output shadow enable
3
1
CH0MS
Channel 0 I/O mode selection
0
2
CH1COMCEN
Channel 1 output compare clear enable
15
1
CH1COMCTL
Channel 1 compare output control
12
3
CH1COMFEN
Channel 1 output compare fast enable
10
1
CH1COMSEN
Channel 1 output compare shadow enable
11
1
CH1MS
Channel 1 mode selection
8
2
CHCTL1_Input
CHCTL1_Input
Channel control register 1 (input mode)
CHCTL1_Output
0x1C
32
read-write
n
0x0
0x0
CH2CAPFLT
Channel 2 input capture filter control
4
4
CH2CAPPSC
Channel 2 input capture prescaler
2
2
CH2MS
Channel 2 mode selection
0
2
CH3CAPFLT
Channel 3 input capture filter control
12
4
CH3CAPPSC
Channel 3 input capture prescaler
10
2
CH3MS
Channel 3 mode selection
8
2
CHCTL1_Output
CHCTL1_Output
Channel control register 1 (output mode)
0x1C
32
read-write
n
0x0
0x0
CH2COMCEN
Channel 2 output compare clear enable
7
1
CH2COMCTL
Channel 2 compare output control
4
3
CH2COMFEN
Channel 2 output compare fast enable
2
1
CH2COMSEN
Channel 2 compare output shadow enable
3
1
CH2MS
Channel 2 I/O mode selection
0
2
CH3COMCEN
Channel 3 output compare clear enable
15
1
CH3COMCTL
Channel 3 compare output control
12
3
CH3COMFEN
Channel 3 output compare fast enable
10
1
CH3COMSEN
Channel 3 output compare shadow enable
11
1
CH3MS
Channel 3 mode selection
8
2
CHCTL2
CHCTL2
Channel control register 2
0x20
32
read-write
n
0x0
0x0
CH0EN
Channel 0 capture/compare function enable
0
1
CH0P
Channel 0 capture/compare function polarity
1
1
CH1EN
Channel 1 capture/compare function enable
4
1
CH1P
Channel 1 capture/compare function polarity
5
1
CH2EN
Channel 2 capture/compare function enable
8
1
CH2P
Channel 2 capture/compare function polarity
9
1
CH3EN
Channel 3 capture/compare function enable
12
1
CH3P
Channel 3 capture/compare function polarity
13
1
CNT
CNT
Counter register
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
ARSE
Auto-reload shadow enable
7
1
CAM
Counter aligns mode selection
5
2
CEN
Counter enable
0
1
CKDIV
Clock division
8
2
DIR
Direction
4
1
SPM
Single pulse mode
3
1
UPDIS
Update disable
1
1
UPS
Update source
2
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
DMAS
DMA request source selection
3
1
MMC
Master mode control
4
3
TI0S
Channel 0 trigger input selection
7
1
DMACFG
DMACFG
DMA configuration register
0x48
32
read-write
n
0x0
0x0
DMATA
DMA transfer access start address
0
5
DMATC
DMA transfer count
8
5
DMAINTEN
DMAINTEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CH0DEN
Channel 0 capture/compare DMA request enable
9
1
CH0IE
Channel 0 capture/compare interrupt enable
1
1
CH1DEN
Channel 1 capture/compare DMA request enable
10
1
CH1IE
Channel 1 capture/compare interrupt enable
2
1
CH2DEN
Channel 2 capture/compare DMA request enable
11
1
CH2IE
Channel 2 capture/compare interrupt enable
3
1
CH3DEN
Channel 3 capture/compare DMA request enable
12
1
CH3IE
Channel 3 capture/compare interrupt enable
4
1
TRGDEN
Trigger DMA request enable
14
1
TRGIE
Trigger interrupt enable
6
1
UPDEN
Update DMA request enable
8
1
UPIE
Update interrupt enable
0
1
DMATB
DMATB
DMA transfer buffer register
0x4C
32
read-write
n
0x0
0x0
DMATB
DMA transfer buffer
0
16
INTF
INTF
interrupt flag register
0x10
32
read-write
n
0x0
0x0
CH0IF
Channel 0 capture/compare interrupt flag
1
1
CH0OF
Channel 0 over capture flag
9
1
CH1IF
Channel 1 capture/compare interrupt flag
2
1
CH1OF
Channel 1 over capture flag
10
1
CH2IF
Channel 2 capture/compare interrupt enable
3
1
CH2OF
Channel 2 over capture flag
11
1
CH3IF
Channel 3 capture/compare interrupt enable
4
1
CH3OF
Channel 3 over capture flag
12
1
TRGIF
Trigger interrupt flag
6
1
UPIF
Update interrupt flag
0
1
PSC
PSC
Prescaler register
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value of the counter clock
0
16
SMCFG
SMCFG
slave mode control register
0x8
32
read-write
n
0x0
0x0
ETFC
External trigger filter control
8
4
ETP
External trigger polarity
15
1
ETPSC
External trigger prescaler
12
2
MSM
Master-slave mode
7
1
SMC
Slave mode control
0
3
SMC1
Part of SMC for enable External clock mode1
14
1
TRGS
Trigger selection
4
3
SWEVG
SWEVG
event generation register
0x14
32
write-only
n
0x0
0x0
CH0G
Channel 0 capture or compare event generation
1
1
CH1G
Channel 1 capture or compare event generation
2
1
CH2G
Channel 2 capture or compare event generation
3
1
CH3G
Channel 3 capture or compare event generation
4
1
TRGG
Trigger event generation
6
1
UPG
Update generation
0
1
TIMER5
Basic-timers
TIMER
0x0
0x0
0x400
registers
n
TIMER5
54
CAR
CAR
Counter auto reload register
0x2C
32
read-write
n
0x0
0x0
CARL
Counter auto reload value
0
16
CNT
CNT
Counter register
0x24
32
read-write
n
0x0
0x0
CNT
Low counter value
0
16
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
ARSE
Auto-reload shadow enable
7
1
CEN
Counter enable
0
1
SPM
Single pulse mode
3
1
UPDIS
Update disable
1
1
UPS
Update source
2
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
MMC
Master mode control
4
3
DMAINTEN
DMAINTEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
UPDEN
Update DMA request enable
8
1
UPIE
Update interrupt enable
0
1
INTF
INTF
Interrupt flag register
0x10
32
read-write
n
0x0
0x0
UPIF
Update interrupt flag
0
1
PSC
PSC
Prescaler register
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value of the counter clock
0
16
SWEVG
SWEVG
event generation register
0x14
32
write-only
n
0x0
0x0
UPG
Update generation
0
1
TIMER6
Basic-timers
TIMER
0x0
0x0
0x400
registers
n
TIMER6
55
CAR
CAR
Counter auto reload register
0x2C
32
read-write
n
0x0
0x0
CARL
Counter auto reload value
0
16
CNT
CNT
Counter register
0x24
32
read-write
n
0x0
0x0
CNT
Low counter value
0
16
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
ARSE
Auto-reload shadow enable
7
1
CEN
Counter enable
0
1
SPM
Single pulse mode
3
1
UPDIS
Update disable
1
1
UPS
Update source
2
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
MMC
Master mode control
4
3
DMAINTEN
DMAINTEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
UPDEN
Update DMA request enable
8
1
UPIE
Update interrupt enable
0
1
INTF
INTF
Interrupt flag register
0x10
32
read-write
n
0x0
0x0
UPIF
Update interrupt flag
0
1
PSC
PSC
Prescaler register
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value of the counter clock
0
16
SWEVG
SWEVG
event generation register
0x14
32
write-only
n
0x0
0x0
UPG
Update generation
0
1
TIMER7
Advanced-timers
TIMER
0x0
0x0
0x400
registers
n
TIMER7_BRK
43
TIMER7_UP
44
TIMER7_TRG_CMT
45
TIMER7_Channel
46
CAR
CAR
Counter auto reload register
0x2C
32
read-write
n
0x0
0x0
CARL
Counter auto reload value
0
16
CCHP
CCHP
channel complementary protection register
0x44
32
read-write
n
0x0
0x0
BRKEN
Break enable
12
1
BRKP
Break polarity
13
1
DTCFG
Dead time configure
0
8
IOS
Idle mode off-state configure
10
1
OAEN
Output automatic enable
14
1
POEN
Primary output enable
15
1
PROT
Complementary register protect control
8
2
ROS
Run mode off-state configure
11
1
CH0CV
CH0CV
Channel 0 capture/compare value register
0x34
32
read-write
n
0x0
0x0
CH0VAL
Capture or compare value of channel0
0
16
CH1CV
CH1CV
Channel 1 capture/compare value register
0x38
32
read-write
n
0x0
0x0
CH1VAL
Capture or compare value of channel1
0
16
CH2CV
CH2CV
Channel 2 capture/compare value register
0x3C
32
read-write
n
0x0
0x0
CH2VAL
Capture or compare value of channel 2
0
16
CH3CV
CH3CV
Channel 3 capture/compare value register
0x40
32
read-write
n
0x0
0x0
CH3VAL
Capture or compare value of channel 3
0
16
CHCTL0_Input
CHCTL0_Input
Channel control register 0 (input mode)
CHCTL0_Output
0x18
32
read-write
n
0x0
0x0
CH0CAPFLT
Channel 0 input capture filter control
4
4
CH0CAPPSC
Channel 0 input capture prescaler
2
2
CH0MS
Channel 0 mode selection
0
2
CH1CAPFLT
Channel 1 input capture filter control
12
4
CH1CAPPSC
Channel 1 input capture prescaler
10
2
CH1MS
Channel 1 mode selection
8
2
CHCTL0_Output
CHCTL0_Output
Channel control register 0 (output mode)
0x18
32
read-write
n
0x0
0x0
CH0COMCEN
Channel 0 output compare clear enable
7
1
CH0COMCTL
Channel 0 compare output control
4
3
CH0COMFEN
Channel 0 output compare fast enable
2
1
CH0COMSEN
Channel 0 compare output shadow enable
3
1
CH0MS
Channel 0 I/O mode selection
0
2
CH1COMCEN
Channel 1 output compare clear enable
15
1
CH1COMCTL
Channel 1 compare output control
12
3
CH1COMFEN
Channel 1 output compare fast enable
10
1
CH1COMSEN
Channel 1 output compare shadow enable
11
1
CH1MS
Channel 1 mode selection
8
2
CHCTL1_Input
CHCTL1_Input
Channel control register 1 (input mode)
CHCTL1_Output
0x1C
32
read-write
n
0x0
0x0
CH2CAPFLT
Channel 2 input capture filter control
4
4
CH2CAPPSC
Channel 2 input capture prescaler
2
2
CH2MS
Channel 2 mode selection
0
2
CH3CAPFLT
Channel 3 input capture filter control
12
4
CH3CAPPSC
Channel 3 input capture prescaler
10
2
CH3MS
Channel 3 mode selection
8
2
CHCTL1_Output
CHCTL1_Output
Channel control register 1 (output mode)
0x1C
32
read-write
n
0x0
0x0
CH2COMCEN
Channel 2 output compare clear enable
7
1
CH2COMCTL
Channel 2 compare output control
4
3
CH2COMFEN
Channel 2 output compare fast enable
2
1
CH2COMSEN
Channel 2 compare output shadow enable
3
1
CH2MS
Channel 2 I/O mode selection
0
2
CH3COMCEN
Channel 3 output compare clear enable
15
1
CH3COMCTL
Channel 3 compare output control
12
3
CH3COMFEN
Channel 3 output compare fast enable
10
1
CH3COMSEN
Channel 3 output compare shadow enable
11
1
CH3MS
Channel 3 mode selection
8
2
CHCTL2
CHCTL2
Channel control register 2
0x20
32
read-write
n
0x0
0x0
CH0EN
Channel 0 capture/compare function enable
0
1
CH0NEN
Channel 0 complementary output enable
2
1
CH0NP
Channel 0 complementary output polarity
3
1
CH0P
Channel 0 capture/compare function polarity
1
1
CH1EN
Channel 1 capture/compare function enable
4
1
CH1NEN
Channel 1 complementary output enable
6
1
CH1NP
Channel 1 complementary output polarity
7
1
CH1P
Channel 1 capture/compare function polarity
5
1
CH2EN
Channel 2 capture/compare function enable
8
1
CH2NEN
Channel 2 complementary output enable
10
1
CH2NP
Channel 2 complementary output polarity
11
1
CH2P
Channel 2 capture/compare function polarity
9
1
CH3EN
Channel 3 capture/compare function enable
12
1
CH3P
Channel 3 capture/compare function polarity
13
1
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
current counter value
0
16
CREP
CREP
Counter repetition register
0x30
32
read-write
n
0x0
0x0
CREP
Counter repetition value
0
8
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
ARSE
Auto-reload shadow enable
7
1
CAM
Counter aligns mode selection
5
2
CEN
Counter enable
0
1
CKDIV
Clock division
8
2
DIR
Direction
4
1
SPM
Single pulse mode
3
1
UPDIS
Update disable
1
1
UPS
Update source
2
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
CCSE
Commutation control shadow enable
0
1
CCUC
Commutation control shadow register update control
2
1
DMAS
DMA request source selection
3
1
ISO0
Idle state of channel 0 output
8
1
ISO0N
Idle state of channel 0 complementary output
9
1
ISO1
Idle state of channel 1 output
10
1
ISO1N
Idle state of channel 1 complementary output
11
1
ISO2
Idle state of channel 2 output
12
1
ISO2N
Idle state of channel 2 complementary output
13
1
ISO3
Idle state of channel 3 output
14
1
MMC
Master mode control
4
3
TI0S
Channel 0 trigger input selection
7
1
DMACFG
DMACFG
DMA configuration register
0x48
32
read-write
n
0x0
0x0
DMATA
DMA transfer access start address
0
5
DMATC
DMA transfer count
8
5
DMAINTEN
DMAINTEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BRKIE
Break interrupt enable
7
1
CH0DEN
Channel 0 capture/compare DMA request enable
9
1
CH0IE
Channel 0 capture/compare interrupt enable
1
1
CH1DEN
Channel 1 capture/compare DMA request enable
10
1
CH1IE
Channel 1 capture/compare interrupt enable
2
1
CH2DEN
Channel 2 capture/compare DMA request enable
11
1
CH2IE
Channel 2 capture/compare interrupt enable
3
1
CH3DEN
Channel 3 capture/compare DMA request enable
12
1
CH3IE
Channel 3 capture/compare interrupt enable
4
1
CMTDEN
Commutation DMA request enable
13
1
CMTIE
commutation interrupt enable
5
1
TRGDEN
Trigger DMA request enable
14
1
TRGIE
Trigger interrupt enable
6
1
UPDEN
Update DMA request enable
8
1
UPIE
Update interrupt enable
0
1
DMATB
DMATB
DMA transfer buffer register
0x4C
32
read-write
n
0x0
0x0
DMATB
DMA transfer buffer
0
16
INTF
INTF
Interrupt flag register
0x10
32
read-write
n
0x0
0x0
BRKIF
Break interrupt flag
7
1
CH0IF
Channel 0 capture/compare interrupt flag
1
1
CH0OF
Channel 0 over capture flag
9
1
CH1IF
Channel 1 capture/compare interrupt flag
2
1
CH1OF
Channel 1 over capture flag
10
1
CH2IF
Channel 2 capture/compare interrupt flag
3
1
CH2OF
Channel 2 over capture flag
11
1
CH3IF
Channel 3 capture/compare interrupt flag
4
1
CH3OF
Channel 3 over capture flag
12
1
CMTIF
Channel commutation interrupt flag
5
1
TRGIF
Trigger interrupt flag
6
1
UPIF
Update interrupt flag
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value of the counter clock
0
16
SMCFG
SMCFG
slave mode configuration register
0x8
32
read-write
n
0x0
0x0
ETFC
External trigger filter control
8
4
ETP
External trigger polarity
15
1
ETPSC
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
SMC
Slave mode selection
0
3
SMC1
Part of SMC for enable External clock mode1
14
1
TRGS
Trigger selection
4
3
SWEVG
SWEVG
Software event generation register
0x14
32
write-only
n
0x0
0x0
BRKG
Break event generation
7
1
CH0G
Channel 0 capture or compare event generation
1
1
CH1G
Channel 1 capture or compare event generation
2
1
CH2G
Channel 2 capture or compare event generation
3
1
CH3G
Channel 3 capture or compare event generation
4
1
CMTG
Channel commutation event generation
5
1
TRGG
Trigger event generation
6
1
UPG
Update event generation
0
1
UART3
Universal asynchronous receiver transmitter
UART
0x0
0x0
0x400
registers
n
UART3
52
BAUD
BAUD
Baud rate register
0x8
32
read-write
n
0x0
0x0
FRADIV
Fraction part of baud-rate divider
0
4
INTDIV
Integer part of baud-rate divider
4
12
CTL0
CTL0
Control register 0
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE line detected interrupt enable
4
1
PCEN
Parity check function enable
10
1
PERRIE
Parity error interrupt enable
8
1
PM
Parity mode
9
1
RBNEIE
Read data buffer not empty interrupt and overrun error interrupt enable
5
1
REN
Receiver enable
2
1
RWU
Receiver wakeup from mute mode
1
1
SBKCMD
Send break command
0
1
TBEIE
Transmitter buffer empty interrupt enable
7
1
TCIE
Transmission complete interrupt enable
6
1
TEN
Transmitter enable
3
1
UEN
USART enable
13
1
WL
Word length
12
1
WM
Wakeup method in mute mode
11
1
CTL1
CTL1
Control register 1
0x10
32
read-write
n
0x0
0x0
ADDR
Address of the USART
0
4
LBDIE
LIN break detection interrupt enable
6
1
LBLEN
LIN break frame length
5
1
LMEN
LIN mode enable
14
1
STB
STOP bits length
12
2
CTL2
CTL2
Control register 2
0x14
32
read-write
n
0x0
0x0
DENR
DMA request enable for reception
6
1
DENT
DMA request enable for transmission
7
1
ERRIE
Error interrupt enable
0
1
HDEN
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
DATA
DATA
Data register
0x4
32
read-write
n
0x0
0x0
DATA
Transmit or read data value
0
9
GP
GP
Guard time and prescaler register
0x18
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
8
STAT
STAT
Status register
0x0
32
read-write
n
0x0
0x0
FERR
Frame error flag
1
1
read-only
IDLEF
IDLE frame detected flag
4
1
read-only
LBDF
LIN break detection flag
8
1
read-write
NERR
Noise error flag
2
1
read-only
ORERR
Overrun error
3
1
read-only
PERR
Parity error flag
0
1
read-only
RBNE
Read data buffer not empty
5
1
read-write
TBE
Transmit data buffer empty
7
1
read-only
TC
Transmission complete
6
1
read-write
UART4
Universal asynchronous receiver transmitter
UART
0x0
0x0
0x400
registers
n
UART4
53
BAUD
BAUD
Baud rate register
0x8
32
read-write
n
0x0
0x0
FRADIV
Fraction part of baud-rate divider
0
4
INTDIV
Integer part of baud-rate divider
4
12
CTL0
CTL0
Control register 0
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE line detected interrupt enable
4
1
PCEN
Parity check function enable
10
1
PERRIE
Parity error interrupt enable
8
1
PM
Parity mode
9
1
RBNEIE
Read data buffer not empty interrupt and overrun error interrupt enable
5
1
REN
Receiver enable
2
1
RWU
Receiver wakeup from mute mode
1
1
SBKCMD
Send break command
0
1
TBEIE
Transmitter buffer empty interrupt enable
7
1
TCIE
Transmission complete interrupt enable
6
1
TEN
Transmitter enable
3
1
UEN
USART enable
13
1
WL
Word length
12
1
WM
Wakeup method in mute mode
11
1
CTL1
CTL1
Control register 1
0x10
32
read-write
n
0x0
0x0
ADDR
Address of the USART
0
4
LBDIE
LIN break detection interrupt enable
6
1
LBLEN
LIN break frame length
5
1
LMEN
LIN mode enable
14
1
STB
STOP bits length
12
2
CTL2
CTL2
Control register 2
0x14
32
read-write
n
0x0
0x0
DENR
DMA request enable for reception
6
1
DENT
DMA request enable for transmission
7
1
ERRIE
Error interrupt enable
0
1
HDEN
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
DATA
DATA
Data register
0x4
32
read-write
n
0x0
0x0
DATA
Transmit or read data value
0
9
GP
GP
Guard time and prescaler register
0x18
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
8
STAT
STAT
Status register
0x0
32
read-write
n
0x0
0x0
FERR
Frame error flag
1
1
read-only
IDLEF
IDLE frame detected flag
4
1
read-only
LBDF
LIN break detection flag
8
1
read-write
NERR
Noise error flag
2
1
read-only
ORERR
Overrun error
3
1
read-only
PERR
Parity error flag
0
1
read-only
RBNE
Read data buffer not empty
5
1
read-write
TBE
Transmit data buffer empty
7
1
read-only
TC
Transmission complete
6
1
read-write
USART0
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART0
37
BAUD
BAUD
Baud rate register
0x8
32
read-write
n
0x0
0x0
FRADIV
Fraction part of baud-rate divider
0
4
INTDIV
Integer part of baud-rate divider
4
12
CTL0
CTL0
Control register 0
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE line detected interrupt enable
4
1
PCEN
Parity check function enable
10
1
PERRIE
Parity error interrupt enable
8
1
PM
Parity mode
9
1
RBNEIE
Read data buffer not empty interrupt and overrun error interrupt enable
5
1
REN
Receiver enable
2
1
RWU
Receiver wakeup from mute mode
1
1
SBKCMD
Send break command
0
1
TBEIE
Transmitter buffer empty interrupt enable
7
1
TCIE
Transmission complete interrupt enable
6
1
TEN
Transmitter enable
3
1
UEN
USART enable
13
1
WL
Word length
12
1
WM
Wakeup method in mute mode
11
1
CTL1
CTL1
Control register 1
0x10
32
read-write
n
0x0
0x0
ADDR
Address of the USART
0
4
CKEN
CK pin enable
11
1
CLEN
CK Length
8
1
CPH
Clock phase
9
1
CPL
Clock polarity
10
1
LBDIE
LIN break detection interrupt enable
6
1
LBLEN
LIN break frame length
5
1
LMEN
LIN mode enable
14
1
STB
STOP bits length
12
2
CTL2
CTL2
Control register 2
0x14
32
read-write
n
0x0
0x0
CTSEN
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DENR
DMA request enable for reception
6
1
DENT
DMA request enable for transmission
7
1
ERRIE
Error interrupt enable
0
1
HDEN
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NKEN
Smartcard NACK enable
4
1
RTSEN
RTS enable
8
1
SCEN
Smartcard mode enable
5
1
DATA
DATA
Data register
0x4
32
read-write
n
0x0
0x0
DATA
Transmit or read data value
0
9
GP
GP
Guard time and prescaler register
0x18
32
read-write
n
0x0
0x0
GUAT
Guard time value in Smartcard mode
8
8
PSC
Prescaler value
0
8
STAT
STAT
Status register
0x0
32
read-write
n
0x0
0x0
CTSF
CTS change flag
9
1
read-write
FERR
Frame error flag
1
1
read-only
IDLEF
IDLE frame detected flag
4
1
read-only
LBDF
LIN break detection flag
8
1
read-write
NERR
Noise error flag
2
1
read-only
ORERR
Overrun error
3
1
read-only
PERR
Parity error flag
0
1
read-only
RBNE
Read data buffer not empty
5
1
read-write
TBE
Transmit data buffer empty
7
1
read-only
TC
Transmission complete
6
1
read-write
USART1
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART1
38
BAUD
BAUD
Baud rate register
0x8
32
read-write
n
0x0
0x0
FRADIV
Fraction part of baud-rate divider
0
4
INTDIV
Integer part of baud-rate divider
4
12
CTL0
CTL0
Control register 0
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE line detected interrupt enable
4
1
PCEN
Parity check function enable
10
1
PERRIE
Parity error interrupt enable
8
1
PM
Parity mode
9
1
RBNEIE
Read data buffer not empty interrupt and overrun error interrupt enable
5
1
REN
Receiver enable
2
1
RWU
Receiver wakeup from mute mode
1
1
SBKCMD
Send break command
0
1
TBEIE
Transmitter buffer empty interrupt enable
7
1
TCIE
Transmission complete interrupt enable
6
1
TEN
Transmitter enable
3
1
UEN
USART enable
13
1
WL
Word length
12
1
WM
Wakeup method in mute mode
11
1
CTL1
CTL1
Control register 1
0x10
32
read-write
n
0x0
0x0
ADDR
Address of the USART
0
4
CKEN
CK pin enable
11
1
CLEN
CK Length
8
1
CPH
Clock phase
9
1
CPL
Clock polarity
10
1
LBDIE
LIN break detection interrupt enable
6
1
LBLEN
LIN break frame length
5
1
LMEN
LIN mode enable
14
1
STB
STOP bits length
12
2
CTL2
CTL2
Control register 2
0x14
32
read-write
n
0x0
0x0
CTSEN
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DENR
DMA request enable for reception
6
1
DENT
DMA request enable for transmission
7
1
ERRIE
Error interrupt enable
0
1
HDEN
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NKEN
Smartcard NACK enable
4
1
RTSEN
RTS enable
8
1
SCEN
Smartcard mode enable
5
1
DATA
DATA
Data register
0x4
32
read-write
n
0x0
0x0
DATA
Transmit or read data value
0
9
GP
GP
Guard time and prescaler register
0x18
32
read-write
n
0x0
0x0
GUAT
Guard time value in Smartcard mode
8
8
PSC
Prescaler value
0
8
STAT
STAT
Status register
0x0
32
read-write
n
0x0
0x0
CTSF
CTS change flag
9
1
read-write
FERR
Frame error flag
1
1
read-only
IDLEF
IDLE frame detected flag
4
1
read-only
LBDF
LIN break detection flag
8
1
read-write
NERR
Noise error flag
2
1
read-only
ORERR
Overrun error
3
1
read-only
PERR
Parity error flag
0
1
read-only
RBNE
Read data buffer not empty
5
1
read-write
TBE
Transmit data buffer empty
7
1
read-only
TC
Transmission complete
6
1
read-write
USART2
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART2
39
BAUD
BAUD
Baud rate register
0x8
32
read-write
n
0x0
0x0
FRADIV
Fraction part of baud-rate divider
0
4
INTDIV
Integer part of baud-rate divider
4
12
CTL0
CTL0
Control register 0
0xC
32
read-write
n
0x0
0x0
IDLEIE
IDLE line detected interrupt enable
4
1
PCEN
Parity check function enable
10
1
PERRIE
Parity error interrupt enable
8
1
PM
Parity mode
9
1
RBNEIE
Read data buffer not empty interrupt and overrun error interrupt enable
5
1
REN
Receiver enable
2
1
RWU
Receiver wakeup from mute mode
1
1
SBKCMD
Send break command
0
1
TBEIE
Transmitter buffer empty interrupt enable
7
1
TCIE
Transmission complete interrupt enable
6
1
TEN
Transmitter enable
3
1
UEN
USART enable
13
1
WL
Word length
12
1
WM
Wakeup method in mute mode
11
1
CTL1
CTL1
Control register 1
0x10
32
read-write
n
0x0
0x0
ADDR
Address of the USART
0
4
CKEN
CK pin enable
11
1
CLEN
CK Length
8
1
CPH
Clock phase
9
1
CPL
Clock polarity
10
1
LBDIE
LIN break detection interrupt enable
6
1
LBLEN
LIN break frame length
5
1
LMEN
LIN mode enable
14
1
STB
STOP bits length
12
2
CTL2
CTL2
Control register 2
0x14
32
read-write
n
0x0
0x0
CTSEN
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DENR
DMA request enable for reception
6
1
DENT
DMA request enable for transmission
7
1
ERRIE
Error interrupt enable
0
1
HDEN
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NKEN
Smartcard NACK enable
4
1
RTSEN
RTS enable
8
1
SCEN
Smartcard mode enable
5
1
DATA
DATA
Data register
0x4
32
read-write
n
0x0
0x0
DATA
Transmit or read data value
0
9
GP
GP
Guard time and prescaler register
0x18
32
read-write
n
0x0
0x0
GUAT
Guard time value in Smartcard mode
8
8
PSC
Prescaler value
0
8
STAT
STAT
Status register
0x0
32
read-write
n
0x0
0x0
CTSF
CTS change flag
9
1
read-write
FERR
Frame error flag
1
1
read-only
IDLEF
IDLE frame detected flag
4
1
read-only
LBDF
LIN break detection flag
8
1
read-write
NERR
Noise error flag
2
1
read-only
ORERR
Overrun error
3
1
read-only
PERR
Parity error flag
0
1
read-only
RBNE
Read data buffer not empty
5
1
read-write
TBE
Transmit data buffer empty
7
1
read-only
TC
Transmission complete
6
1
read-write
USBD
Universal serial bus full-speed device interface
USBD
0x0
0x0
0x400
registers
n
USBD_HP_CAN0_TX
19
USBD_LP_CAN0_RX0
20
USBD_WKUP
42
BADDR
BADDR
Buffer address register
0x50
32
read-write
n
0x0
0x0
BAR
Buffer address
3
13
CTL
CTL
control register
0x40
32
read-write
n
0x0
0x0
CLOSE
Close state
1
1
ERRIE
Error interrupt mask
13
1
ESOFIE
Expected start of frame interrupt enable
8
1
LOWM
Low-power mode
2
1
PMOUIE
Packet memory area over / underrun interrupt enable
14
1
RSREQ
Resume request
4
1
RSTIE
USB reset interrupt mask
10
1
SETRST
Set reset
0
1
SETSPS
Set suspend
3
1
SOFIE
Start of frame interrupt mask
9
1
SPSIE
Suspend mode interrupt mask
11
1
STIE
Successful transfer interrupt enable
15
1
WKUPIE
Wakeup interrupt enable
12
1
DADDR
DADDR
device address register
0x4C
32
read-write
n
0x0
0x0
USBDAR
Device address
0
7
USBEN
USB device enable
7
1
EP0CS
EP0CS
endpoint 0 register
0x0
32
read-write
n
0x0
0x0
EP_ADDR
Endpoint address
0
4
EP_CTL
Endpoint type
9
2
EP_KCTL
Endpoint kind
8
1
RX_DTG
Data Toggle, for reception transfers
14
1
RX_ST
Correct transfer for reception
15
1
RX_STA
Status bits, for reception transfers
12
2
SETUP
Setup transaction completed
11
1
TX_DTG
Data PID Toggle, for transmission transfers
6
1
TX_ST
Correct Transfer for transmission
7
1
TX_STA
Status bits, for transmission transfers
4
2
EP1CS
EP1CS
endpoint 1 register
0x4
32
read-write
n
0x0
0x0
EP_ADDR
Endpoint address
0
4
EP_CTL
Endpoint type
9
2
EP_KCTL
Endpoint kind
8
1
RX_DTG
Data Toggle, for reception transfers
14
1
RX_ST
Correct transfer for reception
15
1
RX_STA
Status bits, for reception transfers
12
2
SETUP
Setup transaction completed
11
1
TX_DTG
Data Toggle, for transmission transfers
6
1
TX_ST
Correct Transfer for transmission
7
1
TX_STA
Status bits, for transmission transfers
4
2
EP2CS
EP2CS
endpoint 2 register
0x8
32
read-write
n
0x0
0x0
EP_ADDR
Endpoint address
0
4
EP_CTL
Endpoint type
9
2
EP_KCTL
Endpoint kind
8
1
RX_DTG
Data Toggle, for reception transfers
14
1
RX_ST
Correct transfer for reception
15
1
RX_STA
Status bits, for reception transfers
12
2
SETUP
Setup transaction completed
11
1
TX_DTG
Data Toggle, for transmission transfers
6
1
TX_ST
Correct Transfer for transmission
7
1
TX_STA
Status bits, for transmission transfers
4
2
EP3CS
EP3CS
endpoint 3 register
0xC
32
read-write
n
0x0
0x0
EP_ADDR
Endpoint address
0
4
EP_CTL
Endpoint type
9
2
EP_KCTL
Endpoint kind
8
1
RX_DTG
Data Toggle, for reception transfers
14
1
RX_ST
Correct transfer for reception
15
1
RX_STA
Status bits, for reception transfers
12
2
SETUP
Setup transaction completed
11
1
TX_DTG
Data Toggle, for transmission transfers
6
1
TX_ST
Correct Transfer for transmission
7
1
TX_STA
Status bits, for transmission transfers
4
2
EP4CS
EP4CS
endpoint 4 register
0x10
32
read-write
n
0x0
0x0
EP_ADDR
Endpoint address
0
4
EP_CTL
Endpoint type
9
2
EP_KCTL
Endpoint kind
8
1
RX_DTG
Data Toggle, for reception transfers
14
1
RX_ST
Correct transfer for reception
15
1
RX_STA
Status bits, for reception transfers
12
2
SETUP
Setup transaction completed
11
1
TX_DTG
Data Toggle, for transmission transfers
6
1
TX_ST
Correct Transfer for transmission
7
1
TX_STA
Status bits, for transmission transfers
4
2
EP5CS
EP5CS
endpoint 5 register
0x14
32
read-write
n
0x0
0x0
EP_ADDR
Endpoint address
0
4
EP_CTL
Endpoint type
9
2
EP_KCTL
Endpoint kind
8
1
RX_DTG
Data Toggle, for reception transfers
14
1
RX_ST
Correct transfer for reception
15
1
RX_STA
Status bits, for reception transfers
12
2
SETUP
Setup transaction completed
11
1
TX_DTG
Data Toggle, for transmission transfers
6
1
TX_ST
Correct Transfer for transmission
7
1
TX_STA
Status bits, for transmission transfers
4
2
EP6CS
EP6CS
endpoint 6 register
0x18
32
read-write
n
0x0
0x0
EP_ADDR
Endpoint address
0
4
EP_CTL
Endpoint type
9
2
EP_KCTL
Endpoint kind
8
1
RX_DTG
Data Toggle, for reception transfers
14
1
RX_ST
Correct transfer for reception
15
1
RX_STA
Status bits, for reception transfers
12
2
SETUP
Setup transaction completed
11
1
TX_DTG
Data Toggle, for transmission transfers
6
1
TX_ST
Correct Transfer for transmission
7
1
TX_STA
Status bits, for transmission transfers
4
2
EP7CS
EP7CS
endpoint 7 register
0x1C
32
read-write
n
0x0
0x0
EP_ADDR
Endpoint address
0
4
EP_CTL
Endpoint type
9
2
EP_KCTL
Endpoint kind
8
1
RX_DTG
Data Toggle, for reception transfers
14
1
RX_ST
Correct transfer for reception
15
1
RX_STA
Status bits, for reception transfers
12
2
SETUP
Setup transaction completed
11
1
TX_DTG
Data Toggle, for transmission transfers
6
1
TX_ST
Correct Transfer for transmission
7
1
TX_STA
Status bits, for transmission transfers
4
2
INTF
INTF
interrupt flag register
0x44
32
read-write
n
0x0
0x0
DIR
Direction of transaction
4
1
read-only
EPNUM
Endpoint Identifier
0
4
read-only
ERRIF
Error interrupt flag
13
1
read-write
ESOFIF
Expected start of frame interrupt flag
8
1
read-write
PMOUIF
Packet memory area over / underrun interrupt flag
14
1
read-write
RSTIF
reset interrupt flag
10
1
read-write
SOFIF
start of frame interrupt flag
9
1
read-write
SPSIF
Suspend mode interrupt flag
11
1
read-write
STIF
Successful transfer interrupt flag
15
1
read-only
WKUPIF
Wakeup interrupt flag
12
1
read-write
STAT
STAT
Status register
0x48
32
read-only
n
0x0
0x0
FCNT
Frame number counter
0
11
LOCK
Locked the USB
13
1
RX_DM
Receive data - line status
14
1
RX_DP
Receive data + line status
15
1
SOFLN
Lost SOF number
11
2
WWDGT
Window watchdog timer
WWDGT
0x0
0x0
0x400
registers
n
WWDGT
0
CFG
CFG
Configuration register
0x4
32
read-write
n
0x0
0x0
EWIE
Early wakeup interrupt
9
1
PSC
Prescaler
7
2
WIN
7-bit window value
0
7
CTL
CTL
Control register
0x0
32
read-write
n
0x0
0x0
CNT
7-bit counter
0
7
WDGTEN
Activation bit
7
1
STAT
STAT
Status register
0x8
32
read-write
n
0x0
0x0
EWIF
Early wakeup interrupt flag
0
1