GigaDevice
GD32F3x0
2024.05.02
GD32F3x0 ARM 32-bit Cortex-M4 Microcontroller based device
CM4
r2p1
little
true
true
4
false
8
32
ADC
Analog to digital converter
ADC
0x0
0x0
0x400
registers
n
ADC_CMP
12
CTL0
CTL0
control register 0
0x4
32
read-write
n
0x0
0x0
DISIC
Discontinuous mode on injected channels
12
1
DISNUM
Discontinuous mode channel count
13
3
DISRC
Discontinuous mode on regular channels
11
1
DRES
ADC resolution
24
2
EOCIE
Interrupt enable for EOC
5
1
EOICIE
Interrupt enable for injected channels
7
1
ICA
Automatic injected group conversion
10
1
IWDEN
Analog watchdog enable on injected channels
22
1
RWDEN
Analog watchdog enable on regular channels
23
1
SM
Scan mode
8
1
WDCHSEL
Analog watchdog channel select bits
0
5
WDEIE
Analog watchdog interrupt enable
6
1
WDSC
Enable the watchdog on a single channel in scan mode
9
1
CTL1
CTL1
control register 1
0x8
32
read-write
n
0x0
0x0
ADCON
A/D converter ON / OFF
0
1
CLB
A/D calibration
2
1
CTN
Continuous conversion
1
1
DAL
Data alignment
11
1
DMA
Direct memory access mode
8
1
ETEIC
External trigger conversion mode for injected channels
15
1
ETERC
External trigger conversion mode for regular channels
20
1
ETSIC
External event select for injected group
12
3
ETSRC
External event select for regular group
17
3
RSTCLB
Reset calibration
3
1
SWICST
Start conversion of injected channels
21
1
SWRCST
Start conversion of regular channels
22
1
TSVREN
Temperature sensor and VREFINT enable
23
1
VBATEN
enable/disable the VBAT channel
24
1
IDATA0
IDATA0
injected data register 0
0x3C
32
read-only
n
0x0
0x0
IDATAn
Injected data
0
16
IDATA1
IDATA1
injected data register 1
0x40
32
read-only
n
0x0
0x0
IDATAn
Injected data
0
16
IDATA2
IDATA2
injected data register 2
0x44
32
read-only
n
0x0
0x0
IDATAn
Injected data
0
16
IDATA3
IDATA3
injected data register 3
0x48
32
read-only
n
0x0
0x0
IDATAn
Injected data
0
16
IOFF0
IOFF0
Inserted channel data offset register 0
0x14
32
read-write
n
0x0
0x0
IOFF
Data offset for injected channel x
0
12
IOFF1
IOFF1
Inserted channel data offset register 1
0x18
32
read-write
n
0x0
0x0
IOFF
Data offset for injected channel x
0
12
IOFF2
IOFF2
Inserted channel data offset register 2
0x1C
32
read-write
n
0x0
0x0
IOFF
Data offset for injected channel x
0
12
IOFF3
IOFF3
Inserted channel data offset register 3
0x20
32
read-write
n
0x0
0x0
IOFF
Data offset for injected channel x
0
12
ISQ
ISQ
injected sequence register
0x38
32
read-write
n
0x0
0x0
IL
Injected sequence length
20
2
ISQ0
conversion in injected sequence
0
5
ISQ1
1st conversion in injected sequence
5
5
ISQ2
2nd conversion in injected sequence
10
5
ISQ3
3rd conversion in injected sequence
15
5
OVSAMPCTL
OVSAMPCTL
ADC oversample control register
0x80
32
read-write
n
0x0
0x0
OVSEN
Oversampler Enable
0
1
OVSR
Oversampling ratio
2
3
OVSS
Oversampling shift
5
4
TOVS
Triggered Oversampling
9
1
RDATA
RDATA
regular data register
0x4C
32
read-only
n
0x0
0x0
RDATA
Regular data
0
16
RSQ0
RSQ0
regular sequence register 0
0x2C
32
read-write
n
0x0
0x0
RL
Regular channel sequence length
20
4
RSQ12
12th conversion in regular sequence
0
5
RSQ13
13th conversion in regular sequence
5
5
RSQ14
14th conversion in regular sequence
10
5
RSQ15
15th conversion in regular sequence
15
5
RSQ1
RSQ1
regular sequence register 1
0x30
32
read-write
n
0x0
0x0
RSQ10
10th conversion in regular sequence
20
5
RSQ11
11th conversion in regular sequence
25
5
RSQ6
6th conversion in regular sequence
0
5
RSQ7
7th conversion in regular sequence
5
5
RSQ8
8th conversion in regular sequence
10
5
RSQ9
9th conversion in regular sequence
15
5
RSQ2
RSQ2
regular sequence register 2
0x34
32
read-write
n
0x0
0x0
RSQ0
conversion in regular sequence
0
5
RSQ1
1st conversion in regular sequence
5
5
RSQ2
2nd conversion in regular sequence
10
5
RSQ3
3rd conversion in regular sequence
15
5
RSQ4
4th conversion in regular sequence
20
5
RSQ5
5th conversion in regular sequence
25
5
SAMPT0
SAMPT0
Sampling time register 0
0xC
32
read-write
n
0x0
0x0
SPT10
Channel 10 sample time selection
0
3
SPT11
Channel 11 sample time selection
3
3
SPT12
Channel 12 sample time selection
6
3
SPT13
Channel 13 sample time selection
9
3
SPT14
Channel 14 sample time selection
12
3
SPT15
Channel 15 sample time selection
15
3
SPT16
Channel 16 sample time selection
18
3
SPT17
Channel 17 sample time selection
21
3
SPT18
Channel 18 sample time selection
24
3
SAMPT1
SAMPT1
Sampling time register 1
0x10
32
read-write
n
0x0
0x0
SPT0
Channel 0 sample time selection
0
3
SPT1
Channel 1 sample time selection
3
3
SPT2
Channel 2 sample time selection
6
3
SPT3
Channel 3 sample time selection
9
3
SPT4
Channel 4 sample time selection
12
3
SPT5
Channel 5 sample time selection
15
3
SPT6
Channel 6 sample time selection
18
3
SPT7
Channel 7 sample time selection
21
3
SPT8
Channel 8 sample time selection
24
3
SPT9
Channel 9 sample time selection
27
3
STAT
STAT
status register
0x0
32
read-write
n
0x0
0x0
EOC
End of group conversion flag
1
1
EOIC
End of inserted group conversion flag
2
1
STIC
Start flag of inserted channel group
3
1
STRC
Start flag of regular channel group
4
1
WDE
Analog watchdog flag
0
1
WDHT
WDHT
watchdog higher threshold register
0x24
32
read-write
n
0x0
0x0
WDHT
Analog watchdog higher threshold
0
12
WDLT
WDLT
watchdog lower threshold register
0x28
32
read-write
n
0x0
0x0
WDLT
Analog watchdog lower threshold
0
12
CEC
HDMI-CEC controller
CEC
0x0
0x0
0x400
registers
n
CEC
30
CFG
CFG
Configuration register
0x4
32
read-write
n
0x0
0x0
BCNG
Do not generate Error-bit in broadcast message
7
1
BPLEG
Generate an Error-bit when detected BPLE in singlecast
6
1
BREG
Generate an Error-bit when detected BRE in singlecast
5
1
BRES
Whether stop receive message when detected BRE
4
1
LMEN
Listen mode enable
31
1
OAD
Own Address
16
15
RTOL
Reception bit timing tolerance
3
1
SFT
Signal Free Time
0
3
SFTOPT
The SFT start option bit
8
1
CTL
CTL
control register
0x0
32
read-write
n
0x0
0x0
CECEN
CEC controller Enable
0
1
ENDOM
ENDOM bit value in the next frame in TX mode
2
1
STAOM
Start of sending a message
1
1
INTEN
INTEN
interrupt enable register
0x14
32
read-write
n
0x0
0x0
ARBFIE
ARBF Interrupt Enable
7
1
BPLEIE
Long Bit Period Error Interrupt Enable
5
1
BPSEIE
Short Bit Period Error Interrupt Enable
4
1
BREIE
Bit Rising Error Interrupt Enable
3
1
BRIE
Rx-Byte Received Interrupt Enable
0
1
RAEIE
Rx-Missing Acknowledge Error Interrupt Enable
6
1
RENDIE
End Of Reception Interrupt Enable
1
1
ROIE
Rx-Buffer Overrun Interrupt Enable
2
1
TAERRIE
Tx-Missing Acknowledge Error Interrupt Enable
12
1
TBRIE
Tx-Byte Request Interrupt Enable
8
1
TERRIE
Tx-Error Interrupt Enable
11
1
TUIE
Tx-Underrun interrupt enable
10
1
TXENDIE
Tx-End of message interrupt enable
9
1
INTF
INTF
Interrupt Flag Register
0x10
32
read-write
n
0x0
0x0
ARBF
Arbitration fail
7
1
BPLE
Bit Period Long Error
5
1
BPSE
Bit period short error
4
1
BR
Rx-Byte Received
0
1
BRE
Bit rising error
3
1
RAE
Rx Acknowledge error
6
1
REND
End Of Reception
1
1
RO
Rx-Overrun
2
1
TAERR
Tx-Missing acknowledge error
12
1
TBR
Tx-Byte Request
8
1
TEND
End of Transmission
9
1
TERR
Tx-Error
11
1
TU
Tx-Buffer Underrun
10
1
RDATA
RDATA
Rx Data Register
0xC
32
read-only
n
0x0
0x0
RDATA
CEC Rx Data Register
0
8
TDATA
TDATA
Transmit data register
0x8
32
write-only
n
0x0
0x0
TDATA
Tx Data register
0
8
CMP
Comparator
Comparator
0x0
0x0
0x300
registers
n
ADC_CMP
12
CS
CS
control and status register
0x0
32
read-write
n
0x0
0x0
CMP0EN
Comparator 0 enable
0
1
read-write
CMP0HST
Comparator 0 hysteresis
12
2
read-write
CMP0LK
Comparator 0 lock
15
1
read-write
CMP0M
Comparator 0 mode
2
2
read-write
CMP0MSEL
Comparator 0 input selection
4
3
read-write
CMP0O
Comparator 0 output
14
1
read-only
CMP0OSEL
Comparator 0 output selection
8
3
read-write
CMP0PL
Polarity of comparator 0 output
11
1
read-write
CMP0SW
Comparator 0 switch
1
1
read-write
CMP1EN
Comparator 1 enable
16
1
read-write
CMP1HST
Comparator 1 hysteresis
28
2
read-write
CMP1LK
Comparator 1 lock
31
1
read-write
CMP1M
Comparator 1 mode
18
2
read-write
CMP1MSEL
Comparator 1 inverting input selection
20
3
read-write
CMP1O
Comparator 1 output
30
1
read-only
CMP1OSEL
Comparator 1 output selection
24
3
read-write
CMP1PL
Comparator 1 output polarity
27
1
read-write
WNDEN
Window mode enable
23
1
read-write
CRC
cyclic redundancy check calculation unit
CRC
0x0
0x0
0x400
registers
n
CTL
CTL
Control register
0x8
32
read-write
n
0x0
0x0
PS
Size of polynomial
3
2
REV_I
Reverse input data
5
2
REV_O
Reverse output data
7
1
RST
reset bit
0
1
DATA
DATA
Data register
0x0
32
read-write
n
0x0
0x0
DATA
CRC calculation result bits
0
32
FDATA
FDATA
Free data register
0x4
32
read-write
n
0x0
0x0
FDATA
General-purpose 8-bit data register bits
0
8
IDATA
IDATA
Initialization Data Register
0x10
32
read-write
n
0x0
0x0
IDATA
CRC calculation initial value
0
32
POLY
POLY
Polynomial register
0x14
32
read-write
n
0x0
0x0
POLY
User configurable polynomial value
0
32
CTC
Clock trim controller
CTC
0x0
0x0
0x400
registers
n
CTL0
CTL0
Control Register 0
0x0
32
read-write
n
0x0
0x0
AUTOTRIM
Hardware automatically trim mode
6
1
CKOKIE
Clock trim OK (CKOKIF) interrupt enable
0
1
CKWARNIE
Clock trim warning (CKWARNIF) interrupt enable
1
1
CNTEN
CTC counter enable
5
1
EREFIE
EREFIF interrupt enable
3
1
ERRIE
Error (ERRIF) interrupt enable
2
1
SWREFPUL
Software reference source sync pulse
7
1
TRIMVALUE
IRC48M trim value
8
6
CTL1
CTL1
Control Register 1
0x4
32
read-write
n
0x0
0x0
CKLIM
Clock trim base limit value
16
8
REFPOL
Reference signal source polarity
31
1
REFPSC
Reference signal source prescaler
24
3
REFSEL
Reference signal source selection
28
2
RLVALUE
CTC counter reload value
0
16
INTC
INTC
Interrupt clear Register
0xC
32
write-only
n
0x0
0x0
CKOKIC
CKOKIF interrupt clear bit
0
1
CKWARNIC
CKWARNIF interrupt clear bit
1
1
EREFIC
EREFIF interrupt clear bit
3
1
ERRIC
ERRIF interrupt clear bit
2
1
STAT
STAT
Status Register
0x8
32
read-only
n
0x0
0x0
CKERR
Clock trim error bit
8
1
CKOKIF
Clock trim OK interrupt flag
0
1
CKWARNIF
Clock trim warning interrupt flag
1
1
EREFIF
Expect reference interrupt flag
3
1
ERRIF
Error interrupt flag
2
1
REFCAP
CTC counter capture when reference sync pulse
16
16
REFDIR
CTC trim counter direction when reference sync pulse
15
1
REFMISS
Reference sync pulse miss
9
1
TRIMERR
Trim value error bit
10
1
DAC
Digital-to-analog converter
DAC
0x0
0x0
0x400
registers
n
CTL
CTL
control register
0x0
32
read-write
n
0x0
0x0
DBOFF
DAC output buffer disable
1
1
DDMAEN
DAC DMA enable
12
1
DDUDRIE
DAC DMA underrun interrupt enable
13
1
DEN
DAC enable
0
1
DTEN
DAC trigger enable
2
1
DTSEL
DAC trigger selection
3
3
DWBW
DAC noise wave bit width
8
4
DWM
DAC noise wave mode
6
2
DO
DAC_DO
DAC data output register
0x2C
32
read-only
n
0x0
0x0
DAC_DO
DAC data output
0
12
L12DH
DAC_L12DH
DAC 12-bit left aligned data holding register
0xC
32
read-write
n
0x0
0x0
DAC_DH
DAC 12-bit left-aligned data
4
12
R12DH
DAC_R12DH
DAC 12-bit right-aligned data holding register
0x8
32
read-write
n
0x0
0x0
DAC_DH
DAC 12-bit right-aligned data
0
12
R8DH
DAC_R8DH
DAC 8-bit right aligned data holding register
0x10
32
read-write
n
0x0
0x0
DAC_DH
DAC 8-bit right-aligned data
0
8
STAT
STAT
status register
0x34
32
read-write
n
0x0
0x0
DDUDR
DAC DMA underrun flag
13
1
SWT
SWT
software trigger register
0x4
32
write-only
n
0x0
0x0
SWTR
DAC software trigger
0
1
DBG
Debug support
DBG
0x0
0x0
0x400
registers
n
CTL0
CTL0
Debug Control Register 0
0x4
32
read-write
n
0x0
0x0
DSLP_HOLD
DEEPSLEEP mode hold Mode
1
1
FWDGT_HOLD
FWDGT hold register
8
1
I2C0_HOLD
I2C0 hold register
15
1
I2C1_HOLD
I2C1 hold register
16
1
SLP_HOLD
Sleep mode hold register
0
1
STB_HOLD
Standby mode hold Mode
2
1
TIMER0_HOLD
Timer 0 hold register
10
1
TIMER13_HOLD
Timer 13 hold register
27
1
TIMER1_HOLD
Timer 1 hold register
11
1
TIMER2_HOLD
Timer 2 hold register
12
1
TIMER5_HOLD
Timer 5 hold register
19
1
WWDGT_HOLD
WWDGT hold register
9
1
CTL1
CTL1
Debug Control Register 1
0x8
32
read-write
n
0x0
0x0
RTC_HOLD
RTC hold register
10
1
TIMER14_HOLD
Timer 14 hold register
16
1
TIMER15_HOLD
Timer 15 hold register
17
1
TIMER16_HOLD
Timer 16 hold register
18
1
ID
ID
MCU Device ID Code Register
0x0
32
read-only
n
0x0
0x0
ID_CODE
DBG ID code register
0
32
DMA
DMA controller
DMA
0x0
0x0
0x400
registers
n
DMA_Channel0
9
DMA_Channel1_2
10
DMA_Channel3_4
11
DMA_Channel5_6
48
CH0CNT
CH0CNT
DMA channel 0 counter register
0xC
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH0CTL
CH0CTL
DMA channel configuration register (DMA_CH0CTL)
0x8
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Transfer access error interrupt enable
3
1
FTFIE
Full Transfer Finish interrupt enable
1
1
HTFIE
Half Transfer Finish interrupt enable
2
1
M2M
Memory to memory mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority Level of this channel
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH0MADDR
CH0MADDR
DMA channel 0 memory base address register
0x14
32
read-write
n
0x0
0x0
MADDR
Memory address
0
32
CH0PADDR
CH0PADDR
DMA channel 0 peripheral base address register
0x10
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
CH1CNT
CH1CNT
DMA channel 1 counter register
0x20
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH1CTL
CH1CTL
DMA channel configuration register (DMA_CH1CTL)
0x1C
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Error interrupt enable
3
1
FTFIE
Full Transfer Finish interrupt enable
1
1
HTFIE
Half Transfer Finish interrupt enable
2
1
M2M
Memory to memory mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority Level of this channel
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH1MADDR
CH1MADDR
DMA channel 1 memory base address register
0x28
32
read-write
n
0x0
0x0
MADDR
Memory address
0
32
CH1PADDR
CH1PADDR
DMA channel 1 peripheral base address register
0x24
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
CH2CNT
CH2CNT
DMA channel 2 counter register
0x34
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH2CTL
CH2CTL
DMA channel configuration register (DMA_CH2CTL)
0x30
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Error interrupt enable
3
1
FTFIE
Full Transfer Finish interrupt enable
1
1
HTFIE
Half Transfer Finish interrupt enable
2
1
M2M
Memory to memory mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority Level of this channel
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH2MADDR
CH2MADDR
DMA channel 2 memory base address register
0x3C
32
read-write
n
0x0
0x0
MADDR
Memory address
0
32
CH2PADDR
CH2PADDR
DMA channel 2 peripheral base address register
0x38
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
CH3CNT
CH3CNT
DMA channel 3 counter register
0x48
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH3CTL
CH3CTL
DMA channel configuration register (DMA_CH3CTL)
0x44
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Error interrupt enable
3
1
FTFIE
Full Transfer Finish interrupt enable
1
1
HTFIE
Half Transfer Finish interrupt enable
2
1
M2M
Memory to memory mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority Level of this channel
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH3MADDR
CH3MADDR
DMA channel 3 memory base address register
0x50
32
read-write
n
0x0
0x0
MADDR
Memory address
0
32
CH3PADDR
CH3PADDR
DMA channel 3 peripheral base address register
0x4C
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
CH4CNT
CH4CNT
DMA channel 4 counter register
0x5C
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH4CTL
CH4CTL
DMA channel configuration register (DMA_CH4CTL)
0x58
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Error interrupt enable
3
1
FTFIE
Full Transfer Finish interrupt enable
1
1
HTFIE
Half Transfer Finish interrupt enable
2
1
M2M
Memory to memory mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority Level of this channel
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH4MADDR
CH4MADDR
DMA channel 4 memory base address register
0x64
32
read-write
n
0x0
0x0
MADDR
Memory address
0
32
CH4PADDR
CH4PADDR
DMA channel 4 peripheral base address register
0x60
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
CH5CNT
CH5CNT
DMA channel 5 counter register
0x70
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH5CTL
CH5CTL
DMA channel configuration register (DMA_CH5CTL)
0x6C
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Error interrupt enable
3
1
FTFIE
Full Transfer Finish interrupt enable
1
1
HTFIE
Half Transfer Finish interrupt enable
2
1
M2M
Memory to memory mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority Level of this channel
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH5MADDR
CH5MADDR
DMA channel 5 memory base address register
0x78
32
read-write
n
0x0
0x0
MADDR
Memory address
0
32
CH5PADDR
CH5PADDR
DMA channel 5 peripheral base address register
0x74
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
CH6CNT
CH6CNT
DMA channel 6 counter register
0x84
32
read-write
n
0x0
0x0
CNT
Transfer counter
0
16
CH6CTL
CH6CTL
DMA channel configuration register (DMA_CH6CTL)
0x80
32
read-write
n
0x0
0x0
CHEN
Channel enable
0
1
CMEN
Circular mode enable
5
1
DIR
Transfer direction
4
1
ERRIE
Error interrupt enable
3
1
FTFIE
Full Transfer Finish interrupt enable
1
1
HTFIE
Half Transfer Finish interrupt enable
2
1
M2M
Memory to memory mode
14
1
MNAGA
Next address generation algorithm of memory
7
1
MWIDTH
Transfer data size of memory
10
2
PNAGA
Next address generation algorithm of peripheral
6
1
PRIO
Priority Level of this channel
12
2
PWIDTH
Transfer data size of peripheral
8
2
CH6MADDR
CH6MADDR
DMA channel 6 memory base address register
0x8C
32
read-write
n
0x0
0x0
MADDR
Memory address
0
32
CH6PADDR
CH6PADDR
DMA channel 6 peripheral base address register
0x88
32
read-write
n
0x0
0x0
PADDR
Peripheral base address
0
32
INTC
INTC
DMA interrupt flag clear register (DMA_INTC)
0x4
32
write-only
n
0x0
0x0
ERRIFC0
Channel 0 Error clear
3
1
ERRIFC1
Channel 1 Error clear
7
1
ERRIFC2
Channel 2 Error clear
11
1
ERRIFC3
Channel 3 Error clear
15
1
ERRIFC4
Channel 4 Error clear
19
1
ERRIFC5
Channel 5 Error clear
23
1
ERRIFC6
Channel 6 Error clear
27
1
FTFIFC0
Channel 0 Full Transfer Finish clear
1
1
FTFIFC1
Channel 1 Full Transfer Finish clear
5
1
FTFIFC2
Channel 2 Full Transfer Finish clear
9
1
FTFIFC3
Channel 3 Full Transfer Finish clear
13
1
FTFIFC4
Channel 4 Full Transfer Finish clear
17
1
FTFIFC5
Channel 5 Full Transfer Finish clear
21
1
FTFIFC6
Channel 6 Full Transfer Finish clear
25
1
GIFC0
Channel 0 Global interrupt flag clear
0
1
GIFC1
Channel 1 Global interrupt flag clear
4
1
GIFC2
Channel 2 Global interrupt flag clear
8
1
GIFC3
Channel 3 Global interrupt flag clear
12
1
GIFC4
Channel 4 Global interrupt flag clear
16
1
GIFC5
Channel 5 Global interrupt flag clear
20
1
GIFC6
Channel 6 Global interrupt flag clear
24
1
HTFIFC0
Channel 0 Half Transfer clear
2
1
HTFIFC1
Channel 1 Half Transfer clear
6
1
HTFIFC2
Channel 2 Half Transfer clear
10
1
HTFIFC3
Channel 3 Half Transfer clear
14
1
HTFIFC4
Channel 4 Half Transfer clear
18
1
HTFIFC5
Channel 5 Half Transfer clear
22
1
HTFIFC6
Channel 6 Half Transfer clear
26
1
INTF
INTF
DMA interrupt flag register (DMA_INTF)
0x0
32
read-only
n
0x0
0x0
ERRIF0
Channel 0 Error flag
3
1
ERRIF1
Channel 1 Error flag
7
1
ERRIF2
Channel 2 Error flag
11
1
ERRIF3
Channel 3 Error flag
15
1
ERRIF4
Channel 4 Error flag
19
1
ERRIF5
Channel 5 Error flag
23
1
ERRIF6
Channel 6 Error flag
27
1
FTFIF0
Channel 0 Full Transfer Finish flag
1
1
FTFIF1
Channel 1 Full Transfer Finish flag
5
1
FTFIF2
Channel 2 Full Transfer Finish flag
9
1
FTFIF3
Channel 3 Full Transfer Finish flag
13
1
FTFIF4
Channel 4 Full Transfer Finish flag
17
1
FTFIF5
Channel 5 Full Transfer Finish flag
21
1
FTFIF6
Channel 6 Full Transfer Finish flag
25
1
GIF0
Channel 0 Global interrupt flag
0
1
GIF1
Channel 1 Global interrupt flag
4
1
GIF2
Channel 2 Global interrupt flag
8
1
GIF3
Channel 3 Global interrupt flag
12
1
GIF4
Channel 4 Global interrupt flag
16
1
GIF5
Channel 5 Global interrupt flag
20
1
GIF6
Channel 6 Global interrupt flag
24
1
HTFIF0
Channel 0 Half Transfer Finish flag
2
1
HTFIF1
Channel 1 Half Transfer Finish flag
6
1
HTFIF2
Channel 2 Half Transfer Finish flag
10
1
HTFIF3
Channel 3 Half Transfer Finish flag
14
1
HTFIF4
Channel 4 Half Transfer Finish flag
18
1
HTFIF5
Channel 5 Half Transfer Finish flag
22
1
HTFIF6
Channel 6 Half Transfer Finish flag
26
1
EXTI
External interrupt/event controller
EXTI
0x0
0x0
0x400
registers
n
LVD
1
EXTI0_1
5
EXTI2_3
6
EXTI4_15
7
EVEN
EVEN
Event enable register (EXTI_EVEN)
0x4
32
read-write
n
0x0
0x0
EVEN0
Enable Event on line 0
0
1
EVEN1
Enable Event on line 1
1
1
EVEN10
Enable Event on line 10
10
1
EVEN11
Enable Event on line 11
11
1
EVEN12
Enable Event on line 12
12
1
EVEN13
Enable Event on line 13
13
1
EVEN14
Enable Event on line 14
14
1
EVEN15
Enable Event on line 15
15
1
EVEN16
Enable Event on line 16
16
1
EVEN17
Enable Event on line 17
17
1
EVEN18
Enable Event on line 18
18
1
EVEN19
Enable Event on line 19
19
1
EVEN2
Enable Event on line 2
2
1
EVEN20
Enable Event on line 20
20
1
EVEN21
Enable Event on line 21
21
1
EVEN22
Enable Event on line 22
22
1
EVEN23
Enable Event on line 23
23
1
EVEN24
Enable Event on line 24
24
1
EVEN25
Enable Event on line 25
25
1
EVEN26
Enable Event on line 26
26
1
EVEN27
Enable Event on line 27
27
1
EVEN3
Enable Event on line 3
3
1
EVEN4
Enable Event on line 4
4
1
EVEN5
Enable Event on line 5
5
1
EVEN6
Enable Event on line 6
6
1
EVEN7
Enable Event on line 7
7
1
EVEN8
Enable Event on line 8
8
1
EVEN9
Enable Event on line 9
9
1
FTEN
FTEN
Falling Egde Trigger Enable register (EXTI_FTEN)
0xC
32
read-write
n
0x0
0x0
FTEN0
Falling trigger event configuration of line 0
0
1
FTEN1
Falling trigger event configuration of line 1
1
1
FTEN10
Falling trigger event configuration of line 10
10
1
FTEN11
Falling trigger event configuration of line 11
11
1
FTEN12
Falling trigger event configuration of line 12
12
1
FTEN13
Falling trigger event configuration of line 13
13
1
FTEN14
Falling trigger event configuration of line 14
14
1
FTEN15
Falling trigger event configuration of line 15
15
1
FTEN16
Falling trigger event configuration of line 16
16
1
FTEN17
Falling trigger event configuration of line 17
17
1
FTEN18
Falling trigger event configuration of line 18
18
1
FTEN19
Falling trigger event configuration of line 19
19
1
FTEN2
Falling trigger event configuration of line 2
2
1
FTEN21
Falling trigger event configuration of line 21
21
1
FTEN22
Falling trigger event configuration of line 22
22
1
FTEN3
Falling trigger event configuration of line 3
3
1
FTEN4
Falling trigger event configuration of line 4
4
1
FTEN5
Falling trigger event configuration of line 5
5
1
FTEN6
Falling trigger event configuration of line 6
6
1
FTEN7
Falling trigger event configuration of line 7
7
1
FTEN8
Falling trigger event configuration of line 8
8
1
FTEN9
Falling trigger event configuration of line 9
9
1
INTEN
INTEN
Interrupt enable register (EXTI_INTEN)
0x0
32
read-write
n
0x0
0x0
INTEN0
Enable Interrupt on line 0
0
1
INTEN1
Enable Interrupt on line 1
1
1
INTEN10
Enable Interrupt on line 10
10
1
INTEN11
Enable Interrupt on line 11
11
1
INTEN12
Enable Interrupt on line 12
12
1
INTEN13
Enable Interrupt on line 13
13
1
INTEN14
Enable Interrupt on line 14
14
1
INTEN15
Enable Interrupt on line 15
15
1
INTEN16
Enable Interrupt on line 16
16
1
INTEN17
Enable Interrupt on line 17
17
1
INTEN18
Enable Interrupt on line 18
18
1
INTEN19
Enable Interrupt on line 19
19
1
INTEN2
Enable Interrupt on line 2
2
1
INTEN20
Enable Interrupt on line 20
20
1
INTEN21
Enable Interrupt on line 21
21
1
INTEN22
Enable Interrupt on line 22
22
1
INTEN23
Enable Interrupt on line 23
23
1
INTEN24
Enable Interrupt on line 24
24
1
INTEN25
Enable Interrupt on line 25
25
1
INTEN26
Enable Interrupt on line 26
26
1
INTEN27
Enable Interrupt on line 27
27
1
INTEN3
Enable Interrupt on line 3
3
1
INTEN4
Enable Interrupt on line 4
4
1
INTEN5
Enable Interrupt on line 5
5
1
INTEN6
Enable Interrupt on line 6
6
1
INTEN7
Enable Interrupt on line 7
7
1
INTEN8
Enable Interrupt on line 8
8
1
INTEN9
Enable Interrupt on line 9
9
1
PD
PD
Pending register (EXTI_PD)
0x14
32
read-write
n
0x0
0x0
PD0
Pending bit 0
0
1
PD1
Pending bit 1
1
1
PD10
Pending bit 10
10
1
PD11
Pending bit 11
11
1
PD12
Pending bit 12
12
1
PD13
Pending bit 13
13
1
PD14
Pending bit 14
14
1
PD15
Pending bit 15
15
1
PD16
Pending bit 16
16
1
PD17
Pending bit 17
17
1
PD18
Pending bit 18
18
1
PD19
Pending bit 19
19
1
PD2
Pending bit 2
2
1
PD21
Pending bit 21
21
1
PD22
Pending bit 22
22
1
PD3
Pending bit 3
3
1
PD4
Pending bit 4
4
1
PD5
Pending bit 5
5
1
PD6
Pending bit 6
6
1
PD7
Pending bit 7
7
1
PD8
Pending bit 8
8
1
PD9
Pending bit 9
9
1
RTEN
RTEN
Rising Edge Trigger Enable register (EXTI_RTEN)
0x8
32
read-write
n
0x0
0x0
RTEN0
Rising trigger event configuration of line 0
0
1
RTEN1
Rising trigger event configuration of line 1
1
1
RTEN10
Rising trigger event configuration of line 10
10
1
RTEN11
Rising trigger event configuration of line 11
11
1
RTEN12
Rising trigger event configuration of line 12
12
1
RTEN13
Rising trigger event configuration of line 13
13
1
RTEN14
Rising trigger event configuration of line 14
14
1
RTEN15
Rising trigger event configuration of line 15
15
1
RTEN16
Rising trigger event configuration of line 16
16
1
RTEN17
Rising trigger event configuration of line 17
17
1
RTEN18
Rising trigger event configuration of line 18
18
1
RTEN19
Rising trigger event configuration of line 19
19
1
RTEN2
Rising trigger event configuration of line 2
2
1
RTEN21
Rising trigger event configuration of line 21
21
1
RTEN22
Rising trigger event configuration of line 22
22
1
RTEN3
Rising trigger event configuration of line 3
3
1
RTEN4
Rising trigger event configuration of line 4
4
1
RTEN5
Rising trigger event configuration of line 5
5
1
RTEN6
Rising trigger event configuration of line 6
6
1
RTEN7
Rising trigger event configuration of line 7
7
1
RTEN8
Rising trigger event configuration of line 8
8
1
RTEN9
Rising trigger event configuration of line 9
9
1
SWIEV
SWIEV
Software interrupt event register (EXTI_SWIEV)
0x10
32
read-write
n
0x0
0x0
SWIEV0
Software Interrupt on line 0
0
1
SWIEV1
Software Interrupt on line 1
1
1
SWIEV10
Software Interrupt on line 10
10
1
SWIEV11
Software Interrupt on line 11
11
1
SWIEV12
Software Interrupt on line 12
12
1
SWIEV13
Software Interrupt on line 13
13
1
SWIEV14
Software Interrupt on line 14
14
1
SWIEV15
Software Interrupt on line 15
15
1
SWIEV16
Software Interrupt on line 16
16
1
SWIEV17
Software Interrupt on line 17
17
1
SWIEV18
Software Interrupt on line 18
18
1
SWIEV19
Software Interrupt on line 19
19
1
SWIEV2
Software Interrupt on line 2
2
1
SWIEV21
Software Interrupt on line 21
21
1
SWIEV22
Software Interrupt on line 22
22
1
SWIEV3
Software Interrupt on line 3
3
1
SWIEV4
Software Interrupt on line 4
4
1
SWIEV5
Software Interrupt on line 5
5
1
SWIEV6
Software Interrupt on line 6
6
1
SWIEV7
Software Interrupt on line 7
7
1
SWIEV8
Software Interrupt on line 8
8
1
SWIEV9
Software Interrupt on line 9
9
1
FMC
FMC
FMC
0x0
0x0
0x400
registers
n
FMC
3
ADDR
ADDR
Flash address register
0x14
32
read-write
n
0x0
0x0
ADDR
Flash command address
0
32
CTL
CTL
Flash control register
0x10
32
read-write
n
0x0
0x0
ENDIE
End of operation interrupt enable
12
1
ERRIE
Error interrupt enable
10
1
LK
Lock
7
1
MER
Main flash mass erase command bit
2
1
OBER
Option byte erase
5
1
OBPG
Option byte programming
4
1
OBRLD
Option byte reload bit
13
1
OBWEN
Option bytes write enable
9
1
PER
Main flash page erase command bit
1
1
PG
Programming
0
1
START
Start
6
1
KEY
KEY
Flash unlock key register
0x4
32
write-only
n
0x0
0x0
KEY
FMC_CTL unlock register
0
32
OBKEY
OBKEY
Flash option byte unlock key register
0x8
32
write-only
n
0x0
0x0
OBKEY
Option byte key
0
32
OBSTAT
OBSTAT
Option byte status register
0x1C
32
read-only
n
0x0
0x0
OBERR
Option byte error
0
1
OB_DATA
OB_DATA
16
16
OB_USER
OB_USER
8
8
PLEVEL
PLEVEL
1
2
PID
PID
Flash Product ID register
0x100
32
read-only
n
0x0
0x0
PID
Product reserved ID code register1
0
32
STAT
STAT
Flash status register
0xC
32
read-write
n
0x0
0x0
BUSY
Busy
0
1
read-only
ENDF
End of operation flag bit
5
1
read-write
PGERR
Program error flag bit
2
1
read-write
WPERR
Erase/Program protection error flag bit
4
1
read-write
WP
WP
Write protection register
0x20
32
read-only
n
0x0
0x0
OB_WP
Write protect
0
16
WS
WS
Wait state register
0x0
32
read-write
n
0x0
0x0
WSCNT
WSCNT
0
3
read-write
WSEN
WSEN
Flash wait state control register
0xFC
32
read-only
n
0x0
0x0
BPEN
FMC bit program enable register
1
1
WSEN
FMC wait state enable register
0
1
FWDGT
free watchdog timer
FWDGT
0x0
0x0
0x400
registers
n
CTL
CTL
Control register
0x0
32
write-only
n
0x0
0x0
CMD
Key value
0
16
PSC
PSC
Prescaler register
0x4
32
read-write
n
0x0
0x0
PSC
Prescaler divider
0
3
RLD
RLD
Reload register
0x8
32
read-write
n
0x0
0x0
RLD
Watchdog counter reload value
0
12
STAT
STAT
Status register
0xC
32
read-only
n
0x0
0x0
PUD
Watchdog prescaler value update
0
1
RUD
Watchdog counter reload value update
1
1
WUD
Watchdog counter window value update
2
1
WND
WND
Window register
0x10
32
read-only
n
0x0
0x0
WND
Watchdog counter window value
0
12
GPIOA
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFSEL0
AFSEL0
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
SEL0
Alternate function selection for port x bit y (y = 0..7)
0
4
SEL1
Alternate function selection for port x bit y (y = 0..7)
4
4
SEL2
Alternate function selection for port x bit y (y = 0..7)
8
4
SEL3
Alternate function selection for port x bit y (y = 0..7)
12
4
SEL4
Alternate function selection for port x bit y (y = 0..7)
16
4
SEL5
Alternate function selection for port x bit y (y = 0..7)
20
4
SEL6
Alternate function selection for port x bit y (y = 0..7)
24
4
SEL7
Alternate function selection for port x bit y (y = 0..7)
28
4
AFSEL1
AFSEL1
GPIO alternate function register 1
0x24
32
read-write
n
0x0
0x0
SEL10
Alternate function selection for port x bit y (y = 8..15)
8
4
SEL11
Alternate function selection for port x bit y (y = 8..15)
12
4
SEL12
Alternate function selection for port x bit y (y = 8..15)
16
4
SEL13
Alternate function selection for port x bit y (y = 8..15)
20
4
SEL14
Alternate function selection for port x bit y (y = 8..15)
24
4
SEL15
Alternate function selection for port x bit y (y = 8..15)
28
4
SEL8
Alternate function selection for port x bit y (y = 8..15)
0
4
SEL9
Alternate function selection for port x bit y (y = 8..15)
4
4
BC
BC
Port bit reset register
0x28
32
write-only
n
0x0
0x0
CR0
Port cleat bit
0
1
CR1
Port cleat bit
1
1
CR10
Port cleat bit
10
1
CR11
Port cleat bit
11
1
CR12
Port cleat bit
12
1
CR13
Port cleat bit
13
1
CR14
Port cleat bit
14
1
CR15
Port cleat bit
15
1
CR2
Port cleat bit
2
1
CR3
Port cleat bit
3
1
CR4
Port cleat bit
4
1
CR5
Port cleat bit
5
1
CR6
Port cleat bit
6
1
CR7
Port cleat bit
7
1
CR8
Port cleat bit
8
1
CR9
Port cleat bit
9
1
BOP
BOP
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BOP0
Port x set bit y (y= 0..15)
0
1
BOP1
Port x set bit y (y= 0..15)
1
1
BOP10
Port x set bit y (y= 0..15)
10
1
BOP11
Port x set bit y (y= 0..15)
11
1
BOP12
Port x set bit y (y= 0..15)
12
1
BOP13
Port x set bit y (y= 0..15)
13
1
BOP14
Port x set bit y (y= 0..15)
14
1
BOP15
Port x set bit y (y= 0..15)
15
1
BOP2
Port x set bit y (y= 0..15)
2
1
BOP3
Port x set bit y (y= 0..15)
3
1
BOP4
Port x set bit y (y= 0..15)
4
1
BOP5
Port x set bit y (y= 0..15)
5
1
BOP6
Port x set bit y (y= 0..15)
6
1
BOP7
Port x set bit y (y= 0..15)
7
1
BOP8
Port x set bit y (y= 0..15)
8
1
BOP9
Port x set bit y (y= 0..15)
9
1
CR0
Port x reset bit y (y= 0..15)
16
1
CR1
Port x reset bit y (y = 0..15)
17
1
CR10
Port x reset bit y (y = 0..15)
26
1
CR11
Port x reset bit y (y = 0..15)
27
1
CR12
Port x reset bit y (y = 0..15)
28
1
CR13
Port x reset bit y (y = 0..15)
29
1
CR14
Port x reset bit y (y = 0..15)
30
1
CR15
Port x reset bit y (y = 0..15)
31
1
CR2
Port x reset bit y (y = 0..15)
18
1
CR3
Port x reset bit y (y = 0..15)
19
1
CR4
Port x reset bit y (y = 0..15)
20
1
CR5
Port x reset bit y (y = 0..15)
21
1
CR6
Port x reset bit y (y = 0..15)
22
1
CR7
Port x reset bit y (y = 0..15)
23
1
CR8
Port x reset bit y (y = 0..15)
24
1
CR9
Port x reset bit y (y = 0..15)
25
1
CTL
CTL
GPIO port control register
0x0
32
read-write
n
0x0
0x0
CTL0
Port x configuration bits (y = 0..15)
0
2
CTL1
Port x configuration bits (y = 0..15)
2
2
CTL10
Port x configuration bits (y = 0..15)
20
2
CTL11
Port x configuration bits (y = 0..15)
22
2
CTL12
Port x configuration bits (y = 0..15)
24
2
CTL13
Port x configuration bits (y = 0..15)
26
2
CTL14
Port x configuration bits (y = 0..15)
28
2
CTL15
Port x configuration bits (y = 0..15)
30
2
CTL2
Port x configuration bits (y = 0..15)
4
2
CTL3
Port x configuration bits (y = 0..15)
6
2
CTL4
Port x configuration bits (y = 0..15)
8
2
CTL5
Port x configuration bits (y = 0..15)
10
2
CTL6
Port x configuration bits (y = 0..15)
12
2
CTL7
Port x configuration bits (y = 0..15)
14
2
CTL8
Port x configuration bits (y = 0..15)
16
2
CTL9
Port x configuration bits (y = 0..15)
18
2
ISTAT
ISTAT
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
ISTAT0
Port input data (y = 0..15)
0
1
ISTAT1
Port input data (y = 0..15)
1
1
ISTAT10
Port input data (y = 0..15)
10
1
ISTAT11
Port input data (y = 0..15)
11
1
ISTAT12
Port input data (y = 0..15)
12
1
ISTAT13
Port input data (y = 0..15)
13
1
ISTAT14
Port input data (y = 0..15)
14
1
ISTAT15
Port input data (y = 0..15)
15
1
ISTAT2
Port input data (y = 0..15)
2
1
ISTAT3
Port input data (y = 0..15)
3
1
ISTAT4
Port input data (y = 0..15)
4
1
ISTAT5
Port input data (y = 0..15)
5
1
ISTAT6
Port input data (y = 0..15)
6
1
ISTAT7
Port input data (y = 0..15)
7
1
ISTAT8
Port input data (y = 0..15)
8
1
ISTAT9
Port input data (y = 0..15)
9
1
LOCK
LOCK
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LK0
Port x lock bit y (y= 0..15)
0
1
LK1
Port x lock bit y (y= 0..15)
1
1
LK10
Port x lock bit y (y= 0..15)
10
1
LK11
Port x lock bit y (y= 0..15)
11
1
LK12
Port x lock bit y (y= 0..15)
12
1
LK13
Port x lock bit y (y= 0..15)
13
1
LK14
Port x lock bit y (y= 0..15)
14
1
LK15
Port x lock bit y (y= 0..15)
15
1
LK2
Port x lock bit y (y= 0..15)
2
1
LK3
Port x lock bit y (y= 0..15)
3
1
LK4
Port x lock bit y (y= 0..15)
4
1
LK5
Port x lock bit y (y= 0..15)
5
1
LK6
Port x lock bit y (y= 0..15)
6
1
LK7
Port x lock bit y (y= 0..15)
7
1
LK8
Port x lock bit y (y= 0..15)
8
1
LK9
Port x lock bit y (y= 0..15)
9
1
LKK
Port x lock bit y
16
1
OCTL
OCTL
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
OCTL0
Port output data (y = 0..15)
0
1
OCTL1
Port output data (y = 0..15)
1
1
OCTL10
Port output data (y = 0..15)
10
1
OCTL11
Port output data (y = 0..15)
11
1
OCTL12
Port output data (y = 0..15)
12
1
OCTL13
Port output data (y = 0..15)
13
1
OCTL14
Port output data (y = 0..15)
14
1
OCTL15
Port output data (y = 0..15)
15
1
OCTL2
Port output data (y = 0..15)
2
1
OCTL3
Port output data (y = 0..15)
3
1
OCTL4
Port output data (y = 0..15)
4
1
OCTL5
Port output data (y = 0..15)
5
1
OCTL6
Port output data (y = 0..15)
6
1
OCTL7
Port output data (y = 0..15)
7
1
OCTL8
Port output data (y = 0..15)
8
1
OCTL9
Port output data (y = 0..15)
9
1
OMODE
OMODE
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OM0
Port x configuration bit 0
0
1
OM1
Port x configuration bit 1
1
1
OM10
Port x configuration bit 10
10
1
OM11
Port x configuration bit 11
11
1
OM12
Port x configuration bit 12
12
1
OM13
Port x configuration bit 13
13
1
OM14
Port x configuration bit 14
14
1
OM15
Port x configuration bit 15
15
1
OM2
Port x configuration bit 2
2
1
OM3
Port x configuration bit 3
3
1
OM4
Port x configuration bit 4
4
1
OM5
Port x configuration bit 5
5
1
OM6
Port x configuration bit 6
6
1
OM7
Port x configuration bit 7
7
1
OM8
Port x configuration bit 8
8
1
OM9
Port x configuration bit 9
9
1
OSPD0
OSPD0
GPIO port output speed register 0
0x8
32
read-write
n
0x0
0x0
OSPD0
Port x configuration bits (y = 0..15)
0
2
OSPD1
Port x configuration bits (y = 0..15)
2
2
OSPD10
Port x configuration bits (y = 0..15)
20
2
OSPD11
Port x configuration bits (y = 0..15)
22
2
OSPD12
Port x configuration bits (y = 0..15)
24
2
OSPD13
Port x configuration bits (y = 0..15)
26
2
OSPD14
Port x configuration bits (y = 0..15)
28
2
OSPD15
Port x configuration bits (y = 0..15)
30
2
OSPD2
Port x configuration bits (y = 0..15)
4
2
OSPD3
Port x configuration bits (y = 0..15)
6
2
OSPD4
Port x configuration bits (y = 0..15)
8
2
OSPD5
Port x configuration bits (y = 0..15)
10
2
OSPD6
Port x configuration bits (y = 0..15)
12
2
OSPD7
Port x configuration bits (y = 0..15)
14
2
OSPD8
Port x configuration bits (y = 0..15)
16
2
OSPD9
Port x configuration bits (y = 0..15)
18
2
OSPD1
OSPD1
Port output speed register 1
0x3C
32
read-write
n
0x0
0x0
SPD0
Set Very High output speed when OSPDy(y=0..15) is 0b11
0
1
SPD1
Set Very High output speed when OSPDy(y=0..15) is 0b11
1
1
SPD10
Set Very High output speed when OSPDy(y=0..15) is 0b11
10
1
SPD11
Set Very High output speed when OSPDy(y=0..15) is 0b11
11
1
SPD12
Set Very High output speed when OSPDy(y=0..15) is 0b11
12
1
SPD13
Set Very High output speed when OSPDy(y=0..15) is 0b11
13
1
SPD14
Set Very High output speed when OSPDy(y=0..15) is 0b11
14
1
SPD15
Set Very High output speed when OSPDy(y=0..15) is 0b11
15
1
SPD2
Set Very High output speed when OSPDy(y=0..15) is 0b11
2
1
SPD3
Set Very High output speed when OSPDy(y=0..15) is 0b11
3
1
SPD4
Set Very High output speed when OSPDy(y=0..15) is 0b11
4
1
SPD5
Set Very High output speed when OSPDy(y=0..15) is 0b11
5
1
SPD6
Set Very High output speed when OSPDy(y=0..15) is 0b11
6
1
SPD7
Set Very High output speed when OSPDy(y=0..15) is 0b11
7
1
SPD8
Set Very High output speed when OSPDy(y=0..15) is 0b11
8
1
SPD9
Set Very High output speed when OSPDy(y=0..15) is 0b11
9
1
PUD
PUD
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUD0
Port x configuration bits (y = 0..15)
0
2
PUD1
Port x configuration bits (y = 0..15)
2
2
PUD10
Port x configuration bits (y = 0..15)
20
2
PUD11
Port x configuration bits (y = 0..15)
22
2
PUD12
Port x configuration bits (y = 0..15)
24
2
PUD13
Port x configuration bits (y = 0..15)
26
2
PUD14
Port x configuration bits (y = 0..15)
28
2
PUD15
Port x configuration bits (y = 0..15)
30
2
PUD2
Port x configuration bits (y = 0..15)
4
2
PUD3
Port x configuration bits (y = 0..15)
6
2
PUD4
Port x configuration bits (y = 0..15)
8
2
PUD5
Port x configuration bits (y = 0..15)
10
2
PUD6
Port x configuration bits (y = 0..15)
12
2
PUD7
Port x configuration bits (y = 0..15)
14
2
PUD8
Port x configuration bits (y = 0..15)
16
2
PUD9
Port x configuration bits (y = 0..15)
18
2
TG
TG
Port bit toggle register
0x2C
32
write-only
n
0x0
0x0
TG0
Port toggle bit
0
1
TG1
Port toggle bit
1
1
TG10
Port toggle bit
10
1
TG11
Port toggle bit
11
1
TG12
Port toggle bit
12
1
TG13
Port toggle bit
13
1
TG14
Port toggle bit
14
1
TG15
Port toggle bit
15
1
TG2
Port toggle bit
2
1
TG3
Port toggle bit
3
1
TG4
Port toggle bit
4
1
TG5
Port toggle bit
5
1
TG6
Port toggle bit
6
1
TG7
Port toggle bit
7
1
TG8
Port toggle bit
8
1
TG9
Port toggle bit
9
1
GPIOB
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFSEL0
AFSEL0
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
SEL0
Alternate function selection for port x bit y (y = 0..7)
0
4
SEL1
Alternate function selection for port x bit y (y = 0..7)
4
4
SEL2
Alternate function selection for port x bit y (y = 0..7)
8
4
SEL3
Alternate function selection for port x bit y (y = 0..7)
12
4
SEL4
Alternate function selection for port x bit y (y = 0..7)
16
4
SEL5
Alternate function selection for port x bit y (y = 0..7)
20
4
SEL6
Alternate function selection for port x bit y (y = 0..7)
24
4
SEL7
Alternate function selection for port x bit y (y = 0..7)
28
4
AFSEL1
AFSEL1
GPIO alternate function register 1
0x24
32
read-write
n
0x0
0x0
SEL10
Alternate function selection for port x bit y (y = 8..15)
8
4
SEL11
Alternate function selection for port x bit y (y = 8..15)
12
4
SEL12
Alternate function selection for port x bit y (y = 8..15)
16
4
SEL13
Alternate function selection for port x bit y (y = 8..15)
20
4
SEL14
Alternate function selection for port x bit y (y = 8..15)
24
4
SEL15
Alternate function selection for port x bit y (y = 8..15)
28
4
SEL8
Alternate function selection for port x bit y (y = 8..15)
0
4
SEL9
Alternate function selection for port x bit y (y = 8..15)
4
4
BC
BC
Port bit reset register
0x28
32
write-only
n
0x0
0x0
CR0
Port cleat bit
0
1
CR1
Port cleat bit
1
1
CR10
Port cleat bit
10
1
CR11
Port cleat bit
11
1
CR12
Port cleat bit
12
1
CR13
Port cleat bit
13
1
CR14
Port cleat bit
14
1
CR15
Port cleat bit
15
1
CR2
Port cleat bit
2
1
CR3
Port cleat bit
3
1
CR4
Port cleat bit
4
1
CR5
Port cleat bit
5
1
CR6
Port cleat bit
6
1
CR7
Port cleat bit
7
1
CR8
Port cleat bit
8
1
CR9
Port cleat bit
9
1
BOP
BOP
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BOP0
Port x set bit y (y= 0..15)
0
1
BOP1
Port x set bit y (y= 0..15)
1
1
BOP10
Port x set bit y (y= 0..15)
10
1
BOP11
Port x set bit y (y= 0..15)
11
1
BOP12
Port x set bit y (y= 0..15)
12
1
BOP13
Port x set bit y (y= 0..15)
13
1
BOP14
Port x set bit y (y= 0..15)
14
1
BOP15
Port x set bit y (y= 0..15)
15
1
BOP2
Port x set bit y (y= 0..15)
2
1
BOP3
Port x set bit y (y= 0..15)
3
1
BOP4
Port x set bit y (y= 0..15)
4
1
BOP5
Port x set bit y (y= 0..15)
5
1
BOP6
Port x set bit y (y= 0..15)
6
1
BOP7
Port x set bit y (y= 0..15)
7
1
BOP8
Port x set bit y (y= 0..15)
8
1
BOP9
Port x set bit y (y= 0..15)
9
1
CR0
Port x reset bit y (y= 0..15)
16
1
CR1
Port x reset bit y (y = 0..15)
17
1
CR10
Port x reset bit y (y = 0..15)
26
1
CR11
Port x reset bit y (y = 0..15)
27
1
CR12
Port x reset bit y (y = 0..15)
28
1
CR13
Port x reset bit y (y = 0..15)
29
1
CR14
Port x reset bit y (y = 0..15)
30
1
CR15
Port x reset bit y (y = 0..15)
31
1
CR2
Port x reset bit y (y = 0..15)
18
1
CR3
Port x reset bit y (y = 0..15)
19
1
CR4
Port x reset bit y (y = 0..15)
20
1
CR5
Port x reset bit y (y = 0..15)
21
1
CR6
Port x reset bit y (y = 0..15)
22
1
CR7
Port x reset bit y (y = 0..15)
23
1
CR8
Port x reset bit y (y = 0..15)
24
1
CR9
Port x reset bit y (y = 0..15)
25
1
CTL
CTL
GPIO port control register
0x0
32
read-write
n
0x0
0x0
CTL0
Port x configuration bits (y = 0..15)
0
2
CTL1
Port x configuration bits (y = 0..15)
2
2
CTL10
Port x configuration bits (y = 0..15)
20
2
CTL11
Port x configuration bits (y = 0..15)
22
2
CTL12
Port x configuration bits (y = 0..15)
24
2
CTL13
Port x configuration bits (y = 0..15)
26
2
CTL14
Port x configuration bits (y = 0..15)
28
2
CTL15
Port x configuration bits (y = 0..15)
30
2
CTL2
Port x configuration bits (y = 0..15)
4
2
CTL3
Port x configuration bits (y = 0..15)
6
2
CTL4
Port x configuration bits (y = 0..15)
8
2
CTL5
Port x configuration bits (y = 0..15)
10
2
CTL6
Port x configuration bits (y = 0..15)
12
2
CTL7
Port x configuration bits (y = 0..15)
14
2
CTL8
Port x configuration bits (y = 0..15)
16
2
CTL9
Port x configuration bits (y = 0..15)
18
2
ISTAT
ISTAT
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
ISTAT0
Port input data (y = 0..15)
0
1
ISTAT1
Port input data (y = 0..15)
1
1
ISTAT10
Port input data (y = 0..15)
10
1
ISTAT11
Port input data (y = 0..15)
11
1
ISTAT12
Port input data (y = 0..15)
12
1
ISTAT13
Port input data (y = 0..15)
13
1
ISTAT14
Port input data (y = 0..15)
14
1
ISTAT15
Port input data (y = 0..15)
15
1
ISTAT2
Port input data (y = 0..15)
2
1
ISTAT3
Port input data (y = 0..15)
3
1
ISTAT4
Port input data (y = 0..15)
4
1
ISTAT5
Port input data (y = 0..15)
5
1
ISTAT6
Port input data (y = 0..15)
6
1
ISTAT7
Port input data (y = 0..15)
7
1
ISTAT8
Port input data (y = 0..15)
8
1
ISTAT9
Port input data (y = 0..15)
9
1
LOCK
LOCK
GPIO port configuration lock register
0x1C
32
read-write
n
0x0
0x0
LK0
Port x lock bit y (y= 0..15)
0
1
LK1
Port x lock bit y (y= 0..15)
1
1
LK10
Port x lock bit y (y= 0..15)
10
1
LK11
Port x lock bit y (y= 0..15)
11
1
LK12
Port x lock bit y (y= 0..15)
12
1
LK13
Port x lock bit y (y= 0..15)
13
1
LK14
Port x lock bit y (y= 0..15)
14
1
LK15
Port x lock bit y (y= 0..15)
15
1
LK2
Port x lock bit y (y= 0..15)
2
1
LK3
Port x lock bit y (y= 0..15)
3
1
LK4
Port x lock bit y (y= 0..15)
4
1
LK5
Port x lock bit y (y= 0..15)
5
1
LK6
Port x lock bit y (y= 0..15)
6
1
LK7
Port x lock bit y (y= 0..15)
7
1
LK8
Port x lock bit y (y= 0..15)
8
1
LK9
Port x lock bit y (y= 0..15)
9
1
LKK
Port x lock bit y
16
1
OCTL
OCTL
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
OCTL0
Port output data (y = 0..15)
0
1
OCTL1
Port output data (y = 0..15)
1
1
OCTL10
Port output data (y = 0..15)
10
1
OCTL11
Port output data (y = 0..15)
11
1
OCTL12
Port output data (y = 0..15)
12
1
OCTL13
Port output data (y = 0..15)
13
1
OCTL14
Port output data (y = 0..15)
14
1
OCTL15
Port output data (y = 0..15)
15
1
OCTL2
Port output data (y = 0..15)
2
1
OCTL3
Port output data (y = 0..15)
3
1
OCTL4
Port output data (y = 0..15)
4
1
OCTL5
Port output data (y = 0..15)
5
1
OCTL6
Port output data (y = 0..15)
6
1
OCTL7
Port output data (y = 0..15)
7
1
OCTL8
Port output data (y = 0..15)
8
1
OCTL9
Port output data (y = 0..15)
9
1
OMODE
OMODE
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OM0
Port x configuration bit 0
0
1
OM1
Port x configuration bit 1
1
1
OM10
Port x configuration bit 10
10
1
OM11
Port x configuration bit 11
11
1
OM12
Port x configuration bit 12
12
1
OM13
Port x configuration bit 13
13
1
OM14
Port x configuration bit 14
14
1
OM15
Port x configuration bit 15
15
1
OM2
Port x configuration bit 2
2
1
OM3
Port x configuration bit 3
3
1
OM4
Port x configuration bit 4
4
1
OM5
Port x configuration bit 5
5
1
OM6
Port x configuration bit 6
6
1
OM7
Port x configuration bit 7
7
1
OM8
Port x configuration bit 8
8
1
OM9
Port x configuration bit 9
9
1
OSPD0
OSPD0
GPIO port output speed register 0
0x8
32
read-write
n
0x0
0x0
OSPD0
Port x configuration bits (y = 0..15)
0
2
OSPD1
Port x configuration bits (y = 0..15)
2
2
OSPD10
Port x configuration bits (y = 0..15)
20
2
OSPD11
Port x configuration bits (y = 0..15)
22
2
OSPD12
Port x configuration bits (y = 0..15)
24
2
OSPD13
Port x configuration bits (y = 0..15)
26
2
OSPD14
Port x configuration bits (y = 0..15)
28
2
OSPD15
Port x configuration bits (y = 0..15)
30
2
OSPD2
Port x configuration bits (y = 0..15)
4
2
OSPD3
Port x configuration bits (y = 0..15)
6
2
OSPD4
Port x configuration bits (y = 0..15)
8
2
OSPD5
Port x configuration bits (y = 0..15)
10
2
OSPD6
Port x configuration bits (y = 0..15)
12
2
OSPD7
Port x configuration bits (y = 0..15)
14
2
OSPD8
Port x configuration bits (y = 0..15)
16
2
OSPD9
Port x configuration bits (y = 0..15)
18
2
OSPD1
OSPD1
Port output speed register 1
0x3C
32
read-write
n
0x0
0x0
SPD0
Set Very High output speed when OSPDy(y=0..15) is 0b11
0
1
SPD1
Set Very High output speed when OSPDy(y=0..15) is 0b11
1
1
SPD10
Set Very High output speed when OSPDy(y=0..15) is 0b11
10
1
SPD11
Set Very High output speed when OSPDy(y=0..15) is 0b11
11
1
SPD12
Set Very High output speed when OSPDy(y=0..15) is 0b11
12
1
SPD13
Set Very High output speed when OSPDy(y=0..15) is 0b11
13
1
SPD14
Set Very High output speed when OSPDy(y=0..15) is 0b11
14
1
SPD15
Set Very High output speed when OSPDy(y=0..15) is 0b11
15
1
SPD2
Set Very High output speed when OSPDy(y=0..15) is 0b11
2
1
SPD3
Set Very High output speed when OSPDy(y=0..15) is 0b11
3
1
SPD4
Set Very High output speed when OSPDy(y=0..15) is 0b11
4
1
SPD5
Set Very High output speed when OSPDy(y=0..15) is 0b11
5
1
SPD6
Set Very High output speed when OSPDy(y=0..15) is 0b11
6
1
SPD7
Set Very High output speed when OSPDy(y=0..15) is 0b11
7
1
SPD8
Set Very High output speed when OSPDy(y=0..15) is 0b11
8
1
SPD9
Set Very High output speed when OSPDy(y=0..15) is 0b11
9
1
PUD
PUD
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUD0
Port x configuration bits (y = 0..15)
0
2
PUD1
Port x configuration bits (y = 0..15)
2
2
PUD10
Port x configuration bits (y = 0..15)
20
2
PUD11
Port x configuration bits (y = 0..15)
22
2
PUD12
Port x configuration bits (y = 0..15)
24
2
PUD13
Port x configuration bits (y = 0..15)
26
2
PUD14
Port x configuration bits (y = 0..15)
28
2
PUD15
Port x configuration bits (y = 0..15)
30
2
PUD2
Port x configuration bits (y = 0..15)
4
2
PUD3
Port x configuration bits (y = 0..15)
6
2
PUD4
Port x configuration bits (y = 0..15)
8
2
PUD5
Port x configuration bits (y = 0..15)
10
2
PUD6
Port x configuration bits (y = 0..15)
12
2
PUD7
Port x configuration bits (y = 0..15)
14
2
PUD8
Port x configuration bits (y = 0..15)
16
2
PUD9
Port x configuration bits (y = 0..15)
18
2
TG
TG
Port bit toggle register
0x2C
32
write-only
n
0x0
0x0
TG0
Port toggle bit
0
1
TG1
Port toggle bit
1
1
TG10
Port toggle bit
10
1
TG11
Port toggle bit
11
1
TG12
Port toggle bit
12
1
TG13
Port toggle bit
13
1
TG14
Port toggle bit
14
1
TG15
Port toggle bit
15
1
TG2
Port toggle bit
2
1
TG3
Port toggle bit
3
1
TG4
Port toggle bit
4
1
TG5
Port toggle bit
5
1
TG6
Port toggle bit
6
1
TG7
Port toggle bit
7
1
TG8
Port toggle bit
8
1
TG9
Port toggle bit
9
1
GPIOC
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
AFSEL0
AFSEL0
GPIO alternate function low register
0x20
32
read-write
n
0x0
0x0
SEL0
Alternate function selection for port x bit y (y = 0..7)
0
4
SEL1
Alternate function selection for port x bit y (y = 0..7)
4
4
SEL2
Alternate function selection for port x bit y (y = 0..7)
8
4
SEL3
Alternate function selection for port x bit y (y = 0..7)
12
4
SEL4
Alternate function selection for port x bit y (y = 0..7)
16
4
SEL5
Alternate function selection for port x bit y (y = 0..7)
20
4
SEL6
Alternate function selection for port x bit y (y = 0..7)
24
4
SEL7
Alternate function selection for port x bit y (y = 0..7)
28
4
AFSEL1
AFSEL1
GPIO alternate function register 1
0x24
32
read-write
n
0x0
0x0
SEL10
Alternate function selection for port x bit y (y = 8..15)
8
4
SEL11
Alternate function selection for port x bit y (y = 8..15)
12
4
SEL12
Alternate function selection for port x bit y (y = 8..15)
16
4
SEL13
Alternate function selection for port x bit y (y = 8..15)
20
4
SEL14
Alternate function selection for port x bit y (y = 8..15)
24
4
SEL15
Alternate function selection for port x bit y (y = 8..15)
28
4
SEL8
Alternate function selection for port x bit y (y = 8..15)
0
4
SEL9
Alternate function selection for port x bit y (y = 8..15)
4
4
BC
BC
Port bit reset register
0x28
32
write-only
n
0x0
0x0
CR0
Port cleat bit
0
1
CR1
Port cleat bit
1
1
CR10
Port cleat bit
10
1
CR11
Port cleat bit
11
1
CR12
Port cleat bit
12
1
CR13
Port cleat bit
13
1
CR14
Port cleat bit
14
1
CR15
Port cleat bit
15
1
CR2
Port cleat bit
2
1
CR3
Port cleat bit
3
1
CR4
Port cleat bit
4
1
CR5
Port cleat bit
5
1
CR6
Port cleat bit
6
1
CR7
Port cleat bit
7
1
CR8
Port cleat bit
8
1
CR9
Port cleat bit
9
1
BOP
BOP
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BOP0
Port x set bit y (y= 0..15)
0
1
BOP1
Port x set bit y (y= 0..15)
1
1
BOP10
Port x set bit y (y= 0..15)
10
1
BOP11
Port x set bit y (y= 0..15)
11
1
BOP12
Port x set bit y (y= 0..15)
12
1
BOP13
Port x set bit y (y= 0..15)
13
1
BOP14
Port x set bit y (y= 0..15)
14
1
BOP15
Port x set bit y (y= 0..15)
15
1
BOP2
Port x set bit y (y= 0..15)
2
1
BOP3
Port x set bit y (y= 0..15)
3
1
BOP4
Port x set bit y (y= 0..15)
4
1
BOP5
Port x set bit y (y= 0..15)
5
1
BOP6
Port x set bit y (y= 0..15)
6
1
BOP7
Port x set bit y (y= 0..15)
7
1
BOP8
Port x set bit y (y= 0..15)
8
1
BOP9
Port x set bit y (y= 0..15)
9
1
CR0
Port x reset bit y (y= 0..15)
16
1
CR1
Port x reset bit y (y = 0..15)
17
1
CR10
Port x reset bit y (y = 0..15)
26
1
CR11
Port x reset bit y (y = 0..15)
27
1
CR12
Port x reset bit y (y = 0..15)
28
1
CR13
Port x reset bit y (y = 0..15)
29
1
CR14
Port x reset bit y (y = 0..15)
30
1
CR15
Port x reset bit y (y = 0..15)
31
1
CR2
Port x reset bit y (y = 0..15)
18
1
CR3
Port x reset bit y (y = 0..15)
19
1
CR4
Port x reset bit y (y = 0..15)
20
1
CR5
Port x reset bit y (y = 0..15)
21
1
CR6
Port x reset bit y (y = 0..15)
22
1
CR7
Port x reset bit y (y = 0..15)
23
1
CR8
Port x reset bit y (y = 0..15)
24
1
CR9
Port x reset bit y (y = 0..15)
25
1
CTL
CTL
GPIO port control register
0x0
32
read-write
n
0x0
0x0
CTL0
Port x configuration bits (y = 0..15)
0
2
CTL1
Port x configuration bits (y = 0..15)
2
2
CTL10
Port x configuration bits (y = 0..15)
20
2
CTL11
Port x configuration bits (y = 0..15)
22
2
CTL12
Port x configuration bits (y = 0..15)
24
2
CTL13
Port x configuration bits (y = 0..15)
26
2
CTL14
Port x configuration bits (y = 0..15)
28
2
CTL15
Port x configuration bits (y = 0..15)
30
2
CTL2
Port x configuration bits (y = 0..15)
4
2
CTL3
Port x configuration bits (y = 0..15)
6
2
CTL4
Port x configuration bits (y = 0..15)
8
2
CTL5
Port x configuration bits (y = 0..15)
10
2
CTL6
Port x configuration bits (y = 0..15)
12
2
CTL7
Port x configuration bits (y = 0..15)
14
2
CTL8
Port x configuration bits (y = 0..15)
16
2
CTL9
Port x configuration bits (y = 0..15)
18
2
ISTAT
ISTAT
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
ISTAT0
Port input data (y = 0..15)
0
1
ISTAT1
Port input data (y = 0..15)
1
1
ISTAT10
Port input data (y = 0..15)
10
1
ISTAT11
Port input data (y = 0..15)
11
1
ISTAT12
Port input data (y = 0..15)
12
1
ISTAT13
Port input data (y = 0..15)
13
1
ISTAT14
Port input data (y = 0..15)
14
1
ISTAT15
Port input data (y = 0..15)
15
1
ISTAT2
Port input data (y = 0..15)
2
1
ISTAT3
Port input data (y = 0..15)
3
1
ISTAT4
Port input data (y = 0..15)
4
1
ISTAT5
Port input data (y = 0..15)
5
1
ISTAT6
Port input data (y = 0..15)
6
1
ISTAT7
Port input data (y = 0..15)
7
1
ISTAT8
Port input data (y = 0..15)
8
1
ISTAT9
Port input data (y = 0..15)
9
1
OCTL
OCTL
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
OCTL0
Port output data (y = 0..15)
0
1
OCTL1
Port output data (y = 0..15)
1
1
OCTL10
Port output data (y = 0..15)
10
1
OCTL11
Port output data (y = 0..15)
11
1
OCTL12
Port output data (y = 0..15)
12
1
OCTL13
Port output data (y = 0..15)
13
1
OCTL14
Port output data (y = 0..15)
14
1
OCTL15
Port output data (y = 0..15)
15
1
OCTL2
Port output data (y = 0..15)
2
1
OCTL3
Port output data (y = 0..15)
3
1
OCTL4
Port output data (y = 0..15)
4
1
OCTL5
Port output data (y = 0..15)
5
1
OCTL6
Port output data (y = 0..15)
6
1
OCTL7
Port output data (y = 0..15)
7
1
OCTL8
Port output data (y = 0..15)
8
1
OCTL9
Port output data (y = 0..15)
9
1
OMODE
OMODE
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OM0
Port x configuration bit 0
0
1
OM1
Port x configuration bit 1
1
1
OM10
Port x configuration bit 10
10
1
OM11
Port x configuration bit 11
11
1
OM12
Port x configuration bit 12
12
1
OM13
Port x configuration bit 13
13
1
OM14
Port x configuration bit 14
14
1
OM15
Port x configuration bit 15
15
1
OM2
Port x configuration bit 2
2
1
OM3
Port x configuration bit 3
3
1
OM4
Port x configuration bit 4
4
1
OM5
Port x configuration bit 5
5
1
OM6
Port x configuration bit 6
6
1
OM7
Port x configuration bit 7
7
1
OM8
Port x configuration bit 8
8
1
OM9
Port x configuration bit 9
9
1
OSPD0
OSPD0
GPIO port output speed register 0
0x8
32
read-write
n
0x0
0x0
OSPD0
Port x configuration bits (y = 0..15)
0
2
OSPD1
Port x configuration bits (y = 0..15)
2
2
OSPD10
Port x configuration bits (y = 0..15)
20
2
OSPD11
Port x configuration bits (y = 0..15)
22
2
OSPD12
Port x configuration bits (y = 0..15)
24
2
OSPD13
Port x configuration bits (y = 0..15)
26
2
OSPD14
Port x configuration bits (y = 0..15)
28
2
OSPD15
Port x configuration bits (y = 0..15)
30
2
OSPD2
Port x configuration bits (y = 0..15)
4
2
OSPD3
Port x configuration bits (y = 0..15)
6
2
OSPD4
Port x configuration bits (y = 0..15)
8
2
OSPD5
Port x configuration bits (y = 0..15)
10
2
OSPD6
Port x configuration bits (y = 0..15)
12
2
OSPD7
Port x configuration bits (y = 0..15)
14
2
OSPD8
Port x configuration bits (y = 0..15)
16
2
OSPD9
Port x configuration bits (y = 0..15)
18
2
OSPD1
OSPD1
Port output speed register 1
0x3C
32
read-write
n
0x0
0x0
SPD0
Set Very High output speed when OSPDy(y=0..15) is 0b11
0
1
SPD1
Set Very High output speed when OSPDy(y=0..15) is 0b11
1
1
SPD10
Set Very High output speed when OSPDy(y=0..15) is 0b11
10
1
SPD11
Set Very High output speed when OSPDy(y=0..15) is 0b11
11
1
SPD12
Set Very High output speed when OSPDy(y=0..15) is 0b11
12
1
SPD13
Set Very High output speed when OSPDy(y=0..15) is 0b11
13
1
SPD14
Set Very High output speed when OSPDy(y=0..15) is 0b11
14
1
SPD15
Set Very High output speed when OSPDy(y=0..15) is 0b11
15
1
SPD2
Set Very High output speed when OSPDy(y=0..15) is 0b11
2
1
SPD3
Set Very High output speed when OSPDy(y=0..15) is 0b11
3
1
SPD4
Set Very High output speed when OSPDy(y=0..15) is 0b11
4
1
SPD5
Set Very High output speed when OSPDy(y=0..15) is 0b11
5
1
SPD6
Set Very High output speed when OSPDy(y=0..15) is 0b11
6
1
SPD7
Set Very High output speed when OSPDy(y=0..15) is 0b11
7
1
SPD8
Set Very High output speed when OSPDy(y=0..15) is 0b11
8
1
SPD9
Set Very High output speed when OSPDy(y=0..15) is 0b11
9
1
PUD
PUD
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUD0
Port x configuration bits (y = 0..15)
0
2
PUD1
Port x configuration bits (y = 0..15)
2
2
PUD10
Port x configuration bits (y = 0..15)
20
2
PUD11
Port x configuration bits (y = 0..15)
22
2
PUD12
Port x configuration bits (y = 0..15)
24
2
PUD13
Port x configuration bits (y = 0..15)
26
2
PUD14
Port x configuration bits (y = 0..15)
28
2
PUD15
Port x configuration bits (y = 0..15)
30
2
PUD2
Port x configuration bits (y = 0..15)
4
2
PUD3
Port x configuration bits (y = 0..15)
6
2
PUD4
Port x configuration bits (y = 0..15)
8
2
PUD5
Port x configuration bits (y = 0..15)
10
2
PUD6
Port x configuration bits (y = 0..15)
12
2
PUD7
Port x configuration bits (y = 0..15)
14
2
PUD8
Port x configuration bits (y = 0..15)
16
2
PUD9
Port x configuration bits (y = 0..15)
18
2
TG
TG
Port bit toggle register
0x2C
32
write-only
n
0x0
0x0
TG0
Port toggle bit
0
1
TG1
Port toggle bit
1
1
TG10
Port toggle bit
10
1
TG11
Port toggle bit
11
1
TG12
Port toggle bit
12
1
TG13
Port toggle bit
13
1
TG14
Port toggle bit
14
1
TG15
Port toggle bit
15
1
TG2
Port toggle bit
2
1
TG3
Port toggle bit
3
1
TG4
Port toggle bit
4
1
TG5
Port toggle bit
5
1
TG6
Port toggle bit
6
1
TG7
Port toggle bit
7
1
TG8
Port toggle bit
8
1
TG9
Port toggle bit
9
1
GPIOD
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
BC
BC
Port bit reset register
0x28
32
write-only
n
0x0
0x0
CR0
Port cleat bit
0
1
CR1
Port cleat bit
1
1
CR10
Port cleat bit
10
1
CR11
Port cleat bit
11
1
CR12
Port cleat bit
12
1
CR13
Port cleat bit
13
1
CR14
Port cleat bit
14
1
CR15
Port cleat bit
15
1
CR2
Port cleat bit
2
1
CR3
Port cleat bit
3
1
CR4
Port cleat bit
4
1
CR5
Port cleat bit
5
1
CR6
Port cleat bit
6
1
CR7
Port cleat bit
7
1
CR8
Port cleat bit
8
1
CR9
Port cleat bit
9
1
BOP
BOP
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BOP0
Port x set bit y (y= 0..15)
0
1
BOP1
Port x set bit y (y= 0..15)
1
1
BOP10
Port x set bit y (y= 0..15)
10
1
BOP11
Port x set bit y (y= 0..15)
11
1
BOP12
Port x set bit y (y= 0..15)
12
1
BOP13
Port x set bit y (y= 0..15)
13
1
BOP14
Port x set bit y (y= 0..15)
14
1
BOP15
Port x set bit y (y= 0..15)
15
1
BOP2
Port x set bit y (y= 0..15)
2
1
BOP3
Port x set bit y (y= 0..15)
3
1
BOP4
Port x set bit y (y= 0..15)
4
1
BOP5
Port x set bit y (y= 0..15)
5
1
BOP6
Port x set bit y (y= 0..15)
6
1
BOP7
Port x set bit y (y= 0..15)
7
1
BOP8
Port x set bit y (y= 0..15)
8
1
BOP9
Port x set bit y (y= 0..15)
9
1
CR0
Port x reset bit y (y= 0..15)
16
1
CR1
Port x reset bit y (y = 0..15)
17
1
CR10
Port x reset bit y (y = 0..15)
26
1
CR11
Port x reset bit y (y = 0..15)
27
1
CR12
Port x reset bit y (y = 0..15)
28
1
CR13
Port x reset bit y (y = 0..15)
29
1
CR14
Port x reset bit y (y = 0..15)
30
1
CR15
Port x reset bit y (y = 0..15)
31
1
CR2
Port x reset bit y (y = 0..15)
18
1
CR3
Port x reset bit y (y = 0..15)
19
1
CR4
Port x reset bit y (y = 0..15)
20
1
CR5
Port x reset bit y (y = 0..15)
21
1
CR6
Port x reset bit y (y = 0..15)
22
1
CR7
Port x reset bit y (y = 0..15)
23
1
CR8
Port x reset bit y (y = 0..15)
24
1
CR9
Port x reset bit y (y = 0..15)
25
1
CTL
CTL
GPIO port control register
0x0
32
read-write
n
0x0
0x0
CTL0
Port x configuration bits (y = 0..15)
0
2
CTL1
Port x configuration bits (y = 0..15)
2
2
CTL10
Port x configuration bits (y = 0..15)
20
2
CTL11
Port x configuration bits (y = 0..15)
22
2
CTL12
Port x configuration bits (y = 0..15)
24
2
CTL13
Port x configuration bits (y = 0..15)
26
2
CTL14
Port x configuration bits (y = 0..15)
28
2
CTL15
Port x configuration bits (y = 0..15)
30
2
CTL2
Port x configuration bits (y = 0..15)
4
2
CTL3
Port x configuration bits (y = 0..15)
6
2
CTL4
Port x configuration bits (y = 0..15)
8
2
CTL5
Port x configuration bits (y = 0..15)
10
2
CTL6
Port x configuration bits (y = 0..15)
12
2
CTL7
Port x configuration bits (y = 0..15)
14
2
CTL8
Port x configuration bits (y = 0..15)
16
2
CTL9
Port x configuration bits (y = 0..15)
18
2
ISTAT
ISTAT
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
ISTAT0
Port input data (y = 0..15)
0
1
ISTAT1
Port input data (y = 0..15)
1
1
ISTAT10
Port input data (y = 0..15)
10
1
ISTAT11
Port input data (y = 0..15)
11
1
ISTAT12
Port input data (y = 0..15)
12
1
ISTAT13
Port input data (y = 0..15)
13
1
ISTAT14
Port input data (y = 0..15)
14
1
ISTAT15
Port input data (y = 0..15)
15
1
ISTAT2
Port input data (y = 0..15)
2
1
ISTAT3
Port input data (y = 0..15)
3
1
ISTAT4
Port input data (y = 0..15)
4
1
ISTAT5
Port input data (y = 0..15)
5
1
ISTAT6
Port input data (y = 0..15)
6
1
ISTAT7
Port input data (y = 0..15)
7
1
ISTAT8
Port input data (y = 0..15)
8
1
ISTAT9
Port input data (y = 0..15)
9
1
OCTL
OCTL
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
OCTL0
Port output data (y = 0..15)
0
1
OCTL1
Port output data (y = 0..15)
1
1
OCTL10
Port output data (y = 0..15)
10
1
OCTL11
Port output data (y = 0..15)
11
1
OCTL12
Port output data (y = 0..15)
12
1
OCTL13
Port output data (y = 0..15)
13
1
OCTL14
Port output data (y = 0..15)
14
1
OCTL15
Port output data (y = 0..15)
15
1
OCTL2
Port output data (y = 0..15)
2
1
OCTL3
Port output data (y = 0..15)
3
1
OCTL4
Port output data (y = 0..15)
4
1
OCTL5
Port output data (y = 0..15)
5
1
OCTL6
Port output data (y = 0..15)
6
1
OCTL7
Port output data (y = 0..15)
7
1
OCTL8
Port output data (y = 0..15)
8
1
OCTL9
Port output data (y = 0..15)
9
1
OMODE
OMODE
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OM0
Port x configuration bit 0
0
1
OM1
Port x configuration bit 1
1
1
OM10
Port x configuration bit 10
10
1
OM11
Port x configuration bit 11
11
1
OM12
Port x configuration bit 12
12
1
OM13
Port x configuration bit 13
13
1
OM14
Port x configuration bit 14
14
1
OM15
Port x configuration bit 15
15
1
OM2
Port x configuration bit 2
2
1
OM3
Port x configuration bit 3
3
1
OM4
Port x configuration bit 4
4
1
OM5
Port x configuration bit 5
5
1
OM6
Port x configuration bit 6
6
1
OM7
Port x configuration bit 7
7
1
OM8
Port x configuration bit 8
8
1
OM9
Port x configuration bit 9
9
1
OSPD0
OSPD0
GPIO port output speed register 0
0x8
32
read-write
n
0x0
0x0
OSPD0
Port x configuration bits (y = 0..15)
0
2
OSPD1
Port x configuration bits (y = 0..15)
2
2
OSPD10
Port x configuration bits (y = 0..15)
20
2
OSPD11
Port x configuration bits (y = 0..15)
22
2
OSPD12
Port x configuration bits (y = 0..15)
24
2
OSPD13
Port x configuration bits (y = 0..15)
26
2
OSPD14
Port x configuration bits (y = 0..15)
28
2
OSPD15
Port x configuration bits (y = 0..15)
30
2
OSPD2
Port x configuration bits (y = 0..15)
4
2
OSPD3
Port x configuration bits (y = 0..15)
6
2
OSPD4
Port x configuration bits (y = 0..15)
8
2
OSPD5
Port x configuration bits (y = 0..15)
10
2
OSPD6
Port x configuration bits (y = 0..15)
12
2
OSPD7
Port x configuration bits (y = 0..15)
14
2
OSPD8
Port x configuration bits (y = 0..15)
16
2
OSPD9
Port x configuration bits (y = 0..15)
18
2
OSPD1
OSPD1
Port output speed register 1
0x3C
32
read-write
n
0x0
0x0
SPD0
Set Very High output speed when OSPDy(y=0..15) is 0b11
0
1
SPD1
Set Very High output speed when OSPDy(y=0..15) is 0b11
1
1
SPD10
Set Very High output speed when OSPDy(y=0..15) is 0b11
10
1
SPD11
Set Very High output speed when OSPDy(y=0..15) is 0b11
11
1
SPD12
Set Very High output speed when OSPDy(y=0..15) is 0b11
12
1
SPD13
Set Very High output speed when OSPDy(y=0..15) is 0b11
13
1
SPD14
Set Very High output speed when OSPDy(y=0..15) is 0b11
14
1
SPD15
Set Very High output speed when OSPDy(y=0..15) is 0b11
15
1
SPD2
Set Very High output speed when OSPDy(y=0..15) is 0b11
2
1
SPD3
Set Very High output speed when OSPDy(y=0..15) is 0b11
3
1
SPD4
Set Very High output speed when OSPDy(y=0..15) is 0b11
4
1
SPD5
Set Very High output speed when OSPDy(y=0..15) is 0b11
5
1
SPD6
Set Very High output speed when OSPDy(y=0..15) is 0b11
6
1
SPD7
Set Very High output speed when OSPDy(y=0..15) is 0b11
7
1
SPD8
Set Very High output speed when OSPDy(y=0..15) is 0b11
8
1
SPD9
Set Very High output speed when OSPDy(y=0..15) is 0b11
9
1
PUD
PUD
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUD0
Port x configuration bits (y = 0..15)
0
2
PUD1
Port x configuration bits (y = 0..15)
2
2
PUD10
Port x configuration bits (y = 0..15)
20
2
PUD11
Port x configuration bits (y = 0..15)
22
2
PUD12
Port x configuration bits (y = 0..15)
24
2
PUD13
Port x configuration bits (y = 0..15)
26
2
PUD14
Port x configuration bits (y = 0..15)
28
2
PUD15
Port x configuration bits (y = 0..15)
30
2
PUD2
Port x configuration bits (y = 0..15)
4
2
PUD3
Port x configuration bits (y = 0..15)
6
2
PUD4
Port x configuration bits (y = 0..15)
8
2
PUD5
Port x configuration bits (y = 0..15)
10
2
PUD6
Port x configuration bits (y = 0..15)
12
2
PUD7
Port x configuration bits (y = 0..15)
14
2
PUD8
Port x configuration bits (y = 0..15)
16
2
PUD9
Port x configuration bits (y = 0..15)
18
2
TG
TG
Port bit toggle register
0x2C
32
write-only
n
0x0
0x0
TG0
Port toggle bit
0
1
TG1
Port toggle bit
1
1
TG10
Port toggle bit
10
1
TG11
Port toggle bit
11
1
TG12
Port toggle bit
12
1
TG13
Port toggle bit
13
1
TG14
Port toggle bit
14
1
TG15
Port toggle bit
15
1
TG2
Port toggle bit
2
1
TG3
Port toggle bit
3
1
TG4
Port toggle bit
4
1
TG5
Port toggle bit
5
1
TG6
Port toggle bit
6
1
TG7
Port toggle bit
7
1
TG8
Port toggle bit
8
1
TG9
Port toggle bit
9
1
GPIOF
General-purpose I/Os
GPIO
0x0
0x0
0x400
registers
n
BC
BC
Port bit reset register
0x28
32
write-only
n
0x0
0x0
CR0
Port x Reset bit y
0
1
CR1
Port x Reset bit y
1
1
CR10
Port x Reset bit y
10
1
CR11
Port x Reset bit y
11
1
CR12
Port x Reset bit y
12
1
CR13
Port x Reset bit y
13
1
CR14
Port x Reset bit y
14
1
CR15
Port x Reset bit y
15
1
CR2
Port x Reset bit y
2
1
CR3
Port x Reset bit y
3
1
CR4
Port x Reset bit y
4
1
CR5
Port x Reset bit y
5
1
CR6
Port x Reset bit y
6
1
CR7
Port x Reset bit y
7
1
CR8
Port x Reset bit y
8
1
CR9
Port x Reset bit y
9
1
BOP
BOP
GPIO port bit set/reset register
0x18
32
write-only
n
0x0
0x0
BOP0
Port x set bit y (y= 0..15)
0
1
BOP1
Port x set bit y (y= 0..15)
1
1
BOP10
Port x set bit y (y= 0..15)
10
1
BOP11
Port x set bit y (y= 0..15)
11
1
BOP12
Port x set bit y (y= 0..15)
12
1
BOP13
Port x set bit y (y= 0..15)
13
1
BOP14
Port x set bit y (y= 0..15)
14
1
BOP15
Port x set bit y (y= 0..15)
15
1
BOP2
Port x set bit y (y= 0..15)
2
1
BOP3
Port x set bit y (y= 0..15)
3
1
BOP4
Port x set bit y (y= 0..15)
4
1
BOP5
Port x set bit y (y= 0..15)
5
1
BOP6
Port x set bit y (y= 0..15)
6
1
BOP7
Port x set bit y (y= 0..15)
7
1
BOP8
Port x set bit y (y= 0..15)
8
1
BOP9
Port x set bit y (y= 0..15)
9
1
CR0
Port x set bit y (y= 0..15)
16
1
CR1
Port x reset bit y (y = 0..15)
17
1
CR10
Port x reset bit y (y = 0..15)
26
1
CR11
Port x reset bit y (y = 0..15)
27
1
CR12
Port x reset bit y (y = 0..15)
28
1
CR13
Port x reset bit y (y = 0..15)
29
1
CR14
Port x reset bit y (y = 0..15)
30
1
CR15
Port x reset bit y (y = 0..15)
31
1
CR2
Port x reset bit y (y = 0..15)
18
1
CR3
Port x reset bit y (y = 0..15)
19
1
CR4
Port x reset bit y (y = 0..15)
20
1
CR5
Port x reset bit y (y = 0..15)
21
1
CR6
Port x reset bit y (y = 0..15)
22
1
CR7
Port x reset bit y (y = 0..15)
23
1
CR8
Port x reset bit y (y = 0..15)
24
1
CR9
Port x reset bit y (y = 0..15)
25
1
CTL
CTL
GPIOF port control register
0x0
32
read-write
n
0x0
0x0
CTL0
Port x configuration bits (y = 0..15)
0
2
CTL1
Port x configuration bits (y = 0..15)
2
2
CTL10
Port x configuration bits (y = 0..15)
20
2
CTL11
Port x configuration bits (y = 0..15)
22
2
CTL12
Port x configuration bits (y = 0..15)
24
2
CTL13
Port x configuration bits (y = 0..15)
26
2
CTL14
Port x configuration bits (y = 0..15)
28
2
CTL15
Port x configuration bits (y = 0..15)
30
2
CTL2
Port x configuration bits (y = 0..15)
4
2
CTL3
Port x configuration bits (y = 0..15)
6
2
CTL4
Port x configuration bits (y = 0..15)
8
2
CTL5
Port x configuration bits (y = 0..15)
10
2
CTL6
Port x configuration bits (y = 0..15)
12
2
CTL7
Port x configuration bits (y = 0..15)
14
2
CTL8
Port x configuration bits (y = 0..15)
16
2
CTL9
Port x configuration bits (y = 0..15)
18
2
ISTAT
ISTAT
GPIO port input data register
0x10
32
read-only
n
0x0
0x0
ISTAT0
Port input data (y = 0..15)
0
1
ISTAT1
Port input data (y = 0..15)
1
1
ISTAT10
Port input data (y = 0..15)
10
1
ISTAT11
Port input data (y = 0..15)
11
1
ISTAT12
Port input data (y = 0..15)
12
1
ISTAT13
Port input data (y = 0..15)
13
1
ISTAT14
Port input data (y = 0..15)
14
1
ISTAT15
Port input data (y = 0..15)
15
1
ISTAT2
Port input data (y = 0..15)
2
1
ISTAT3
Port input data (y = 0..15)
3
1
ISTAT4
Port input data (y = 0..15)
4
1
ISTAT5
Port input data (y = 0..15)
5
1
ISTAT6
Port input data (y = 0..15)
6
1
ISTAT7
Port input data (y = 0..15)
7
1
ISTAT8
Port input data (y = 0..15)
8
1
ISTAT9
Port input data (y = 0..15)
9
1
OCTL
OCTL
GPIO port output data register
0x14
32
read-write
n
0x0
0x0
OCTL0
Port output data (y = 0..15)
0
1
OCTL1
Port output data (y = 0..15)
1
1
OCTL10
Port output data (y = 0..15)
10
1
OCTL11
Port output data (y = 0..15)
11
1
OCTL12
Port output data (y = 0..15)
12
1
OCTL13
Port output data (y = 0..15)
13
1
OCTL14
Port output data (y = 0..15)
14
1
OCTL15
Port output data (y = 0..15)
15
1
OCTL2
Port output data (y = 0..15)
2
1
OCTL3
Port output data (y = 0..15)
3
1
OCTL4
Port output data (y = 0..15)
4
1
OCTL5
Port output data (y = 0..15)
5
1
OCTL6
Port output data (y = 0..15)
6
1
OCTL7
Port output data (y = 0..15)
7
1
OCTL8
Port output data (y = 0..15)
8
1
OCTL9
Port output data (y = 0..15)
9
1
OMODE
OMODE
GPIO port output type register
0x4
32
read-write
n
0x0
0x0
OM0
Port x configuration bit 0
0
1
OM1
Port x configuration bit 1
1
1
OM10
Port x configuration bit 10
10
1
OM11
Port x configuration bit 11
11
1
OM12
Port x configuration bit 12
12
1
OM13
Port x configuration bit 13
13
1
OM14
Port x configuration bit 14
14
1
OM15
Port x configuration bit 15
15
1
OM2
Port x configuration bit 2
2
1
OM3
Port x configuration bit 3
3
1
OM4
Port x configuration bit 4
4
1
OM5
Port x configuration bit 5
5
1
OM6
Port x configuration bit 6
6
1
OM7
Port x configuration bit 7
7
1
OM8
Port x configuration bit 8
8
1
OM9
Port x configuration bit 9
9
1
OSPD0
OSPD0
GPIO port output speed register 0
0x8
32
read-write
n
0x0
0x0
OSPD0
Port x configuration bits (y = 0..15)
0
2
OSPD1
Port x configuration bits (y = 0..15)
2
2
OSPD10
Port x configuration bits (y = 0..15)
20
2
OSPD11
Port x configuration bits (y = 0..15)
22
2
OSPD12
Port x configuration bits (y = 0..15)
24
2
OSPD13
Port x configuration bits (y = 0..15)
26
2
OSPD14
Port x configuration bits (y = 0..15)
28
2
OSPD15
Port x configuration bits (y = 0..15)
30
2
OSPD2
Port x configuration bits (y = 0..15)
4
2
OSPD3
Port x configuration bits (y = 0..15)
6
2
OSPD4
Port x configuration bits (y = 0..15)
8
2
OSPD5
Port x configuration bits (y = 0..15)
10
2
OSPD6
Port x configuration bits (y = 0..15)
12
2
OSPD7
Port x configuration bits (y = 0..15)
14
2
OSPD8
Port x configuration bits (y = 0..15)
16
2
OSPD9
Port x configuration bits (y = 0..15)
18
2
OSPD1
OSPD1
Port output speed register 1
0x3C
32
read-write
n
0x0
0x0
SPD0
Set Very High output speed when OSPDy(y=0..15) is 0b11
0
1
SPD1
Set Very High output speed when OSPDy(y=0..15) is 0b11
1
1
SPD10
Set Very High output speed when OSPDy(y=0..15) is 0b11
10
1
SPD11
Set Very High output speed when OSPDy(y=0..15) is 0b11
11
1
SPD12
Set Very High output speed when OSPDy(y=0..15) is 0b11
12
1
SPD13
Set Very High output speed when OSPDy(y=0..15) is 0b11
13
1
SPD14
Set Very High output speed when OSPDy(y=0..15) is 0b11
14
1
SPD15
Set Very High output speed when OSPDy(y=0..15) is 0b11
15
1
SPD2
Set Very High output speed when OSPDy(y=0..15) is 0b11
2
1
SPD3
Set Very High output speed when OSPDy(y=0..15) is 0b11
3
1
SPD4
Set Very High output speed when OSPDy(y=0..15) is 0b11
4
1
SPD5
Set Very High output speed when OSPDy(y=0..15) is 0b11
5
1
SPD6
Set Very High output speed when OSPDy(y=0..15) is 0b11
6
1
SPD7
Set Very High output speed when OSPDy(y=0..15) is 0b11
7
1
SPD8
Set Very High output speed when OSPDy(y=0..15) is 0b11
8
1
SPD9
Set Very High output speed when OSPDy(y=0..15) is 0b11
9
1
PUD
PUD
GPIO port pull-up/pull-down register
0xC
32
read-write
n
0x0
0x0
PUD0
Port x configuration bits (y = 0..15)
0
2
PUD1
Port x configuration bits (y = 0..15)
2
2
PUD10
Port x configuration bits (y = 0..15)
20
2
PUD11
Port x configuration bits (y = 0..15)
22
2
PUD12
Port x configuration bits (y = 0..15)
24
2
PUD13
Port x configuration bits (y = 0..15)
26
2
PUD14
Port x configuration bits (y = 0..15)
28
2
PUD15
Port x configuration bits (y = 0..15)
30
2
PUD2
Port x configuration bits (y = 0..15)
4
2
PUD3
Port x configuration bits (y = 0..15)
6
2
PUD4
Port x configuration bits (y = 0..15)
8
2
PUD5
Port x configuration bits (y = 0..15)
10
2
PUD6
Port x configuration bits (y = 0..15)
12
2
PUD7
Port x configuration bits (y = 0..15)
14
2
PUD8
Port x configuration bits (y = 0..15)
16
2
PUD9
Port x configuration bits (y = 0..15)
18
2
TG
TG
Port bit toggle register
0x2C
32
write-only
n
0x0
0x0
TG0
Port toggle bit
0
1
TG1
Port toggle bit
1
1
TG10
Port toggle bit
10
1
TG11
Port toggle bit
11
1
TG12
Port toggle bit
12
1
TG13
Port toggle bit
13
1
TG14
Port toggle bit
14
1
TG15
Port toggle bit
15
1
TG2
Port toggle bit
2
1
TG3
Port toggle bit
3
1
TG4
Port toggle bit
4
1
TG5
Port toggle bit
5
1
TG6
Port toggle bit
6
1
TG7
Port toggle bit
7
1
TG8
Port toggle bit
8
1
TG9
Port toggle bit
9
1
I2C0
Inter integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C0_EV
23
I2C0_ER
32
CKCFG
CKCFG
Clock configure register
0x1C
32
read-write
n
0x0
0x0
CLKC
Clock control register in Fast/Standard mode (Master mode)
0
12
DTCY
Fast mode duty cycle
14
1
FAST
I2C master mode selection
15
1
CTL0
CTL0
Control register 0
0x0
32
read-write
n
0x0
0x0
ACKEN
Acknowledge enable
10
1
ARPEN
ARP enable
4
1
GCEN
General call enable
6
1
I2CEN
Peripheral enable
0
1
PECEN
PEC enable
5
1
PECTRANS
Packet error checking
12
1
POAP
Acknowledge/PEC Position (for data reception)
11
1
SALT
SMBus alert
13
1
SMBEN
SMBus mode
1
1
SMBSEL
SMBus type
3
1
SRESET
Software reset
15
1
SS
Clock stretching disable (Slave mode)
7
1
START
Start generation
8
1
STOP
Stop condition
9
1
CTL1
CTL1
Control register 1
0x4
32
read-write
n
0x0
0x0
BUFIE
Buffer interrupt enable
10
1
DMALST
Flag indicating DMA last transfer
12
1
DMAON
DMA mode switch
11
1
ERRIE
Error interrupt enable
8
1
EVIE
Event interrupt enable
9
1
I2CCLK
Peripheral clock frequency
0
6
DATA
DATA
Data register
0x10
32
read-write
n
0x0
0x0
TRB
Transmission or reception data buffer
0
8
FMPCFG
FMPCFG
Fast-mode-plus configure register
0x90
32
read-write
n
0x0
0x0
FMPEN
Fast-mode-plus enable
0
1
RT
RT
Rise time register
0x20
32
read-write
n
0x0
0x0
RISETIME
Maximum rise time in master mode
0
6
SADDR0
SADDR0
Own address register 0
0x8
32
read-write
n
0x0
0x0
ADDFORMAT
Addressing mode (slave mode)
15
1
ADDRESS
Interface address
0
10
SADDR1
SADDR1
Own address register 1
0xC
32
read-write
n
0x0
0x0
ADDRESS2
Interface address
1
7
DUADEN
Dual addressing mode enable
0
1
STAT0
STAT0
Transfer status register 0
0x14
32
read-write
n
0x0
0x0
ADD10SEND
Header of 10-bit address is sent in master mode
3
1
read-only
ADDSEND
Address sent (master mode)/matched (slave mode)
1
1
read-only
AERR
Acknowledge error
10
1
read-write
BERR
Bus error
8
1
read-write
BTC
Byte transmission completed
2
1
read-only
LOSTARB
Arbitration lost (master mode)
9
1
read-write
OUERR
Overrun/Underrun occurs in slave mode
11
1
read-write
PECERR
PEC error when receiving data
12
1
read-write
RBNE
I2C_DATA is not Empty during receiving
6
1
read-only
SBSEND
Start bit (Master mode)
0
1
read-only
SMBALT
SMBus alert
15
1
read-write
SMBTO
Timeout signal in SMBus mode
14
1
read-write
STPDET
Stop detection (slave mode)
4
1
read-only
TBE
I2C_DATA is Empty during transmitting
7
1
read-only
STAT1
STAT1
Transfer status register 1
0x18
32
read-only
n
0x0
0x0
DEFSMB
SMBus device default address (Slave mode)
5
1
DUMODF
Dual flag (Slave mode)
7
1
HSTSMB
SMBus host header (Slave mode)
6
1
I2CBSY
Bus busy
1
1
MASTER
Master/slave
0
1
PECV
Packet error checking register
8
8
RXGC
General call address (Slave mode)
4
1
TR
Transmitter/receiver
2
1
I2C1
Inter integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C1_EV
24
I2C1_ER
34
CKCFG
CKCFG
Clock configure register
0x1C
32
read-write
n
0x0
0x0
CLKC
Clock control register in Fast/Standard mode (Master mode)
0
12
DTCY
Fast mode duty cycle
14
1
FAST
I2C master mode selection
15
1
CTL0
CTL0
Control register 0
0x0
32
read-write
n
0x0
0x0
ACKEN
Acknowledge enable
10
1
ARPEN
ARP enable
4
1
GCEN
General call enable
6
1
I2CEN
Peripheral enable
0
1
PECEN
PEC enable
5
1
PECTRANS
Packet error checking
12
1
POAP
Acknowledge/PEC Position (for data reception)
11
1
SALT
SMBus alert
13
1
SMBEN
SMBus mode
1
1
SMBSEL
SMBus type
3
1
SRESET
Software reset
15
1
SS
Clock stretching disable (Slave mode)
7
1
START
Start generation
8
1
STOP
Stop condition
9
1
CTL1
CTL1
Control register 1
0x4
32
read-write
n
0x0
0x0
BUFIE
Buffer interrupt enable
10
1
DMALST
Flag indicating DMA last transfer
12
1
DMAON
DMA mode switch
11
1
ERRIE
Error interrupt enable
8
1
EVIE
Event interrupt enable
9
1
I2CCLK
Peripheral clock frequency
0
6
DATA
DATA
Data register
0x10
32
read-write
n
0x0
0x0
TRB
Transmission or reception data buffer
0
8
FMPCFG
FMPCFG
Fast-mode-plus configure register
0x90
32
read-write
n
0x0
0x0
FMPEN
Fast-mode-plus enable
0
1
RT
RT
Rise time register
0x20
32
read-write
n
0x0
0x0
RISETIME
Maximum rise time in master mode
0
6
SADDR0
SADDR0
Own address register 0
0x8
32
read-write
n
0x0
0x0
ADDFORMAT
Addressing mode (slave mode)
15
1
ADDRESS
Interface address
0
10
SADDR1
SADDR1
Own address register 1
0xC
32
read-write
n
0x0
0x0
ADDRESS2
Interface address
1
7
DUADEN
Dual addressing mode enable
0
1
STAT0
STAT0
Transfer status register 0
0x14
32
read-write
n
0x0
0x0
ADD10SEND
Header of 10-bit address is sent in master mode
3
1
read-only
ADDSEND
Address sent (master mode)/matched (slave mode)
1
1
read-only
AERR
Acknowledge error
10
1
read-write
BERR
Bus error
8
1
read-write
BTC
Byte transmission completed
2
1
read-only
LOSTARB
Arbitration lost (master mode)
9
1
read-write
OUERR
Overrun/Underrun occurs in slave mode
11
1
read-write
PECERR
PEC error when receiving data
12
1
read-write
RBNE
I2C_DATA is not Empty during receiving
6
1
read-only
SBSEND
Start bit (Master mode)
0
1
read-only
SMBALT
SMBus alert
15
1
read-write
SMBTO
Timeout signal in SMBus mode
14
1
read-write
STPDET
Stop detection (slave mode)
4
1
read-only
TBE
I2C_DATA is Empty during transmitting
7
1
read-only
STAT1
STAT1
Transfer status register 1
0x18
32
read-only
n
0x0
0x0
DEFSMB
SMBus device default address (Slave mode)
5
1
DUMODF
Dual flag (Slave mode)
7
1
HSTSMB
SMBus host header (Slave mode)
6
1
I2CBSY
Bus busy
1
1
MASTER
Master/slave
0
1
PECV
Packet error checking register
8
8
RXGC
General call address (Slave mode)
4
1
TR
Transmitter/receiver
2
1
NVIC
Nested Vectored Interrupt Controller
NVIC
0x0
0x0
0xF00
registers
n
0x33D
0xC3
reserved
n
IABR
IABR
Interrupt Active bit Register
0x200
32
read-write
n
0x0
0x0
IABR
IABR
0
32
ICER
ICER
Interrupt Clear Enable Register
0x80
32
read-write
n
0x0
0x0
CLRENA
CLRENA
0
32
ICPR
ICPR
Interrupt Clear-Pending Register
0x180
32
read-write
n
0x0
0x0
CLRPEND
CLRPEND
0
32
IPR0
IPR0
Interrupt Priority Register 0
0x300
8
read-write
n
0x0
0x0
PRI_00
PRI_00
0
8
IPR1
IPR1
Interrupt Priority Register 1
0x301
8
read-write
n
0x0
0x0
PRI_01
PRI_01
0
8
IPR10
IPR10
Interrupt Priority Register 10
0x30A
8
read-write
n
0x0
0x0
PRI_10
PRI_10
0
8
IPR11
IPR11
Interrupt Priority Register 11
0x30B
8
read-write
n
0x0
0x0
PRI_11
PRI_11
0
8
IPR12
IPR12
Interrupt Priority Register 12
0x30C
8
read-write
n
0x0
0x0
PRI_12
PRI_12
0
8
IPR13
IPR13
Interrupt Priority Register 13
0x30D
8
read-write
n
0x0
0x0
PRI_13
PRI_13
0
8
IPR14
IPR14
Interrupt Priority Register 14
0x30E
8
read-write
n
0x0
0x0
PRI_14
PRI_14
0
8
IPR15
IPR15
Interrupt Priority Register 15
0x30F
8
read-write
n
0x0
0x0
PRI_15
PRI_15
0
8
IPR16
IPR16
Interrupt Priority Register 16
0x310
8
read-write
n
0x0
0x0
PRI_16
PRI_16
0
8
IPR17
IPR17
Interrupt Priority Register 17
0x311
8
read-write
n
0x0
0x0
PRI_17
PRI_17
0
8
IPR18
IPR18
Interrupt Priority Register 18
0x312
8
read-write
n
0x0
0x0
PRI_18
PRI_18
0
8
IPR19
IPR19
Interrupt Priority Register 19
0x313
8
read-write
n
0x0
0x0
PRI_19
PRI_19
0
8
IPR2
IPR2
Interrupt Priority Register 2
0x302
8
read-write
n
0x0
0x0
PRI_02
PRI_02
0
8
IPR20
IPR20
Interrupt Priority Register 20
0x314
8
read-write
n
0x0
0x0
PRI_20
PRI_20
0
8
IPR21
IPR21
Interrupt Priority Register 21
0x315
8
read-write
n
0x0
0x0
PRI_21
PRI_21
0
8
IPR22
IPR22
Interrupt Priority Register 22
0x316
8
read-write
n
0x0
0x0
PRI_22
PRI_22
0
8
IPR23
IPR23
Interrupt Priority Register 23
0x317
8
read-write
n
0x0
0x0
PRI_23
PRI_23
0
8
IPR24
IPR24
Interrupt Priority Register 24
0x318
8
read-write
n
0x0
0x0
PRI_24
PRI_24
0
8
IPR25
IPR25
Interrupt Priority Register 25
0x319
8
read-write
n
0x0
0x0
PRI_25
PRI_25
0
8
IPR26
IPR26
Interrupt Priority Register 26
0x31A
8
read-write
n
0x0
0x0
PRI_26
PRI_26
0
8
IPR27
IPR27
Interrupt Priority Register 27
0x31B
8
read-write
n
0x0
0x0
PRI_27
PRI_27
0
8
IPR28
IPR28
Interrupt Priority Register 28
0x31C
8
read-write
n
0x0
0x0
PRI_28
PRI_28
0
8
IPR29
IPR29
Interrupt Priority Register 29
0x31D
8
read-write
n
0x0
0x0
PRI_29
PRI_29
0
8
IPR3
IPR3
Interrupt Priority Register 3
0x303
8
read-write
n
0x0
0x0
PRI_03
PRI_03
0
8
IPR30
IPR30
Interrupt Priority Register 30
0x31E
8
read-write
n
0x0
0x0
PRI_30
PRI_30
0
8
IPR31
IPR31
Interrupt Priority Register 31
0x31F
8
read-write
n
0x0
0x0
PRI_31
PRI_31
0
8
IPR32
IPR32
Interrupt Priority Register 32
0x320
8
read-write
n
0x0
0x0
PRI_32
PRI_32
0
8
IPR33
IPR33
Interrupt Priority Register 33
0x321
8
read-write
n
0x0
0x0
PRI_33
PRI_33
0
8
IPR34
IPR34
Interrupt Priority Register 34
0x322
8
read-write
n
0x0
0x0
PRI_34
PRI_34
0
8
IPR35
IPR35
Interrupt Priority Register 35
0x323
8
read-write
n
0x0
0x0
PRI_35
PRI_35
0
8
IPR36
IPR36
Interrupt Priority Register 36
0x324
8
read-write
n
0x0
0x0
PRI_36
PRI_36
0
8
IPR37
IPR37
Interrupt Priority Register 37
0x325
8
read-write
n
0x0
0x0
PRI_37
PRI_37
0
8
IPR38
IPR38
Interrupt Priority Register 38
0x326
8
read-write
n
0x0
0x0
PRI_38
PRI_38
0
8
IPR39
IPR39
Interrupt Priority Register 39
0x327
8
read-write
n
0x0
0x0
PRI_39
PRI_39
0
8
IPR4
IPR4
Interrupt Priority Register 4
0x304
8
read-write
n
0x0
0x0
PRI_04
PRI_04
0
8
IPR40
IPR40
Interrupt Priority Register 40
0x328
8
read-write
n
0x0
0x0
PRI_40
PRI_40
0
8
IPR41
IPR41
Interrupt Priority Register 41
0x329
8
read-write
n
0x0
0x0
PRI_41
PRI_41
0
8
IPR42
IPR42
Interrupt Priority Register 42
0x32A
8
read-write
n
0x0
0x0
PRI_42
PRI_42
0
8
IPR43
IPR43
Interrupt Priority Register 43
0x32B
8
read-write
n
0x0
0x0
PRI_43
PRI_43
0
8
IPR44
IPR44
Interrupt Priority Register 44
0x32C
8
read-write
n
0x0
0x0
PRI_44
PRI_44
0
8
IPR45
IPR45
Interrupt Priority Register 45
0x32D
8
read-write
n
0x0
0x0
PRI_45
PRI_45
0
8
IPR46
IPR46
Interrupt Priority Register 46
0x32E
8
read-write
n
0x0
0x0
PRI_46
PRI_46
0
8
IPR47
IPR47
Interrupt Priority Register 47
0x32F
8
read-write
n
0x0
0x0
PRI_47
PRI_47
0
8
IPR48
IPR48
Interrupt Priority Register 48
0x330
8
read-write
n
0x0
0x0
PRI_48
PRI_48
0
8
IPR49
IPR49
Interrupt Priority Register 49
0x331
8
read-write
n
0x0
0x0
PRI_49
PRI_49
0
8
IPR5
IPR5
Interrupt Priority Register 5
0x305
8
read-write
n
0x0
0x0
PRI_05
PRI_05
0
8
IPR50
IPR50
Interrupt Priority Register 50
0x332
8
read-write
n
0x0
0x0
PRI_50
PRI_50
0
8
IPR51
IPR51
Interrupt Priority Register 51
0x333
8
read-write
n
0x0
0x0
PRI_51
PRI_51
0
8
IPR52
IPR52
Interrupt Priority Register 52
0x334
8
read-write
n
0x0
0x0
PRI_52
PRI_52
0
8
IPR53
IPR53
Interrupt Priority Register 53
0x335
8
read-write
n
0x0
0x0
PRI_53
PRI_53
0
8
IPR54
IPR54
Interrupt Priority Register 54
0x336
8
read-write
n
0x0
0x0
PRI_54
PRI_54
0
8
IPR55
IPR55
Interrupt Priority Register 55
0x337
8
read-write
n
0x0
0x0
PRI_55
PRI_55
0
8
IPR56
IPR56
Interrupt Priority Register 56
0x338
8
read-write
n
0x0
0x0
PRI_56
PRI_56
0
8
IPR57
IPR57
Interrupt Priority Register 57
0x339
8
read-write
n
0x0
0x0
PRI_57
PRI_57
0
8
IPR58
IPR58
Interrupt Priority Register 58
0x33A
8
read-write
n
0x0
0x0
PRI_58
PRI_58
0
8
IPR59
IPR59
Interrupt Priority Register 59
0x33B
8
read-write
n
0x0
0x0
PRI_59
PRI_59
0
8
IPR6
IPR6
Interrupt Priority Register 6
0x306
8
read-write
n
0x0
0x0
PRI_06
PRI_06
0
8
IPR60
IPR60
Interrupt Priority Register 60
0x33C
8
read-write
n
0x0
0x0
PRI_60
PRI_60
0
8
IPR61
IPR61
Interrupt Priority Register 61
0x33D
8
read-write
n
0x0
0x0
PRI_61
PRI_61
0
8
IPR62
IPR62
Interrupt Priority Register 62
0x33E
8
read-write
n
0x0
0x0
PRI_62
PRI_62
0
8
IPR63
IPR63
Interrupt Priority Register 63
0x33F
8
read-write
n
0x0
0x0
PRI_63
PRI_63
0
8
IPR64
IPR64
Interrupt Priority Register 64
0x340
8
read-write
n
0x0
0x0
PRI_64
PRI_64
0
8
IPR65
IPR65
Interrupt Priority Register 65
0x341
8
read-write
n
0x0
0x0
PRI_65
PRI_65
0
8
IPR66
IPR66
Interrupt Priority Register 66
0x342
8
read-write
n
0x0
0x0
PRI_66
PRI_66
0
8
IPR67
IPR67
Interrupt Priority Register 67
0x343
8
read-write
n
0x0
0x0
PRI_67
PRI_67
0
8
IPR68
IPR68
Interrupt Priority Register 68
0x344
8
read-write
n
0x0
0x0
PRI_68
PRI_68
0
8
IPR69
IPR69
Interrupt Priority Register 69
0x345
8
read-write
n
0x0
0x0
PRI_69
PRI_69
0
8
IPR7
IPR7
Interrupt Priority Register 7
0x307
8
read-write
n
0x0
0x0
PRI_07
PRI_07
0
8
IPR70
IPR70
Interrupt Priority Register 70
0x346
8
read-write
n
0x0
0x0
PRI_70
PRI_70
0
8
IPR71
IPR71
Interrupt Priority Register 71
0x347
8
read-write
n
0x0
0x0
PRI_71
PRI_71
0
8
IPR72
IPR72
Interrupt Priority Register 72
0x348
8
read-write
n
0x0
0x0
PRI_72
PRI_72
0
8
IPR73
IPR73
Interrupt Priority Register 73
0x349
8
read-write
n
0x0
0x0
PRI_73
PRI_73
0
8
IPR8
IPR8
Interrupt Priority Register 8
0x308
8
read-write
n
0x0
0x0
PRI_08
PRI_08
0
8
IPR9
IPR9
Interrupt Priority Register 9
0x309
8
read-write
n
0x0
0x0
PRI_09
PRI_09
0
8
ISER
ISER
Interrupt Set Enable Register
0x0
32
read-write
n
0x0
0x0
SETENA
SETENA
0
32
ISPR
ISPR
Interrupt Set-Pending Register
0x100
32
read-write
n
0x0
0x0
SETPEND
SETPEND
0
32
STIR
STIR
Software Trigger Interrupt Register
0xE00
32
write-only
n
0x0
0x0
STIR
STIR
0
32
PMU
Power management unit
PMU
0x0
0x0
0x400
registers
n
CS
CS
power control/status register
0x4
32
read-write
n
0x0
0x0
HDRF
High-driver ready flag
16
1
read-write
HDSRF
High-driver switch ready flag
17
1
read-write
LDOVSRF
LDO voltage select ready flag
15
1
read-write
LDRF
Low-driver mode ready flag
18
2
read-write
LVDF
Low Voltage Detector Status Flag
2
1
read-only
STBF
Standby flag
1
1
read-only
WUF
Wakeup flag
0
1
read-only
WUPEN0
WKUP pin0 Enable
8
1
read-write
WUPEN1
WKUP pin1 Enable
9
1
read-write
WUPEN4
WKUP pin4 Enable
12
1
read-write
WUPEN5
WKUP pin5 Enable
13
1
read-write
WUPEN6
WKUP pin6 Enable
14
1
read-write
CTL
CTL
power control register
0x0
32
read-write
n
0x0
0x0
BKPWEN
Backup Domain Write Enable
8
1
HDEN
High-driver mode enable
16
1
HDS
High-driver mode switch
17
1
LDEN
Low-driver mode enable in Deep-sleep mode
18
2
LDLP
Low-driver mode when use low power LDO
10
1
LDNP
Low-driver mode when use normal power LDO
11
1
LDOLP
LDO Low Power Mode
0
1
LDOVS
LDO output voltage select
14
2
LVDEN
Low Voltage Detector Enable
4
1
LVDT
Low Voltage Detector Threshold
5
3
STBMOD
Standby Mode
1
1
STBRST
Standby Flag Reset
3
1
WURST
Wakeup Flag Reset
2
1
RCU
Reset and clock unit
RCU
0x0
0x0
0x400
registers
n
RCU
4
ADDAPB1EN
ADDAPB1EN
APB1 additional enable register
0xF8
32
read-write
n
0x0
0x0
CTCEN
CTC clock enable
27
1
read-write
ADDAPB1RST
ADDAPB1RST
APB1 additional reset register
0xFC
32
read-write
n
0x0
0x0
CTCRST
CTC reset
27
1
read-write
ADDCTL
ADDCTL
Additional clock control register
0xC0
32
read-write
n
0x0
0x0
CK48MSEL
48MHz clock selection
0
1
read-write
IRC48MCALIB
Internal 48MHz RC oscillator calibration value register
24
8
read-write
IRC48MEN
Internal 48MHz RC oscillator enable
16
1
read-write
IRC48MSTB
Internal 48MHz RC oscillator clock stabilization Flag
17
1
read-write
ADDINT
ADDINT
Additional clock interrupt register
0xCC
32
read-write
n
0x0
0x0
IRC48MSTBIC
Internal 48 MHz RC oscillator Stabilization Interrupt Clear
22
1
read-write
IRC48MSTBIE
Internal 48 MHz RC oscillator Stabilization Interrupt Enable
14
1
read-write
IRC48MSTBIF
IRC48M stabilization interrupt flag
6
1
read-only
AHBEN
AHBEN
AHB enable register (RCU_AHBEN)
0x14
32
read-write
n
0x0
0x0
CRCEN
CRC clock enable
6
1
DMAEN
DMA clock enable
0
1
FMCSPEN
FMC clock enable
4
1
PAEN
GPIO port A clock enable
17
1
PBEN
GPIO port B clock enable
18
1
PCEN
GPIO port C clock enable
19
1
PDEN
GPIO port D clock enable
20
1
PFEN
GPIO port F clock enable
22
1
SRAMSPEN
SRAM interface clock enable
2
1
TSIEN
TSI clock enable
24
1
USBFSEN
USBFS clock enable
12
1
AHBRST
AHBRST
AHB reset register
0x28
32
read-write
n
0x0
0x0
PARST
GPIO port A reset
17
1
PBRST
GPIO port B reset
18
1
PCRST
GPIO port C reset
19
1
PDRST
GPIO port D reset
20
1
PFRST
GPIO port F reset
22
1
TSIRST
TSI unit reset
24
1
USBFSRST
USBFS unit reset
12
1
APB1EN
APB1EN
APB1 enable register (RCU_APB1EN)
0x1C
32
read-write
n
0x0
0x0
CECEN
HDMI CEC interface clock enable
30
1
DACEN
DAC interface clock enable
29
1
I2C0EN
I2C0 clock enable
21
1
I2C1EN
I2C1 clock enable
22
1
PMUEN
Power interface clock enable
28
1
SPI1EN
SPI1 clock enable
14
1
TIMER13EN
TIMER13 timer clock enable
8
1
TIMER1EN
TIMER1 timer clock enable
0
1
TIMER2EN
TIMER2 timer clock enable
1
1
TIMER5EN
TIMER5 timer clock enable
4
1
USART1EN
USART1 clock enable
17
1
WWDGTEN
Window watchdog timer clock enable
11
1
APB1RST
APB1RST
APB1 reset register (RCU_APB1RST)
0x10
32
read-write
n
0x0
0x0
CECRST
HDMI CEC reset
30
1
DACRST
DAC reset
29
1
I2C0RST
I2C0 reset
21
1
I2C1RST
I2C1 reset
22
1
PMURST
Power control reset
28
1
SPI1RST
SPI1 reset
14
1
TIMER13RST
TIMER13 timer reset
8
1
TIMER1RST
TIMER1 timer reset
0
1
TIMER2RST
TIMER2 timer reset
1
1
TIMER5RST
TIMER5 timer reset
4
1
USART1RST
USART1 reset
17
1
WWDGTRST
Window watchdog timer reset
11
1
APB2EN
APB2EN
APB2 enable register (RCU_APB2EN)
0x18
32
read-write
n
0x0
0x0
ADCEN
ADC interface clock enable
9
1
CFGCMPEN
System configuration and comparator clock enable
0
1
SPI0EN
SPI0 clock enable
12
1
TIMER0EN
TIMER0 timer clock enable
11
1
TIMER14EN
TIMER14 timer clock enable
16
1
TIMER15EN
TIMER15 timer clock enable
17
1
TIMER16EN
TIMER16 timer clock enable
18
1
USART0EN
USART0 clock enable
14
1
APB2RST
APB2RST
APB2 reset register (RCU_APB2RST)
0xC
32
read-write
n
0x0
0x0
ADCRST
ADC reset
9
1
CFGCMPRST
System configuration and comparator reset
0
1
SPI0RST
SPI0 Reset
12
1
TIMER0RST
TIMER0 reset
11
1
TIMER14RST
TIMER14 reset
16
1
TIMER15RST
TIMER15 reset
17
1
TIMER16RST
TIMER16 reset
18
1
USART0RST
USART0 Reset
14
1
BDCTL
BDCTL
Backup domain control register (RCU_BDCTL)
0x20
32
read-write
n
0x0
0x0
BKPRST
Backup domain reset
16
1
read-write
LXTALBPS
LXTAL bypass mode enable
2
1
read-write
LXTALDRI
LXTAL drive capability
3
2
read-write
LXTALEN
LXTAL enable
0
1
read-write
LXTALSTB
External low-speed oscillator stabilization
1
1
read-only
RTCEN
RTC clock enable
15
1
read-write
RTCSRC
RTC clock entry selection
8
2
read-write
CFG0
CFG0
Clock configuration register 0 (RCU_CFG0)
0x4
32
read-write
n
0x0
0x0
ADCPSC
ADC clock prescaler selection
14
2
read-write
AHBPSC
AHB prescaler selection
4
4
read-write
APB1PSC
APB1 prescaler selection
8
3
read-write
APB2PSC
APB2 prescaler selection
11
3
read-write
CKOUTDIV
The CK_OUT divider which the CK_OUT frequency can be reduced
28
3
read-write
CKOUTSEL
CK_OUT Clock Source Selection
24
3
read-write
PLLDV
The CK_PLL divide by 1 or 2 for CK_OUT
31
1
read-write
PLLMF
PLL multiply factor
18
4
read-write
PLLMF_MSB
Bit 4 of PLLMF register
27
1
read-write
PLLPREDV
HXTAL divider for PLL source clock selection.
17
1
read-write
PLLSEL
PLL Clock Source Selection
16
1
read-write
SCS
System clock switch
0
2
read-write
SCSS
System clock switch status
2
2
read-only
USBFSPSC
USBFS clock prescaler selection
22
2
read-write
CFG1
CFG1
Configuration register 1
0x2C
32
read-write
n
0x0
0x0
PLLMF
Bit 5 of PLLMF
31
1
PLLPRESEL
PLL clock source preselection
30
1
PREDV
CK_HXTAL or CK_IRC48M divider previous PLL
0
4
CFG2
CFG2
Configuration register 2
0x30
32
read-write
n
0x0
0x0
ADCPSC
Bit 2 of ADCPSC
31
1
ADCSEL
CK_ADC clock source selection
8
1
CECSEL
CK_CEC clock source selection
6
1
IRC28MDIV
CK_IRC28M divider 2 or not
16
1
USART0SEL
CK_USART0 clock source selection
0
2
USBFSPSC
Bit 2 of USBFSPSC
30
1
CTL0
CTL0
Control register 0
0x0
32
read-write
n
0x0
0x0
CKMEN
HXTAL Clock Monitor Enable
19
1
read-write
HXTALBPS
External crystal oscillator (HXTAL) clock bypass mode enable
18
1
read-write
HXTALEN
External High Speed oscillator Enable
16
1
read-write
HXTALSTB
External crystal oscillator (HXTAL) clock stabilization flag
17
1
read-only
IRC8MADJ
High Speed Internal Oscillator clock trim adjust value
3
5
read-write
IRC8MCALIB
High Speed Internal Oscillator calibration value register
8
8
read-only
IRC8MEN
Internal High Speed oscillator Enable
0
1
read-write
IRC8MSTB
IRC8M High Speed Internal Oscillator stabilization Flag
1
1
read-only
PLLEN
PLL enable
24
1
read-write
PLLSTB
PLL Clock Stabilization Flag
25
1
read-only
CTL1
CTL1
Control register 1
0x34
32
read-write
n
0x0
0x0
IRC28MADJ
Internal 28M RC Oscillator clock trim adjust value
3
5
read-write
IRC28MCALIB
Internal 28M RC Oscillator calibration value register
8
8
read-only
IRC28MEN
IRC28M Internal 28M RC oscillator Enable
0
1
read-write
IRC28MSTB
IRC28M Internal 28M RC Oscillator stabilization Flag
1
1
read-only
DSV
DSV
Deep-sleep mode voltage register
0x134
32
read-write
n
0x0
0x0
DSLPVS
Deep-sleep mode voltage select
0
2
read-write
INT
INT
Clock interrupt register (RCU_INT)
0x8
32
read-write
n
0x0
0x0
CKMIC
HXTAL Clock Stuck Interrupt Clear
23
1
write-only
CKMIF
HXTAL Clock Stuck Interrupt Flag
7
1
read-only
HXTALSTBIC
HXTAL Stabilization Interrupt Clear
19
1
write-only
HXTALSTBIE
HXTAL Stabilization Interrupt Enable
11
1
read-write
HXTALSTBIF
HXTAL stabilization interrupt flag
3
1
read-only
IRC28MSTBIC
IRC28M stabilization Interrupt Clear
21
1
write-only
IRC28MSTBIE
IRC28M Stabilization Interrupt Enable
13
1
read-write
IRC28MSTBIF
IRC28M stabilization interrupt flag
5
1
read-only
IRC40KSTBIC
IRC40K Stabilization Interrupt Clear
16
1
write-only
IRC40KSTBIE
IRC40K Stabilization interrupt enable
8
1
read-write
IRC40KSTBIF
IRC40K stabilization interrupt flag
0
1
read-only
IRC8MSTBIC
IRC8M Stabilization Interrupt Clear
18
1
write-only
IRC8MSTBIE
IRC8M Stabilization Interrupt Enable
10
1
read-write
IRC8MSTBIF
IRC8M stabilization interrupt flag
2
1
read-only
LXTALSTBIC
LXTAL Stabilization Interrupt Clear
17
1
write-only
LXTALSTBIE
LXTAL Stabilization Interrupt Enable
9
1
read-write
LXTALSTBIF
LXTAL stabilization interrupt flag
1
1
read-only
PLLSTBIC
PLL stabilization Interrupt Clear
20
1
write-only
PLLSTBIE
PLL Stabilization Interrupt Enable
12
1
read-write
PLLSTBIF
PLL stabilization interrupt flag
4
1
read-only
RSTSCK
RSTSCK
Reset source /clock register (RCU_RSTSCK)
0x24
32
read-write
n
0x0
0x0
EPRSTF
External PIN reset flag
26
1
read-write
FWDGTRSTF
Free Watchdog timer reset flag
29
1
read-write
IRC40KEN
IRC40K enable
0
1
read-write
IRC40KSTB
IRC40K stabilization
1
1
read-only
LPRSTF
Low-power reset flag
31
1
read-write
OBLRSTF
Option byte loader reset flag
25
1
read-write
PORRSTF
Power reset flag
27
1
read-write
RSTFC
Reset flag clear
24
1
read-write
SWRSTF
Software reset flag
28
1
read-write
V12RSTF
V12 domain Power reset flag
23
1
read-write
WWDGTRSTF
Window watchdog timer reset flag
30
1
read-write
VKEY
VKEY
Voltage key register
0x100
32
read-write
n
0x0
0x0
KEY
The key of RCU_DSV register
0
32
read-write
RTC
Real-time clock
RTC
0x0
0x0
0x400
registers
n
RTC
2
ALRM0SS
ALRM0SS
alarm 0 sub second register
0x44
32
read-write
n
0x0
0x0
MSKSSC
Mask control bit of SSC
24
4
SSC
Alarm sub second value
0
15
ALRM0TD
ALRM0TD
alarm A register
0x1C
32
read-write
n
0x0
0x0
DAYT
Date tens in BCD format.
28
2
DAYU
Date units or day in BCD format.
24
4
DOWS
Week day selection
30
1
HRT
Hour tens in BCD format.
20
2
HRU
Hour units in BCD format.
16
4
MNT
Minute tens in BCD format.
12
3
MNU
Minute units in BCD format.
8
4
MSKD
Alarm date mask
31
1
MSKH
Alarm hours mask
23
1
MSKM
Alarm minutes mask
15
1
MSKS
Alarm seconds mask
7
1
PM
AM/PM notation
22
1
SCT
Second tens in BCD format.
4
3
SCU
Second units in BCD format.
0
4
BKP0
BKP0
backup register
0x50
32
read-write
n
0x0
0x0
DATA
BKP data
0
32
BKP1
BKP1
backup register
0x54
32
read-write
n
0x0
0x0
DATA
BKP data
0
32
BKP2
BKP2
backup register
0x58
32
read-write
n
0x0
0x0
DATA
BKP data
0
32
BKP3
BKP3
backup register
0x5C
32
read-write
n
0x0
0x0
DATA
BKP data
0
32
BKP4
BKP4
backup register
0x60
32
read-write
n
0x0
0x0
DATA
BKP data
0
32
CTL
CTL
control register
0x8
32
read-write
n
0x0
0x0
A1H
Add 1 hour (summer time change)
16
1
write-only
ALRM0EN
Alarm A enable
8
1
read-write
ALRM0IE
Alarm A interrupt enable
12
1
read-write
BPSHAD
Bypass the shadow registers
5
1
read-write
COEN
Calibration output enable
23
1
read-write
COS
Calibration output selection
19
1
read-write
CS
Hour format
6
1
read-write
DSM
Backup
18
1
read-write
OPOL
Output polarity
20
1
read-write
OS
Output selection
21
2
read-write
REFEN
RTC_REFIN reference clock detection enable (50 or 60 Hz)
4
1
read-write
S1H
Subtract 1 hour (winter time change)
17
1
write-only
TSEG
Time-stamp event active edge
3
1
read-write
TSEN
timestamp enable
11
1
read-write
TSIE
Time-stamp interrupt enable
15
1
read-write
DATE
DATE
date register
0x4
32
read-write
n
0x0
0x0
DAYT
Date tens in BCD code
4
2
DAYU
Date units in BCD code
0
4
DOW
Days of the week
13
3
MONT
Month tens in BCD code
12
1
MONU
Month units in BCD code
8
4
YRT
Year tens in BCD code
20
4
YRU
Year units in BCD code
16
4
DTS
DTS
Date of time stamp register
0x34
32
read-only
n
0x0
0x0
DAYT
Date tens in BCD code
4
2
DAYU
Date units in BCD code
0
4
DOW
Week day units
13
3
MONT
Month tens in BCD code
12
1
MONU
Month units in BCD code
8
4
HRFC
HRFC
High resolution frequency compensation register
0x3C
32
read-write
n
0x0
0x0
CMSK
Calibration mask number
0
9
CWND16
Frequency compensation window 16 second selected
13
1
CWND8
Frequency compensation window 8 second selected
14
1
FREQI
Increase RTC frequency by 488.5PPM
15
1
PSC
PSC
prescaler register
0x10
32
read-write
n
0x0
0x0
FACTOR_A
Asynchronous prescaler factor
16
7
FACTOR_S
Synchronous prescaler factor
0
15
SHIFTCTL
SHIFTCTL
shift control register
0x2C
32
write-only
n
0x0
0x0
A1S
One second add
31
1
SFS
Subtract a fraction of a second
0
15
SS
SS
sub second register
0x28
32
read-only
n
0x0
0x0
SSC
Sub second value
0
16
SSTS
SSTS
time-stamp sub second register
0x38
32
read-only
n
0x0
0x0
SSC
Sub second value
0
16
STAT
STAT
initialization and status register
0xC
32
read-write
n
0x0
0x0
ALRM0F
Alarm A flag
8
1
read-write
ALRM0WF
Alarm A write flag
0
1
read-only
INITF
Initialization flag
6
1
read-only
INITM
Initialization mode
7
1
read-write
RSYNF
Registers synchronization flag
5
1
read-write
SCPF
Recalibration pending Flag
16
1
read-only
SOPF
Shift operation pending
3
1
read-write
TP0F
RTC_TAMP0 detection flag
13
1
read-write
TP1F
RTC_TAMP1 detection flag
14
1
read-write
TSF
Time-stamp flag
11
1
read-write
TSOVRF
Time-stamp overflow flag
12
1
read-write
YCM
Initialization status flag
4
1
read-only
TAMP
TAMP
tamper and alternate function configuration register
0x40
32
read-write
n
0x0
0x0
DISPU
RTC_TAMPx pull-up disable
15
1
FLT
RTC_TAMPx filter count
11
2
FREQ
Tamper sampling frequency
8
3
PC13MDE
PC13 mode
19
1
PC13VAL
RTC_ALARM output type/PC13 value
18
1
PC14MDE
PC14 mode
21
1
PC14VAL
PC14 value
20
1
PC15MDE
PC15 mode
23
1
PC15VAL
PC15 value
22
1
PRCH
RTC_TAMPx precharge duration
13
2
TP0EG
Active level for RTC_TAMP1 input
1
1
TP0EN
Tamper 0 event trigger edge
0
1
TP1EG
Tamper 1 event trigger edge
4
1
TP1EN
Tamper 1 detection enable
3
1
TPIE
Tamper detection interrupt enable
2
1
TPTS
Activate timestamp on tamper detection event
7
1
TIME
TIME
time register
0x0
32
read-write
n
0x0
0x0
HRT
Hour tens in BCD code
20
2
HRU
Hour units in BCD format
16
4
MNT
Minute tens in BCD code
12
3
MNU
Minute units in BCD code
8
4
PM
AM/PM mark
22
1
SCT
Second tens in BCD code
4
3
SCU
Second units in BCD code
0
4
TTS
TTS
timestamp time register
0x30
32
read-only
n
0x0
0x0
HRT
Hour tens in BCD code
20
2
HRU
Hour units in BCD code
16
4
MNT
Minute tens in BCD code
12
3
MNU
Minute units in BCD code
8
4
PM
AM/PM mark
22
1
SCT
Second tens in BCD code
4
3
SCU
Second units in BCD code
0
4
WPK
WPK
write protection register
0x24
32
write-only
n
0x0
0x0
WPK
Write protection key
0
8
SPI0
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI0
25
CPCPOLY
CPCPOLY
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CPR
CRC polynomial register
0
16
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
BDEN
Bidirectional enable
15
1
BDOEN
Bidirectional Transmit output enable
14
1
CKPH
Clock Phase Selection
0
1
CKPL
Clock Polarity Selection
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNT
CRC transfer next
12
1
FF16
Data frame format
11
1
LF
LSB First Mode
7
1
MSTMOD
Master Mode Enable
2
1
PSC
Master Clock Prescaler Selection
3
3
RO
Receive only
10
1
SPIEN
SPI enable
6
1
SWNSS
NSS Pin Selection In NSS Software Mode
8
1
SWNSSEN
NSS Software Mode Selection
9
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
DMAREN
Rx buffer DMA enable
0
1
DMATEN
Tx buffer DMA enable
1
1
ERRIE
Error interrupt enable
5
1
NSSDRV
NSS output enable
2
1
NSSP
SPI NSS Pulse Mode Enable
3
1
RBNEIE
Receive Buffer Not Empty Interrupt Enable
6
1
TBEIE
Transmit Buffer Empty Interrupt Enable
7
1
TMOD
SPI TI Mode Enable
4
1
DATA
DATA
data register
0xC
32
read-write
n
0x0
0x0
DATA
Data register
0
16
I2SCTL
I2SCTL
I2S configuration register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPL
Idle state clock polarity
3
1
DTLEN
Data length to be transferred
1
2
I2SEN
I2S Enable
10
1
I2SOPMOD
I2S configuration mode
8
2
I2SSEL
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSMOD
PCM frame synchronization
7
1
I2SPSC
I2SPSC
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
DIV
Dividing factor for the prescaler
0
8
MCKOEN
I2S_MCK output enable
9
1
OF
Odd factor for the prescaler
8
1
QCTL
QCTL
SPI quad wird control register
0x80
32
read-write
n
0x0
0x0
IO23_DRV
Drive IO2 and IO3 enable
2
1
QMOD
Quad wire mode enable
0
1
QRD
Quad wire read select
1
1
RCRC
RCRC
RX CRC register
0x14
32
read-only
n
0x0
0x0
RCR
RX RCR register
0
16
STAT
STAT
status register
0x8
32
read-write
n
0x0
0x0
CONFERR
SPI Configuration error
5
1
read-only
CRCERR
SPI CRC Error Bit
4
1
read-write
FERR
Format Error
8
1
read-only
I2SCH
I2S channel side
2
1
read-only
RBNE
Receive Buffer Not Empty
0
1
read-only
RXORERR
Reception Overrun Error Bit
6
1
read-only
TBE
Transmit Buffer Empty
1
1
read-only
TRANS
Transmitting On-going Bit
7
1
read-only
TXURERR
Transmission underrun error bit
3
1
read-only
TCRC
TCRC
TX CRC register
0x18
32
read-only
n
0x0
0x0
TCR
Tx CRC register
0
16
SPI1
Serial peripheral interface
SPI
0x0
0x0
0x400
registers
n
SPI1
26
CPCPOLY
CPCPOLY
CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CPR
CRC polynomial register
0
16
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
BDEN
Bidirectional enable
15
1
BDOEN
Bidirectional Transmit output enable
14
1
CKPH
Clock Phase Selection
0
1
CKPL
Clock Polarity Selection
1
1
CRCEN
Hardware CRC calculation enable
13
1
CRCNT
CRC transfer next
12
1
FF16
Data frame format
11
1
LF
LSB First Mode
7
1
MSTMOD
Master Mode Enable
2
1
PSC
Master Clock Prescaler Selection
3
3
RO
Receive only
10
1
SPIEN
SPI enable
6
1
SWNSS
NSS Pin Selection In NSS Software Mode
8
1
SWNSSEN
NSS Software Mode Selection
9
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
DMAREN
Rx buffer DMA enable
0
1
DMATEN
Tx buffer DMA enable
1
1
ERRIE
Error interrupt enable
5
1
NSSDRV
NSS output enable
2
1
NSSP
SPI NSS Pulse Mode Enable
3
1
RBNEIE
Receive Buffer Not Empty Interrupt Enable
6
1
TBEIE
Transmit Buffer Empty Interrupt Enable
7
1
TMOD
SPI TI Mode Enable
4
1
DATA
DATA
data register
0xC
32
read-write
n
0x0
0x0
DATA
Data register
0
16
I2SCTL
I2SCTL
I2S configuration register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length (number of bits per audio channel)
0
1
CKPL
Idle state clock polarity
3
1
DTLEN
Data length to be transferred
1
2
I2SEN
I2S Enable
10
1
I2SOPMOD
I2S configuration mode
8
2
I2SSEL
I2S mode selection
11
1
I2SSTD
I2S standard selection
4
2
PCMSMOD
PCM frame synchronization
7
1
I2SPSC
I2SPSC
I2S prescaler register
0x20
32
read-write
n
0x0
0x0
DIV
Dividing factor for the prescaler
0
8
MCKOEN
I2S_MCK output enable
9
1
OF
Odd factor for the prescaler
8
1
QCTL
QCTL
SPI quad wird control register
0x80
32
read-write
n
0x0
0x0
IO23_DRV
Drive IO2 and IO3 enable
2
1
QMOD
Quad wire mode enable
0
1
QRD
Quad wire read select
1
1
RCRC
RCRC
RX CRC register
0x14
32
read-only
n
0x0
0x0
RCR
RX RCR register
0
16
STAT
STAT
status register
0x8
32
read-write
n
0x0
0x0
CONFERR
SPI Configuration error
5
1
read-only
CRCERR
SPI CRC Error Bit
4
1
read-write
FERR
Format Error
8
1
read-only
I2SCH
I2S channel side
2
1
read-only
RBNE
Receive Buffer Not Empty
0
1
read-only
RXORERR
Reception Overrun Error Bit
6
1
read-only
TBE
Transmit Buffer Empty
1
1
read-only
TRANS
Transmitting On-going Bit
7
1
read-only
TXURERR
Transmission underrun error bit
3
1
read-only
TCRC
TCRC
TX CRC register
0x18
32
read-only
n
0x0
0x0
TCR
Tx CRC register
0
16
SYSCFG
System configuration controller
SYSCFG
0x0
0x0
0x2C
registers
n
CFG0
CFG0
System configuration register 0
0x0
32
read-write
n
0x0
0x0
ADC_DMA_RMP
ADC DMA request remapping enable
8
1
BOOT_MODE
Boot mode
0
2
read-only
PB9_HCCE
PB9 pin high current capability enable
19
1
TIMER15_DMA_RMP
Timer 15 DMA request remapping enable
11
1
TIMER16_DMA_RMP
Timer 16 DMA request remapping enable
12
1
USART0_RX_DMA_RMP
USART0_RX DMA request remapping enable
10
1
USART0_TX_DMA_RMP
USART0_TX DMA request remapping enable
9
1
CFG2
CFG2
System configuration register 2
0x18
32
read-write
n
0x0
0x0
LOCKUP_LOCK
Cortex-M4 LOCKUP output lock
0
1
LVD_LOCK
LVD lock
2
1
SRAM_PARITY_ERROR_LOCK
SRAM parity check error lock
1
1
SRAM_PCEF
SRAM parity check error flag
8
1
CPSCTL
CPSCTL
I/O compensation control register
0x20
32
read-write
n
0x0
0x0
CPS_EN
I/O compensation cell enable
0
1
CPS_RDY
I/O compensation cell is ready
8
1
EXTISS0
EXTISS0
EXTI sources selection register 0
0x8
32
read-write
n
0x0
0x0
EXTI0_SS
EXTI 0 sources selection
0
4
EXTI1_SS
EXTI 1 sources selection
4
4
EXTI2_SS
EXTI 2 sources selection
8
4
EXTI3_SS
EXTI 3 sources selection
12
4
EXTISS1
EXTISS1
EXTI sources selection register 1
0xC
32
read-write
n
0x0
0x0
EXTI4_SS
EXTI 4 sources selection
0
4
EXTI5_SS
EXTI 5 sources selection
4
4
EXTI6_SS
EXTI 6 sources selection
8
4
EXTI7_SS
EXTI 7 sources selection
12
4
EXTISS2
EXTISS2
EXTI sources selection register 2
0x10
32
read-write
n
0x0
0x0
EXTI10_SS
EXTI 10 sources selection
8
4
EXTI11_SS
EXTI 11 sources selection
12
4
EXTI8_SS
EXTI 8 sources selection
0
4
EXTI9_SS
EXTI 9 sources selection
4
4
EXTISS3
EXTISS3
EXTI sources selection register 3
0x14
32
read-write
n
0x0
0x0
EXTI12_SS
EXTI 12 sources selection
0
4
EXTI13_SS
EXTI 13 sources selection
4
4
EXTI14_SS
EXTI 14 sources selection
8
4
EXTI15_SS
EXTI 15 sources selection
12
4
TIMER0
Advanced-timers
TIMER
0x0
0x0
0x400
registers
n
TIMER0_BRK_UP_TRG_COM
13
TIMER0_CC
14
CAR
CAR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
CARL
Counter auto reload value
0
16
CCHP
CCHP
channel complementary protection register
0x44
32
read-write
n
0x0
0x0
BRKEN
Break enable
12
1
BRKP
Break polarity
13
1
DTCFG
Dead-time generator setup
0
8
IOS
Off-state selection for Idle mode
10
1
OAEN
Automatic output enable
14
1
POEN
Main output enable
15
1
PROT
Lock configuration
8
2
ROS
Off-state selection for Run mode
11
1
CFG
CFG
Configuration register
0xFC
32
read-write
n
0x0
0x0
CHVSEL
Write CHxVAL register selection
1
1
OUTSEL
The output value selection
0
1
CH0CV
CH0CV
capture/compare register 0
0x34
32
read-write
n
0x0
0x0
CH0VAL
Capture/Compare 0 value
0
16
CH1CV
CH1CV
capture/compare register 1
0x38
32
read-write
n
0x0
0x0
CH1VAL
Capture/Compare 1 value
0
16
CH2CV
CH2CV
capture/compare register 2
0x3C
32
read-write
n
0x0
0x0
CH2VAL
Capture/Compare 2 value
0
16
CH3CV
CH3CV
capture/compare register 3
0x40
32
read-write
n
0x0
0x0
CH3VAL
Capture/Compare 3 value
0
16
CHCTL0_Input
CHCTL0_Input
capture/compare mode register 0 (input mode)
CHCTL0_Output
0x18
32
read-write
n
0x0
0x0
CH0CAPFLT
Channel 0 input capture filter control
4
4
CH0CAPPSC
Channel 0 input capture prescaler
2
2
CH0MS
Channel 0 mode selection
0
2
CH1CAPFLT
Channel 1 input capture filter control
12
4
CH1CAPPSC
Channel 1 input capture prescaler
10
2
CH1MS
Channel 1 mode selection
8
2
CHCTL0_Output
CHCTL0_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CH0COMCEN
Channel 0 output compare clear enable
7
1
CH0COMCTL
Channel 0 compare output control
4
3
CH0COMFEN
Channel 0 output compare fast enable
2
1
CH0COMSEN
Channel 0 compare output shadow enable
3
1
CH0MS
Channel 0 I/O mode selection
0
2
CH1COMCEN
Channel 1 output compare clear enable
15
1
CH1COMCTL
Channel 1 compare output control
12
3
CH1COMFEN
Channel 1 output compare fast enable
10
1
CH1COMSEN
Channel 1 output compare shadow enable
11
1
CH1MS
Channel 1 mode selection
8
2
CHCTL1_Input
CHCTL1_Input
capture/compare mode register 1 (input mode)
CHCTL1_Output
0x1C
32
read-write
n
0x0
0x0
CH2CAPFLT
Input capture 2 filter
4
4
CH2CAPPSC
Input capture 2 prescaler
2
2
CH2MS
Capture/compare 2 selection
0
2
CH3CAPFLT
Channel 3 input capture filter control
12
4
CH3CAPPSC
Channel 3 input capture prescaler
10
2
CH3MS
Channel 3 mode selection
8
2
CHCTL1_Output
CHCTL1_Output
capture/compare mode register (output mode)
0x1C
32
read-write
n
0x0
0x0
CH2COMCEN
Channel 2 output compare clear enable
7
1
CH2COMCTL
Channel 2 compare output control
4
3
CH2COMFEN
Channel 2 output compare fast enable
2
1
CH2COMSEN
Channel 2 compare output shadow enable
3
1
CH2MS
Channel 2 I/O mode selection
0
2
CH3COMCEN
Channel 3 output compare clear enable
15
1
CH3COMCTL
Channel 3 compare output control
12
3
CH3COMFEN
Channel 3 output compare fast enable
10
1
CH3COMSEN
Channel 3 output compare shadow enable
11
1
CH3MS
Channel 3 mode selection
8
2
CHCTL2
CHCTL2
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CH0EN
Capture/Compare 1 output enable
0
1
CH0NEN
Capture/Compare 0 complementary output enable
2
1
CH0NP
Capture/Compare 0 output Polarity
3
1
CH0P
Capture/Compare 0 output Polarity
1
1
CH1EN
Capture/Compare 1 output enable
4
1
CH1NEN
Capture/Compare 1 complementary output enable
6
1
CH1NP
Capture/Compare 1 output Polarity
7
1
CH1P
Capture/Compare 1 output Polarity
5
1
CH2EN
Capture/Compare 2 output enable
8
1
CH2NEN
Capture/Compare 2 complementary output enable
10
1
CH2NP
Capture/Compare 2 output Polarity
11
1
CH2P
Capture/Compare 2 output Polarity
9
1
CH3EN
Capture/Compare 3 output enable
12
1
CH3P
Capture/Compare 3 output Polarity
13
1
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CREP
CREP
repetition counter register
0x30
32
read-write
n
0x0
0x0
CREP
Repetition counter value
0
8
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
ARSE
Auto-reload preload enable
7
1
CAM
Center-aligned mode selection
5
2
CEN
Counter enable
0
1
CKDIV
Clock division
8
2
DIR
Direction
4
1
SPM
One-pulse mode
3
1
UPDIS
Update disable
1
1
UPS
Update request source
2
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
CCSE
Commutation control shadow enable
0
1
CCUC
Commutation control shadow register update control
2
1
DMAS
DMA request source selection
3
1
ISO0
Idle state of channel 0 output
8
1
ISO0N
Idle state of channel 0 complementary output
9
1
ISO1
Idle state of channel 1 output
10
1
ISO1N
Idle state of channel 1 complementary output
11
1
ISO2
Idle state of channel 2 output
12
1
ISO2N
Idle state of channel 2 complementary output
13
1
ISO3
Idle state of channel 3 output
14
1
MMC
Master mode control
4
3
TI0S
Channel 0 trigger input selection
7
1
DMACFG
DMACFG
DMA configuration register
0x48
32
read-write
n
0x0
0x0
DMATA
DMA transfer access start address
0
5
DMATC
DMA transfer count
8
5
DMAINTEN
DMAINTEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BRKIE
Break interrupt enable
7
1
CH0DEN
Capture/Compare 0 DMA request enable
9
1
CH0IE
Capture/Compare 0 interrupt enable
1
1
CH1DEN
Capture/Compare 1 DMA request enable
10
1
CH1IE
Capture/Compare 1 interrupt enable
2
1
CH2DEN
Capture/Compare 2 DMA request enable
11
1
CH2IE
Capture/Compare 2 interrupt enable
3
1
CH3DEN
Capture/Compare 3 DMA request enable
12
1
CH3IE
Capture/Compare 3 interrupt enable
4
1
CMTDEN
Reserved
13
1
CMTIE
COM interrupt enable
5
1
TRGDEN
Trigger DMA request enable
14
1
TRGIE
Trigger interrupt enable
6
1
UPDEN
Update DMA request enable
8
1
UPIE
Update interrupt enable
0
1
DMATB
DMATB
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMATB
DMA register for burst accesses
0
16
INTF
INTF
status register
0x10
32
read-write
n
0x0
0x0
BRKIF
Break interrupt flag
7
1
CH0IF
Capture/compare 0 interrupt flag
1
1
CH0OF
Channel 0 over capture flag
9
1
CH1IF
Capture/Compare 1 interrupt flag
2
1
CH1OF
Channel 1 over capture flag
10
1
CH2IF
Capture/Compare 2 interrupt flag
3
1
CH2OF
Channel 2 over capture flag
11
1
CH3IF
Capture/Compare 3 interrupt flag
4
1
CH3OF
Channel 3 over capture flag
12
1
CMTIF
COM interrupt flag
5
1
TRGIF
Trigger interrupt flag
6
1
UPIF
Update interrupt flag
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCFG
SMCFG
slave mode configuration register
0x8
32
read-write
n
0x0
0x0
ETFC
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPSC
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
OCRC
Trigger selection
3
1
SMC
Slave mode selection
0
3
SMC1
Part of SMC for enable External clock mode1
14
1
TRGS
Trigger selection
4
3
SWEVG
SWEVG
Software event generation register
0x14
32
write-only
n
0x0
0x0
BRKG
Break event generation
7
1
CH0G
Channel 0's capture or compare event generation
1
1
CH1G
Channel 1's capture or compare event generation
2
1
CH2G
Channel 2's capture or compare event generation
3
1
CH3G
Channel 3's capture or compare event generation
4
1
CMTG
Channel commutation event generation
5
1
TRGG
Trigger event generation
6
1
UPG
Update event generation
0
1
TIMER1
General-purpose-timers
TIMER
0x0
0x0
0x400
registers
n
TIMER1
15
CAR
CAR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
CARL
Low Auto-reload value
0
32
CFG
CFG
Configuration
0xFC
32
read-write
n
0x0
0x0
CHVSEL
Write CHxVAL register selection
1
1
CH0CV
CH0CV
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CH0VAL
Low Capture/Compare 1 value
0
32
CH1CV
CH1CV
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CH1VAL
Low Capture/Compare 2 value
0
32
CH2CV
CH2CV
capture/compare register 2
0x3C
32
read-write
n
0x0
0x0
CH2VAL
High Capture/Compare value (TIM2 only)
0
32
CH3CV
CH3CV
capture/compare register 3
0x40
32
read-write
n
0x0
0x0
CH3VAL
High Capture/Compare value (TIM2 only)
0
32
CHCTL0_Input
CHCTL0_Input
capture/compare mode register 0 (input mode)
CHCTL0_Output
0x18
32
read-write
n
0x0
0x0
CH0CAPFLT
Input capture 0 filter
4
4
CH0CAPPSC
Input capture 0 prescaler
2
2
CH0MS
Capture/Compare 0 selection
0
2
CH1CAPFLT
Input capture 1 filter
12
4
CH1CAPPSC
Input capture 1 prescaler
10
2
CH1MS
Capture/compare 1 selection
8
2
CHCTL0_Output
CHCTL0_Output
capture/compare mode register 0 (output mode)
0x18
32
read-write
n
0x0
0x0
CH0COMCEN
Output compare 0 clear enable
7
1
CH0COMCTL
Output compare 0 mode
4
3
CH0COMFEN
Output compare 0 fast enable
2
1
CH0COMSEN
Output compare 0 preload enable
3
1
CH0MS
Capture/Compare 0 selection
0
2
CH1COMCEN
Output compare 1 clear enable
15
1
CH1COMCTL
Output compare 1 mode
12
3
CH1COMFEN
Output compare 1 fast enable
10
1
CH1COMSEN
Output compare 1 preload enable
11
1
CH1MS
Capture/Compare 1 selection
8
2
CHCTL1_Input
CHCTL1_Input
capture/compare mode register 1 (input mode)
CHCTL1_Output
0x1C
32
read-write
n
0x0
0x0
CH2CAPFLT
Input capture 2 filter
4
4
CH2CAPPSC
Input capture 2 prescaler
2
2
CH2MS
Capture/Compare 2 selection
0
2
CH3CAPFLT
Input capture 3 filter
12
4
CH3CAPPSC
Input capture 3 prescaler
10
2
CH3MS
Capture/Compare 3 selection
8
2
CHCTL1_Output
CHCTL1_Output
capture/compare mode register 1 (output mode)
0x1C
32
read-write
n
0x0
0x0
CH2COMCEN
Output compare 2 clear enable
7
1
CH2COMCTL
Output compare 2 mode
4
3
CH2COMFEN
Output compare 2 fast enable
2
1
CH2COMSEN
Output compare 2 preload enable
3
1
CH2MS
Capture/Compare 2 selection
0
2
CH3COMCEN
Output compare 3 clear enable
15
1
CH3COMCTL
Output compare 3 mode
12
3
CH3COMFEN
Output compare 3 fast enable
10
1
CH3COMSEN
Output compare 3 preload enable
11
1
CH3MS
Capture/Compare 3 selection
8
2
CHCTL2
CHCTL2
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CH0EN
Capture/Compare 0 output enable
0
1
CH0NP
Capture/Compare 0 output Polarity
3
1
CH0P
Capture/Compare 0 output Polarity
1
1
CH1EN
Capture/Compare 1 output enable
4
1
CH1NP
Capture/Compare 1 output Polarity
7
1
CH1P
Capture/Compare 1 output Polarity
5
1
CH2EN
Capture/Compare 2 output enable
8
1
CH2NP
Capture/Compare 2 output Polarity
11
1
CH2P
Capture/Compare 2 output Polarity
9
1
CH3EN
Capture/Compare 3 output enable
12
1
CH3NP
Capture/Compare 3 output Polarity
15
1
CH3P
Capture/Compare 3 output Polarity
13
1
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
32
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
ARSE
Auto-reload preload enable
7
1
CAM
Center-aligned mode selection
5
2
CEN
Counter enable
0
1
CKDIV
Clock division
8
2
DIR
Direction
4
1
SPM
One-pulse mode
3
1
UPDIS
Update disable
1
1
UPS
Update request source
2
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
DMAS
Capture/compare DMA selection
3
1
MMC
Master mode selection
4
3
TI0S
TI0 selection
7
1
DMACFG
DMACFG
DMA control register
0x48
32
read-write
n
0x0
0x0
DMATA
DMA base address
0
5
DMATC
DMA burst length
8
5
DMAINTEN
DMAINTEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CH0DEN
Capture/Compare 1 DMA request enable
9
1
CH0IE
Capture/Compare 0 interrupt enable
1
1
CH1DEN
Capture/Compare 1 DMA request enable
10
1
CH1IE
Capture/Compare 1 interrupt enable
2
1
CH2DEN
Capture/Compare 2 DMA request enable
11
1
CH2IE
Capture/Compare 2 interrupt enable
3
1
CH3DEN
Capture/Compare 3 DMA request enable
12
1
CH3IE
Capture/Compare 3 interrupt enable
4
1
TRGDEN
Trigger DMA request enable
14
1
TRGIE
Trigger interrupt enable
6
1
UPDEN
Update DMA request enable
8
1
UPIE
Update interrupt enable
0
1
DMATB
DMATB
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMATB
DMA register for burst accesses
0
16
INTF
INTF
interrupt flag register
0x10
32
read-write
n
0x0
0x0
CH0IF
Capture/compare 0 interrupt flag
1
1
CH0OF
Capture/Compare 0 overcapture flag
9
1
CH1IF
Capture/Compare 1 interrupt flag
2
1
CH1OF
Capture/compare 1 overcapture flag
10
1
CH2IF
Capture/Compare 2 interrupt flag
3
1
CH2OF
Capture/Compare 2 overcapture flag
11
1
CH3IF
Capture/Compare 3 interrupt flag
4
1
CH3OF
Capture/Compare 3 overcapture flag
12
1
TRGIF
Trigger interrupt flag
6
1
UPIF
Update interrupt flag
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCFG
SMCFG
slave mode control register
0x8
32
read-write
n
0x0
0x0
ETFC
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPSC
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
OCRC
OCREF clear source selection
3
1
SMC
Slave mode selection
0
3
SMC1
External clock enable
14
1
TRGS
Trigger selection
4
3
SWEVG
SWEVG
event generation register
0x14
32
write-only
n
0x0
0x0
CH0G
Capture/compare 0 generation
1
1
CH1G
Capture/compare 1 generation
2
1
CH2G
Capture/compare 2 generation
3
1
CH3G
Capture/compare 3 generation
4
1
TRGG
Trigger generation
6
1
UPG
Update generation
0
1
TIMER13
General-purpose-timers
TIMER
0x0
0x0
0x400
registers
n
TIMER13
19
CAR
CAR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
CARL
Auto-reload value
0
16
CFG
CFG
configuration register
0xFC
32
read-write
n
0x0
0x0
CHVSEL
Write CHxVAL register selection
1
1
CH0CV
CH0CV
capture/compare register 0
0x34
32
read-write
n
0x0
0x0
CH0VAL
Capture/Compare 1 value
0
16
CHCTL0_Input
CHCTL0_Input
capture/compare mode register (input mode)
CHCTL0_Output
0x18
32
read-write
n
0x0
0x0
CH0CAPFLT
Input capture 0 filter
4
4
CH0CAPPSC
Input capture 0 prescaler
2
2
CH0MS
Capture/Compare 0 selection
0
2
CHCTL0_Output
CHCTL0_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CH0COMCTL
Output Compare 0 mode
4
3
CH0COMFEN
Output compare 0 fast enable
2
1
CH0COMSEN
Output Compare 0 preload enable
3
1
CH0MS
Capture/Compare 0 selection
0
2
CHCTL2
CHCTL2
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CH0EN
Capture/Compare 1 output enable
0
1
CH0NP
Capture/Compare 0 output Polarity
3
1
CH0P
Capture/Compare 0 output Polarity
1
1
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CTL0
CTL0
control register 1
0x0
32
read-write
n
0x0
0x0
ARSE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKDIV
Clock division
8
2
UPDIS
Update disable
1
1
UPS
Update request source
2
1
DMAINTEN
DMAINTEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CH0IE
Capture/Compare 0 interrupt enable
1
1
UPIE
Update interrupt enable
0
1
INTF
INTF
interrupt flag register
0x10
32
read-write
n
0x0
0x0
CH0IF
Capture/compare 0 interrupt flag
1
1
CH0OF
Capture/Compare 0 overcapture flag
9
1
UPIF
Update interrupt flag
0
1
IRMP
IRMP
channel input remap register
0x50
32
read-write
n
0x0
0x0
CI0_RMP
Timer input 0 remap
0
2
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SWEVG
SWEVG
event generation register
0x14
32
write-only
n
0x0
0x0
CH0G
Capture/compare 0 generation
1
1
UPG
Update generation
0
1
TIMER14
General-purpose-timers
TIMER
0x0
0x0
0x400
registers
n
TIMER14
20
CAR
CAR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
CARL
Auto-reload value
0
16
CCHP
CCHP
break and dead-time register
0x44
32
read-write
n
0x0
0x0
BRKEN
Break enable
12
1
BRKP
Break polarity
13
1
DTCFG
Dead-time generator configure
0
8
IOS
Off-state selection for Idle mode
10
1
OAEN
Automatic output enable
14
1
POEN
Main output enable
15
1
PROT
complementary register protect control
8
2
ROS
Off-state selection for Run mode
11
1
CFG
CFG
configuration register
0xFC
32
read-write
n
0x0
0x0
CHVSEL
Write CHxVAL register selection
1
1
OUTSEL
The output value selection
0
1
CH0CV
CH0CV
capture/compare register 0
0x34
32
read-write
n
0x0
0x0
CH0VAL
Capture/Compare 0 value
0
16
CH1CV
CH1CV
capture/compare register 1
0x38
32
read-write
n
0x0
0x0
CH1VAL
Capture/Compare 1 value
0
16
CHCTL0_Input
CHCTL0_Input
capture/compare mode register 0 (input mode)
CHCTL0_Output
0x18
32
read-write
n
0x0
0x0
CH0CAPFLT
Input capture 0 filter
4
4
CH0CAPPSC
Input capture 0 prescaler
2
2
CH0MS
Capture/Compare 0 selection
0
2
CH1CAPFLT
Input capture 1 filter
12
4
CH1CAPPSC
Input capture 1 prescaler
10
2
CH1MS
Capture/Compare 1 selection
8
2
CHCTL0_Output
CHCTL0_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CH0COMCTL
Output Compare 0 mode
4
3
CH0COMFEN
Output Compare 0 fast enable
2
1
CH0COMSEN
Output Compare 0 preload enable
3
1
CH0MS
Capture/Compare 0 selection
0
2
CH1COMCTL
Output Compare 1 mode
12
3
CH1COMFEN
Output Compare 1 fast enable
10
1
CH1COMSEN
Output Compare 1 preload enable
11
1
CH1MS
Capture/Compare 1 selection
8
2
CHCTL2
CHCTL2
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CH0EN
Capture/Compare 0 output enable
0
1
CH0NEN
Capture/Compare 0 complementary output enable
2
1
CH0NP
Capture/Compare 0 output Polarity
3
1
CH0P
Capture/Compare 0 output Polarity
1
1
CH1EN
Capture/Compare 1 output enable
4
1
CH1NP
Capture/Compare 1 output Polarity
7
1
CH1P
Capture/Compare 1 output Polarity
5
1
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CREP
CREP
repetition counter register
0x30
32
read-write
n
0x0
0x0
CREP
Repetition counter value
0
8
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
ARSE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKDIV
Clock division
8
2
SPM
One-pulse mode
3
1
UPDIS
Update disable
1
1
UPS
Update request source
2
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
CCSE
Capture/compare preloaded control
0
1
CCUC
Capture/compare control update selection
2
1
DMAS
Capture/compare DMA selection
3
1
ISO0
Output Idle state 0
8
1
ISO0N
Output Idle state 0
9
1
ISO1
Output Idle state 1
10
1
MMC
Master mode selection
4
3
DMACFG
DMACFG
DMA configuration register
0x48
32
read-write
n
0x0
0x0
DMATA
DMA base address
0
5
DMATC
DMA burst length
8
5
DMAINTEN
DMAINTEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BRKIE
Break interrupt enable
7
1
CH0DEN
Capture/Compare 0 DMA request enable
9
1
CH0IE
Capture/Compare 1 interrupt enable
1
1
CH1DEN
Capture/Compare 1 DMA request enable
10
1
CH1IE
Capture/Compare 2 interrupt enable
2
1
CMTDEN
Commutation DMA request enable
13
1
CMTIE
COM interrupt enable
5
1
TRGDEN
Trigger DMA request enable
14
1
TRGIE
Trigger interrupt enable
6
1
UPDEN
Update DMA request enable
8
1
UPIE
Update interrupt enable
0
1
DMATB
DMATB
DMA transfer buffer register
0x4C
32
read-write
n
0x0
0x0
DMATB
DMA register for burst accesses
0
16
INTF
INTF
interrupt flag register
0x10
32
read-write
n
0x0
0x0
BRKIF
Break interrupt flag
7
1
CH0IF
Capture/compare 0 interrupt flag
1
1
CH0OF
Capture/Compare 0 overcapture flag
9
1
CH1IF
Capture/Compare 1 interrupt flag
2
1
CH1OF
Capture/compare 1 overcapture flag
10
1
CMTIF
COM interrupt flag
5
1
TRGIF
Trigger interrupt flag
6
1
UPIF
Update interrupt flag
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCFG
SMCFG
slave mode configuration register
0x8
32
read-write
n
0x0
0x0
MSM
Master/Slave mode
7
1
SMC
Slave mode selection
0
3
TRGS
Trigger selection
4
3
SWEVG
SWEVG
event generation register
0x14
32
write-only
n
0x0
0x0
BRKG
Break generation
7
1
CH0G
Capture/compare 0 generation
1
1
CH1G
Capture/compare 1 generation
2
1
CMTG
Capture/Compare control update generation
5
1
TRGG
Trigger generation
6
1
UPG
Update generation
0
1
TIMER15
General-purpose-timers
TIMER
0x0
0x0
0x400
registers
n
TIMER15
21
CAR
CAR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
CARL
Auto-reload value
0
16
CCHP
CCHP
break and dead-time register
0x44
32
read-write
n
0x0
0x0
BRKEN
Break enable
12
1
BRKP
Break polarity
13
1
DTCFG
Dead-time generator setup
0
8
IOS
Off-state selection for Idle mode
10
1
OAEN
Automatic output enable
14
1
POEN
Main output enable
15
1
PROT
complementary register protect control
8
2
ROS
Off-state selection for Run mode
11
1
CFG
CFG
configuration register
0xFC
32
read-write
n
0x0
0x0
CHVSEL
Write CHxVAL register selection
1
1
OUTSEL
The output value selection
0
1
CH0CV
CH0CV
capture/compare register 0
0x34
32
read-write
n
0x0
0x0
CH0VAL
Capture/Compare 0 value
0
16
CHCTL0_Input
CHCTL0_Input
capture/compare mode register 0 (input mode)
CHCTL0_Output
0x18
32
read-write
n
0x0
0x0
CH0CAPFLT
Input capture 0 filter
4
4
CH0CAPPSC
Input capture 0 prescaler
2
2
CH0MS
Capture/Compare 0 selection
0
2
CHCTL0_Output
CHCTL0_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CH0COMCTL
Output Compare 0 mode
4
3
CH0COMFEN
Output Compare 0 fast enable
2
1
CH0COMSEN
Output Compare 0 preload enable
3
1
CH0MS
Capture/Compare 0 selection
0
2
CHCTL2
CHCTL2
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CH0EN
Capture/Compare 0 output enable
0
1
CH0NEN
Capture/Compare 0 complementary output enable
2
1
CH0NP
Capture/Compare 0 output Polarity
3
1
CH0P
Capture/Compare 0 output Polarity
1
1
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CREP
CREP
repetition counter register
0x30
32
read-write
n
0x0
0x0
CREP
Repetition counter value
0
8
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
ARSE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKDIV
Clock division
8
2
SPM
One-pulse mode
3
1
UPDIS
Update disable
1
1
UPS
Update request source
2
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
CCSE
Capture/compare preloaded control
0
1
CCUC
Capture/compare control update selection
2
1
DMAS
Capture/compare DMA selection
3
1
ISO0
Output Idle state 0
8
1
ISO0N
Output Idle state 0
9
1
DMACFG
DMACFG
DMA configuration register
0x48
32
read-write
n
0x0
0x0
DMATA
DMA transfer access start address
0
5
DMATC
DMA transfer count
8
5
DMAINTEN
DMAINTEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BRKIE
Break interrupt enable
7
1
CH0DEN
Capture/Compare 0 DMA request enable
9
1
CH0IE
Capture/Compare 0 interrupt enable
1
1
CMTIE
COM interrupt enable
5
1
UPDEN
Update DMA request enable
8
1
UPIE
Update interrupt enable
0
1
DMATB
DMATB
DMA transfer buffer register
0x4C
32
read-write
n
0x0
0x0
DMATB
DMA register for burst accesses
0
16
INTF
INTF
interrupt flag register
0x10
32
read-write
n
0x0
0x0
BRKIF
Break interrupt flag
7
1
CH0IF
Capture/compare 0 interrupt flag
1
1
CH0OF
Capture/Compare 0 overcapture flag
9
1
CMTIF
COM interrupt flag
5
1
UPIF
Update interrupt flag
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SWEVG
SWEVG
event generation register
0x14
32
write-only
n
0x0
0x0
BRKG
Break generation
7
1
CH0G
Capture/compare 0 generation
1
1
CMTG
Capture/Compare control update generation
5
1
UPG
Update generation
0
1
TIMER16
General-purpose-timers
TIMER
0x0
0x0
0x400
registers
n
TIMER16
22
CAR
CAR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
CARL
Auto-reload value
0
16
CCHP
CCHP
break and dead-time register
0x44
32
read-write
n
0x0
0x0
BRKEN
Break enable
12
1
BRKP
Break polarity
13
1
DTCFG
Dead-time generator setup
0
8
IOS
Off-state selection for Idle mode
10
1
OAEN
Automatic output enable
14
1
POEN
Main output enable
15
1
PROT
complementary register protect control
8
2
ROS
Off-state selection for Run mode
11
1
CFG
CFG
configuration register
0xFC
32
read-write
n
0x0
0x0
CHVSEL
Write CHxVAL register selection
1
1
OUTSEL
The output value selection
0
1
CH0CV
CH0CV
capture/compare register 0
0x34
32
read-write
n
0x0
0x0
CH0VAL
Capture/Compare 0 value
0
16
CHCTL0_Input
CHCTL0_Input
capture/compare mode register 0 (input mode)
CHCTL0_Output
0x18
32
read-write
n
0x0
0x0
CH0CAPFLT
Input capture 0 filter
4
4
CH0CAPPSC
Input capture 0 prescaler
2
2
CH0MS
Capture/Compare 0 selection
0
2
CHCTL0_Output
CHCTL0_Output
capture/compare mode register (output mode)
0x18
32
read-write
n
0x0
0x0
CH0COMCTL
Output Compare 0 mode
4
3
CH0COMFEN
Output Compare 0 fast enable
2
1
CH0COMSEN
Output Compare 0 preload enable
3
1
CH0MS
Capture/Compare 0 selection
0
2
CHCTL2
CHCTL2
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CH0EN
Capture/Compare 0 output enable
0
1
CH0NEN
Capture/Compare 0 complementary output enable
2
1
CH0NP
Capture/Compare 0 output Polarity
3
1
CH0P
Capture/Compare 0 output Polarity
1
1
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
16
CREP
CREP
repetition counter register
0x30
32
read-write
n
0x0
0x0
CREP
Repetition counter value
0
8
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
ARSE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
CKDIV
Clock division
8
2
SPM
One-pulse mode
3
1
UPDIS
Update disable
1
1
UPS
Update request source
2
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
CCSE
Capture/compare preloaded control
0
1
CCUC
Capture/compare control update selection
2
1
DMAS
Capture/compare DMA selection
3
1
ISO0
Output Idle state 0
8
1
ISO0N
Output Idle state 0
9
1
DMACFG
DMACFG
DMA configuration register
0x48
32
read-write
n
0x0
0x0
DMATA
DMA transfer access start address
0
5
DMATC
DMA transfer count
8
5
DMAINTEN
DMAINTEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
BRKIE
Break interrupt enable
7
1
CH0DEN
Capture/Compare 0 DMA request enable
9
1
CH0IE
Capture/Compare 0 interrupt enable
1
1
CMTIE
COM interrupt enable
5
1
UPDEN
Update DMA request enable
8
1
UPIE
Update interrupt enable
0
1
DMATB
DMATB
DMA transfer buffer register
0x4C
32
read-write
n
0x0
0x0
DMATB
DMA register for burst accesses
0
16
INTF
INTF
interrupt flag register
0x10
32
read-write
n
0x0
0x0
BRKIF
Break interrupt flag
7
1
CH0IF
Capture/compare 0 interrupt flag
1
1
CH0OF
Capture/Compare 0 overcapture flag
9
1
CMTIF
COM interrupt flag
5
1
UPIF
Update interrupt flag
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SWEVG
SWEVG
event generation register
0x14
32
write-only
n
0x0
0x0
BRKG
Break generation
7
1
CH0G
Capture/compare 0 generation
1
1
CMTG
Capture/Compare control update generation
5
1
UPG
Update generation
0
1
TIMER2
General-purpose-timers
TIMER
0x0
0x0
0x400
registers
n
TIMER2
16
CAR
CAR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
CARL
Low Auto-reload value
0
32
CFG
CFG
Configuration
0xFC
32
read-write
n
0x0
0x0
CHVSEL
Write CHxVAL register selection
1
1
CH0CV
CH0CV
capture/compare register 1
0x34
32
read-write
n
0x0
0x0
CH0VAL
Low Capture/Compare 1 value
0
32
CH1CV
CH1CV
capture/compare register 2
0x38
32
read-write
n
0x0
0x0
CH1VAL
Low Capture/Compare 2 value
0
32
CH2CV
CH2CV
capture/compare register 2
0x3C
32
read-write
n
0x0
0x0
CH2VAL
High Capture/Compare value (TIM2 only)
0
32
CH3CV
CH3CV
capture/compare register 3
0x40
32
read-write
n
0x0
0x0
CH3VAL
High Capture/Compare value (TIM2 only)
0
32
CHCTL0_Input
CHCTL0_Input
capture/compare mode register 0 (input mode)
CHCTL0_Output
0x18
32
read-write
n
0x0
0x0
CH0CAPFLT
Input capture 0 filter
4
4
CH0CAPPSC
Input capture 0 prescaler
2
2
CH0MS
Capture/Compare 0 selection
0
2
CH1CAPFLT
Input capture 1 filter
12
4
CH1CAPPSC
Input capture 1 prescaler
10
2
CH1MS
Capture/compare 1 selection
8
2
CHCTL0_Output
CHCTL0_Output
capture/compare mode register 0 (output mode)
0x18
32
read-write
n
0x0
0x0
CH0COMCEN
Output compare 0 clear enable
7
1
CH0COMCTL
Output compare 0 mode
4
3
CH0COMFEN
Output compare 0 fast enable
2
1
CH0COMSEN
Output compare 0 preload enable
3
1
CH0MS
Capture/Compare 0 selection
0
2
CH1COMCEN
Output compare 1 clear enable
15
1
CH1COMCTL
Output compare 1 mode
12
3
CH1COMFEN
Output compare 1 fast enable
10
1
CH1COMSEN
Output compare 1 preload enable
11
1
CH1MS
Capture/Compare 1 selection
8
2
CHCTL1_Input
CHCTL1_Input
capture/compare mode register 1 (input mode)
CHCTL1_Output
0x1C
32
read-write
n
0x0
0x0
CH2CAPFLT
Input capture 2 filter
4
4
CH2CAPPSC
Input capture 2 prescaler
2
2
CH2MS
Capture/Compare 2 selection
0
2
CH3CAPFLT
Input capture 3 filter
12
4
CH3CAPPSC
Input capture 3 prescaler
10
2
CH3MS
Capture/Compare 3 selection
8
2
CHCTL1_Output
CHCTL1_Output
capture/compare mode register 1 (output mode)
0x1C
32
read-write
n
0x0
0x0
CH2COMCEN
Output compare 2 clear enable
7
1
CH2COMCTL
Output compare 2 mode
4
3
CH2COMFEN
Output compare 2 fast enable
2
1
CH2COMSEN
Output compare 2 preload enable
3
1
CH2MS
Capture/Compare 2 selection
0
2
CH3COMCEN
Output compare 3 clear enable
15
1
CH3COMCTL
Output compare 3 mode
12
3
CH3COMFEN
Output compare 3 fast enable
10
1
CH3COMSEN
Output compare 3 preload enable
11
1
CH3MS
Capture/Compare 3 selection
8
2
CHCTL2
CHCTL2
capture/compare enable register
0x20
32
read-write
n
0x0
0x0
CH0EN
Capture/Compare 0 output enable
0
1
CH0NP
Capture/Compare 0 output Polarity
3
1
CH0P
Capture/Compare 0 output Polarity
1
1
CH1EN
Capture/Compare 1 output enable
4
1
CH1NP
Capture/Compare 1 output Polarity
7
1
CH1P
Capture/Compare 1 output Polarity
5
1
CH2EN
Capture/Compare 2 output enable
8
1
CH2NP
Capture/Compare 2 output Polarity
11
1
CH2P
Capture/Compare 2 output Polarity
9
1
CH3EN
Capture/Compare 3 output enable
12
1
CH3NP
Capture/Compare 3 output Polarity
15
1
CH3P
Capture/Compare 3 output Polarity
13
1
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
counter value
0
32
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
ARSE
Auto-reload preload enable
7
1
CAM
Center-aligned mode selection
5
2
CEN
Counter enable
0
1
CKDIV
Clock division
8
2
DIR
Direction
4
1
SPM
One-pulse mode
3
1
UPDIS
Update disable
1
1
UPS
Update request source
2
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
DMAS
Capture/compare DMA selection
3
1
MMC
Master mode selection
4
3
TI0S
TI0 selection
7
1
DMACFG
DMACFG
DMA control register
0x48
32
read-write
n
0x0
0x0
DMATA
DMA base address
0
5
DMATC
DMA burst length
8
5
DMAINTEN
DMAINTEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
CH0DEN
Capture/Compare 1 DMA request enable
9
1
CH0IE
Capture/Compare 0 interrupt enable
1
1
CH1DEN
Capture/Compare 1 DMA request enable
10
1
CH1IE
Capture/Compare 1 interrupt enable
2
1
CH2DEN
Capture/Compare 2 DMA request enable
11
1
CH2IE
Capture/Compare 2 interrupt enable
3
1
CH3DEN
Capture/Compare 3 DMA request enable
12
1
CH3IE
Capture/Compare 3 interrupt enable
4
1
TRGDEN
Trigger DMA request enable
14
1
TRGIE
Trigger interrupt enable
6
1
UPDEN
Update DMA request enable
8
1
UPIE
Update interrupt enable
0
1
DMATB
DMATB
DMA address for full transfer
0x4C
32
read-write
n
0x0
0x0
DMATB
DMA register for burst accesses
0
16
INTF
INTF
interrupt flag register
0x10
32
read-write
n
0x0
0x0
CH0IF
Capture/compare 0 interrupt flag
1
1
CH0OF
Capture/Compare 0 overcapture flag
9
1
CH1IF
Capture/Compare 1 interrupt flag
2
1
CH1OF
Capture/compare 1 overcapture flag
10
1
CH2IF
Capture/Compare 2 interrupt flag
3
1
CH2OF
Capture/Compare 2 overcapture flag
11
1
CH3IF
Capture/Compare 3 interrupt flag
4
1
CH3OF
Capture/Compare 3 overcapture flag
12
1
TRGIF
Trigger interrupt flag
6
1
UPIF
Update interrupt flag
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SMCFG
SMCFG
slave mode control register
0x8
32
read-write
n
0x0
0x0
ETFC
External trigger filter
8
4
ETP
External trigger polarity
15
1
ETPSC
External trigger prescaler
12
2
MSM
Master/Slave mode
7
1
OCRC
OCREF clear source selection
3
1
SMC
Slave mode selection
0
3
SMC1
External clock enable
14
1
TRGS
Trigger selection
4
3
SWEVG
SWEVG
event generation register
0x14
32
write-only
n
0x0
0x0
CH0G
Capture/compare 0 generation
1
1
CH1G
Capture/compare 1 generation
2
1
CH2G
Capture/compare 2 generation
3
1
CH3G
Capture/compare 3 generation
4
1
TRGG
Trigger generation
6
1
UPG
Update generation
0
1
TIMER5
Basic-timers
TIMER
0x0
0x0
0x400
registers
n
TIMER5_DAC
17
CAR
CAR
auto-reload register
0x2C
32
read-write
n
0x0
0x0
CARL
Low Auto-reload value
0
16
CNT
CNT
counter
0x24
32
read-write
n
0x0
0x0
CNT
Low counter value
0
16
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
ARSE
Auto-reload preload enable
7
1
CEN
Counter enable
0
1
SPM
One-pulse mode
3
1
UPDIS
Update disable
1
1
UPS
Update request source
2
1
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
MMC
Master mode selection
4
3
DMAINTEN
DMAINTEN
DMA/Interrupt enable register
0xC
32
read-write
n
0x0
0x0
UPDEN
Update DMA request enable
8
1
UPIE
Update interrupt enable
0
1
INTF
INTF
status register
0x10
32
read-write
n
0x0
0x0
UPIF
Update interrupt flag
0
1
PSC
PSC
prescaler
0x28
32
read-write
n
0x0
0x0
PSC
Prescaler value
0
16
SWEVG
SWEVG
event generation register
0x14
32
write-only
n
0x0
0x0
UPG
Update generation
0
1
TSI
Touch sensing Interface
TSI
0x0
0x0
0x400
registers
n
TSI
8
ASW
ASW
I/O analog switch register
0x18
32
read-write
n
0x0
0x0
G0P0
G0P0 analog switch enable
0
1
G0P1
G0P1 analog switch enable
1
1
G0P2
G0P2 analog switch enable
2
1
G0P3
G0P3 analog switch enable
3
1
G1P0
G1P0 analog switch enable
4
1
G1P1
G1P1 analog switch enable
5
1
G1P2
G1P2 analog switch enable
6
1
G1P3
G1P3 analog switch enable
7
1
G2P0
G2P0 analog switch enable
8
1
G2P1
G2P1 analog switch enable
9
1
G2P2
G2P2 analog switch enable
10
1
G2P3
G2P3 analog switch enable
11
1
G3P0
G3P0 analog switch enable
12
1
G3P1
G3P1 analog switch enable
13
1
G3P2
G3P2 analog switch enable
14
1
G3P3
G3P3 analog switch enable
15
1
G4P0
G4P0 analog switch enable
16
1
G4P1
G4P1 analog switch enable
17
1
G4P2
G4P2 analog switch enable
18
1
G4P3
G4P3 analog switch enable
19
1
G5P0
G5P0 analog switch enable
20
1
G5P1
G5P1 analog switch enable
21
1
G5P2
G5P2 analog switch enable
22
1
G5P3
G5P3 analog switch enable
23
1
CHCFG
CHCFG
I/O channel configuration register
0x28
32
read-write
n
0x0
0x0
G0P0
G0P0 channel mode
0
1
G0P1
G0P1 channel mode
1
1
G0P2
G0P2 channel mode
2
1
G0P3
G0P3 channel mode
3
1
G1P0
G1P0 channel mode
4
1
G1P1
G1P1 channel mode
5
1
G1P2
G1P2 channel mode
6
1
G1P3
G1P3 channel mode
7
1
G2P0
G2P0 channel mode
8
1
G2P1
G2P1 channel mode
9
1
G2P2
G2P2 channel mode
10
1
G2P3
G2P3 channel mode
11
1
G3P0
G3P0 channel mode
12
1
G3P1
G3P1 channel mode
13
1
G3P2
G3P2 channel mode
14
1
G3P3
G3P3 channel mode
15
1
G4P0
G4P0 channel mode
16
1
G4P1
G4P1 channel mode
17
1
G4P2
G4P2 channel mode
18
1
G4P3
G4P3 channel mode
19
1
G5P0
G5P0 channel mode
20
1
G5P1
G5P1 channel mode
21
1
G5P2
G5P2 channel mode
22
1
G5P3
G5P3 channel mode
23
1
CTL0
CTL0
control register
0x0
32
read-write
n
0x0
0x0
CDT
Charge transfer pulse high
28
4
CTCDIV
pulse generator prescaler
12
3
CTDT
Charge transfer pulse low
24
4
ECDIV
Spread spectrum prescaler
15
1
ECDT
Spread spectrum deviation
17
7
ECEN
Spread spectrum enable
16
1
EGSEL
Edge selection
3
1
MCN
Max count value
5
3
PINMOD
I/O Default mode
4
1
TRGMOD
Trigger mode selection
2
1
TSIEN
Touch sensing controller enable
0
1
TSIS
Start a new acquisition
1
1
CTL1
CTL1
control register 1
0x300
32
write-only
n
0x0
0x0
CTCDIV_MSB
Charge Transfer clock division factor
24
1
ECDIV
Extend Charge clock division factor
28
2
G0CYCN
G0CYCN
I/O group x cycle number register
0x34
32
read-only
n
0x0
0x0
CYCN
Cycle number
0
14
G1CYCN
G1CYCN
I/O group x cycle number register
0x38
32
read-only
n
0x0
0x0
CYCN
Cycle number
0
14
G2CYCN
G2CYCN
I/O group x cycle number register
0x3C
32
read-only
n
0x0
0x0
CYCN
Cycle number
0
14
G3CYCN
G3CYCN
I/O group x cycle number register
0x40
32
read-only
n
0x0
0x0
CYCN
Cycle number
0
14
G4CYCN
G4CYCN
I/O group x cycle number register
0x44
32
read-only
n
0x0
0x0
CYCN
Cycle number
0
14
G5CYCN
G5CYCN
I/O group x cycle number register
0x48
32
read-only
n
0x0
0x0
CYCN
Cycle number
0
14
GCTL
GCTL
I/O group control register
0x30
32
read-write
n
0x0
0x0
GC0
Analog I/O group x status
16
1
read-only
GC1
Analog I/O group x status
17
1
read-only
GC2
Analog I/O group x status
18
1
read-only
GC3
Analog I/O group x status
19
1
read-only
GC4
Analog I/O group x status
20
1
read-only
GC5
Analog I/O group x status
21
1
read-only
GE0
Analog I/O group x enable
0
1
read-write
GE1
Analog I/O group x enable
1
1
read-write
GE2
Analog I/O group x enable
2
1
read-write
GE3
Analog I/O group x enable
3
1
read-write
GE4
Analog I/O group x enable
4
1
read-write
GE5
Analog I/O group x enable
5
1
read-write
INTC
INTC
interrupt flag clear register
0x8
32
read-write
n
0x0
0x0
CCTCF
Clear charge-transfer complete flag
0
1
CMNERR
Clear max cycle number error
1
1
INTEN
INTEN
interrupt enable register
0x4
32
read-write
n
0x0
0x0
CTCFIE
Charge-transfer complete flag Interrupt Enable
0
1
MNERRIE
Max Cycle Number Error Interrupt Enable
1
1
INTF
INTF
interrupt flag register
0xC
32
read-write
n
0x0
0x0
CTCF
End of acquisition flag
0
1
MNERR
Max count error flag
1
1
PHM
PHM
Pin hysteresis mode register
0x10
32
read-write
n
0x0
0x0
G0P0
G0P0 Schmitt trigger hysteresis mode
0
1
G0P1
G0P1 Schmitt trigger hysteresis mode
1
1
G0P2
G0P2 Schmitt trigger hysteresis mode
2
1
G0P3
G0P3 Schmitt trigger hysteresis mode
3
1
G1P0
G1P0 Schmitt trigger hysteresis mode
4
1
G1P1
G1P1 Schmitt trigger hysteresis mode
5
1
G1P2
G1P2 Schmitt trigger hysteresis mode
6
1
G1P3
G1P3 Schmitt trigger hysteresis mode
7
1
G2P0
G2P0 Schmitt trigger hysteresis mode
8
1
G2P1
G2P1 Schmitt trigger hysteresis mode
9
1
G2P2
G2P2 Schmitt trigger hysteresis mode
10
1
G2P3
G2P3 Schmitt trigger hysteresis mode
11
1
G3P0
G3P0 Schmitt trigger hysteresis mode
12
1
G3P1
G3P1 Schmitt trigger hysteresis mode
13
1
G3P2
G3P2 Schmitt trigger hysteresis mode
14
1
G3P3
G3P3 Schmitt trigger hysteresis mode
15
1
G4P0
G4P0 Schmitt trigger hysteresis mode
16
1
G4P1
G4P1 Schmitt trigger hysteresis mode
17
1
G4P2
G4P2 Schmitt trigger hysteresis mode
18
1
G4P3
G4P3 Schmitt trigger hysteresis mode
19
1
G5P0
G5P0 Schmitt trigger hysteresis mode
20
1
G5P1
G5P1 Schmitt trigger hysteresis mode
21
1
G5P2
G5P2 Schmitt trigger hysteresis mode
22
1
G5P3
G5P3 Schmitt trigger hysteresis mode
23
1
SAMPCFG
SAMPCFG
I/O sample configuration register
0x20
32
read-write
n
0x0
0x0
G0P0
G0P0 sampling mode
0
1
G0P1
G0P1 sampling mode
1
1
G0P2
G0P2 sampling mode
2
1
G0P3
G0P3 sampling mode
3
1
G1P0
G1P0 sampling mode
4
1
G1P1
G1P1 sampling mode
5
1
G1P2
G1P2 sampling mode
6
1
G1P3
G1P3 sampling mode
7
1
G2P0
G2P0 sampling mode
8
1
G2P1
G2P1 sampling mode
9
1
G2P2
G2P2 sampling mode
10
1
G2P3
G2P3 sampling mode
11
1
G3P0
G3P0 sampling mode
12
1
G3P1
G3P1 sampling mode
13
1
G3P2
G3P2 sampling mode
14
1
G3P3
G3P3 sampling mode
15
1
G4P0
G4P0 sampling mode
16
1
G4P1
G4P1 sampling mode
17
1
G4P2
G4P2 sampling mode
18
1
G4P3
G4P3 sampling mode
19
1
G5P0
G5P0 sampling mode
20
1
G5P1
G5P1 sampling mode
21
1
G5P2
G5P2 sampling mode
22
1
G5P3
G5P3 sampling mode
23
1
USART0
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART0
27
BAUD
BAUD
Baud rate register
0xC
32
read-write
n
0x0
0x0
BRR_FRA
integer of baud-rate divider
0
4
BRR_INT
integer of baud-rate divider
4
12
CMD
CMD
Request register
0x18
32
write-only
n
0x0
0x0
ABDCMD
Auto baud rate request
0
1
MMCMD
Mute mode request
2
1
RXFCMD
Receive data flush request
3
1
SBKCMD
Send break request
1
1
TXFCMD
Transmit data flush request
4
1
CTL0
CTL0
Control register 0
0x0
32
read-write
n
0x0
0x0
AMIE
Character match interrupt enable
14
1
DEA
Driver Enable assertion time
21
5
DED
Driver Enable deassertion time
16
5
EBIE
End of Block interrupt enable
27
1
IDLEIE
IDLE interrupt enable
4
1
MEN
Mute mode enable
13
1
OVSMOD
Oversampling mode
15
1
PCEN
Parity control enable
10
1
PERRIE
PE interrupt enable
8
1
PM
Parity selection
9
1
RBNEIE
RXNE interrupt enable
5
1
REN
Receiver enable
2
1
RTIE
Receiver timeout interrupt enable
26
1
TBEIE
interrupt enable
7
1
TCIE
Transmission complete interrupt enable
6
1
TEN
Transmitter enable
3
1
UEN
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WL
Word length
12
1
WM
Receiver wakeup method
11
1
CTL1
CTL1
Control register 1
0x4
32
read-write
n
0x0
0x0
ABDEN
Auto baud rate enable
20
1
ABDM
Auto baud rate mode
21
2
ADDM
7-bit Address Detection/4-bit Address Detection
4
1
ADDR
Address of the USART node
24
8
CKEN
Clock enable
11
1
CLEN
Last bit clock pulse
8
1
CPH
Clock phase
9
1
CPL
Clock polarity
10
1
DINV
Binary data inversion
18
1
LBDIE
LIN break detection interrupt enable
6
1
LBLEN
LIN break detection length
5
1
LMEN
LIN mode enable
14
1
MSBF
Most significant bit first
19
1
RINV
RX pin active level inversion
16
1
RTEN
Receiver timeout enable
23
1
STB
STOP bits
12
2
STRP
Swap TX/RX pins
15
1
TINV
TX pin active level inversion
17
1
CTL2
CTL2
Control register 2
0x8
32
read-write
n
0x0
0x0
CTSEN
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DENR
DMA enable receiver
6
1
DENT
DMA enable transmitter
7
1
DEP
Driver enable polarity selection
15
1
ERRIE
Error interrupt enable
0
1
HDEN
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NKEN
Smartcard NACK enable
4
1
OSB
One sample bit method enable
11
1
OVRD
Overrun Disable
12
1
RTSEN
RTS enable
8
1
SCEN
Smartcard mode enable
5
1
SCRTNUM
Smartcard auto-retry count
17
3
WUIE
Wakeup from Stop mode interrupt enable
22
1
WUM
Wakeup from Stop mode interrupt flag selection
20
2
GP
GP
Guard time and prescaler register
0x10
32
read-write
n
0x0
0x0
GUAT
Guard time value
8
8
PSC
Prescaler value
0
8
INTC
INTC
Interrupt flag clear register
0x20
32
write-only
n
0x0
0x0
AMC
Character match clear flag
17
1
CTSC
CTS clear flag
9
1
EBC
End of timeout clear flag
12
1
FEC
Framing error clear flag
1
1
IDLEC
Idle line detected clear flag
4
1
LBDC
LIN break detection clear flag
8
1
NEC
Noise detected clear flag
2
1
OREC
Overrun error clear flag
3
1
PEC
Parity error clear flag
0
1
RTC
Receiver timeout clear flag
11
1
TCC
Transmission complete clear flag
6
1
WUC
Wakeup from Stop mode clear flag
20
1
RDATA
RDATA
Receive data register
0x24
32
read-only
n
0x0
0x0
RDATA
Receive data value
0
9
RFCS
RFCS
USART receive FIFO control and status register
0xD0
32
read-write
n
0x0
0x0
ELNACK
Early NKEN when smartcard mode is selected
0
1
RFCNT
Receive FIFO count number
12
3
RFE
Receive FIFO empty flag
10
1
RFEN
Receive FIFO enable
8
1
RFF
Receive FIFO full flag
11
1
RFFIE
Receive FIFO full interrupt enable
9
1
RFFINT
Receive FIFO full interrupt flag
15
1
RT
RT
Receiver timeout register
0x14
32
read-write
n
0x0
0x0
BL
Block Length
24
8
RT
Receiver timeout value
0
24
STAT
STAT
Interrupt and status register
0x1C
32
read-only
n
0x0
0x0
ABDE
Auto baud rate error
14
1
ABDF
Auto baud rate flag
15
1
AMF
character match flag
17
1
BSY
Busy flag
16
1
CTS
CTS flag
10
1
CTSF
CTS interrupt flag
9
1
EBF
End of block flag
12
1
FERR
Framing error
1
1
IDLEF
Idle line detected
4
1
LBDF
LIN break detection flag
8
1
NERR
Noise detected flag
2
1
ORERR
Overrun error
3
1
PERR
Parity error
0
1
RBNE
Read data register not empty
5
1
REA
Receive enable acknowledge flag
22
1
RTF
Receiver timeout
11
1
RWU
Receiver wakeup from Mute mode
19
1
SBF
Send break flag
18
1
TBE
Transmit data register empty
7
1
TC
Transmission complete
6
1
TEA
Transmit enable acknowledge flag
21
1
WUF
Wakeup from Stop mode flag
20
1
TDATA
TDATA
Transmit data register
0x28
32
read-write
n
0x0
0x0
TDATA
Transmit data value
0
9
USART1
Universal synchronous asynchronous receiver transmitter
USART
0x0
0x0
0x400
registers
n
USART1
28
BAUD
BAUD
Baud rate register
0xC
32
read-write
n
0x0
0x0
BRR_FRA
integer of baud-rate divider
0
4
BRR_INT
integer of baud-rate divider
4
12
CMD
CMD
Request register
0x18
32
write-only
n
0x0
0x0
ABDCMD
Auto baud rate request
0
1
MMCMD
Mute mode request
2
1
RXFCMD
Receive data flush request
3
1
SBKCMD
Send break request
1
1
TXFCMD
Transmit data flush request
4
1
CTL0
CTL0
Control register 0
0x0
32
read-write
n
0x0
0x0
AMIE
Character match interrupt enable
14
1
DEA
Driver Enable assertion time
21
5
DED
Driver Enable deassertion time
16
5
EBIE
End of Block interrupt enable
27
1
IDLEIE
IDLE interrupt enable
4
1
MEN
Mute mode enable
13
1
OVSMOD
Oversampling mode
15
1
PCEN
Parity control enable
10
1
PERRIE
PE interrupt enable
8
1
PM
Parity selection
9
1
RBNEIE
RXNE interrupt enable
5
1
REN
Receiver enable
2
1
RTIE
Receiver timeout interrupt enable
26
1
TBEIE
interrupt enable
7
1
TCIE
Transmission complete interrupt enable
6
1
TEN
Transmitter enable
3
1
UEN
USART enable
0
1
UESM
USART enable in Stop mode
1
1
WL
Word length
12
1
WM
Receiver wakeup method
11
1
CTL1
CTL1
Control register 1
0x4
32
read-write
n
0x0
0x0
ABDEN
Auto baud rate enable
20
1
ABDM
Auto baud rate mode
21
2
ADDM
7-bit Address Detection/4-bit Address Detection
4
1
ADDR
Address of the USART node
24
8
CKEN
Clock enable
11
1
CLEN
Last bit clock pulse
8
1
CPH
Clock phase
9
1
CPL
Clock polarity
10
1
DINV
Binary data inversion
18
1
LBDIE
LIN break detection interrupt enable
6
1
LBLEN
LIN break detection length
5
1
LMEN
LIN mode enable
14
1
MSBF
Most significant bit first
19
1
RINV
RX pin active level inversion
16
1
RTEN
Receiver timeout enable
23
1
STB
STOP bits
12
2
STRP
Swap TX/RX pins
15
1
TINV
TX pin active level inversion
17
1
CTL2
CTL2
Control register 2
0x8
32
read-write
n
0x0
0x0
CTSEN
CTS enable
9
1
CTSIE
CTS interrupt enable
10
1
DDRE
DMA Disable on Reception Error
13
1
DEM
Driver enable mode
14
1
DENR
DMA enable receiver
6
1
DENT
DMA enable transmitter
7
1
DEP
Driver enable polarity selection
15
1
ERRIE
Error interrupt enable
0
1
HDEN
Half-duplex selection
3
1
IREN
IrDA mode enable
1
1
IRLP
IrDA low-power
2
1
NKEN
Smartcard NACK enable
4
1
OSB
One sample bit method enable
11
1
OVRD
Overrun Disable
12
1
RTSEN
RTS enable
8
1
SCEN
Smartcard mode enable
5
1
SCRTNUM
Smartcard auto-retry count
17
3
WUIE
Wakeup from Stop mode interrupt enable
22
1
WUM
Wakeup from Stop mode interrupt flag selection
20
2
GP
GP
Guard time and prescaler register
0x10
32
read-write
n
0x0
0x0
GUAT
Guard time value
8
8
PSC
Prescaler value
0
8
INTC
INTC
Interrupt flag clear register
0x20
32
write-only
n
0x0
0x0
AMC
Character match clear flag
17
1
CTSC
CTS clear flag
9
1
EBC
End of timeout clear flag
12
1
FEC
Framing error clear flag
1
1
IDLEC
Idle line detected clear flag
4
1
LBDC
LIN break detection clear flag
8
1
NEC
Noise detected clear flag
2
1
OREC
Overrun error clear flag
3
1
PEC
Parity error clear flag
0
1
RTC
Receiver timeout clear flag
11
1
TCC
Transmission complete clear flag
6
1
WUC
Wakeup from Stop mode clear flag
20
1
RDATA
RDATA
Receive data register
0x24
32
read-only
n
0x0
0x0
RDATA
Receive data value
0
9
RFCS
RFCS
USART receive FIFO control and status register
0xD0
32
read-write
n
0x0
0x0
ELNACK
Early NKEN when smartcard mode is selected
0
1
RFCNT
Receive FIFO count number
12
3
RFE
Receive FIFO empty flag
10
1
RFEN
Receive FIFO enable
8
1
RFF
Receive FIFO full flag
11
1
RFFIE
Receive FIFO full interrupt enable
9
1
RFFINT
Receive FIFO full interrupt flag
15
1
RT
RT
Receiver timeout register
0x14
32
read-write
n
0x0
0x0
BL
Block Length
24
8
RT
Receiver timeout value
0
24
STAT
STAT
Interrupt and status register
0x1C
32
read-only
n
0x0
0x0
ABDE
Auto baud rate error
14
1
ABDF
Auto baud rate flag
15
1
AMF
character match flag
17
1
BSY
Busy flag
16
1
CTS
CTS flag
10
1
CTSF
CTS interrupt flag
9
1
EBF
End of block flag
12
1
FERR
Framing error
1
1
IDLEF
Idle line detected
4
1
LBDF
LIN break detection flag
8
1
NERR
Noise detected flag
2
1
ORERR
Overrun error
3
1
PERR
Parity error
0
1
RBNE
Read data register not empty
5
1
REA
Receive enable acknowledge flag
22
1
RTF
Receiver timeout
11
1
RWU
Receiver wakeup from Mute mode
19
1
SBF
Send break flag
18
1
TBE
Transmit data register empty
7
1
TC
Transmission complete
6
1
TEA
Transmit enable acknowledge flag
21
1
WUF
Wakeup from Stop mode flag
20
1
TDATA
TDATA
Transmit data register
0x28
32
read-write
n
0x0
0x0
TDATA
Transmit data value
0
9
USBFS_DEVICE
USB on the go full speed device
USBFS
0x0
0x0
0x400
registers
n
DAEPINT
DAEPINT
device all endpoints interrupt register (DAEPINT)
0x18
32
read-only
n
0x0
0x0
IEPITB
Device all IN endpoint interrupt bits
0
4
OEPITB
Device all OUT endpoint interrupt bits
16
4
DAEPINTEN
DAEPINTEN
Device all endpoints interrupt enable register (DAEPINTEN)
0x1C
32
read-write
n
0x0
0x0
IEPIE
IN EP interrupt interrupt enable bits
0
4
OEPIE
OUT endpoint interrupt enable bits
16
4
DCFG
DCFG
device configuration register (DCFG)
0x0
32
read-write
n
0x0
0x0
DAR
Device address
4
7
DS
Device speed
0
2
EOPFT
end of periodic frame time
11
2
NZLSOH
Non-zero-length status OUT handshake
2
1
DCTL
DCTL
device control register (DCTL)
0x4
32
read-write
n
0x0
0x0
CGINAK
Clear global IN NAK
8
1
write-only
CGONAK
Clear global OUT NAK
10
1
write-only
GINS
Global IN NAK status
2
1
read-only
GONS
Global OUT NAK status
3
1
read-only
POIF
Power-on initialization flag
11
1
read-write
RWKUP
Remote wakeup
0
1
read-write
SD
Soft disconnect
1
1
read-write
SGINAK
Set global IN NAK
7
1
write-only
SGONAK
Set global OUT NAK
9
1
write-only
DIEP0CTL
DIEP0CTL
device IN endpoint 0 control register (DIEP0CTL)
0x100
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EPACT
endpoint active
15
1
read-only
EPD
Endpoint disable
30
1
read-write
EPEN
Endpoint enable
31
1
read-write
EPTYPE
Endpoint type
18
2
read-only
MPL
Maximum packet length
0
2
read-write
NAKS
NAK status
17
1
read-only
SNAK
Set NAK
27
1
write-only
STALL
STALL handshake
21
1
read-write
TXFNUM
TxFIFO number
22
4
read-write
DIEP0INTF
DIEP0INTF
device endpoint-0 interrupt register
0x108
32
read-write
n
0x0
0x0
CITO
Control in timeout interrupt
3
1
read-write
EPDIS
Endpoint finished
1
1
read-write
EPTXFUD
Endpoint Tx FIFO underrun
4
1
read-write
IEPNE
IN endpoint NAK effective
6
1
read-write
TF
Transfer finished
0
1
read-write
TXFE
Transmit FIFO empty
7
1
read-only
DIEP0LEN
DIEP0LEN
device IN endpoint-0 transfer length register
0x110
32
read-write
n
0x0
0x0
PCNT
Packet count
19
2
TLEN
Transfer length
0
7
DIEP0TFSTAT
DIEP0TFSTAT
device IN endpoint 0 transmit FIFO status register
0x118
32
read-only
n
0x0
0x0
IEPTFS
IN endpoint TxFIFO space remaining
0
16
DIEP1CTL
DIEP1CTL
device in endpoint-1 control register
0x120
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EOFRM_DPID
EOFRM/DPID
16
1
read-only
EPACT
Endpoint active
15
1
read-write
EPD
Endpoint disable
30
1
read-write
EPEN
Endpoint enable
31
1
read-write
EPTYPE
Endpoint type
18
2
read-write
MPL
maximum packet length
0
11
read-write
NAKS
NAK status
17
1
read-only
SD0PID_SEVENFRM
SD0PID/SEVNFRM
28
1
write-only
SD1PID_SODDFRM
Set DATA1 PID/Set odd frame
29
1
write-only
SNAK
Set NAK
27
1
write-only
STALL
STALL handshake
21
1
read-write
TXFNUM
Tx FIFO number
22
4
read-write
DIEP1INTF
DIEP1INTF
device endpoint-1 interrupt register
0x128
32
read-write
n
0x0
0x0
CITO
Control in timeout interrupt
3
1
read-write
EPDIS
Endpoint finished
1
1
read-write
EPTXFUD
Endpoint Tx FIFO underrun
4
1
read-write
IEPNE
IN endpoint NAK effective
6
1
read-write
TF
Transfer finished
0
1
read-write
TXFE
Transmit FIFO empty
7
1
read-only
DIEP1LEN
DIEP1LEN
device IN endpoint-1 transfer length register
0x130
32
read-write
n
0x0
0x0
MCPF
Multi packet count per frame
29
2
PCNT
Packet count
19
10
TLEN
Transfer length
0
19
DIEP1TFSTAT
DIEP1TFSTAT
device IN endpoint 1 transmit FIFO status register
0x138
32
read-only
n
0x0
0x0
IEPTFS
IN endpoint TxFIFO space remaining
0
16
DIEP2CTL
DIEP2CTL
device endpoint-2 control register
0x140
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EOFRM_DPID
EOFRM/DPID
16
1
read-only
EPACT
Endpoint active
15
1
read-write
EPD
Endpoint disable
30
1
read-write
EPEN
Endpoint enable
31
1
read-write
EPTYPE
Endpoint type
18
2
read-write
MPL
maximum packet length
0
11
read-write
NAKS
NAK status
17
1
read-only
SD0PID_SEVENFRM
SD0PID/SEVNFRM
28
1
write-only
SD1PID_SODDFRM
Set DATA1 PID/Set odd frame
29
1
write-only
SNAK
Set NAK
27
1
write-only
STALL
STALL handshake
21
1
read-write
TXFNUM
Tx FIFO number
22
4
read-write
DIEP2INTF
DIEP2INTF
device endpoint-2 interrupt register
0x148
32
read-write
n
0x0
0x0
CITO
Control in timeout interrupt
3
1
read-write
EPDIS
Endpoint finished
1
1
read-write
EPTXFUD
Endpoint Tx FIFO underrun
4
1
read-write
IEPNE
IN endpoint NAK effective
6
1
read-write
TF
Transfer finished
0
1
read-write
TXFE
Transmit FIFO empty
7
1
read-only
DIEP2LEN
DIEP2LEN
device IN endpoint-2 transfer length register
0x150
32
read-write
n
0x0
0x0
MCPF
Multi packet count per frame
29
2
PCNT
Packet count
19
10
TLEN
Transfer length
0
19
DIEP2TFSTAT
DIEP2TFSTAT
device IN endpoint 2 transmit FIFO status register
0x158
32
read-only
n
0x0
0x0
IEPTFS
IN endpoint TxFIFO space remaining
0
16
DIEP3CTL
DIEP3CTL
device endpoint-3 control register
0x160
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EOFRM_DPID
EOFRM/DPID
16
1
read-only
EPACT
Endpoint active
15
1
read-write
EPD
Endpoint disable
30
1
read-write
EPEN
Endpoint enable
31
1
read-write
EPTYPE
Endpoint type
18
2
read-write
MPL
maximum packet length
0
11
read-write
NAKS
NAK status
17
1
read-only
SD0PID_SEVENFRM
SD0PID/SEVNFRM
28
1
write-only
SD1PID_SODDFRM
Set DATA1 PID/Set odd frame
29
1
write-only
SNAK
Set NAK
27
1
write-only
STALL
STALL handshake
21
1
read-write
TXFNUM
Tx FIFO number
22
4
read-write
DIEP3INTF
DIEP3INTF
device endpoint-3 interrupt register
0x168
32
read-write
n
0x0
0x0
CITO
Control in timeout interrupt
3
1
read-write
EPDIS
Endpoint finished
1
1
read-write
EPTXFUD
Endpoint Tx FIFO underrun
4
1
read-write
IEPNE
IN endpoint NAK effective
6
1
read-write
TF
Transfer finished
0
1
read-write
TXFE
Transmit FIFO empty
7
1
read-only
DIEP3LEN
DIEP3LEN
device IN endpoint-3 transfer length register
0x170
32
read-write
n
0x0
0x0
MCPF
Multi packet count per frame
29
2
PCNT
Packet count
19
10
TLEN
Transfer length
0
19
DIEP3TFSTAT
DIEP3TFSTAT
device IN endpoint 3 transmit FIFO status register
0x178
32
read-only
n
0x0
0x0
IEPTFS
IN endpoint TxFIFO space remaining
0
16
DIEPFEINTEN
DIEPFEINTEN
device IN endpoint FIFO empty interrupt enable register
0x34
32
read-write
n
0x0
0x0
IEPTXFEIE
IN EP Tx FIFO empty interrupt enable bits
0
4
DIEPINTEN
DIEPINTEN
device IN endpoint common interrupt mask register (DIEPINTEN)
0x10
32
read-write
n
0x0
0x0
CITOEN
Control IN timeout condition interrupt enable (Non-isochronous endpoints)
3
1
EPDISEN
Endpoint disabled interrupt enable
1
1
EPTXFUDEN
Endpoint Tx FIFO underrun interrupt enable bit
4
1
IEPNEEN
IN endpoint NAK effective interrupt enable
6
1
TFEN
Transfer finished interrupt enable
0
1
DOEP0CTL
DOEP0CTL
device endpoint-0 control register
0x300
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EPACT
Endpoint active
15
1
read-only
EPD
Endpoint disable
30
1
read-only
EPEN
Endpoint enable
31
1
write-only
EPTYPE
Endpoint type
18
2
read-only
MPL
Maximum packet length
0
2
read-only
NAKS
NAK status
17
1
read-only
SNAK
Set NAK
27
1
write-only
SNOOP
Snoop mode
20
1
read-write
STALL
STALL handshake
21
1
read-write
DOEP0INTF
DOEP0INTF
device out endpoint-0 interrupt flag register
0x308
32
read-write
n
0x0
0x0
BTBSTP
Back-to-back SETUP packets
6
1
EPDIS
Endpoint disabled
1
1
EPRXFOVR
Endpoint Rx FIFO overrun
4
1
STPF
Setup phase finished
3
1
TF
Transfer finished
0
1
DOEP0LEN
DOEP0LEN
device OUT endpoint-0 transfer length register
0x310
32
read-write
n
0x0
0x0
PCNT
Packet count
19
1
STPCNT
SETUP packet count
29
2
TLEN
Transfer length
0
7
DOEP1CTL
DOEP1CTL
device endpoint-1 control register
0x320
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EOFRM_DPID
EOFRM/DPID
16
1
read-only
EPACT
Endpoint active
15
1
read-write
EPD
Endpoint disable
30
1
read-write
EPEN
Endpoint enable
31
1
read-write
EPTYPE
Endpoint type
18
2
read-write
MPL
maximum packet length
0
11
read-write
NAKS
NAK status
17
1
read-only
SD0PID_SEVENFRM
SD0PID/SEVENFRM
28
1
write-only
SD1PID_SODDFRM
SD1PID/SODDFRM
29
1
write-only
SNAK
Set NAK
27
1
write-only
SNOOP
Snoop mode
20
1
read-write
STALL
STALL handshake
21
1
read-write
DOEP1INTF
DOEP1INTF
device out endpoint-1 interrupt flag register
0x328
32
read-write
n
0x0
0x0
BTBSTP
Back-to-back SETUP packets
6
1
EPDIS
Endpoint disabled
1
1
EPRXFOVR
Endpoint Rx FIFO overrun
4
1
STPF
Setup phase finished
3
1
TF
Transfer finished
0
1
DOEP1LEN
DOEP1LEN
device OUT endpoint-1 transfer length register
0x330
32
read-write
n
0x0
0x0
PCNT
Packet count
19
10
STPCNT_RXDPID
SETUP packet count/Received data PID
29
2
TLEN
Transfer length
0
19
DOEP2CTL
DOEP2CTL
device endpoint-2 control register
0x340
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EOFRM_DPID
EOFRM/DPID
16
1
read-only
EPACT
Endpoint active
15
1
read-write
EPD
Endpoint disable
30
1
read-write
EPEN
Endpoint enable
31
1
read-write
EPTYPE
Endpoint type
18
2
read-write
MPL
maximum packet length
0
11
read-write
NAKS
NAK status
17
1
read-only
SD0PID_SEVENFRM
SD0PID/SEVENFRM
28
1
write-only
SD1PID_SODDFRM
SD1PID/SODDFRM
29
1
write-only
SNAK
Set NAK
27
1
write-only
SNOOP
Snoop mode
20
1
read-write
STALL
STALL handshake
21
1
read-write
DOEP2INTF
DOEP2INTF
device out endpoint-2 interrupt flag register
0x348
32
read-write
n
0x0
0x0
BTBSTP
Back-to-back SETUP packets
6
1
EPDIS
Endpoint disabled
1
1
EPRXFOVR
Endpoint Rx FIFO overrun
4
1
STPF
Setup phase finished
3
1
TF
Transfer finished
0
1
DOEP2LEN
DOEP2LEN
device OUT endpoint-2 transfer length register
0x350
32
read-write
n
0x0
0x0
PCNT
Packet count
19
10
STPCNT_RXDPID
SETUP packet count/Received data PID
29
2
TLEN
Transfer length
0
19
DOEP3CTL
DOEP3CTL
device endpoint-3 control register
0x360
32
read-write
n
0x0
0x0
CNAK
Clear NAK
26
1
write-only
EOFRM_DPID
EOFRM/DPID
16
1
read-only
EPACT
Endpoint active
15
1
read-write
EPD
Endpoint disable
30
1
read-write
EPEN
Endpoint enable
31
1
read-write
EPTYPE
Endpoint type
18
2
read-write
MPL
maximum packet length
0
11
read-write
NAKS
NAK status
17
1
read-only
SD0PID_SEVENFRM
SD0PID/SEVENFRM
28
1
write-only
SD1PID_SODDFRM
SD1PID/SODDFRM
29
1
write-only
SNAK
Set NAK
27
1
write-only
SNOOP
Snoop mode
20
1
read-write
STALL
STALL handshake
21
1
read-write
DOEP3INTF
DOEP3INTF
device out endpoint-3 interrupt flag register
0x368
32
read-write
n
0x0
0x0
BTBSTP
Back-to-back SETUP packets
6
1
EPDIS
Endpoint disabled
1
1
EPRXFOVR
Endpoint Rx FIFO overrun
4
1
STPF
Setup phase finished
3
1
TF
Transfer finished
0
1
DOEP3LEN
DOEP3LEN
device OUT endpoint-3 transfer length register
0x370
32
read-write
n
0x0
0x0
PCNT
Packet count
19
10
STPCNT_RXDPID
SETUP packet count/Received data PID
29
2
TLEN
Transfer length
0
19
DOEPINTEN
DOEPINTEN
device OUT endpoint common interrupt enable register (DOEPINTEN)
0x14
32
read-write
n
0x0
0x0
BTBSTPEN
Back-to-back SETUP packets interrupt enable
6
1
EPDISEN
Endpoint disabled interrupt enable
1
1
EPRXFOVREN
Endpoint Rx FIFO overrun interrupt enable
4
1
STPFEN
SETUP phase finished interrupt enable
3
1
TFEN
Transfer finished interrupt enable
0
1
DSTAT
DSTAT
device status register (DSTAT)
0x8
32
read-only
n
0x0
0x0
ES
Enumerated speed
1
2
FNRSOF
Frame number of the received SOF
8
14
SPST
Suspend status
0
1
DVBUSDT
DVBUSDT
device VBUS discharge time register
0x28
32
read-write
n
0x0
0x0
DVBUSDT
Device VBUS discharge time
0
16
DVBUSPT
DVBUSPT
device VBUS pulsing time register
0x2C
32
read-write
n
0x0
0x0
DVBUSPT
Device VBUS pulsing time
0
12
USBFS_GLOBAL
USB full speed global registers
USBFS
0x0
0x0
0x400
registers
n
USBFS_WKUP
42
USBFS
67
CID
CID
core ID register
0x3C
32
read-write
n
0x0
0x0
CID
Core ID
0
32
DIEP0TFLEN
DIEP0TFLEN
Device IN endpoint 0 transmit FIFO length (Device mode)
HNPTFLEN
0x28
32
read-write
n
0x0
0x0
IEP0TXFD
in endpoint 0 Tx FIFO depth
16
16
IEP0TXRSAR
in endpoint 0 Tx RAM start address
0
16
DIEP1TFLEN
DIEP1TFLEN
device IN endpoint transmit FIFO size register (DIEP1TFLEN)
0x104
32
read-write
n
0x0
0x0
IEPTXFD
IN endpoint TxFIFO depth
16
16
IEPTXRSAR
IN endpoint FIFO transmit RAM start address
0
16
DIEP2TFLEN
DIEP2TFLEN
device IN endpoint transmit FIFO size register (DIEP2TFLEN)
0x108
32
read-write
n
0x0
0x0
IEPTXFD
IN endpoint TxFIFO depth
16
16
IEPTXRSAR
IN endpoint FIFO transmit RAM start address
0
16
DIEP3TFLEN
DIEP3TFLEN
device IN endpoint transmit FIFO size register (FS_DIEP3TXFLEN)
0x10C
32
read-write
n
0x0
0x0
IEPTXFD
IN endpoint TxFIFO depth
16
16
IEPTXRSAR
IN endpoint FIFO4 transmit RAM start address
0
16
GAHBCS
GAHBCS
Global AHB control and status register (USBFS_GAHBCS)
0x8
32
read-write
n
0x0
0x0
GINTEN
Global interrupt enable
0
1
PTXFTH
Periodic Tx FIFO threshold
8
1
TXFTH
Tx FIFO threshold
7
1
GCCFG
GCCFG
Global core configuration register (USBFS_GCCFG)
0x38
32
read-write
n
0x0
0x0
PWRON
Power on
16
1
SOFOEN
SOF output enable
20
1
VBUSACEN
The VBUS A-device Comparer enable
18
1
VBUSBCEN
The VBUS B-device Comparer enable
19
1
VBUSIG
VBUS ignored
21
1
GINTEN
GINTEN
Global interrupt enable register (USBFS_GINTEN)
0x18
32
read-write
n
0x0
0x0
DISCIE
Disconnect interrupt enable
29
1
read-write
ENUMFIE
Enumeration finish interrupt enable
13
1
read-write
EOPFIE
End of periodic frame interrupt enable
15
1
read-write
ESPIE
Early suspend interrupt enable
10
1
read-write
GNPINAKIE
Global non-periodic IN NAK effective interrupt enable
6
1
read-write
GONAKIE
Global OUT NAK effective interrupt enable
7
1
read-write
HCIE
Host channels interrupt enable
25
1
read-write
HPIE
Host port interrupt enable
24
1
read-only
IDPSCIE
ID pin status change interrupt enable
28
1
read-write
IEPIE
IN endpoints interrupt enable
18
1
read-write
ISOINCIE
isochronous IN transfer not complete interrupt enable
20
1
read-write
ISOOPDIE
Isochronous OUT packet dropped interrupt enable
14
1
read-write
MFIE
Mode fault interrupt enable
1
1
read-write
NPTXFEIE
Non-periodic TxFIFO empty interrupt enable
5
1
read-write
OEPIE
OUT endpoints interrupt enable
19
1
read-write
OTGIE
OTG interrupt enable
2
1
read-write
PTXFEIE
Periodic TxFIFO empty interrupt enable
26
1
read-write
PXNCIE_ISOONCIE
periodic transfer not compelete Interrupt enable(Host mode)/isochronous OUT transfer not complete interrupt enable(Device mode)
21
1
read-write
RSTIE
USB reset interrupt enable
12
1
read-write
RXFNEIE
Receive FIFO non-empty interrupt enable
4
1
read-write
SESIE
Session interrupt enable
30
1
read-write
SOFIE
Start of frame interrupt enable
3
1
read-write
SPIE
USB suspend interrupt enable
11
1
read-write
WKUPIE
Wakeup interrupt enable
31
1
read-write
GINTF
GINTF
Global interrupt flag register (USBFS_GINTF)
0x14
32
read-write
n
0x0
0x0
COPM
Current operation mode
0
1
read-only
DISCIF
Disconnect interrupt flag
29
1
read-write
ENUMF
Enumeration finished
13
1
read-write
EOPFIF
End of periodic frame interrupt flag
15
1
read-write
ESP
Early suspend
10
1
read-write
GNPINAK
Global Non-Periodic IN NAK effective
6
1
read-only
GONAK
Global OUT NAK effective
7
1
read-only
HCIF
Host channels interrupt flag
25
1
read-only
HPIF
Host port interrupt flag
24
1
read-only
IDPSC
ID pin status change
28
1
read-write
IEPIF
IN endpoint interrupt flag
18
1
read-only
ISOINCIF
Isochronous IN transfer Not Complete Interrupt Flag
20
1
read-write
ISOOPDIF
Isochronous OUT packet dropped interrupt
14
1
read-write
MFIF
Mode fault interrupt flag
1
1
read-write
NPTXFEIF
Non-periodic TxFIFO empty interrupt flag
5
1
read-only
OEPIF
OUT endpoint interrupt flag
19
1
read-only
OTGIF
OTG interrupt flag
2
1
read-only
PTXFEIF
Periodic TxFIFO empty interrupt flag
26
1
read-only
PXNCIF_ISOONCIF
periodic transfer not complete interrupt flag(Host mode)/isochronous OUT transfer not complete interrupt flag(Device mode)
21
1
read-write
RST
USB reset
12
1
read-write
RXFNEIF
RxFIFO non-empty interrupt flag
4
1
read-only
SESIF
Session interrupt flag
30
1
read-write
SOF
Start of frame
3
1
read-write
SP
USB suspend
11
1
read-write
WKUPIF
Wakeup interrupt flag
31
1
read-write
GOTGCS
GOTGCS
Global OTG control and status register (USBFS_GOTGCS)
0x0
32
read-write
n
0x0
0x0
ASV
A-session valid
18
1
read-only
BSV
B-session valid
19
1
read-only
DHNPEN
Device HNP enabled
11
1
read-write
DI
Debounce interval
17
1
read-only
HHNPEN
Host HNP enable
10
1
read-write
HNPREQ
HNP request
9
1
read-write
HNPS
Host success
8
1
read-only
IDPS
ID pin status
16
1
read-only
SRPREQ
SRP request
1
1
read-write
SRPS
SRP success
0
1
read-only
GOTGINTF
GOTGINTF
Global OTG interrupt flag register (USBFS_GOTGINTF)
0x4
32
read-write
n
0x0
0x0
ADTO
A-device timeout
18
1
DF
Debounce finish
19
1
HNPDET
Host negotiation request detected
17
1
HNPEND
HNP end
9
1
SESEND
Session end
2
1
SRPEND
Session request success status change
8
1
GRFLEN
GRFLEN
Global Receive FIFO size register (USBFS_GRFLEN)
0x24
32
read-write
n
0x0
0x0
RXFD
Rx FIFO depth
0
16
GRSTATP_Device
GRSTATP_Device
Global Receive status pop(Device mode)
0x20
32
read-only
n
0x0
0x0
BCOUNT
Byte count
4
11
DPID
Data PID
15
2
EPNUM
Endpoint number
0
4
RPCKST
Recieve packet status
17
4
GRSTATP_Host
GRSTATP_Host
Global Receive status pop(Host mode)
GRSTATP_Device
0x20
32
read-only
n
0x0
0x0
BCOUNT
Byte count
4
11
CNUM
Channel number
0
4
DPID
Data PID
15
2
RPCKST
Reivece packet status
17
4
GRSTATR_Device
GRSTATR_Device
Global Receive status read(Device mode)
0x1C
32
read-only
n
0x0
0x0
BCOUNT
Byte count
4
11
DPID
Data PID
15
2
EPNUM
Endpoint number
0
4
RPCKST
Recieve packet status
17
4
GRSTATR_Host
GRSTATR_Host
Global Receive status read(Host mode)
GRSTATR_Device
0x1C
32
read-only
n
0x0
0x0
BCOUNT
Byte count
4
11
CNUM
Channel number
0
4
DPID
Data PID
15
2
RPCKST
Reivece packet status
17
4
GRSTCTL
GRSTCTL
Global reset control register (USBFS_GRSTCTL)
0x10
32
read-write
n
0x0
0x0
CSRST
Core soft reset
0
1
read-write
HCSRST
HCLK soft reset
1
1
read-write
HFCRST
Host frame counter reset
2
1
read-write
RXFF
RxFIFO flush
4
1
read-write
TXFF
TxFIFO flush
5
1
read-write
TXFNUM
TxFIFO number
6
5
read-write
GUSBCS
GUSBCS
Global USB control and status register (OTG_FS_GUSBCS)
0xC
32
read-write
n
0x0
0x0
FDM
Force device mode
30
1
read-write
FHM
Force host mode
29
1
read-write
HNPCEN
HNP capability enable
9
1
read-write
SRPCEN
SRP capability enable
8
1
read-write
TOC
Timeout calibration
0
3
read-write
UTT
USB turnaround time
10
4
read-write
HNPTFLEN
HNPTFLEN
Host non-periodic transmit FIFO length register (Host mode)
0x28
32
read-write
n
0x0
0x0
HNPTXFD
host non-periodic TxFIFO depth
16
16
HNPTXRSAR
host non-periodic transmit Tx RAM start address
0
16
HNPTFQSTAT
HNPTFQSTAT
Host non-periodic transmit FIFO/queue status register (HNPTFQSTAT)
0x2C
32
read-only
n
0x0
0x0
NPTXFS
Non-periodic TxFIFO space
0
16
NPTXRQS
Non-periodic transmit request queue space
16
8
NPTXRQTOP
Top of the non-periodic transmit request queue
24
7
HPTFLEN
HPTFLEN
Host periodic transmit FIFO length register (HPTFLEN)
0x100
32
read-write
n
0x0
0x0
HPTXFD
Host periodic TxFIFO depth
16
16
HPTXFSAR
Host periodic TxFIFO start address
0
16
USBFS_HOST
USB on the go full speed host
USBFS
0x0
0x0
0x400
registers
n
HACHINT
HACHINT
Host all channels interrupt register
0x14
32
read-only
n
0x0
0x0
HACHINT
Host all channel interrupts
0
8
HACHINTEN
HACHINTEN
host all channels interrupt mask register
0x18
32
read-write
n
0x0
0x0
CINTEN
Channel interrupt enable
0
8
HCH0CTL
HCH0CTL
host channel-0 characteristics register (HCH0CTL)
0x100
32
read-write
n
0x0
0x0
CDIS
Channel disable
30
1
CEN
Channel enable
31
1
DAR
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYPE
Endpoint type
18
2
LSD
Low-speed device
17
1
MPL
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
HCH0INTEN
HCH0INTEN
host channel-0 interrupt enable register (HCH0INTEN)
0x10C
32
read-write
n
0x0
0x0
ACKIE
ACK interrupt enable
5
1
BBERIE
Babble error interrupt enable
8
1
CHIE
Channel halted interrupt enable
1
1
DTERIE
Data toggle error interrupt enable
10
1
NAKIE
NAK interrupt enable
4
1
REQOVRIE
request queue overrun interrupt enable
9
1
STALLIE
STALL interrupt enable
3
1
TFIE
Transfer completed interrupt enable
0
1
USBERIE
USB bus error interrupt enable
7
1
HCH0INTF
HCH0INTF
host channel-0 interrupt register (USBFS_HCHxINTF)
0x108
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
BBER
Babble error
8
1
CH
Channel halted
1
1
DTER
Data toggle error
10
1
NAK
NAK response received interrupt
4
1
REQOVR
Request queue overrun
9
1
STALL
STALL response received interrupt
3
1
TF
Transfer finished
0
1
USBER
USB bus error
7
1
HCH0LEN
HCH0LEN
host channel-0 transfer length register
0x110
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PCNT
Packet count
19
10
TLEN
Transfer length
0
19
HCH1CTL
HCH1CTL
host channel-1 characteristics register (HCH1CTL)
0x120
32
read-write
n
0x0
0x0
CDIS
Channel disable
30
1
CEN
Channel enable
31
1
DAR
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYPE
Endpoint type
18
2
LSD
Low-speed device
17
1
MPL
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
HCH1INTEN
HCH1INTEN
host channel-1 interrupt enable register (HCH1INTEN)
0x12C
32
read-write
n
0x0
0x0
ACKIE
ACK interrupt enable
5
1
BBERIE
Babble error interrupt enable
8
1
CHIE
Channel halted interrupt enable
1
1
DTERIE
Data toggle error interrupt enable
10
1
NAKIE
NAK interrupt enable
4
1
REQOVRIE
request queue overrun interrupt enable
9
1
STALLIE
STALL interrupt enable
3
1
TFIE
Transfer completed interrupt enable
0
1
USBERIE
USB bus error interrupt enable
7
1
HCH1INTF
HCH1INTF
host channel-1 interrupt register (HCH1INTF)
0x128
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
BBER
Babble error
8
1
CH
Channel halted
1
1
DTER
Data toggle error
10
1
NAK
NAK response received interrupt
4
1
REQOVR
Request queue overrun
9
1
STALL
STALL response received interrupt
3
1
TF
Transfer finished
0
1
USBER
USB bus error
7
1
HCH1LEN
HCH1LEN
host channel-1 transfer length register
0x130
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PCNT
Packet count
19
10
TLEN
Transfer length
0
19
HCH2CTL
HCH2CTL
host channel-2 characteristics register (HCH2CTL)
0x140
32
read-write
n
0x0
0x0
CDIS
Channel disable
30
1
CEN
Channel enable
31
1
DAR
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYPE
Endpoint type
18
2
LSD
Low-speed device
17
1
MPL
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
HCH2INTEN
HCH2INTEN
host channel-2 interrupt enable register (HCH2INTEN)
0x14C
32
read-write
n
0x0
0x0
ACKIE
ACK interrupt enable
5
1
BBERIE
Babble error interrupt enable
8
1
CHIE
Channel halted interrupt enable
1
1
DTERIE
Data toggle error interrupt enable
10
1
NAKIE
NAK interrupt enable
4
1
REQOVRIE
request queue overrun interrupt enable
9
1
STALLIE
STALL interrupt enable
3
1
TFIE
Transfer completed interrupt enable
0
1
USBERIE
USB bus error interrupt enable
7
1
HCH2INTF
HCH2INTF
host channel-2 interrupt register (HCH2INTF)
0x148
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
BBER
Babble error
8
1
CH
Channel halted
1
1
DTER
Data toggle error
10
1
NAK
NAK response received interrupt
4
1
REQOVR
Request queue overrun
9
1
STALL
STALL response received interrupt
3
1
TF
Transfer finished
0
1
USBER
USB bus error
7
1
HCH2LEN
HCH2LEN
host channel-2 transfer length register
0x150
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PCNT
Packet count
19
10
TLEN
Transfer length
0
19
HCH3CTL
HCH3CTL
host channel-3 characteristics register (HCH3CTL)
0x160
32
read-write
n
0x0
0x0
CDIS
Channel disable
30
1
CEN
Channel enable
31
1
DAR
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYPE
Endpoint type
18
2
LSD
Low-speed device
17
1
MPL
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
HCH3INTEN
HCH3INTEN
host channel-3 interrupt enable register (HCH3INTEN)
0x16C
32
read-write
n
0x0
0x0
ACKIE
ACK interrupt enable
5
1
BBERIE
Babble error interrupt enable
8
1
CHIE
Channel halted interrupt enable
1
1
DTERIE
Data toggle error interrupt enable
10
1
NAKIE
NAK interrupt enable
4
1
REQOVRIE
request queue overrun interrupt enable
9
1
STALLIE
STALL interrupt enable
3
1
TFIE
Transfer completed interrupt enable
0
1
USBERIE
USB bus error interrupt enable
7
1
HCH3INTF
HCH3INTF
host channel-3 interrupt register (HCH3INTF)
0x168
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
BBER
Babble error
8
1
CH
Channel halted
1
1
DTER
Data toggle error
10
1
NAK
NAK response received interrupt
4
1
REQOVR
Request queue overrun
9
1
STALL
STALL response received interrupt
3
1
TF
Transfer finished
0
1
USBER
USB bus error
7
1
HCH3LEN
HCH3LEN
host channel-3 transfer length register
0x170
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PCNT
Packet count
19
10
TLEN
Transfer length
0
19
HCH4CTL
HCH4CTL
host channel-4 characteristics register (HCH4CTL)
0x180
32
read-write
n
0x0
0x0
CDIS
Channel disable
30
1
CEN
Channel enable
31
1
DAR
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYPE
Endpoint type
18
2
LSD
Low-speed device
17
1
MPL
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
HCH4INTEN
HCH4INTEN
host channel-4 interrupt enable register (HCH4INTEN)
0x18C
32
read-write
n
0x0
0x0
ACKIE
ACK interrupt enable
5
1
BBERIE
Babble error interrupt enable
8
1
CHIE
Channel halted interrupt enable
1
1
DTERIE
Data toggle error interrupt enable
10
1
NAKIE
NAK interrupt enable
4
1
REQOVRIE
request queue overrun interrupt enable
9
1
STALLIE
STALL interrupt enable
3
1
TFIE
Transfer completed interrupt enable
0
1
USBERIE
USB bus error interrupt enable
7
1
HCH4INTF
HCH4INTF
host channel-4 interrupt register (HCH4INTF)
0x188
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
BBER
Babble error
8
1
CH
Channel halted
1
1
DTER
Data toggle error
10
1
NAK
NAK response received interrupt
4
1
REQOVR
Request queue overrun
9
1
STALL
STALL response received interrupt
3
1
TF
Transfer finished
0
1
USBER
USB bus error
7
1
HCH4LEN
HCH4LEN
host channel-4 transfer length register
0x190
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PCNT
Packet count
19
10
TLEN
Transfer length
0
19
HCH5CTL
HCH5CTL
host channel-5 characteristics register (HCH5CTL)
0x1A0
32
read-write
n
0x0
0x0
CDIS
Channel disable
30
1
CEN
Channel enable
31
1
DAR
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYPE
Endpoint type
18
2
LSD
Low-speed device
17
1
MPL
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
HCH5INTEN
HCH5INTEN
host channel-5 interrupt enable register (HCH5INTEN)
0x1AC
32
read-write
n
0x0
0x0
ACKIE
ACK interrupt enable
5
1
BBERIE
Babble error interrupt enable
8
1
CHIE
Channel halted interrupt enable
1
1
DTERIE
Data toggle error interrupt enable
10
1
NAKIE
NAK interrupt enable
4
1
REQOVRIE
request queue overrun interrupt enable
9
1
STALLIE
STALL interrupt enable
3
1
TFIE
Transfer completed interrupt enable
0
1
USBERIE
USB bus error interrupt enable
7
1
HCH5INTF
HCH5INTF
host channel-5 interrupt register (HCH5INTF)
0x1A8
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
BBER
Babble error
8
1
CH
Channel halted
1
1
DTER
Data toggle error
10
1
NAK
NAK response received interrupt
4
1
REQOVR
Request queue overrun
9
1
STALL
STALL response received interrupt
3
1
TF
Transfer finished
0
1
USBER
USB bus error
7
1
HCH5LEN
HCH5LEN
host channel-5 transfer length register
0x1B0
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PCNT
Packet count
19
10
TLEN
Transfer length
0
19
HCH6CTL
HCH6CTL
host channel-6 characteristics register (HCH6CTL)
0x1C0
32
read-write
n
0x0
0x0
CDIS
Channel disable
30
1
CEN
Channel enable
31
1
DAR
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYPE
Endpoint type
18
2
LSD
Low-speed device
17
1
MPL
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
HCH6INTEN
HCH6INTEN
host channel-6 interrupt enable register (HCH6INTEN)
0x1CC
32
read-write
n
0x0
0x0
ACKIE
ACK interrupt enable
5
1
BBERIE
Babble error interrupt enable
8
1
CHIE
Channel halted interrupt enable
1
1
DTERIE
Data toggle error interrupt enable
10
1
NAKIE
NAK interrupt enable
4
1
REQOVRIE
request queue overrun interrupt enable
9
1
STALLIE
STALL interrupt enable
3
1
TFIE
Transfer completed interrupt enable
0
1
USBERIE
USB bus error interrupt enable
7
1
HCH6INTF
HCH6INTF
host channel-6 interrupt register (HCH6INTF)
0x1C8
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
BBER
Babble error
8
1
CH
Channel halted
1
1
DTER
Data toggle error
10
1
NAK
NAK response received interrupt
4
1
REQOVR
Request queue overrun
9
1
STALL
STALL response received interrupt
3
1
TF
Transfer finished
0
1
USBER
USB bus error
7
1
HCH6LEN
HCH6LEN
host channel-6 transfer length register
0x1D0
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PCNT
Packet count
19
10
TLEN
Transfer length
0
19
HCH7CTL
HCH7CTL
host channel-7 characteristics register (HCH7CTL)
0x1E0
32
read-write
n
0x0
0x0
CDIS
Channel disable
30
1
CEN
Channel enable
31
1
DAR
Device address
22
7
EPDIR
Endpoint direction
15
1
EPNUM
Endpoint number
11
4
EPTYPE
Endpoint type
18
2
LSD
Low-speed device
17
1
MPL
Maximum packet size
0
11
ODDFRM
Odd frame
29
1
HCH7INTEN
HCH7INTEN
host channel-7 interrupt enable register (HCH7INTEN)
0x1EC
32
read-write
n
0x0
0x0
ACKIE
ACK interrupt enable
5
1
BBERIE
Babble error interrupt enable
8
1
CHIE
Channel halted interrupt enable
1
1
DTERIE
Data toggle error interrupt enable
10
1
NAKIE
NAK interrupt enable
4
1
REQOVRIE
request queue overrun interrupt enable
9
1
STALLIE
STALL interrupt enable
3
1
TFIE
Transfer completed interrupt enable
0
1
USBERIE
USB bus error interrupt enable
7
1
HCH7INTF
HCH7INTF
host channel-7 interrupt register (HCH7INTF)
0x1E8
32
read-write
n
0x0
0x0
ACK
ACK response received/transmitted interrupt
5
1
BBER
Babble error
8
1
CH
Channel halted
1
1
DTER
Data toggle error
10
1
NAK
NAK response received interrupt
4
1
REQOVR
Request queue overrun
9
1
STALL
STALL response received interrupt
3
1
TF
Transfer finished
0
1
USBER
USB bus error
7
1
HCH7LEN
HCH7LEN
host channel-7 transfer length register
0x1F0
32
read-write
n
0x0
0x0
DPID
Data PID
29
2
PCNT
Packet count
19
10
TLEN
Transfer length
0
19
HCTL
HCTL
host configuration register (HCTL)
0x0
32
read-write
n
0x0
0x0
CLKSEL
clock select for USB clock
0
2
read-write
HFINFR
HFINFR
OTG_FS host frame number/frame time remaining register (HFINFR)
0x8
32
read-only
n
0x0
0x0
FRNUM
Frame number
0
16
FRT
Frame remaining time
16
16
HFT
HFT
Host frame interval register
0x4
32
read-write
n
0x0
0x0
FRI
Frame interval
0
16
HPCS
HPCS
Host port control and status register (USBFS_HPCS)
0x40
32
read-write
n
0x0
0x0
PCD
Port connect detected
1
1
read-write
PCST
Port connect status
0
1
read-only
PE
Port enable
2
1
read-write
PEDC
Port enable/disable change
3
1
read-write
PLST
Port line status
10
2
read-only
PP
Port power
12
1
read-write
PREM
Port resume
6
1
read-write
PRST
Port reset
8
1
read-write
PS
Port speed
17
2
read-only
PSP
Port suspend
7
1
read-write
HPTFQSTAT
HPTFQSTAT
Host periodic transmit FIFO/queue status register (HPTFQSTAT)
0x10
32
read-write
n
0x0
0x0
PTXFS
Periodic transmit data FIFO space available
0
16
read-only
PTXREQS
Periodic transmit request queue space available
16
8
read-only
PTXREQT
Top of the periodic transmit request queue
24
8
read-only
USBFS_PWRCLK
USB on the go full speed
USBFS
0x0
0x0
0x100
registers
n
PWRCLKCTL
PWRCLKCTL
power and clock gating control register (PWRCLKCTL)
0x0
32
read-write
n
0x0
0x0
SHCLK
Stop HCLK
1
1
SUCLK
Stop the USB clock
0
1
WWDGT
Window watchdog timer
WWDGT
0x0
0x0
0x400
registers
n
WWDGT
0
CFG
CFG
Configuration register
0x4
32
read-write
n
0x0
0x0
EWIE
Early wakeup interrupt
9
1
PSC
Prescaler
7
2
WIN
7-bit window value
0
7
CTL
CTL
Control register
0x0
32
read-write
n
0x0
0x0
CNT
The value of the watchdog timer counter
0
7
WDGTEN
Activation bit
7
1
STAT
STAT
Status register
0x8
32
read-write
n
0x0
0x0
EWIF
Early wakeup interrupt flag
0
1