GigaDevice GD32F4xx 2024.04.30 GD32F4xx ARM 32-bit Cortex-M4 Microcontroller based device CM4 r2p1 little true true 4 false 8 32 ADC0 Analog to digital converter ADC 0x0 0x0 0x100 registers n ADC 18 CTL0 CTL0 control register 0 0x4 32 read-write n 0x0 0x0 DISIC Discontinuous mode on inserted channels 12 1 DISNUM Number of conversions in discontinuous mode 13 3 DISRC Discontinuous mode on regular channels 11 1 DRES ADC data resolution 24 2 EOCIE Interrupt enable for EOC 5 1 EOICIE Interrupt enable for EOIC 7 1 ICA Inserted channel group convert automatically 10 1 IWDEN Inserted channel analog watchdog enable 22 1 ROVFIE Interrupt enable for ROVF 26 1 RWDEN Regular channel analog watchdog enable 23 1 SM Scan mode 8 1 WDCHSEL Analog watchdog channel select 0 5 WDEIE Analog watchdog WDE 6 1 WDSC When in scan mode, analog watchdog is effective on a single channel 9 1 CTL1 CTL1 control register 1 0x8 32 read-write n 0x0 0x0 ADCON ADC on 0 1 CLB ADC calibration 2 1 CTN Continuous mode 1 1 DAL Data alignment 11 1 DDM DMA disable mode 9 1 DMA DMA request enable 8 1 EOCM End of conversion mode 10 1 ETMIC External trigger mode for inserted channel 20 2 ETMRC External trigger mode for regular channel 28 2 ETSIC External trigger select for inserted channel 16 4 ETSRC External trigger select for regular channel 24 4 RSTCLB Reset calibration 3 1 SWICST Software start on inserted channel 22 1 SWRCST Software start on regular channel 30 1 IDATA0 IDATA0 Inserted data register 0 0x3C 32 read-only n 0x0 0x0 IDATAn Inserted number n conversion data 0 16 IDATA1 IDATA1 Inserted data register 1 0x40 32 read-only n 0x0 0x0 IDATAn Inserted number n conversion data 0 16 IDATA2 IDATA2 Inserted data register 2 0x44 32 read-only n 0x0 0x0 IDATAn Inserted number n conversion data 0 16 IDATA3 IDATA3 Inserted data register 3 0x48 32 read-only n 0x0 0x0 IDATAn Inserted number n conversion data 0 16 IOFF0 IOFF0 Inserted channel data offset register 0 0x14 32 read-write n 0x0 0x0 IOFF Data offset for inserted channel 0 0 12 IOFF1 IOFF1 Inserted channel data offset register 1 0x18 32 read-write n 0x0 0x0 IOFF Data offset for inserted channel 1 0 12 IOFF2 IOFF2 Inserted channel data offset register 2 0x1C 32 read-write n 0x0 0x0 IOFF Data offset for inserted channel 2 0 12 IOFF3 IOFF3 Inserted channel data offset register 3 0x20 32 read-write n 0x0 0x0 IOFF Data offset for inserted channel 3 0 12 ISQ ISQ Inserted sequence register 0x38 32 read-write n 0x0 0x0 IL Inserted channel group length 20 2 ISQ0 1st conversion in inserted sequence 0 5 ISQ1 2nd conversion in inserted sequence 5 5 ISQ2 3rd conversion in inserted sequence 10 5 ISQ3 4th conversion in inserted sequence 15 5 OVSAMPCTL OVSAMPCTL Oversample control register 0x80 32 read-only n 0x0 0x0 OVSEN Oversampling Enable 0 1 OVSR Oversampling ratio 2 3 OVSS Oversampling shift 5 4 TOVS Triggered Oversampling 9 1 RDATA RDATA regular data register 0x4C 32 read-only n 0x0 0x0 RDATA Regular channel data 0 16 RSQ0 RSQ0 regular sequence register 0 0x2C 32 read-write n 0x0 0x0 RL Regular channel group length 20 4 RSQ12 13th conversion in regular sequence 0 5 RSQ13 14th conversion in regular sequence 5 5 RSQ14 15th conversion in regular sequence 10 5 RSQ15 16th conversion in regular sequence 15 5 RSQ1 RSQ1 regular sequence register 1 0x30 32 read-write n 0x0 0x0 RSQ10 11th conversion in regular sequence 20 5 RSQ11 12th conversion in regular sequence 25 5 RSQ6 7th conversion in regular sequence 0 5 RSQ7 8th conversion in regular sequence 5 5 RSQ8 9th conversion in regular sequence 10 5 RSQ9 10th conversion in regular sequence 15 5 RSQ2 RSQ2 regular sequence register 2 0x34 32 read-write n 0x0 0x0 RSQ0 1st conversion in regular sequence 0 5 RSQ1 2nd conversion in regular sequence 5 5 RSQ2 3rd conversion in regular sequence 10 5 RSQ3 4th conversion in regular sequence 15 5 RSQ4 5th conversion in regular sequence 20 5 RSQ5 6th conversion in regular sequence 25 5 SAMPT0 SAMPT0 Sample time register 0 0xC 32 read-write n 0x0 0x0 SPT10 Channel 10 sample time selection 0 3 SPT11 Channel 11 sample time selection 3 3 SPT12 Channel 12 sample time selection 6 3 SPT13 Channel 13 sample time selection 9 3 SPT14 Channel 14 sample time selection 12 3 SPT15 Channel 15 sample time selection 15 3 SPT16 Channel 16 sample time selection 18 3 SPT17 Channel 17 sample time selection 21 3 SPT18 Channel 18 sample time selection 24 3 SAMPT1 SAMPT1 Sample time register 1 0x10 32 read-write n 0x0 0x0 SPT0 Channel 0 sample time selection 0 3 SPT1 Channel 1 sample time selection 3 3 SPT2 Channel 2 sample time selection 6 3 SPT3 Channel 3 sample time selection 9 3 SPT4 Channel 4 sample time selection 12 3 SPT5 Channel 5 sample time selection 15 3 SPT6 Channel 6 sample time selection 18 3 SPT7 Channel 7 sample time selection 21 3 SPT8 Channel 8 sample time selection 24 3 SPT9 Channel 9 sample time selection 27 3 STAT STAT status register 0x0 32 read-write n 0x0 0x0 EOC End of group conversion flag 1 1 EOIC End of inserted group conversion flag 2 1 ROVF Regular data register overflow 5 1 STIC Start flag of inserted channel group 3 1 STRC Start flag of regular channel group 4 1 WDE Analog watchdog event flag 0 1 WDHT WDHT watchdog higher threshold register 0x24 32 read-write n 0x0 0x0 WDHT Analog watchdog higher threshold 0 12 WDLT WDLT watchdog lower threshold register 0x28 32 read-write n 0x0 0x0 WDLT Analog watchdog lower threshold 0 12 ADC1 Analog to digital converter ADC 0x0 0x0 0x100 registers n ADC 18 CTL0 CTL0 control register 0 0x4 32 read-write n 0x0 0x0 DISIC Discontinuous mode on inserted channels 12 1 DISNUM Number of conversions in discontinuous mode 13 3 DISRC Discontinuous mode on regular channels 11 1 DRES ADC data resolution 24 2 EOCIE Interrupt enable for EOC 5 1 EOICIE Interrupt enable for EOIC 7 1 ICA Inserted channel group convert automatically 10 1 IWDEN Inserted channel analog watchdog enable 22 1 ROVFIE Interrupt enable for ROVF 26 1 RWDEN Regular channel analog watchdog enable 23 1 SM Scan mode 8 1 WDCHSEL Analog watchdog channel select 0 5 WDEIE Analog watchdog WDE 6 1 WDSC When in scan mode, analog watchdog is effective on a single channel 9 1 CTL1 CTL1 control register 1 0x8 32 read-write n 0x0 0x0 ADCON ADC on 0 1 CLB ADC calibration 2 1 CTN Continuous mode 1 1 DAL Data alignment 11 1 DDM DMA disable mode 9 1 DMA DMA request enable 8 1 EOCM End of conversion mode 10 1 ETMIC External trigger mode for inserted channel 20 2 ETMRC External trigger mode for regular channel 28 2 ETSIC External trigger select for inserted channel 16 4 ETSRC External trigger select for regular channel 24 4 RSTCLB Reset calibration 3 1 SWICST Software start on inserted channel 22 1 SWRCST Software start on regular channel 30 1 IDATA0 IDATA0 Inserted data register 0 0x3C 32 read-only n 0x0 0x0 IDATAn Inserted number n conversion data 0 16 IDATA1 IDATA1 Inserted data register 1 0x40 32 read-only n 0x0 0x0 IDATAn Inserted number n conversion data 0 16 IDATA2 IDATA2 Inserted data register 2 0x44 32 read-only n 0x0 0x0 IDATAn Inserted number n conversion data 0 16 IDATA3 IDATA3 Inserted data register 3 0x48 32 read-only n 0x0 0x0 IDATAn Inserted number n conversion data 0 16 IOFF0 IOFF0 Inserted channel data offset register 0 0x14 32 read-write n 0x0 0x0 IOFF Data offset for inserted channel 0 0 12 IOFF1 IOFF1 Inserted channel data offset register 1 0x18 32 read-write n 0x0 0x0 IOFF Data offset for inserted channel 1 0 12 IOFF2 IOFF2 Inserted channel data offset register 2 0x1C 32 read-write n 0x0 0x0 IOFF Data offset for inserted channel 2 0 12 IOFF3 IOFF3 Inserted channel data offset register 3 0x20 32 read-write n 0x0 0x0 IOFF Data offset for inserted channel 3 0 12 ISQ ISQ Inserted sequence register 0x38 32 read-write n 0x0 0x0 IL Inserted channel group length 20 2 ISQ0 1st conversion in inserted sequence 0 5 ISQ1 2nd conversion in inserted sequence 5 5 ISQ2 3rd conversion in inserted sequence 10 5 ISQ3 4th conversion in inserted sequence 15 5 OVSAMPCTL OVSAMPCTL Oversample control register 0x80 32 read-only n 0x0 0x0 OVSEN Oversampling Enable 0 1 OVSR Oversampling ratio 2 3 OVSS Oversampling shift 5 4 TOVS Triggered Oversampling 9 1 RDATA RDATA regular data register 0x4C 32 read-only n 0x0 0x0 RDATA Regular channel data 0 16 RSQ0 RSQ0 regular sequence register 0 0x2C 32 read-write n 0x0 0x0 RL Regular channel group length 20 4 RSQ12 13th conversion in regular sequence 0 5 RSQ13 14th conversion in regular sequence 5 5 RSQ14 15th conversion in regular sequence 10 5 RSQ15 16th conversion in regular sequence 15 5 RSQ1 RSQ1 regular sequence register 1 0x30 32 read-write n 0x0 0x0 RSQ10 11th conversion in regular sequence 20 5 RSQ11 12th conversion in regular sequence 25 5 RSQ6 7th conversion in regular sequence 0 5 RSQ7 8th conversion in regular sequence 5 5 RSQ8 9th conversion in regular sequence 10 5 RSQ9 10th conversion in regular sequence 15 5 RSQ2 RSQ2 regular sequence register 2 0x34 32 read-write n 0x0 0x0 RSQ0 1st conversion in regular sequence 0 5 RSQ1 2nd conversion in regular sequence 5 5 RSQ2 3rd conversion in regular sequence 10 5 RSQ3 4th conversion in regular sequence 15 5 RSQ4 5th conversion in regular sequence 20 5 RSQ5 6th conversion in regular sequence 25 5 SAMPT0 SAMPT0 Sample time register 0 0xC 32 read-write n 0x0 0x0 SPT10 Channel 10 sample time selection 0 3 SPT11 Channel 11 sample time selection 3 3 SPT12 Channel 12 sample time selection 6 3 SPT13 Channel 13 sample time selection 9 3 SPT14 Channel 14 sample time selection 12 3 SPT15 Channel 15 sample time selection 15 3 SPT16 Channel 16 sample time selection 18 3 SPT17 Channel 17 sample time selection 21 3 SPT18 Channel 18 sample time selection 24 3 SAMPT1 SAMPT1 Sample time register 1 0x10 32 read-write n 0x0 0x0 SPT0 Channel 0 sample time selection 0 3 SPT1 Channel 1 sample time selection 3 3 SPT2 Channel 2 sample time selection 6 3 SPT3 Channel 3 sample time selection 9 3 SPT4 Channel 4 sample time selection 12 3 SPT5 Channel 5 sample time selection 15 3 SPT6 Channel 6 sample time selection 18 3 SPT7 Channel 7 sample time selection 21 3 SPT8 Channel 8 sample time selection 24 3 SPT9 Channel 9 sample time selection 27 3 STAT STAT status register 0x0 32 read-write n 0x0 0x0 EOC End of group conversion flag 1 1 EOIC End of inserted group conversion flag 2 1 ROVF Regular data register overflow 5 1 STIC Start flag of inserted channel group 3 1 STRC Start flag of regular channel group 4 1 WDE Analog watchdog event flag 0 1 WDHT WDHT watchdog higher threshold register 0x24 32 read-write n 0x0 0x0 WDHT Analog watchdog higher threshold 0 12 WDLT WDLT watchdog lower threshold register 0x28 32 read-write n 0x0 0x0 WDLT Analog watchdog lower threshold 0 12 ADC2 Analog to digital converter ADC 0x0 0x0 0x100 registers n ADC 18 CTL0 CTL0 control register 0 0x4 32 read-write n 0x0 0x0 DISIC Discontinuous mode on inserted channels 12 1 DISNUM Number of conversions in discontinuous mode 13 3 DISRC Discontinuous mode on regular channels 11 1 DRES ADC data resolution 24 2 EOCIE Interrupt enable for EOC 5 1 EOICIE Interrupt enable for EOIC 7 1 ICA Inserted channel group convert automatically 10 1 IWDEN Inserted channel analog watchdog enable 22 1 ROVFIE Interrupt enable for ROVF 26 1 RWDEN Regular channel analog watchdog enable 23 1 SM Scan mode 8 1 WDCHSEL Analog watchdog channel select 0 5 WDEIE Analog watchdog WDE 6 1 WDSC When in scan mode, analog watchdog is effective on a single channel 9 1 CTL1 CTL1 control register 1 0x8 32 read-write n 0x0 0x0 ADCON ADC on 0 1 CLB ADC calibration 2 1 CTN Continuous mode 1 1 DAL Data alignment 11 1 DDM DMA disable mode 9 1 DMA DMA request enable 8 1 EOCM End of conversion mode 10 1 ETMIC External trigger mode for inserted channel 20 2 ETMRC External trigger mode for regular channel 28 2 ETSIC External trigger select for inserted channel 16 4 ETSRC External trigger select for regular channel 24 4 RSTCLB Reset calibration 3 1 SWICST Software start on inserted channel 22 1 SWRCST Software start on regular channel 30 1 IDATA0 IDATA0 Inserted data register 0 0x3C 32 read-only n 0x0 0x0 IDATAn Inserted number n conversion data 0 16 IDATA1 IDATA1 Inserted data register 1 0x40 32 read-only n 0x0 0x0 IDATAn Inserted number n conversion data 0 16 IDATA2 IDATA2 Inserted data register 2 0x44 32 read-only n 0x0 0x0 IDATAn Inserted number n conversion data 0 16 IDATA3 IDATA3 Inserted data register 3 0x48 32 read-only n 0x0 0x0 IDATAn Inserted number n conversion data 0 16 IOFF0 IOFF0 Inserted channel data offset register 0 0x14 32 read-write n 0x0 0x0 IOFF Data offset for inserted channel 0 0 12 IOFF1 IOFF1 Inserted channel data offset register 1 0x18 32 read-write n 0x0 0x0 IOFF Data offset for inserted channel 1 0 12 IOFF2 IOFF2 Inserted channel data offset register 2 0x1C 32 read-write n 0x0 0x0 IOFF Data offset for inserted channel 2 0 12 IOFF3 IOFF3 Inserted channel data offset register 3 0x20 32 read-write n 0x0 0x0 IOFF Data offset for inserted channel 3 0 12 ISQ ISQ Inserted sequence register 0x38 32 read-write n 0x0 0x0 IL Inserted channel group length 20 2 ISQ0 1st conversion in inserted sequence 0 5 ISQ1 2nd conversion in inserted sequence 5 5 ISQ2 3rd conversion in inserted sequence 10 5 ISQ3 4th conversion in inserted sequence 15 5 OVSAMPCTL OVSAMPCTL Oversample control register 0x80 32 read-only n 0x0 0x0 OVSEN Oversampling Enable 0 1 OVSR Oversampling ratio 2 3 OVSS Oversampling shift 5 4 TOVS Triggered Oversampling 9 1 RDATA RDATA regular data register 0x4C 32 read-only n 0x0 0x0 RDATA Regular channel data 0 16 RSQ0 RSQ0 regular sequence register 0 0x2C 32 read-write n 0x0 0x0 RL Regular channel group length 20 4 RSQ12 13th conversion in regular sequence 0 5 RSQ13 14th conversion in regular sequence 5 5 RSQ14 15th conversion in regular sequence 10 5 RSQ15 16th conversion in regular sequence 15 5 RSQ1 RSQ1 regular sequence register 1 0x30 32 read-write n 0x0 0x0 RSQ10 11th conversion in regular sequence 20 5 RSQ11 12th conversion in regular sequence 25 5 RSQ6 7th conversion in regular sequence 0 5 RSQ7 8th conversion in regular sequence 5 5 RSQ8 9th conversion in regular sequence 10 5 RSQ9 10th conversion in regular sequence 15 5 RSQ2 RSQ2 regular sequence register 2 0x34 32 read-write n 0x0 0x0 RSQ0 1st conversion in regular sequence 0 5 RSQ1 2nd conversion in regular sequence 5 5 RSQ2 3rd conversion in regular sequence 10 5 RSQ3 4th conversion in regular sequence 15 5 RSQ4 5th conversion in regular sequence 20 5 RSQ5 6th conversion in regular sequence 25 5 SAMPT0 SAMPT0 Sample time register 0 0xC 32 read-write n 0x0 0x0 SPT10 Channel 10 sample time selection 0 3 SPT11 Channel 11 sample time selection 3 3 SPT12 Channel 12 sample time selection 6 3 SPT13 Channel 13 sample time selection 9 3 SPT14 Channel 14 sample time selection 12 3 SPT15 Channel 15 sample time selection 15 3 SPT16 Channel 16 sample time selection 18 3 SPT17 Channel 17 sample time selection 21 3 SPT18 Channel 18 sample time selection 24 3 SAMPT1 SAMPT1 Sample time register 1 0x10 32 read-write n 0x0 0x0 SPT0 Channel 0 sample time selection 0 3 SPT1 Channel 1 sample time selection 3 3 SPT2 Channel 2 sample time selection 6 3 SPT3 Channel 3 sample time selection 9 3 SPT4 Channel 4 sample time selection 12 3 SPT5 Channel 5 sample time selection 15 3 SPT6 Channel 6 sample time selection 18 3 SPT7 Channel 7 sample time selection 21 3 SPT8 Channel 8 sample time selection 24 3 SPT9 Channel 9 sample time selection 27 3 STAT STAT status register 0x0 32 read-write n 0x0 0x0 EOC End of group conversion flag 1 1 EOIC End of inserted group conversion flag 2 1 ROVF Regular data register overflow 5 1 STIC Start flag of inserted channel group 3 1 STRC Start flag of regular channel group 4 1 WDE Analog watchdog event flag 0 1 WDHT WDHT watchdog higher threshold register 0x24 32 read-write n 0x0 0x0 WDHT Analog watchdog higher threshold 0 12 WDLT WDLT watchdog lower threshold register 0x28 32 read-write n 0x0 0x0 WDLT Analog watchdog lower threshold 0 12 ADC_Common common ADC register ADC_Common 0x0 0x0 0x100 registers n SSTAT SSTAT summary status register 0x0 32 read-only n 0x0 0x0 EOC0 This bit equals to the EOC bit of ADC0 1 1 EOC1 This bit equals to the EOC bit of ADC1 9 1 EOC2 This bit equals to the EOC bit of ADC2 17 1 EOIC0 This bit equals to the EOIC bit of ADC0 2 1 EOIC1 This bit equals to the EOIC bit of ADC1 10 1 EOIC2 This bit equals to the EOIC bit of ADC2 18 1 ROVF0 This bit equals to the ROVF bit of ADC0 5 1 ROVF1 This bit equals to the ROVF bit of ADC1 13 1 ROVF2 This bit equals to the ROVF bit of ADC2 21 1 STIC0 This bit equals to the STIC bit of ADC0 3 1 STIC1 This bit equals to the STIC bit of ADC1 11 1 STIC2 This bit equals to the STIC bit of ADC2 19 1 STRC0 This bit equals to the STRC bit of ADC0 4 1 STRC1 This bit equals to the STRC bit of ADC1 12 1 STRC2 This bit equals to the STRC bit of ADC2 20 1 WDE0 This bit equals to the WDE bit of ADC0 0 1 WDE1 This bit equals to the WDE bit of ADC1 8 1 WDE2 This bit equals to the WDE bit of ADC2 16 1 SYNCCTL SYNCCTL sync control register 0x4 32 read-write n 0x0 0x0 ADCCK ADC clock 16 3 SYNCDDM ADC sync DMA disable mode 13 1 SYNCDLY ADC sync delay 8 4 SYNCDMA ADC sync DMA mode selection 14 2 SYNCM ADC sync mode 0 5 TSVREN Channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0 23 1 VBATEN Channel 18 (1/4 voltate of external battery) enable of ADC0 22 1 SYNCDATA SYNCDATA Sync regular data register 0x8 32 read-only n 0x0 0x0 SYNCDATA1 Regular data1 in ADC sync mode 0 16 SYNCDATA2 Regular data2 in ADC sync mode 16 16 CAN0 Controller area network CAN 0x0 0x0 0x400 registers n CAN0_TX 19 CAN0_RX0 20 CAN0_RX1 21 CAN0_EWMC 22 BT BT Bit timing register 0x1C 32 read-write n 0x0 0x0 BS1 Bit segment 1 16 4 BS2 Bit segment 2 20 3 BUADPSC Baud rate prescaler 0 10 LCMOD Loopback communication mode 30 1 SCMOD Silent communication mode 31 1 SJW Resynchronization jump width 24 2 CTL CTL Control register 0x0 32 read-write n 0x0 0x0 ABOR Automatic bus-off recovery 6 1 ARD Automatic retransmission disable 4 1 AWU Automatic wakeup 5 1 DFZ Debug freeze 16 1 IWMOD Initial working mode 0 1 RFOD Receive FIFO overwrite disable 3 1 SLPWMOD Sleep working mode 1 1 SWRST Software reset 15 1 TFO Transmit FIFO order 2 1 TTC Time-triggered communication 7 1 ERR ERR Error register 0x18 32 read-write n 0x0 0x0 BOERR Bus-off error 2 1 read-only ERRN Error number 4 3 read-write PERR Passive error 1 1 read-only RECNT Receive Error Count defined by the CAN standard 24 8 read-only TECNT Transmit Error Count defined by the CAN standard 16 8 read-only WERR Warning error 0 1 read-only F0DATA0 F0DATA0 Filter 0 data 0 register 0x240 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F0DATA1 F0DATA1 Filter 0 data 1 register 0x244 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F10DATA0 F10DATA0 Filter 10 data 0 register 0x290 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F10DATA1 F10DATA1 Filter 10 data 1 register 0x294 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F11DATA0 F11DATA0 Filter 11 data 0 register 0x298 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F11DATA1 F11DATA1 Filter 11 data 1 register 0x29C 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F12DATA0 F12DATA0 Filter 12 data 0 register 0x2A0 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F12DATA1 F12DATA1 Filter 12 data 1 register 0x2A4 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F13DATA0 F13DATA0 Filter 13 data 0 register 0x2A8 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F13DATA1 F13DATA1 Filter 13 data 1 register 0x2AC 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F14DATA0 F14DATA0 Filter 14 data 0 register 0x2B0 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F14DATA1 F14DATA1 Filter 14 data 1 register 0x2B4 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F15DATA0 F15DATA0 Filter 15 data 0 register 0x2B8 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F15DATA1 F15DATA1 Filter 15 data 1 register 0x2BC 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F16DATA0 F16DATA0 Filter 16 data 0 register 0x2C0 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F16DATA1 F16DATA1 Filter 16 data 1 register 0x2C4 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F17DATA0 F17DATA0 Filter 17 data 0 register 0x2C8 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F17DATA1 F17DATA1 Filter 17 data 1 register 0x2CC 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F18DATA0 F18DATA0 Filter 18 data 0 register 0x2D0 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F18DATA1 F18DATA1 Filter 18 data 1 register 0x2D4 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F19DATA0 F19DATA0 Filter 19 data 0 register 0x2D8 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F19DATA1 F19DATA1 Filter 19 data 1 register 0x2DC 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F1DATA0 F1DATA0 Filter 1 data 0 register 0x248 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F1DATA1 F1DATA1 Filter 1 data 1 register 0x24C 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F20DATA0 F20DATA0 Filter 20 data 0 register 0x2E0 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F20DATA1 F20DATA1 Filter 20 data 1 register 0x2E4 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F21DATA0 F21DATA0 Filter 21 data 0 register 0x2E8 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F21DATA1 F21DATA1 Filter 21 data 1 register 0x2EC 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F22DATA0 F22DATA0 Filter 22 data 0 register 0x2F0 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F22DATA1 F22DATA1 Filter 22 data 1 register 0x2F4 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F23DATA0 F23DATA0 Filter 23 data 0 register 0x2F8 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F23DATA1 F23DATA1 Filter 23 data 1 register 0x2FC 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F24DATA0 F24DATA0 Filter 24 data 0 register 0x300 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F24DATA1 F24DATA1 Filter 24 data 1 register 0x304 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F25DATA0 F25DATA0 Filter 25 data 0 register 0x308 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F25DATA1 F25DATA1 Filter 25 data 1 register 0x30C 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F26DATA0 F26DATA0 Filter 26 data 0 register 0x310 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F26DATA1 F26DATA1 Filter 26 data 1 register 0x314 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F27DATA0 F27DATA0 Filter 27 data 0 register 0x318 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F27DATA1 F27DATA1 Filter 27 data 1 register 0x31C 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F2DATA0 F2DATA0 Filter 2 data 0 register 0x250 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F2DATA1 F2DATA1 Filter 2 data 1 register 0x254 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F3DATA0 F3DATA0 Filter 3 data 0 register 0x258 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F3DATA1 F3DATA1 Filter 3 data 1 register 0x25C 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F4DATA0 F4DATA0 Filter 4 data 0 register 0x260 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F4DATA1 F4DATA1 Filter 4 data 1 register 0x264 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F5DATA0 F5DATA0 Filter 5 data 0 register 0x268 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F5DATA1 F5DATA1 Filter 5 data 1 register 0x26C 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F6DATA0 F6DATA0 Filter 6 data 0 register 0x270 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F6DATA1 F6DATA1 Filter 6 data 1 register 0x274 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F7DATA0 F7DATA0 Filter 7 data 0 register 0x278 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F7DATA1 F7DATA1 Filter 7 data 1 register 0x27C 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F8DATA0 F8DATA0 Filter 8 data 0 register 0x280 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F8DATA1 F8DATA1 Filter 8 data 1 register 0x284 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F9DATA0 F9DATA0 Filter 9 data 0 register 0x288 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F9DATA1 F9DATA1 Filter 9 data 1 register 0x28C 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FAFIFO FAFIFO Filter associated FIFO register 0x214 32 read-write n 0x0 0x0 FAF0 Filter 0 associated with FIFO 0 1 FAF1 Filter 1 associated with FIFO 1 1 FAF10 Filter 10 associated with FIFO 10 1 FAF11 Filter 11 associated with FIFO 11 1 FAF12 Filter 12 associated with FIFO 12 1 FAF13 Filter 13 associated with FIFO 13 1 FAF14 Filter 14 associated with FIFO 14 1 FAF15 Filter 15 associated with FIFO 15 1 FAF16 Filter 16 associated with FIFO 16 1 FAF17 Filter 17 associated with FIFO 17 1 FAF18 Filter 18 associated with FIFO 18 1 FAF19 Filter 19 associated with FIFO 19 1 FAF2 Filter 2 associated with FIFO 2 1 FAF20 Filter 20 associated with FIFO 20 1 FAF21 Filter 21 associated with FIFO 21 1 FAF22 Filter 22 associated with FIFO 22 1 FAF23 Filter 23 associated with FIFO 23 1 FAF24 Filter 24 associated with FIFO 24 1 FAF25 Filter 25 associated with FIFO 25 1 FAF26 Filter 26 associated with FIFO 26 1 FAF27 Filter 27 associated with FIFO 27 1 FAF3 Filter 3 associated with FIFO 3 1 FAF4 Filter 4 associated with FIFO 4 1 FAF5 Filter 5 associated with FIFO 5 1 FAF6 Filter 6 associated with FIFO 6 1 FAF7 Filter 7 associated with FIFO 7 1 FAF8 Filter 8 associated with FIFO 8 1 FAF9 Filter 9 associated with FIFO 9 1 FCTL FCTL Filter control register 0x200 32 read-write n 0x0 0x0 FLD Filter lock disable 0 1 HBC1F Header bank of CAN1 filter 8 6 FMCFG FMCFG Filter mode configuration register 0x204 32 read-write n 0x0 0x0 FMOD0 Filter mode 0 1 FMOD1 Filter mode 1 1 FMOD10 Filter mode 10 1 FMOD11 Filter mode 11 1 FMOD12 Filter mode 12 1 FMOD13 Filter mode 13 1 FMOD14 Filter mode 14 1 FMOD15 Filter mode 15 1 FMOD16 Filter mode 16 1 FMOD17 Filter mode 17 1 FMOD18 Filter mode 18 1 FMOD19 Filter mode 19 1 FMOD2 Filter mode 2 1 FMOD20 Filter mode 20 1 FMOD21 Filter mode 21 1 FMOD22 Filter mode 22 1 FMOD23 Filter mode 23 1 FMOD24 Filter mode 24 1 FMOD25 Filter mode 25 1 FMOD26 Filter mode 26 1 FMOD27 Filter mode 27 1 FMOD3 Filter mode 3 1 FMOD4 Filter mode 4 1 FMOD5 Filter mode 5 1 FMOD6 Filter mode 6 1 FMOD7 Filter mode 7 1 FMOD8 Filter mode 8 1 FMOD9 Filter mode 9 1 FSCFG FSCFG Filter scale configuration register 0x20C 32 read-write n 0x0 0x0 FS0 Filter scale configuration 0 1 FS1 Filter scale configuration 1 1 FS10 Filter scale configuration 10 1 FS11 Filter scale configuration 11 1 FS12 Filter scale configuration 12 1 FS13 Filter scale configuration 13 1 FS14 Filter scale configuration 14 1 FS15 Filter scale configuration 15 1 FS16 Filter scale configuration 16 1 FS17 Filter scale configuration 17 1 FS18 Filter scale configuration 18 1 FS19 Filter scale configuration 19 1 FS2 Filter scale configuration 2 1 FS20 Filter scale configuration 20 1 FS21 Filter scale configuration 21 1 FS22 Filter scale configuration 22 1 FS23 Filter scale configuration 23 1 FS24 Filter scale configuration 24 1 FS25 Filter scale configuration 25 1 FS26 Filter scale configuration 26 1 FS27 Filter scale configuration 27 1 FS3 Filter scale configuration 3 1 FS4 Filter scale configuration 4 1 FS5 Filter scale configuration 5 1 FS6 Filter scale configuration 6 1 FS7 Filter scale configuration 7 1 FS8 Filter scale configuration 8 1 FS9 Filter scale configuration 9 1 FW FW Filter working register 0x21C 32 read-write n 0x0 0x0 FW0 Filter working 0 1 FW1 Filter working 1 1 FW10 Filter working 10 1 FW11 Filter working 11 1 FW12 Filter working 12 1 FW13 Filter working 13 1 FW14 Filter working 14 1 FW15 Filter working 15 1 FW16 Filter working 16 1 FW17 Filter working 17 1 FW18 Filter working 18 1 FW19 Filter working 19 1 FW2 Filter working 2 1 FW20 Filter working 20 1 FW21 Filter working 21 1 FW22 Filter working 22 1 FW23 Filter working 23 1 FW24 Filter working 24 1 FW25 Filter working 25 1 FW26 Filter working 26 1 FW27 Filter working 27 1 FW3 Filter working 3 1 FW4 Filter working 4 1 FW5 Filter working 5 1 FW6 Filter working 6 1 FW7 Filter working 7 1 FW8 Filter working 8 1 FW9 Filter working 9 1 INTEN INTEN Interrupt enable register 0x14 32 read-write n 0x0 0x0 BOIE Bus-off interrupt enable 10 1 ERRIE Error interrupt enable 15 1 ERRNIE Error number interrupt enable 11 1 PERRIE Passive error interrupt enable 9 1 RFFIE0 Receive FIFO0 full interrupt enable 2 1 RFFIE1 Receive FIFO1 full interrupt enable 5 1 RFNEIE0 Receive FIFO0 not empty interrupt enable 1 1 RFNEIE1 Receive FIFO1 not empty interrupt enable 4 1 RFOIE0 Receive FIFO0 overfull interrupt enable 3 1 RFOIE1 Receive FIFO1 overfull interrupt enable 6 1 SLPWIE Sleep working interrupt enable 17 1 TMEIE Transmit mailbox empty interrupt enable 0 1 WERRIE Warning error interrupt enable 8 1 WIE Wakeup interrupt enable 16 1 RFIFO0 RFIFO0 Receive message FIFO0 register 0xC 32 read-write n 0x0 0x0 RFD0 Receive FIFO0 dequeue 5 1 read-write RFF0 Receive FIFO0 full 3 1 read-write RFL0 Receive FIFO0 length 0 2 read-only RFO0 Receive FIFO0 overfull 4 1 read-write RFIFO1 RFIFO1 Receive message FIFO1 register 0x10 32 read-write n 0x0 0x0 RFD1 Receive FIFO1 dequeue 5 1 read-write RFF1 Receive FIFO1 full 3 1 read-write RFL1 Receive FIFO1 length 0 2 read-only RFO1 Receive FIFO1 overfull 4 1 read-write RFIFOMDATA00 RFIFOMDATA00 Receive FIFO0 mailbox data0 register 0x1B8 32 read-only n 0x0 0x0 DB0 Data byte 0 0 8 DB1 Data byte 1 8 8 DB2 Data byte 2 16 8 DB3 Data byte 3 24 8 RFIFOMDATA01 RFIFOMDATA01 Receive FIFO1 mailbox data0 register 0x1C8 32 read-only n 0x0 0x0 DB0 Data byte 0 0 8 DB1 Data byte 1 8 8 DB2 Data byte 2 16 8 DB3 Data byte 3 24 8 RFIFOMDATA10 RFIFOMDATA10 Receive FIFO0 mailbox data1 register 0x1BC 32 read-only n 0x0 0x0 DB4 Data byte 4 0 8 DB5 Data byte 5 8 8 DB6 Data byte 6 16 8 DB7 Data byte 7 24 8 RFIFOMDATA11 RFIFOMDATA11 Receive FIFO1 mailbox data1 register 0x1CC 32 read-only n 0x0 0x0 DB4 Data byte 4 0 8 DB5 Data byte 5 8 8 DB6 Data byte 6 16 8 DB7 Data byte 7 24 8 RFIFOMI0 RFIFOMI0 Receive FIFO mailbox identifier register 0x1B0 32 read-only n 0x0 0x0 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 SFID_EFID The frame identifier 21 11 RFIFOMI1 RFIFOMI1 Receive FIFO1 mailbox identifier register 0x1C0 32 read-only n 0x0 0x0 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 SFID_EFID The frame identifier 21 11 RFIFOMP0 RFIFOMP0 Receive FIFO0 mailbox property register 0x1B4 32 read-only n 0x0 0x0 DLENC Data length code 0 4 FI Filtering index 8 8 TS Time stamp 16 16 RFIFOMP1 RFIFOMP1 Receive FIFO1 mailbox property register 0x1C4 32 read-only n 0x0 0x0 DLENC Data length code 0 4 FI Filtering index 8 8 TS Time stamp 16 16 STAT STAT Status register 0x4 32 read-write n 0x0 0x0 ERRIF Error interrupt flag 2 1 read-write IWS Initial working state 0 1 read-only LASTRX Last sample value of RX pin 10 1 read-only RS Receiving state 9 1 read-only RXL RX level 11 1 read-only SLPIF Status change interrupt flag of sleep working mode entering 4 1 read-write SLPWS Sleep working state 1 1 read-only TS Transmitting state 8 1 read-only WUIF Status change interrupt flag of wakeup from sleep working mode 3 1 read-write TMDATA00 TMDATA00 Transmit mailbox data0 register 0x188 32 read-write n 0x0 0x0 DB0 Data byte 0 0 8 DB1 Data byte 1 8 8 DB2 Data byte 2 16 8 DB3 Data byte 3 24 8 TMDATA01 TMDATA01 Transmit mailbox data0 register 0x198 32 read-write n 0x0 0x0 DB0 Data byte 0 0 8 DB1 Data byte 1 8 8 DB2 Data byte 2 16 8 DB3 Data byte 3 24 8 TMDATA02 TMDATA02 Transmit mailbox data0 register 0x1A8 32 read-write n 0x0 0x0 DB0 Data byte 0 0 8 DB1 Data byte 1 8 8 DB2 Data byte 2 16 8 DB3 Data byte 3 24 8 TMDATA10 TMDATA10 Transmit mailbox data1 register 0x18C 32 read-write n 0x0 0x0 DB4 Data byte 4 0 8 DB5 Data byte 5 8 8 DB6 Data byte 6 16 8 DB7 Data byte 7 24 8 TMDATA11 TMDATA11 Transmit mailbox data1 register 0x19C 32 read-write n 0x0 0x0 DB4 Data byte 4 0 8 DB5 Data byte 5 8 8 DB6 Data byte 6 16 8 DB7 Data byte 7 24 8 TMDATA12 TMDATA12 Transmit mailbox data1 register 0x1AC 32 read-write n 0x0 0x0 DB4 Data byte 4 0 8 DB5 Data byte 5 8 8 DB6 Data byte 6 16 8 DB7 Data byte 7 24 8 TMI0 TMI0 Transmit mailbox identifier register 0 0x180 32 read-write n 0x0 0x0 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 SFID_EFID The frame identifier 21 11 TEN Transmit enable 0 1 TMI1 TMI1 Transmit mailbox identifier register 1 0x190 32 read-write n 0x0 0x0 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 SFID_EFID The frame identifier 21 11 TEN Transmit enable 0 1 TMI2 TMI2 Transmit mailbox identifier register 2 0x1A0 32 read-write n 0x0 0x0 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 SFID_EFID The frame identifier 21 11 TEN Transmit enable 0 1 TMP0 TMP0 Transmit mailbox property register 0 0x184 32 read-write n 0x0 0x0 DLENC Data length code 0 4 TS Time stamp 16 16 TSEN Time stamp enable 8 1 TMP1 TMP1 Transmit mailbox property register 1 0x194 32 read-write n 0x0 0x0 DLENC Data length code 0 4 TS Time stamp 16 16 TSEN Time stamp enable 8 1 TMP2 TMP2 Transmit mailbox property register 2 0x1A4 32 read-write n 0x0 0x0 DLENC Data length code 0 4 TS Time stamp 16 16 TSEN Time stamp enable 8 1 TSTAT TSTAT Transmit status register 0x8 32 read-write n 0x0 0x0 MAL0 Mailbox 0 arbitration lost 2 1 read-write MAL1 Mailbox 1 arbitration lost 10 1 read-write MAL2 Mailbox 2 arbitration lost 18 1 read-write MST0 Mailbox 0 stop transmitting 7 1 read-write MST1 Mailbox 1 stop transmitting 15 1 read-write MST2 Mailbox 2 stop transmitting 23 1 read-write MTE0 Mailbox 0 transmit error 3 1 read-write MTE1 Mailbox 1 transmit error 11 1 read-write MTE2 Mailbox 2 transmit error 19 1 read-write MTF0 Mailbox 0 transmit finished 0 1 read-write MTF1 Mailbox 1 transmit finished 8 1 read-write MTF2 Mailbox 2 transmit finished 16 1 read-write MTFNERR0 Mailbox 0 transmit finished and no error 1 1 read-write MTFNERR1 Mailbox 1 transmit finished and no error 9 1 read-write MTFNERR2 Mailbox 2 transmit finished and no error 17 1 read-write NUM number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty 24 2 read-only TME0 Transmit mailbox 0 empty 26 1 read-only TME1 Transmit mailbox 1 empty 27 1 read-only TME2 Transmit mailbox 2 empty 28 1 read-only TMLS0 Transmit mailbox 0 last sending in transmit FIFO 29 1 read-only TMLS1 Transmit mailbox 1 last sending in transmit FIFO 30 1 read-only TMLS2 Transmit mailbox 2 last sending in transmit FIFO 31 1 read-only CAN1 Controller area network CAN 0x0 0x0 0x400 registers n CAN1_TX 63 CAN1_RX0 64 CAN1_RX1 65 CAN1_EWMC 66 BT BT Bit timing register 0x1C 32 read-write n 0x0 0x0 BS1 Bit segment 1 16 4 BS2 Bit segment 2 20 3 BUADPSC Baud rate prescaler 0 10 LCMOD Loopback communication mode 30 1 SCMOD Silent communication mode 31 1 SJW Resynchronization jump width 24 2 CTL CTL Control register 0x0 32 read-write n 0x0 0x0 ABOR Automatic bus-off recovery 6 1 ARD Automatic retransmission disable 4 1 AWU Automatic wakeup 5 1 DFZ Debug freeze 16 1 IWMOD Initial working mode 0 1 RFOD Receive FIFO overwrite disable 3 1 SLPWMOD Sleep working mode 1 1 SWRST Software reset 15 1 TFO Transmit FIFO order 2 1 TTC Time-triggered communication 7 1 ERR ERR Error register 0x18 32 read-write n 0x0 0x0 BOERR Bus-off error 2 1 read-only ERRN Error number 4 3 read-write PERR Passive error 1 1 read-only RECNT Receive Error Count defined by the CAN standard 24 8 read-only TECNT Transmit Error Count defined by the CAN standard 16 8 read-only WERR Warning error 0 1 read-only F0DATA0 F0DATA0 Filter 0 data 0 register 0x240 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F0DATA1 F0DATA1 Filter 0 data 1 register 0x244 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F10DATA0 F10DATA0 Filter 10 data 0 register 0x290 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F10DATA1 F10DATA1 Filter 10 data 1 register 0x294 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F11DATA0 F11DATA0 Filter 11 data 0 register 0x298 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F11DATA1 F11DATA1 Filter 11 data 1 register 0x29C 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F12DATA0 F12DATA0 Filter 12 data 0 register 0x2A0 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F12DATA1 F12DATA1 Filter 12 data 1 register 0x2A4 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F13DATA0 F13DATA0 Filter 13 data 0 register 0x2A8 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F13DATA1 F13DATA1 Filter 13 data 1 register 0x2AC 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F14DATA0 F14DATA0 Filter 14 data 0 register 0x2B0 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F14DATA1 F14DATA1 Filter 14 data 1 register 0x2B4 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F15DATA0 F15DATA0 Filter 15 data 0 register 0x2B8 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F15DATA1 F15DATA1 Filter 15 data 1 register 0x2BC 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F16DATA0 F16DATA0 Filter 16 data 0 register 0x2C0 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F16DATA1 F16DATA1 Filter 16 data 1 register 0x2C4 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F17DATA0 F17DATA0 Filter 17 data 0 register 0x2C8 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F17DATA1 F17DATA1 Filter 17 data 1 register 0x2CC 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F18DATA0 F18DATA0 Filter 18 data 0 register 0x2D0 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F18DATA1 F18DATA1 Filter 18 data 1 register 0x2D4 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F19DATA0 F19DATA0 Filter 19 data 0 register 0x2D8 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F19DATA1 F19DATA1 Filter 19 data 1 register 0x2DC 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F1DATA0 F1DATA0 Filter 1 data 0 register 0x248 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F1DATA1 F1DATA1 Filter 1 data 1 register 0x24C 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F20DATA0 F20DATA0 Filter 20 data 0 register 0x2E0 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F20DATA1 F20DATA1 Filter 20 data 1 register 0x2E4 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F21DATA0 F21DATA0 Filter 21 data 0 register 0x2E8 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F21DATA1 F21DATA1 Filter 21 data 1 register 0x2EC 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F22DATA0 F22DATA0 Filter 22 data 0 register 0x2F0 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F22DATA1 F22DATA1 Filter 22 data 1 register 0x2F4 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F23DATA0 F23DATA0 Filter 23 data 0 register 0x2F8 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F23DATA1 F23DATA1 Filter 23 data 1 register 0x2FC 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F24DATA0 F24DATA0 Filter 24 data 0 register 0x300 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F24DATA1 F24DATA1 Filter 24 data 1 register 0x304 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F25DATA0 F25DATA0 Filter 25 data 0 register 0x308 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F25DATA1 F25DATA1 Filter 25 data 1 register 0x30C 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F26DATA0 F26DATA0 Filter 26 data 0 register 0x310 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F26DATA1 F26DATA1 Filter 26 data 1 register 0x314 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F27DATA0 F27DATA0 Filter 27 data 0 register 0x318 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F27DATA1 F27DATA1 Filter 27 data 1 register 0x31C 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F2DATA0 F2DATA0 Filter 2 data 0 register 0x250 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F2DATA1 F2DATA1 Filter 2 data 1 register 0x254 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F3DATA0 F3DATA0 Filter 3 data 0 register 0x258 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F3DATA1 F3DATA1 Filter 3 data 1 register 0x25C 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F4DATA0 F4DATA0 Filter 4 data 0 register 0x260 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F4DATA1 F4DATA1 Filter 4 data 1 register 0x264 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F5DATA0 F5DATA0 Filter 5 data 0 register 0x268 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F5DATA1 F5DATA1 Filter 5 data 1 register 0x26C 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F6DATA0 F6DATA0 Filter 6 data 0 register 0x270 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F6DATA1 F6DATA1 Filter 6 data 1 register 0x274 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F7DATA0 F7DATA0 Filter 7 data 0 register 0x278 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F7DATA1 F7DATA1 Filter 7 data 1 register 0x27C 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F8DATA0 F8DATA0 Filter 8 data 0 register 0x280 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F8DATA1 F8DATA1 Filter 8 data 1 register 0x284 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F9DATA0 F9DATA0 Filter 9 data 0 register 0x288 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 F9DATA1 F9DATA1 Filter 9 data 1 register 0x28C 32 read-write n 0x0 0x0 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD2 Filter bits 2 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD3 Filter bits 3 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FAFIFO FAFIFO Filter associated FIFO register 0x214 32 read-write n 0x0 0x0 FAF0 Filter 0 associated with FIFO 0 1 FAF1 Filter 1 associated with FIFO 1 1 FAF10 Filter 10 associated with FIFO 10 1 FAF11 Filter 11 associated with FIFO 11 1 FAF12 Filter 12 associated with FIFO 12 1 FAF13 Filter 13 associated with FIFO 13 1 FAF14 Filter 14 associated with FIFO 14 1 FAF15 Filter 15 associated with FIFO 15 1 FAF16 Filter 16 associated with FIFO 16 1 FAF17 Filter 17 associated with FIFO 17 1 FAF18 Filter 18 associated with FIFO 18 1 FAF19 Filter 19 associated with FIFO 19 1 FAF2 Filter 2 associated with FIFO 2 1 FAF20 Filter 20 associated with FIFO 20 1 FAF21 Filter 21 associated with FIFO 21 1 FAF22 Filter 22 associated with FIFO 22 1 FAF23 Filter 23 associated with FIFO 23 1 FAF24 Filter 24 associated with FIFO 24 1 FAF25 Filter 25 associated with FIFO 25 1 FAF26 Filter 26 associated with FIFO 26 1 FAF27 Filter 27 associated with FIFO 27 1 FAF3 Filter 3 associated with FIFO 3 1 FAF4 Filter 4 associated with FIFO 4 1 FAF5 Filter 5 associated with FIFO 5 1 FAF6 Filter 6 associated with FIFO 6 1 FAF7 Filter 7 associated with FIFO 7 1 FAF8 Filter 8 associated with FIFO 8 1 FAF9 Filter 9 associated with FIFO 9 1 FCTL FCTL Filter control register 0x200 32 read-write n 0x0 0x0 FLD Filter lock disable 0 1 HBC1F Header bank of CAN1 filter 8 6 FMCFG FMCFG Filter mode configuration register 0x204 32 read-write n 0x0 0x0 FMOD0 Filter mode 0 1 FMOD1 Filter mode 1 1 FMOD10 Filter mode 10 1 FMOD11 Filter mode 11 1 FMOD12 Filter mode 12 1 FMOD13 Filter mode 13 1 FMOD14 Filter mode 14 1 FMOD15 Filter mode 15 1 FMOD16 Filter mode 16 1 FMOD17 Filter mode 17 1 FMOD18 Filter mode 18 1 FMOD19 Filter mode 19 1 FMOD2 Filter mode 2 1 FMOD20 Filter mode 20 1 FMOD21 Filter mode 21 1 FMOD22 Filter mode 22 1 FMOD23 Filter mode 23 1 FMOD24 Filter mode 24 1 FMOD25 Filter mode 25 1 FMOD26 Filter mode 26 1 FMOD27 Filter mode 27 1 FMOD3 Filter mode 3 1 FMOD4 Filter mode 4 1 FMOD5 Filter mode 5 1 FMOD6 Filter mode 6 1 FMOD7 Filter mode 7 1 FMOD8 Filter mode 8 1 FMOD9 Filter mode 9 1 FSCFG FSCFG Filter scale configuration register 0x20C 32 read-write n 0x0 0x0 FS0 Filter scale configuration 0 1 FS1 Filter scale configuration 1 1 FS10 Filter scale configuration 10 1 FS11 Filter scale configuration 11 1 FS12 Filter scale configuration 12 1 FS13 Filter scale configuration 13 1 FS14 Filter scale configuration 14 1 FS15 Filter scale configuration 15 1 FS16 Filter scale configuration 16 1 FS17 Filter scale configuration 17 1 FS18 Filter scale configuration 18 1 FS19 Filter scale configuration 19 1 FS2 Filter scale configuration 2 1 FS20 Filter scale configuration 20 1 FS21 Filter scale configuration 21 1 FS22 Filter scale configuration 22 1 FS23 Filter scale configuration 23 1 FS24 Filter scale configuration 24 1 FS25 Filter scale configuration 25 1 FS26 Filter scale configuration 26 1 FS27 Filter scale configuration 27 1 FS3 Filter scale configuration 3 1 FS4 Filter scale configuration 4 1 FS5 Filter scale configuration 5 1 FS6 Filter scale configuration 6 1 FS7 Filter scale configuration 7 1 FS8 Filter scale configuration 8 1 FS9 Filter scale configuration 9 1 FW FW Filter working register 0x21C 32 read-write n 0x0 0x0 FW0 Filter working 0 1 FW1 Filter working 1 1 FW10 Filter working 10 1 FW11 Filter working 11 1 FW12 Filter working 12 1 FW13 Filter working 13 1 FW14 Filter working 14 1 FW15 Filter working 15 1 FW16 Filter working 16 1 FW17 Filter working 17 1 FW18 Filter working 18 1 FW19 Filter working 19 1 FW2 Filter working 2 1 FW20 Filter working 20 1 FW21 Filter working 21 1 FW22 Filter working 22 1 FW23 Filter working 23 1 FW24 Filter working 24 1 FW25 Filter working 25 1 FW26 Filter working 26 1 FW27 Filter working 27 1 FW3 Filter working 3 1 FW4 Filter working 4 1 FW5 Filter working 5 1 FW6 Filter working 6 1 FW7 Filter working 7 1 FW8 Filter working 8 1 FW9 Filter working 9 1 INTEN INTEN Interrupt enable register 0x14 32 read-write n 0x0 0x0 BOIE Bus-off interrupt enable 10 1 ERRIE Error interrupt enable 15 1 ERRNIE Error number interrupt enable 11 1 PERRIE Passive error interrupt enable 9 1 RFFIE0 Receive FIFO0 full interrupt enable 2 1 RFFIE1 Receive FIFO1 full interrupt enable 5 1 RFNEIE0 Receive FIFO0 not empty interrupt enable 1 1 RFNEIE1 Receive FIFO1 not empty interrupt enable 4 1 RFOIE0 Receive FIFO0 overfull interrupt enable 3 1 RFOIE1 Receive FIFO1 overfull interrupt enable 6 1 SLPWIE Sleep working interrupt enable 17 1 TMEIE Transmit mailbox empty interrupt enable 0 1 WERRIE Warning error interrupt enable 8 1 WIE Wakeup interrupt enable 16 1 RFIFO0 RFIFO0 Receive message FIFO0 register 0xC 32 read-write n 0x0 0x0 RFD0 Receive FIFO0 dequeue 5 1 read-write RFF0 Receive FIFO0 full 3 1 read-write RFL0 Receive FIFO0 length 0 2 read-only RFO0 Receive FIFO0 overfull 4 1 read-write RFIFO1 RFIFO1 Receive message FIFO1 register 0x10 32 read-write n 0x0 0x0 RFD1 Receive FIFO1 dequeue 5 1 read-write RFF1 Receive FIFO1 full 3 1 read-write RFL1 Receive FIFO1 length 0 2 read-only RFO1 Receive FIFO1 overfull 4 1 read-write RFIFOMDATA00 RFIFOMDATA00 Receive FIFO0 mailbox data0 register 0x1B8 32 read-only n 0x0 0x0 DB0 Data byte 0 0 8 DB1 Data byte 1 8 8 DB2 Data byte 2 16 8 DB3 Data byte 3 24 8 RFIFOMDATA01 RFIFOMDATA01 Receive FIFO1 mailbox data0 register 0x1C8 32 read-only n 0x0 0x0 DB0 Data byte 0 0 8 DB1 Data byte 1 8 8 DB2 Data byte 2 16 8 DB3 Data byte 3 24 8 RFIFOMDATA10 RFIFOMDATA10 Receive FIFO0 mailbox data1 register 0x1BC 32 read-only n 0x0 0x0 DB4 Data byte 4 0 8 DB5 Data byte 5 8 8 DB6 Data byte 6 16 8 DB7 Data byte 7 24 8 RFIFOMDATA11 RFIFOMDATA11 Receive FIFO1 mailbox data1 register 0x1CC 32 read-only n 0x0 0x0 DB4 Data byte 4 0 8 DB5 Data byte 5 8 8 DB6 Data byte 6 16 8 DB7 Data byte 7 24 8 RFIFOMI0 RFIFOMI0 Receive FIFO mailbox identifier register 0x1B0 32 read-only n 0x0 0x0 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 SFID_EFID The frame identifier 21 11 RFIFOMI1 RFIFOMI1 Receive FIFO1 mailbox identifier register 0x1C0 32 read-only n 0x0 0x0 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 SFID_EFID The frame identifier 21 11 RFIFOMP0 RFIFOMP0 Receive FIFO0 mailbox property register 0x1B4 32 read-only n 0x0 0x0 DLENC Data length code 0 4 FI Filtering index 8 8 TS Time stamp 16 16 RFIFOMP1 RFIFOMP1 Receive FIFO1 mailbox property register 0x1C4 32 read-only n 0x0 0x0 DLENC Data length code 0 4 FI Filtering index 8 8 TS Time stamp 16 16 STAT STAT Status register 0x4 32 read-write n 0x0 0x0 ERRIF Error interrupt flag 2 1 read-write IWS Initial working state 0 1 read-only LASTRX Last sample value of RX pin 10 1 read-only RS Receiving state 9 1 read-only RXL RX level 11 1 read-only SLPIF Status change interrupt flag of sleep working mode entering 4 1 read-write SLPWS Sleep working state 1 1 read-only TS Transmitting state 8 1 read-only WUIF Status change interrupt flag of wakeup from sleep working mode 3 1 read-write TMDATA00 TMDATA00 Transmit mailbox data0 register 0x188 32 read-write n 0x0 0x0 DB0 Data byte 0 0 8 DB1 Data byte 1 8 8 DB2 Data byte 2 16 8 DB3 Data byte 3 24 8 TMDATA01 TMDATA01 Transmit mailbox data0 register 0x198 32 read-write n 0x0 0x0 DB0 Data byte 0 0 8 DB1 Data byte 1 8 8 DB2 Data byte 2 16 8 DB3 Data byte 3 24 8 TMDATA02 TMDATA02 Transmit mailbox data0 register 0x1A8 32 read-write n 0x0 0x0 DB0 Data byte 0 0 8 DB1 Data byte 1 8 8 DB2 Data byte 2 16 8 DB3 Data byte 3 24 8 TMDATA10 TMDATA10 Transmit mailbox data1 register 0x18C 32 read-write n 0x0 0x0 DB4 Data byte 4 0 8 DB5 Data byte 5 8 8 DB6 Data byte 6 16 8 DB7 Data byte 7 24 8 TMDATA11 TMDATA11 Transmit mailbox data1 register 0x19C 32 read-write n 0x0 0x0 DB4 Data byte 4 0 8 DB5 Data byte 5 8 8 DB6 Data byte 6 16 8 DB7 Data byte 7 24 8 TMDATA12 TMDATA12 Transmit mailbox data1 register 0x1AC 32 read-write n 0x0 0x0 DB4 Data byte 4 0 8 DB5 Data byte 5 8 8 DB6 Data byte 6 16 8 DB7 Data byte 7 24 8 TMI0 TMI0 Transmit mailbox identifier register 0 0x180 32 read-write n 0x0 0x0 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 SFID_EFID The frame identifier 21 11 TEN Transmit enable 0 1 TMI1 TMI1 Transmit mailbox identifier register 1 0x190 32 read-write n 0x0 0x0 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 SFID_EFID The frame identifier 21 11 TEN Transmit enable 0 1 TMI2 TMI2 Transmit mailbox identifier register 2 0x1A0 32 read-write n 0x0 0x0 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 SFID_EFID The frame identifier 21 11 TEN Transmit enable 0 1 TMP0 TMP0 Transmit mailbox property register 0 0x184 32 read-write n 0x0 0x0 DLENC Data length code 0 4 TS Time stamp 16 16 TSEN Time stamp enable 8 1 TMP1 TMP1 Transmit mailbox property register 1 0x194 32 read-write n 0x0 0x0 DLENC Data length code 0 4 TS Time stamp 16 16 TSEN Time stamp enable 8 1 TMP2 TMP2 Transmit mailbox property register 2 0x1A4 32 read-write n 0x0 0x0 DLENC Data length code 0 4 TS Time stamp 16 16 TSEN Time stamp enable 8 1 TSTAT TSTAT Transmit status register 0x8 32 read-write n 0x0 0x0 MAL0 Mailbox 0 arbitration lost 2 1 read-write MAL1 Mailbox 1 arbitration lost 10 1 read-write MAL2 Mailbox 2 arbitration lost 18 1 read-write MST0 Mailbox 0 stop transmitting 7 1 read-write MST1 Mailbox 1 stop transmitting 15 1 read-write MST2 Mailbox 2 stop transmitting 23 1 read-write MTE0 Mailbox 0 transmit error 3 1 read-write MTE1 Mailbox 1 transmit error 11 1 read-write MTE2 Mailbox 2 transmit error 19 1 read-write MTF0 Mailbox 0 transmit finished 0 1 read-write MTF1 Mailbox 1 transmit finished 8 1 read-write MTF2 Mailbox 2 transmit finished 16 1 read-write MTFNERR0 Mailbox 0 transmit finished and no error 1 1 read-write MTFNERR1 Mailbox 1 transmit finished and no error 9 1 read-write MTFNERR2 Mailbox 2 transmit finished and no error 17 1 read-write NUM number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty 24 2 read-only TME0 Transmit mailbox 0 empty 26 1 read-only TME1 Transmit mailbox 1 empty 27 1 read-only TME2 Transmit mailbox 2 empty 28 1 read-only TMLS0 Transmit mailbox 0 last sending in transmit FIFO 29 1 read-only TMLS1 Transmit mailbox 1 last sending in transmit FIFO 30 1 read-only TMLS2 Transmit mailbox 2 last sending in transmit FIFO 31 1 read-only CRC cyclic redundancy check calculation unit CRC 0x0 0x0 0x400 registers n CTL CTL Control register 0x8 32 read-write n 0x0 0x0 RST reset bit 0 1 DATA DATA Data register 0x0 32 read-write n 0x0 0x0 DATA CRC calculation result bits 0 32 FDATA FDATA Free data register 0x4 32 read-write n 0x0 0x0 FDATA Free Data Register bits 0 8 CTC Clock trim controller CTC 0x0 0x0 0x400 registers n RCU_CTC 5 CTL0 CTL0 Control register 0 0x0 32 read-write n 0x0 0x0 AUTOTRIM Hardware automatically trim mode 6 1 CKOKIE Clock trim ok interrupt enable 0 1 CKWARNIE Clock trim warning interrupt enable 1 1 CNTEN CTC counter enable 5 1 EREFIE EREFIF interrupt enable 3 1 ERRIE Error interrupt enable 2 1 SWREFPUL Software reference source sync pulse 7 1 TRIMVALUE IRC48M trim value 8 6 CTL1 CTL1 Control register 1 0x4 32 read-write n 0x0 0x0 CKLIM Clock trim base limit value 16 8 REFPOL Reference signal source polarity 31 1 REFPSC Reference signal source prescaler 24 3 REFSEL Reference signal source selection 28 2 RLVALUE CTC counter reload value 0 16 USBSOFSEL SOF signal selection 30 1 INTC INTC Interrupt clear register 0xC 32 read-write n 0x0 0x0 CKOKIC CKOKIF interrupt clear bit 0 1 CKWARNIC CKWARNIF interrupt clear bit 1 1 EREFIC EREFIF interrupt clear bit 3 1 ERRIC ERRIF interrupt clear bit 2 1 STAT STAT Status register 0x8 32 read-only n 0x0 0x0 CKERR Clock trim error bit 8 1 CKOKIF Clock trim OK interrupt flag 0 1 CKWARNIF Clock trim warning interrupt flag 1 1 EREFIF Expect reference interrupt flag 3 1 ERRIF Error interrupt flag 2 1 REFCAP CTC counter capture when reference sync pulse 16 16 REFDIR CTC trim counter direction when reference sync pulse 15 1 REFMISS Reference sync pulse miss 9 1 TRIMERR Trim value error bit 10 1 DAC Digital-to-analog converter DAC 0x0 0x0 0x400 registers n TIMER5_DAC 54 CTL CTL control register 0x0 32 read-write n 0x0 0x0 DBOFF0 DAC0 output buffer turn off 1 1 DBOFF1 DAC1 output buffer turn off 17 1 DDMAEN0 DAC0 DMA enable 12 1 DDMAEN1 DAC1 DMA enable 28 1 DDUDRIE0 DAC0 DMA Underrun Interrupt enable 13 1 DDUDRIE1 DAC1 DMA Underrun Interrupt enable 29 1 DEN0 DAC0 enable 0 1 DEN1 DAC1 enable 16 1 DTEN0 DAC0 trigger enable 2 1 DTEN1 DAC1 trigger enable 18 1 DTSEL0 DAC0 trigger selection 3 3 DTSEL1 DAC1 trigger selection 19 3 DWBW0 DAC0 noise wave bit width 8 4 DWBW1 DAC1 noise wave bit width 24 4 DWM0 DAC0 noise wave mode 6 2 DWM1 DAC1 noise wave mode 22 2 DAC0_DO DAC0_DO DAC0 data output register 0x2C 32 read-only n 0x0 0x0 DAC0_DO DAC0 data output 0 12 DAC0_L12DH DAC0_L12DH DAC0 12-bit left-aligned data holding register 0xC 32 read-write n 0x0 0x0 DAC0_DH DAC0 12-bit left-aligned data 4 12 DAC0_R12DH DAC0_R12DH DAC0 12-bit right-aligned data holding register 0x8 32 read-write n 0x0 0x0 DAC0_DH DAC0 12-bit right-aligned data 0 12 DAC0_R8DH DAC0_R8DH DAC0 8-bit right aligned data holding register 0x10 32 read-write n 0x0 0x0 DAC0_DH DAC0 8-bit right-aligned data 0 8 DAC1_DO DAC1_DO DAC1 data output register 0x30 32 read-only n 0x0 0x0 DAC1_DO DAC1 data output 0 12 DAC1_L12DH DAC1_L12DH DAC1 12-bit left aligned data holding register 0x18 32 read-write n 0x0 0x0 DAC1_DH DAC1 12-bit left-aligned data 4 12 DAC1_R12DH DAC1_R12DH DAC1 12-bit right-aligned data holding register 0x14 32 read-write n 0x0 0x0 DAC1_DH DAC1 12-bit right-aligned data 0 12 DAC1_R8DH DAC1_R8DH DAC1 8-bit right aligned data holding register 0x1C 32 read-write n 0x0 0x0 DAC1_DH DAC1 8-bit right-aligned data 0 8 DACC_L12DH DACC_L12DH DAC concurrent mode 12-bit left aligned data holding register 0x24 32 read-write n 0x0 0x0 DAC0_DH DAC0 12-bit left-aligned data 4 12 DAC1_DH DAC1 12-bit left-aligned data 20 12 DACC_R12DH DACC_R12DH DAC concurrent mode 12-bit right-aligned data holding register 0x20 32 read-write n 0x0 0x0 DAC0_DH DAC0 12-bit right-aligned data 0 12 DAC1_DH DAC1 12-bit right-aligned data 16 12 DACC_R8DH DACC_R8DH DAC concurrent mode 8-bit right aligned data holding register 0x28 32 read-write n 0x0 0x0 DAC0_DH DAC0 8-bit right-aligned data 0 8 DAC1_DH DAC1 8-bit right-aligned data 8 8 STAT STAT status register 0x34 32 read-write n 0x0 0x0 DDUDR0 DAC0 DMA underrun flag 13 1 DDUDR1 DAC1 DMA underrun flag 29 1 SWT SWT software trigger register 0x4 32 write-only n 0x0 0x0 SWTR0 DAC0 software trigger 0 1 SWTR1 DAC1 software trigger 1 1 DBG Debug support DBG 0x0 0x0 0x400 registers n CTL0 CTL0 Control register 0 0x4 32 read-write n 0x0 0x0 DSLP_HOLD Deep-sleep mode hold register 1 1 SLP_HOLD Sleep mode hold register 0 1 STB_HOLD Standby mode hold register 2 1 TRACE_IOEN Trace pin allocation enable 5 1 TRACE_MODE Trace pin allocation mode 6 2 CTL1 CTL1 Control register 1 0x8 32 read-write n 0x0 0x0 CAN0_HOLD CAN0 hold register 25 1 CAN1_HOLD CAN1 hold register 26 1 FWDGT_HOLD FWDGT hold register 12 1 I2C0_HOLD I2C0 hold register 21 1 I2C1_HOLD I2C1 hold register 22 1 I2C2_HOLD I2C2 hold register 23 1 RTC_HOLD RTC hold register 10 1 TIMER11_HOLD TIMER 11 hold register 6 1 TIMER12_HOLD TIMER 12 hold register 7 1 TIMER13_HOLD TIMER 13 hold register 8 1 TIMER1_HOLD TIMER 1 hold register 0 1 TIMER2_HOLD TIMER 2 hold register 1 1 TIMER3_HOLD TIMER 3 hold register 2 1 TIMER4_HOLD TIMER 4 hold register 3 1 TIMER5_HOLD TIMER 5 hold register 4 1 TIMER6_HOLD TIMER 6 hold register 5 1 WWDGT_HOLD WWDGT hold register 11 1 CTL2 CTL2 Control register 2 0xC 32 read-write n 0x0 0x0 TIMER0_HOLD TIMER 0 hold register 0 1 TIMER10_HOLD TIMER 10 hold register 18 1 TIMER7_HOLD TIMER 7 hold register 1 1 TIMER8_HOLD TIMER 8 hold register 16 1 TIMER9_HOLD TIMER 9 hold register 17 1 ID ID ID code register 0x0 32 read-only n 0x0 0x0 ID_CODE DBG ID code register 0 32 DCI Digital Camera Interface DCI 0x0 0x0 0x400 registers n DCI 78 CTL CTL Control register 0x0 32 read-write n 0x0 0x0 CAP Capture Enable 0 1 CKS Clock Polarity Selection 5 1 DCIEN DCI Enable 14 1 DCIF Digital camera interface format 10 2 ESM Embedded Synchronous Mode 4 1 FR Frame rate 8 2 HPS Horizontal Polarity Selection 6 1 JM JPEG mode 3 1 SNAP Snapshot mode 1 1 VPS Vertical Polarity Selection 7 1 WDEN Window Enable 2 1 CWSPOS CWSPOS Cropping window start position register 0x20 32 read-write n 0x0 0x0 WHSP Window Horizontal Start Position 0 14 WVSP Window Vertical Start Position 16 13 CWSZ CWSZ Cropping window size register 0x24 32 read-write n 0x0 0x0 WHSZ Window Horizontal Size 0 14 WVSZ Window Vertical Size 16 14 DATA DATA DATA register 0x28 32 read-only n 0x0 0x0 DT0 Pixel Data 0 0 8 DT1 Pixel Data 1 8 8 DT2 Pixel Data 2 16 8 DT3 Pixel Data 3 24 8 INTC INTC Interrupt flag clear register 0x14 32 write-only n 0x0 0x0 EFFC Clear End of Frame Flag 0 1 ELFC End of Line Flag Clear 4 1 ESEFC Clear embedded synchronous Error Flag 2 1 OVRFC Clear FIFO Overrun Flag 1 1 VSFC Vsync flag clear 3 1 INTEN INTEN Interrupt enable register 0xC 32 read-write n 0x0 0x0 EFIE End of Frame Interrupt Enable 0 1 ELIE End of Line Interrupt Enable 4 1 ESEIE Embedded Synchronous Error Interrupt Enable 2 1 OVRIE FIFO Overrun Interrupt Enable 1 1 VSIE Vsync Interrupt Enable 3 1 INTF INTF Interrupt flag register 0x10 32 read-only n 0x0 0x0 EFIF End of Frame Interrupt Flag 0 1 ELIF End of Line Interrupt Flag 4 1 ESEIF Embedded Synchronous Error Interrupt Flag 2 1 OVRIF FIFO Overrun Interrupt Flag 1 1 VSIF Vsync Interrupt Flag 3 1 SC SC Synchronization codes register 0x18 32 read-write n 0x0 0x0 FE Frame End Code in Embedded Synchronous Mode 24 8 FS Frame Start Code in Embedded Synchronous Mode 0 8 LE Line End Code in Embedded Synchronous Mode 16 8 LS Line Start Code in Embedded Synchronous Mode 8 8 SCUMSK SCUMSK Synchronization codes unmask register 0x1C 32 read-write n 0x0 0x0 FEM Frame End Code unMask Bits in Embedded Synchronous Mode 24 8 FSM Frame Start Code unMask Bits in Embedded Synchronous Mode 0 8 LEM Line End Code unMask Bits in Embedded Synchronous Mode 16 8 LSM Line Start Code unMask Bits in Embedded Synchronous Mode 8 8 STAT0 STAT0 Status register 0 0x4 32 read-only n 0x0 0x0 FV FIFO Valid 2 1 HS HS line status 0 1 VS VS line status 1 1 STAT1 STAT1 Status register 1 0x8 32 read-only n 0x0 0x0 EFF End of Frame Flag 0 1 ELF End of Line Flag 4 1 ESEF Embedded Synchronous Error Flag 2 1 OVRF FIFO Overrun Flag 1 1 VSF Vsync Flag 3 1 DMA0 DMA controller DMA 0x0 0x0 0x400 registers n DMA0_Channel0 11 DMA0_Channel1 12 DMA0_Channel2 13 DMA0_Channel3 14 DMA0_Channel4 15 DMA0_Channel5 16 DMA0_Channel6 17 DMA0_Channel7 47 CH0CNT CH0CNT Channel 0 counter register 0x14 32 read-write n 0x0 0x0 CNT Transfer counter 0 16 CH0CTL CH0CTL Channel 0 control register 0x10 32 read-write n 0x0 0x0 CHEN Channel enable 0 1 CMEN Circulation mode enable 8 1 FTFIE Enable bit for full transfer finish interrupt 4 1 HTFIE Enable bit for half transfer finish interrupt 3 1 MBS Memory buffer select 19 1 MBURST Transfer burst type of memory 23 2 MNAGA Next address generation algorithm of memory 10 1 MWIDTH Transfer width of memory 13 2 PAIF Peripheral address increment fixed 15 1 PBURST Transfer burst type of peripheral 21 2 PERIEN Peripheral enable 25 3 PNAGA Next address generation algorithm of peripheral 9 1 PRIO Priority level 16 2 PWIDTH Transfer width of peripheral 11 2 SBMEN Switch-buffer mode enable 18 1 SDEIE Enable bit for single data mode exception interrupt 1 1 TAEIE Enable bit for tranfer access error interrupt 2 1 TFCS Transfer flow controller select 5 1 TM Transfer mode 6 2 CH0FCTL CH0FCTL Channel 0 FIFO control register 0x24 32 read-write n 0x0 0x0 FCCV FIFO counter critical value 0 2 FCNT FIFO counter 3 3 FEEIE Enable bit for FIFO error and exception interrupt 7 1 MDMEN Multi-data mode enable 2 1 CH0M0ADDR CH0M0ADDR Channel 0 memory 0 base address register 0x1C 32 read-write n 0x0 0x0 M0ADDR Memory 0 base address 0 32 CH0M1ADDR CH0M1ADDR Channel 0 memory 1 base address register 0x20 32 read-write n 0x0 0x0 M1ADDR Memory 1 base address 0 32 CH0PADDR CH0PADDR Channel 0 peripheral base address register 0x18 32 read-write n 0x0 0x0 PADDR Peripheral base address 0 32 CH1CNT CH1CNT Channel 1 counter register 0x2C 32 read-write n 0x0 0x0 CNT Transfer counter 0 16 CH1CTL CH1CTL Channel 1 control register 0x28 32 read-write n 0x0 0x0 CHEN Channel enable 0 1 CMEN Circulation mode enable 8 1 FTFIE Enable bit for full transfer finish interrupt 4 1 HTFIE Enable bit for half transfer finish interrupt 3 1 MBS Memory buffer select 19 1 MBURST Transfer burst type of memory 23 2 MNAGA Next address generation algorithm of memory 10 1 MWIDTH Transfer width of memory 13 2 PAIF Peripheral address increment fixed 15 1 PBURST Transfer burst type of peripheral 21 2 PERIEN Peripheral enable 25 3 PNAGA Next address generation algorithm of peripheral 9 1 PRIO Priority level 16 2 PWIDTH Transfer width of peripheral 11 2 SBMEN Switch-buffer mode enable 18 1 SDEIE Enable bit for single data mode exception interrupt 1 1 TAEIE Enable bit for tranfer access error interrupt 2 1 TFCS Transfer flow controller select 5 1 TM Transfer mode 6 2 CH1FCTL CH1FCTL Channel 1 FIFO control register 0x3C 32 read-write n 0x0 0x0 FCCV FIFO counter critical value 0 2 FCNT FIFO counter 3 3 FEEIE Enable bit for FIFO error and exception interrupt 7 1 MDMEN Multi-data mode enable 2 1 CH1M0ADDR CH1M0ADDR Channel 1 memory 0 base address register 0x34 32 read-write n 0x0 0x0 M0ADDR Memory 0 base address 0 32 CH1M1ADDR CH1M1ADDR Channel 1 memory 1 base address register 0x38 32 read-write n 0x0 0x0 M1ADDR Memory 1 base address 0 32 CH1PADDR CH1PADDR Channel 1 peripheral base address register 0x30 32 read-write n 0x0 0x0 PADDR Peripheral base address 0 32 CH2CNT CH2CNT Channel 2 counter register 0x44 32 read-write n 0x0 0x0 CNT Transfer counter 0 16 CH2CTL CH2CTL Channel 2 control register 0x40 32 read-write n 0x0 0x0 CHEN Channel enable 0 1 CMEN Circulation mode enable 8 1 FTFIE Enable bit for full transfer finish interrupt 4 1 HTFIE Enable bit for half transfer finish interrupt 3 1 MBS Memory buffer select 19 1 MBURST Transfer burst type of memory 23 2 MNAGA Next address generation algorithm of memory 10 1 MWIDTH Transfer width of memory 13 2 PAIF Peripheral address increment fixed 15 1 PBURST Transfer burst type of peripheral 21 2 PERIEN Peripheral enable 25 3 PNAGA Next address generation algorithm of peripheral 9 1 PRIO Priority level 16 2 PWIDTH Transfer width of peripheral 11 2 SBMEN Switch-buffer mode enable 18 1 SDEIE Enable bit for single data mode exception interrupt 1 1 TAEIE Enable bit for tranfer access error interrupt 2 1 TFCS Transfer flow controller select 5 1 TM Transfer mode 6 2 CH2FCTL CH2FCTL Channel 2 FIFO control register 0x54 32 read-write n 0x0 0x0 FCCV FIFO counter critical value 0 2 FCNT FIFO counter 3 3 FEEIE Enable bit for FIFO error and exception interrupt 7 1 MDMEN Multi-data mode enable 2 1 CH2M0ADDR CH2M0ADDR Channel 2 memory 0 base address register 0x4C 32 read-write n 0x0 0x0 M0ADDR Memory 0 base address 0 32 CH2M1ADDR CH2M1ADDR Channel 2 memory 1 base address register 0x50 32 read-write n 0x0 0x0 M1ADDR Memory 1 base address 0 32 CH2PADDR CH2PADDR Channel 2 peripheral base address register 0x48 32 read-write n 0x0 0x0 PADDR Peripheral base address 0 32 CH3CNT CH3CNT Channel 3 counter register 0x5C 32 read-write n 0x0 0x0 CNT Transfer counter 0 16 CH3CTL CH3CTL Channel 3 control register 0x58 32 read-write n 0x0 0x0 CHEN Channel enable 0 1 CMEN Circulation mode enable 8 1 FTFIE Enable bit for full transfer finish interrupt 4 1 HTFIE Enable bit for half transfer finish interrupt 3 1 MBS Memory buffer select 19 1 MBURST Transfer burst type of memory 23 2 MNAGA Next address generation algorithm of memory 10 1 MWIDTH Transfer width of memory 13 2 PAIF Peripheral address increment fixed 15 1 PBURST Transfer burst type of peripheral 21 2 PERIEN Peripheral enable 25 3 PNAGA Next address generation algorithm of peripheral 9 1 PRIO Priority level 16 2 PWIDTH Transfer width of peripheral 11 2 SBMEN Switch-buffer mode enable 18 1 SDEIE Enable bit for single data mode exception interrupt 1 1 TAEIE Enable bit for tranfer access error interrupt 2 1 TFCS Transfer flow controller select 5 1 TM Transfer mode 6 2 CH3FCTL CH3FCTL Channel 3 FIFO control register 0x6C 32 read-write n 0x0 0x0 FCCV FIFO counter critical value 0 2 FCNT FIFO counter 3 3 FEEIE Enable bit for FIFO error and exception interrupt 7 1 MDMEN Multi-data mode enable 2 1 CH3M0ADDR CH3M0ADDR Channel 3 memory 0 base address register 0x64 32 read-write n 0x0 0x0 M0ADDR Memory 0 base address 0 32 CH3M1ADDR CH3M1ADDR Channel 3 memory 1 base address register 0x68 32 read-write n 0x0 0x0 M1ADDR Memory 1 base address 0 32 CH3PADDR CH3PADDR Channel 3 peripheral base address register 0x60 32 read-write n 0x0 0x0 PADDR Peripheral base address 0 32 CH4CNT CH4CNT Channel 4 counter register 0x74 32 read-write n 0x0 0x0 CNT Transfer counter 0 16 CH4CTL CH4CTL Channel 4 control register 0x70 32 read-write n 0x0 0x0 CHEN Channel enable 0 1 CMEN Circulation mode enable 8 1 FTFIE Enable bit for full transfer finish interrupt 4 1 HTFIE Enable bit for half transfer finish interrupt 3 1 MBS Memory buffer select 19 1 MBURST Transfer burst type of memory 23 2 MNAGA Next address generation algorithm of memory 10 1 MWIDTH Transfer width of memory 13 2 PAIF Peripheral address increment fixed 15 1 PBURST Transfer burst type of peripheral 21 2 PERIEN Peripheral enable 25 3 PNAGA Next address generation algorithm of peripheral 9 1 PRIO Priority level 16 2 PWIDTH Transfer width of peripheral 11 2 SBMEN Switch-buffer mode enable 18 1 SDEIE Enable bit for single data mode exception interrupt 1 1 TAEIE Enable bit for tranfer access error interrupt 2 1 TFCS Transfer flow controller select 5 1 TM Transfer mode 6 2 CH4FCTL CH4FCTL Channel 4 FIFO control register 0x84 32 read-write n 0x0 0x0 FCCV FIFO counter critical value 0 2 FCNT FIFO counter 3 3 FEEIE Enable bit for FIFO error and exception interrupt 7 1 MDMEN Multi-data mode enable 2 1 CH4M0ADDR CH4M0ADDR Channel 4 memory 0 base address register 0x7C 32 read-write n 0x0 0x0 M0ADDR Memory 0 base address 0 32 CH4M1ADDR CH4M1ADDR Channel 4 memory 1 base address register 0x80 32 read-write n 0x0 0x0 M1ADDR Memory 1 base address 0 32 CH4PADDR CH4PADDR Channel 4 peripheral base address register 0x78 32 read-write n 0x0 0x0 PADDR Peripheral base address 0 32 CH5CNT CH5CNT Channel 5 counter register 0x8C 32 read-write n 0x0 0x0 CNT Transfer counter 0 16 CH5CTL CH5CTL Channel 5 control register 0x88 32 read-write n 0x0 0x0 CHEN Channel enable 0 1 CMEN Circulation mode enable 8 1 FTFIE Enable bit for full transfer finish interrupt 4 1 HTFIE Enable bit for half transfer finish interrupt 3 1 MBS Memory buffer select 19 1 MBURST Transfer burst type of memory 23 2 MNAGA Next address generation algorithm of memory 10 1 MWIDTH Transfer width of memory 13 2 PAIF Peripheral address increment fixed 15 1 PBURST Transfer burst type of peripheral 21 2 PERIEN Peripheral enable 25 3 PNAGA Next address generation algorithm of peripheral 9 1 PRIO Priority level 16 2 PWIDTH Transfer width of peripheral 11 2 SBMEN Switch-buffer mode enable 18 1 SDEIE Enable bit for single data mode exception interrupt 1 1 TAEIE Enable bit for tranfer access error interrupt 2 1 TFCS Transfer flow controller select 5 1 TM Transfer mode 6 2 CH5FCTL CH5FCTL Channel 5 FIFO control register 0x9C 32 read-write n 0x0 0x0 FCCV FIFO counter critical value 0 2 FCNT FIFO counter 3 3 FEEIE Enable bit for FIFO error and exception interrupt 7 1 MDMEN Multi-data mode enable 2 1 CH5M0ADDR CH5M0ADDR Channel 5 memory 0 base address register 0x94 32 read-write n 0x0 0x0 M0ADDR Memory 0 base address 0 32 CH5M1ADDR CH5M1ADDR Channel 5 memory 1 base address register 0x98 32 read-write n 0x0 0x0 M1ADDR Memory 1 base address 0 32 CH5PADDR CH5PADDR Channel 5 peripheral base address register 0x90 32 read-write n 0x0 0x0 PADDR Peripheral base address 0 32 CH6CNT CH6CNT Channel 6 counter register 0xA4 32 read-write n 0x0 0x0 CNT Transfer counter 0 16 CH6CTL CH6CTL Channel 6 control register 0xA0 32 read-write n 0x0 0x0 CHEN Channel enable 0 1 CMEN Circulation mode enable 8 1 FTFIE Enable bit for full transfer finish interrupt 4 1 HTFIE Enable bit for half transfer finish interrupt 3 1 MBS Memory buffer select 19 1 MBURST Transfer burst type of memory 23 2 MNAGA Next address generation algorithm of memory 10 1 MWIDTH Transfer width of memory 13 2 PAIF Peripheral address increment fixed 15 1 PBURST Transfer burst type of peripheral 21 2 PERIEN Peripheral enable 25 3 PNAGA Next address generation algorithm of peripheral 9 1 PRIO Priority level 16 2 PWIDTH Transfer width of peripheral 11 2 SBMEN Switch-buffer mode enable 18 1 SDEIE Enable bit for single data mode exception interrupt 1 1 TAEIE Enable bit for tranfer access error interrupt 2 1 TFCS Transfer flow controller select 5 1 TM Transfer mode 6 2 CH6FCTL CH6FCTL Channel 6 FIFO control register 0xB4 32 read-write n 0x0 0x0 FCCV FIFO counter critical value 0 2 FCNT FIFO counter 3 3 FEEIE Enable bit for FIFO error and exception interrupt 7 1 MDMEN Multi-data mode enable 2 1 CH6M0ADDR CH6M0ADDR Channel 6 memory 0 base address register 0xAC 32 read-write n 0x0 0x0 M0ADDR Memory 0 base address 0 32 CH6M1ADDR CH6M1ADDR Channel 6 memory 1 base address register 0xB0 32 read-write n 0x0 0x0 M1ADDR Memory 1 base address 0 32 CH6PADDR CH6PADDR Channel 6 peripheral base address register 0xA8 32 read-write n 0x0 0x0 PADDR Peripheral base address 0 32 CH7CNT CH7CNT Channel 7 counter register 0xBC 32 read-write n 0x0 0x0 CNT Transfer counter 0 16 CH7CTL CH7CTL Channel 7 control register 0xB8 32 read-write n 0x0 0x0 CHEN Channel enable 0 1 CMEN Circulation mode enable 8 1 FTFIE Enable bit for full transfer finish interrupt 4 1 HTFIE Enable bit for half transfer finish interrupt 3 1 MBS Memory buffer select 19 1 MBURST Transfer burst type of memory 23 2 MNAGA Next address generation algorithm of memory 10 1 MWIDTH Transfer width of memory 13 2 PAIF Peripheral address increment fixed 15 1 PBURST Transfer burst type of peripheral 21 2 PERIEN Peripheral enable 25 3 PNAGA Next address generation algorithm of peripheral 9 1 PRIO Priority level 16 2 PWIDTH Transfer width of peripheral 11 2 SBMEN Switch-buffer mode enable 18 1 SDEIE Enable bit for single data mode exception interrupt 1 1 TAEIE Enable bit for tranfer access error interrupt 2 1 TFCS Transfer flow controller select 5 1 TM Transfer mode 6 2 CH7FCTL CH7FCTL Channel 7 FIFO control register 0xCC 32 read-write n 0x0 0x0 FCCV FIFO counter critical value 0 2 FCNT FIFO counter 3 3 FEEIE Enable bit for FIFO error and exception interrupt 7 1 MDMEN Multi-data mode enable 2 1 CH7M0ADDR CH7M0ADDR Channel 7 memory 0 base address register 0xC4 32 read-write n 0x0 0x0 M0ADDR Memory 0 base address 0 32 CH7M1ADDR CH7M1ADDR Channel 7 memory 1 base address register 0xC8 32 read-write n 0x0 0x0 M1ADDR Memory 1 base address 0 32 CH7PADDR CH7PADDR Channel 7 peripheral base address register 0xC0 32 read-write n 0x0 0x0 PADDR Peripheral base address 0 32 INTC0 INTC0 Interrupt flag clear register 0 0x8 32 write-only n 0x0 0x0 FEEIFC0 Clear bit for FIFO error and exception of channel 0 0 1 FEEIFC1 Clear bit for FIFO error and exception of channel 1 6 1 FEEIFC2 Clear bit for FIFO error and exception of channel 2 16 1 FEEIFC3 Clear bit for FIFO error and exception of channel 3 22 1 FTFIFC0 Clear bit for Full transfer finish flag of channel 0 5 1 FTFIFC1 Clear bit for Full transfer finish flag of channel 1 11 1 FTFIFC2 Clear bit for Full transfer finish flag of channel 2 21 1 FTFIFC3 Clear bit for Full transfer finish flag of channel 3 27 1 HTFIFC0 Clear bit for half transfer finish flag of channel 0 4 1 HTFIFC1 Clear bit for half transfer finish flag of channel 1 10 1 HTFIFC2 Clear bit for half transfer finish flag of channel 2 20 1 HTFIFC3 Clear bit for half transfer finish flag of channel 3 26 1 SDEIFC0 Clear bit for single data mode exception of channel 0 2 1 SDEIFC1 Clear bit for single data mode exception of channel 1 8 1 SDEIFC2 Clear bit for single data mode exception of channel 2 18 1 SDEIFC3 Clear bit for single data mode exception of channel 3 24 1 TAEIFC0 Clear bit for transfer access error flag of channel 0 3 1 TAEIFC1 Clear bit for transfer access error flag of channel 1 9 1 TAEIFC2 Clear bit for transfer access error flag of channel 2 19 1 TAEIFC3 Clear bit for transfer access error flag of channel 3 25 1 INTC1 INTC1 Interrupt flag clear register 1 0xC 32 write-only n 0x0 0x0 FEEIFC4 Clear bit for FIFO error and exception of channel 4 0 1 FEEIFC5 Clear bit for FIFO error and exception of channel 5 6 1 FEEIFC6 Clear bit for FIFO error and exception of channel 6 16 1 FEEIFC7 Clear bit for FIFO error and exception of channel 7 22 1 FTFIFC4 Clear bit for Full transfer finish flag of channel 4 5 1 FTFIFC5 Clear bit for Full transfer finish flag of channel 5 11 1 FTFIFC6 Clear bit for Full transfer finish flag of channel 6 21 1 FTFIFC7 Clear bit for Full transfer finish flag of channel 7 27 1 HTFIFC4 Clear bit for half transfer finish flag of channel 4 4 1 HTFIFC5 Clear bit for half transfer finish flag of channel 5 10 1 HTFIFC6 Clear bit for half transfer finish flag of channel 6 20 1 HTFIFC7 Clear bit for half transfer finish flag of channel 7 26 1 SDEIFC4 Clear bit for single data mode exception of channel 4 2 1 SDEIFC5 Clear bit for single data mode exception of channel 5 8 1 SDEIFC6 Clear bit for single data mode exception of channel 6 18 1 SDEIFC7 Clear bit for single data mode exception of channel 7 24 1 TAEIFC4 Clear bit for transfer access error flag of channel 4 3 1 TAEIFC5 Clear bit for transfer access error flag of channel 5 9 1 TAEIFC6 Clear bit for transfer access error flag of channel 6 19 1 TAEIFC7 Clear bit for transfer access error flag of channel 7 25 1 INTF0 INTF0 Interrupt flag register 0 0x0 32 read-only n 0x0 0x0 FEEIF0 FIFO error and exception of channel 0 0 1 FEEIF1 FIFO error and exception of channel 1 6 1 FEEIF2 FIFO error and exception of channel 2 16 1 FEEIF3 FIFO error and exception of channel 3 22 1 FTFIF0 Full Transfer finish flag of channel 0 5 1 FTFIF1 Full Transfer finish flag of channel 1 11 1 FTFIF2 Full Transfer finish flag of channel 2 21 1 FTFIF3 Full Transfer finish flag of channel 3 27 1 HTFIF0 Half transfer finish flag of channel 0 4 1 HTFIF1 Half transfer finish flag of channel 1 10 1 HTFIF2 Half transfer finish flag of channel 2 20 1 HTFIF3 Half transfer finish flag of channel 3 26 1 SDEIF0 Single data mode exception of channel 0 2 1 SDEIF1 Single data mode exception of channel 1 8 1 SDEIF2 Single data mode exception of channel 2 18 1 SDEIF3 Single data mode exception of channel 3 24 1 TAEIF0 Transfer access error flag of channel 0 3 1 TAEIF1 Transfer access error flag of channel 1 9 1 TAEIF2 Transfer access error flag of channel 2 19 1 TAEIF3 Transfer access error flag of channel 3 25 1 INTF1 INTF1 Interrupt flag register 1 0x4 32 read-only n 0x0 0x0 FEEIF4 FIFO error and exception of channel 4 0 1 FEEIF5 FIFO error and exception of channel 5 6 1 FEEIF6 FIFO error and exception of channel 6 16 1 FEEIF7 FIFO error and exception of channel 7 22 1 FTFIF4 Full Transfer finish flag of channel 4 5 1 FTFIF5 Full Transfer finish flag of channel 5 11 1 FTFIF6 Full Transfer finish flag of channel 6 21 1 FTFIF7 Full Transfer finish flag of channel 7 27 1 HTFIF4 Half transfer finish flag of channel 4 4 1 HTFIF5 Half transfer finish flag of channel 5 10 1 HTFIF6 Half transfer finish flag of channel 6 20 1 HTFIF7 Half transfer finish flag of channel 7 26 1 SDEIF4 Single data mode exception of channel 4 2 1 SDEIF5 Single data mode exception of channel 5 8 1 SDEIF6 Single data mode exception of channel 6 18 1 SDEIF7 Single data mode exception of channel 7 24 1 TAEIF4 Transfer access error flag of channel 4 3 1 TAEIF5 Transfer access error flag of channel 5 9 1 TAEIF6 Transfer access error flag of channel 6 19 1 TAEIF7 Transfer access error flag of channel 7 25 1 DMA1 DMA controller DMA 0x0 0x0 0x400 registers n DMA1_Channel0 56 DMA1_Channel1 57 DMA1_Channel2 58 DMA1_Channel3 59 DMA1_Channel4 60 DMA1_Channel5 68 DMA1_Channel6 69 DMA1_Channel7 70 CH0CNT CH0CNT Channel 0 counter register 0x14 32 read-write n 0x0 0x0 CNT Transfer counter 0 16 CH0CTL CH0CTL Channel 0 control register 0x10 32 read-write n 0x0 0x0 CHEN Channel enable 0 1 CMEN Circulation mode enable 8 1 FTFIE Enable bit for full transfer finish interrupt 4 1 HTFIE Enable bit for half transfer finish interrupt 3 1 MBS Memory buffer select 19 1 MBURST Transfer burst type of memory 23 2 MNAGA Next address generation algorithm of memory 10 1 MWIDTH Transfer width of memory 13 2 PAIF Peripheral address increment fixed 15 1 PBURST Transfer burst type of peripheral 21 2 PERIEN Peripheral enable 25 3 PNAGA Next address generation algorithm of peripheral 9 1 PRIO Priority level 16 2 PWIDTH Transfer width of peripheral 11 2 SBMEN Switch-buffer mode enable 18 1 SDEIE Enable bit for single data mode exception interrupt 1 1 TAEIE Enable bit for tranfer access error interrupt 2 1 TFCS Transfer flow controller select 5 1 TM Transfer mode 6 2 CH0FCTL CH0FCTL Channel 0 FIFO control register 0x24 32 read-write n 0x0 0x0 FCCV FIFO counter critical value 0 2 FCNT FIFO counter 3 3 FEEIE Enable bit for FIFO error and exception interrupt 7 1 MDMEN Multi-data mode enable 2 1 CH0M0ADDR CH0M0ADDR Channel 0 memory 0 base address register 0x1C 32 read-write n 0x0 0x0 M0ADDR Memory 0 base address 0 32 CH0M1ADDR CH0M1ADDR Channel 0 memory 1 base address register 0x20 32 read-write n 0x0 0x0 M1ADDR Memory 1 base address 0 32 CH0PADDR CH0PADDR Channel 0 peripheral base address register 0x18 32 read-write n 0x0 0x0 PADDR Peripheral base address 0 32 CH1CNT CH1CNT Channel 1 counter register 0x2C 32 read-write n 0x0 0x0 CNT Transfer counter 0 16 CH1CTL CH1CTL Channel 1 control register 0x28 32 read-write n 0x0 0x0 CHEN Channel enable 0 1 CMEN Circulation mode enable 8 1 FTFIE Enable bit for full transfer finish interrupt 4 1 HTFIE Enable bit for half transfer finish interrupt 3 1 MBS Memory buffer select 19 1 MBURST Transfer burst type of memory 23 2 MNAGA Next address generation algorithm of memory 10 1 MWIDTH Transfer width of memory 13 2 PAIF Peripheral address increment fixed 15 1 PBURST Transfer burst type of peripheral 21 2 PERIEN Peripheral enable 25 3 PNAGA Next address generation algorithm of peripheral 9 1 PRIO Priority level 16 2 PWIDTH Transfer width of peripheral 11 2 SBMEN Switch-buffer mode enable 18 1 SDEIE Enable bit for single data mode exception interrupt 1 1 TAEIE Enable bit for tranfer access error interrupt 2 1 TFCS Transfer flow controller select 5 1 TM Transfer mode 6 2 CH1FCTL CH1FCTL Channel 1 FIFO control register 0x3C 32 read-write n 0x0 0x0 FCCV FIFO counter critical value 0 2 FCNT FIFO counter 3 3 FEEIE Enable bit for FIFO error and exception interrupt 7 1 MDMEN Multi-data mode enable 2 1 CH1M0ADDR CH1M0ADDR Channel 1 memory 0 base address register 0x34 32 read-write n 0x0 0x0 M0ADDR Memory 0 base address 0 32 CH1M1ADDR CH1M1ADDR Channel 1 memory 1 base address register 0x38 32 read-write n 0x0 0x0 M1ADDR Memory 1 base address 0 32 CH1PADDR CH1PADDR Channel 1 peripheral base address register 0x30 32 read-write n 0x0 0x0 PADDR Peripheral base address 0 32 CH2CNT CH2CNT Channel 2 counter register 0x44 32 read-write n 0x0 0x0 CNT Transfer counter 0 16 CH2CTL CH2CTL Channel 2 control register 0x40 32 read-write n 0x0 0x0 CHEN Channel enable 0 1 CMEN Circulation mode enable 8 1 FTFIE Enable bit for full transfer finish interrupt 4 1 HTFIE Enable bit for half transfer finish interrupt 3 1 MBS Memory buffer select 19 1 MBURST Transfer burst type of memory 23 2 MNAGA Next address generation algorithm of memory 10 1 MWIDTH Transfer width of memory 13 2 PAIF Peripheral address increment fixed 15 1 PBURST Transfer burst type of peripheral 21 2 PERIEN Peripheral enable 25 3 PNAGA Next address generation algorithm of peripheral 9 1 PRIO Priority level 16 2 PWIDTH Transfer width of peripheral 11 2 SBMEN Switch-buffer mode enable 18 1 SDEIE Enable bit for single data mode exception interrupt 1 1 TAEIE Enable bit for tranfer access error interrupt 2 1 TFCS Transfer flow controller select 5 1 TM Transfer mode 6 2 CH2FCTL CH2FCTL Channel 2 FIFO control register 0x54 32 read-write n 0x0 0x0 FCCV FIFO counter critical value 0 2 FCNT FIFO counter 3 3 FEEIE Enable bit for FIFO error and exception interrupt 7 1 MDMEN Multi-data mode enable 2 1 CH2M0ADDR CH2M0ADDR Channel 2 memory 0 base address register 0x4C 32 read-write n 0x0 0x0 M0ADDR Memory 0 base address 0 32 CH2M1ADDR CH2M1ADDR Channel 2 memory 1 base address register 0x50 32 read-write n 0x0 0x0 M1ADDR Memory 1 base address 0 32 CH2PADDR CH2PADDR Channel 2 peripheral base address register 0x48 32 read-write n 0x0 0x0 PADDR Peripheral base address 0 32 CH3CNT CH3CNT Channel 3 counter register 0x5C 32 read-write n 0x0 0x0 CNT Transfer counter 0 16 CH3CTL CH3CTL Channel 3 control register 0x58 32 read-write n 0x0 0x0 CHEN Channel enable 0 1 CMEN Circulation mode enable 8 1 FTFIE Enable bit for full transfer finish interrupt 4 1 HTFIE Enable bit for half transfer finish interrupt 3 1 MBS Memory buffer select 19 1 MBURST Transfer burst type of memory 23 2 MNAGA Next address generation algorithm of memory 10 1 MWIDTH Transfer width of memory 13 2 PAIF Peripheral address increment fixed 15 1 PBURST Transfer burst type of peripheral 21 2 PERIEN Peripheral enable 25 3 PNAGA Next address generation algorithm of peripheral 9 1 PRIO Priority level 16 2 PWIDTH Transfer width of peripheral 11 2 SBMEN Switch-buffer mode enable 18 1 SDEIE Enable bit for single data mode exception interrupt 1 1 TAEIE Enable bit for tranfer access error interrupt 2 1 TFCS Transfer flow controller select 5 1 TM Transfer mode 6 2 CH3FCTL CH3FCTL Channel 3 FIFO control register 0x6C 32 read-write n 0x0 0x0 FCCV FIFO counter critical value 0 2 FCNT FIFO counter 3 3 FEEIE Enable bit for FIFO error and exception interrupt 7 1 MDMEN Multi-data mode enable 2 1 CH3M0ADDR CH3M0ADDR Channel 3 memory 0 base address register 0x64 32 read-write n 0x0 0x0 M0ADDR Memory 0 base address 0 32 CH3M1ADDR CH3M1ADDR Channel 3 memory 1 base address register 0x68 32 read-write n 0x0 0x0 M1ADDR Memory 1 base address 0 32 CH3PADDR CH3PADDR Channel 3 peripheral base address register 0x60 32 read-write n 0x0 0x0 PADDR Peripheral base address 0 32 CH4CNT CH4CNT Channel 4 counter register 0x74 32 read-write n 0x0 0x0 CNT Transfer counter 0 16 CH4CTL CH4CTL Channel 4 control register 0x70 32 read-write n 0x0 0x0 CHEN Channel enable 0 1 CMEN Circulation mode enable 8 1 FTFIE Enable bit for full transfer finish interrupt 4 1 HTFIE Enable bit for half transfer finish interrupt 3 1 MBS Memory buffer select 19 1 MBURST Transfer burst type of memory 23 2 MNAGA Next address generation algorithm of memory 10 1 MWIDTH Transfer width of memory 13 2 PAIF Peripheral address increment fixed 15 1 PBURST Transfer burst type of peripheral 21 2 PERIEN Peripheral enable 25 3 PNAGA Next address generation algorithm of peripheral 9 1 PRIO Priority level 16 2 PWIDTH Transfer width of peripheral 11 2 SBMEN Switch-buffer mode enable 18 1 SDEIE Enable bit for single data mode exception interrupt 1 1 TAEIE Enable bit for tranfer access error interrupt 2 1 TFCS Transfer flow controller select 5 1 TM Transfer mode 6 2 CH4FCTL CH4FCTL Channel 4 FIFO control register 0x84 32 read-write n 0x0 0x0 FCCV FIFO counter critical value 0 2 FCNT FIFO counter 3 3 FEEIE Enable bit for FIFO error and exception interrupt 7 1 MDMEN Multi-data mode enable 2 1 CH4M0ADDR CH4M0ADDR Channel 4 memory 0 base address register 0x7C 32 read-write n 0x0 0x0 M0ADDR Memory 0 base address 0 32 CH4M1ADDR CH4M1ADDR Channel 4 memory 1 base address register 0x80 32 read-write n 0x0 0x0 M1ADDR Memory 1 base address 0 32 CH4PADDR CH4PADDR Channel 4 peripheral base address register 0x78 32 read-write n 0x0 0x0 PADDR Peripheral base address 0 32 CH5CNT CH5CNT Channel 5 counter register 0x8C 32 read-write n 0x0 0x0 CNT Transfer counter 0 16 CH5CTL CH5CTL Channel 5 control register 0x88 32 read-write n 0x0 0x0 CHEN Channel enable 0 1 CMEN Circulation mode enable 8 1 FTFIE Enable bit for full transfer finish interrupt 4 1 HTFIE Enable bit for half transfer finish interrupt 3 1 MBS Memory buffer select 19 1 MBURST Transfer burst type of memory 23 2 MNAGA Next address generation algorithm of memory 10 1 MWIDTH Transfer width of memory 13 2 PAIF Peripheral address increment fixed 15 1 PBURST Transfer burst type of peripheral 21 2 PERIEN Peripheral enable 25 3 PNAGA Next address generation algorithm of peripheral 9 1 PRIO Priority level 16 2 PWIDTH Transfer width of peripheral 11 2 SBMEN Switch-buffer mode enable 18 1 SDEIE Enable bit for single data mode exception interrupt 1 1 TAEIE Enable bit for tranfer access error interrupt 2 1 TFCS Transfer flow controller select 5 1 TM Transfer mode 6 2 CH5FCTL CH5FCTL Channel 5 FIFO control register 0x9C 32 read-write n 0x0 0x0 FCCV FIFO counter critical value 0 2 FCNT FIFO counter 3 3 FEEIE Enable bit for FIFO error and exception interrupt 7 1 MDMEN Multi-data mode enable 2 1 CH5M0ADDR CH5M0ADDR Channel 5 memory 0 base address register 0x94 32 read-write n 0x0 0x0 M0ADDR Memory 0 base address 0 32 CH5M1ADDR CH5M1ADDR Channel 5 memory 1 base address register 0x98 32 read-write n 0x0 0x0 M1ADDR Memory 1 base address 0 32 CH5PADDR CH5PADDR Channel 5 peripheral base address register 0x90 32 read-write n 0x0 0x0 PADDR Peripheral base address 0 32 CH6CNT CH6CNT Channel 6 counter register 0xA4 32 read-write n 0x0 0x0 CNT Transfer counter 0 16 CH6CTL CH6CTL Channel 6 control register 0xA0 32 read-write n 0x0 0x0 CHEN Channel enable 0 1 CMEN Circulation mode enable 8 1 FTFIE Enable bit for full transfer finish interrupt 4 1 HTFIE Enable bit for half transfer finish interrupt 3 1 MBS Memory buffer select 19 1 MBURST Transfer burst type of memory 23 2 MNAGA Next address generation algorithm of memory 10 1 MWIDTH Transfer width of memory 13 2 PAIF Peripheral address increment fixed 15 1 PBURST Transfer burst type of peripheral 21 2 PERIEN Peripheral enable 25 3 PNAGA Next address generation algorithm of peripheral 9 1 PRIO Priority level 16 2 PWIDTH Transfer width of peripheral 11 2 SBMEN Switch-buffer mode enable 18 1 SDEIE Enable bit for single data mode exception interrupt 1 1 TAEIE Enable bit for tranfer access error interrupt 2 1 TFCS Transfer flow controller select 5 1 TM Transfer mode 6 2 CH6FCTL CH6FCTL Channel 6 FIFO control register 0xB4 32 read-write n 0x0 0x0 FCCV FIFO counter critical value 0 2 FCNT FIFO counter 3 3 FEEIE Enable bit for FIFO error and exception interrupt 7 1 MDMEN Multi-data mode enable 2 1 CH6M0ADDR CH6M0ADDR Channel 6 memory 0 base address register 0xAC 32 read-write n 0x0 0x0 M0ADDR Memory 0 base address 0 32 CH6M1ADDR CH6M1ADDR Channel 6 memory 1 base address register 0xB0 32 read-write n 0x0 0x0 M1ADDR Memory 1 base address 0 32 CH6PADDR CH6PADDR Channel 6 peripheral base address register 0xA8 32 read-write n 0x0 0x0 PADDR Peripheral base address 0 32 CH7CNT CH7CNT Channel 7 counter register 0xBC 32 read-write n 0x0 0x0 CNT Transfer counter 0 16 CH7CTL CH7CTL Channel 7 control register 0xB8 32 read-write n 0x0 0x0 CHEN Channel enable 0 1 CMEN Circulation mode enable 8 1 FTFIE Enable bit for full transfer finish interrupt 4 1 HTFIE Enable bit for half transfer finish interrupt 3 1 MBS Memory buffer select 19 1 MBURST Transfer burst type of memory 23 2 MNAGA Next address generation algorithm of memory 10 1 MWIDTH Transfer width of memory 13 2 PAIF Peripheral address increment fixed 15 1 PBURST Transfer burst type of peripheral 21 2 PERIEN Peripheral enable 25 3 PNAGA Next address generation algorithm of peripheral 9 1 PRIO Priority level 16 2 PWIDTH Transfer width of peripheral 11 2 SBMEN Switch-buffer mode enable 18 1 SDEIE Enable bit for single data mode exception interrupt 1 1 TAEIE Enable bit for tranfer access error interrupt 2 1 TFCS Transfer flow controller select 5 1 TM Transfer mode 6 2 CH7FCTL CH7FCTL Channel 7 FIFO control register 0xCC 32 read-write n 0x0 0x0 FCCV FIFO counter critical value 0 2 FCNT FIFO counter 3 3 FEEIE Enable bit for FIFO error and exception interrupt 7 1 MDMEN Multi-data mode enable 2 1 CH7M0ADDR CH7M0ADDR Channel 7 memory 0 base address register 0xC4 32 read-write n 0x0 0x0 M0ADDR Memory 0 base address 0 32 CH7M1ADDR CH7M1ADDR Channel 7 memory 1 base address register 0xC8 32 read-write n 0x0 0x0 M1ADDR Memory 1 base address 0 32 CH7PADDR CH7PADDR Channel 7 peripheral base address register 0xC0 32 read-write n 0x0 0x0 PADDR Peripheral base address 0 32 INTC0 INTC0 Interrupt flag clear register 0 0x8 32 write-only n 0x0 0x0 FEEIFC0 Clear bit for FIFO error and exception of channel 0 0 1 FEEIFC1 Clear bit for FIFO error and exception of channel 1 6 1 FEEIFC2 Clear bit for FIFO error and exception of channel 2 16 1 FEEIFC3 Clear bit for FIFO error and exception of channel 3 22 1 FTFIFC0 Clear bit for Full transfer finish flag of channel 0 5 1 FTFIFC1 Clear bit for Full transfer finish flag of channel 1 11 1 FTFIFC2 Clear bit for Full transfer finish flag of channel 2 21 1 FTFIFC3 Clear bit for Full transfer finish flag of channel 3 27 1 HTFIFC0 Clear bit for half transfer finish flag of channel 0 4 1 HTFIFC1 Clear bit for half transfer finish flag of channel 1 10 1 HTFIFC2 Clear bit for half transfer finish flag of channel 2 20 1 HTFIFC3 Clear bit for half transfer finish flag of channel 3 26 1 SDEIFC0 Clear bit for single data mode exception of channel 0 2 1 SDEIFC1 Clear bit for single data mode exception of channel 1 8 1 SDEIFC2 Clear bit for single data mode exception of channel 2 18 1 SDEIFC3 Clear bit for single data mode exception of channel 3 24 1 TAEIFC0 Clear bit for transfer access error flag of channel 0 3 1 TAEIFC1 Clear bit for transfer access error flag of channel 1 9 1 TAEIFC2 Clear bit for transfer access error flag of channel 2 19 1 TAEIFC3 Clear bit for transfer access error flag of channel 3 25 1 INTC1 INTC1 Interrupt flag clear register 1 0xC 32 write-only n 0x0 0x0 FEEIFC4 Clear bit for FIFO error and exception of channel 4 0 1 FEEIFC5 Clear bit for FIFO error and exception of channel 5 6 1 FEEIFC6 Clear bit for FIFO error and exception of channel 6 16 1 FEEIFC7 Clear bit for FIFO error and exception of channel 7 22 1 FTFIFC4 Clear bit for Full transfer finish flag of channel 4 5 1 FTFIFC5 Clear bit for Full transfer finish flag of channel 5 11 1 FTFIFC6 Clear bit for Full transfer finish flag of channel 6 21 1 FTFIFC7 Clear bit for Full transfer finish flag of channel 7 27 1 HTFIFC4 Clear bit for half transfer finish flag of channel 4 4 1 HTFIFC5 Clear bit for half transfer finish flag of channel 5 10 1 HTFIFC6 Clear bit for half transfer finish flag of channel 6 20 1 HTFIFC7 Clear bit for half transfer finish flag of channel 7 26 1 SDEIFC4 Clear bit for single data mode exception of channel 4 2 1 SDEIFC5 Clear bit for single data mode exception of channel 5 8 1 SDEIFC6 Clear bit for single data mode exception of channel 6 18 1 SDEIFC7 Clear bit for single data mode exception of channel 7 24 1 TAEIFC4 Clear bit for transfer access error flag of channel 4 3 1 TAEIFC5 Clear bit for transfer access error flag of channel 5 9 1 TAEIFC6 Clear bit for transfer access error flag of channel 6 19 1 TAEIFC7 Clear bit for transfer access error flag of channel 7 25 1 INTF0 INTF0 Interrupt flag register 0 0x0 32 read-only n 0x0 0x0 FEEIF0 FIFO error and exception of channel 0 0 1 FEEIF1 FIFO error and exception of channel 1 6 1 FEEIF2 FIFO error and exception of channel 2 16 1 FEEIF3 FIFO error and exception of channel 3 22 1 FTFIF0 Full Transfer finish flag of channel 0 5 1 FTFIF1 Full Transfer finish flag of channel 1 11 1 FTFIF2 Full Transfer finish flag of channel 2 21 1 FTFIF3 Full Transfer finish flag of channel 3 27 1 HTFIF0 Half transfer finish flag of channel 0 4 1 HTFIF1 Half transfer finish flag of channel 1 10 1 HTFIF2 Half transfer finish flag of channel 2 20 1 HTFIF3 Half transfer finish flag of channel 3 26 1 SDEIF0 Single data mode exception of channel 0 2 1 SDEIF1 Single data mode exception of channel 1 8 1 SDEIF2 Single data mode exception of channel 2 18 1 SDEIF3 Single data mode exception of channel 3 24 1 TAEIF0 Transfer access error flag of channel 0 3 1 TAEIF1 Transfer access error flag of channel 1 9 1 TAEIF2 Transfer access error flag of channel 2 19 1 TAEIF3 Transfer access error flag of channel 3 25 1 INTF1 INTF1 Interrupt flag register 1 0x4 32 read-only n 0x0 0x0 FEEIF4 FIFO error and exception of channel 4 0 1 FEEIF5 FIFO error and exception of channel 5 6 1 FEEIF6 FIFO error and exception of channel 6 16 1 FEEIF7 FIFO error and exception of channel 7 22 1 FTFIF4 Full Transfer finish flag of channel 4 5 1 FTFIF5 Full Transfer finish flag of channel 5 11 1 FTFIF6 Full Transfer finish flag of channel 6 21 1 FTFIF7 Full Transfer finish flag of channel 7 27 1 HTFIF4 Half transfer finish flag of channel 4 4 1 HTFIF5 Half transfer finish flag of channel 5 10 1 HTFIF6 Half transfer finish flag of channel 6 20 1 HTFIF7 Half transfer finish flag of channel 7 26 1 SDEIF4 Single data mode exception of channel 4 2 1 SDEIF5 Single data mode exception of channel 5 8 1 SDEIF6 Single data mode exception of channel 6 18 1 SDEIF7 Single data mode exception of channel 7 24 1 TAEIF4 Transfer access error flag of channel 4 3 1 TAEIF5 Transfer access error flag of channel 5 9 1 TAEIF6 Transfer access error flag of channel 6 19 1 TAEIF7 Transfer access error flag of channel 7 25 1 ENET_DMA Ethernet: DMA controller operation ENET 0x0 0x0 0x60 registers n DMA_BCTL DMA_BCTL Ethernet DMA bus control register 0x0 32 read-write n 0x0 0x0 AA Address-aligned 25 1 DAB DMA Arbitration 1 1 DFM Descriptor format mode 7 1 DPSL Descriptor skip length 2 5 FB Fixed burst 16 1 FPBL Four times PGBL mode 24 1 MB Mixed burst 26 1 PGBL Programmable burst length 8 6 RTPR RxDMA and TxDMA transfer priority ratio 14 2 RXDP Rx DMA PGBL 17 6 SWR Software reset 0 1 UIP Use independent PGBL 23 1 DMA_CRBADDR DMA_CRBADDR Ethernet DMA current receive buffer address register 0x54 32 read-only n 0x0 0x0 RBAP receive buffer address pointer 0 32 DMA_CRDADDR DMA_CRDADDR Ethernet DMA current receive descriptor address register 0x4C 32 read-only n 0x0 0x0 RDAP Receive descriptor address pointer 0 32 DMA_CTBADDR DMA_CTBADDR Ethernet DMA current transmit buffer address register 0x50 32 read-only n 0x0 0x0 TBAP Transmit buffer address pointer 0 32 DMA_CTDADDR DMA_CTDADDR DMA current transmit descriptor address register 0x48 32 read-only n 0x0 0x0 TDAP transmit descriptor address pointer 0 32 DMA_CTL DMA_CTL Ethernet DMA control register 0x18 32 read-write n 0x0 0x0 DAFRF Disable flushing of received frames 24 1 DTCERFD Dropping of TCP/IP checksum error frames disable 26 1 FERF Forward error frames 7 1 FTF Flush transmit FIFO 20 1 FUF Forward undersized good frames 6 1 OSF Operate on second frame 2 1 RSFD Receive Store-and-Forward 25 1 RTHC Receive threshold control 3 2 SRE Start/stop receive enable 1 1 STE Start/stop transmission enable 13 1 TSFD Transmit Store-and-Forward 21 1 TTHC Transmit threshold control 14 3 DMA_INTEN DMA_INTEN Ethernet DMA interrupt enable register 0x1C 32 read-write n 0x0 0x0 AIEN Abnormal interrupt summary enable 15 1 ERIEN Early receive interrupt enable 14 1 ETIEN Early transmit interrupt enable 10 1 FBEIEN Fatal bus error interrupt enable 13 1 NIEN Normal interrupt summary enable 16 1 RBUIEN Receive buffer unavailable interrupt enable 7 1 RIEN Receive interrupt enable 6 1 ROIEN Receive overflow interrupt enable 4 1 RPSIEN Receive process stopped interrupt enable 8 1 RWTIEN receive watchdog timeout interrupt enable 9 1 TBUIEN Transmit buffer unavailable interrupt enable 2 1 TIEN Transmit interrupt enable 0 1 TJTIEN Transmit jabber timeout interrupt enable 3 1 TPSIEN Transmit process stopped interrupt enable 1 1 TUIEN Transmit underflow interrupt enable 5 1 DMA_MFBOCNT DMA_MFBOCNT Ethernet DMA missed frame and buffer overflow counter register 0x20 32 read-only n 0x0 0x0 MSFA Missed frames by the application 17 11 MSFC Missed frames by the controller 0 16 DMA_RDTADDR DMA_RDTADDR Ethernet DMA receive descriptor table address register 0xC 32 read-write n 0x0 0x0 SRT Start address of receive table 0 32 DMA_RPEN DMA_RPEN Ethernet DMA receive poll enable register 0x8 32 read-write n 0x0 0x0 RPE Receive poll enable 0 32 DMA_RSWDC DMA_RSWDC Ethernet DMA receive state watchdog counter register 0x24 32 read-write n 0x0 0x0 WDCFRS Watchdog counter for receive status (RS) 0 8 DMA_STAT DMA_STAT Ethernet DMA status register 0x14 32 read-write n 0x0 0x0 AI Abnormal interrupt summary 15 1 read-write EB Error bits status 23 3 read-only ER Early receive status 14 1 read-write ET Early transmit status 10 1 read-write FBE Fatal bus error status 13 1 read-write MSC MSC status 27 1 read-only NI Normal interrupt summary 16 1 read-write RBU Receive buffer unavailable status 7 1 read-write RO Receive overflow status 4 1 read-write RP Receive process state 17 3 read-only RPS Receive process stopped status 8 1 read-write RS Receive status 6 1 read-write RWT Receive watchdog timeout status 9 1 read-write TBU Transmit buffer unavailable status 2 1 read-write TJT Transmit jabber timeout status 3 1 read-write TP Transmit process state 20 3 read-only TPS Transmit process stopped status 1 1 read-write TS Transmit status 0 1 read-write TST Time stamp trigger status 29 1 read-only TU Transmit underflow status 5 1 read-write WUM WUM status 28 1 read-only DMA_TDTADDR DMA_TDTADDR Ethernet DMA transmit descriptor table address register 0x10 32 read-write n 0x0 0x0 STT Start address of transmit table 0 32 DMA_TPEN DMA_TPEN Ethernet DMA transmit poll enable register 0x4 32 read-write n 0x0 0x0 TPE Transmit poll enable 0 32 ENET_MAC Ethernet: media access control ENET 0x0 0x0 0x100 registers n ENET 61 ENET_WKUP 62 MAC_ADDR0H MAC_ADDR0H Ethernet MAC address 0 high register (MAC_ADDR0H) 0x40 32 read-write n 0x0 0x0 ADDR0H MAC address0 high 0 16 read-write MO Always 1 31 1 read-write MAC_ADDR0L MAC_ADDR0L Ethernet MAC address 0 low register 0x44 32 read-write n 0x0 0x0 ADDR0L MAC address0 low 0 32 MAC_ADDR1H MAC_ADDR1H Ethernet MAC address 1 high register (MAC_ADDR1H) 0x48 32 read-write n 0x0 0x0 ADDR1H MAC address1 high 0 16 AFE Address filter enable 31 1 MB Mask byte 24 6 SAF Source address filter 30 1 MAC_ADDR1L MAC_ADDR1L Ethernet MAC address1 low register 0x4C 32 read-write n 0x0 0x0 ADDR1L MAC address1 low 0 32 MAC_ADDR2H MAC_ADDR2H Ethernet MAC address 2 high register (MAC_ADDR2H) 0x50 32 read-write n 0x0 0x0 ADDR2H Ethernet MAC address 2 high register 0 16 AFE Address filter enable 31 1 MB Mask byte 24 6 SAF Source address filter 30 1 MAC_ADDR2L MAC_ADDR2L Ethernet MAC address 2 low register 0x54 32 read-write n 0x0 0x0 ADDR2L MAC address2 low 0 32 MAC_ADDR3H MAC_ADDR3H Ethernet MAC address 3 high register (MAC_ADDR3H) 0x58 32 read-write n 0x0 0x0 ADDR3H MAC address3 high 0 16 AFE Address filter enable 31 1 MB Mask byte 24 6 SAF Source address filter 30 1 MAC_ADDR3L MAC_ADDR3L Ethernet MAC address 3 low register 0x5C 32 read-write n 0x0 0x0 ADDR3L MAC address3 low 0 32 MAC_CFG MAC_CFG Ethernet MAC configuration register (MAC_CFG) 0x0 32 read-write n 0x0 0x0 APCD Automatic pad/CRC drop 7 1 BOL Back-off limit 5 2 CSD Carrier sense disable 16 1 DFC Deferral check 4 1 DPM Duplex mode 11 1 IGBS Inter frame gap bit selection 17 3 IPFCO IP frame checksum offload 10 1 JBD Jabber disable 22 1 LBM Loopback mode 12 1 REN Receiver enable 2 1 ROD Receive own disable 13 1 RTD Retry disable 9 1 SPD Fast Ethernet speed 14 1 TEN Transmitter enable 3 1 TFCD Type Frame CRC Dropping 25 1 WDD Watchdog disable 23 1 MAC_DBG MAC_DBG Ethernet MAC debug register (MAC_DBG) 0x34 32 read-only n 0x0 0x0 MRNI MAC receive state not idle 0 1 MTNI MAC transmit state not idle 16 1 PCS Pause condition status 19 1 RXAFS Rx asynchronous FIFO status 1 2 RXFRS RxFIFO read operation status 5 2 RXFS RxFIFO state 8 2 RXFW RxFIFO is writing 4 1 SOMT Status of MAC transmitter 17 2 TXFF TxFIFO Full flag 25 1 TXFNE TxFIFO not empty flag 24 1 TXFRS TxFIFO read operation status 20 2 TXFW TxFIFO is writing 22 1 MAC_FCTL MAC_FCTL Ethernet MAC flow control register (MAC_FCTL) 0x18 32 read-write n 0x0 0x0 DZQP Disable Zero-quanta pause 7 1 FLCB_BKPA Flow control busy/back pressure activate 0 1 PLTS Pause low threshold 4 2 PTM Pause time 16 16 RFCEN Receive flow control enable 2 1 TFCEN Transmit flow control enable 1 1 UPFDT Unicast pause frame detect 3 1 MAC_FRMF MAC_FRMF Ethernet MAC frame filter register (MAC_FRMF) 0x4 32 read-write n 0x0 0x0 BFRMD Broadcast frames disable 5 1 DAIFLT Destination address inverse filtering 3 1 FAR Frames all receive 31 1 HMF Hash multicast filter 2 1 HPFLT Hash or perfect filter 10 1 HUF Hash unicast filter 1 1 MFD multicast filter disable 4 1 PCFRM Pass control frames 6 2 PM Promiscuous mode 0 1 SAFLT Source address filter 9 1 SAIFLT Source address inverse filtering 8 1 MAC_HLH MAC_HLH Ethernet MAC hash list high register 0x8 32 read-write n 0x0 0x0 HLH Hash list high 0 32 MAC_HLL MAC_HLL Ethernet MAC hash list low register 0xC 32 read-write n 0x0 0x0 HLL Hash list low 0 32 MAC_INTF MAC_INTF Ethernet MAC interrupt flag register (MAC_INTF) 0x38 32 read-only n 0x0 0x0 MSC MSC status 4 1 MSCR MSC receive status 5 1 MSCT MSC transmit status 6 1 TMST Time stamp trigger status 9 1 WUM WUM status 3 1 MAC_INTMSK MAC_INTMSK Ethernet MAC interrupt mask register (MAC_INTMSK) 0x3C 32 read-write n 0x0 0x0 TMSTIM Time stamp trigger interrupt mask 9 1 WUMIM WUM interrupt mask 3 1 MAC_PHY_CTL MAC_PHY_CTL Ethernet MAC PHY control register (MAC_PHY_CTL) 0x10 32 read-write n 0x0 0x0 CLR Clock range 2 3 PA PHY address 11 5 PB PHY busy 0 1 PR PHY register 6 5 PW PHY write 1 1 MAC_PHY_DATA MAC_PHY_DATA Ethernet MAC MII data register (MAC_PHY_DATA) 0x14 32 read-write n 0x0 0x0 PD PHY data 0 16 MAC_RWFF MAC_RWFF Ethernet MAC remote wakeup frame filter register (MAC_RWFF) 0x28 32 read-write n 0x0 0x0 MAC_VLT MAC_VLT Ethernet MAC VLAN tag register (MAC_VLT) 0x1C 32 read-write n 0x0 0x0 VLTC 12-bit VLAN tag comparison 16 1 VLTI VLAN tag identifier (for receive frames) 0 16 MAC_WUM MAC_WUM Ethernet MAC wakeup management register (MAC_WUM) 0x2C 32 read-write n 0x0 0x0 GU Global unicast 9 1 MPEN Magic Packet enable 1 1 MPKR Magic packet received 5 1 PWD Power down 0 1 WFEN Wakeup frame enable 2 1 WUFFRPR Wakeup frame filter register pointer reset 31 1 WUFR Wakeup frame received 6 1 ENET_MAC_FCTH MAC flow control threshold register ENET 0x0 0x0 0x20 registers n MAC_FCTH MAC_FCTH Ethernet MAC flow control threshold register 0x0 32 read-write n 0x0 0x0 RFA Threshold of active flow control 0 3 RFD Threshold of deactive flow control 4 3 ENET_MSC Ethernet: MAC statistics counters ENET 0x0 0x0 0x400 registers n MSC_CTL MSC_CTL Ethernet MSC control register (MSC_CTL) 0x0 32 read-write n 0x0 0x0 AFHPM Almost full or half preset mode 5 1 CTR Counter reset 0 1 CTSR Counter stop rollover 1 1 MCFZ MSC counter freeze 3 1 PMC Preset MSC counter 4 1 write-only RTOR Reset on read 2 1 MSC_MSCCNT MSC_MSCCNT Ethernet MSC transmitted good frames after more than a single collision 0x50 32 read-only n 0x0 0x0 MSCC Transmitted good frames after more than a single collision counter 0 32 MSC_RFAECNT MSC_RFAECNT Ethernet MSC received frames with alignment error counter register 0x98 32 read-only n 0x0 0x0 RFAER Received frames with alignment error counter 0 32 MSC_RFCECNT MSC_RFCECNT Ethernet MSC received frames with CRC error counter register 0x94 32 read-only n 0x0 0x0 RFCER Received frames with CRC error counter 0 32 MSC_RGUFCNT MSC_RGUFCNT MSC received good unicast frames counter register 0xC4 32 read-only n 0x0 0x0 RGUF Received good unicast frames counter 0 32 MSC_RINTF MSC_RINTF Ethernet MSC receive interrupt flag register (MSC_RINTF) 0x4 32 read-only n 0x0 0x0 RFAE Received frames alignment error 6 1 RFCE Received frames CRC error 5 1 RGUF Received Good Unicast Frames 17 1 MSC_RINTMSK MSC_RINTMSK Ethernet MSC receive interrupt mask register (MSC_RINTMSK) 0xC 32 read-write n 0x0 0x0 RFAEIM Received frames alignment error interrupt mask 6 1 RFCEIM Received frame CRC error interrupt mask 5 1 RGUFIM Received good unicast frames interrupt mask 17 1 MSC_SCCNT MSC_SCCNT Ethernet MSC transmitted good frames after a single collision counter 0x4C 32 read-only n 0x0 0x0 SCC Transmitted good frames after a single collision counter 0 32 MSC_TGFCNT MSC_TGFCNT Ethernet MSC transmitted good frames counter register 0x68 32 read-only n 0x0 0x0 TGF Transmitted good frames counter 0 32 MSC_TINTF MSC_TINTF Ethernet MSC transmit interrupt flag register (MSC_TINTF) 0x8 32 read-only n 0x0 0x0 TGF Transmitted good frames 21 1 TGFMSC Transmitted good frames more single collision 15 1 TGFSC Transmitted good frames single collision 14 1 MSC_TINTMSK MSC_TINTMSK Ethernet MSC transmit interrupt mask register (MSC_TINTMSK) 0x10 32 read-write n 0x0 0x0 TGFIM Transmitted good frames interrupt mask 21 1 TGFMSCIM Transmitted good frames more single interrupt collision mask 15 1 TGFSCIM Transmitted good frames single collision interrupt mask 14 1 ENET_PTP Ethernet: Precision time protocol ENET 0x0 0x0 0x400 registers n PTP_ETH PTP_ETH Ethernet PTP expected time high register 0x1C 32 read-write n 0x0 0x0 ETSH Expected time stamp high 0 32 PTP_ETL PTP_ETL Ethernet PTP expected time low register 0x20 32 read-write n 0x0 0x0 ETSL Expected time stamp low 0 32 PTP_PPSCTL PTP_PPSCTL Ethernet PTP PPS control register 0x2C 32 read-write n 0x0 0x0 PPSOFC PPS output frequency configure 0 4 PTP_SSINC PTP_SSINC Ethernet PTP subsecond increment register 0x4 32 read-write n 0x0 0x0 STMSSI System time subsecond increment 0 8 PTP_TSADDEND PTP_TSADDEND Ethernet PTP time stamp addend register 0x18 32 read-write n 0x0 0x0 TMSA Time stamp addend 0 32 PTP_TSCTL PTP_TSCTL Ethernet PTP time stamp control register (PTP_TSCTL) 0x0 32 read-write n 0x0 0x0 ARFSEN All received frames snapshot enable 8 1 CKNT Clock node type for time stamp 16 2 ESEN Received Ethernet snapshot enable 11 1 ETMSEN Received event type message snapshot enable 14 1 IP4SEN Received IPv4 snapshot enable 13 1 IP6SEN Received IPv6 snapshot enable 12 1 MAFEN MAC address filter enable for PTP frame 18 1 MNMSEN Received master node message snapshot enable 15 1 PFSV PTP frame snooping version 10 1 SCROM Subsecond counter rollover mode 9 1 TMSARU Time stamp addend register update 5 1 TMSEN Time stamp enable 0 1 TMSFCU Time stamp fine or coarse update 1 1 TMSITEN Time stamp interrupt trigger enable 4 1 TMSSTI Time stamp system time initialize 2 1 TMSSTU Time stamp system time update 3 1 PTP_TSF PTP_TSF Ethernet PTP time stamp flag register 0x28 32 read-only n 0x0 0x0 TSSCO Timestamp second counter overflow 0 1 TTM Target time match 1 1 PTP_TSH PTP_TSH Ethernet PTP time stamp high register 0x8 32 read-only n 0x0 0x0 STMS System time second 0 32 PTP_TSL PTP_TSL Ethernet PTP time stamp low register (PTP_TSL) 0xC 32 read-only n 0x0 0x0 STMSS System time subseconds 0 31 STS System time sign 31 1 PTP_TSUH PTP_TSUH Ethernet PTP time stamp high update register 0x10 32 read-write n 0x0 0x0 TMSUS Time stamp update second 0 32 PTP_TSUL PTP_TSUL Ethernet PTP time stamp low update register (PTP_TSUL) 0x14 32 read-write n 0x0 0x0 TMSUPNS Time stamp update positive or negative sign 31 1 TMSUSS Time stamp update subseconds 0 31 EXMC External memory controller EXMC 0x0 0x0 0x1000 registers n EXMC 48 NECC1 NECC1 NAND flash ECC register 1 0x74 32 read-write n 0x0 0x0 ECC ECC result 0 32 read-only NECC2 NECC2 NAND flash ECC register 2 0x94 32 read-write n 0x0 0x0 ECC ECC result 0 32 read-only NPATCFG1 NPATCFG1 NAND flash/PC card attribute space timing configuration register 1 0x6C 32 read-write n 0x0 0x0 ATTHIZ Attribute memory data bus HiZ time 24 8 ATTHLD Attribute memory hold time 16 8 ATTSET Attribute memory setup time 0 8 ATTWAIT Attribute memory wait time 8 8 NPATCFG2 NPATCFG2 NAND flash/PC card attribute space timing configuration register 2 0x8C 32 read-write n 0x0 0x0 ATTHIZ Attribute memory data bus HiZ time 24 8 ATTHLD Attribute memory hold time 16 8 ATTSET Attribute memory setup time 0 8 ATTWAIT Attribute memory wait time 8 8 NPATCFG3 NPATCFG3 NAND flash/PC card attribute space timing configuration register 3 0xAC 32 read-write n 0x0 0x0 ATTHIZ Attribute memory data bus HiZ time 24 8 ATTHLD Attribute memory hold time 16 8 ATTSET Attribute memory setup time 0 8 ATTWAIT Attribute memory wait time 8 8 NPCTCFG1 NPCTCFG1 NAND flash/PC card common space timing configuration register 1 0x68 32 read-write n 0x0 0x0 COMHIZ Common memory data bus HiZ time 24 8 COMHLD Common memory hold time 16 8 COMSET Common memory setup time 0 8 COMWAIT Common memory wait time 8 8 NPCTCFG2 NPCTCFG2 NAND flash/PC card common space timing configuration register 2 0x88 32 read-write n 0x0 0x0 COMHIZ Common memory data bus HiZ time 24 8 COMHLD Common memory hold time 16 8 COMSET Common memory setup time 0 8 COMWAIT Common memory wait time 8 8 NPCTCFG3 NPCTCFG3 NAND flash/PC card common space timing configuration register 3 0xA8 32 read-write n 0x0 0x0 COMHIZ Common memory data bus HiZ time 24 8 COMHLD Common memory hold time 16 8 COMSET Common memory setup time 0 8 COMWAIT Common memory wait time 8 8 NPCTL1 NPCTL1 NAND flash/PC card control register 1 0x60 32 read-write n 0x0 0x0 ATR ALE to RE delay 13 4 CTR CLE to RE delay 9 4 ECCEN ECC enable 6 1 ECCSZ ECC size 17 3 NDBKEN NAND bank enable 2 1 NDTP NAND bank memory type 3 1 NDW NAND bank memory data bus width 4 2 NDWTEN Wait feature enable 1 1 NPCTL2 NPCTL2 NAND flash/PC card control register 2 0x80 32 read-write n 0x0 0x0 ATR ALE to RE delay 13 4 CTR CLE to RE delay 9 4 ECCEN ECC enable 6 1 ECCSZ ECC size 17 3 NDBKEN NAND bank enable 2 1 NDTP NAND bank memory type 3 1 NDW NAND bank memory data bus width 4 2 NDWTEN Wait feature enable 1 1 NPCTL3 NPCTL3 NAND flash/PC card control register 3 0xA0 32 read-write n 0x0 0x0 ATR ALE to RE delay 13 4 CTR CLE to RE delay 9 4 ECCEN ECC enable 6 1 ECCSZ ECC size 17 3 NDBKEN NAND bank enable 2 1 NDTP NAND bank memory type 3 1 NDW NAND bank memory data bus width 4 2 NDWTEN Wait feature enable 1 1 NPINTEN1 NPINTEN1 NAND flash/PC card interrupt enable register 1 0x64 32 read-write n 0x0 0x0 FFEPT FIFO empty flag 6 1 INTFEN Interrupt falling edge detection enable 5 1 INTFS Interrupt falling edge status 2 1 INTHEN Interrupt high-level detection enable 4 1 INTHS Interrupt high-level status 1 1 INTREN Interrupt rising edge detection enable bit 3 1 INTRS Interrupt rising edge status 0 1 NPINTEN2 NPINTEN2 NAND flash/PC card interrupt enable register 2 0x84 32 read-write n 0x0 0x0 FFEPT FIFO empty flag 6 1 INTFEN Interrupt falling edge detection enable 5 1 INTFS Interrupt falling edge status 2 1 INTHEN Interrupt high-level detection enable 4 1 INTHS Interrupt high-level status 1 1 INTREN Interrupt rising edge detection enable bit 3 1 INTRS Interrupt rising edge status 0 1 NPINTEN3 NPINTEN3 NAND flash/PC card interrupt enable register 3 0xA4 32 read-write n 0x0 0x0 FFEPT FIFO empty flag 6 1 INTFEN Interrupt falling edge detection enable 5 1 INTFS Interrupt falling edge status 2 1 INTHEN Interrupt high-level detection enable 4 1 INTHS Interrupt high-level status 1 1 INTREN Interrupt rising edge detection enable bit 3 1 INTRS Interrupt rising edge status 0 1 PIOTCFG3 PIOTCFG3 PC card I/O space timing configuration register 0xB0 32 read-write n 0x0 0x0 IOHIZ IO space data bus HiZ time 24 8 IOHLD IO space hold time 16 8 IOSET IO space setup time 0 8 IOWAIT IO space wait time 8 8 SDARI SDARI SDRAM auto-refresh interval register 0x154 32 read-write n 0x0 0x0 ARINTV Auto-Refresh Interval 1 13 REC Refresh error flag clear 0 1 REIE Refresh error interrupt Enable 14 1 SDCMD SDCMD SDRAM command register 0x150 32 read-write n 0x0 0x0 CMD Command 0 3 DS0 Device select 0 4 1 DS1 Device select 1 3 1 MRC Mode register content 9 13 NARF Number of successive Auto-refresh 5 4 SDCTL0 SDCTL0 SDRAM control register 0 0x140 32 read-write n 0x0 0x0 BRSTRD Burst read 12 1 CAW Column address bit width 0 2 CL CAS Latency 7 2 NBK Number of banks 6 1 PIPED Pipeline delay 13 2 RAW Row address bit width 2 2 SDCLK SDRAM clock configuration 10 2 SDW SDRAM data bus width 4 2 WPEN Write protection enable 9 1 SDCTL1 SDCTL1 SDRAM control register 1 0x144 32 read-write n 0x0 0x0 BRSTRD Burst read 12 1 CAW Column address bit width 0 2 CL CAS Latency 7 2 NBK Number of banks 6 1 PIPED Pipeline delay 13 2 RAW Row address bit width 2 2 SDCLK SDRAM clock configuration 10 2 SDW SDRAM data bus width 4 2 WPEN Write protection enable 9 1 SDRSCTL SDRSCTL SDRAM read sample control register 0x180 32 read-write n 0x0 0x0 RSEN Read sample enable 0 1 SDSC Select the delayed sample clock of read data 4 4 SSCR Select sample cycle of read data 1 1 SDSTAT SDSTAT SDRAM status register 0x158 32 read-write n 0x0 0x0 NRDY Not Ready status 5 1 read-write REIF Refresh error interrupt flag 0 1 read-write STA0 Device 0 status 1 2 read-write STA1 Device1 status 3 2 read-write SDTCFG0 SDTCFG0 SDRAM timing configuration register 0 0x148 32 read-write n 0x0 0x0 ARFD Auto refresh delay 12 4 LMRD Load Mode Register Delay 0 4 RASD Row address select delay 8 4 RCD Row to column delay 24 4 RPD Row precharge delay 20 4 WRD Write recovery delay 16 4 XSRD Exit Self-refresh delay 4 4 SDTCFG1 SDTCFG1 SDRAM timing configuration register 1 0x14C 32 read-write n 0x0 0x0 ARFD Auto refresh delay 12 4 LMRD Load Mode Register Delay 0 4 RASD Row address select delay 8 4 RCD Row to column delay 24 4 RPD Row precharge delay 20 4 WRD Write recovery delay 16 4 XSRD Exit Self-refresh delay 4 4 SIDH SIDH SPI ID high register 0x350 32 read-write n 0x0 0x0 SIDH ID High Data saved for SPI Read ID Command 0 32 SIDL SIDL SPI ID low register 0x340 32 read-write n 0x0 0x0 SIDL ID Low Data saved for SPI Read ID Command 0 32 read-write SINIT SINIT SPI initialization register 0x310 32 read-write n 0x0 0x0 ADRBIT Bit number of SPI PSRAM address phase 24 5 CMDBIT Bit number of SPI PSRAM command phase 16 2 IDL SPI PSRAM ID Length 29 2 POL Read data sample polarity 31 1 SNCTL0 SNCTL0 SRAM/NOR flash control register 0 0x0 32 read-write n 0x0 0x0 ASYNCWAIT Asynchronous wait 15 1 CCK Consecutive Clock 20 1 CPS CRAM page size 16 3 EXMODEN Extended mode enable 14 1 NRBKEN NOR bank enable 0 1 NREN NOR Flash access enable 6 1 NRMUX NOR bank memory address/data multiplexing 1 1 NRTP NOR bank memory type 2 2 NRW NOR bank memory data bus width 4 2 NRWTCFG NWAIT signal configuration, only work in synchronous mode 11 1 NRWTEN NWAIT signal enable 13 1 NRWTPOL NWAIT signal polarity 9 1 SBRSTEN Synchronous burst enable 8 1 SYNCWR Synchronous write 19 1 WRAPEN Wrapped burst mode enable 10 1 WREN Write enable 12 1 SNCTL1 SNCTL1 SRAM/NOR flash control register 1 0x8 32 read-write n 0x0 0x0 ASYNCWAIT Asynchronous wait 15 1 CCK Consecutive Clock 20 1 CPS CRAM page size 16 3 EXMODEN Extended mode enable 14 1 NRBKEN NOR bank enable 0 1 NREN NOR Flash access enable 6 1 NRMUX NOR bank memory address/data multiplexing 1 1 NRTP NOR bank memory type 2 2 NRW NOR bank memory data bus width 4 2 NRWTCFG NWAIT signal configuration, only work in synchronous mode 11 1 NRWTEN NWAIT signal enable 13 1 NRWTPOL NWAIT signal polarity 9 1 SBRSTEN Synchronous burst enable 8 1 SYNCWR Synchronous write 19 1 WRAPEN Wrapped burst mode enable 10 1 WREN Write enable 12 1 SNCTL2 SNCTL2 SRAM/NOR flash control register 2 0x10 32 read-write n 0x0 0x0 ASYNCWAIT Asynchronous wait 15 1 CCK Consecutive Clock 20 1 CPS CRAM page size 16 3 EXMODEN Extended mode enable 14 1 NRBKEN NOR bank enable 0 1 NREN NOR Flash access enable 6 1 NRMUX NOR bank memory address/data multiplexing 1 1 NRTP NOR bank memory type 2 2 NRW NOR bank memory data bus width 4 2 NRWTCFG NWAIT signal configuration, only work in synchronous mode 11 1 NRWTEN NWAIT signal enable 13 1 NRWTPOL NWAIT signal polarity 9 1 SBRSTEN Synchronous burst enable 8 1 SYNCWR Synchronous write 19 1 WRAPEN Wrapped burst mode enable 10 1 WREN Write enable 12 1 SNCTL3 SNCTL3 SRAM/NOR flash control register 3 0x18 32 read-write n 0x0 0x0 ASYNCWAIT Asynchronous wait 15 1 CCK Consecutive Clock 20 1 CPS CRAM page size 16 3 EXMODEN Extended mode enable 14 1 NRBKEN NOR bank enable 0 1 NREN NOR Flash access enable 6 1 NRMUX NOR bank memory address/data multiplexing 1 1 NRTP NOR bank memory type 2 2 NRW NOR bank memory data bus width 4 2 NRWTCFG NWAIT signal configuration, only work in synchronous mode 11 1 NRWTEN NWAIT signal enable 13 1 NRWTPOL NWAIT signal polarity 9 1 SBRSTEN Synchronous burst enable 8 1 SYNCWR Synchronous write 19 1 WRAPEN Wrapped burst mode enable 10 1 WREN Write enable 12 1 SNTCFG0 SNTCFG0 SRAM/NOR flash timing configuration register 0 0x4 32 read-write n 0x0 0x0 AHLD Address hold time 4 4 ASET Address setup time 0 4 ASYNCMOD Asynchronous access mode 28 2 BUSLAT Bus latency 16 4 CKDIV Synchronous clock divide ratio 20 4 DLAT Data latency for NOR Flash 24 4 DSET Data setup time 8 8 SNTCFG1 SNTCFG1 SRAM/NOR flash timing configuration register 1 0xC 32 read-write n 0x0 0x0 AHLD Address hold time 4 4 ASET Address setup time 0 4 ASYNCMOD Asynchronous access mode 28 2 BUSLAT Bus latency 16 4 CKDIV Synchronous clock divide ratio 20 4 DLAT Data latency for NOR Flash 24 4 DSET Data setup time 8 8 SNTCFG2 SNTCFG2 SRAM/NOR flash timing configuration register 2 0x14 32 read-write n 0x0 0x0 AHLD Address hold time 4 4 ASET Address setup time 0 4 ASYNCMOD Asynchronous access mode 28 2 BUSLAT Bus latency 16 4 CKDIV Synchronous clock divide ratio 20 4 DLAT Data latency for NOR Flash 24 4 DSET Data setup time 8 8 SNTCFG3 SNTCFG3 SRAM/NOR flash timing configuration register 3 0x1C 32 read-write n 0x0 0x0 AHLD Address hold time 4 4 ASET Address setup time 0 4 ASYNCMOD Asynchronous access mode 28 2 BUSLAT Bus latency 16 4 CKDIV Synchronous clock divide ratio 20 4 DLAT Data latency for NOR Flash 24 4 DSET Data setup time 8 8 SNWTCFG0 SNWTCFG0 SRAM/NOR flash write timing configuration register 0 0x104 32 read-write n 0x0 0x0 WAHLD Address hold time 4 4 WASET Address setup time 0 4 WASYNCMOD Asynchronous access mode 28 2 WBUSLAT Bus latency 16 4 WDSET Data setup time 8 8 SNWTCFG1 SNWTCFG1 SRAM/NOR flash write timing configuration register 1 0x10C 32 read-write n 0x0 0x0 WAHLD Address hold time 4 4 WASET Address setup time 0 4 WASYNCMOD Asynchronous access mode 28 2 WBUSLAT Bus latency 16 4 WDSET Data setup time 8 8 SNWTCFG2 SNWTCFG2 SRAM/NOR flash write timing configuration register 2 0x114 32 read-write n 0x0 0x0 WAHLD Address hold time 4 4 WASET Address setup time 0 4 WASYNCMOD Asynchronous access mode 28 2 WBUSLAT Bus latency 16 4 WDSET Data setup time 8 8 SNWTCFG3 SNWTCFG3 SRAM/NOR flash write timing configuration register 3 0x11C 32 read-write n 0x0 0x0 WAHLD Address hold time 4 4 WASET Address setup time 0 4 WASYNCMOD Asynchronous access mode 28 2 WBUSLAT Bus latency 16 4 WDSET Data setup time 8 8 SRCMD SRCMD SPI read command register 0x320 32 read-write n 0x0 0x0 RCMD SPI Read Command for AHB read transfer 0 16 RDID Send SPI Read ID Command 31 1 RMODE SPI PSRAM Read command mode 20 2 RWAITCYCLE SPI Read Wait Cycle number after address phase 16 4 SWCMD SWCMD SPI write command register 0x330 32 read-write n 0x0 0x0 SC Send SPI Special Command which does not have address and data phase, command code and mode come from WCMD and WMODE 31 1 WCMD SPI Write Command for AHB write transfer 0 15 WMODE SPI PSRAM Write command mode 20 2 WWAITCYCLE SPI Write Wait Cycle number after address phase 16 4 EXTI External interrupt/event controller EXTI 0x0 0x0 0x400 registers n EXTI_Line0 6 EXTI_Line1 7 EXTI_Line2 8 EXTI_Line3 9 EXTI_Line4 10 EXTI_line9_5 23 EXTI_line15_10 40 EVEN EVEN Event enable register (EXTI_EVEN) 0x4 32 read-write n 0x0 0x0 EVEN0 Enable Event on line 0 0 1 EVEN1 Enable Event on line 1 1 1 EVEN10 Enable Event on line 10 10 1 EVEN11 Enable Event on line 11 11 1 EVEN12 Enable Event on line 12 12 1 EVEN13 Enable Event on line 13 13 1 EVEN14 Enable Event on line 14 14 1 EVEN15 Enable Event on line 15 15 1 EVEN16 Enable Event on line 16 16 1 EVEN17 Enable Event on line 17 17 1 EVEN18 Enable Event on line 18 18 1 EVEN19 Enable Event on line 19 19 1 EVEN2 Enable Event on line 2 2 1 EVEN20 Enable Event on line 20 20 1 EVEN21 Enable Event on line 21 21 1 EVEN22 Enable Event on line 22 22 1 EVEN3 Enable Event on line 3 3 1 EVEN4 Enable Event on line 4 4 1 EVEN5 Enable Event on line 5 5 1 EVEN6 Enable Event on line 6 6 1 EVEN7 Enable Event on line 7 7 1 EVEN8 Enable Event on line 8 8 1 EVEN9 Enable Event on line 9 9 1 FTEN FTEN Falling Egde Trigger Enable register (EXTI_FTEN) 0xC 32 read-write n 0x0 0x0 FTEN0 Falling edge trigger enable of line 0 0 1 FTEN1 Falling edge trigger enable of line 1 1 1 FTEN10 Falling edge trigger enable of line 10 10 1 FTEN11 Falling edge trigger enable of line 11 11 1 FTEN12 Falling edge trigger enable of line 12 12 1 FTEN13 Falling edge trigger enable of line 13 13 1 FTEN14 Falling edge trigger enable of line 14 14 1 FTEN15 Falling edge trigger enable of line 15 15 1 FTEN16 Falling edge trigger enable of line 16 16 1 FTEN17 Falling edge trigger enable of line 17 17 1 FTEN18 Falling edge trigger enable of line 18 18 1 FTEN19 Falling edge trigger enable of line 19 19 1 FTEN2 Falling edge trigger enable of line 2 2 1 FTEN20 Falling edge trigger enable of line 20 20 1 FTEN21 Falling edge trigger enable of line 21 21 1 FTEN22 Falling edge trigger enable of line 22 22 1 FTEN3 Falling edge trigger enable of line 3 3 1 FTEN4 Falling edge trigger enable of line 4 4 1 FTEN5 Falling edge trigger enable of line 5 5 1 FTEN6 Falling edge trigger enable of line 6 6 1 FTEN7 Falling edge trigger enable of line 7 7 1 FTEN8 Falling edge trigger enable of line 8 8 1 FTEN9 Falling edge trigger enable of line 9 9 1 INTEN INTEN Interrupt enable register (EXTI_INTEN) 0x0 32 read-write n 0x0 0x0 INTEN0 Enable Interrupt on line 0 0 1 INTEN1 Enable Interrupt on line 1 1 1 INTEN10 Enable Interrupt on line 10 10 1 INTEN11 Enable Interrupt on line 11 11 1 INTEN12 Enable Interrupt on line 12 12 1 INTEN13 Enable Interrupt on line 13 13 1 INTEN14 Enable Interrupt on line 14 14 1 INTEN15 Enable Interrupt on line 15 15 1 INTEN16 Enable Interrupt on line 16 16 1 INTEN17 Enable Interrupt on line 17 17 1 INTEN18 Enable Interrupt on line 18 18 1 INTEN19 Enable Interrupt on line 19 19 1 INTEN2 Enable Interrupt on line 2 2 1 INTEN20 Enable Interrupt on line 20 20 1 INTEN21 Enable Interrupt on line 21 21 1 INTEN22 Enable Interrupt on line 22 22 1 INTEN3 Enable Interrupt on line 3 3 1 INTEN4 Enable Interrupt on line 4 4 1 INTEN5 Enable Interrupt on line 5 5 1 INTEN6 Enable Interrupt on line 6 6 1 INTEN7 Enable Interrupt on line 7 7 1 INTEN8 Enable Interrupt on line 8 8 1 INTEN9 Enable Interrupt on line 9 9 1 PD PD Pending register (EXTI_PD) 0x14 32 read-write n 0x0 0x0 PD0 Interrupt pending status of line 0 0 1 PD1 Interrupt pending status of line 1 1 1 PD10 Interrupt pending status of line 10 10 1 PD11 Interrupt pending status of line 11 11 1 PD12 Interrupt pending status of line 12 12 1 PD13 Interrupt pending status of line 13 13 1 PD14 Interrupt pending status of line 14 14 1 PD15 Interrupt pending status of line 15 15 1 PD16 Interrupt pending status of line 16 16 1 PD17 Interrupt pending status of line 17 17 1 PD18 Interrupt pending status of line 18 18 1 PD19 Interrupt pending status of line 19 19 1 PD2 Interrupt pending status of line 2 2 1 PD20 Interrupt pending status of line 20 20 1 PD21 Interrupt pending status of line 21 21 1 PD22 Interrupt pending status of line 22 22 1 PD3 Interrupt pending status of line 3 3 1 PD4 Interrupt pending status of line 4 4 1 PD5 Interrupt pending status of line 5 5 1 PD6 Interrupt pending status of line 6 6 1 PD7 Interrupt pending status of line 7 7 1 PD8 Interrupt pending status of line 8 8 1 PD9 Interrupt pending status of line 9 9 1 RTEN RTEN Rising Edge Trigger Enable register (EXTI_RTEN) 0x8 32 read-write n 0x0 0x0 RTEN0 Rising edge trigger enable of line 0 0 1 RTEN1 Rising edge trigger enable of line 1 1 1 RTEN10 Rising edge trigger enable of line 10 10 1 RTEN11 Rising edge trigger enable of line 11 11 1 RTEN12 Rising edge trigger enable of line 12 12 1 RTEN13 Rising edge trigger enable of line 13 13 1 RTEN14 Rising edge trigger enable of line 14 14 1 RTEN15 Rising edge trigger enable of line 15 15 1 RTEN16 Rising edge trigger enable of line 16 16 1 RTEN17 Rising edge trigger enable of line 17 17 1 RTEN18 Rising edge trigger enable of line 18 18 1 RTEN19 Rising edge trigger enable of line 19 19 1 RTEN2 Rising edge trigger enable of line 2 2 1 RTEN20 Rising edge trigger enable of line 20 20 1 RTEN21 Rising edge trigger enable of line 21 21 1 RTEN22 Rising edge trigger enable of line 22 22 1 RTEN3 Rising edge trigger enable of line 3 3 1 RTEN4 Rising edge trigger enable of line 4 4 1 RTEN5 Rising edge trigger enable of line 5 5 1 RTEN6 Rising edge trigger enable of line 6 6 1 RTEN7 Rising edge trigger enable of line 7 7 1 RTEN8 Rising edge trigger enable of line 8 8 1 RTEN9 Rising edge trigger enable of line 9 9 1 SWIEV SWIEV Software interrupt event register (EXTI_SWIEV) 0x10 32 read-write n 0x0 0x0 SWIEV0 Interrupt/Event software trigger on line 0 0 1 SWIEV1 Interrupt/Event software trigger on line 1 1 1 SWIEV10 Interrupt/Event software trigger on line 10 10 1 SWIEV11 Interrupt/Event software trigger on line 11 11 1 SWIEV12 Interrupt/Event software trigger on line 12 12 1 SWIEV13 Interrupt/Event software trigger on line 13 13 1 SWIEV14 Interrupt/Event software trigger on line 14 14 1 SWIEV15 Interrupt/Event software trigger on line 15 15 1 SWIEV16 Interrupt/Event software trigger on line 16 16 1 SWIEV17 Interrupt/Event software trigger on line 17 17 1 SWIEV18 Interrupt/Event software trigger on line 18 18 1 SWIEV19 Interrupt/Event software trigger on line 19 19 1 SWIEV2 Interrupt/Event software trigger on line 2 2 1 SWIEV20 Interrupt/Event software trigger on line 20 20 1 SWIEV21 Interrupt/Event software trigger on line 21 21 1 SWIEV22 Interrupt/Event software trigger on line 22 22 1 SWIEV3 Interrupt/Event software trigger on line 3 3 1 SWIEV4 Interrupt/Event software trigger on line 4 4 1 SWIEV5 Interrupt/Event software trigger on line 5 5 1 SWIEV6 Interrupt/Event software trigger on line 6 6 1 SWIEV7 Interrupt/Event software trigger on line 7 7 1 SWIEV8 Interrupt/Event software trigger on line 8 8 1 SWIEV9 Interrupt/Event software trigger on line 9 9 1 FMC FMC FMC 0x0 0x0 0x400 registers n FMC 4 CTL CTL Control register 0x10 32 read-write n 0x0 0x0 ENDIE End of operation interrupt enable bit 24 1 ERRIE Error interrupt enable bit 25 1 LK FMC_CTL lock bit 31 1 MER0 main flash mass erase for bank0 command bit 2 1 MER1 main flash mass erase for bank1command bit 15 1 PG main flash program command bit 0 1 PSZ Program size bit 8 2 SER main flash sector erase command bit 1 1 SN Select which sector number to be erased. 3 5 START send erase command to FMC bit 16 1 KEY KEY Unlock key register 0x4 32 write-only n 0x0 0x0 KEY FMC_CTL unlock register 0 32 OBCTL0 OBCTL0 Option byte control register 0 0x14 32 read-write n 0x0 0x0 BB option byte boot bank value 4 1 BOR_TH option byte BOR threshold value 2 2 DBS Double banks or single bank selection when flash size is 1M 30 1 DRP D-bus read protection bit 31 1 nRST_DPSLP option byte deepsleep reset value 6 1 nRST_STDBY option byte standby reset value 7 1 nWDG_HW option byte watchdog value 5 1 OB_LK FMC_OBCTL0 lock bit 0 1 OB_START send option byte change command to FMC bit 1 1 SPC option byte Security Protection code 8 8 WP0 Erase/program protection of each sector when DRP is 0 16 12 OBCTL1 OBCTL1 Option byte control register 1 0x18 32 read-write n 0x0 0x0 WP1 Erase/program protection of each sector when DRP is 0 16 12 OBKEY OBKEY Option byte unlock key register 0x8 32 write-only n 0x0 0x0 OBKEY FMC_ OBCTL0 option byte operation unlock register 0 32 PID PID Product ID register 0x100 32 read-only n 0x0 0x0 PID Product reserved ID code register 0 32 STAT STAT Status register 0xC 32 read-write n 0x0 0x0 BUSY The flash is busy bit 16 1 read-only END End of operation flag bit 0 1 read-write OPERR Flash operation error flag bit 1 1 read-write PGMERR Program size not match error flag bit 6 1 read-write PGSERR Program sequence error flag bit 7 1 read-write RDDERR Read D-bus protection error flag bit 8 1 read-write WPERR Erase/Program protection error flag bit 4 1 read-write WS WS wait state counter register 0x0 32 read-write n 0x0 0x0 WSCNT wait state counter register 0 4 WSEN WSEN Wait state enable register 0xFC 32 read-only n 0x0 0x0 WSEN FMC wait state enable register 0 1 FS_DEVICE USB on the go full speed device USB_FS 0x0 0x0 0x400 registers n DAEPINT DAEPINT device all endpoints interrupt register (DAEPINT) 0x18 32 read-only n 0x0 0x0 IEPITB Device all IN endpoint interrupt bits 0 4 OEPITB Device all OUT endpoint interrupt bits 16 4 DAEPINTEN DAEPINTEN Device all endpoints interrupt enable register (DAEPINTEN) 0x1C 32 read-write n 0x0 0x0 IEPIE IN EP interrupt interrupt enable bits 0 4 OEPIE OUT endpoint interrupt enable bits 16 4 DCFG DCFG device configuration register (DCFG) 0x0 32 read-write n 0x0 0x0 DAR Device address 4 7 DS Device speed 0 2 EOPFT end of periodic frame time 11 2 NZLSOH Non-zero-length status OUT handshake 2 1 DCTL DCTL device control register (DCTL) 0x4 32 read-write n 0x0 0x0 CGINAK Clear global IN NAK 8 1 write-only CGONAK Clear global OUT NAK 10 1 write-only GINS Global IN NAK status 2 1 read-only GONS Global OUT NAK status 3 1 read-only POIF Power-on initialization flag 11 1 read-write RWKUP Remote wakeup 0 1 read-write SD Soft disconnect 1 1 read-write SGINAK Set global IN NAK 7 1 write-only SGONAK Set global OUT NAK 9 1 write-only DIEP0CTL DIEP0CTL device IN endpoint 0 control register (DIEP0CTL) 0x100 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EPACT endpoint active 15 1 read-only EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write EPTYPE Endpoint type 18 2 read-only MPL Maximum packet length 0 2 read-write NAKS NAK status 17 1 read-only SNAK Set NAK 27 1 write-only STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write DIEP0INTF DIEP0INTF device endpoint-0 interrupt register 0x108 32 read-write n 0x0 0x0 CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write IEPNE IN endpoint NAK effective 6 1 read-write TF Transfer finished 0 1 read-write TXFE Transmit FIFO empty 7 1 read-only DIEP0LEN DIEP0LEN device IN endpoint-0 transfer length register 0x110 32 read-write n 0x0 0x0 PCNT Packet count 19 2 TLEN Transfer length 0 7 DIEP0TFSTAT DIEP0TFSTAT device IN endpoint 0 transmit FIFO status register 0x118 32 read-only n 0x0 0x0 IEPTFS IN endpoint TxFIFO space remaining 0 16 DIEP1CTL DIEP1CTL device in endpoint-1 control register 0x120 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write EPTYPE Endpoint type 18 2 read-write MPL maximum packet length 0 11 read-write NAKS NAK status 17 1 read-only SD0PID_SEVENFRM SD0PID/SEVNFRM 28 1 write-only SD1PID_SODDFRM Set DATA1 PID/Set odd frame 29 1 write-only SNAK Set NAK 27 1 write-only STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write DIEP1INTF DIEP1INTF device endpoint-1 interrupt register 0x128 32 read-write n 0x0 0x0 CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write IEPNE IN endpoint NAK effective 6 1 read-write TF Transfer finished 0 1 read-write TXFE Transmit FIFO empty 7 1 read-only DIEP1LEN DIEP1LEN device IN endpoint-1 transfer length register 0x130 32 read-write n 0x0 0x0 PCNT Packet count 19 10 TLEN Transfer length 0 19 DIEP1TFSTAT DIEP1TFSTAT device IN endpoint 1 transmit FIFO status register 0x138 32 read-only n 0x0 0x0 IEPTFS IN endpoint TxFIFO space remaining 0 16 DIEP2CTL DIEP2CTL device endpoint-2 control register 0x140 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write EPTYPE Endpoint type 18 2 read-write MPL maximum packet length 0 11 read-write NAKS NAK status 17 1 read-only SD0PID_SEVENFRM SD0PID/SEVNFRM 28 1 write-only SD1PID_SODDFRM Set DATA1 PID/Set odd frame 29 1 write-only SNAK Set NAK 27 1 write-only STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write DIEP2INTF DIEP2INTF device endpoint-2 interrupt register 0x148 32 read-write n 0x0 0x0 CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write IEPNE IN endpoint NAK effective 6 1 read-write TF Transfer finished 0 1 read-write TXFE Transmit FIFO empty 7 1 read-only DIEP2LEN DIEP2LEN device IN endpoint-2 transfer length register 0x150 32 read-write n 0x0 0x0 PCNT Packet count 19 10 TLEN Transfer length 0 19 DIEP2TFSTAT DIEP2TFSTAT device IN endpoint 2 transmit FIFO status register 0x158 32 read-only n 0x0 0x0 IEPTFS IN endpoint TxFIFO space remaining 0 16 DIEP3CTL DIEP3CTL device endpoint-3 control register 0x160 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write EPTYPE Endpoint type 18 2 read-write MPL maximum packet length 0 11 read-write NAKS NAK status 17 1 read-only SD0PID_SEVENFRM SD0PID/SEVNFRM 28 1 write-only SD1PID_SODDFRM Set DATA1 PID/Set odd frame 29 1 write-only SNAK Set NAK 27 1 write-only STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write DIEP3INTF DIEP3INTF device endpoint-3 interrupt register 0x168 32 read-write n 0x0 0x0 CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write IEPNE IN endpoint NAK effective 6 1 read-write TF Transfer finished 0 1 read-write TXFE Transmit FIFO empty 7 1 read-only DIEP3LEN DIEP3LEN device IN endpoint-3 transfer length register 0x170 32 read-write n 0x0 0x0 PCNT Packet count 19 10 TLEN Transfer length 0 19 DIEP3TFSTAT DIEP3TFSTAT device IN endpoint 3 transmit FIFO status register 0x178 32 read-only n 0x0 0x0 IEPTFS IN endpoint TxFIFO space remaining 0 16 DIEPFEINTEN DIEPFEINTEN device IN endpoint FIFO empty interrupt enable register 0x34 32 read-write n 0x0 0x0 IEPTXFEIE IN EP Tx FIFO empty interrupt enable bits 0 4 DIEPINTEN DIEPINTEN device IN endpoint common interrupt mask register (DIEPINTEN) 0x10 32 read-write n 0x0 0x0 CITOEN Control IN timeout condition interrupt enable (Non-isochronous endpoints) 3 1 EPDISEN Endpoint disabled interrupt enable 1 1 EPTXFUDEN Endpoint Tx FIFO underrun interrupt enable bit 4 1 IEPNEEN IN endpoint NAK effective interrupt enable 6 1 TFEN Transfer finished interrupt enable 0 1 TXFEEN Trabsmit FIFO empty interrupt enable 7 1 DOEP0CTL DOEP0CTL device endpoint-0 control register 0x300 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EPACT Endpoint active 15 1 read-only EPD Endpoint disable 30 1 read-only EPEN Endpoint enable 31 1 write-only EPTYPE Endpoint type 18 2 read-only MPL Maximum packet length 0 2 read-only NAKS NAK status 17 1 read-only SNAK Set NAK 27 1 write-only SNOOP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write DOEP0INTF DOEP0INTF device out endpoint-0 interrupt flag register 0x308 32 read-write n 0x0 0x0 BTBSTP Back-to-back SETUP packets 6 1 EPDIS Endpoint disabled 1 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 STPF Setup phase finished 3 1 TF Transfer finished 0 1 DOEP0LEN DOEP0LEN device OUT endpoint-0 transfer length register 0x310 32 read-write n 0x0 0x0 PCNT Packet count 19 1 STPCNT SETUP packet count 29 2 TLEN Transfer length 0 7 DOEP1CTL DOEP1CTL device endpoint-1 control register 0x320 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write EPTYPE Endpoint type 18 2 read-write MPL maximum packet length 0 11 read-write NAKS NAK status 17 1 read-only SD0PID_SEVENFRM SD0PID/SEVENFRM 28 1 write-only SD1PID_SODDFRM SD1PID/SODDFRM 29 1 write-only SNAK Set NAK 27 1 write-only SNOOP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write DOEP1INTF DOEP1INTF device out endpoint-1 interrupt flag register 0x328 32 read-write n 0x0 0x0 BTBSTP Back-to-back SETUP packets 6 1 EPDIS Endpoint disabled 1 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 STPF Setup phase finished 3 1 TF Transfer finished 0 1 DOEP1LEN DOEP1LEN device OUT endpoint-1 transfer length register 0x330 32 read-write n 0x0 0x0 PCNT Packet count 19 10 STPCNT_RXDPID SETUP packet count/Received data PID 29 2 TLEN Transfer length 0 19 DOEP2CTL DOEP2CTL device endpoint-2 control register 0x340 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write EPTYPE Endpoint type 18 2 read-write MPL maximum packet length 0 11 read-write NAKS NAK status 17 1 read-only SD0PID_SEVENFRM SD0PID/SEVENFRM 28 1 write-only SD1PID_SODDFRM SD1PID/SODDFRM 29 1 write-only SNAK Set NAK 27 1 write-only SNOOP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write DOEP2INTF DOEP2INTF device out endpoint-2 interrupt flag register 0x348 32 read-write n 0x0 0x0 BTBSTP Back-to-back SETUP packets 6 1 EPDIS Endpoint disabled 1 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 STPF Setup phase finished 3 1 TF Transfer finished 0 1 DOEP2LEN DOEP2LEN device OUT endpoint-2 transfer length register 0x350 32 read-write n 0x0 0x0 PCNT Packet count 19 10 STPCNT_RXDPID SETUP packet count/Received data PID 29 2 TLEN Transfer length 0 19 DOEP3CTL DOEP3CTL device endpoint-3 control register 0x360 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write EPTYPE Endpoint type 18 2 read-write MPL maximum packet length 0 11 read-write NAKS NAK status 17 1 read-only SD0PID_SEVENFRM SD0PID/SEVENFRM 28 1 write-only SD1PID_SODDFRM SD1PID/SODDFRM 29 1 write-only SNAK Set NAK 27 1 write-only SNOOP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write DOEP3INTF DOEP3INTF device out endpoint-3 interrupt flag register 0x368 32 read-write n 0x0 0x0 BTBSTP Back-to-back SETUP packets 6 1 EPDIS Endpoint disabled 1 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 STPF Setup phase finished 3 1 TF Transfer finished 0 1 DOEP3LEN DOEP3LEN device OUT endpoint-3 transfer length register 0x370 32 read-write n 0x0 0x0 PCNT Packet count 19 10 STPCNT_RXDPID SETUP packet count/Received data PID 29 2 TLEN Transfer length 0 19 DOEPINTEN DOEPINTEN device OUT endpoint common interrupt enable register (DOEPINTEN) 0x14 32 read-write n 0x0 0x0 BTBSTPEN Back-to-back SETUP packets interrupt enable 6 1 EPDISEN Endpoint disabled interrupt enable 1 1 EPRXFOVREN Endpoint Rx FIFO overrun interrupt enable 4 1 STPFEN SETUP phase finished interrupt enable 3 1 TFEN Transfer finished interrupt enable 0 1 DSTAT DSTAT device status register (DSTAT) 0x8 32 read-only n 0x0 0x0 ES Enumerated speed 1 2 FNRSOF Frame number of the received SOF 8 14 SPST Suspend status 0 1 DVBUSDT DVBUSDT device VBUS discharge time register 0x28 32 read-write n 0x0 0x0 DVBUSDT Device VBUS discharge time 0 16 DVBUSPT DVBUSPT device VBUS pulsing time register 0x2C 32 read-write n 0x0 0x0 DVBUSPT Device VBUS pulsing time 0 12 FS_GLOBAL USB full speed global registers USB_FS 0x0 0x0 0x400 registers n OTG_FS_WKUP 42 OTG_FS 67 CID CID core ID register 0x3C 32 read-write n 0x0 0x0 CID Core ID 0 32 DIEP0TFLEN DIEP0TFLEN Device IN endpoint 0 transmit FIFO length (Device mode) HNPTFLEN 0x28 32 read-write n 0x0 0x0 IEP0TXFD in endpoint 0 Tx FIFO depth 0 16 IEP0TXRSAR in endpoint 0 Tx RAM start address 16 16 DIEP1TFLEN DIEP1TFLEN device IN endpoint transmit FIFO size register (DIEP1TFLEN) 0x104 32 read-write n 0x0 0x0 IEPTXFD IN endpoint TxFIFO depth 16 16 IEPTXRSAR IN endpoint FIFO transmit RAM start address 0 16 DIEP2TFLEN DIEP2TFLEN device IN endpoint transmit FIFO size register (DIEP2TFLEN) 0x108 32 read-write n 0x0 0x0 IEPTXFD IN endpoint TxFIFO depth 16 16 IEPTXRSAR IN endpoint FIFO transmit RAM start address 0 16 DIEP3TFLEN DIEP3TFLEN device IN endpoint transmit FIFO size register (FS_DIEP3TXFLEN) 0x10C 32 read-write n 0x0 0x0 IEPTXFD IN endpoint TxFIFO depth 16 16 IEPTXRSAR IN endpoint FIFO4 transmit RAM start address 0 16 GAHBCS GAHBCS Global AHB control and status register (USBFS_GAHBCS) 0x8 32 read-write n 0x0 0x0 GINTEN Global interrupt enable 0 1 PTXFTH Periodic Tx FIFO threshold 8 1 TXFTH Tx FIFO threshold 7 1 GCCFG GCCFG Global core configuration register (USBFS_GCCFG) 0x38 32 read-write n 0x0 0x0 PWRON Power on 16 1 SOFOEN SOF output enable 20 1 VBUSACEN The VBUS A-device Comparer enable 18 1 VBUSBCEN The VBUS B-device Comparer enable 19 1 VBUSIG VBUS ignored 21 1 GINTEN GINTEN Global interrupt enable register (USBFS_GINTEN) 0x18 32 read-write n 0x0 0x0 DISCIE Disconnect interrupt enable 29 1 read-write ENUMFIE Enumeration finish interrupt enable 13 1 read-write EOPFIE End of periodic frame interrupt enable 15 1 read-write ESPIE Early suspend interrupt enable 10 1 read-write GNPINAKIE Global non-periodic IN NAK effective interrupt enable 6 1 read-write GONAKIE Global OUT NAK effective interrupt enable 7 1 read-write HCIE Host channels interrupt enable 25 1 read-write HPIE Host port interrupt enable 24 1 read-only IDPSCIE ID pin status change interrupt enable 28 1 read-write IEPIE IN endpoints interrupt enable 18 1 read-write ISOINCIE isochronous IN transfer not complete interrupt enable 20 1 read-write ISOOPDIE Isochronous OUT packet dropped interrupt enable 14 1 read-write MFIE Mode fault interrupt enable 1 1 read-write NPTXFEIE Non-periodic TxFIFO empty interrupt enable 5 1 read-write OEPIE OUT endpoints interrupt enable 19 1 read-write OTGIE OTG interrupt enable 2 1 read-write PTXFEIE Periodic TxFIFO empty interrupt enable 26 1 read-write PXNCIE_ISOONCIE periodic transfer not compelete Interrupt enable(Host mode)/isochronous OUT transfer not complete interrupt enable(Device mode) 21 1 read-write RSTIE USB reset interrupt enable 12 1 read-write RXFNEIE Receive FIFO non-empty interrupt enable 4 1 read-write SESIE Session interrupt enable 30 1 read-write SOFIE Start of frame interrupt enable 3 1 read-write SPIE USB suspend interrupt enable 11 1 read-write WKUPIE Wakeup interrupt enable 31 1 read-write GINTF GINTF Global interrupt flag register (USBFS_GINTF) 0x14 32 read-write n 0x0 0x0 COPM Current operation mode 0 1 read-only DISCIF Disconnect interrupt flag 29 1 read-write ENUMF Enumeration finished 13 1 read-write EOPFIF End of periodic frame interrupt flag 15 1 read-write ESP Early suspend 10 1 read-write GNPINAK Global Non-Periodic IN NAK effective 6 1 read-only GONAK Global OUT NAK effective 7 1 read-only HCIF Host channels interrupt flag 25 1 read-only HPIF Host port interrupt flag 24 1 read-only IDPSC ID pin status change 28 1 read-write IEPIF IN endpoint interrupt flag 18 1 read-only ISOINCIF Isochronous IN transfer Not Complete Interrupt Flag 20 1 read-write ISOOPDIF Isochronous OUT packet dropped interrupt 14 1 read-write MFIF Mode fault interrupt flag 1 1 read-write NPTXFEIF Non-periodic TxFIFO empty interrupt flag 5 1 read-only OEPIF OUT endpoint interrupt flag 19 1 read-only OTGIF OTG interrupt flag 2 1 read-only PTXFEIF Periodic TxFIFO empty interrupt flag 26 1 read-only PXNCIF_ISOONCIF periodic transfer not complete interrupt flag(Host mode)/isochronous OUT transfer not complete interrupt flag(Device mode) 21 1 read-write RST USB reset 12 1 read-write RXFNEIF RxFIFO non-empty interrupt flag 4 1 read-only SESIF Session interrupt flag 30 1 read-write SOF Start of frame 3 1 read-write SP USB suspend 11 1 read-write WKUPIF Wakeup interrupt flag 31 1 read-write GOTGCS GOTGCS Global OTG control and status register (USBFS_GOTGCS) 0x0 32 read-write n 0x0 0x0 ASV A-session valid 18 1 read-only BSV B-session valid 19 1 read-only DHNPEN Device HNP enabled 11 1 read-write DI Debounce interval 17 1 read-only HHNPEN Host HNP enable 10 1 read-write HNPREQ HNP request 9 1 read-write HNPS Host success 8 1 read-only IDPS ID pin status 16 1 read-only SRPREQ SRP request 1 1 read-write SRPS SRP success 0 1 read-only GOTGINTF GOTGINTF Global OTG interrupt flag register (OTG_FS_GOTGINTF) 0x4 32 read-write n 0x0 0x0 ADTO A-device timeout 18 1 DF Debounce finish 19 1 HNPDET Host negotiation request detected 17 1 HNPEND HNP end 9 1 SESEND Session end 2 1 SRPEND Session request success status change 8 1 GRFLEN GRFLEN Global Receive FIFO size register (USBFS_GRFLEN) 0x24 32 read-write n 0x0 0x0 RXFD Rx FIFO depth 0 16 GRSTATP_Device GRSTATP_Device Global Receive status pop(Device mode) 0x20 32 read-only n 0x0 0x0 BCOUNT Byte count 4 11 DPID Data PID 15 2 EPNUM Endpoint number 0 4 RPCKST Recieve packet status 17 4 GRSTATP_Host GRSTATP_Host Global Receive status pop(Host mode) GRSTATP_Device 0x20 32 read-only n 0x0 0x0 BCOUNT Byte count 4 11 CNUM Channel number 0 4 DPID Data PID 15 2 RPCKST Reivece packet status 17 4 GRSTATR_Device GRSTATR_Device Global Receive status read(Device mode) 0x1C 32 read-only n 0x0 0x0 BCOUNT Byte count 4 11 DPID Data PID 15 2 EPNUM Endpoint number 0 4 RPCKST Recieve packet status 17 4 GRSTATR_Host GRSTATR_Host Global Receive status read(Host mode) GRSTATR_Device 0x1C 32 read-only n 0x0 0x0 BCOUNT Byte count 4 11 CNUM Channel number 0 4 DPID Data PID 15 2 RPCKST Reivece packet status 17 4 GRSTCTL GRSTCTL Global reset control register (USBFS_GRSTCTL) 0x10 32 read-write n 0x0 0x0 CSRST Core soft reset 0 1 read-write HCSRST HCLK soft reset 1 1 read-write HFCRST Host frame counter reset 2 1 read-write RXFF RxFIFO flush 4 1 read-write TXFF TxFIFO flush 5 1 read-write TXFNUM TxFIFO number 6 5 read-write GUSBCS GUSBCS Global USB control and status register (OTG_FS_GUSBCSR) 0xC 32 read-write n 0x0 0x0 FDM Force device mode 30 1 read-write FHM Force host mode 29 1 read-write HNPCEN HNP capability enable 9 1 read-write SRPCEN SRP capability enable 8 1 read-write TOC Timeout calibration 0 3 read-write UTT USB turnaround time 10 4 read-write HNPTFLEN HNPTFLEN Host non-periodic transmit FIFO length register (Host mode) 0x28 32 read-write n 0x0 0x0 HNPTXFD host non-periodic TxFIFO depth 16 16 HNPTXRSAR host non-periodic transmit Tx RAM start address 0 16 HNPTFQSTAT HNPTFQSTAT Host non-periodic transmit FIFO/queue status register (HNPTFQSTAT) 0x2C 32 read-only n 0x0 0x0 NPTXFS Non-periodic TxFIFO space 0 16 NPTXRQS Non-periodic transmit request queue space 16 8 NPTXRQTOP Top of the non-periodic transmit request queue 24 7 HPTFLEN HPTFLEN Host periodic transmit FIFO length register (HPTFLEN) 0x100 32 read-write n 0x0 0x0 HPTXFD Host periodic TxFIFO depth 16 16 HPTXFSAR Host periodic TxFIFO start address 0 16 FS_HOST USB on the go full speed host USB_FS 0x0 0x0 0x400 registers n HACHINT HACHINT Host all channels interrupt register 0x14 32 read-only n 0x0 0x0 HACHINT Host all channel interrupts 0 8 HACHINTEN HACHINTEN host all channels interrupt mask register 0x18 32 read-write n 0x0 0x0 CINTEN Channel interrupt enable 0 8 HCH0CTL HCH0CTL host channel-0 characteristics register (HCH0CTL) 0x100 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH0INTEN HCH0INTEN host channel-0 interrupt enable register (HCH0INTEN) 0x10C 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer completed interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH0INTF HCH0INTF host channel-0 interrupt register (USBFS_HCHxINTF) 0x108 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer finished 0 1 USBER USB bus error 7 1 HCH0LEN HCH0LEN host channel-0 transfer length register 0x110 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 HCH1CTL HCH1CTL host channel-1 characteristics register (HCH1CTL) 0x120 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH1INTEN HCH1INTEN host channel-1 interrupt enable register (HCH1INTEN) 0x12C 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer completed interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH1INTF HCH1INTF host channel-1 interrupt register (HCH1INTF) 0x128 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer finished 0 1 USBER USB bus error 7 1 HCH1LEN HCH1LEN host channel-1 transfer length register 0x130 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 HCH2CTL HCH2CTL host channel-2 characteristics register (HCH2CTL) 0x140 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH2INTEN HCH2INTEN host channel-2 interrupt enable register (HCH2INTEN) 0x14C 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer completed interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH2INTF HCH2INTF host channel-2 interrupt register (HCH2INTF) 0x148 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer finished 0 1 USBER USB bus error 7 1 HCH2LEN HCH2LEN host channel-2 transfer length register 0x150 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 HCH3CTL HCH3CTL host channel-3 characteristics register (HCH3CTL) 0x160 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH3INTEN HCH3INTEN host channel-3 interrupt enable register (HCH3INTEN) 0x16C 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer completed interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH3INTF HCH3INTF host channel-3 interrupt register (HCH3INTF) 0x168 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer finished 0 1 USBER USB bus error 7 1 HCH3LEN HCH3LEN host channel-3 transfer length register 0x170 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 HCH4CTL HCH4CTL host channel-4 characteristics register (HCH4CTL) 0x180 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH4INTEN HCH4INTEN host channel-4 interrupt enable register (HCH4INTEN) 0x18C 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer completed interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH4INTF HCH4INTF host channel-4 interrupt register (HCH4INTF) 0x188 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer finished 0 1 USBER USB bus error 7 1 HCH4LEN HCH4LEN host channel-4 transfer length register 0x190 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 HCH5CTL HCH5CTL host channel-5 characteristics register (HCH5CTL) 0x1A0 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH5INTEN HCH5INTEN host channel-5 interrupt enable register (HCH5INTEN) 0x1AC 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer completed interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH5INTF HCH5INTF host channel-5 interrupt register (HCH5INTF) 0x1A8 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer finished 0 1 USBER USB bus error 7 1 HCH5LEN HCH5LEN host channel-5 transfer length register 0x1B0 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 HCH6CTL HCH6CTL host channel-6 characteristics register (HCH6CTL) 0x1C0 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH6INTEN HCH6INTEN host channel-6 interrupt enable register (HCH6INTEN) 0x1CC 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer completed interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH6INTF HCH6INTF host channel-6 interrupt register (HCH6INTF) 0x1C8 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer finished 0 1 USBER USB bus error 7 1 HCH6LEN HCH6LEN host channel-6 transfer length register 0x1D0 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 HCH7CTL HCH7CTL host channel-7 characteristics register (HCH7CTL) 0x1E0 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH7INTEN HCH7INTEN host channel-7 interrupt enable register (HCH7INTEN) 0x1EC 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer completed interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH7INTF HCH7INTF host channel-7 interrupt register (HCH7INTF) 0x1E8 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer finished 0 1 USBER USB bus error 7 1 HCH7LEN HCH7LEN host channel-7 transfer length register 0x1F0 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 HCTL HCTL host configuration register (HCTL) 0x0 32 read-write n 0x0 0x0 CLKSEL clock select for USB clock 0 2 read-write HFINFR HFINFR OTG_FS host frame number/frame time remaining register (HFINFR) 0x8 32 read-only n 0x0 0x0 FRNUM Frame number 0 16 FRT Frame remaining time 16 16 HFT HFT Host frame interval register 0x4 32 read-write n 0x0 0x0 FRI Frame interval 0 16 HPCS HPCS Host port control and status register (USBFS_HPCS) 0x40 32 read-write n 0x0 0x0 PCD Port connect detected 1 1 read-write PCST Port connect status 0 1 read-only PE Port enable 2 1 read-write PEDC Port enable/disable change 3 1 read-write PLST Port line status 10 2 read-only PP Port power 12 1 read-write PREM Port resume 6 1 read-write PRST Port reset 8 1 read-write PS Port speed 17 2 read-only PSP Port suspend 7 1 read-write HPTFQSTAT HPTFQSTAT Host periodic transmit FIFO/queue status register (HPTFQSTAT) 0x10 32 read-write n 0x0 0x0 PTXFS Periodic transmit data FIFO space available 0 16 read-only PTXREQS Periodic transmit request queue space available 16 8 read-only PTXREQT Top of the periodic transmit request queue 24 8 read-only FS_PWRCLK USB on the go full speed USB_FS 0x0 0x0 0x100 registers n PWRCLKCTL PWRCLKCTL power and clock gating control register (PWRCLKCTL) 0x0 32 read-write n 0x0 0x0 SHCLK Stop HCLK 1 1 SUCLK Stop the USB clock 0 1 FWDGT free watchdog timer FWDGT 0x0 0x0 0x400 registers n CTL CTL Control register 0x0 32 write-only n 0x0 0x0 CMD Key value 0 16 PSC PSC Prescaler register 0x4 32 read-write n 0x0 0x0 PSC Prescaler divider 0 3 RLD RLD Reload register 0x8 32 read-write n 0x0 0x0 RLD Free watchdog timer counter reload value 0 12 STAT STAT Status register 0xC 32 read-only n 0x0 0x0 PUD Free watchdog timer prescaler value update 0 1 RUD Free watchdog timer counter reload value update 1 1 GPIOA General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFSEL0 AFSEL0 GPIO alternate function selected register 0 0x20 32 read-write n 0x0 0x0 SEL0 Port 0 alternate function selected 0 4 SEL1 Port 1 alternate function selected 4 4 SEL2 Port 2 alternate function selected 8 4 SEL3 Port 3 alternate function selected 12 4 SEL4 Port 4 alternate function selected 16 4 SEL5 Port 5 alternate function selected 20 4 SEL6 Port 6 alternate function selected 24 4 SEL7 Port 7 alternate function selected 28 4 AFSEL1 AFSEL1 GPIO alternate function selected register 1 0x24 32 read-write n 0x0 0x0 SEL10 Port 10 alternate function selected 8 4 SEL11 Port 11 alternate function selected 12 4 SEL12 Port 12 alternate function selected 16 4 SEL13 Port 13 alternate function selected 20 4 SEL14 Port 14 alternate function selected 24 4 SEL15 Port 15 alternate function selected 28 4 SEL8 Port 8 alternate function selected 0 4 SEL9 Port 9 alternate function selected 4 4 BC BC Bit clear register 0x28 32 write-only n 0x0 0x0 CR0 Port cleat bit 0 1 CR1 Port cleat bit 1 1 CR10 Port cleat bit 10 1 CR11 Port cleat bit 11 1 CR12 Port cleat bit 12 1 CR13 Port cleat bit 13 1 CR14 Port cleat bit 14 1 CR15 Port cleat bit 15 1 CR2 Port cleat bit 2 1 CR3 Port cleat bit 3 1 CR4 Port cleat bit 4 1 CR5 Port cleat bit 5 1 CR6 Port cleat bit 6 1 CR7 Port cleat bit 7 1 CR8 Port cleat bit 8 1 CR9 Port cleat bit 9 1 BOP BOP GPIO port bit operate register 0x18 32 write-only n 0x0 0x0 BOP0 Port Set bit 0 0 1 BOP1 Port Set bit 1 1 1 BOP10 Port Set bit 10 10 1 BOP11 Port Set bit 11 11 1 BOP12 Port Set bit 12 12 1 BOP13 Port Set bit 13 13 1 BOP14 Port Set bit 14 14 1 BOP15 Port Set bit 15 15 1 BOP2 Port Set bit 2 2 1 BOP3 Port Set bit 3 3 1 BOP4 Port Set bit 4 4 1 BOP5 Port Set bit 5 5 1 BOP6 Port Set bit 6 6 1 BOP7 Port Set bit 7 7 1 BOP8 Port Set bit 8 8 1 BOP9 Port Set bit 9 9 1 CR0 Port Clear bit 0 16 1 CR1 Port Clear bit 1 17 1 CR10 Port Clear bit 10 26 1 CR11 Port Clear bit 11 27 1 CR12 Port Clear bit 12 28 1 CR13 Port Clear bit 13 29 1 CR14 Port Clear bit 14 30 1 CR15 Port Clear bit 15 31 1 CR2 Port Clear bit 2 18 1 CR3 Port Clear bit 3 19 1 CR4 Port Clear bit 4 20 1 CR5 Port Clear bit 5 21 1 CR6 Port Clear bit 6 22 1 CR7 Port Clear bit 7 23 1 CR8 Port Clear bit 8 24 1 CR9 Port Clear bit 9 25 1 CTL CTL GPIO port control register 0x0 32 read-write n 0x0 0x0 CTL0 Port x configuration bits (x = 0) 0 2 CTL1 Port x configuration bits (x = 1) 2 2 CTL10 Port x configuration bits (x = 10) 20 2 CTL11 Port x configuration bits (x = 11) 22 2 CTL12 Port x configuration bits (x = 12) 24 2 CTL13 Port x configuration bits (x = 13) 26 2 CTL14 Port x configuration bits (x = 14) 28 2 CTL15 Port x configuration bits (x = 15) 30 2 CTL2 Port x configuration bits (x = 2) 4 2 CTL3 Port x configuration bits (x = 3) 6 2 CTL4 Port x configuration bits (x = 4 ) 8 2 CTL5 Port x configuration bits (x = 5) 10 2 CTL6 Port x configuration bits (x = 6 ) 12 2 CTL7 Port x configuration bits (x = 7) 14 2 CTL8 Port x configuration bits (x = 8) 16 2 CTL9 Port x configuration bits (x = 9) 18 2 ISTAT ISTAT GPIO port input status register 0x10 32 read-only n 0x0 0x0 ISTAT0 Port input status (y = 0) 0 1 ISTAT1 Port input status (y = 1) 1 1 ISTAT10 Port input status (y = 10) 10 1 ISTAT11 Port input status (y = 11) 11 1 ISTAT12 Port input status (y = 12) 12 1 ISTAT13 Port input status (y = 13) 13 1 ISTAT14 Port input status (y = 14) 14 1 ISTAT15 Port input status (y = 15) 15 1 ISTAT2 Port input status (y = 2) 2 1 ISTAT3 Port input status (y = 3) 3 1 ISTAT4 Port input status (y = 4) 4 1 ISTAT5 Port input status (y = 5) 5 1 ISTAT6 Port input status (y = 6) 6 1 ISTAT7 Port input status (y = 7) 7 1 ISTAT8 Port input status (y = 8) 8 1 ISTAT9 Port input status (y = 9) 9 1 LOCK LOCK GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LK0 Port Lock bit 0 0 1 LK1 Port Lock bit 1 1 1 LK10 Port Lock bit 10 10 1 LK11 Port Lock bit 11 11 1 LK12 Port Lock bit 12 12 1 LK13 Port Lock bit 13 13 1 LK14 Port Lock bit 14 14 1 LK15 Port Lock bit 15 15 1 LK2 Port Lock bit 2 2 1 LK3 Port Lock bit 3 3 1 LK4 Port Lock bit 4 4 1 LK5 Port Lock bit 5 5 1 LK6 Port Lock bit 6 6 1 LK7 Port Lock bit 7 7 1 LK8 Port Lock bit 8 8 1 LK9 Port Lock bit 9 9 1 LKK Lock sequence key 16 1 OCTL OCTL GPIO port output control register 0x14 32 read-write n 0x0 0x0 OCTL0 Port output control (y = 0) 0 1 OCTL1 Port output control (y = 1) 1 1 OCTL10 Port output control (y = 10) 10 1 OCTL11 Port output control (y = 11) 11 1 OCTL12 Port output control (y = 12) 12 1 OCTL13 Port output control (y = 13) 13 1 OCTL14 Port output control (y = 14) 14 1 OCTL15 Port output control (y = 15) 15 1 OCTL2 Port output control (y = 2) 2 1 OCTL3 Port output control (y = 3) 3 1 OCTL4 Port output control (y = 4) 4 1 OCTL5 Port output control (y = 5) 5 1 OCTL6 Port output control (y = 6) 6 1 OCTL7 Port output control (y = 7) 7 1 OCTL8 Port output control (y = 8) 8 1 OCTL9 Port output control (y = 9) 9 1 OMODE OMODE GPIO port output mode register 0x4 32 read-write n 0x0 0x0 OM0 Port 0 output mode bit 0 1 OM1 Port 1 output mode bit 1 1 OM10 Port 10 output mode bit 10 1 OM11 Port 11 output mode bit 11 1 OM12 Port 12 output mode bit 12 1 OM13 Port 13 output mode bit 13 1 OM14 Port 14 output mode bit 14 1 OM15 Port 15 output mode bit 15 1 OM2 Port 2 output mode bit 2 1 OM3 Port 3 output mode bit 3 1 OM4 Port 4 output mode bit 4 1 OM5 Port 5 output mode bit 5 1 OM6 Port 6 output mode bit 6 1 OM7 Port 7 output mode bit 7 1 OM8 Port 8 output mode bit 8 1 OM9 Port 9 output mode bit 9 1 OSPD OSPD GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPD0 Port 0 output max speed bits 0 2 OSPD1 Port 1 output max speed bits 2 2 OSPD10 Port 10 output max speed bits 20 2 OSPD11 Port 11 output max speed bits 22 2 OSPD12 Port 12 output max speed bits 24 2 OSPD13 Port 13 output max speed bits 26 2 OSPD14 Port 14 output max speed bits 28 2 OSPD15 Port 15 output max speed bits 30 2 OSPD2 Port 2 output max speed bits 4 2 OSPD3 Port 3 output max speed bits 6 2 OSPD4 Port 4 output max speed bits 8 2 OSPD5 Port 5 output max speed bits 10 2 OSPD6 Port 6 output max speed bits 12 2 OSPD7 Port 7 output max speed bits 14 2 OSPD8 Port 8 output max speed bits 16 2 OSPD9 Port 9 output max speed bits 18 2 PUD PUD GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUD0 Port 0 pull-up or pull-down bits 0 2 PUD1 Port 1 pull-up or pull-down bits 2 2 PUD10 Port 10 pull-up or pull-down bits 20 2 PUD11 Port 11 pull-up or pull-down bits 22 2 PUD12 Port 12 pull-up or pull-down bits 24 2 PUD13 Port 13 pull-up or pull-down bits 26 2 PUD14 Port 14 pull-up or pull-down bits 28 2 PUD15 Port 15 pull-up or pull-down bits 30 2 PUD2 Port 2 pull-up or pull-down bits 4 2 PUD3 Port 3 pull-up or pull-down bits 6 2 PUD4 Port 4 pull-up or pull-down bits 8 2 PUD5 Port 5 pull-up or pull-down bits 10 2 PUD6 Port 6 pull-up or pull-down bits 12 2 PUD7 Port 7 pull-up or pull-down bits 14 2 PUD8 Port 8 pull-up or pull-down bits 16 2 PUD9 Port 9 pull-up or pull-down bits 18 2 TG TG Port bit toggle register 0x2C 32 write-only n 0x0 0x0 TG0 Port toggle bit 0 1 TG1 Port toggle bit 1 1 TG10 Port toggle bit 10 1 TG11 Port toggle bit 11 1 TG12 Port toggle bit 12 1 TG13 Port toggle bit 13 1 TG14 Port toggle bit 14 1 TG15 Port toggle bit 15 1 TG2 Port toggle bit 2 1 TG3 Port toggle bit 3 1 TG4 Port toggle bit 4 1 TG5 Port toggle bit 5 1 TG6 Port toggle bit 6 1 TG7 Port toggle bit 7 1 TG8 Port toggle bit 8 1 TG9 Port toggle bit 9 1 GPIOB General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFSEL0 AFSEL0 GPIO alternate function selected register 0 0x20 32 read-write n 0x0 0x0 SEL0 Port 0 alternate function selected 0 4 SEL1 Port 1 alternate function selected 4 4 SEL2 Port 2 alternate function selected 8 4 SEL3 Port 3 alternate function selected 12 4 SEL4 Port 4 alternate function selected 16 4 SEL5 Port 5 alternate function selected 20 4 SEL6 Port 6 alternate function selected 24 4 SEL7 Port 7 alternate function selected 28 4 AFSEL1 AFSEL1 GPIO alternate function selected register 1 0x24 32 read-write n 0x0 0x0 SEL10 Port 10 alternate function selected 8 4 SEL11 Port 11 alternate function selected 12 4 SEL12 Port 12 alternate function selected 16 4 SEL13 Port 13 alternate function selected 20 4 SEL14 Port 14 alternate function selected 24 4 SEL15 Port 15 alternate function selected 28 4 SEL8 Port 8 alternate function selected 0 4 SEL9 Port 9 alternate function selected 4 4 BC BC Bit clear register 0x28 32 write-only n 0x0 0x0 CR0 Port cleat bit 0 1 CR1 Port cleat bit 1 1 CR10 Port cleat bit 10 1 CR11 Port cleat bit 11 1 CR12 Port cleat bit 12 1 CR13 Port cleat bit 13 1 CR14 Port cleat bit 14 1 CR15 Port cleat bit 15 1 CR2 Port cleat bit 2 1 CR3 Port cleat bit 3 1 CR4 Port cleat bit 4 1 CR5 Port cleat bit 5 1 CR6 Port cleat bit 6 1 CR7 Port cleat bit 7 1 CR8 Port cleat bit 8 1 CR9 Port cleat bit 9 1 BOP BOP GPIO port bit operate register 0x18 32 write-only n 0x0 0x0 BOP0 Port Set bit 0 0 1 BOP1 Port Set bit 1 1 1 BOP10 Port Set bit 10 10 1 BOP11 Port Set bit 11 11 1 BOP12 Port Set bit 12 12 1 BOP13 Port Set bit 13 13 1 BOP14 Port Set bit 14 14 1 BOP15 Port Set bit 15 15 1 BOP2 Port Set bit 2 2 1 BOP3 Port Set bit 3 3 1 BOP4 Port Set bit 4 4 1 BOP5 Port Set bit 5 5 1 BOP6 Port Set bit 6 6 1 BOP7 Port Set bit 7 7 1 BOP8 Port Set bit 8 8 1 BOP9 Port Set bit 9 9 1 CR0 Port Clear bit 0 16 1 CR1 Port Clear bit 1 17 1 CR10 Port Clear bit 10 26 1 CR11 Port Clear bit 11 27 1 CR12 Port Clear bit 12 28 1 CR13 Port Clear bit 13 29 1 CR14 Port Clear bit 14 30 1 CR15 Port Clear bit 15 31 1 CR2 Port Clear bit 2 18 1 CR3 Port Clear bit 3 19 1 CR4 Port Clear bit 4 20 1 CR5 Port Clear bit 5 21 1 CR6 Port Clear bit 6 22 1 CR7 Port Clear bit 7 23 1 CR8 Port Clear bit 8 24 1 CR9 Port Clear bit 9 25 1 CTL CTL GPIO port control register 0x0 32 read-write n 0x0 0x0 CTL0 Port x configuration bits (x = 0) 0 2 CTL1 Port x configuration bits (x = 1) 2 2 CTL10 Port x configuration bits (x = 10) 20 2 CTL11 Port x configuration bits (x = 11) 22 2 CTL12 Port x configuration bits (x = 12) 24 2 CTL13 Port x configuration bits (x = 13) 26 2 CTL14 Port x configuration bits (x = 14) 28 2 CTL15 Port x configuration bits (x = 15) 30 2 CTL2 Port x configuration bits (x = 2) 4 2 CTL3 Port x configuration bits (x = 3) 6 2 CTL4 Port x configuration bits (x = 4 ) 8 2 CTL5 Port x configuration bits (x = 5) 10 2 CTL6 Port x configuration bits (x = 6 ) 12 2 CTL7 Port x configuration bits (x = 7) 14 2 CTL8 Port x configuration bits (x = 8) 16 2 CTL9 Port x configuration bits (x = 9) 18 2 ISTAT ISTAT GPIO port input status register 0x10 32 read-only n 0x0 0x0 ISTAT0 Port input status (y = 0) 0 1 ISTAT1 Port input status (y = 1) 1 1 ISTAT10 Port input status (y = 10) 10 1 ISTAT11 Port input status (y = 11) 11 1 ISTAT12 Port input status (y = 12) 12 1 ISTAT13 Port input status (y = 13) 13 1 ISTAT14 Port input status (y = 14) 14 1 ISTAT15 Port input status (y = 15) 15 1 ISTAT2 Port input status (y = 2) 2 1 ISTAT3 Port input status (y = 3) 3 1 ISTAT4 Port input status (y = 4) 4 1 ISTAT5 Port input status (y = 5) 5 1 ISTAT6 Port input status (y = 6) 6 1 ISTAT7 Port input status (y = 7) 7 1 ISTAT8 Port input status (y = 8) 8 1 ISTAT9 Port input status (y = 9) 9 1 LOCK LOCK GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LK0 Port Lock bit 0 0 1 LK1 Port Lock bit 1 1 1 LK10 Port Lock bit 10 10 1 LK11 Port Lock bit 11 11 1 LK12 Port Lock bit 12 12 1 LK13 Port Lock bit 13 13 1 LK14 Port Lock bit 14 14 1 LK15 Port Lock bit 15 15 1 LK2 Port Lock bit 2 2 1 LK3 Port Lock bit 3 3 1 LK4 Port Lock bit 4 4 1 LK5 Port Lock bit 5 5 1 LK6 Port Lock bit 6 6 1 LK7 Port Lock bit 7 7 1 LK8 Port Lock bit 8 8 1 LK9 Port Lock bit 9 9 1 LKK Lock sequence key 16 1 OCTL OCTL GPIO port output control register 0x14 32 read-write n 0x0 0x0 OCTL0 Port output control (y = 0) 0 1 OCTL1 Port output control (y = 1) 1 1 OCTL10 Port output control (y = 10) 10 1 OCTL11 Port output control (y = 11) 11 1 OCTL12 Port output control (y = 12) 12 1 OCTL13 Port output control (y = 13) 13 1 OCTL14 Port output control (y = 14) 14 1 OCTL15 Port output control (y = 15) 15 1 OCTL2 Port output control (y = 2) 2 1 OCTL3 Port output control (y = 3) 3 1 OCTL4 Port output control (y = 4) 4 1 OCTL5 Port output control (y = 5) 5 1 OCTL6 Port output control (y = 6) 6 1 OCTL7 Port output control (y = 7) 7 1 OCTL8 Port output control (y = 8) 8 1 OCTL9 Port output control (y = 9) 9 1 OMODE OMODE GPIO port output mode register 0x4 32 read-write n 0x0 0x0 OM0 Port 0 output mode bit 0 1 OM1 Port 1 output mode bit 1 1 OM10 Port 10 output mode bit 10 1 OM11 Port 11 output mode bit 11 1 OM12 Port 12 output mode bit 12 1 OM13 Port 13 output mode bit 13 1 OM14 Port 14 output mode bit 14 1 OM15 Port 15 output mode bit 15 1 OM2 Port 2 output mode bit 2 1 OM3 Port 3 output mode bit 3 1 OM4 Port 4 output mode bit 4 1 OM5 Port 5 output mode bit 5 1 OM6 Port 6 output mode bit 6 1 OM7 Port 7 output mode bit 7 1 OM8 Port 8 output mode bit 8 1 OM9 Port 9 output mode bit 9 1 OSPD OSPD GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPD0 Port 0 output max speed bits 0 2 OSPD1 Port 1 output max speed bits 2 2 OSPD10 Port 10 output max speed bits 20 2 OSPD11 Port 11 output max speed bits 22 2 OSPD12 Port 12 output max speed bits 24 2 OSPD13 Port 13 output max speed bits 26 2 OSPD14 Port 14 output max speed bits 28 2 OSPD15 Port 15 output max speed bits 30 2 OSPD2 Port 2 output max speed bits 4 2 OSPD3 Port 3 output max speed bits 6 2 OSPD4 Port 4 output max speed bits 8 2 OSPD5 Port 5 output max speed bits 10 2 OSPD6 Port 6 output max speed bits 12 2 OSPD7 Port 7 output max speed bits 14 2 OSPD8 Port 8 output max speed bits 16 2 OSPD9 Port 9 output max speed bits 18 2 PUD PUD GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUD0 Port 0 pull-up or pull-down bits 0 2 PUD1 Port 1 pull-up or pull-down bits 2 2 PUD10 Port 10 pull-up or pull-down bits 20 2 PUD11 Port 11 pull-up or pull-down bits 22 2 PUD12 Port 12 pull-up or pull-down bits 24 2 PUD13 Port 13 pull-up or pull-down bits 26 2 PUD14 Port 14 pull-up or pull-down bits 28 2 PUD15 Port 15 pull-up or pull-down bits 30 2 PUD2 Port 2 pull-up or pull-down bits 4 2 PUD3 Port 3 pull-up or pull-down bits 6 2 PUD4 Port 4 pull-up or pull-down bits 8 2 PUD5 Port 5 pull-up or pull-down bits 10 2 PUD6 Port 6 pull-up or pull-down bits 12 2 PUD7 Port 7 pull-up or pull-down bits 14 2 PUD8 Port 8 pull-up or pull-down bits 16 2 PUD9 Port 9 pull-up or pull-down bits 18 2 TG TG Port bit toggle register 0x2C 32 write-only n 0x0 0x0 TG0 Port toggle bit 0 1 TG1 Port toggle bit 1 1 TG10 Port toggle bit 10 1 TG11 Port toggle bit 11 1 TG12 Port toggle bit 12 1 TG13 Port toggle bit 13 1 TG14 Port toggle bit 14 1 TG15 Port toggle bit 15 1 TG2 Port toggle bit 2 1 TG3 Port toggle bit 3 1 TG4 Port toggle bit 4 1 TG5 Port toggle bit 5 1 TG6 Port toggle bit 6 1 TG7 Port toggle bit 7 1 TG8 Port toggle bit 8 1 TG9 Port toggle bit 9 1 GPIOC General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFSEL0 AFSEL0 GPIO alternate function selected register 0 0x20 32 read-write n 0x0 0x0 SEL0 Port 0 alternate function selected 0 4 SEL1 Port 1 alternate function selected 4 4 SEL2 Port 2 alternate function selected 8 4 SEL3 Port 3 alternate function selected 12 4 SEL4 Port 4 alternate function selected 16 4 SEL5 Port 5 alternate function selected 20 4 SEL6 Port 6 alternate function selected 24 4 SEL7 Port 7 alternate function selected 28 4 AFSEL1 AFSEL1 GPIO alternate function selected register 1 0x24 32 read-write n 0x0 0x0 SEL10 Port 10 alternate function selected 8 4 SEL11 Port 11 alternate function selected 12 4 SEL12 Port 12 alternate function selected 16 4 SEL13 Port 13 alternate function selected 20 4 SEL14 Port 14 alternate function selected 24 4 SEL15 Port 15 alternate function selected 28 4 SEL8 Port 8 alternate function selected 0 4 SEL9 Port 9 alternate function selected 4 4 BC BC Bit clear register 0x28 32 write-only n 0x0 0x0 CR0 Port cleat bit 0 1 CR1 Port cleat bit 1 1 CR10 Port cleat bit 10 1 CR11 Port cleat bit 11 1 CR12 Port cleat bit 12 1 CR13 Port cleat bit 13 1 CR14 Port cleat bit 14 1 CR15 Port cleat bit 15 1 CR2 Port cleat bit 2 1 CR3 Port cleat bit 3 1 CR4 Port cleat bit 4 1 CR5 Port cleat bit 5 1 CR6 Port cleat bit 6 1 CR7 Port cleat bit 7 1 CR8 Port cleat bit 8 1 CR9 Port cleat bit 9 1 BOP BOP GPIO port bit operate register 0x18 32 write-only n 0x0 0x0 BOP0 Port Set bit 0 0 1 BOP1 Port Set bit 1 1 1 BOP10 Port Set bit 10 10 1 BOP11 Port Set bit 11 11 1 BOP12 Port Set bit 12 12 1 BOP13 Port Set bit 13 13 1 BOP14 Port Set bit 14 14 1 BOP15 Port Set bit 15 15 1 BOP2 Port Set bit 2 2 1 BOP3 Port Set bit 3 3 1 BOP4 Port Set bit 4 4 1 BOP5 Port Set bit 5 5 1 BOP6 Port Set bit 6 6 1 BOP7 Port Set bit 7 7 1 BOP8 Port Set bit 8 8 1 BOP9 Port Set bit 9 9 1 CR0 Port Clear bit 0 16 1 CR1 Port Clear bit 1 17 1 CR10 Port Clear bit 10 26 1 CR11 Port Clear bit 11 27 1 CR12 Port Clear bit 12 28 1 CR13 Port Clear bit 13 29 1 CR14 Port Clear bit 14 30 1 CR15 Port Clear bit 15 31 1 CR2 Port Clear bit 2 18 1 CR3 Port Clear bit 3 19 1 CR4 Port Clear bit 4 20 1 CR5 Port Clear bit 5 21 1 CR6 Port Clear bit 6 22 1 CR7 Port Clear bit 7 23 1 CR8 Port Clear bit 8 24 1 CR9 Port Clear bit 9 25 1 CTL CTL GPIO port control register 0x0 32 read-write n 0x0 0x0 CTL0 Port x configuration bits (x = 0) 0 2 CTL1 Port x configuration bits (x = 1) 2 2 CTL10 Port x configuration bits (x = 10) 20 2 CTL11 Port x configuration bits (x = 11) 22 2 CTL12 Port x configuration bits (x = 12) 24 2 CTL13 Port x configuration bits (x = 13) 26 2 CTL14 Port x configuration bits (x = 14) 28 2 CTL15 Port x configuration bits (x = 15) 30 2 CTL2 Port x configuration bits (x = 2) 4 2 CTL3 Port x configuration bits (x = 3) 6 2 CTL4 Port x configuration bits (x = 4 ) 8 2 CTL5 Port x configuration bits (x = 5) 10 2 CTL6 Port x configuration bits (x = 6 ) 12 2 CTL7 Port x configuration bits (x = 7) 14 2 CTL8 Port x configuration bits (x = 8) 16 2 CTL9 Port x configuration bits (x = 9) 18 2 ISTAT ISTAT GPIO port input status register 0x10 32 read-only n 0x0 0x0 ISTAT0 Port input status (y = 0) 0 1 ISTAT1 Port input status (y = 1) 1 1 ISTAT10 Port input status (y = 10) 10 1 ISTAT11 Port input status (y = 11) 11 1 ISTAT12 Port input status (y = 12) 12 1 ISTAT13 Port input status (y = 13) 13 1 ISTAT14 Port input status (y = 14) 14 1 ISTAT15 Port input status (y = 15) 15 1 ISTAT2 Port input status (y = 2) 2 1 ISTAT3 Port input status (y = 3) 3 1 ISTAT4 Port input status (y = 4) 4 1 ISTAT5 Port input status (y = 5) 5 1 ISTAT6 Port input status (y = 6) 6 1 ISTAT7 Port input status (y = 7) 7 1 ISTAT8 Port input status (y = 8) 8 1 ISTAT9 Port input status (y = 9) 9 1 LOCK LOCK GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LK0 Port Lock bit 0 0 1 LK1 Port Lock bit 1 1 1 LK10 Port Lock bit 10 10 1 LK11 Port Lock bit 11 11 1 LK12 Port Lock bit 12 12 1 LK13 Port Lock bit 13 13 1 LK14 Port Lock bit 14 14 1 LK15 Port Lock bit 15 15 1 LK2 Port Lock bit 2 2 1 LK3 Port Lock bit 3 3 1 LK4 Port Lock bit 4 4 1 LK5 Port Lock bit 5 5 1 LK6 Port Lock bit 6 6 1 LK7 Port Lock bit 7 7 1 LK8 Port Lock bit 8 8 1 LK9 Port Lock bit 9 9 1 LKK Lock sequence key 16 1 OCTL OCTL GPIO port output control register 0x14 32 read-write n 0x0 0x0 OCTL0 Port output control (y = 0) 0 1 OCTL1 Port output control (y = 1) 1 1 OCTL10 Port output control (y = 10) 10 1 OCTL11 Port output control (y = 11) 11 1 OCTL12 Port output control (y = 12) 12 1 OCTL13 Port output control (y = 13) 13 1 OCTL14 Port output control (y = 14) 14 1 OCTL15 Port output control (y = 15) 15 1 OCTL2 Port output control (y = 2) 2 1 OCTL3 Port output control (y = 3) 3 1 OCTL4 Port output control (y = 4) 4 1 OCTL5 Port output control (y = 5) 5 1 OCTL6 Port output control (y = 6) 6 1 OCTL7 Port output control (y = 7) 7 1 OCTL8 Port output control (y = 8) 8 1 OCTL9 Port output control (y = 9) 9 1 OMODE OMODE GPIO port output mode register 0x4 32 read-write n 0x0 0x0 OM0 Port 0 output mode bit 0 1 OM1 Port 1 output mode bit 1 1 OM10 Port 10 output mode bit 10 1 OM11 Port 11 output mode bit 11 1 OM12 Port 12 output mode bit 12 1 OM13 Port 13 output mode bit 13 1 OM14 Port 14 output mode bit 14 1 OM15 Port 15 output mode bit 15 1 OM2 Port 2 output mode bit 2 1 OM3 Port 3 output mode bit 3 1 OM4 Port 4 output mode bit 4 1 OM5 Port 5 output mode bit 5 1 OM6 Port 6 output mode bit 6 1 OM7 Port 7 output mode bit 7 1 OM8 Port 8 output mode bit 8 1 OM9 Port 9 output mode bit 9 1 OSPD OSPD GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPD0 Port 0 output max speed bits 0 2 OSPD1 Port 1 output max speed bits 2 2 OSPD10 Port 10 output max speed bits 20 2 OSPD11 Port 11 output max speed bits 22 2 OSPD12 Port 12 output max speed bits 24 2 OSPD13 Port 13 output max speed bits 26 2 OSPD14 Port 14 output max speed bits 28 2 OSPD15 Port 15 output max speed bits 30 2 OSPD2 Port 2 output max speed bits 4 2 OSPD3 Port 3 output max speed bits 6 2 OSPD4 Port 4 output max speed bits 8 2 OSPD5 Port 5 output max speed bits 10 2 OSPD6 Port 6 output max speed bits 12 2 OSPD7 Port 7 output max speed bits 14 2 OSPD8 Port 8 output max speed bits 16 2 OSPD9 Port 9 output max speed bits 18 2 PUD PUD GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUD0 Port 0 pull-up or pull-down bits 0 2 PUD1 Port 1 pull-up or pull-down bits 2 2 PUD10 Port 10 pull-up or pull-down bits 20 2 PUD11 Port 11 pull-up or pull-down bits 22 2 PUD12 Port 12 pull-up or pull-down bits 24 2 PUD13 Port 13 pull-up or pull-down bits 26 2 PUD14 Port 14 pull-up or pull-down bits 28 2 PUD15 Port 15 pull-up or pull-down bits 30 2 PUD2 Port 2 pull-up or pull-down bits 4 2 PUD3 Port 3 pull-up or pull-down bits 6 2 PUD4 Port 4 pull-up or pull-down bits 8 2 PUD5 Port 5 pull-up or pull-down bits 10 2 PUD6 Port 6 pull-up or pull-down bits 12 2 PUD7 Port 7 pull-up or pull-down bits 14 2 PUD8 Port 8 pull-up or pull-down bits 16 2 PUD9 Port 9 pull-up or pull-down bits 18 2 TG TG Port bit toggle register 0x2C 32 write-only n 0x0 0x0 TG0 Port toggle bit 0 1 TG1 Port toggle bit 1 1 TG10 Port toggle bit 10 1 TG11 Port toggle bit 11 1 TG12 Port toggle bit 12 1 TG13 Port toggle bit 13 1 TG14 Port toggle bit 14 1 TG15 Port toggle bit 15 1 TG2 Port toggle bit 2 1 TG3 Port toggle bit 3 1 TG4 Port toggle bit 4 1 TG5 Port toggle bit 5 1 TG6 Port toggle bit 6 1 TG7 Port toggle bit 7 1 TG8 Port toggle bit 8 1 TG9 Port toggle bit 9 1 GPIOD General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFSEL0 AFSEL0 GPIO alternate function selected register 0 0x20 32 read-write n 0x0 0x0 SEL0 Port 0 alternate function selected 0 4 SEL1 Port 1 alternate function selected 4 4 SEL2 Port 2 alternate function selected 8 4 SEL3 Port 3 alternate function selected 12 4 SEL4 Port 4 alternate function selected 16 4 SEL5 Port 5 alternate function selected 20 4 SEL6 Port 6 alternate function selected 24 4 SEL7 Port 7 alternate function selected 28 4 AFSEL1 AFSEL1 GPIO alternate function selected register 1 0x24 32 read-write n 0x0 0x0 SEL10 Port 10 alternate function selected 8 4 SEL11 Port 11 alternate function selected 12 4 SEL12 Port 12 alternate function selected 16 4 SEL13 Port 13 alternate function selected 20 4 SEL14 Port 14 alternate function selected 24 4 SEL15 Port 15 alternate function selected 28 4 SEL8 Port 8 alternate function selected 0 4 SEL9 Port 9 alternate function selected 4 4 BC BC Bit clear register 0x28 32 write-only n 0x0 0x0 CR0 Port cleat bit 0 1 CR1 Port cleat bit 1 1 CR10 Port cleat bit 10 1 CR11 Port cleat bit 11 1 CR12 Port cleat bit 12 1 CR13 Port cleat bit 13 1 CR14 Port cleat bit 14 1 CR15 Port cleat bit 15 1 CR2 Port cleat bit 2 1 CR3 Port cleat bit 3 1 CR4 Port cleat bit 4 1 CR5 Port cleat bit 5 1 CR6 Port cleat bit 6 1 CR7 Port cleat bit 7 1 CR8 Port cleat bit 8 1 CR9 Port cleat bit 9 1 BOP BOP GPIO port bit operate register 0x18 32 write-only n 0x0 0x0 BOP0 Port Set bit 0 0 1 BOP1 Port Set bit 1 1 1 BOP10 Port Set bit 10 10 1 BOP11 Port Set bit 11 11 1 BOP12 Port Set bit 12 12 1 BOP13 Port Set bit 13 13 1 BOP14 Port Set bit 14 14 1 BOP15 Port Set bit 15 15 1 BOP2 Port Set bit 2 2 1 BOP3 Port Set bit 3 3 1 BOP4 Port Set bit 4 4 1 BOP5 Port Set bit 5 5 1 BOP6 Port Set bit 6 6 1 BOP7 Port Set bit 7 7 1 BOP8 Port Set bit 8 8 1 BOP9 Port Set bit 9 9 1 CR0 Port Clear bit 0 16 1 CR1 Port Clear bit 1 17 1 CR10 Port Clear bit 10 26 1 CR11 Port Clear bit 11 27 1 CR12 Port Clear bit 12 28 1 CR13 Port Clear bit 13 29 1 CR14 Port Clear bit 14 30 1 CR15 Port Clear bit 15 31 1 CR2 Port Clear bit 2 18 1 CR3 Port Clear bit 3 19 1 CR4 Port Clear bit 4 20 1 CR5 Port Clear bit 5 21 1 CR6 Port Clear bit 6 22 1 CR7 Port Clear bit 7 23 1 CR8 Port Clear bit 8 24 1 CR9 Port Clear bit 9 25 1 CTL CTL GPIO port control register 0x0 32 read-write n 0x0 0x0 CTL0 Port x configuration bits (x = 0) 0 2 CTL1 Port x configuration bits (x = 1) 2 2 CTL10 Port x configuration bits (x = 10) 20 2 CTL11 Port x configuration bits (x = 11) 22 2 CTL12 Port x configuration bits (x = 12) 24 2 CTL13 Port x configuration bits (x = 13) 26 2 CTL14 Port x configuration bits (x = 14) 28 2 CTL15 Port x configuration bits (x = 15) 30 2 CTL2 Port x configuration bits (x = 2) 4 2 CTL3 Port x configuration bits (x = 3) 6 2 CTL4 Port x configuration bits (x = 4 ) 8 2 CTL5 Port x configuration bits (x = 5) 10 2 CTL6 Port x configuration bits (x = 6 ) 12 2 CTL7 Port x configuration bits (x = 7) 14 2 CTL8 Port x configuration bits (x = 8) 16 2 CTL9 Port x configuration bits (x = 9) 18 2 ISTAT ISTAT GPIO port input status register 0x10 32 read-only n 0x0 0x0 ISTAT0 Port input status (y = 0) 0 1 ISTAT1 Port input status (y = 1) 1 1 ISTAT10 Port input status (y = 10) 10 1 ISTAT11 Port input status (y = 11) 11 1 ISTAT12 Port input status (y = 12) 12 1 ISTAT13 Port input status (y = 13) 13 1 ISTAT14 Port input status (y = 14) 14 1 ISTAT15 Port input status (y = 15) 15 1 ISTAT2 Port input status (y = 2) 2 1 ISTAT3 Port input status (y = 3) 3 1 ISTAT4 Port input status (y = 4) 4 1 ISTAT5 Port input status (y = 5) 5 1 ISTAT6 Port input status (y = 6) 6 1 ISTAT7 Port input status (y = 7) 7 1 ISTAT8 Port input status (y = 8) 8 1 ISTAT9 Port input status (y = 9) 9 1 LOCK LOCK GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LK0 Port Lock bit 0 0 1 LK1 Port Lock bit 1 1 1 LK10 Port Lock bit 10 10 1 LK11 Port Lock bit 11 11 1 LK12 Port Lock bit 12 12 1 LK13 Port Lock bit 13 13 1 LK14 Port Lock bit 14 14 1 LK15 Port Lock bit 15 15 1 LK2 Port Lock bit 2 2 1 LK3 Port Lock bit 3 3 1 LK4 Port Lock bit 4 4 1 LK5 Port Lock bit 5 5 1 LK6 Port Lock bit 6 6 1 LK7 Port Lock bit 7 7 1 LK8 Port Lock bit 8 8 1 LK9 Port Lock bit 9 9 1 LKK Lock sequence key 16 1 OCTL OCTL GPIO port output control register 0x14 32 read-write n 0x0 0x0 OCTL0 Port output control (y = 0) 0 1 OCTL1 Port output control (y = 1) 1 1 OCTL10 Port output control (y = 10) 10 1 OCTL11 Port output control (y = 11) 11 1 OCTL12 Port output control (y = 12) 12 1 OCTL13 Port output control (y = 13) 13 1 OCTL14 Port output control (y = 14) 14 1 OCTL15 Port output control (y = 15) 15 1 OCTL2 Port output control (y = 2) 2 1 OCTL3 Port output control (y = 3) 3 1 OCTL4 Port output control (y = 4) 4 1 OCTL5 Port output control (y = 5) 5 1 OCTL6 Port output control (y = 6) 6 1 OCTL7 Port output control (y = 7) 7 1 OCTL8 Port output control (y = 8) 8 1 OCTL9 Port output control (y = 9) 9 1 OMODE OMODE GPIO port output mode register 0x4 32 read-write n 0x0 0x0 OM0 Port 0 output mode bit 0 1 OM1 Port 1 output mode bit 1 1 OM10 Port 10 output mode bit 10 1 OM11 Port 11 output mode bit 11 1 OM12 Port 12 output mode bit 12 1 OM13 Port 13 output mode bit 13 1 OM14 Port 14 output mode bit 14 1 OM15 Port 15 output mode bit 15 1 OM2 Port 2 output mode bit 2 1 OM3 Port 3 output mode bit 3 1 OM4 Port 4 output mode bit 4 1 OM5 Port 5 output mode bit 5 1 OM6 Port 6 output mode bit 6 1 OM7 Port 7 output mode bit 7 1 OM8 Port 8 output mode bit 8 1 OM9 Port 9 output mode bit 9 1 OSPD OSPD GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPD0 Port 0 output max speed bits 0 2 OSPD1 Port 1 output max speed bits 2 2 OSPD10 Port 10 output max speed bits 20 2 OSPD11 Port 11 output max speed bits 22 2 OSPD12 Port 12 output max speed bits 24 2 OSPD13 Port 13 output max speed bits 26 2 OSPD14 Port 14 output max speed bits 28 2 OSPD15 Port 15 output max speed bits 30 2 OSPD2 Port 2 output max speed bits 4 2 OSPD3 Port 3 output max speed bits 6 2 OSPD4 Port 4 output max speed bits 8 2 OSPD5 Port 5 output max speed bits 10 2 OSPD6 Port 6 output max speed bits 12 2 OSPD7 Port 7 output max speed bits 14 2 OSPD8 Port 8 output max speed bits 16 2 OSPD9 Port 9 output max speed bits 18 2 PUD PUD GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUD0 Port 0 pull-up or pull-down bits 0 2 PUD1 Port 1 pull-up or pull-down bits 2 2 PUD10 Port 10 pull-up or pull-down bits 20 2 PUD11 Port 11 pull-up or pull-down bits 22 2 PUD12 Port 12 pull-up or pull-down bits 24 2 PUD13 Port 13 pull-up or pull-down bits 26 2 PUD14 Port 14 pull-up or pull-down bits 28 2 PUD15 Port 15 pull-up or pull-down bits 30 2 PUD2 Port 2 pull-up or pull-down bits 4 2 PUD3 Port 3 pull-up or pull-down bits 6 2 PUD4 Port 4 pull-up or pull-down bits 8 2 PUD5 Port 5 pull-up or pull-down bits 10 2 PUD6 Port 6 pull-up or pull-down bits 12 2 PUD7 Port 7 pull-up or pull-down bits 14 2 PUD8 Port 8 pull-up or pull-down bits 16 2 PUD9 Port 9 pull-up or pull-down bits 18 2 TG TG Port bit toggle register 0x2C 32 write-only n 0x0 0x0 TG0 Port toggle bit 0 1 TG1 Port toggle bit 1 1 TG10 Port toggle bit 10 1 TG11 Port toggle bit 11 1 TG12 Port toggle bit 12 1 TG13 Port toggle bit 13 1 TG14 Port toggle bit 14 1 TG15 Port toggle bit 15 1 TG2 Port toggle bit 2 1 TG3 Port toggle bit 3 1 TG4 Port toggle bit 4 1 TG5 Port toggle bit 5 1 TG6 Port toggle bit 6 1 TG7 Port toggle bit 7 1 TG8 Port toggle bit 8 1 TG9 Port toggle bit 9 1 GPIOE General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFSEL0 AFSEL0 GPIO alternate function selected register 0 0x20 32 read-write n 0x0 0x0 SEL0 Port 0 alternate function selected 0 4 SEL1 Port 1 alternate function selected 4 4 SEL2 Port 2 alternate function selected 8 4 SEL3 Port 3 alternate function selected 12 4 SEL4 Port 4 alternate function selected 16 4 SEL5 Port 5 alternate function selected 20 4 SEL6 Port 6 alternate function selected 24 4 SEL7 Port 7 alternate function selected 28 4 AFSEL1 AFSEL1 GPIO alternate function selected register 1 0x24 32 read-write n 0x0 0x0 SEL10 Port 10 alternate function selected 8 4 SEL11 Port 11 alternate function selected 12 4 SEL12 Port 12 alternate function selected 16 4 SEL13 Port 13 alternate function selected 20 4 SEL14 Port 14 alternate function selected 24 4 SEL15 Port 15 alternate function selected 28 4 SEL8 Port 8 alternate function selected 0 4 SEL9 Port 9 alternate function selected 4 4 BC BC Bit clear register 0x28 32 write-only n 0x0 0x0 CR0 Port cleat bit 0 1 CR1 Port cleat bit 1 1 CR10 Port cleat bit 10 1 CR11 Port cleat bit 11 1 CR12 Port cleat bit 12 1 CR13 Port cleat bit 13 1 CR14 Port cleat bit 14 1 CR15 Port cleat bit 15 1 CR2 Port cleat bit 2 1 CR3 Port cleat bit 3 1 CR4 Port cleat bit 4 1 CR5 Port cleat bit 5 1 CR6 Port cleat bit 6 1 CR7 Port cleat bit 7 1 CR8 Port cleat bit 8 1 CR9 Port cleat bit 9 1 BOP BOP GPIO port bit operate register 0x18 32 write-only n 0x0 0x0 BOP0 Port Set bit 0 0 1 BOP1 Port Set bit 1 1 1 BOP10 Port Set bit 10 10 1 BOP11 Port Set bit 11 11 1 BOP12 Port Set bit 12 12 1 BOP13 Port Set bit 13 13 1 BOP14 Port Set bit 14 14 1 BOP15 Port Set bit 15 15 1 BOP2 Port Set bit 2 2 1 BOP3 Port Set bit 3 3 1 BOP4 Port Set bit 4 4 1 BOP5 Port Set bit 5 5 1 BOP6 Port Set bit 6 6 1 BOP7 Port Set bit 7 7 1 BOP8 Port Set bit 8 8 1 BOP9 Port Set bit 9 9 1 CR0 Port Clear bit 0 16 1 CR1 Port Clear bit 1 17 1 CR10 Port Clear bit 10 26 1 CR11 Port Clear bit 11 27 1 CR12 Port Clear bit 12 28 1 CR13 Port Clear bit 13 29 1 CR14 Port Clear bit 14 30 1 CR15 Port Clear bit 15 31 1 CR2 Port Clear bit 2 18 1 CR3 Port Clear bit 3 19 1 CR4 Port Clear bit 4 20 1 CR5 Port Clear bit 5 21 1 CR6 Port Clear bit 6 22 1 CR7 Port Clear bit 7 23 1 CR8 Port Clear bit 8 24 1 CR9 Port Clear bit 9 25 1 CTL CTL GPIO port control register 0x0 32 read-write n 0x0 0x0 CTL0 Port x configuration bits (x = 0) 0 2 CTL1 Port x configuration bits (x = 1) 2 2 CTL10 Port x configuration bits (x = 10) 20 2 CTL11 Port x configuration bits (x = 11) 22 2 CTL12 Port x configuration bits (x = 12) 24 2 CTL13 Port x configuration bits (x = 13) 26 2 CTL14 Port x configuration bits (x = 14) 28 2 CTL15 Port x configuration bits (x = 15) 30 2 CTL2 Port x configuration bits (x = 2) 4 2 CTL3 Port x configuration bits (x = 3) 6 2 CTL4 Port x configuration bits (x = 4 ) 8 2 CTL5 Port x configuration bits (x = 5) 10 2 CTL6 Port x configuration bits (x = 6 ) 12 2 CTL7 Port x configuration bits (x = 7) 14 2 CTL8 Port x configuration bits (x = 8) 16 2 CTL9 Port x configuration bits (x = 9) 18 2 ISTAT ISTAT GPIO port input status register 0x10 32 read-only n 0x0 0x0 ISTAT0 Port input status (y = 0) 0 1 ISTAT1 Port input status (y = 1) 1 1 ISTAT10 Port input status (y = 10) 10 1 ISTAT11 Port input status (y = 11) 11 1 ISTAT12 Port input status (y = 12) 12 1 ISTAT13 Port input status (y = 13) 13 1 ISTAT14 Port input status (y = 14) 14 1 ISTAT15 Port input status (y = 15) 15 1 ISTAT2 Port input status (y = 2) 2 1 ISTAT3 Port input status (y = 3) 3 1 ISTAT4 Port input status (y = 4) 4 1 ISTAT5 Port input status (y = 5) 5 1 ISTAT6 Port input status (y = 6) 6 1 ISTAT7 Port input status (y = 7) 7 1 ISTAT8 Port input status (y = 8) 8 1 ISTAT9 Port input status (y = 9) 9 1 LOCK LOCK GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LK0 Port Lock bit 0 0 1 LK1 Port Lock bit 1 1 1 LK10 Port Lock bit 10 10 1 LK11 Port Lock bit 11 11 1 LK12 Port Lock bit 12 12 1 LK13 Port Lock bit 13 13 1 LK14 Port Lock bit 14 14 1 LK15 Port Lock bit 15 15 1 LK2 Port Lock bit 2 2 1 LK3 Port Lock bit 3 3 1 LK4 Port Lock bit 4 4 1 LK5 Port Lock bit 5 5 1 LK6 Port Lock bit 6 6 1 LK7 Port Lock bit 7 7 1 LK8 Port Lock bit 8 8 1 LK9 Port Lock bit 9 9 1 LKK Lock sequence key 16 1 OCTL OCTL GPIO port output control register 0x14 32 read-write n 0x0 0x0 OCTL0 Port output control (y = 0) 0 1 OCTL1 Port output control (y = 1) 1 1 OCTL10 Port output control (y = 10) 10 1 OCTL11 Port output control (y = 11) 11 1 OCTL12 Port output control (y = 12) 12 1 OCTL13 Port output control (y = 13) 13 1 OCTL14 Port output control (y = 14) 14 1 OCTL15 Port output control (y = 15) 15 1 OCTL2 Port output control (y = 2) 2 1 OCTL3 Port output control (y = 3) 3 1 OCTL4 Port output control (y = 4) 4 1 OCTL5 Port output control (y = 5) 5 1 OCTL6 Port output control (y = 6) 6 1 OCTL7 Port output control (y = 7) 7 1 OCTL8 Port output control (y = 8) 8 1 OCTL9 Port output control (y = 9) 9 1 OMODE OMODE GPIO port output mode register 0x4 32 read-write n 0x0 0x0 OM0 Port 0 output mode bit 0 1 OM1 Port 1 output mode bit 1 1 OM10 Port 10 output mode bit 10 1 OM11 Port 11 output mode bit 11 1 OM12 Port 12 output mode bit 12 1 OM13 Port 13 output mode bit 13 1 OM14 Port 14 output mode bit 14 1 OM15 Port 15 output mode bit 15 1 OM2 Port 2 output mode bit 2 1 OM3 Port 3 output mode bit 3 1 OM4 Port 4 output mode bit 4 1 OM5 Port 5 output mode bit 5 1 OM6 Port 6 output mode bit 6 1 OM7 Port 7 output mode bit 7 1 OM8 Port 8 output mode bit 8 1 OM9 Port 9 output mode bit 9 1 OSPD OSPD GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPD0 Port 0 output max speed bits 0 2 OSPD1 Port 1 output max speed bits 2 2 OSPD10 Port 10 output max speed bits 20 2 OSPD11 Port 11 output max speed bits 22 2 OSPD12 Port 12 output max speed bits 24 2 OSPD13 Port 13 output max speed bits 26 2 OSPD14 Port 14 output max speed bits 28 2 OSPD15 Port 15 output max speed bits 30 2 OSPD2 Port 2 output max speed bits 4 2 OSPD3 Port 3 output max speed bits 6 2 OSPD4 Port 4 output max speed bits 8 2 OSPD5 Port 5 output max speed bits 10 2 OSPD6 Port 6 output max speed bits 12 2 OSPD7 Port 7 output max speed bits 14 2 OSPD8 Port 8 output max speed bits 16 2 OSPD9 Port 9 output max speed bits 18 2 PUD PUD GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUD0 Port 0 pull-up or pull-down bits 0 2 PUD1 Port 1 pull-up or pull-down bits 2 2 PUD10 Port 10 pull-up or pull-down bits 20 2 PUD11 Port 11 pull-up or pull-down bits 22 2 PUD12 Port 12 pull-up or pull-down bits 24 2 PUD13 Port 13 pull-up or pull-down bits 26 2 PUD14 Port 14 pull-up or pull-down bits 28 2 PUD15 Port 15 pull-up or pull-down bits 30 2 PUD2 Port 2 pull-up or pull-down bits 4 2 PUD3 Port 3 pull-up or pull-down bits 6 2 PUD4 Port 4 pull-up or pull-down bits 8 2 PUD5 Port 5 pull-up or pull-down bits 10 2 PUD6 Port 6 pull-up or pull-down bits 12 2 PUD7 Port 7 pull-up or pull-down bits 14 2 PUD8 Port 8 pull-up or pull-down bits 16 2 PUD9 Port 9 pull-up or pull-down bits 18 2 TG TG Port bit toggle register 0x2C 32 write-only n 0x0 0x0 TG0 Port toggle bit 0 1 TG1 Port toggle bit 1 1 TG10 Port toggle bit 10 1 TG11 Port toggle bit 11 1 TG12 Port toggle bit 12 1 TG13 Port toggle bit 13 1 TG14 Port toggle bit 14 1 TG15 Port toggle bit 15 1 TG2 Port toggle bit 2 1 TG3 Port toggle bit 3 1 TG4 Port toggle bit 4 1 TG5 Port toggle bit 5 1 TG6 Port toggle bit 6 1 TG7 Port toggle bit 7 1 TG8 Port toggle bit 8 1 TG9 Port toggle bit 9 1 GPIOF General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFSEL0 AFSEL0 GPIO alternate function selected register 0 0x20 32 read-write n 0x0 0x0 SEL0 Port 0 alternate function selected 0 4 SEL1 Port 1 alternate function selected 4 4 SEL2 Port 2 alternate function selected 8 4 SEL3 Port 3 alternate function selected 12 4 SEL4 Port 4 alternate function selected 16 4 SEL5 Port 5 alternate function selected 20 4 SEL6 Port 6 alternate function selected 24 4 SEL7 Port 7 alternate function selected 28 4 AFSEL1 AFSEL1 GPIO alternate function selected register 1 0x24 32 read-write n 0x0 0x0 SEL10 Port 10 alternate function selected 8 4 SEL11 Port 11 alternate function selected 12 4 SEL12 Port 12 alternate function selected 16 4 SEL13 Port 13 alternate function selected 20 4 SEL14 Port 14 alternate function selected 24 4 SEL15 Port 15 alternate function selected 28 4 SEL8 Port 8 alternate function selected 0 4 SEL9 Port 9 alternate function selected 4 4 BC BC Bit clear register 0x28 32 write-only n 0x0 0x0 CR0 Port cleat bit 0 1 CR1 Port cleat bit 1 1 CR10 Port cleat bit 10 1 CR11 Port cleat bit 11 1 CR12 Port cleat bit 12 1 CR13 Port cleat bit 13 1 CR14 Port cleat bit 14 1 CR15 Port cleat bit 15 1 CR2 Port cleat bit 2 1 CR3 Port cleat bit 3 1 CR4 Port cleat bit 4 1 CR5 Port cleat bit 5 1 CR6 Port cleat bit 6 1 CR7 Port cleat bit 7 1 CR8 Port cleat bit 8 1 CR9 Port cleat bit 9 1 BOP BOP GPIO port bit operate register 0x18 32 write-only n 0x0 0x0 BOP0 Port Set bit 0 0 1 BOP1 Port Set bit 1 1 1 BOP10 Port Set bit 10 10 1 BOP11 Port Set bit 11 11 1 BOP12 Port Set bit 12 12 1 BOP13 Port Set bit 13 13 1 BOP14 Port Set bit 14 14 1 BOP15 Port Set bit 15 15 1 BOP2 Port Set bit 2 2 1 BOP3 Port Set bit 3 3 1 BOP4 Port Set bit 4 4 1 BOP5 Port Set bit 5 5 1 BOP6 Port Set bit 6 6 1 BOP7 Port Set bit 7 7 1 BOP8 Port Set bit 8 8 1 BOP9 Port Set bit 9 9 1 CR0 Port Clear bit 0 16 1 CR1 Port Clear bit 1 17 1 CR10 Port Clear bit 10 26 1 CR11 Port Clear bit 11 27 1 CR12 Port Clear bit 12 28 1 CR13 Port Clear bit 13 29 1 CR14 Port Clear bit 14 30 1 CR15 Port Clear bit 15 31 1 CR2 Port Clear bit 2 18 1 CR3 Port Clear bit 3 19 1 CR4 Port Clear bit 4 20 1 CR5 Port Clear bit 5 21 1 CR6 Port Clear bit 6 22 1 CR7 Port Clear bit 7 23 1 CR8 Port Clear bit 8 24 1 CR9 Port Clear bit 9 25 1 CTL CTL GPIO port control register 0x0 32 read-write n 0x0 0x0 CTL0 Port x configuration bits (x = 0) 0 2 CTL1 Port x configuration bits (x = 1) 2 2 CTL10 Port x configuration bits (x = 10) 20 2 CTL11 Port x configuration bits (x = 11) 22 2 CTL12 Port x configuration bits (x = 12) 24 2 CTL13 Port x configuration bits (x = 13) 26 2 CTL14 Port x configuration bits (x = 14) 28 2 CTL15 Port x configuration bits (x = 15) 30 2 CTL2 Port x configuration bits (x = 2) 4 2 CTL3 Port x configuration bits (x = 3) 6 2 CTL4 Port x configuration bits (x = 4 ) 8 2 CTL5 Port x configuration bits (x = 5) 10 2 CTL6 Port x configuration bits (x = 6 ) 12 2 CTL7 Port x configuration bits (x = 7) 14 2 CTL8 Port x configuration bits (x = 8) 16 2 CTL9 Port x configuration bits (x = 9) 18 2 ISTAT ISTAT GPIO port input status register 0x10 32 read-only n 0x0 0x0 ISTAT0 Port input status (y = 0) 0 1 ISTAT1 Port input status (y = 1) 1 1 ISTAT10 Port input status (y = 10) 10 1 ISTAT11 Port input status (y = 11) 11 1 ISTAT12 Port input status (y = 12) 12 1 ISTAT13 Port input status (y = 13) 13 1 ISTAT14 Port input status (y = 14) 14 1 ISTAT15 Port input status (y = 15) 15 1 ISTAT2 Port input status (y = 2) 2 1 ISTAT3 Port input status (y = 3) 3 1 ISTAT4 Port input status (y = 4) 4 1 ISTAT5 Port input status (y = 5) 5 1 ISTAT6 Port input status (y = 6) 6 1 ISTAT7 Port input status (y = 7) 7 1 ISTAT8 Port input status (y = 8) 8 1 ISTAT9 Port input status (y = 9) 9 1 LOCK LOCK GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LK0 Port Lock bit 0 0 1 LK1 Port Lock bit 1 1 1 LK10 Port Lock bit 10 10 1 LK11 Port Lock bit 11 11 1 LK12 Port Lock bit 12 12 1 LK13 Port Lock bit 13 13 1 LK14 Port Lock bit 14 14 1 LK15 Port Lock bit 15 15 1 LK2 Port Lock bit 2 2 1 LK3 Port Lock bit 3 3 1 LK4 Port Lock bit 4 4 1 LK5 Port Lock bit 5 5 1 LK6 Port Lock bit 6 6 1 LK7 Port Lock bit 7 7 1 LK8 Port Lock bit 8 8 1 LK9 Port Lock bit 9 9 1 LKK Lock sequence key 16 1 OCTL OCTL GPIO port output control register 0x14 32 read-write n 0x0 0x0 OCTL0 Port output control (y = 0) 0 1 OCTL1 Port output control (y = 1) 1 1 OCTL10 Port output control (y = 10) 10 1 OCTL11 Port output control (y = 11) 11 1 OCTL12 Port output control (y = 12) 12 1 OCTL13 Port output control (y = 13) 13 1 OCTL14 Port output control (y = 14) 14 1 OCTL15 Port output control (y = 15) 15 1 OCTL2 Port output control (y = 2) 2 1 OCTL3 Port output control (y = 3) 3 1 OCTL4 Port output control (y = 4) 4 1 OCTL5 Port output control (y = 5) 5 1 OCTL6 Port output control (y = 6) 6 1 OCTL7 Port output control (y = 7) 7 1 OCTL8 Port output control (y = 8) 8 1 OCTL9 Port output control (y = 9) 9 1 OMODE OMODE GPIO port output mode register 0x4 32 read-write n 0x0 0x0 OM0 Port 0 output mode bit 0 1 OM1 Port 1 output mode bit 1 1 OM10 Port 10 output mode bit 10 1 OM11 Port 11 output mode bit 11 1 OM12 Port 12 output mode bit 12 1 OM13 Port 13 output mode bit 13 1 OM14 Port 14 output mode bit 14 1 OM15 Port 15 output mode bit 15 1 OM2 Port 2 output mode bit 2 1 OM3 Port 3 output mode bit 3 1 OM4 Port 4 output mode bit 4 1 OM5 Port 5 output mode bit 5 1 OM6 Port 6 output mode bit 6 1 OM7 Port 7 output mode bit 7 1 OM8 Port 8 output mode bit 8 1 OM9 Port 9 output mode bit 9 1 OSPD OSPD GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPD0 Port 0 output max speed bits 0 2 OSPD1 Port 1 output max speed bits 2 2 OSPD10 Port 10 output max speed bits 20 2 OSPD11 Port 11 output max speed bits 22 2 OSPD12 Port 12 output max speed bits 24 2 OSPD13 Port 13 output max speed bits 26 2 OSPD14 Port 14 output max speed bits 28 2 OSPD15 Port 15 output max speed bits 30 2 OSPD2 Port 2 output max speed bits 4 2 OSPD3 Port 3 output max speed bits 6 2 OSPD4 Port 4 output max speed bits 8 2 OSPD5 Port 5 output max speed bits 10 2 OSPD6 Port 6 output max speed bits 12 2 OSPD7 Port 7 output max speed bits 14 2 OSPD8 Port 8 output max speed bits 16 2 OSPD9 Port 9 output max speed bits 18 2 PUD PUD GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUD0 Port 0 pull-up or pull-down bits 0 2 PUD1 Port 1 pull-up or pull-down bits 2 2 PUD10 Port 10 pull-up or pull-down bits 20 2 PUD11 Port 11 pull-up or pull-down bits 22 2 PUD12 Port 12 pull-up or pull-down bits 24 2 PUD13 Port 13 pull-up or pull-down bits 26 2 PUD14 Port 14 pull-up or pull-down bits 28 2 PUD15 Port 15 pull-up or pull-down bits 30 2 PUD2 Port 2 pull-up or pull-down bits 4 2 PUD3 Port 3 pull-up or pull-down bits 6 2 PUD4 Port 4 pull-up or pull-down bits 8 2 PUD5 Port 5 pull-up or pull-down bits 10 2 PUD6 Port 6 pull-up or pull-down bits 12 2 PUD7 Port 7 pull-up or pull-down bits 14 2 PUD8 Port 8 pull-up or pull-down bits 16 2 PUD9 Port 9 pull-up or pull-down bits 18 2 TG TG Port bit toggle register 0x2C 32 write-only n 0x0 0x0 TG0 Port toggle bit 0 1 TG1 Port toggle bit 1 1 TG10 Port toggle bit 10 1 TG11 Port toggle bit 11 1 TG12 Port toggle bit 12 1 TG13 Port toggle bit 13 1 TG14 Port toggle bit 14 1 TG15 Port toggle bit 15 1 TG2 Port toggle bit 2 1 TG3 Port toggle bit 3 1 TG4 Port toggle bit 4 1 TG5 Port toggle bit 5 1 TG6 Port toggle bit 6 1 TG7 Port toggle bit 7 1 TG8 Port toggle bit 8 1 TG9 Port toggle bit 9 1 GPIOG General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFSEL0 AFSEL0 GPIO alternate function selected register 0 0x20 32 read-write n 0x0 0x0 SEL0 Port 0 alternate function selected 0 4 SEL1 Port 1 alternate function selected 4 4 SEL2 Port 2 alternate function selected 8 4 SEL3 Port 3 alternate function selected 12 4 SEL4 Port 4 alternate function selected 16 4 SEL5 Port 5 alternate function selected 20 4 SEL6 Port 6 alternate function selected 24 4 SEL7 Port 7 alternate function selected 28 4 AFSEL1 AFSEL1 GPIO alternate function selected register 1 0x24 32 read-write n 0x0 0x0 SEL10 Port 10 alternate function selected 8 4 SEL11 Port 11 alternate function selected 12 4 SEL12 Port 12 alternate function selected 16 4 SEL13 Port 13 alternate function selected 20 4 SEL14 Port 14 alternate function selected 24 4 SEL15 Port 15 alternate function selected 28 4 SEL8 Port 8 alternate function selected 0 4 SEL9 Port 9 alternate function selected 4 4 BC BC Bit clear register 0x28 32 write-only n 0x0 0x0 CR0 Port cleat bit 0 1 CR1 Port cleat bit 1 1 CR10 Port cleat bit 10 1 CR11 Port cleat bit 11 1 CR12 Port cleat bit 12 1 CR13 Port cleat bit 13 1 CR14 Port cleat bit 14 1 CR15 Port cleat bit 15 1 CR2 Port cleat bit 2 1 CR3 Port cleat bit 3 1 CR4 Port cleat bit 4 1 CR5 Port cleat bit 5 1 CR6 Port cleat bit 6 1 CR7 Port cleat bit 7 1 CR8 Port cleat bit 8 1 CR9 Port cleat bit 9 1 BOP BOP GPIO port bit operate register 0x18 32 write-only n 0x0 0x0 BOP0 Port Set bit 0 0 1 BOP1 Port Set bit 1 1 1 BOP10 Port Set bit 10 10 1 BOP11 Port Set bit 11 11 1 BOP12 Port Set bit 12 12 1 BOP13 Port Set bit 13 13 1 BOP14 Port Set bit 14 14 1 BOP15 Port Set bit 15 15 1 BOP2 Port Set bit 2 2 1 BOP3 Port Set bit 3 3 1 BOP4 Port Set bit 4 4 1 BOP5 Port Set bit 5 5 1 BOP6 Port Set bit 6 6 1 BOP7 Port Set bit 7 7 1 BOP8 Port Set bit 8 8 1 BOP9 Port Set bit 9 9 1 CR0 Port Clear bit 0 16 1 CR1 Port Clear bit 1 17 1 CR10 Port Clear bit 10 26 1 CR11 Port Clear bit 11 27 1 CR12 Port Clear bit 12 28 1 CR13 Port Clear bit 13 29 1 CR14 Port Clear bit 14 30 1 CR15 Port Clear bit 15 31 1 CR2 Port Clear bit 2 18 1 CR3 Port Clear bit 3 19 1 CR4 Port Clear bit 4 20 1 CR5 Port Clear bit 5 21 1 CR6 Port Clear bit 6 22 1 CR7 Port Clear bit 7 23 1 CR8 Port Clear bit 8 24 1 CR9 Port Clear bit 9 25 1 CTL CTL GPIO port control register 0x0 32 read-write n 0x0 0x0 CTL0 Port x configuration bits (x = 0) 0 2 CTL1 Port x configuration bits (x = 1) 2 2 CTL10 Port x configuration bits (x = 10) 20 2 CTL11 Port x configuration bits (x = 11) 22 2 CTL12 Port x configuration bits (x = 12) 24 2 CTL13 Port x configuration bits (x = 13) 26 2 CTL14 Port x configuration bits (x = 14) 28 2 CTL15 Port x configuration bits (x = 15) 30 2 CTL2 Port x configuration bits (x = 2) 4 2 CTL3 Port x configuration bits (x = 3) 6 2 CTL4 Port x configuration bits (x = 4 ) 8 2 CTL5 Port x configuration bits (x = 5) 10 2 CTL6 Port x configuration bits (x = 6 ) 12 2 CTL7 Port x configuration bits (x = 7) 14 2 CTL8 Port x configuration bits (x = 8) 16 2 CTL9 Port x configuration bits (x = 9) 18 2 ISTAT ISTAT GPIO port input status register 0x10 32 read-only n 0x0 0x0 ISTAT0 Port input status (y = 0) 0 1 ISTAT1 Port input status (y = 1) 1 1 ISTAT10 Port input status (y = 10) 10 1 ISTAT11 Port input status (y = 11) 11 1 ISTAT12 Port input status (y = 12) 12 1 ISTAT13 Port input status (y = 13) 13 1 ISTAT14 Port input status (y = 14) 14 1 ISTAT15 Port input status (y = 15) 15 1 ISTAT2 Port input status (y = 2) 2 1 ISTAT3 Port input status (y = 3) 3 1 ISTAT4 Port input status (y = 4) 4 1 ISTAT5 Port input status (y = 5) 5 1 ISTAT6 Port input status (y = 6) 6 1 ISTAT7 Port input status (y = 7) 7 1 ISTAT8 Port input status (y = 8) 8 1 ISTAT9 Port input status (y = 9) 9 1 LOCK LOCK GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LK0 Port Lock bit 0 0 1 LK1 Port Lock bit 1 1 1 LK10 Port Lock bit 10 10 1 LK11 Port Lock bit 11 11 1 LK12 Port Lock bit 12 12 1 LK13 Port Lock bit 13 13 1 LK14 Port Lock bit 14 14 1 LK15 Port Lock bit 15 15 1 LK2 Port Lock bit 2 2 1 LK3 Port Lock bit 3 3 1 LK4 Port Lock bit 4 4 1 LK5 Port Lock bit 5 5 1 LK6 Port Lock bit 6 6 1 LK7 Port Lock bit 7 7 1 LK8 Port Lock bit 8 8 1 LK9 Port Lock bit 9 9 1 LKK Lock sequence key 16 1 OCTL OCTL GPIO port output control register 0x14 32 read-write n 0x0 0x0 OCTL0 Port output control (y = 0) 0 1 OCTL1 Port output control (y = 1) 1 1 OCTL10 Port output control (y = 10) 10 1 OCTL11 Port output control (y = 11) 11 1 OCTL12 Port output control (y = 12) 12 1 OCTL13 Port output control (y = 13) 13 1 OCTL14 Port output control (y = 14) 14 1 OCTL15 Port output control (y = 15) 15 1 OCTL2 Port output control (y = 2) 2 1 OCTL3 Port output control (y = 3) 3 1 OCTL4 Port output control (y = 4) 4 1 OCTL5 Port output control (y = 5) 5 1 OCTL6 Port output control (y = 6) 6 1 OCTL7 Port output control (y = 7) 7 1 OCTL8 Port output control (y = 8) 8 1 OCTL9 Port output control (y = 9) 9 1 OMODE OMODE GPIO port output mode register 0x4 32 read-write n 0x0 0x0 OM0 Port 0 output mode bit 0 1 OM1 Port 1 output mode bit 1 1 OM10 Port 10 output mode bit 10 1 OM11 Port 11 output mode bit 11 1 OM12 Port 12 output mode bit 12 1 OM13 Port 13 output mode bit 13 1 OM14 Port 14 output mode bit 14 1 OM15 Port 15 output mode bit 15 1 OM2 Port 2 output mode bit 2 1 OM3 Port 3 output mode bit 3 1 OM4 Port 4 output mode bit 4 1 OM5 Port 5 output mode bit 5 1 OM6 Port 6 output mode bit 6 1 OM7 Port 7 output mode bit 7 1 OM8 Port 8 output mode bit 8 1 OM9 Port 9 output mode bit 9 1 OSPD OSPD GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPD0 Port 0 output max speed bits 0 2 OSPD1 Port 1 output max speed bits 2 2 OSPD10 Port 10 output max speed bits 20 2 OSPD11 Port 11 output max speed bits 22 2 OSPD12 Port 12 output max speed bits 24 2 OSPD13 Port 13 output max speed bits 26 2 OSPD14 Port 14 output max speed bits 28 2 OSPD15 Port 15 output max speed bits 30 2 OSPD2 Port 2 output max speed bits 4 2 OSPD3 Port 3 output max speed bits 6 2 OSPD4 Port 4 output max speed bits 8 2 OSPD5 Port 5 output max speed bits 10 2 OSPD6 Port 6 output max speed bits 12 2 OSPD7 Port 7 output max speed bits 14 2 OSPD8 Port 8 output max speed bits 16 2 OSPD9 Port 9 output max speed bits 18 2 PUD PUD GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUD0 Port 0 pull-up or pull-down bits 0 2 PUD1 Port 1 pull-up or pull-down bits 2 2 PUD10 Port 10 pull-up or pull-down bits 20 2 PUD11 Port 11 pull-up or pull-down bits 22 2 PUD12 Port 12 pull-up or pull-down bits 24 2 PUD13 Port 13 pull-up or pull-down bits 26 2 PUD14 Port 14 pull-up or pull-down bits 28 2 PUD15 Port 15 pull-up or pull-down bits 30 2 PUD2 Port 2 pull-up or pull-down bits 4 2 PUD3 Port 3 pull-up or pull-down bits 6 2 PUD4 Port 4 pull-up or pull-down bits 8 2 PUD5 Port 5 pull-up or pull-down bits 10 2 PUD6 Port 6 pull-up or pull-down bits 12 2 PUD7 Port 7 pull-up or pull-down bits 14 2 PUD8 Port 8 pull-up or pull-down bits 16 2 PUD9 Port 9 pull-up or pull-down bits 18 2 TG TG Port bit toggle register 0x2C 32 write-only n 0x0 0x0 TG0 Port toggle bit 0 1 TG1 Port toggle bit 1 1 TG10 Port toggle bit 10 1 TG11 Port toggle bit 11 1 TG12 Port toggle bit 12 1 TG13 Port toggle bit 13 1 TG14 Port toggle bit 14 1 TG15 Port toggle bit 15 1 TG2 Port toggle bit 2 1 TG3 Port toggle bit 3 1 TG4 Port toggle bit 4 1 TG5 Port toggle bit 5 1 TG6 Port toggle bit 6 1 TG7 Port toggle bit 7 1 TG8 Port toggle bit 8 1 TG9 Port toggle bit 9 1 GPIOH General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFSEL0 AFSEL0 GPIO alternate function selected register 0 0x20 32 read-write n 0x0 0x0 SEL0 Port 0 alternate function selected 0 4 SEL1 Port 1 alternate function selected 4 4 SEL2 Port 2 alternate function selected 8 4 SEL3 Port 3 alternate function selected 12 4 SEL4 Port 4 alternate function selected 16 4 SEL5 Port 5 alternate function selected 20 4 SEL6 Port 6 alternate function selected 24 4 SEL7 Port 7 alternate function selected 28 4 AFSEL1 AFSEL1 GPIO alternate function selected register 1 0x24 32 read-write n 0x0 0x0 SEL10 Port 10 alternate function selected 8 4 SEL11 Port 11 alternate function selected 12 4 SEL12 Port 12 alternate function selected 16 4 SEL13 Port 13 alternate function selected 20 4 SEL14 Port 14 alternate function selected 24 4 SEL15 Port 15 alternate function selected 28 4 SEL8 Port 8 alternate function selected 0 4 SEL9 Port 9 alternate function selected 4 4 BC BC Bit clear register 0x28 32 write-only n 0x0 0x0 CR0 Port cleat bit 0 1 CR1 Port cleat bit 1 1 CR10 Port cleat bit 10 1 CR11 Port cleat bit 11 1 CR12 Port cleat bit 12 1 CR13 Port cleat bit 13 1 CR14 Port cleat bit 14 1 CR15 Port cleat bit 15 1 CR2 Port cleat bit 2 1 CR3 Port cleat bit 3 1 CR4 Port cleat bit 4 1 CR5 Port cleat bit 5 1 CR6 Port cleat bit 6 1 CR7 Port cleat bit 7 1 CR8 Port cleat bit 8 1 CR9 Port cleat bit 9 1 BOP BOP GPIO port bit operate register 0x18 32 write-only n 0x0 0x0 BOP0 Port Set bit 0 0 1 BOP1 Port Set bit 1 1 1 BOP10 Port Set bit 10 10 1 BOP11 Port Set bit 11 11 1 BOP12 Port Set bit 12 12 1 BOP13 Port Set bit 13 13 1 BOP14 Port Set bit 14 14 1 BOP15 Port Set bit 15 15 1 BOP2 Port Set bit 2 2 1 BOP3 Port Set bit 3 3 1 BOP4 Port Set bit 4 4 1 BOP5 Port Set bit 5 5 1 BOP6 Port Set bit 6 6 1 BOP7 Port Set bit 7 7 1 BOP8 Port Set bit 8 8 1 BOP9 Port Set bit 9 9 1 CR0 Port Clear bit 0 16 1 CR1 Port Clear bit 1 17 1 CR10 Port Clear bit 10 26 1 CR11 Port Clear bit 11 27 1 CR12 Port Clear bit 12 28 1 CR13 Port Clear bit 13 29 1 CR14 Port Clear bit 14 30 1 CR15 Port Clear bit 15 31 1 CR2 Port Clear bit 2 18 1 CR3 Port Clear bit 3 19 1 CR4 Port Clear bit 4 20 1 CR5 Port Clear bit 5 21 1 CR6 Port Clear bit 6 22 1 CR7 Port Clear bit 7 23 1 CR8 Port Clear bit 8 24 1 CR9 Port Clear bit 9 25 1 CTL CTL GPIO port control register 0x0 32 read-write n 0x0 0x0 CTL0 Port x configuration bits (x = 0) 0 2 CTL1 Port x configuration bits (x = 1) 2 2 CTL10 Port x configuration bits (x = 10) 20 2 CTL11 Port x configuration bits (x = 11) 22 2 CTL12 Port x configuration bits (x = 12) 24 2 CTL13 Port x configuration bits (x = 13) 26 2 CTL14 Port x configuration bits (x = 14) 28 2 CTL15 Port x configuration bits (x = 15) 30 2 CTL2 Port x configuration bits (x = 2) 4 2 CTL3 Port x configuration bits (x = 3) 6 2 CTL4 Port x configuration bits (x = 4 ) 8 2 CTL5 Port x configuration bits (x = 5) 10 2 CTL6 Port x configuration bits (x = 6 ) 12 2 CTL7 Port x configuration bits (x = 7) 14 2 CTL8 Port x configuration bits (x = 8) 16 2 CTL9 Port x configuration bits (x = 9) 18 2 ISTAT ISTAT GPIO port input status register 0x10 32 read-only n 0x0 0x0 ISTAT0 Port input status (y = 0) 0 1 ISTAT1 Port input status (y = 1) 1 1 ISTAT10 Port input status (y = 10) 10 1 ISTAT11 Port input status (y = 11) 11 1 ISTAT12 Port input status (y = 12) 12 1 ISTAT13 Port input status (y = 13) 13 1 ISTAT14 Port input status (y = 14) 14 1 ISTAT15 Port input status (y = 15) 15 1 ISTAT2 Port input status (y = 2) 2 1 ISTAT3 Port input status (y = 3) 3 1 ISTAT4 Port input status (y = 4) 4 1 ISTAT5 Port input status (y = 5) 5 1 ISTAT6 Port input status (y = 6) 6 1 ISTAT7 Port input status (y = 7) 7 1 ISTAT8 Port input status (y = 8) 8 1 ISTAT9 Port input status (y = 9) 9 1 LOCK LOCK GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LK0 Port Lock bit 0 0 1 LK1 Port Lock bit 1 1 1 LK10 Port Lock bit 10 10 1 LK11 Port Lock bit 11 11 1 LK12 Port Lock bit 12 12 1 LK13 Port Lock bit 13 13 1 LK14 Port Lock bit 14 14 1 LK15 Port Lock bit 15 15 1 LK2 Port Lock bit 2 2 1 LK3 Port Lock bit 3 3 1 LK4 Port Lock bit 4 4 1 LK5 Port Lock bit 5 5 1 LK6 Port Lock bit 6 6 1 LK7 Port Lock bit 7 7 1 LK8 Port Lock bit 8 8 1 LK9 Port Lock bit 9 9 1 LKK Lock sequence key 16 1 OCTL OCTL GPIO port output control register 0x14 32 read-write n 0x0 0x0 OCTL0 Port output control (y = 0) 0 1 OCTL1 Port output control (y = 1) 1 1 OCTL10 Port output control (y = 10) 10 1 OCTL11 Port output control (y = 11) 11 1 OCTL12 Port output control (y = 12) 12 1 OCTL13 Port output control (y = 13) 13 1 OCTL14 Port output control (y = 14) 14 1 OCTL15 Port output control (y = 15) 15 1 OCTL2 Port output control (y = 2) 2 1 OCTL3 Port output control (y = 3) 3 1 OCTL4 Port output control (y = 4) 4 1 OCTL5 Port output control (y = 5) 5 1 OCTL6 Port output control (y = 6) 6 1 OCTL7 Port output control (y = 7) 7 1 OCTL8 Port output control (y = 8) 8 1 OCTL9 Port output control (y = 9) 9 1 OMODE OMODE GPIO port output mode register 0x4 32 read-write n 0x0 0x0 OM0 Port 0 output mode bit 0 1 OM1 Port 1 output mode bit 1 1 OM10 Port 10 output mode bit 10 1 OM11 Port 11 output mode bit 11 1 OM12 Port 12 output mode bit 12 1 OM13 Port 13 output mode bit 13 1 OM14 Port 14 output mode bit 14 1 OM15 Port 15 output mode bit 15 1 OM2 Port 2 output mode bit 2 1 OM3 Port 3 output mode bit 3 1 OM4 Port 4 output mode bit 4 1 OM5 Port 5 output mode bit 5 1 OM6 Port 6 output mode bit 6 1 OM7 Port 7 output mode bit 7 1 OM8 Port 8 output mode bit 8 1 OM9 Port 9 output mode bit 9 1 OSPD OSPD GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPD0 Port 0 output max speed bits 0 2 OSPD1 Port 1 output max speed bits 2 2 OSPD10 Port 10 output max speed bits 20 2 OSPD11 Port 11 output max speed bits 22 2 OSPD12 Port 12 output max speed bits 24 2 OSPD13 Port 13 output max speed bits 26 2 OSPD14 Port 14 output max speed bits 28 2 OSPD15 Port 15 output max speed bits 30 2 OSPD2 Port 2 output max speed bits 4 2 OSPD3 Port 3 output max speed bits 6 2 OSPD4 Port 4 output max speed bits 8 2 OSPD5 Port 5 output max speed bits 10 2 OSPD6 Port 6 output max speed bits 12 2 OSPD7 Port 7 output max speed bits 14 2 OSPD8 Port 8 output max speed bits 16 2 OSPD9 Port 9 output max speed bits 18 2 PUD PUD GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUD0 Port 0 pull-up or pull-down bits 0 2 PUD1 Port 1 pull-up or pull-down bits 2 2 PUD10 Port 10 pull-up or pull-down bits 20 2 PUD11 Port 11 pull-up or pull-down bits 22 2 PUD12 Port 12 pull-up or pull-down bits 24 2 PUD13 Port 13 pull-up or pull-down bits 26 2 PUD14 Port 14 pull-up or pull-down bits 28 2 PUD15 Port 15 pull-up or pull-down bits 30 2 PUD2 Port 2 pull-up or pull-down bits 4 2 PUD3 Port 3 pull-up or pull-down bits 6 2 PUD4 Port 4 pull-up or pull-down bits 8 2 PUD5 Port 5 pull-up or pull-down bits 10 2 PUD6 Port 6 pull-up or pull-down bits 12 2 PUD7 Port 7 pull-up or pull-down bits 14 2 PUD8 Port 8 pull-up or pull-down bits 16 2 PUD9 Port 9 pull-up or pull-down bits 18 2 TG TG Port bit toggle register 0x2C 32 write-only n 0x0 0x0 TG0 Port toggle bit 0 1 TG1 Port toggle bit 1 1 TG10 Port toggle bit 10 1 TG11 Port toggle bit 11 1 TG12 Port toggle bit 12 1 TG13 Port toggle bit 13 1 TG14 Port toggle bit 14 1 TG15 Port toggle bit 15 1 TG2 Port toggle bit 2 1 TG3 Port toggle bit 3 1 TG4 Port toggle bit 4 1 TG5 Port toggle bit 5 1 TG6 Port toggle bit 6 1 TG7 Port toggle bit 7 1 TG8 Port toggle bit 8 1 TG9 Port toggle bit 9 1 GPIOI General-purpose I/Os GPIO 0x0 0x0 0x400 registers n AFSEL0 AFSEL0 GPIO alternate function selected register 0 0x20 32 read-write n 0x0 0x0 SEL0 Port 0 alternate function selected 0 4 SEL1 Port 1 alternate function selected 4 4 SEL2 Port 2 alternate function selected 8 4 SEL3 Port 3 alternate function selected 12 4 SEL4 Port 4 alternate function selected 16 4 SEL5 Port 5 alternate function selected 20 4 SEL6 Port 6 alternate function selected 24 4 SEL7 Port 7 alternate function selected 28 4 AFSEL1 AFSEL1 GPIO alternate function selected register 1 0x24 32 read-write n 0x0 0x0 SEL10 Port 10 alternate function selected 8 4 SEL11 Port 11 alternate function selected 12 4 SEL12 Port 12 alternate function selected 16 4 SEL13 Port 13 alternate function selected 20 4 SEL14 Port 14 alternate function selected 24 4 SEL15 Port 15 alternate function selected 28 4 SEL8 Port 8 alternate function selected 0 4 SEL9 Port 9 alternate function selected 4 4 BC BC Bit clear register 0x28 32 write-only n 0x0 0x0 CR0 Port cleat bit 0 1 CR1 Port cleat bit 1 1 CR10 Port cleat bit 10 1 CR11 Port cleat bit 11 1 CR12 Port cleat bit 12 1 CR13 Port cleat bit 13 1 CR14 Port cleat bit 14 1 CR15 Port cleat bit 15 1 CR2 Port cleat bit 2 1 CR3 Port cleat bit 3 1 CR4 Port cleat bit 4 1 CR5 Port cleat bit 5 1 CR6 Port cleat bit 6 1 CR7 Port cleat bit 7 1 CR8 Port cleat bit 8 1 CR9 Port cleat bit 9 1 BOP BOP GPIO port bit operate register 0x18 32 write-only n 0x0 0x0 BOP0 Port Set bit 0 0 1 BOP1 Port Set bit 1 1 1 BOP10 Port Set bit 10 10 1 BOP11 Port Set bit 11 11 1 BOP12 Port Set bit 12 12 1 BOP13 Port Set bit 13 13 1 BOP14 Port Set bit 14 14 1 BOP15 Port Set bit 15 15 1 BOP2 Port Set bit 2 2 1 BOP3 Port Set bit 3 3 1 BOP4 Port Set bit 4 4 1 BOP5 Port Set bit 5 5 1 BOP6 Port Set bit 6 6 1 BOP7 Port Set bit 7 7 1 BOP8 Port Set bit 8 8 1 BOP9 Port Set bit 9 9 1 CR0 Port Clear bit 0 16 1 CR1 Port Clear bit 1 17 1 CR10 Port Clear bit 10 26 1 CR11 Port Clear bit 11 27 1 CR12 Port Clear bit 12 28 1 CR13 Port Clear bit 13 29 1 CR14 Port Clear bit 14 30 1 CR15 Port Clear bit 15 31 1 CR2 Port Clear bit 2 18 1 CR3 Port Clear bit 3 19 1 CR4 Port Clear bit 4 20 1 CR5 Port Clear bit 5 21 1 CR6 Port Clear bit 6 22 1 CR7 Port Clear bit 7 23 1 CR8 Port Clear bit 8 24 1 CR9 Port Clear bit 9 25 1 CTL CTL GPIO port control register 0x0 32 read-write n 0x0 0x0 CTL0 Port x configuration bits (x = 0) 0 2 CTL1 Port x configuration bits (x = 1) 2 2 CTL10 Port x configuration bits (x = 10) 20 2 CTL11 Port x configuration bits (x = 11) 22 2 CTL12 Port x configuration bits (x = 12) 24 2 CTL13 Port x configuration bits (x = 13) 26 2 CTL14 Port x configuration bits (x = 14) 28 2 CTL15 Port x configuration bits (x = 15) 30 2 CTL2 Port x configuration bits (x = 2) 4 2 CTL3 Port x configuration bits (x = 3) 6 2 CTL4 Port x configuration bits (x = 4 ) 8 2 CTL5 Port x configuration bits (x = 5) 10 2 CTL6 Port x configuration bits (x = 6 ) 12 2 CTL7 Port x configuration bits (x = 7) 14 2 CTL8 Port x configuration bits (x = 8) 16 2 CTL9 Port x configuration bits (x = 9) 18 2 ISTAT ISTAT GPIO port input status register 0x10 32 read-only n 0x0 0x0 ISTAT0 Port input status (y = 0) 0 1 ISTAT1 Port input status (y = 1) 1 1 ISTAT10 Port input status (y = 10) 10 1 ISTAT11 Port input status (y = 11) 11 1 ISTAT12 Port input status (y = 12) 12 1 ISTAT13 Port input status (y = 13) 13 1 ISTAT14 Port input status (y = 14) 14 1 ISTAT15 Port input status (y = 15) 15 1 ISTAT2 Port input status (y = 2) 2 1 ISTAT3 Port input status (y = 3) 3 1 ISTAT4 Port input status (y = 4) 4 1 ISTAT5 Port input status (y = 5) 5 1 ISTAT6 Port input status (y = 6) 6 1 ISTAT7 Port input status (y = 7) 7 1 ISTAT8 Port input status (y = 8) 8 1 ISTAT9 Port input status (y = 9) 9 1 LOCK LOCK GPIO port configuration lock register 0x1C 32 read-write n 0x0 0x0 LK0 Port Lock bit 0 0 1 LK1 Port Lock bit 1 1 1 LK10 Port Lock bit 10 10 1 LK11 Port Lock bit 11 11 1 LK12 Port Lock bit 12 12 1 LK13 Port Lock bit 13 13 1 LK14 Port Lock bit 14 14 1 LK15 Port Lock bit 15 15 1 LK2 Port Lock bit 2 2 1 LK3 Port Lock bit 3 3 1 LK4 Port Lock bit 4 4 1 LK5 Port Lock bit 5 5 1 LK6 Port Lock bit 6 6 1 LK7 Port Lock bit 7 7 1 LK8 Port Lock bit 8 8 1 LK9 Port Lock bit 9 9 1 LKK Lock sequence key 16 1 OCTL OCTL GPIO port output control register 0x14 32 read-write n 0x0 0x0 OCTL0 Port output control (y = 0) 0 1 OCTL1 Port output control (y = 1) 1 1 OCTL10 Port output control (y = 10) 10 1 OCTL11 Port output control (y = 11) 11 1 OCTL12 Port output control (y = 12) 12 1 OCTL13 Port output control (y = 13) 13 1 OCTL14 Port output control (y = 14) 14 1 OCTL15 Port output control (y = 15) 15 1 OCTL2 Port output control (y = 2) 2 1 OCTL3 Port output control (y = 3) 3 1 OCTL4 Port output control (y = 4) 4 1 OCTL5 Port output control (y = 5) 5 1 OCTL6 Port output control (y = 6) 6 1 OCTL7 Port output control (y = 7) 7 1 OCTL8 Port output control (y = 8) 8 1 OCTL9 Port output control (y = 9) 9 1 OMODE OMODE GPIO port output mode register 0x4 32 read-write n 0x0 0x0 OM0 Port 0 output mode bit 0 1 OM1 Port 1 output mode bit 1 1 OM10 Port 10 output mode bit 10 1 OM11 Port 11 output mode bit 11 1 OM12 Port 12 output mode bit 12 1 OM13 Port 13 output mode bit 13 1 OM14 Port 14 output mode bit 14 1 OM15 Port 15 output mode bit 15 1 OM2 Port 2 output mode bit 2 1 OM3 Port 3 output mode bit 3 1 OM4 Port 4 output mode bit 4 1 OM5 Port 5 output mode bit 5 1 OM6 Port 6 output mode bit 6 1 OM7 Port 7 output mode bit 7 1 OM8 Port 8 output mode bit 8 1 OM9 Port 9 output mode bit 9 1 OSPD OSPD GPIO port output speed register 0x8 32 read-write n 0x0 0x0 OSPD0 Port 0 output max speed bits 0 2 OSPD1 Port 1 output max speed bits 2 2 OSPD10 Port 10 output max speed bits 20 2 OSPD11 Port 11 output max speed bits 22 2 OSPD12 Port 12 output max speed bits 24 2 OSPD13 Port 13 output max speed bits 26 2 OSPD14 Port 14 output max speed bits 28 2 OSPD15 Port 15 output max speed bits 30 2 OSPD2 Port 2 output max speed bits 4 2 OSPD3 Port 3 output max speed bits 6 2 OSPD4 Port 4 output max speed bits 8 2 OSPD5 Port 5 output max speed bits 10 2 OSPD6 Port 6 output max speed bits 12 2 OSPD7 Port 7 output max speed bits 14 2 OSPD8 Port 8 output max speed bits 16 2 OSPD9 Port 9 output max speed bits 18 2 PUD PUD GPIO port pull-up/pull-down register 0xC 32 read-write n 0x0 0x0 PUD0 Port 0 pull-up or pull-down bits 0 2 PUD1 Port 1 pull-up or pull-down bits 2 2 PUD10 Port 10 pull-up or pull-down bits 20 2 PUD11 Port 11 pull-up or pull-down bits 22 2 PUD12 Port 12 pull-up or pull-down bits 24 2 PUD13 Port 13 pull-up or pull-down bits 26 2 PUD14 Port 14 pull-up or pull-down bits 28 2 PUD15 Port 15 pull-up or pull-down bits 30 2 PUD2 Port 2 pull-up or pull-down bits 4 2 PUD3 Port 3 pull-up or pull-down bits 6 2 PUD4 Port 4 pull-up or pull-down bits 8 2 PUD5 Port 5 pull-up or pull-down bits 10 2 PUD6 Port 6 pull-up or pull-down bits 12 2 PUD7 Port 7 pull-up or pull-down bits 14 2 PUD8 Port 8 pull-up or pull-down bits 16 2 PUD9 Port 9 pull-up or pull-down bits 18 2 TG TG Port bit toggle register 0x2C 32 write-only n 0x0 0x0 TG0 Port toggle bit 0 1 TG1 Port toggle bit 1 1 TG10 Port toggle bit 10 1 TG11 Port toggle bit 11 1 TG12 Port toggle bit 12 1 TG13 Port toggle bit 13 1 TG14 Port toggle bit 14 1 TG15 Port toggle bit 15 1 TG2 Port toggle bit 2 1 TG3 Port toggle bit 3 1 TG4 Port toggle bit 4 1 TG5 Port toggle bit 5 1 TG6 Port toggle bit 6 1 TG7 Port toggle bit 7 1 TG8 Port toggle bit 8 1 TG9 Port toggle bit 9 1 HS_DEVICE USB on the go high speed device USB_HS 0x0 0x0 0x400 registers n DAEPINT DAEPINT device all endpoints interrupt register (DAEPINT) 0x18 32 read-only n 0x0 0x0 IEPITB Device all IN endpoint interrupt bits 0 6 OEPITB Device all OUT endpoint interrupt bits 16 6 DAEPINTEN DAEPINTEN Device all endpoints interrupt enable register (DAEPINTEN) 0x1C 32 read-write n 0x0 0x0 IEPIE IN endpoint interrupt enable bits 0 6 OEPIE OUT endpoint interrupt enable bits 16 6 DCFG DCFG device configuration register (DCFG) 0x0 32 read-write n 0x0 0x0 DAR Device address 4 7 DS Device speed 0 2 EOPFT end of periodic frame time 11 2 NZLSOH Non-zero-length status OUT handshake 2 1 DCTL DCTL device control register (DCTL) 0x4 32 read-write n 0x0 0x0 CGINAK Clear global IN NAK 8 1 read-write CGONAK Clear global OUT NAK 10 1 read-write GINS Global IN NAK status 2 1 read-only GONS Global OUT NAK status 3 1 read-only POIF Power-on initialization finished 11 1 read-write RWKUP Remote wakeup signaling 0 1 read-write SD Soft disconnect 1 1 read-write SGINAK Set global IN NAK 7 1 read-write SGONAK Set global OUT NAK 9 1 read-write DEP1INT DEP1INT device endpoint 1 interrupt register 0x38 32 read-write n 0x0 0x0 IEP1INT IN endpoint 1 interrupt bits 1 1 OEP1INT OUT endpoint 1 interrupt bits 17 1 DEP1INTEN DEP1INTEN device endpoint 1 interrupt enable register 0x3C 32 read-write n 0x0 0x0 IEP1INTEN IN endpoint 1 interrupt enable bits 1 1 OEP1INTEN OUT endpoint 1 interrupt enable bits 17 1 DIEP0CTL DIEP0CTL Device IN endpoint 0 control register (USBHS_DIEP0CTL) 0x100 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EPACT endpoint active 15 1 read-only EPD Endpoint disable 30 1 read-only EPEN Endpoint enable 31 1 read-only EPTYPE Endpoint type 18 2 read-only MPL Maximum packet length 0 2 read-write NAKS NAK status 17 1 read-only SNAK Set NAK 27 1 write-only STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write DIEP0DMAADDR DIEP0DMAADDR device IN endpoint 0 DMA address register 0x114 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 DIEP0INTF DIEP0INTF Device IN endpoint-0 interrupt register 0x108 32 read-write n 0x0 0x0 CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write IEPNE IN endpoint NAK effective 6 1 read-write NAK NAK handshake sent by USBHS 13 1 read-write TF Transfer finished 0 1 read-write TXFE Transmit FIFO empty 7 1 read-only DIEP0LEN DIEP0LEN device IN endpoint-0 transfer length register 0x110 32 read-write n 0x0 0x0 PCNT Packet count 19 2 TLEN Transfer length 0 7 DIEP0TFSTAT DIEP0TFSTAT device IN endpoint 0 transmit FIFO status register 0x118 32 read-only n 0x0 0x0 IEPTFS IN endpoint TxFIFO space available 0 16 DIEP1CTL DIEP1CTL Device IN endpoint-x control register 0x120 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write EPTYPE Endpoint type 18 2 read-write MPL maximum packet length 0 11 read-write NAKS NAK status 17 1 read-only SD0PID_SEVENFRM SD0PID/SEVNFRM 28 1 write-only SD1PID_SODDFRM Set DATA1 PID/Set odd frame 29 1 write-only SNAK Set NAK 27 1 write-only STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write DIEP1DMAADDR DIEP1DMAADDR device IN endpoint 1 DMA address register 0x134 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 DIEP1INTEN DIEP1INTEN device IN endpoint 1 interrupt mask register (DIEP1INTEN) 0x44 32 read-write n 0x0 0x0 CITOEN Control IN timeout condition interrupt enable (Non-isochronous endpoints) 3 1 EPDISEN Endpoint disabled interrupt enable 1 1 EPTXFUDEN Endpoint Tx FIFO underrun interrupt enable bit 4 1 IEPNEEN IN endpoint NAK effective interrupt enable 6 1 NAKEN NAK handshake sent by USBHS interrupt enable bit 13 1 TFEN Transfer finished interrupt enable 0 1 DIEP1INTF DIEP1INTF Device IN endpoint-1 interrupt register 0x128 32 read-write n 0x0 0x0 CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write IEPNE IN endpoint NAK effective 6 1 read-write NAK NAK handshake sent by USBHS 13 1 read-write TF Transfer finished 0 1 read-write TXFE Transmit FIFO empty 7 1 read-only DIEP1LEN DIEP1LEN device IN endpoint-1 transfer length register 0x130 32 read-write n 0x0 0x0 MCNT Multi count 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DIEP1TFSTAT DIEP1TFSTAT device IN endpoint 1 transmit FIFO status register 0x138 32 read-only n 0x0 0x0 IEPTFS IN endpoint TxFIFO space available 0 16 DIEP2CTL DIEP2CTL device endpoint-2 control register 0x140 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write EPTYPE Endpoint type 18 2 read-write MPL maximum packet length 0 11 read-write NAKS NAK status 17 1 read-only SD0PID_SEVENFRM SD0PID/SEVNFRM 28 1 write-only SD1PID_SODDFRM Set DATA1 PID/Set odd frame 29 1 write-only SNAK Set NAK 27 1 write-only STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write DIEP2DMAADDR DIEP2DMAADDR device IN endpoint 2 DMA address register 0x154 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 DIEP2INTF DIEP2INTF Device IN endpoint-2 interrupt register 0x148 32 read-write n 0x0 0x0 CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write IEPNE IN endpoint NAK effective 6 1 read-write NAK NAK handshake sent by USBHS 13 1 read-write TF Transfer finished 0 1 read-write TXFE Transmit FIFO empty 7 1 read-only DIEP2LEN DIEP2LEN device IN endpoint-2 transfer length register 0x150 32 read-write n 0x0 0x0 MCNT Multi count 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DIEP2TFSTAT DIEP2TFSTAT device IN endpoint 2 transmit FIFO status register 0x158 32 read-only n 0x0 0x0 IEPTFS IN endpoint TxFIFO space available 0 16 DIEP3CTL DIEP3CTL device endpoint-3 control register 0x160 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write EPTYPE Endpoint type 18 2 read-write MPL maximum packet length 0 11 read-write NAKS NAK status 17 1 read-only SD0PID_SEVENFRM SD0PID/SEVNFRM 28 1 write-only SD1PID_SODDFRM Set DATA1 PID/Set odd frame 29 1 write-only SNAK Set NAK 27 1 write-only STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write DIEP3DMAADDR DIEP3DMAADDR device IN endpoint 3 DMA address register 0x174 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 DIEP3INTF DIEP3INTF Device IN endpoint-3 interrupt register 0x168 32 read-write n 0x0 0x0 CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write IEPNE IN endpoint NAK effective 6 1 read-write NAK NAK handshake sent by USBHS 13 1 read-write TF Transfer finished 0 1 read-write TXFE Transmit FIFO empty 7 1 read-only DIEP3LEN DIEP3LEN device IN endpoint-3 transfer length register 0x170 32 read-write n 0x0 0x0 MCNT Multi count 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DIEP3TFSTAT DIEP3TFSTAT device IN endpoint 3 transmit FIFO status register 0x178 32 read-only n 0x0 0x0 IEPTFS IN endpoint TxFIFO space available 0 16 DIEP4CTL DIEP4CTL device endpoint-4 control register 0x180 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write EPTYPE Endpoint type 18 2 read-write MPL maximum packet length 0 11 read-write NAKS NAK status 17 1 read-only SD0PID_SEVENFRM SD0PID/SEVNFRM 28 1 write-only SD1PID_SODDFRM Set DATA1 PID/Set odd frame 29 1 write-only SNAK Set NAK 27 1 write-only STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write DIEP4DMAADDR DIEP4DMAADDR device IN endpoint 4 DMA address register 0x194 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 DIEP4INTF DIEP4INTF Device IN endpoint-4 interrupt register 0x188 32 read-write n 0x0 0x0 CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write IEPNE IN endpoint NAK effective 6 1 read-write NAK NAK handshake sent by USBHS 13 1 read-write TF Transfer finished 0 1 read-write TXFE Transmit FIFO empty 7 1 read-only DIEP4LEN DIEP4LEN device IN endpoint-4 transfer length register 0x190 32 read-write n 0x0 0x0 MCNT Multi count 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DIEP4TFSTAT DIEP4TFSTAT device IN endpoint 4 transmit FIFO status register 0x198 32 read-only n 0x0 0x0 IEPTFS IN endpoint TxFIFO space available 0 16 DIEP5CTL DIEP5CTL device endpoint-5 control register 0x1A0 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write EPTYPE Endpoint type 18 2 read-write MPL maximum packet length 0 11 read-write NAKS NAK status 17 1 read-only SD0PID_SEVENFRM SD0PID/SEVNFRM 28 1 write-only SD1PID_SODDFRM Set DATA1 PID/Set odd frame 29 1 write-only SNAK Set NAK 27 1 write-only STALL STALL handshake 21 1 read-write TXFNUM Tx FIFO number 22 4 read-write DIEP5DMAADDR DIEP5DMAADDR device IN endpoint 5 DMA address register 0x1B4 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 DIEP5INTF DIEP5INTF Device IN endpoint-5 interrupt register 0x1A8 32 read-write n 0x0 0x0 CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write IEPNE IN endpoint NAK effective 6 1 read-write NAK NAK handshake sent by USBHS 13 1 read-write TF Transfer finished 0 1 read-write TXFE Transmit FIFO empty 7 1 read-only DIEP5LEN DIEP5LEN device IN endpoint-5 transfer length register 0x1B0 32 read-write n 0x0 0x0 MCNT Multi count 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DIEP5TFSTAT DIEP5TFSTAT device IN endpoint 5 transmit FIFO status register 0x1B8 32 read-only n 0x0 0x0 IEPTFS IN endpoint TxFIFO space available 0 16 DIEPFEINTEN DIEPFEINTEN device IN endpoint FIFO empty interrupt enable register 0x34 32 read-write n 0x0 0x0 IEPTXFEIE IN EP Tx FIFO empty interrupt enable bits 0 6 DIEPINTEN DIEPINTEN device IN endpoint common interrupt mask register (DIEPINTEN) 0x10 32 read-write n 0x0 0x0 CITOEN Control IN timeout condition interrupt enable (Non-isochronous endpoints) 3 1 EPDISEN Endpoint disabled interrupt enable 1 1 EPTXFUDEN Endpoint Tx FIFO underrun interrupt enable bit 4 1 IEPNEEN IN endpoint NAK effective interrupt enable 6 1 NAKEN NAK handshake sent by USBHS interrupt enable bit 13 1 TFEN Transfer completed interrupt enable 0 1 TXFEEN Trabsmit FIFO empty interrupt enable 7 1 DOEP0CTL DOEP0CTL Device OUT endpoint-0 control register 0x300 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EPACT Endpoint active 15 1 read-only EPD Endpoint disable 30 1 read-only EPEN Endpoint enable 31 1 write-only EPTYPE Endpoint type 18 2 read-only MPL Maximum packet length 0 2 read-only NAKS NAK status 17 1 read-only SNAK Set NAK 27 1 write-only SNOOP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write DOEP0DMAADDR DOEP0DMAADDR device OUT endpoint 0 DMA address register 0x314 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 DOEP0INTF DOEP0INTF device out endpoint-0 interrupt register 0x308 32 read-write n 0x0 0x0 BTBSTP Back-to-back SETUP packets 6 1 EPDIS Endpoint disabled 1 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 NYET NYET handshake is sent 14 1 STPF Setup phase finished 3 1 TF Transfer finished 0 1 DOEP0LEN DOEP0LEN device OUT endpoint-0 transfer length register 0x310 32 read-write n 0x0 0x0 PCNT Packet count 19 1 STPCNT SETUP packet count 29 2 TLEN Transfer length 0 7 DOEP1CTL DOEP1CTL Device OUT endpoint-1 control register 0x320 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write EPTYPE Endpoint type 18 2 read-write MPL maximum packet length 0 11 read-write NAKS NAK status 17 1 read-only SD0PID_SEVENFRM SD0PID/SEVENFRM 28 1 write-only SD1PID_SODDFRM SD1PID/SODDFRM 29 1 write-only SNAK Set NAK 27 1 write-only SNOOP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write DOEP1DMAADDR DOEP1DMAADDR device OUT endpoint 1 DMA address register 0x334 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 DOEP1INTEN DOEP1INTEN device OUT endpoint common interrupt enable register (DOEP1INTEN) 0x84 32 read-write n 0x0 0x0 BTBSTPEN Back-to-back SETUP packets ( Only for control OUT endpoint) interrupt enable bit 6 1 EPDISEN Endpoint disabled interrupt enable 1 1 EPRXFOVREN Endpoint Rx FIFO overrun interrupt enable 4 1 NYETEN NYET handshake is sent interrupt enable bit 14 1 STPFEN SETUP phase done interrupt enable 3 1 TFEN Transfer completed interrupt enable 0 1 DOEP1INTF DOEP1INTF device out endpoint-1 interrupt register 0x328 32 read-write n 0x0 0x0 BTBSTP Back-to-back SETUP packets 6 1 EPDIS Endpoint disabled 1 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 NYET NYET handshake is sent 14 1 STPF Setup phase finished 3 1 TF Transfer finished 0 1 DOEP1LEN DOEP1LEN device OUT endpoint-1 transfer length register 0x330 32 read-write n 0x0 0x0 PCNT Packet count 19 10 STPCNT_RXDPID SETUP packet count/Received data PID 29 2 TLEN Transfer length 0 19 DOEP2CTL DOEP2CTL Device OUT endpoint-2 control register 0x340 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write EPTYPE Endpoint type 18 2 read-write MPL maximum packet length 0 11 read-write NAKS NAK status 17 1 read-only SD0PID_SEVENFRM SD0PID/SEVENFRM 28 1 write-only SD1PID_SODDFRM SD1PID/SODDFRM 29 1 write-only SNAK Set NAK 27 1 write-only SNOOP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write DOEP2DMAADDR DOEP2DMAADDR device OUT endpoint 2 DMA address register 0x354 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 DOEP2INTF DOEP2INTF device out endpoint-2 interrupt register 0x348 32 read-write n 0x0 0x0 BTBSTP Back-to-back SETUP packets 6 1 EPDIS Endpoint disabled 1 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 NYET NYET handshake is sent 14 1 STPF Setup phase finished 3 1 TF Transfer finished 0 1 DOEP2LEN DOEP2LEN device OUT endpoint-2 transfer length register 0x350 32 read-write n 0x0 0x0 PCNT Packet count 19 10 STPCNT_RXDPID SETUP packet count/Received data PID 29 2 TLEN Transfer length 0 19 DOEP3CTL DOEP3CTL Device OUT endpoint-3 control register 0x360 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write EPTYPE Endpoint type 18 2 read-write MPL maximum packet length 0 11 read-write NAKS NAK status 17 1 read-only SD0PID_SEVENFRM SD0PID/SEVENFRM 28 1 write-only SD1PID_SODDFRM SD1PID/SODDFRM 29 1 write-only SNAK Set NAK 27 1 write-only SNOOP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write DOEP3DMAADDR DOEP3DMAADDR device OUT endpoint 3 DMA address register 0x374 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 DOEP3INTF DOEP3INTF device out endpoint-3 interrupt register 0x368 32 read-write n 0x0 0x0 BTBSTP Back-to-back SETUP packets 6 1 EPDIS Endpoint disabled 1 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 NYET NYET handshake is sent 14 1 STPF Setup phase finished 3 1 TF Transfer finished 0 1 DOEP3LEN DOEP3LEN device OUT endpoint-3 transfer length register 0x370 32 read-write n 0x0 0x0 PCNT Packet count 19 10 STPCNT_RXDPID SETUP packet count/Received data PID 29 2 TLEN Transfer length 0 19 DOEP4CTL DOEP4CTL Device OUT endpoint-4 control register 0x380 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write EPTYPE Endpoint type 18 2 read-write MPL maximum packet length 0 11 read-write NAKS NAK status 17 1 read-only SD0PID_SEVENFRM SD0PID/SEVENFRM 28 1 write-only SD1PID_SODDFRM SD1PID/SODDFRM 29 1 write-only SNAK Set NAK 27 1 write-only SNOOP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write DOEP4DMAADDR DOEP4DMAADDR device OUT endpoint 4 DMA address register 0x394 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 DOEP4INTF DOEP4INTF device out endpoint-4 interrupt register 0x388 32 read-write n 0x0 0x0 BTBSTP Back-to-back SETUP packets 6 1 EPDIS Endpoint disabled 1 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 NYET NYET handshake is sent 14 1 STPF Setup phase finished 3 1 TF Transfer finished 0 1 DOEP4LEN DOEP4LEN device OUT endpoint-4 transfer length register 0x390 32 read-write n 0x0 0x0 PCNT Packet count 19 10 STPCNT_RXDPID SETUP packet count/Received data PID 29 2 TLEN Transfer length 0 19 DOEP5CTL DOEP5CTL Device OUT endpoint-5 control register 0x3A0 32 read-write n 0x0 0x0 CNAK Clear NAK 26 1 write-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write EPTYPE Endpoint type 18 2 read-write MPL maximum packet length 0 11 read-write NAKS NAK status 17 1 read-only SD0PID_SEVENFRM SD0PID/SEVENFRM 28 1 write-only SD1PID_SODDFRM SD1PID/SODDFRM 29 1 write-only SNAK Set NAK 27 1 write-only SNOOP Snoop mode 20 1 read-write STALL STALL handshake 21 1 read-write DOEP5DMAADDR DOEP5DMAADDR device OUT endpoint 5 DMA address register 0x3B4 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 DOEP5INTF DOEP5INTF device out endpoint-5 interrupt register 0x3A8 32 read-write n 0x0 0x0 BTBSTP Back-to-back SETUP packets 6 1 EPDIS Endpoint disabled 1 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 NYET NYET handshake is sent 14 1 STPF Setup phase finished 3 1 TF Transfer finished 0 1 DOEP5LEN DOEP5LEN device OUT endpoint-5 transfer length register 0x3B0 32 read-write n 0x0 0x0 PCNT Packet count 19 10 STPCNT_RXDPID SETUP packet count/Received data PID 29 2 TLEN Transfer length 0 19 DOEPINTEN DOEPINTEN device OUT endpoint common interrupt enable register (DOEPINTEN) 0x14 32 read-write n 0x0 0x0 BTBSTPEN Back-to-back SETUP packets ( Only for control OUT endpoint) interrupt enable bit 6 1 EPDISEN Endpoint disabled interrupt enable 1 1 EPRXFOVREN Endpoint Rx FIFO overrun interrupt enable 4 1 NYETEN NYET handshake is sent interrupt enable 14 1 STPFEN SETUP phase done interrupt enable 3 1 TFEN Transfer completed interrupt enable 0 1 DSTAT DSTAT device status register (DSTAT) 0x8 32 read-only n 0x0 0x0 ES Enumerated speed 1 2 FNRSOF Frame number of the received SOF 8 14 SPST Suspend status 0 1 DVBUSDT DVBUSDT device VBUS discharge time register 0x28 32 read-write n 0x0 0x0 DVBUSDT Device VBUS discharge time 0 16 DVBUSPT DVBUSPT device VBUS pulsing time register 0x2C 32 read-write n 0x0 0x0 DVBUSPT Device VBUS pulsing time 0 12 HS_GLOBAL USB high speed global registers USB_HS 0x0 0x0 0x400 registers n USBHS_EP1_Out 74 USBHS_EP1_In 75 USBHS_WKUP 76 USBHS 77 CID CID core ID register 0x3C 32 read-write n 0x0 0x0 CID Core ID 0 32 DIEP0TFLEN DIEP0TFLEN Device IN endpoint 0 transmit FIFO length (Device mode) HNPTFLEN 0x28 32 read-write n 0x0 0x0 IEP0TXFD in endpoint 0 Tx FIFO depth 0 16 IEP0TXRSAR in endpoint 0 Tx RAM start address 16 16 DIEP1TFLEN DIEP1TFLEN device IN endpoint transmit FIFO size register (DIEP1TFLEN) 0x104 32 read-write n 0x0 0x0 IEPTXFD IN endpoint TxFIFO depth 16 16 IEPTXRSAR IN endpoint FIFO transmit RAM start address 0 16 DIEP2TFLEN DIEP2TFLEN device IN endpoint transmit FIFO size register (DIEP2TFLEN) 0x108 32 read-write n 0x0 0x0 IEPTXFD IN endpoint TxFIFO depth 16 16 IEPTXRSAR IN endpoint FIFO transmit RAM start address 0 16 DIEP3TFLEN DIEP3TFLEN device IN endpoint transmit FIFO size register (DIEP3TXFLEN) 0x10C 32 read-write n 0x0 0x0 IEPTXFD IN endpoint TxFIFO depth 16 16 IEPTXRSAR IN endpoint FIFO transmit RAM start address 0 16 DIEP4TFLEN DIEP4TFLEN device IN endpoint transmit FIFO size register (DIEP4TXFLEN) 0x110 32 read-write n 0x0 0x0 IEPTXFD IN endpoint TxFIFO depth 16 16 IEPTXRSAR IN endpoint FIFO transmit RAM start address 0 16 DIEP5TFLEN DIEP5TFLEN device IN endpoint transmit FIFO size register (DIEP5TXFLEN) 0x114 32 read-write n 0x0 0x0 IEPTXFD IN endpoint TxFIFO depth 16 16 IEPTXRSAR IN endpoint FIFO4 transmit RAM start address 0 16 GAHBCS GAHBCS Global AHB configuration register (GAHBCS) 0x8 32 read-write n 0x0 0x0 BURST AHB burst type used by DMA 1 4 DMAEN DMA function enalbed 5 1 GINTEN Global interrupt enable 0 1 PTXFTH Periodic TxFIFO empty level 8 1 TXFTH TxFIFO threshold 7 1 GCCFG GCCFG Global core configuration register (GCCFG) 0x38 32 read-write n 0x0 0x0 PWRON Power on 16 1 SOFOEN SOF output enable 20 1 VBUSACEN The VBUS A-device Comparer enable 18 1 VBUSBCEN The VBUS B-device Comparer enable 19 1 VBUSIG VBUS ignored 21 1 GINTEN GINTEN Global interrupt enable register (GINTEN) 0x18 32 read-write n 0x0 0x0 DISCIE Disconnect interrupt enable 29 1 read-write ENUMFIE Enumeration finish enable 13 1 read-write EOPFIE End of periodic frame interrupt enable 15 1 read-write ESPIE Early suspend interrupt enable 10 1 read-write GNPINAKIE Global non-periodic IN NAK interrupt enable 6 1 read-write GONAKIE Global OUT NAK effective interrupt enable 7 1 read-write HCIE Host channels interrupt enable 25 1 read-write HPIE Host port interrupt enable 24 1 read-only IDPSCIE ID pin status change interrupt enable 28 1 read-write IEPIE IN endpoints interrupt enable 18 1 read-write ISOINCIE isochronous IN transfer not complete interrupt enable 20 1 read-write ISOOPDIE Isochronous OUT packet dropped interrupt enable 14 1 read-write MFIE Mode fault interrupt enable 1 1 read-write NPTXFEIE Non-periodic TxFIFO empty interrupt enable 5 1 read-write OEPIE OUT endpoints interrupt enable 19 1 read-write OTGIE OTG interrupt enable 2 1 read-write PTXFEIE Periodic TxFIFO empty interrupt enable 26 1 read-write PXNCIE_ISOONCIE periodic transfer not compelete Interrupt enable(Host mode)/isochronous OUT transfer not complete interrupt enable(Device mode) 21 1 read-write RSTIE USB reset interrupt enable 12 1 read-write RXFNEIE Receive FIFO non-empty interrupt enable 4 1 read-write SESIE Session interrupt enable 30 1 read-write SOFIE Start of frame interrupt enable 3 1 read-write SPIE USB suspend interrupt enable 11 1 read-write WKUPIE Wakeup interrupt enable 31 1 read-write GINTF GINTF Global interrupt flag register (GINTF) 0x14 32 read-write n 0x0 0x0 COPM Current mode of operation 0 1 read-only DISCIF Disconnect interrupt flag 29 1 read-write ENUMF Enumeration finished 13 1 read-write EOPFIF End of periodic frame interrupt flag 15 1 read-write ESP Early suspend 10 1 read-write GNPINAK Global IN non-periodic NAK effective 6 1 read-only GONAK Global OUT NAK effective 7 1 read-only HCIF Host channels interrupt flag 25 1 read-only HPIF Host port interrupt flag 24 1 read-only IDPSC ID pin status change 28 1 read-write IEPIF IN endpoint interrupt flag 18 1 read-only ISOINCIF Isochronous IN transfer Not Complete Interrupt Flag 20 1 read-write ISOOPDIF Isochronous OUT packet dropped interrupt flag 14 1 read-write MFIF Mode fault interrupt flag 1 1 read-write NPTXFEIF Non-periodic TxFIFO empty interrupt flag 5 1 read-only OEPIF OUT endpoint interrupt flag 19 1 read-only OTGIF OTG interrupt 2 1 read-only PTXFEIF Periodic TxFIFO empty interrupt flag 26 1 read-only PXNCIF_ISOONCIF periodic transfer not complete interrupt flag(Host mode)/isochronous OUT transfer not complete interrupt flag(Device mode) 21 1 read-write RST USB reset 12 1 read-write RXFNEIF RxFIFO non-empty 4 1 read-only SESIF Session interrupt flag 30 1 read-write SOF Start of frame 3 1 read-write SP USB suspend 11 1 read-write WKUPIF wakeup interrupt flag 31 1 read-write GOTGCS GOTGCS control and status register (GOTGCS) 0x0 32 read-write n 0x0 0x0 ASV A-session valid 18 1 read-only BSV B-session valid 19 1 read-only CIDPS ID pin status 16 1 read-only DHNPEN Device HNP enabled 11 1 read-write DI Debounce interval of a detected connection 17 1 read-only HHNPEN Host HNP enable 10 1 read-write HNPREQ HNP request 9 1 read-write HNPS Host negotiation success 8 1 read-only SRPREQ SRP request 1 1 read-write SRPS Session request success 0 1 read-only GOTGINTF GOTGINTF Global OTG interrupt register (GOTGINTF) 0x4 32 read-write n 0x0 0x0 ADTO A-device timeout 18 1 DF Debounce finish 19 1 HNPDET Host negotiation detected 17 1 HNPEND HNP end 9 1 SESEND Session end 2 1 SRPEND SRPEND 8 1 GRFLEN GRFLEN Global Receive FIFO size register (OTG_FS_GRFLEN) 0x24 32 read-write n 0x0 0x0 RXFD Rx FIFO depth 0 16 GRSTATP_Device GRSTATP_Device Global Receive status pop(Device mode) 0x20 32 read-only n 0x0 0x0 BCOUNT Byte count 4 11 DPID Data PID 15 2 EPNUM Endpoint number 0 4 RPCKST Recieve packet status 17 4 GRSTATP_Host GRSTATP_Host Global Receive status debug pop(Host mode) GRSTATP_Device 0x20 32 read-only n 0x0 0x0 BCOUNT Byte count 4 11 CNUM Channel number 0 4 DPID Data PID 15 2 RPCKST Reivece packet status 17 4 GRSTATR_Device GRSTATR_Device Global Receive status read(Device mode) 0x1C 32 read-only n 0x0 0x0 BCOUNT Byte count 4 11 DPID Data PID 15 2 EPNUM Endpoint number 0 4 RPCKST Recieve packet status 17 4 GRSTATR_Host GRSTATR_Host Global Receive status debug read(Host mode) GRSTATR_Device 0x1C 32 read-only n 0x0 0x0 BCOUNT Byte count 4 11 CNUM Channel number 0 4 DPID Data PID 15 2 RPCKST Reivece packet status 17 4 GRSTCTL GRSTCTL Global reset register (GRSTCTL) 0x10 32 read-write n 0x0 0x0 CSRST Core soft reset 0 1 read-write DMABSY DMA Busy 30 1 read-only DMAIDL DMA idle state 31 1 read-only HCSRST HCLK soft reset 1 1 read-write HFCRST Host frame counter reset 2 1 read-write RXFF RxFIFO flush 4 1 read-write TXFF TxFIFO flush 5 1 read-write TXFNUM TxFIFO number 6 5 read-write GUSBCS GUSBCS USB configuration register (GUSBCS) 0xC 32 read-write n 0x0 0x0 EMBPHY Embedded PHY selected 6 1 read-write FDM Force device mode 30 1 read-write FHM Force host mode 29 1 read-write HNPCEN HNP capability enable 9 1 read-write SRPCEN SRP capability enable 8 1 read-write TOC timeout calibration 0 3 read-write ULPIEOI ULPI external over current indicator 21 1 read-write ULPIEVD ULPI external VBUS driver 20 1 read-write UTT USB turnaround time 10 4 read-write HNPTFLEN HNPTFLEN Host non-periodic transmit FIFO size register (Host mode) 0x28 32 read-write n 0x0 0x0 HNPTXFD host non-periodic TxFIFO depth 16 16 HNPTXRSAR host non-periodic transmit Tx RAM start address 0 16 HNPTFQSTAT HNPTFQSTAT Host non-periodic transmit FIFO/queue status register (HNPTFQSTAT) 0x2C 32 read-only n 0x0 0x0 NPTXFS Non-periodic TxFIFO space available 0 16 NPTXRQS Non-periodic transmit request queue space 16 8 NPTXRQTOP Top entry of the non-periodic Tx request queue 24 7 HPTFLEN HPTFLEN Host periodic transmit FIFO size register (HPTFLEN) 0x100 32 read-write n 0x0 0x0 HPTXFD Host periodic TxFIFO depth 16 16 HPTXFSAR Host periodic TxFIFO start address 0 16 HS_HOST USB on the go full speed host USB_HS 0x0 0x0 0x400 registers n HACHINT HACHINT Host all channels interrupt register 0x14 32 read-only n 0x0 0x0 HACHINT Host all channel interrupts 0 12 HACHINTEN HACHINTEN host all channels interrupt mask register 0x18 32 read-write n 0x0 0x0 CINTEN Channel interrupt enable 0 12 HCH0CTL HCH0CTL host channel-0 control register (HCH0CTL) 0x100 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPC Multiple packet count 20 2 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH0DMAADDR HCH0DMAADDR host channel-0 DMA address register 0x114 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 HCH0INTEN HCH0INTEN host channel-0 interrupt enable register (HCH0INTEN) 0x10C 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DMAERIE DMA error interrupt enable 2 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 NYETIE NYET interrupt enable 6 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer finished interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH0INTF HCH0INTF host channel-0 interrupt flag register (HCH0INTF) 0x108 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DMAER DMA Error 2 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 NYET NYET 6 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer completed 0 1 USBER USB bus error 7 1 HCH0LEN HCH0LEN host channel-0 transfer length register 0x110 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 PING Ping token request 31 1 TLEN Transfer length 0 19 HCH0STCTL HCH0STCTL host channel-0 split transaction control register (HCH0STCTL) 0x104 32 read-write n 0x0 0x0 CSPLT Complete split enable 16 1 HADDR HUB address 7 7 ISOPCE Isochronous OUT payload continuation encoding 14 2 PADDR Port address 0 7 SPLEN Enable high speed split transaction 31 1 HCH10CTL HCH10CTL host channel-10 control register (HCH10CTL) 0x240 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPC Multiple packet count 20 2 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH10DMAADDR HCH10DMAADDR host channel-10 DMA address register 0x254 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 HCH10INTEN HCH10INTEN host channel-10 interrupt enable register (HCH10INTEN) 0x24C 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DMAERIE DMA error interrupt enable 2 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 NYETIE NYET interrupt enable 6 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer finished interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH10INTF HCH10INTF host channel-10 interrupt flag register (HCH10INTF) 0x248 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DMAER DMA Error 2 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 NYET NYET 6 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer completed 0 1 USBER USB bus error 7 1 HCH10LEN HCH10LEN host channel-10 transfer length register 0x250 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 PING Ping token request 31 1 TLEN Transfer length 0 19 HCH10STCTL HCH10STCTL host channel-10 split transaction control register (HCH10STCTL) 0x244 32 read-write n 0x0 0x0 CSPLT Complete split enable 16 1 HADDR HUB address 7 7 ISOPCE Isochronous OUT payload continuation encoding 14 2 PADDR Port address 0 7 SPLEN Enable high speed split transaction 31 1 HCH11CTL HCH11CTL host channel-11 control register (HCH11CTL) 0x260 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPC Multiple packet count 20 2 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH11DMAADDR HCH11DMAADDR host channel-11 DMA address register 0x274 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 HCH11INTEN HCH11INTEN host channel-11 interrupt enable register (HCH11INTEN) 0x26C 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DMAERIE DMA error interrupt enable 2 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 NYETIE NYET interrupt enable 6 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer finished interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH11INTF HCH11INTF host channel-11 interrupt flag register (HCH11INTF) 0x268 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DMAER DMA Error 2 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 NYET NYET 6 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer completed 0 1 USBER USB bus error 7 1 HCH11LEN HCH11LEN host channel-11 transfer length register 0x270 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 PING Ping token request 31 1 TLEN Transfer length 0 19 HCH11STCTL HCH11STCTL host channel-11 split transaction control register (HCH11STCTL) 0x264 32 read-write n 0x0 0x0 CSPLT Complete split enable 16 1 HADDR HUB address 7 7 ISOPCE Isochronous OUT payload continuation encoding 14 2 PADDR Port address 0 7 SPLEN Enable high speed split transaction 31 1 HCH1CTL HCH1CTL host channel-1 control register (HCH1CTL) 0x120 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPC Multiple packet count 20 2 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH1DMAADDR HCH1DMAADDR host channel-1 DMA address register 0x134 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 HCH1INTEN HCH1INTEN host channel-1 interrupt enable register (HCH1INTEN) 0x12C 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DMAERIE DMA error interrupt enable 2 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 NYETIE NYET interrupt enable 6 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer finished interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH1INTF HCH1INTF host channel-1 interrupt flag register (HCH1INTF) 0x128 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DMAER DMA Error 2 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 NYET NYET 6 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer completed 0 1 USBER USB bus error 7 1 HCH1LEN HCH1LEN host channel-1 transfer length register 0x130 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 PING Ping token request 31 1 TLEN Transfer length 0 19 HCH1STCTL HCH1STCTL host channel-1 split transaction control register (HCH1STCTL) 0x124 32 read-write n 0x0 0x0 CSPLT Complete split enable 16 1 HADDR HUB address 7 7 ISOPCE Isochronous OUT payload continuation encoding 14 2 PADDR Port address 0 7 SPLEN Enable high speed split transaction 31 1 HCH2CTL HCH2CTL host channel-2 control register (HCH2CTL) 0x140 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPC Multiple packet count 20 2 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH2DMAADDR HCH2DMAADDR host channel-2 DMA address register 0x154 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 HCH2INTEN HCH2INTEN host channel-2 interrupt enable register (HCH2INTEN) 0x14C 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DMAERIE DMA error interrupt enable 2 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 NYETIE NYET interrupt enable 6 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer finished interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH2INTF HCH2INTF host channel-2 interrupt flag register (HCH2INTF) 0x148 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DMAER DMA Error 2 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 NYET NYET 6 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer completed 0 1 USBER USB bus error 7 1 HCH2LEN HCH2LEN host channel-2 transfer length register 0x150 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 PING Ping token request 31 1 TLEN Transfer length 0 19 HCH2STCTL HCH2STCTL host channel-2 split transaction control register (HCH2STCTL) 0x144 32 read-write n 0x0 0x0 CSPLT Complete split enable 16 1 HADDR HUB address 7 7 ISOPCE Isochronous OUT payload continuation encoding 14 2 PADDR Port address 0 7 SPLEN Enable high speed split transaction 31 1 HCH3CTL HCH3CTL host channel-3 control register (HCH3CTL) 0x160 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPC Multiple packet count 20 2 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH3DMAADDR HCH3DMAADDR host channel-3 DMA address register 0x174 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 HCH3INTEN HCH3INTEN host channel-3 interrupt enable register (HCH3INTEN) 0x16C 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DMAERIE DMA error interrupt enable 2 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 NYETIE NYET interrupt enable 6 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer finished interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH3INTF HCH3INTF host channel-3 interrupt flag register (HCH3INTF) 0x168 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DMAER DMA Error 2 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 NYET NYET 6 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer completed 0 1 USBER USB bus error 7 1 HCH3LEN HCH3LEN host channel-3 transfer length register 0x170 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 PING Ping token request 31 1 TLEN Transfer length 0 19 HCH3STCTL HCH3STCTL host channel-3 split transaction control register (HCH3STCTL) 0x164 32 read-write n 0x0 0x0 CSPLT Complete split enable 16 1 HADDR HUB address 7 7 ISOPCE Isochronous OUT payload continuation encoding 14 2 PADDR Port address 0 7 SPLEN Enable high speed split transaction 31 1 HCH4CTL HCH4CTL host channel-4 control register (HCH4CTL) 0x180 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPC Multiple packet count 20 2 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH4DMAADDR HCH4DMAADDR host channel-4 DMA address register 0x194 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 HCH4INTEN HCH4INTEN host channel-4 interrupt enable register (HCH4INTEN) 0x18C 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DMAERIE DMA error interrupt enable 2 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 NYETIE NYET interrupt enable 6 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer finished interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH4INTF HCH4INTF host channel-4 interrupt flag register (HCH4INTF) 0x188 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DMAER DMA Error 2 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 NYET NYET 6 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer completed 0 1 USBER USB bus error 7 1 HCH4LEN HCH4LEN host channel-4 transfer length register 0x190 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 PING Ping token request 31 1 TLEN Transfer length 0 19 HCH4STCTL HCH4STCTL host channel-4 split transaction control register (HCH4STCTL) 0x184 32 read-write n 0x0 0x0 CSPLT Complete split enable 16 1 HADDR HUB address 7 7 ISOPCE Isochronous OUT payload continuation encoding 14 2 PADDR Port address 0 7 SPLEN Enable high speed split transaction 31 1 HCH5CTL HCH5CTL host channel-5 control register (HCH5CTL) 0x1A0 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPC Multiple packet count 20 2 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH5DMAADDR HCH5DMAADDR host channel-5 DMA address register 0x1B4 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 HCH5INTEN HCH5INTEN host channel-5 interrupt enable register (HCH5INTEN) 0x1AC 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DMAERIE DMA error interrupt enable 2 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 NYETIE NYET interrupt enable 6 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer finished interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH5INTF HCH5INTF host channel-5 interrupt flag register (HCH5INTF) 0x1A8 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DMAER DMA Error 2 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 NYET NYET 6 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer completed 0 1 USBER USB bus error 7 1 HCH5LEN HCH5LEN host channel-5 transfer length register 0x1B0 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 PING Ping token request 31 1 TLEN Transfer length 0 19 HCH5STCTL HCH5STCTL host channel-5 split transaction control register (HCH5STCTL) 0x1A4 32 read-write n 0x0 0x0 CSPLT Complete split enable 16 1 HADDR HUB address 7 7 ISOPCE Isochronous OUT payload continuation encoding 14 2 PADDR Port address 0 7 SPLEN Enable high speed split transaction 31 1 HCH6CTL HCH6CTL host channel-6 control register (HCH6CTL) 0x1C0 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPC Multiple packet count 20 2 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH6DMAADDR HCH6DMAADDR host channel-6 DMA address register 0x1D4 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 HCH6INTEN HCH6INTEN host channel-6 interrupt enable register (HCH6INTEN) 0x1CC 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DMAERIE DMA error interrupt enable 2 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 NYETIE NYET interrupt enable 6 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer finished interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH6INTF HCH6INTF host channel-6 interrupt flag register (HCH6INTF) 0x1C8 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DMAER DMA Error 2 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 NYET NYET 6 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer completed 0 1 USBER USB bus error 7 1 HCH6LEN HCH6LEN host channel-6 transfer length register 0x1D0 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 PING Ping token request 31 1 TLEN Transfer length 0 19 HCH6STCTL HCH6STCTL host channel-6 split transaction control register (HCH6STCTL) 0x1C4 32 read-write n 0x0 0x0 CSPLT Complete split enable 16 1 HADDR HUB address 7 7 ISOPCE Isochronous OUT payload continuation encoding 14 2 PADDR Port address 0 7 SPLEN Enable high speed split transaction 31 1 HCH7CTL HCH7CTL host channel-7 control register (HCH7CTL) 0x1E0 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPC Multiple packet count 20 2 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH7DMAADDR HCH7DMAADDR host channel-7 DMA address register 0x1F4 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 HCH7INTEN HCH7INTEN host channel-7 interrupt enable register (HCH7INTEN) 0x1EC 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DMAERIE DMA error interrupt enable 2 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 NYETIE NYET interrupt enable 6 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer finished interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH7INTF HCH7INTF host channel-7 interrupt flag register (HCH7INTF) 0x1E8 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DMAER DMA Error 2 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 NYET NYET 6 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer completed 0 1 USBER USB bus error 7 1 HCH7LEN HCH7LEN host channel-7 transfer length register 0x1F0 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 PING Ping token request 31 1 TLEN Transfer length 0 19 HCH7STCTL HCH7STCTL host channel-7 split transaction control register (HCH7STCTL) 0x1E4 32 read-write n 0x0 0x0 CSPLT Complete split enable 16 1 HADDR HUB address 7 7 ISOPCE Isochronous OUT payload continuation encoding 14 2 PADDR Port address 0 7 SPLEN Enable high speed split transaction 31 1 HCH8CTL HCH8CTL host channel-8 control register (HCH8CTL) 0x200 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPC Multiple packet count 20 2 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH8DMAADDR HCH8DMAADDR host channel-8 DMA address register 0x214 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 HCH8INTEN HCH8INTEN host channel-8 interrupt enable register (HCH8INTEN) 0x20C 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DMAERIE DMA error interrupt enable 2 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 NYETIE NYET interrupt enable 6 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer finished interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH8INTF HCH8INTF host channel-8 interrupt flag register (HCH8INTF) 0x208 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DMAER DMA Error 2 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 NYET NYET 6 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer completed 0 1 USBER USB bus error 7 1 HCH8LEN HCH8LEN host channel-8 transfer length register 0x210 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 PING Ping token request 31 1 TLEN Transfer length 0 19 HCH8STCTL HCH8STCTL host channel-8 split transaction control register (HCH8STCTL) 0x204 32 read-write n 0x0 0x0 CSPLT Complete split enable 16 1 HADDR HUB address 7 7 ISOPCE Isochronous OUT payload continuation encoding 14 2 PADDR Port address 0 7 SPLEN Enable high speed split transaction 31 1 HCH9CTL HCH9CTL host channel-9 control register (HCH9CTL) 0x220 32 read-write n 0x0 0x0 CDIS Channel disable 30 1 CEN Channel enable 31 1 DAR Device address 22 7 EPDIR Endpoint direction 15 1 EPNUM Endpoint number 11 4 EPTYPE Endpoint type 18 2 LSD Low-speed device 17 1 MPC Multiple packet count 20 2 MPL Maximum packet size 0 11 ODDFRM Odd frame 29 1 HCH9DMAADDR HCH9DMAADDR host channel-9 DMA address register 0x234 32 read-write n 0x0 0x0 DMAADDR DMA address 0 32 HCH9INTEN HCH9INTEN host channel-9 interrupt enable register (HCH9INTEN) 0x22C 32 read-write n 0x0 0x0 ACKIE ACK interrupt enable 5 1 BBERIE Babble error interrupt enable 8 1 CHIE Channel halted interrupt enable 1 1 DMAERIE DMA error interrupt enable 2 1 DTERIE Data toggle error interrupt enable 10 1 NAKIE NAK interrupt enable 4 1 NYETIE NYET interrupt enable 6 1 REQOVRIE request queue overrun interrupt enable 9 1 STALLIE STALL interrupt enable 3 1 TFIE Transfer finished interrupt enable 0 1 USBERIE USB bus error interrupt enable 7 1 HCH9INTF HCH9INTF host channel-9 interrupt flag register (HCH9INTF) 0x228 32 read-write n 0x0 0x0 ACK ACK response received/transmitted interrupt 5 1 BBER Babble error 8 1 CH Channel halted 1 1 DMAER DMA Error 2 1 DTER Data toggle error 10 1 NAK NAK response received interrupt 4 1 NYET NYET 6 1 REQOVR Request queue overrun 9 1 STALL STALL response received interrupt 3 1 TF Transfer completed 0 1 USBER USB bus error 7 1 HCH9LEN HCH9LEN host channel-9 transfer length register 0x230 32 read-write n 0x0 0x0 DPID Data PID 29 2 PCNT Packet count 19 10 PING Ping token request 31 1 TLEN Transfer length 0 19 HCH9STCTL HCH9STCTL host channel-9 split transaction control register (HCH9STCTL) 0x224 32 read-write n 0x0 0x0 CSPLT Complete split enable 16 1 HADDR HUB address 7 7 ISOPCE Isochronous OUT payload continuation encoding 14 2 PADDR Port address 0 7 SPLEN Enable high speed split transaction 31 1 HCTL HCTL host control register (HCTL) 0x0 32 read-write n 0x0 0x0 SPDFSLS Speed limited to FS and LS 2 1 read-write HFINFR HFINFR host frame number/frame time remaining register (HFINFR) 0x8 32 read-only n 0x0 0x0 FRNUM Frame number 0 16 FRT Frame remaining time 16 16 HFT HFT Host frame interval register 0x4 32 read-write n 0x0 0x0 FRI Frame interval 0 16 HPCS HPCS host port control and status register (HPCS) 0x40 32 read-write n 0x0 0x0 PCD Port connect detected 1 1 read-write PCST Port connect status 0 1 read-only PE Port enable 2 1 read-write PEDC Port enable/disable change 3 1 read-write PLST Port line status 10 2 read-only PP Port power 12 1 read-write PREM Port resume 6 1 read-write PRST Port reset 8 1 read-write PS Port speed 17 2 read-only PSP Port suspend 7 1 read-write HPTFQSTAT HPTFQSTAT Host periodic transmit FIFO/queue status register (HPTFQSTAT) 0x10 32 read-write n 0x0 0x0 PTXFS Periodic transmit data FIFO space available 0 16 read-only PTXREQS Periodic Tx request queue space 16 8 read-only PTXREQT Top of the periodic transmit request queue 24 8 read-only HS_PWRCLK USB on the go high speed power and clock USB_HS 0x0 0x0 0x100 registers n PWRCLKCTL PWRCLKCTL power and clock gating control register (PWRCLKCTL) 0x0 32 read-write n 0x0 0x0 SHCLK Stop HCLK 1 1 SUCLK Stop the USB clock 0 1 I2C0 Inter integrated circuit I2C 0x0 0x0 0x400 registers n I2C0_EV 31 I2C0_ER 32 CKCFG CKCFG Clock configure register 0x1C 32 read-write n 0x0 0x0 CLKC I2C Clock control in master mode 0 12 DTCY Duty cycle in fast mode 14 1 FAST I2C speed selection in master mode 15 1 CTL0 CTL0 Control register 0 0x0 32 read-write n 0x0 0x0 ACKEN Whether or not to send an ACK 10 1 ARPEN ARP protocol in SMBus switch 4 1 DISSTRC Whether to stretch SCL low when data is not ready in slave mode 7 1 GCEN Whether or not to response to a General Call (0x00) 6 1 I2CEN I2C peripheral enable 0 1 PECEN PEC Calculation Switch 5 1 PECTRANS PEC Transfer 12 1 POAP Position of ACK and PEC when receiving 11 1 SALT SMBus alert 13 1 SMBEN SMBus/I2C mode switch 1 1 SMBSEL SMBusType Selection 3 1 SRESET Software reset 15 1 START Generate a START condition on I2C bus 8 1 STOP Generate a STOP condition on I2C bus 9 1 CTL1 CTL1 Control register 1 0x4 32 read-write n 0x0 0x0 BUFIE Buffer interrupt enable 10 1 DMALST Flag indicating DMA last transfer 12 1 DMAON DMA mode switch 11 1 ERRIE Error interrupt enable 8 1 EVIE Event interrupt enable 9 1 I2CCLK I2C Peripheral clock frequency 0 6 DATA DATA Transfer buffer register 0x10 32 read-write n 0x0 0x0 TRB Transmission or reception data buffer register 0 8 FCTL FCTL Filter control register 0x24 32 read-write n 0x0 0x0 AFD Analog noise filter disable 4 1 DF Digital noise filter 0 4 RT RT Rise time register 0x20 32 read-write n 0x0 0x0 RISETIME Maximum rise time in master mode 0 6 SADDR0 SADDR0 Slave address register 0 0x8 32 read-write n 0x0 0x0 ADDFORMAT Address mode for the I2C slave 15 1 ADDRESS0 Bit 0 of a 10-bit address 0 1 ADDRESS7_1 7-bit address or bits 7:1 of a 10-bit address 1 7 ADDRESS9_8 Highest two bits of a 10-bit address 8 2 SADDR1 SADDR1 Slave address register 1 0xC 32 read-write n 0x0 0x0 ADDRESS2 Second I2C address for the slave in Dual-Address mode 1 7 DUADEN Dual-Address mode switch 0 1 SAMCS SAMCS SAM control and status register 0x80 32 read-write n 0x0 0x0 RFF Rxframe fall flag 14 1 read-write RFFIE Rxframe fall interrupt enable 6 1 read-write RFR Rxframe rise flag 15 1 read-write RFRIE Rxframe rise interrupt enable 7 1 read-write RXF Level of Rxframe signal 9 1 read-only SAMEN SAM_V interface enable 0 1 read-write STOEN SAM_V interface timeout detect enable 1 1 read-write TFF Txframe fall flag 12 1 read-write TFFIE Txframe fall interrupt enable 4 1 read-write TFR Txframe rise flag 13 1 read-write TFRIE Txframe rise interrupt enable 5 1 read-write TXF Level of Txframe signal 8 1 read-only STAT0 STAT0 Transfer status register 0 0x14 32 read-write n 0x0 0x0 ADD10SEND Header of 10-bit address is sent in master mode 3 1 read-only ADDSEND Address is sent in master mode or received and matches in slave mode 1 1 read-only AERR Acknowledge error 10 1 read-write BERR A bus error occurs indication a unexpected START or STOP condition on I2C bus 8 1 read-write BTC Byte transmission completed 2 1 read-only LOSTARB Arbitration Lost in master mode 9 1 read-write OUERR Over-run or under-run situation occurs in slave mode 11 1 read-write PECERR PEC error when receiving data 12 1 read-write RBNE I2C_DATA is not Empty during receiving 6 1 read-only SBSEND START condition sent out in master mode 0 1 read-only SMBALT SMBus Alert status 15 1 read-write SMBTO Timeout signal in SMBus mode 14 1 read-write STPDET STOP condition detected in slave mode 4 1 read-only TBE I2C_DATA is Empty during transmitting 7 1 read-only STAT1 STAT1 Transfer status register 1 0x18 32 read-only n 0x0 0x0 DEFSMB Default address of SMBusDevice 5 1 DUMODF Dual Flag in slave mode 7 1 ECV Packet Error Checking Value that calculated by hardware when PEC is enabled 8 8 HSTSMB SMBus Host Header detected in slave mode 6 1 I2CBSY Busy flag 1 1 MASTER A flag indicating whether I2C block is in master or slave mode 0 1 RXGC General call address (00h) received 4 1 TRS Whether the I2C is a transmitter or a receiver 2 1 I2C1 Inter integrated circuit I2C 0x0 0x0 0x400 registers n I2C1_EV 33 I2C1_ER 34 CKCFG CKCFG Clock configure register 0x1C 32 read-write n 0x0 0x0 CLKC I2C Clock control in master mode 0 12 DTCY Duty cycle in fast mode 14 1 FAST I2C speed selection in master mode 15 1 CTL0 CTL0 Control register 0 0x0 32 read-write n 0x0 0x0 ACKEN Whether or not to send an ACK 10 1 ARPEN ARP protocol in SMBus switch 4 1 DISSTRC Whether to stretch SCL low when data is not ready in slave mode 7 1 GCEN Whether or not to response to a General Call (0x00) 6 1 I2CEN I2C peripheral enable 0 1 PECEN PEC Calculation Switch 5 1 PECTRANS PEC Transfer 12 1 POAP Position of ACK and PEC when receiving 11 1 SALT SMBus alert 13 1 SMBEN SMBus/I2C mode switch 1 1 SMBSEL SMBusType Selection 3 1 SRESET Software reset 15 1 START Generate a START condition on I2C bus 8 1 STOP Generate a STOP condition on I2C bus 9 1 CTL1 CTL1 Control register 1 0x4 32 read-write n 0x0 0x0 BUFIE Buffer interrupt enable 10 1 DMALST Flag indicating DMA last transfer 12 1 DMAON DMA mode switch 11 1 ERRIE Error interrupt enable 8 1 EVIE Event interrupt enable 9 1 I2CCLK I2C Peripheral clock frequency 0 6 DATA DATA Transfer buffer register 0x10 32 read-write n 0x0 0x0 TRB Transmission or reception data buffer register 0 8 FCTL FCTL Filter control register 0x24 32 read-write n 0x0 0x0 AFD Analog noise filter disable 4 1 DF Digital noise filter 0 4 RT RT Rise time register 0x20 32 read-write n 0x0 0x0 RISETIME Maximum rise time in master mode 0 6 SADDR0 SADDR0 Slave address register 0 0x8 32 read-write n 0x0 0x0 ADDFORMAT Address mode for the I2C slave 15 1 ADDRESS0 Bit 0 of a 10-bit address 0 1 ADDRESS7_1 7-bit address or bits 7:1 of a 10-bit address 1 7 ADDRESS9_8 Highest two bits of a 10-bit address 8 2 SADDR1 SADDR1 Slave address register 1 0xC 32 read-write n 0x0 0x0 ADDRESS2 Second I2C address for the slave in Dual-Address mode 1 7 DUADEN Dual-Address mode switch 0 1 SAMCS SAMCS SAM control and status register 0x80 32 read-write n 0x0 0x0 RFF Rxframe fall flag 14 1 read-write RFFIE Rxframe fall interrupt enable 6 1 read-write RFR Rxframe rise flag 15 1 read-write RFRIE Rxframe rise interrupt enable 7 1 read-write RXF Level of Rxframe signal 9 1 read-only SAMEN SAM_V interface enable 0 1 read-write STOEN SAM_V interface timeout detect enable 1 1 read-write TFF Txframe fall flag 12 1 read-write TFFIE Txframe fall interrupt enable 4 1 read-write TFR Txframe rise flag 13 1 read-write TFRIE Txframe rise interrupt enable 5 1 read-write TXF Level of Txframe signal 8 1 read-only STAT0 STAT0 Transfer status register 0 0x14 32 read-write n 0x0 0x0 ADD10SEND Header of 10-bit address is sent in master mode 3 1 read-only ADDSEND Address is sent in master mode or received and matches in slave mode 1 1 read-only AERR Acknowledge error 10 1 read-write BERR A bus error occurs indication a unexpected START or STOP condition on I2C bus 8 1 read-write BTC Byte transmission completed 2 1 read-only LOSTARB Arbitration Lost in master mode 9 1 read-write OUERR Over-run or under-run situation occurs in slave mode 11 1 read-write PECERR PEC error when receiving data 12 1 read-write RBNE I2C_DATA is not Empty during receiving 6 1 read-only SBSEND START condition sent out in master mode 0 1 read-only SMBALT SMBus Alert status 15 1 read-write SMBTO Timeout signal in SMBus mode 14 1 read-write STPDET STOP condition detected in slave mode 4 1 read-only TBE I2C_DATA is Empty during transmitting 7 1 read-only STAT1 STAT1 Transfer status register 1 0x18 32 read-only n 0x0 0x0 DEFSMB Default address of SMBusDevice 5 1 DUMODF Dual Flag in slave mode 7 1 ECV Packet Error Checking Value that calculated by hardware when PEC is enabled 8 8 HSTSMB SMBus Host Header detected in slave mode 6 1 I2CBSY Busy flag 1 1 MASTER A flag indicating whether I2C block is in master or slave mode 0 1 RXGC General call address (00h) received 4 1 TRS Whether the I2C is a transmitter or a receiver 2 1 I2C2 Inter integrated circuit I2C 0x0 0x0 0x400 registers n I2C2_EV 72 I2C2_ER 73 CKCFG CKCFG Clock configure register 0x1C 32 read-write n 0x0 0x0 CLKC I2C Clock control in master mode 0 12 DTCY Duty cycle in fast mode 14 1 FAST I2C speed selection in master mode 15 1 CTL0 CTL0 Control register 0 0x0 32 read-write n 0x0 0x0 ACKEN Whether or not to send an ACK 10 1 ARPEN ARP protocol in SMBus switch 4 1 DISSTRC Whether to stretch SCL low when data is not ready in slave mode 7 1 GCEN Whether or not to response to a General Call (0x00) 6 1 I2CEN I2C peripheral enable 0 1 PECEN PEC Calculation Switch 5 1 PECTRANS PEC Transfer 12 1 POAP Position of ACK and PEC when receiving 11 1 SALT SMBus alert 13 1 SMBEN SMBus/I2C mode switch 1 1 SMBSEL SMBusType Selection 3 1 SRESET Software reset 15 1 START Generate a START condition on I2C bus 8 1 STOP Generate a STOP condition on I2C bus 9 1 CTL1 CTL1 Control register 1 0x4 32 read-write n 0x0 0x0 BUFIE Buffer interrupt enable 10 1 DMALST Flag indicating DMA last transfer 12 1 DMAON DMA mode switch 11 1 ERRIE Error interrupt enable 8 1 EVIE Event interrupt enable 9 1 I2CCLK I2C Peripheral clock frequency 0 6 DATA DATA Transfer buffer register 0x10 32 read-write n 0x0 0x0 TRB Transmission or reception data buffer register 0 8 FCTL FCTL Filter control register 0x24 32 read-write n 0x0 0x0 AFD Analog noise filter disable 4 1 DF Digital noise filter 0 4 RT RT Rise time register 0x20 32 read-write n 0x0 0x0 RISETIME Maximum rise time in master mode 0 6 SADDR0 SADDR0 Slave address register 0 0x8 32 read-write n 0x0 0x0 ADDFORMAT Address mode for the I2C slave 15 1 ADDRESS0 Bit 0 of a 10-bit address 0 1 ADDRESS7_1 7-bit address or bits 7:1 of a 10-bit address 1 7 ADDRESS9_8 Highest two bits of a 10-bit address 8 2 SADDR1 SADDR1 Slave address register 1 0xC 32 read-write n 0x0 0x0 ADDRESS2 Second I2C address for the slave in Dual-Address mode 1 7 DUADEN Dual-Address mode switch 0 1 SAMCS SAMCS SAM control and status register 0x80 32 read-write n 0x0 0x0 RFF Rxframe fall flag 14 1 read-write RFFIE Rxframe fall interrupt enable 6 1 read-write RFR Rxframe rise flag 15 1 read-write RFRIE Rxframe rise interrupt enable 7 1 read-write RXF Level of Rxframe signal 9 1 read-only SAMEN SAM_V interface enable 0 1 read-write STOEN SAM_V interface timeout detect enable 1 1 read-write TFF Txframe fall flag 12 1 read-write TFFIE Txframe fall interrupt enable 4 1 read-write TFR Txframe rise flag 13 1 read-write TFRIE Txframe rise interrupt enable 5 1 read-write TXF Level of Txframe signal 8 1 read-only STAT0 STAT0 Transfer status register 0 0x14 32 read-write n 0x0 0x0 ADD10SEND Header of 10-bit address is sent in master mode 3 1 read-only ADDSEND Address is sent in master mode or received and matches in slave mode 1 1 read-only AERR Acknowledge error 10 1 read-write BERR A bus error occurs indication a unexpected START or STOP condition on I2C bus 8 1 read-write BTC Byte transmission completed 2 1 read-only LOSTARB Arbitration Lost in master mode 9 1 read-write OUERR Over-run or under-run situation occurs in slave mode 11 1 read-write PECERR PEC error when receiving data 12 1 read-write RBNE I2C_DATA is not Empty during receiving 6 1 read-only SBSEND START condition sent out in master mode 0 1 read-only SMBALT SMBus Alert status 15 1 read-write SMBTO Timeout signal in SMBus mode 14 1 read-write STPDET STOP condition detected in slave mode 4 1 read-only TBE I2C_DATA is Empty during transmitting 7 1 read-only STAT1 STAT1 Transfer status register 1 0x18 32 read-only n 0x0 0x0 DEFSMB Default address of SMBusDevice 5 1 DUMODF Dual Flag in slave mode 7 1 ECV Packet Error Checking Value that calculated by hardware when PEC is enabled 8 8 HSTSMB SMBus Host Header detected in slave mode 6 1 I2CBSY Busy flag 1 1 MASTER A flag indicating whether I2C block is in master or slave mode 0 1 RXGC General call address (00h) received 4 1 TRS Whether the I2C is a transmitter or a receiver 2 1 I2S1_add Serial peripheral interface SPI 0x0 0x0 0x400 registers n SPI0 35 CPCPOLY CPCPOLY CRC polynomial register 0x10 32 read-write n 0x0 0x0 CPR CRC polynomial register 0 16 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 BDEN Bidirectional enable 15 1 BDOEN Bidirectional Transmit output enable 14 1 CKPH Clock Phase Selection 0 1 CKPL Clock polarity Selection 1 1 CRCEN CRC Calculation Enable 13 1 CRCNT CRC Next Transfer 12 1 FF16 Data frame format 11 1 LF LSB First Mode 7 1 MSTMOD Master Mode Enable 2 1 PSC Master Clock Prescaler Selection 3 3 RO Receive only 10 1 SPIEN SPI enable 6 1 SWNSS NSS Pin Selection In NSS Software Mode 8 1 SWNSSEN NSS Software Mode Selection 9 1 CTL1 CTL1 control register 1 0x4 32 read-write n 0x0 0x0 DMAREN Rx buffer DMA enable 0 1 DMATEN Transmit Buffer DMA Enable 1 1 ERRIE Error interrupt enable 5 1 NSSDRV Drive NSS Output 2 1 RBNEIE RX buffer not empty interrupt enable 6 1 TBEIE Tx buffer empty interrupt enable 7 1 TMOD SPI TI Mode Enable 4 1 DATA DATA data register 0xC 32 read-write n 0x0 0x0 SPI_DATA Data transfer register 0 16 I2SCTL I2SCTL I2S control register 0x1C 32 read-write n 0x0 0x0 CHLEN Channel length (number of bits per audio channel) 0 1 CKPL Idle state clock polarity 3 1 DTLEN Data length 1 2 I2SEN I2S Enable 10 1 I2SOPMOD I2S operation mode 8 2 I2SSEL I2S mode selection 11 1 I2SSTD I2S standard selection 4 2 PCMSMOD PCM frame synchronization mode 7 1 I2SPSC I2SPSC I2S prescaler register 0x20 32 read-write n 0x0 0x0 DIV Dividing factor for the prescaler 0 8 MCKOEN I2S_MCK output enable 9 1 OF Odd factor for the prescaler 8 1 RCRC RCRC RX CRC register 0x14 32 read-only n 0x0 0x0 RCR RX CRC register 0 16 STAT STAT status register 0x8 32 read-write n 0x0 0x0 CONFERR SPI Configuration error 5 1 read-only CRCERR SPI CRC Error Bit 4 1 read-write FERR Format Error 8 1 read-write I2SCH I2S channel side 2 1 read-only RBNE Receive Buffer Not Empty 0 1 read-only RXORERR Reception Overrun Error Bit 6 1 read-only TBE Transmit Buffer Empty 1 1 read-only TRANS Transmitting On-going Bit 7 1 read-only TXURERR Transmission underrun error bit 3 1 read-only TCRC TCRC TX CRC register 0x18 32 read-only n 0x0 0x0 TCR Tx CRC register 0 16 I2S2_add Serial peripheral interface SPI 0x0 0x0 0x400 registers n SPI0 35 CPCPOLY CPCPOLY CRC polynomial register 0x10 32 read-write n 0x0 0x0 CPR CRC polynomial register 0 16 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 BDEN Bidirectional enable 15 1 BDOEN Bidirectional Transmit output enable 14 1 CKPH Clock Phase Selection 0 1 CKPL Clock polarity Selection 1 1 CRCEN CRC Calculation Enable 13 1 CRCNT CRC Next Transfer 12 1 FF16 Data frame format 11 1 LF LSB First Mode 7 1 MSTMOD Master Mode Enable 2 1 PSC Master Clock Prescaler Selection 3 3 RO Receive only 10 1 SPIEN SPI enable 6 1 SWNSS NSS Pin Selection In NSS Software Mode 8 1 SWNSSEN NSS Software Mode Selection 9 1 CTL1 CTL1 control register 1 0x4 32 read-write n 0x0 0x0 DMAREN Rx buffer DMA enable 0 1 DMATEN Transmit Buffer DMA Enable 1 1 ERRIE Error interrupt enable 5 1 NSSDRV Drive NSS Output 2 1 RBNEIE RX buffer not empty interrupt enable 6 1 TBEIE Tx buffer empty interrupt enable 7 1 TMOD SPI TI Mode Enable 4 1 DATA DATA data register 0xC 32 read-write n 0x0 0x0 SPI_DATA Data transfer register 0 16 I2SCTL I2SCTL I2S control register 0x1C 32 read-write n 0x0 0x0 CHLEN Channel length (number of bits per audio channel) 0 1 CKPL Idle state clock polarity 3 1 DTLEN Data length 1 2 I2SEN I2S Enable 10 1 I2SOPMOD I2S operation mode 8 2 I2SSEL I2S mode selection 11 1 I2SSTD I2S standard selection 4 2 PCMSMOD PCM frame synchronization mode 7 1 I2SPSC I2SPSC I2S prescaler register 0x20 32 read-write n 0x0 0x0 DIV Dividing factor for the prescaler 0 8 MCKOEN I2S_MCK output enable 9 1 OF Odd factor for the prescaler 8 1 RCRC RCRC RX CRC register 0x14 32 read-only n 0x0 0x0 RCR RX CRC register 0 16 STAT STAT status register 0x8 32 read-write n 0x0 0x0 CONFERR SPI Configuration error 5 1 read-only CRCERR SPI CRC Error Bit 4 1 read-write FERR Format Error 8 1 read-write I2SCH I2S channel side 2 1 read-only RBNE Receive Buffer Not Empty 0 1 read-only RXORERR Reception Overrun Error Bit 6 1 read-only TBE Transmit Buffer Empty 1 1 read-only TRANS Transmitting On-going Bit 7 1 read-only TXURERR Transmission underrun error bit 3 1 read-only TCRC TCRC TX CRC register 0x18 32 read-only n 0x0 0x0 TCR Tx CRC register 0 16 IPA Image processing accelerator IPA 0x0 0x0 0xC00 registers n IPA 90 BLMADDR IPA_BLMADDR Background LUT memory base address register 0x30 32 read-write n 0x0 0x0 BLMADDR Background LUT memory base address 0 32 BLOFF IPA_BLOFF Background line offset register 0x18 32 read-write n 0x0 0x0 BLOFF Background line offset 0 14 BMADDR IPA_BMADDR Background memory base address register 0x14 32 read-write n 0x0 0x0 BMADDR Background memory base address 0 32 BPCTL IPA_BPCTL Background pixel control register 0x24 32 read-write n 0x0 0x0 BAVCA Background alpha value calculation algorithm 16 2 BCNP Background LUT number of pixel 8 8 BLLEN Background LUT loading enable 5 1 BLPF Background LUT pixel format 4 1 BPDAV Background pre- defined alpha value 24 8 BPF Background pixel format 0 4 BPV IPA_BPV Background pixel value register 0x28 32 read-write n 0x0 0x0 BPDBV Background pre-defined blue value 0 8 BPDGV Background pre-defined green value 8 8 BPDRV Background pre-defined red value 16 8 CTL IPA_CTL Control register 0x0 32 read-write n 0x0 0x0 FTFIE Enable bit for full transfer finish interrupt 9 1 LACIE Enable bit for LUT access conflict interrupt 11 1 LLFIE Enable bit for LUT loading finish interrupt 12 1 PFCM Pixel format convert mode 16 2 TAEIE Enable bit for transfer access error interrupt 8 1 TEN Transfer enable 0 1 THU Transfer hang up 1 1 TLMIE Enable bit for transfer line mark interrupt 10 1 TST Transfer stop 2 1 WCFIE Enable bit for wrong configuration interrupt 13 1 DLOFF IPA_DLOFF Destination line offset register 0x40 32 read-write n 0x0 0x0 DLOFF Destination line offset 0 14 DMADDR IPA_DMADDR Destination memory base address register 0x3C 32 read-write n 0x0 0x0 DMADDR Destination memory base address 0 32 DPCTL IPA_DPCTL Destination pixel control register 0x34 32 read-write n 0x0 0x0 DPF Destination pixel format 0 3 DPV_ARGB1555 IPA_DPV_ARGB1555 Destination pixel value register(When the destination pixel format is ARGB1555) IPA_DPV_ARGB8888 0x38 32 read-write n 0x0 0x0 DPDAV Destination pre-defined alpha value 15 1 DPDBV Destination pre-defined blue value 0 5 DPDGV Destination pre-defined green value 5 5 DPDRV Destination pre-defined red value 10 5 DPV_ARGB4444 IPA_DPV_ARGB4444 Destination pixel value register(When the destination pixel format is ARGB4444,) IPA_DPV_ARGB8888 0x38 32 read-write n 0x0 0x0 DPDAV Destination pre-defined alpha value 12 4 DPDBV Destination pre-defined blue value 0 4 DPDGV Destination pre-defined green value 4 4 DPDRV Destination pre-defined red value 8 4 DPV_ARGB8888 IPA_DPV_ARGB8888 Destination pixel value register(When the destination pixel format is ARGB8888) 0x38 32 read-write n 0x0 0x0 DPDAV Destination pre-defined alpha value 24 8 DPDBV Destination pre-defined blue value 0 8 DPDGV Destination pre-defined green value 8 8 DPDRV Destination pre-defined red value 16 8 DPV_RGB565 IPA_DPV_RGB565 Destination pixel value register(When the destination pixel format is RGB565) IPA_DPV_ARGB8888 0x38 32 read-write n 0x0 0x0 DPDBV Destination pre-defined blue value 0 5 DPDGV Destination pre-defined green value 5 6 DPDRV Destination pre-defined red value 11 5 DPV_RGB888 IPA_DPV_RGB888 Destination pixel value register(When the destination pixel format is RGB888) IPA_DPV_ARGB8888 0x38 32 read-write n 0x0 0x0 DPDBV Destination pre-defined blue value 0 8 DPDGV Destination pre-defined green value 8 8 DPDRV Destination pre-defined red value 16 8 FLMADDR IPA_FLMADDR Foreground LUT memory base address register 0x2C 32 read-write n 0x0 0x0 FLMBADDR Foreground LUT memory base address 0 32 FLOFF IPA_FLOFF Foreground line offset register 0x10 32 read-write n 0x0 0x0 FLOFF Foreground line offset 0 14 FMADDR IPA_FMADDR Foreground memory base address register 0xC 32 read-write n 0x0 0x0 FMADDR Foreground memory base address 0 32 FPCTL IPA_FPCTL Foreground pixel control register 0x1C 32 read-write n 0x0 0x0 FAVCA Foreground alpha value calculation algorithm 16 2 FCNP Foreground LUT number of pixel 8 8 FLLEN Foreground LUT loading enable 5 1 FLPF Foreground LUT pixel format 4 1 FPDAV Foreground pre- defined alpha value 24 8 FPF Foreground pixel format 0 4 FPV IPA_FPV Foreground pixel value register 0x20 32 read-write n 0x0 0x0 FPDBV Foreground pre-defined blue value 0 8 FPDGV Foreground pre-defined green value 8 8 FPDRV Foreground pre-defined red value 16 8 IMS IPA_IMS Image size register 0x44 32 read-write n 0x0 0x0 HEIGHT Height of the image to be processed 0 16 WIDTH Width of the image to be processed 16 14 INTC IPA_INTC Interrupt flag clear register 0x8 32 read-write n 0x0 0x0 CWCFIF Clear bit for wrong configuration interrupt flag 5 1 LACIFC Clear bit for LUT access conflict interrupt flag 3 1 LLFIFC Clear bit for LUT loading finish interrupt flag 4 1 TAEIFC Clear bit for transfer access error interrupt flag 0 1 TFIFC Clear bit for full transfer finish interrupt flag 1 1 TLMIF Clear bit for transfer line mark interrupt flag 2 1 INTF IPA_INTF Interrupt flag register 0x4 32 read-only n 0x0 0x0 FTFIF Full transfer finish interrupt flag 1 1 LACIF LUT access conflict interrupt flag 3 1 LLFIF LUT loading finish interrupt flag 4 1 TAEIF Transfer access error interrupt flag 0 1 TLMIF Transfer line mark interrupt flag 2 1 WCFIF Wrong configuration interrupt flag 5 1 ITCTL IPA_ITCTL Inter-timer control register 0x4C 32 read-write n 0x0 0x0 ITEN Inter-timer enable 0 1 NCCI Number of clock cycles interval 8 8 LM IPA_LM Line mark register 0x48 32 read-write n 0x0 0x0 LM line mark 0 16 IREF Programmable current reference IREF 0x0 0x0 0x400 registers n CTL CTL control register 0x300 32 read-write n 0x0 0x0 CPT Current precision trim 8 5 read-write CREN Current reference enable 15 1 read-write CSDT Current step data 0 6 read-write SCMOD Sink current mode 7 1 read-write SSEL Step selection 14 1 read-write NVIC Nested Vectored Interrupt Controller NVIC 0x0 0x0 0xF00 registers n 0x33D 0xC3 reserved n IABR IABR Interrupt Active bit Register 0x200 32 read-write n 0x0 0x0 IABR IABR 0 32 ICER ICER Interrupt Clear Enable Register 0x80 32 read-write n 0x0 0x0 CLRENA CLRENA 0 32 ICPR ICPR Interrupt Clear-Pending Register 0x180 32 read-write n 0x0 0x0 CLRPEND CLRPEND 0 32 IPR0 IPR0 Interrupt Priority Register 0 0x300 8 read-write n 0x0 0x0 PRI_00 PRI_00 0 8 IPR1 IPR1 Interrupt Priority Register 1 0x301 8 read-write n 0x0 0x0 PRI_01 PRI_01 0 8 IPR10 IPR10 Interrupt Priority Register 10 0x30A 8 read-write n 0x0 0x0 PRI_10 PRI_10 0 8 IPR11 IPR11 Interrupt Priority Register 11 0x30B 8 read-write n 0x0 0x0 PRI_11 PRI_11 0 8 IPR12 IPR12 Interrupt Priority Register 12 0x30C 8 read-write n 0x0 0x0 PRI_12 PRI_12 0 8 IPR13 IPR13 Interrupt Priority Register 13 0x30D 8 read-write n 0x0 0x0 PRI_13 PRI_13 0 8 IPR14 IPR14 Interrupt Priority Register 14 0x30E 8 read-write n 0x0 0x0 PRI_14 PRI_14 0 8 IPR15 IPR15 Interrupt Priority Register 15 0x30F 8 read-write n 0x0 0x0 PRI_15 PRI_15 0 8 IPR16 IPR16 Interrupt Priority Register 16 0x310 8 read-write n 0x0 0x0 PRI_16 PRI_16 0 8 IPR17 IPR17 Interrupt Priority Register 17 0x311 8 read-write n 0x0 0x0 PRI_17 PRI_17 0 8 IPR18 IPR18 Interrupt Priority Register 18 0x312 8 read-write n 0x0 0x0 PRI_18 PRI_18 0 8 IPR19 IPR19 Interrupt Priority Register 19 0x313 8 read-write n 0x0 0x0 PRI_19 PRI_19 0 8 IPR2 IPR2 Interrupt Priority Register 2 0x302 8 read-write n 0x0 0x0 PRI_02 PRI_02 0 8 IPR20 IPR20 Interrupt Priority Register 20 0x314 8 read-write n 0x0 0x0 PRI_20 PRI_20 0 8 IPR21 IPR21 Interrupt Priority Register 21 0x315 8 read-write n 0x0 0x0 PRI_21 PRI_21 0 8 IPR22 IPR22 Interrupt Priority Register 22 0x316 8 read-write n 0x0 0x0 PRI_22 PRI_22 0 8 IPR23 IPR23 Interrupt Priority Register 23 0x317 8 read-write n 0x0 0x0 PRI_23 PRI_23 0 8 IPR24 IPR24 Interrupt Priority Register 24 0x318 8 read-write n 0x0 0x0 PRI_24 PRI_24 0 8 IPR25 IPR25 Interrupt Priority Register 25 0x319 8 read-write n 0x0 0x0 PRI_25 PRI_25 0 8 IPR26 IPR26 Interrupt Priority Register 26 0x31A 8 read-write n 0x0 0x0 PRI_26 PRI_26 0 8 IPR27 IPR27 Interrupt Priority Register 27 0x31B 8 read-write n 0x0 0x0 PRI_27 PRI_27 0 8 IPR28 IPR28 Interrupt Priority Register 28 0x31C 8 read-write n 0x0 0x0 PRI_28 PRI_28 0 8 IPR29 IPR29 Interrupt Priority Register 29 0x31D 8 read-write n 0x0 0x0 PRI_29 PRI_29 0 8 IPR3 IPR3 Interrupt Priority Register 3 0x303 8 read-write n 0x0 0x0 PRI_03 PRI_03 0 8 IPR30 IPR30 Interrupt Priority Register 30 0x31E 8 read-write n 0x0 0x0 PRI_30 PRI_30 0 8 IPR31 IPR31 Interrupt Priority Register 31 0x31F 8 read-write n 0x0 0x0 PRI_31 PRI_31 0 8 IPR32 IPR32 Interrupt Priority Register 32 0x320 8 read-write n 0x0 0x0 PRI_32 PRI_32 0 8 IPR33 IPR33 Interrupt Priority Register 33 0x321 8 read-write n 0x0 0x0 PRI_33 PRI_33 0 8 IPR34 IPR34 Interrupt Priority Register 34 0x322 8 read-write n 0x0 0x0 PRI_34 PRI_34 0 8 IPR35 IPR35 Interrupt Priority Register 35 0x323 8 read-write n 0x0 0x0 PRI_35 PRI_35 0 8 IPR36 IPR36 Interrupt Priority Register 36 0x324 8 read-write n 0x0 0x0 PRI_36 PRI_36 0 8 IPR37 IPR37 Interrupt Priority Register 37 0x325 8 read-write n 0x0 0x0 PRI_37 PRI_37 0 8 IPR38 IPR38 Interrupt Priority Register 38 0x326 8 read-write n 0x0 0x0 PRI_38 PRI_38 0 8 IPR39 IPR39 Interrupt Priority Register 39 0x327 8 read-write n 0x0 0x0 PRI_39 PRI_39 0 8 IPR4 IPR4 Interrupt Priority Register 4 0x304 8 read-write n 0x0 0x0 PRI_04 PRI_04 0 8 IPR40 IPR40 Interrupt Priority Register 40 0x328 8 read-write n 0x0 0x0 PRI_40 PRI_40 0 8 IPR41 IPR41 Interrupt Priority Register 41 0x329 8 read-write n 0x0 0x0 PRI_41 PRI_41 0 8 IPR42 IPR42 Interrupt Priority Register 42 0x32A 8 read-write n 0x0 0x0 PRI_42 PRI_42 0 8 IPR43 IPR43 Interrupt Priority Register 43 0x32B 8 read-write n 0x0 0x0 PRI_43 PRI_43 0 8 IPR44 IPR44 Interrupt Priority Register 44 0x32C 8 read-write n 0x0 0x0 PRI_44 PRI_44 0 8 IPR45 IPR45 Interrupt Priority Register 45 0x32D 8 read-write n 0x0 0x0 PRI_45 PRI_45 0 8 IPR46 IPR46 Interrupt Priority Register 46 0x32E 8 read-write n 0x0 0x0 PRI_46 PRI_46 0 8 IPR47 IPR47 Interrupt Priority Register 47 0x32F 8 read-write n 0x0 0x0 PRI_47 PRI_47 0 8 IPR48 IPR48 Interrupt Priority Register 48 0x330 8 read-write n 0x0 0x0 PRI_48 PRI_48 0 8 IPR49 IPR49 Interrupt Priority Register 49 0x331 8 read-write n 0x0 0x0 PRI_49 PRI_49 0 8 IPR5 IPR5 Interrupt Priority Register 5 0x305 8 read-write n 0x0 0x0 PRI_05 PRI_05 0 8 IPR50 IPR50 Interrupt Priority Register 50 0x332 8 read-write n 0x0 0x0 PRI_50 PRI_50 0 8 IPR51 IPR51 Interrupt Priority Register 51 0x333 8 read-write n 0x0 0x0 PRI_51 PRI_51 0 8 IPR52 IPR52 Interrupt Priority Register 52 0x334 8 read-write n 0x0 0x0 PRI_52 PRI_52 0 8 IPR53 IPR53 Interrupt Priority Register 53 0x335 8 read-write n 0x0 0x0 PRI_53 PRI_53 0 8 IPR54 IPR54 Interrupt Priority Register 54 0x336 8 read-write n 0x0 0x0 PRI_54 PRI_54 0 8 IPR55 IPR55 Interrupt Priority Register 55 0x337 8 read-write n 0x0 0x0 PRI_55 PRI_55 0 8 IPR56 IPR56 Interrupt Priority Register 56 0x338 8 read-write n 0x0 0x0 PRI_56 PRI_56 0 8 IPR57 IPR57 Interrupt Priority Register 57 0x339 8 read-write n 0x0 0x0 PRI_57 PRI_57 0 8 IPR58 IPR58 Interrupt Priority Register 58 0x33A 8 read-write n 0x0 0x0 PRI_58 PRI_58 0 8 IPR59 IPR59 Interrupt Priority Register 59 0x33B 8 read-write n 0x0 0x0 PRI_59 PRI_59 0 8 IPR6 IPR6 Interrupt Priority Register 6 0x306 8 read-write n 0x0 0x0 PRI_06 PRI_06 0 8 IPR60 IPR60 Interrupt Priority Register 60 0x33C 8 read-write n 0x0 0x0 PRI_60 PRI_60 0 8 IPR61 IPR61 Interrupt Priority Register 61 0x33D 8 read-write n 0x0 0x0 PRI_61 PRI_61 0 8 IPR62 IPR62 Interrupt Priority Register 62 0x33E 8 read-write n 0x0 0x0 PRI_62 PRI_62 0 8 IPR63 IPR63 Interrupt Priority Register 63 0x33F 8 read-write n 0x0 0x0 PRI_63 PRI_63 0 8 IPR64 IPR64 Interrupt Priority Register 64 0x340 8 read-write n 0x0 0x0 PRI_64 PRI_64 0 8 IPR65 IPR65 Interrupt Priority Register 65 0x341 8 read-write n 0x0 0x0 PRI_65 PRI_65 0 8 IPR66 IPR66 Interrupt Priority Register 66 0x342 8 read-write n 0x0 0x0 PRI_66 PRI_66 0 8 IPR67 IPR67 Interrupt Priority Register 67 0x343 8 read-write n 0x0 0x0 PRI_67 PRI_67 0 8 IPR68 IPR68 Interrupt Priority Register 68 0x344 8 read-write n 0x0 0x0 PRI_68 PRI_68 0 8 IPR69 IPR69 Interrupt Priority Register 69 0x345 8 read-write n 0x0 0x0 PRI_69 PRI_69 0 8 IPR7 IPR7 Interrupt Priority Register 7 0x307 8 read-write n 0x0 0x0 PRI_07 PRI_07 0 8 IPR70 IPR70 Interrupt Priority Register 70 0x346 8 read-write n 0x0 0x0 PRI_70 PRI_70 0 8 IPR71 IPR71 Interrupt Priority Register 71 0x347 8 read-write n 0x0 0x0 PRI_71 PRI_71 0 8 IPR72 IPR72 Interrupt Priority Register 72 0x348 8 read-write n 0x0 0x0 PRI_72 PRI_72 0 8 IPR73 IPR73 Interrupt Priority Register 73 0x349 8 read-write n 0x0 0x0 PRI_73 PRI_73 0 8 IPR8 IPR8 Interrupt Priority Register 8 0x308 8 read-write n 0x0 0x0 PRI_08 PRI_08 0 8 IPR9 IPR9 Interrupt Priority Register 9 0x309 8 read-write n 0x0 0x0 PRI_09 PRI_09 0 8 ISER ISER Interrupt Set Enable Register 0x0 32 read-write n 0x0 0x0 SETENA SETENA 0 32 ISPR ISPR Interrupt Set-Pending Register 0x100 32 read-write n 0x0 0x0 SETPEND SETPEND 0 32 STIR STIR Software Trigger Interrupt Register 0xE00 32 write-only n 0x0 0x0 STIR STIR 0 32 PMU Power management unit PMU 0x0 0x0 0x400 registers n CS CS power control/status register 0x4 32 read-write n 0x0 0x0 BLDOON Backup SRAM LDO on 9 1 read-write BLDORF Backup SRAM LDO ready flag 3 1 read-only HDRF High-driver ready flag 16 1 read-only HDSRF High-driver switch ready flag 17 1 read-only LDOVSRF LDO voltage select ready flag 14 1 read-only LDRF Low-driver mode ready flag 18 2 read-write LVDF Low Voltage Detector Status Flag 2 1 read-only STBF Standby flag 1 1 read-only WUF Wakeup flag 0 1 read-only WUPEN Enable WKUP pin 8 1 read-write CTL CTL power control register 0x0 32 read-write n 0x0 0x0 BKPWEN Backup Domain Write Enable 8 1 HDEN High-driver mode enable 16 1 HDS High-driver mode switch 17 1 LDEN Low-driver mode enable in Deep-sleep mode 18 2 LDLP Low-driver mode when use low power LDO. 10 1 LDNP Low-driver mode when use normal power LDO 11 1 LDOLP LDO Low Power Mode 0 1 LDOVS LDO output voltage select 14 2 LVDEN Low Voltage Detector Enable 4 1 LVDT Low Voltage Detector Threshold 5 3 STBMOD Standby Mode 1 1 STBRST Standby Flag Reset 3 1 WURST Wakeup Flag Reset 2 1 RCU Reset and clock unit RCU 0x0 0x0 0x400 registers n RCU_CTC 5 ADDAPB1EN ADDAPB1EN APB1 additional enable register 0xE4 32 read-write n 0x0 0x0 CTCEN CTC clock enable 27 1 read-write IREFEN IREF interface clock enable 31 1 read-write ADDAPB1RST ADDAPB1RST APB1 additional reset register 0xE0 32 read-write n 0x0 0x0 CTCRST CTC reset 27 1 read-write IREFRST IREF reset 31 1 read-write ADDAPB1SPEN ADDAPB1SPEN APB1 additional sleep mode enable register 0xE8 32 read-write n 0x0 0x0 CTCSPEN CTC enable when sleep mode 27 1 read-write IREFSPEN IREF enable when sleep mode 31 1 read-write ADDCTL ADDCTL Additional clock control register 0xC0 32 read-write n 0x0 0x0 CK48MSEL 48MHz clock selection 0 1 read-write IRC48MCAL Internal 48MHz RC oscillator calibration value register 24 8 read-only IRC48MEN Internal 48MHz RC oscillator enable 16 1 read-write IRC48MSTB Internal 48MHz RC oscillator clock stabilization Flag 17 1 read-only PLL48MSEL PLL48M clock selection 1 1 read-write ADDINT ADDINT Additional clock interrupt register 0xCC 32 read-write n 0x0 0x0 IRC48MSTBIC Internal 48 MHz RC oscillator Stabilization Interrupt Clear 22 1 write IRC48MSTBIE Internal 48 MHz RC oscillator Stabilization Interrupt Enable 14 1 read-write IRC48MSTBIF IRC48M stabilization interrupt flag 6 1 read-only AHB1EN AHB1EN AHB1 enable register 0x30 32 read-write n 0x0 0x0 BKPSRAMEN BKPSRAM clock enable 18 1 CRCEN CRC clock enable 12 1 DMA0EN DMA0 clock enable 21 1 DMA1EN DMA1 clock enable 22 1 ENETEN Ethernet clock enable 25 1 ENETPTPEN Ethernet PTP clock enable 28 1 ENETRXEN Ethernet RX clock enable 27 1 ENETTXEN Ethernet TX clock enable 26 1 IPAEN IPA clock enable 23 1 PAEN GPIO port A clock enable 0 1 PBEN GPIO port B clock enable 1 1 PCEN GPIO port C clock enable 2 1 PDEN GPIO port D clock enable 3 1 PEEN GPIO port E clock enable 4 1 PFEN GPIO port F clock enable 5 1 PGEN GPIO port G clock enable 6 1 PHEN GPIO port H clock enable 7 1 PIEN GPIO port I clock enable 8 1 TCMSRAMEN TCMSRAM clock enable 20 1 USBHSEN USBHS clock enable 29 1 USBHSULPIEN USBHS ULPI clock enable 30 1 AHB1RST AHB1RST AHB1 reset register 0x10 32 read-write n 0x0 0x0 CRCRST CRC reset 12 1 DMA0RST DMA0 reset 21 1 DMA1RST DMA1 reset 22 1 ENETRST Ethernet reset 25 1 IPARST IPA reset 23 1 PARST GPIO port A reset 0 1 PBRST GPIO port B reset 1 1 PCRST GPIO port C reset 2 1 PDRST GPIO port D reset 3 1 PERST GPIO port E reset 4 1 PFRST GPIO port F reset 5 1 PGRST GPIO port G reset 6 1 PHRST GPIO port H reset 7 1 PIRST GPIO port I reset 8 1 USBHSRST USBHS reset 29 1 AHB1SPEN AHB1SPEN AHB1 sleep mode enable register 0x50 32 read-write n 0x0 0x0 BKPSRAMSPEN BKPSRAM clock enable when sleep mode 18 1 CRCSPEN CRC clock enable when sleep mode 12 1 DMA0SPEN DMA0 clock enable when sleep mode 21 1 DMA1SPEN DMA1 clock enable when sleep mode 22 1 ENETPTPSPEN Ethernet PTP clock enable when sleep mode 28 1 ENETRXSPEN Ethernet RX clock enable when sleep mode 27 1 ENETSPEN Ethernet clock enable when sleep mode 25 1 ENETTXSPEN Ethernet TX clock enable when sleep mode 26 1 FMCSPEN FMC clock enable when sleep mode 15 1 IPASPEN IPA clock enable when sleep mode 23 1 PASPEN GPIO port A clock enable when sleep mode 0 1 PBSPEN GPIO port B clock enable when sleep mode 1 1 PCSPEN GPIO port C clock enable when sleep mode 2 1 PDSPEN GPIO port D clock enable when sleep mode 3 1 PESPEN GPIO port E clock enable when sleep mode 4 1 PFSPEN GPIO port F clock enable when sleep mode 5 1 PGSPEN GPIO port G clock enable when sleep mode 6 1 PHSPEN GPIO port H clock enable when sleep mode 7 1 PISPEN GPIO port I clock enable when sleep mode 8 1 SRAM0SPEN SRAM0 clock enable when sleep mode 16 1 SRAM1SPEN SRAM1 clock enable when sleep mode 17 1 SRAM2SPEN SRAM2 clock enable when sleep mode 19 1 USBHSSPEN USBHS clock enable when sleep mode 29 1 USBHSULPISPEN USBHS ULPI clock enable when sleep mode 30 1 AHB2EN AHB2EN AHB2 enable register 0x34 32 read-write n 0x0 0x0 DCIEN DCI clock enable 0 1 TRNGEN TRNG clock enable 6 1 USBFSEN USBFS clock enable 7 1 AHB2RST AHB2RST AHB2 reset register 0x14 32 read-write n 0x0 0x0 DCIRST DCI reset 0 1 TRNGRST TRNG reset 6 1 USBFSRST USBFS reset 7 1 AHB2SPEN AHB2SPEN AHB2 sleep mode enable register 0x54 32 read-write n 0x0 0x0 DCISPEN DCI clock enable when sleep mode 0 1 TRNGSPEN TRNG clock enable when sleep mode 6 1 USBFSSPEN USBFS clock enable when sleep mode 7 1 AHB3EN AHB3EN AHB3 clock enable register 0x38 32 read-write n 0x0 0x0 EXMCEN EXMC clock enable 0 1 AHB3RST AHB3RST AHB3 reset register 0x18 32 read-write n 0x0 0x0 EXMCRST EXMC reset 0 1 AHB3SPEN AHB3SPEN AHB3 Sleep mode enable register 0x58 32 read-write n 0x0 0x0 EXMCSPEN EXMC clock enable when sleep mode 0 1 APB1EN APB1EN APB1 clock enable register (RCU_APB1EN) 0x40 32 read-write n 0x0 0x0 CAN0EN CAN0 clock enable 25 1 CAN1EN CAN1 clock enable 26 1 DACEN DAC clock enable 29 1 I2C0EN I2C0 clock enable 21 1 I2C1EN I2C1 clock enable 22 1 I2C2EN I2C2 clock enable 23 1 PMUEN Power control clock enable 28 1 SPI1EN SPI1 clock enable 14 1 SPI2EN SPI2 clock enable 15 1 TIMER11EN TIMER11 timer clock enable 6 1 TIMER12EN TIMER12 timer clock enable 7 1 TIMER13EN TIMER13 timer clock enable 8 1 TIMER1EN TIMER1 timer clock enable 0 1 TIMER2EN TIMER2 timer clock enable 1 1 TIMER3EN TIMER3 timer clock enable 2 1 TIMER4EN TIMER4 timer clock enable 3 1 TIMER5EN TIMER5 timer clock enable 4 1 TIMER6EN TIMER6 timer clock enable 5 1 UART3EN UART3 clock enable 19 1 UART4EN UART4 clock enable 20 1 UART6EN UART6 clock enable 30 1 UART7EN UART7 clock enable 31 1 USART1EN USART1 clock enable 17 1 USART2EN USART2 clock enable 18 1 WWDGTEN Window watchdog timer clock enable 11 1 APB1RST APB1RST APB1 reset register (RCU_APB1RST) 0x20 32 read-write n 0x0 0x0 CAN0RST CAN0 reset 25 1 CAN1RST CAN1 reset 26 1 DACRST DAC reset 29 1 I2C0RST I2C0 reset 21 1 I2C1RST I2C1 reset 22 1 I2C2RST I2C2 reset 23 1 PMURST Power control reset 28 1 SPI1RST SPI1 reset 14 1 SPI2RST SPI2 reset 15 1 TIMER11RST TIMER11 timer reset 6 1 TIMER12RST TIMER12 timer reset 7 1 TIMER13RST TIMER13 timer reset 8 1 TIMER1RST TIMER1 timer reset 0 1 TIMER2RST TIMER2 timer reset 1 1 TIMER3RST TIMER3 timer reset 2 1 TIMER4RST TIMER4 timer reset 3 1 TIMER5RST TIMER5 timer reset 4 1 TIMER6RST TIMER6 timer reset 5 1 UART3RST UART3 reset 19 1 UART4RST UART4 reset 20 1 UART6RST UART6 reset 30 1 UART7RST UART7 reset 31 1 USART1RST USART1 reset 17 1 USART2RST USART2 reset 18 1 WWDGTRST Window watchdog timer reset 11 1 APB1SPEN APB1SPEN APB1 sleep mode clock enable register (RCU_APB1EN) 0x60 32 read-write n 0x0 0x0 CAN0SPEN CAN0 clock enable when sleep mode 25 1 CAN1SPEN CAN1 clock enable when sleep mode 26 1 DACSPEN DAC clock enable when sleep mode 29 1 I2C0SPEN I2C0 clock enable when sleep mode 21 1 I2C1SPEN I2C1 clock enable when sleep mode 22 1 I2C2SPEN I2C2 clock enable when sleep mode 23 1 PMUSPEN Power control clock enable when sleep mode 28 1 SPI1SPEN SPI1 clock enable when sleep mode 14 1 SPI2SPEN SPI2 clock enable when sleep mode 15 1 TIMER11SPEN TIMER11 timer clock enable when sleep mode 6 1 TIMER12SPEN TIMER12 timer clock enable when sleep mode 7 1 TIMER13SPEN TIMER13 timer clock enable when sleep mode 8 1 TIMER1SPEN TIMER1 timer clock enable when sleep mode 0 1 TIMER2SPEN TIMER2 timer clock enable when sleep mode 1 1 TIMER3SPEN TIMER3 timer clock enable when sleep mode 2 1 TIMER4SPEN TIMER4 timer clock enable when sleep mode 3 1 TIMER5SPEN TIMER5 timer clock enable when sleep mode 4 1 TIMER6SPEN TIMER6 timer clock enable when sleep mode 5 1 UART3SPEN UART3 clock enable when sleep mode 19 1 UART4SPEN UART4 clock enable when sleep mode 20 1 UART6SPEN UART6 clock enable when sleep mode 30 1 UART7SPEN UART7 clock enable when sleep mode 31 1 USART1SPEN USART1 clock enable when sleep mode 17 1 USART2SPEN USART2 clock enable when sleep mode 18 1 WWDGTSPEN Window watchdog timer clock enable when sleep mode 11 1 APB2EN APB2EN APB2 clock enable register (RCU_APB2EN) 0x44 32 read-write n 0x0 0x0 ADC0EN ADC0 clock enable 8 1 ADC1EN ADC1 clock enable 9 1 ADC2EN ADC2 clock enable 10 1 SDIOEN SDIO clock enable 11 1 SPI0EN SPI0 clock enable 12 1 SPI3EN SPI3 clock enable 13 1 SPI4EN SPI4 clock enable 20 1 SPI5EN SPI5 clock enable 21 1 SYSCFGEN SYSCFG clock enable 14 1 TIMER0EN TIMER0 clock enable 0 1 TIMER10EN TIMER10 clock enable 18 1 TIMER7EN TIMER7 clock enable 1 1 TIMER8EN TIMER8 clock enable 16 1 TIMER9EN TIMER9 clock enable 17 1 TLIEN TLI clock enable 26 1 USART0EN USART0 clock enable 4 1 USART5EN USART5 clock enable 5 1 APB2RST APB2RST APB2 reset register (RCU_APB2RST) 0x24 32 read-write n 0x0 0x0 ADCRST ADC reset 8 1 SDIORST SDIO reset 11 1 SPI0RST SPI0 Reset 12 1 SPI3RST SPI3 Reset 13 1 SPI4RST SPI4 Reset 20 1 SPI5RST SPI5 Reset 21 1 SYSCFGRST SYSCFG Reset 14 1 TIMER0RST TIMER0 reset 0 1 TIMER10RST TIMER10 reset 18 1 TIMER7RST TIMER7 reset 1 1 TIMER8RST TIMER8 reset 16 1 TIMER9RST TIMER9 reset 17 1 TLIRST TLI Reset 26 1 USART0RST USART0 reset 4 1 USART5RST USART5 reset 5 1 APB2SPEN APB2SPEN APB2 sleep mode enable register (RCU_APB2SPEN) 0x64 32 read-write n 0x0 0x0 ADC0SPEN ADC0 clock enable when sleep mode 8 1 ADC1SPEN ADC1 clock enable when sleep mode 9 1 ADC2SPEN ADC2 clock enable when sleep mode 10 1 SDIOSPEN SDIO clock enable when sleep mode 11 1 SPI0SPEN SPI0 clock enable when sleep mode 12 1 SPI3SPEN SPI3 clock enable when sleep mode 13 1 SPI4SPEN SPI4 clock enable when sleep mode 20 1 SPI5SPEN SPI5 clock enable when sleep mode 21 1 SYSCFGSPEN SYSCFG clock enable when sleep mode 14 1 TIMER0SPEN TIMER0 clock enable when sleep mode 0 1 TIMER10SPEN TIMER10 clock enable when sleep mode 18 1 TIMER7SPEN TIMER7 clock enable when sleep mode 1 1 TIMER8SPEN TIMER8 clock enable when sleep mode 16 1 TIMER9SPEN TIMER9 clock enable when sleep mode 17 1 TLISPEN TLI clock enable when sleep mode 26 1 USART0SPEN USART0 clock enable when sleep mode 4 1 USART5SPEN USART5 clock enable when sleep mode 5 1 BDCTL BDCTL Backup domain control register (RCU_BDCTL) 0x70 32 read-write n 0x0 0x0 BKPRST Backup domain reset 16 1 read-write LXTALBPS LXTAL bypass mode enable 2 1 read-write LXTALDRI LXTAL drive capability 3 2 read-write LXTALEN LXTAL enable 0 1 read-write LXTALSTB External low-speed oscillator stabilization 1 1 read-only RTCEN RTC clock enable 15 1 read-write RTCSRC RTC clock entry selection 8 2 read-write CFG0 CFG0 Clock configuration register 0 (RCU_CFG0) 0x8 32 read-write n 0x0 0x0 AHBPSC AHB prescaler selection 4 4 read-write APB1PSC APB1 prescaler selection 10 3 read-write APB2PSC APB2 prescaler selection 13 3 read-write CKOUT0DIV The CK_OUT0 divider which the CK_OUT0 frequency can be reduced 24 3 read-write CKOUT0SEL CKOUT0 Clock Source Selection 21 2 read-write CKOUT1DIV The CK_OUT1 divider which the CK_OUT1 frequency can be reduced 27 3 read-write CKOUT1SEL CKOUT1 Clock Source Selection 30 2 read-write I2SSEL I2S Clock Source Selection 23 1 read-write RTCDIV RTC clock divider factor 16 5 read-write SCS System clock switch 0 2 read-write SCSS System clock switch status 2 2 read-only CFG1 CFG1 Clock Configuration register 1 0x8C 32 read-write n 0x0 0x0 PLLSAIRDIV The divider factor from PLLSAIR clock 16 2 TIMERSEL TIMER clock selection 24 1 CTL CTL Control register 0x0 32 read-write n 0x0 0x0 CKMEN HXTAL Clock Monitor Enable 19 1 read-write HXTALBPS External crystal oscillator (HXTAL) clock bypass mode enable 18 1 read-write HXTALEN External High Speed oscillator Enable 16 1 read-write HXTALSTB External crystal oscillator (HXTAL) clock stabilization flag 17 1 read-only IRC16MADJ Internal 16MHz RC Oscillator clock trim adjust value 3 5 read-write IRC16MCALIB Internal 16MHz RC Oscillator calibration value register 8 8 read-only IRC16MEN Internal 16MHz RC oscillator Enable 0 1 read-write IRC16MSTB IRC16M Internal 16MHz RC Oscillator stabilization Flag 1 1 read-only PLLEN PLL enable 24 1 read-write PLLI2SEN PLLI2S enable 26 1 read-write PLLI2SSTB PLLI2S Clock Stabilization Flag 27 1 read-only PLLSAIEN PLLSAI enable 28 1 read-write PLLSAISTB PLLSAI Clock Stabilization Flag 29 1 read-only PLLSTB PLL Clock Stabilization Flag 25 1 read-only DSV DSV Deep sleep mode Voltage register 0x134 32 read-write n 0x0 0x0 DSLPVS Deep-sleep mode voltage select 0 3 read-write INT INT Clock interrupt register (RCU_INT) 0xC 32 read-write n 0x0 0x0 CKMIC HXTAL Clock Stuck Interrupt Clear 23 1 write-only CKMIF HXTAL Clock Stuck Interrupt Flag 7 1 read-only HXTALSTBIC HXTAL Stabilization Interrupt Clear 19 1 write-only HXTALSTBIE HXTAL Stabilization Interrupt Enable 11 1 read-write HXTALSTBIF HXTAL stabilization interrupt flag 3 1 read-only IRC16MSTBIC IRC16M Stabilization Interrupt Clear 18 1 write-only IRC16MSTBIE IRC16M Stabilization Interrupt Enable 10 1 read-write IRC16MSTBIF IRC16M stabilization interrupt flag 2 1 read-only IRC32KSTBIC IRC32K Stabilization Interrupt Clear 16 1 write-only IRC32KSTBIE IRC32K Stabilization interrupt enable 8 1 read-write IRC32KSTBIF IRC32K stabilization interrupt flag 0 1 read-only LXTALSTBIC LXTAL Stabilization Interrupt Clear 17 1 write-only LXTALSTBIE LXTAL Stabilization Interrupt Enable 9 1 read-write LXTALSTBIF LXTAL stabilization interrupt flag 1 1 read-only PLLI2SSTBIC PLLI2S stabilization Interrupt Clear 21 1 write-only PLLI2SSTBIE PLLI2S Stabilization Interrupt Enable 13 1 read-write PLLI2SSTBIF PLLI2S stabilization interrupt flag 5 1 read-only PLLSAISTBIC PLLSAI stabilization Interrupt Clear 22 1 write-only PLLSAISTBIE PLLSAI Stabilization Interrupt Enable 14 1 read-write PLLSAISTBIF PLLSAI stabilization interrupt flag 6 1 read-only PLLSTBIC PLL stabilization Interrupt Clear 20 1 write-only PLLSTBIE PLL Stabilization Interrupt Enable 12 1 read-write PLLSTBIF PLL stabilization interrupt flag 4 1 read-only PLL PLL PLL register (RCU_PLL) 0x4 32 read-write n 0x0 0x0 PLLN The PLL VCO clock multi factor 6 9 read-write PLLP The PLLP output frequency division factor from PLL VCO clock 16 2 read-write PLLPSC The PLL VCO source clock prescaler 0 6 read-write PLLQ The PLL Q output frequency division factor from PLL VCO clock 24 4 read-write PLLSEL PLL Clock Source Selection 22 1 read-write PLLI2S PLLI2S PLLI2S register (RCU_PLLI2S) 0x84 32 read-write n 0x0 0x0 PLLI2SN The PLLI2S VCO clock multi factor 6 9 read-write PLLI2SPSC The PLLI2S VCO source clock prescaler 0 6 read-write PLLI2SQ The PLLI2S Q output frequency division factor from PLLI2S VCO clock 24 4 read-write PLLI2SR The PLLI2S R output frequency division factor from PLLI2S VCO clock 28 3 read-write PLLSAI PLLSAI PLLSAI register (RCU_PLLSAI) 0x88 32 read-write n 0x0 0x0 PLLSAIN The PLLSAI VCO clock multi factor 6 9 read-write PLLSAIP The PLLSAI P output frequency division factor from PLLSAI VCO clock 16 2 read-write PLLSAIQ The PLLI2S Q output frequency division factor from PLLI2S VCO clock 24 4 read-write PLLSAIR The PLLSAI R output frequency division factor from PLLSAI VCO clock 28 3 read-write PLLSSCTL PLLSSCTL PLL clock spread spectrum control register (RCU_PLLSSCTL) 0x80 32 read-write n 0x0 0x0 MODCNT configure PLL spread spectrum modulation profile amplitude and frequency 0 13 read-write MODSTEP configure PLL spread spectrum modulation profile amplitude and frequency 13 15 read-write SSCGON PLL spread spectrum modulation enable 31 1 read-write SS_TYPE PLL spread spectrum modulation type select 30 1 read-write RSTSCK RSTSCK Reset source /clock register (RCU_RSTSCK) 0x74 32 read-write n 0x0 0x0 BORRSTF BOR reset flag 25 1 read-only EPRSTF External PIN reset flag 26 1 read-only FWDGTRSTF Free Watchdog timer reset flag 29 1 read-only IRC32KEN IRC32K enable 0 1 read-write IRC32KSTB IRC32K stabilization 1 1 read-only LPRSTF Low-power reset flag 31 1 read-only PORRSTF Power reset flag 27 1 read-only RSTFC Reset flag clear 24 1 read-write SWRSTF Software reset flag 28 1 read-only WWDGTRSTF Window watchdog timer reset flag 30 1 read-only VKEY VKEY Voltage key register 0x100 32 read-write n 0x0 0x0 KEY The key of RCU_DSV registe 0 32 write RTC Real-time clock RTC 0x0 0x0 0x400 registers n RTC_T amper 2 RTC_WKUP 3 RTC_Alarm 41 ALRM0SS ALRM0SS alarm A sub second register 0x44 32 read-write n 0x0 0x0 MSKSSC Mask control bit of SSC 24 4 SSC Alarm sub second value 0 15 ALRM0TD ALRM0TD Alarm 0 time and date register 0x1C 32 read-write n 0x0 0x0 DAYT Date tens in BCD code. 28 2 DAYU Date units or week day in BCD code. 24 4 DOWS Day of the week selected 30 1 HRT Hour tens in BCD code. 20 2 HRU Hour units in BCD code. 16 4 MNT Minute tens in BCD code. 12 3 MNU Minute units in BCD code. 8 4 MSKD Alarm date mask bit 31 1 MSKH Alarm hours mask bit 23 1 MSKM Alarm minutes mask bit 15 1 MSKS Alarm seconds mask bit 7 1 PM AM/PM flag 22 1 SCT Second tens in BCD code. 4 3 SCU Second units in BCD code. 0 4 ALRM1SS ALRM1SS Alarm 1 sub second register 0x48 32 read-write n 0x0 0x0 MSKSSC Mask control bit of SSC 24 4 SSC Alarm sub second value 0 15 ALRM1TD ALRM1TD Alarm 1 time and date register 0x20 32 read-write n 0x0 0x0 DAYT Date tens in BCD code. 28 2 DAYU Date units or week day in BCD code. 24 4 DOWS Day of the week selected 30 1 HRT Hour tens in BCD code. 20 2 HRU Hour units in BCD code. 16 4 MNT Minute tens in BCD code. 12 3 MNU Minute units in BCD code. 8 4 MSKD Alarm date mask bit 31 1 MSKH Alarm hours mask bit 23 1 MSKM Alarm minutes mask bit 15 1 MSKS Alarm seconds mask bit 7 1 PM AM/PM flag 22 1 SCT Second tens in BCD code. 4 3 SCU Second units in BCD code. 0 4 BKP0 BKP0 backup register 0x50 32 read-write n 0x0 0x0 DATA BKP 0 32 BKP1 BKP1 backup register 0x54 32 read-write n 0x0 0x0 DATA Data 0 32 BKP10 BKP10 backup register 0x78 32 read-write n 0x0 0x0 DATA Data 0 32 BKP11 BKP11 backup register 0x7C 32 read-write n 0x0 0x0 DATA Data 0 32 BKP12 BKP12 backup register 0x80 32 read-write n 0x0 0x0 DATA Data 0 32 BKP13 BKP13 backup register 0x84 32 read-write n 0x0 0x0 DATA Data 0 32 BKP14 BKP14 backup register 0x88 32 read-write n 0x0 0x0 DATA Data 0 32 BKP15 BKP15 backup register 0x8C 32 read-write n 0x0 0x0 DATA Data 0 32 BKP16 BKP16 backup register 0x90 32 read-write n 0x0 0x0 DATA Data 0 32 BKP17 BKP7 backup register 0x94 32 read-write n 0x0 0x0 DATA Data 0 32 BKP18 BKP18 backup register 0x98 32 read-write n 0x0 0x0 DATA Data 0 32 BKP19 BKP19 backup register 0x9C 32 read-write n 0x0 0x0 DATA Data 0 32 BKP2 BKP2 backup register 0x58 32 read-write n 0x0 0x0 DATA Data 0 32 BKP3 BKP3 backup register 0x5C 32 read-write n 0x0 0x0 DATA Data 0 32 BKP4 BKP4 backup register 0x60 32 read-write n 0x0 0x0 DATA Data 0 32 BKP5 BKP5 backup register 0x64 32 read-write n 0x0 0x0 DATA Data 0 32 BKP6 BKP6 backup register 0x68 32 read-write n 0x0 0x0 DATA Data 0 32 BKP7 BKP7 backup register 0x6C 32 read-write n 0x0 0x0 DATA Data 0 32 BKP8 BKP8 backup register 0x70 32 read-write n 0x0 0x0 DATA Data 0 32 BKP9 BKP9 backup register 0x74 32 read-write n 0x0 0x0 DATA Data 0 32 COSC COSC Coarse calibration register 0x18 32 read-write n 0x0 0x0 COSD Coarse Calibration direction 7 1 COSS Coarse Calibration step 0 5 CTL CTL control register 0x8 32 read-write n 0x0 0x0 A1H Add 1 hour (summer time change) 16 1 write-only ALRM0EN Alarm-0 function enable 8 1 read-write ALRM0IE RTC alarm-0 interrupt enable 12 1 read-write ALRM1EN Alarm-1 function enable 9 1 read-write ALRM1IE RTC alarm-1 interrupt enable 13 1 read-write BPSHAD Shadow registers bypass control 5 1 read-write CCEN Coarse calibration function enable 7 1 read-write COEN Calibration output enable 23 1 read-write COS Calibration output selection 19 1 read-write CS Clock System 6 1 read-write DSM Daylight saving mark 18 1 read-write OPOL Output polarity 20 1 read-write OS Output selection 21 2 read-write REFEN Reference clock detection function enable enable (50 or 60 Hz) 4 1 read-write S1H Subtract 1 hour (winter time change) 17 1 write-only TSEG Valid event edge of time-stamp 3 1 read-write TSEN Time-stamp function enable 11 1 read-write TSIE Time-stamp interrupt enable 15 1 read-write WTCS Auto-wakeup timer clock selection 0 3 read-write WTEN Auto-wakeup timer function enable 10 1 read-write WTIE Auto-wakeup timer interrupt enable 14 1 read-write DATE DATE date register 0x4 32 read-write n 0x0 0x0 DAYT Date tens in BCD code 4 2 DAYU Date units in BCD code 0 4 DOW Days of the week 13 3 MONT Month tens in BCD code 12 1 MONU Month units in BCD code 8 4 YRT Year tens in BCD code 20 4 YRU Year units in BCD code 16 4 DTS DTS Date of time stamp register 0x34 32 read-only n 0x0 0x0 DAYT Date tens in BCD format 4 2 DAYU Date units in BCD format 0 4 DOW Week day units 13 3 MONT Month tens in BCD format 12 1 MONU Month units in BCD format 8 4 HRFC HRFC calibration register 0x3C 32 read-write n 0x0 0x0 CMSK Calibration mask number 0 9 CWND16 Frequency compensation window 16 second selected 13 1 CWND8 Frequency compensation window 8 second selected 14 1 FREQI Increase RTC frequency by 488.5PPM 15 1 PSC PSC prescaler register 0x10 32 read-write n 0x0 0x0 FACTOR_A Asynchronous prescaler factor 16 7 FACTOR_S Synchronous prescaler factor 0 15 SHIFTCTL SHIFTCTL shift function control register 0x2C 32 write-only n 0x0 0x0 A1S One second add 31 1 SFS Subtract a fraction of a second 0 15 SS SS sub second register 0x28 32 read-only n 0x0 0x0 SSC Sub second value 0 16 SSTS SSTS Sub second of time stamp register 0x38 32 read-only n 0x0 0x0 SSC Sub second value 0 16 STAT STAT status register 0xC 32 read-write n 0x0 0x0 ALRM0F Alarm-0 occurs flag 8 1 read-write ALRM0WF Alarm 0 configuration can be write flag 0 1 read-only ALRM1F Alarm-1 occurs flag 9 1 read-write ALRM1WF Alarm 1 configuration can be write flag 1 1 read-only INITF Initialization state flag 6 1 read-only INITM Enter initialization mode 7 1 read-write RSYNF Register synchronization flag 5 1 read-write SCPF Smooth calibration pending flag 16 1 read-only SOPF Shift function operation pending flag 3 1 read-write TP0F RTC_TAMP0 detected flag 13 1 read-write TP1F RTC_TAMP1 detected flag 14 1 read-write TSF Time-stamp flag 11 1 read-write TSOVRF Time-stamp overflow flag 12 1 read-write WTF Wakeup timer flag 10 1 read-write WTWF Wakeup timer write enable flag 2 1 read-only YCM Year configuration mark 4 1 read-only TAMP TAMP tamper and alternate function configuration register 0x40 32 read-write n 0x0 0x0 AOT RTC_ALARM Output Type 18 1 DISPU RTC_TAMPx pull-up disable 15 1 FLT RTC_TAMPx filter count setting 11 2 FREQ Sampling frequency of tamper event detection 8 3 PRCH Pre-charge duration time of RTC_TAMPx 13 2 TP0EG Tamper 0 event trigger edge 1 1 TP0EN Tamper 0 detection enable 0 1 TP0SEL Tamper 0 function input mapping selection 16 1 TP1EG Tamper 1 event trigger edge 4 1 TP1EN Tamper 1 detection enable 3 1 TPIE Tamper detection interrupt enable 2 1 TPTS Make tamper function used for timestamp function 7 1 TSSEL Timestamp input mapping selection 17 1 TIME TIME time register 0x0 32 read-write n 0x0 0x0 HRT Hour tens in BCD format 20 2 HRU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 PM AM/PM notation 22 1 SCT Second tens in BCD format 4 3 SCU Second units in BCD format 0 4 TTS TTS Time of time stamp register 0x30 32 read-only n 0x0 0x0 HRT Hour tens in BCD code. 20 2 HRU Hour units in BCD code. 16 4 MNT Minute tens in BCD code. 12 3 MNU Minute units in BCD code. 8 4 PM AM/PM mark 22 1 SCT Second tens in BCD code. 4 3 SCU Second units in BCD code. 0 4 WPK WPK write protection register 0x24 32 write-only n 0x0 0x0 WPK Write protection key 0 8 WUT WUT Wakeup timer register 0x14 32 read-write n 0x0 0x0 WTRV Auto-wakeup timer reloads value 0 16 SDIO Secure digital input/output interface SDIO 0x0 0x0 0x400 registers n SDIO 49 CLKCTL CLKCTL Clock control register 0x4 32 read-write n 0x0 0x0 BUSMODE SDIO card bus mode control bit 11 2 CLKBYP Clock bypass enable bit 10 1 CLKEDGE SDIO_CLK clock edge selection bit 13 1 CLKEN SDIO_CLK clock output enable bit 8 1 CLKPWRSAV SDIO_CLK clock dynamic switch on/off for power saving 9 1 DIV_0_7 Clock division 0 8 DIV_8 MSB of Clock division 31 1 HWCLKEN Hardware Clock Control enable bit 14 1 CMDAGMT CMDAGMT Command argument register 0x8 32 read-write n 0x0 0x0 CMDAGMT SDIO card command argument 0 32 CMDCTL CMDCTL Command control register 0xC 32 read-write n 0x0 0x0 ATAEN CE-ATA command enable(CE-ATA only) 14 1 CMDIDX Command index 0 6 CMDRESP Command response type bits 6 2 CSMEN Command state machine (CSM) enable bit 10 1 ENCMDC CMD completion signal enabled (CE-ATA only) 12 1 INTWAIT Interrupt wait instead of timeout 8 1 NINTEN No CE-ATA Interrupt (CE-ATA only) 13 1 SUSPEND SD I/O suspend command(SD I/O only) 11 1 WAITDEND Waits for ends of data transfer 9 1 DATACNT DATACNT Data counter register 0x30 32 read-only n 0x0 0x0 DATACNT Data count value 0 25 DATACTL DATACTL Data control register 0x2C 32 read-write n 0x0 0x0 BLKSZ Data block size 4 4 DATADIR Data transfer direction 1 1 DATAEN Data transfer enabled bit 0 1 DMAEN DMA enable bit 3 1 IOEN SD I/O specific function enable 11 1 RWEN Read wait mode enabled 8 1 RWSTOP Read wait stop 9 1 RWTYPE Read wait type 10 1 TRANSMOD Data transfer mode 2 1 DATALEN DATALEN Data length register 0x28 32 read-write n 0x0 0x0 DATALEN Data transfer length 0 25 DATATO DATATO Data timeout register 0x24 32 read-write n 0x0 0x0 DATATO Data timeout period 0 32 FIFO FIFO FIFO data register 0x80 32 read-write n 0x0 0x0 FIFODT Receive FIFO data or transmit FIFO data 0 32 FIFOCNT FIFOCNT FIFO counter register 0x48 32 read-only n 0x0 0x0 FIFOCNT FIFO counter 0 24 INTC INTC Interrupt clear register 0x38 32 write-only n 0x0 0x0 ATAENDC ATAEND flag clear bit 23 1 CCRCERRC CCRCERR flag clear bit 0 1 CMDRECVC CMDRECV flag clear bit 6 1 CMDSENDC CMDSEND flag clear bit 7 1 CMDTMOUTC CMDTMOUT flag clear bit 2 1 DTBLKENDC DTBLKEND flag clear bit 10 1 DTCRCERRC DTCRCERR flag clear bit 1 1 DTENDC DTEND flag clear bit 8 1 DTTMOUTC DTTMOUT flag clear bit 3 1 RXOREC RXORE flag clear bit 5 1 SDIOINTC SDIOINT flag clear bit 22 1 STBITEC STBITE flag clear bit 9 1 TXUREC TXURE flag clear bit 4 1 INTEN INTEN Interrupt enable register 0x3C 32 read-write n 0x0 0x0 ATAENDIE CE-ATA command completion signal received interrupt enable 23 1 CCRCERRIE Command response CRC fail interrupt enable 0 1 CMDRECVIE Command response received interrupt enable 6 1 CMDRUNIE Command transmission interrupt enable 11 1 CMDSENDIE Command sent interrupt enable 7 1 CMDTMOUTIE Command response timeout interrupt enable 2 1 DTBLKENDIE Data block end interrupt enable 10 1 DTCRCERRIE Data CRC fail interrupt enable 1 1 DTENDIE Data end interrupt enable 8 1 DTTMOUTIE Data timeout interrupt enable 3 1 RFEIE Receive FIFO empty interrupt enable 19 1 RFFIE Receive FIFO full interrupt enable 17 1 RFHIE Receive FIFO half full interrupt enable 15 1 RXDTVALIE Data valid in receive FIFO interrupt enable 21 1 RXOREIE Received FIFO overrun error interrupt enable 5 1 RXRUNIE Data reception interrupt enable 13 1 SDIOINTIE SD I/O interrupt received interrupt enable 22 1 STBITEIE Start bit error interrupt enable 9 1 TFEIE Transmit FIFO empty interrupt enable 18 1 TFFIE Transmit FIFO full interrupt enable 16 1 TFHIE Transmit FIFO half empty interrupt enable 14 1 TXDTVALIE Data valid in transmit FIFO interrupt enable 20 1 TXRUNIE Data transmission interrupt enable 12 1 TXUREIE Transmit FIFO underrun error interrupt enable 4 1 PWRCTL PWRCTL Power control register 0x0 32 read-write n 0x0 0x0 PWRCTL SDIO power control bits 0 2 RESP0 RESP0 Response register 0 0x14 32 read-only n 0x0 0x0 RESP0 Card state 0 32 RESP1 RESP1 Response register 1 0x18 32 read-only n 0x0 0x0 RESP1 Card state 0 32 RESP2 RESP2 Response register 2 0x1C 32 read-only n 0x0 0x0 RESP2 Card state 0 32 RESP3 RESP3 Response register 3 0x20 32 read-only n 0x0 0x0 RESP3 Response register 3 0 32 RSPCMDIDX RSPCMDIDX Command index response register 0x10 32 read-only n 0x0 0x0 RSPCMDIDX Last response command index 0 6 STAT STAT Status register 0x34 32 read-only n 0x0 0x0 ATAEND CE-ATA command completion signal received 23 1 CCRCERR Command response received 0 1 CMDRECV Command response received 6 1 CMDRUN Command transmission in progress 11 1 CMDSEND Command sent 7 1 CMDTMOUT Command response timeout 2 1 DTBLKEND Data block sent/received 10 1 DTCRCERR Data block sent/received 1 1 DTEND Data end 8 1 DTTMOUT Data timeout 3 1 RFE Receive FIFO is empty 19 1 RFF Receive FIFO is full 17 1 RFH Receive FIFO is half full 15 1 RXDTVAL Data is valid in receive FIFO 21 1 RXORE Received FIFO overrun error occurs 5 1 RXRUN Data reception in progress 13 1 SDIOINT SD I/O interrupt received 22 1 STBITE Start bit error in the bus 9 1 TFE Transmit FIFO is empty 18 1 TFF Transmit FIFO is full 16 1 TFH Transmit FIFO is half empty 14 1 TXDTVAL Data is valid in transmit FIFO 20 1 TXRUN Data transmission in progress 12 1 TXURE Transmit FIFO underrun error occurs 4 1 SPI0 Serial peripheral interface SPI 0x0 0x0 0x400 registers n SPI0 35 CPCPOLY CPCPOLY CRC polynomial register 0x10 32 read-write n 0x0 0x0 CPR CRC polynomial register 0 16 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 BDEN Bidirectional enable 15 1 BDOEN Bidirectional Transmit output enable 14 1 CKPH Clock Phase Selection 0 1 CKPL Clock polarity Selection 1 1 CRCEN CRC Calculation Enable 13 1 CRCNT CRC Next Transfer 12 1 FF16 Data frame format 11 1 LF LSB First Mode 7 1 MSTMOD Master Mode Enable 2 1 PSC Master Clock Prescaler Selection 3 3 RO Receive only 10 1 SPIEN SPI enable 6 1 SWNSS NSS Pin Selection In NSS Software Mode 8 1 SWNSSEN NSS Software Mode Selection 9 1 CTL1 CTL1 control register 1 0x4 32 read-write n 0x0 0x0 DMAREN Rx buffer DMA enable 0 1 DMATEN Transmit Buffer DMA Enable 1 1 ERRIE Error interrupt enable 5 1 NSSDRV Drive NSS Output 2 1 RBNEIE RX buffer not empty interrupt enable 6 1 TBEIE Tx buffer empty interrupt enable 7 1 TMOD SPI TI Mode Enable 4 1 DATA DATA data register 0xC 32 read-write n 0x0 0x0 SPI_DATA Data transfer register 0 16 I2SCTL I2SCTL I2S control register 0x1C 32 read-write n 0x0 0x0 CHLEN Channel length (number of bits per audio channel) 0 1 CKPL Idle state clock polarity 3 1 DTLEN Data length 1 2 I2SEN I2S Enable 10 1 I2SOPMOD I2S operation mode 8 2 I2SSEL I2S mode selection 11 1 I2SSTD I2S standard selection 4 2 PCMSMOD PCM frame synchronization mode 7 1 I2SPSC I2SPSC I2S prescaler register 0x20 32 read-write n 0x0 0x0 DIV Dividing factor for the prescaler 0 8 MCKOEN I2S_MCK output enable 9 1 OF Odd factor for the prescaler 8 1 RCRC RCRC RX CRC register 0x14 32 read-only n 0x0 0x0 RCR RX CRC register 0 16 STAT STAT status register 0x8 32 read-write n 0x0 0x0 CONFERR SPI Configuration error 5 1 read-only CRCERR SPI CRC Error Bit 4 1 read-write FERR Format Error 8 1 read-write I2SCH I2S channel side 2 1 read-only RBNE Receive Buffer Not Empty 0 1 read-only RXORERR Reception Overrun Error Bit 6 1 read-only TBE Transmit Buffer Empty 1 1 read-only TRANS Transmitting On-going Bit 7 1 read-only TXURERR Transmission underrun error bit 3 1 read-only TCRC TCRC TX CRC register 0x18 32 read-only n 0x0 0x0 TCR Tx CRC register 0 16 SPI1 Serial peripheral interface SPI 0x0 0x0 0x400 registers n SPI1 36 CPCPOLY CPCPOLY CRC polynomial register 0x10 32 read-write n 0x0 0x0 CPR CRC polynomial register 0 16 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 BDEN Bidirectional enable 15 1 BDOEN Bidirectional Transmit output enable 14 1 CKPH Clock Phase Selection 0 1 CKPL Clock polarity Selection 1 1 CRCEN CRC Calculation Enable 13 1 CRCNT CRC Next Transfer 12 1 FF16 Data frame format 11 1 LF LSB First Mode 7 1 MSTMOD Master Mode Enable 2 1 PSC Master Clock Prescaler Selection 3 3 RO Receive only 10 1 SPIEN SPI enable 6 1 SWNSS NSS Pin Selection In NSS Software Mode 8 1 SWNSSEN NSS Software Mode Selection 9 1 CTL1 CTL1 control register 1 0x4 32 read-write n 0x0 0x0 DMAREN Rx buffer DMA enable 0 1 DMATEN Transmit Buffer DMA Enable 1 1 ERRIE Error interrupt enable 5 1 NSSDRV Drive NSS Output 2 1 RBNEIE RX buffer not empty interrupt enable 6 1 TBEIE Tx buffer empty interrupt enable 7 1 TMOD SPI TI Mode Enable 4 1 DATA DATA data register 0xC 32 read-write n 0x0 0x0 SPI_DATA Data transfer register 0 16 I2SCTL I2SCTL I2S control register 0x1C 32 read-write n 0x0 0x0 CHLEN Channel length (number of bits per audio channel) 0 1 CKPL Idle state clock polarity 3 1 DTLEN Data length 1 2 I2SEN I2S Enable 10 1 I2SOPMOD I2S operation mode 8 2 I2SSEL I2S mode selection 11 1 I2SSTD I2S standard selection 4 2 PCMSMOD PCM frame synchronization mode 7 1 I2SPSC I2SPSC I2S prescaler register 0x20 32 read-write n 0x0 0x0 DIV Dividing factor for the prescaler 0 8 MCKOEN I2S_MCK output enable 9 1 OF Odd factor for the prescaler 8 1 RCRC RCRC RX CRC register 0x14 32 read-only n 0x0 0x0 RCR RX CRC register 0 16 STAT STAT status register 0x8 32 read-write n 0x0 0x0 CONFERR SPI Configuration error 5 1 read-only CRCERR SPI CRC Error Bit 4 1 read-write FERR Format Error 8 1 read-write I2SCH I2S channel side 2 1 read-only RBNE Receive Buffer Not Empty 0 1 read-only RXORERR Reception Overrun Error Bit 6 1 read-only TBE Transmit Buffer Empty 1 1 read-only TRANS Transmitting On-going Bit 7 1 read-only TXURERR Transmission underrun error bit 3 1 read-only TCRC TCRC TX CRC register 0x18 32 read-only n 0x0 0x0 TCR Tx CRC register 0 16 SPI2 Serial peripheral interface SPI 0x0 0x0 0x400 registers n SPI2 51 CPCPOLY CPCPOLY CRC polynomial register 0x10 32 read-write n 0x0 0x0 CPR CRC polynomial register 0 16 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 BDEN Bidirectional enable 15 1 BDOEN Bidirectional Transmit output enable 14 1 CKPH Clock Phase Selection 0 1 CKPL Clock polarity Selection 1 1 CRCEN CRC Calculation Enable 13 1 CRCNT CRC Next Transfer 12 1 FF16 Data frame format 11 1 LF LSB First Mode 7 1 MSTMOD Master Mode Enable 2 1 PSC Master Clock Prescaler Selection 3 3 RO Receive only 10 1 SPIEN SPI enable 6 1 SWNSS NSS Pin Selection In NSS Software Mode 8 1 SWNSSEN NSS Software Mode Selection 9 1 CTL1 CTL1 control register 1 0x4 32 read-write n 0x0 0x0 DMAREN Rx buffer DMA enable 0 1 DMATEN Transmit Buffer DMA Enable 1 1 ERRIE Error interrupt enable 5 1 NSSDRV Drive NSS Output 2 1 RBNEIE RX buffer not empty interrupt enable 6 1 TBEIE Tx buffer empty interrupt enable 7 1 TMOD SPI TI Mode Enable 4 1 DATA DATA data register 0xC 32 read-write n 0x0 0x0 SPI_DATA Data transfer register 0 16 I2SCTL I2SCTL I2S control register 0x1C 32 read-write n 0x0 0x0 CHLEN Channel length (number of bits per audio channel) 0 1 CKPL Idle state clock polarity 3 1 DTLEN Data length 1 2 I2SEN I2S Enable 10 1 I2SOPMOD I2S operation mode 8 2 I2SSEL I2S mode selection 11 1 I2SSTD I2S standard selection 4 2 PCMSMOD PCM frame synchronization mode 7 1 I2SPSC I2SPSC I2S prescaler register 0x20 32 read-write n 0x0 0x0 DIV Dividing factor for the prescaler 0 8 MCKOEN I2S_MCK output enable 9 1 OF Odd factor for the prescaler 8 1 RCRC RCRC RX CRC register 0x14 32 read-only n 0x0 0x0 RCR RX CRC register 0 16 STAT STAT status register 0x8 32 read-write n 0x0 0x0 CONFERR SPI Configuration error 5 1 read-only CRCERR SPI CRC Error Bit 4 1 read-write FERR Format Error 8 1 read-write I2SCH I2S channel side 2 1 read-only RBNE Receive Buffer Not Empty 0 1 read-only RXORERR Reception Overrun Error Bit 6 1 read-only TBE Transmit Buffer Empty 1 1 read-only TRANS Transmitting On-going Bit 7 1 read-only TXURERR Transmission underrun error bit 3 1 read-only TCRC TCRC TX CRC register 0x18 32 read-only n 0x0 0x0 TCR Tx CRC register 0 16 SPI3 Serial peripheral interface SPI 0x0 0x0 0x400 registers n SPI3 84 CPCPOLY CPCPOLY CRC polynomial register 0x10 32 read-write n 0x0 0x0 CPR CRC polynomial register 0 16 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 BDEN Bidirectional enable 15 1 BDOEN Bidirectional Transmit output enable 14 1 CKPH Clock Phase Selection 0 1 CKPL Clock polarity Selection 1 1 CRCEN CRC Calculation Enable 13 1 CRCNT CRC Next Transfer 12 1 FF16 Data frame format 11 1 LF LSB First Mode 7 1 MSTMOD Master Mode Enable 2 1 PSC Master Clock Prescaler Selection 3 3 RO Receive only 10 1 SPIEN SPI enable 6 1 SWNSS NSS Pin Selection In NSS Software Mode 8 1 SWNSSEN NSS Software Mode Selection 9 1 CTL1 CTL1 control register 1 0x4 32 read-write n 0x0 0x0 DMAREN Rx buffer DMA enable 0 1 DMATEN Transmit Buffer DMA Enable 1 1 ERRIE Error interrupt enable 5 1 NSSDRV Drive NSS Output 2 1 RBNEIE RX buffer not empty interrupt enable 6 1 TBEIE Tx buffer empty interrupt enable 7 1 TMOD SPI TI Mode Enable 4 1 DATA DATA data register 0xC 32 read-write n 0x0 0x0 SPI_DATA Data transfer register 0 16 I2SCTL I2SCTL I2S control register 0x1C 32 read-write n 0x0 0x0 CHLEN Channel length (number of bits per audio channel) 0 1 CKPL Idle state clock polarity 3 1 DTLEN Data length 1 2 I2SEN I2S Enable 10 1 I2SOPMOD I2S operation mode 8 2 I2SSEL I2S mode selection 11 1 I2SSTD I2S standard selection 4 2 PCMSMOD PCM frame synchronization mode 7 1 I2SPSC I2SPSC I2S prescaler register 0x20 32 read-write n 0x0 0x0 DIV Dividing factor for the prescaler 0 8 MCKOEN I2S_MCK output enable 9 1 OF Odd factor for the prescaler 8 1 RCRC RCRC RX CRC register 0x14 32 read-only n 0x0 0x0 RCR RX CRC register 0 16 STAT STAT status register 0x8 32 read-write n 0x0 0x0 CONFERR SPI Configuration error 5 1 read-only CRCERR SPI CRC Error Bit 4 1 read-write FERR Format Error 8 1 read-write I2SCH I2S channel side 2 1 read-only RBNE Receive Buffer Not Empty 0 1 read-only RXORERR Reception Overrun Error Bit 6 1 read-only TBE Transmit Buffer Empty 1 1 read-only TRANS Transmitting On-going Bit 7 1 read-only TXURERR Transmission underrun error bit 3 1 read-only TCRC TCRC TX CRC register 0x18 32 read-only n 0x0 0x0 TCR Tx CRC register 0 16 SPI4 Serial peripheral interface SPI 0x0 0x0 0x400 registers n SPI4 85 CPCPOLY CPCPOLY CRC polynomial register 0x10 32 read-write n 0x0 0x0 CPR CRC polynomial register 0 16 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 BDEN Bidirectional enable 15 1 BDOEN Bidirectional Transmit output enable 14 1 CKPH Clock Phase Selection 0 1 CKPL Clock polarity Selection 1 1 CRCEN CRC Calculation Enable 13 1 CRCNT CRC Next Transfer 12 1 FF16 Data frame format 11 1 LF LSB First Mode 7 1 MSTMOD Master Mode Enable 2 1 PSC Master Clock Prescaler Selection 3 3 RO Receive only 10 1 SPIEN SPI enable 6 1 SWNSS NSS Pin Selection In NSS Software Mode 8 1 SWNSSEN NSS Software Mode Selection 9 1 CTL1 CTL1 control register 1 0x4 32 read-write n 0x0 0x0 DMAREN Rx buffer DMA enable 0 1 DMATEN Transmit Buffer DMA Enable 1 1 ERRIE Error interrupt enable 5 1 NSSDRV Drive NSS Output 2 1 RBNEIE RX buffer not empty interrupt enable 6 1 TBEIE Tx buffer empty interrupt enable 7 1 TMOD SPI TI Mode Enable 4 1 DATA DATA data register 0xC 32 read-write n 0x0 0x0 SPI_DATA Data transfer register 0 16 I2SCTL I2SCTL I2S control register 0x1C 32 read-write n 0x0 0x0 CHLEN Channel length (number of bits per audio channel) 0 1 CKPL Idle state clock polarity 3 1 DTLEN Data length 1 2 I2SEN I2S Enable 10 1 I2SOPMOD I2S operation mode 8 2 I2SSEL I2S mode selection 11 1 I2SSTD I2S standard selection 4 2 PCMSMOD PCM frame synchronization mode 7 1 I2SPSC I2SPSC I2S prescaler register 0x20 32 read-write n 0x0 0x0 DIV Dividing factor for the prescaler 0 8 MCKOEN I2S_MCK output enable 9 1 OF Odd factor for the prescaler 8 1 RCRC RCRC RX CRC register 0x14 32 read-only n 0x0 0x0 RCR RX CRC register 0 16 STAT STAT status register 0x8 32 read-write n 0x0 0x0 CONFERR SPI Configuration error 5 1 read-only CRCERR SPI CRC Error Bit 4 1 read-write FERR Format Error 8 1 read-write I2SCH I2S channel side 2 1 read-only RBNE Receive Buffer Not Empty 0 1 read-only RXORERR Reception Overrun Error Bit 6 1 read-only TBE Transmit Buffer Empty 1 1 read-only TRANS Transmitting On-going Bit 7 1 read-only TXURERR Transmission underrun error bit 3 1 read-only TCRC TCRC TX CRC register 0x18 32 read-only n 0x0 0x0 TCR Tx CRC register 0 16 SPI5 Serial peripheral interface SPI 0x0 0x0 0x400 registers n SPI5 86 CPCPOLY CPCPOLY CRC polynomial register 0x10 32 read-write n 0x0 0x0 CPR CRC polynomial register 0 16 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 BDEN Bidirectional enable 15 1 BDOEN Bidirectional Transmit output enable 14 1 CKPH Clock Phase Selection 0 1 CKPL Clock polarity Selection 1 1 CRCEN CRC Calculation Enable 13 1 CRCNT CRC Next Transfer 12 1 FF16 Data frame format 11 1 LF LSB First Mode 7 1 MSTMOD Master Mode Enable 2 1 PSC Master Clock Prescaler Selection 3 3 RO Receive only 10 1 SPIEN SPI enable 6 1 SWNSS NSS Pin Selection In NSS Software Mode 8 1 SWNSSEN NSS Software Mode Selection 9 1 CTL1 CTL1 control register 1 0x4 32 read-write n 0x0 0x0 DMAREN Rx buffer DMA enable 0 1 DMATEN Transmit Buffer DMA Enable 1 1 ERRIE Error interrupt enable 5 1 NSSDRV Drive NSS Output 2 1 RBNEIE RX buffer not empty interrupt enable 6 1 TBEIE Tx buffer empty interrupt enable 7 1 TMOD SPI TI Mode Enable 4 1 DATA DATA data register 0xC 32 read-write n 0x0 0x0 SPI_DATA Data transfer register 0 16 I2SCTL I2SCTL I2S control register 0x1C 32 read-write n 0x0 0x0 CHLEN Channel length (number of bits per audio channel) 0 1 CKPL Idle state clock polarity 3 1 DTLEN Data length to be transferred 1 2 I2SEN I2S Enable 10 1 I2SOPMOD I2S operation mode 8 2 I2SSEL I2S mode selection 11 1 I2SSTD I2S standard selection 4 2 PCMSMOD PCM frame synchronization mode 7 1 I2SPSC I2SPSC I2S prescaler register 0x20 32 read-write n 0x0 0x0 DIV Dividing factor for the prescaler 0 8 MCKOEN I2S_MCK output enable 9 1 OF Odd factor for the prescaler 8 1 QCTL QCTL Quad-SPI mode control register 0x80 32 read-write n 0x0 0x0 IO23_DRV Drive IO2 and IO3 enable 2 1 QMOD Quad-SPI mode enable 0 1 QRD Quad-SPI mode read select 1 1 RCRC RCRC RX CRC register 0x14 32 read-only n 0x0 0x0 RCR RX CRC register 0 16 STAT STAT status register 0x8 32 read-write n 0x0 0x0 CONFERR SPI Configuration error 5 1 read-only CRCERR SPI CRC Error Bit 4 1 read-write FERR Format Error 8 1 read-write I2SCH I2S channel side 2 1 read-only RBNE Receive Buffer Not Empty 0 1 read-only RXORERR Reception Overrun Error Bit 6 1 read-only TBE Transmit Buffer Empty 1 1 read-only TRANS Transmitting On-going Bit 7 1 read-only TXURERR Transmission underrun error bit 3 1 read-only TCRC TCRC TX CRC register 0x18 32 read-only n 0x0 0x0 TCR Tx CRC register 0 16 SYSCFG System configuration controller SYSCFG 0x0 0x0 0x400 registers n CFG0 CFG0 Configuration register 0 0x0 32 read-write n 0x0 0x0 BOOT_MODE Boot mode 0 3 read-write EXMC_SWP EXMC memory mapping swap 10 2 read-write FMC_SWP FMC memory mapping swap 8 1 read-write CFG1 CFG1 Configuration register 1 0x4 32 read-write n 0x0 0x0 ENET_PHY_SEL Ethernet PHY selection 23 1 CPSCTL CPSCTL I/O compensation control register 0x20 32 read-write n 0x0 0x0 CPS_EN I/O compensation cell enable 0 1 CPS_RDY I/O compensation cell is ready or not 8 1 EXTISS0 EXTISS0 EXTI sources selection register 0 0x8 32 read-write n 0x0 0x0 EXTI0_SS EXTI 0 sources selection 0 4 EXTI1_SS EXTI 1 sources selection 4 4 EXTI2_SS EXTI 2 sources selection 8 4 EXTI3_SS EXTI 3 sources selection 12 4 EXTISS1 EXTISS1 EXTI sources selection register 1 0xC 32 read-write n 0x0 0x0 EXTI4_SS EXTI 4 sources selection 0 4 EXTI5_SS EXTI 5 sources selection 4 4 EXTI6_SS EXTI 6 sources selection 8 4 EXTI7_SS EXTI 7 sources selection 12 4 EXTISS2 EXTISS2 EXTI sources selection register 2 0x10 32 read-write n 0x0 0x0 EXTI10_SS EXTI 10 sources selection 8 4 EXTI11_SS EXTI 11 sources selection 12 4 EXTI8_SS EXTI 8 sources selection 0 4 EXTI9_SS EXTI 9 sources selection 4 4 EXTISS3 EXTISS3 EXTI sources selection register 3 0x14 32 read-write n 0x0 0x0 EXTI12_SS EXTI 12 sources selection 0 4 EXTI13_SS EXTI 13 sources selection 4 4 EXTI14_SS EXTI 14 sources selection 8 4 EXTI15_SS EXTI 15 sources selection 12 4 TIMER0 Advanced-timers TIMER 0x0 0x0 0x400 registers n TIMER0_BRK_TIMER8 24 TIMER0_UP_TIMER9 25 TIMER0_TRG_CMT_TIMER10 26 TIMER0_CC 27 CAR CAR Counter auto reload register 0x2C 32 read-write n 0x0 0x0 CAR Counter auto reload value 0 16 CCHP CCHP channel complementary protection register 0x44 32 read-write n 0x0 0x0 BRKEN Break enable 12 1 BRKP Break polarity 13 1 DTCFG Dead time configure 0 8 IOS Idle mode off-state configure 10 1 OAEN Output automatic enable 14 1 POEN Primary output enable 15 1 PROT Complementary register protect control 8 2 ROS Run mode off-state configure 11 1 CFG CFG Configuration register 0xFC 32 read-write n 0x0 0x0 CHVSEL Write CHxVAL register selection 1 1 OUTSEL The output value selection 0 1 CH0CV CH0CV Channel 0 capture/compare value register 0x34 32 read-write n 0x0 0x0 CH0VAL Capture or compare value of channel0 0 16 CH1CV CH1CV Channel 1 capture/compare value register 0x38 32 read-write n 0x0 0x0 CH1VAL Capture or compare value of channel1 0 16 CH2CV CH2CV Channel 2 capture/compare value register 0x3C 32 read-write n 0x0 0x0 CH2VAL Capture or compare value of channel 2 0 16 CH3CV CH3CV Channel 3 capture/compare value register 0x40 32 read-write n 0x0 0x0 CH3VAL Capture or compare value of channel 3 0 16 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 32 read-write n 0x0 0x0 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 32 read-write n 0x0 0x0 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0MS Channel 0 I/O mode selection 0 2 CH1COMCEN Channel 1 output compare clear enable 15 1 CH1COMCTL Channel 1 compare output control 12 3 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1MS Channel 1 mode selection 8 2 CHCTL1_Input CHCTL1_Input Channel control register 1 (input mode) CHCTL1_Output 0x1C 32 read-write n 0x0 0x0 CH2CAPFLT Channel 2 input capture filter control 4 4 CH2CAPPSC Channel 2 input capture prescaler 2 2 CH2MS Channel 2 mode selection 0 2 CH3CAPFLT Channel 3 input capture filter control 12 4 CH3CAPPSC Channel 3 input capture prescaler 10 2 CH3MS Channel 3 mode selection 8 2 CHCTL1_Output CHCTL1_Output Channel control register 1 (output mode) 0x1C 32 read-write n 0x0 0x0 CH2COMCEN Channel 2 output compare clear enable 7 1 CH2COMCTL Channel 2 compare output control 4 3 CH2COMFEN Channel 2 output compare fast enable 2 1 CH2COMSEN Channel 2 compare output shadow enable 3 1 CH2MS Channel 2 I/O mode selection 0 2 CH3COMCEN Channel 3 output compare clear enable 15 1 CH3COMCTL Channel 3 compare output control 12 3 CH3COMFEN Channel 3 output compare fast enable 10 1 CH3COMSEN Channel 3 output compare shadow enable 11 1 CH3MS Channel 3 mode selection 8 2 CHCTL2 CHCTL2 Channel control register 2 0x20 32 read-write n 0x0 0x0 CH0EN Channel 0 capture/compare function enable 0 1 CH0NEN Channel 0 complementary output enable 2 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare function polarity 1 1 CH1EN Channel 1 capture/compare function enable 4 1 CH1NEN Channel 1 complementary output enable 6 1 CH1NP Channel 1 complementary output polarity 7 1 CH1P Channel 1 capture/compare function polarity 5 1 CH2EN Channel 2 capture/compare function enable 8 1 CH2NEN Channel 2 complementary output enable 10 1 CH2NP Channel 2 complementary output polarity 11 1 CH2P Channel 2 capture/compare function polarity 9 1 CH3EN Channel 3 capture/compare function enable 12 1 CH3P Channel 3 capture/compare function polarity 13 1 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT current counter value 0 16 CREP CREP Counter repetition register 0x30 32 read-write n 0x0 0x0 CREP Counter repetition value 0 8 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 ARSE Auto-reload shadow enable 7 1 CAM Counter aligns mode selection 5 2 CEN Counter enable 0 1 CKDIV Clock division 8 2 DIR Direction 4 1 SPM Single pulse mode 3 1 UPDIS Update disable 1 1 UPS Update source 2 1 CTL1 CTL1 control register 1 0x4 32 read-write n 0x0 0x0 CCSE Commutation control shadow enable 0 1 CCUC Commutation control shadow register update control 2 1 DMAS DMA request source selection 3 1 ISO0 Idle state of channel 0 output 8 1 ISO0N Idle state of channel 0 complementary output 9 1 ISO1 Idle state of channel 1 output 10 1 ISO1N Idle state of channel 1 complementary output 11 1 ISO2 Idle state of channel 2 output 12 1 ISO2N Idle state of channel 2 complementary output 13 1 ISO3 Idle state of channel 3 output 14 1 MMC Master mode control 4 3 TI0S Channel 0 trigger input selection 7 1 DMACFG DMACFG DMA configuration register 0x48 32 read-write n 0x0 0x0 DMATA DMA transfer access start address 0 5 DMATC DMA transfer count 8 5 DMAINTEN DMAINTEN DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BRKIE Break interrupt enable 7 1 CH0DEN Channel 0 capture/compare DMA request enable 9 1 CH0IE Channel 0 capture/compare interrupt enable 1 1 CH1DEN Channel 1 capture/compare DMA request enable 10 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 CH2DEN Channel 2 capture/compare DMA request enable 11 1 CH2IE Channel 2 capture/compare interrupt enable 3 1 CH3DEN Channel 3 capture/compare DMA request enable 12 1 CH3IE Channel 3 capture/compare interrupt enable 4 1 CMTDEN Commutation DMA request enable 13 1 CMTIE commutation interrupt enable 5 1 TRGDEN Trigger DMA request enable 14 1 TRGIE Trigger interrupt enable 6 1 UPDEN Update DMA request enable 8 1 UPIE Update interrupt enable 0 1 DMATB DMATB DMA transfer buffer register 0x4C 32 read-write n 0x0 0x0 DMATB DMA transfer buffer 0 16 INTF INTF Interrupt flag register 0x10 32 read-write n 0x0 0x0 BRKIF Break interrupt flag 7 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 CH0OF Channel 0 over capture flag 9 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH1OF Channel 1 over capture flag 10 1 CH2IF Channel 2 capture/compare interrupt flag 3 1 CH2OF Channel 2 over capture flag 11 1 CH3IF Channel 3 capture/compare interrupt flag 4 1 CH3OF Channel 3 over capture flag 12 1 CMTIF Channel commutation interrupt flag 5 1 TRGIF Trigger interrupt flag 6 1 UPIF Update interrupt flag 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value of the counter clock 0 16 SMCFG SMCFG slave mode configuration register 0x8 32 read-write n 0x0 0x0 ETFC External trigger filter control 8 4 ETP External trigger polarity 15 1 ETPSC External trigger prescaler 12 2 MSM Master/Slave mode 7 1 SCM1 Part of SMC for enable External clock mode1 14 1 SMC Slave mode selection 0 3 TRGS Trigger selection 4 3 SWEVG SWEVG Software event generation register 0x14 32 write-only n 0x0 0x0 BRKG Break event generation 7 1 CH0G Channel 0 capture or compare event generation 1 1 CH1G Channel 1 capture or compare event generation 2 1 CH2G Channel 2 capture or compare event generation 3 1 CH3G Channel 3 capture or compare event generation 4 1 CMTG Channel commutation event generation 5 1 TRGG Trigger event generation 6 1 UPG Update event generation 0 1 TIMER1 General-purpose-timers TIMER 0x0 0x0 0x400 registers n TIMER1 28 CAR CAR Counter auto reload register 0x2C 32 read-write n 0x0 0x0 CARL Counter auto reload value 0 32 CFG CFG Configuration 0xFC 32 read-write n 0x0 0x0 CHVSEL Write CHxVAL register selection 1 1 CH0CV CH0CV Channel 0 capture/compare value register 0x34 32 read-write n 0x0 0x0 CH0VAL Capture or compare value of channel 0 0 32 CH1CV CH1CV Channel 1 capture/compare value register 0x38 32 read-write n 0x0 0x0 CH1VAL Capture or compare value of channel1 0 32 CH2CV CH2CV Channel 2 capture/compare value register 0x3C 32 read-write n 0x0 0x0 CH2VAL Capture or compare value of channel 2 0 32 CH3CV CH3CV Channel 3 capture/compare value register 0x40 32 read-write n 0x0 0x0 CH3VAL Capture or compare value of channel 3 0 32 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 32 read-write n 0x0 0x0 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 32 read-write n 0x0 0x0 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0MS Channel 0 I/O mode selection 0 2 CH1COMCEN Channel 1 output compare clear enable 15 1 CH1COMCTL Channel 1 compare output control 12 3 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1MS Channel 1 mode selection 8 2 CHCTL1_Input CHCTL1_Input Channel control register 1 (input mode) CHCTL1_Output 0x1C 32 read-write n 0x0 0x0 CH2CAPFLT Channel 2 input capture filter control 4 4 CH2CAPPSC Channel 2 input capture prescaler 2 2 CH2MS Channel 2 mode selection 0 2 CH3CAPFLT Channel 3 input capture filter control 12 4 CH3CAPPSC Channel 3 input capture prescaler 10 2 CH3MS Channel 3 mode selection 8 2 CHCTL1_Output CHCTL1_Output Channel control register 1 (output mode) 0x1C 32 read-write n 0x0 0x0 CH2COMCEN Channel 2 output compare clear enable 7 1 CH2COMCTL Channel 2 compare output control 4 3 CH2COMFEN Channel 2 output compare fast enable 2 1 CH2COMSEN Channel 2 compare output shadow enable 3 1 CH2MS Channel 2 I/O mode selection 0 2 CH3COMCEN Channel 3 output compare clear enable 15 1 CH3COMCTL Channel 3 compare output control 12 3 CH3COMFEN Channel 3 output compare fast enable 10 1 CH3COMSEN Channel 3 output compare shadow enable 11 1 CH3MS Channel 3 mode selection 8 2 CHCTL2 CHCTL2 Channel control register 2 0x20 32 read-write n 0x0 0x0 CH0EN Channel 0 capture/compare function enable 0 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare function polarity 1 1 CH1EN Channel 1 capture/compare function enable 4 1 CH1NP Channel 1 complementary output polarity 7 1 CH1P Channel 1 capture/compare function polarity 5 1 CH2EN Channel 2 capture/compare function enable 8 1 CH2NP Channel 2 complementary output polarity 11 1 CH2P Channel 2 capture/compare function polarity 9 1 CH3EN Channel 3 capture/compare function enable 12 1 CH3P Channel 3 capture/compare function polarity 13 1 CNT CNT Counter register 0x24 32 read-write n 0x0 0x0 CNT counter value 0 32 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 ARSE Auto-reload shadow enable 7 1 CAM Counter aligns mode selection 5 2 CEN Counter enable 0 1 CKDIV Clock division 8 2 DIR Direction 4 1 SPM Single pulse mode 3 1 UPDIS Update disable 1 1 UPS Update source 2 1 CTL1 CTL1 control register 1 0x4 32 read-write n 0x0 0x0 DMAS DMA request source selection 3 1 MMC Master mode control 4 3 TI0S Channel 0 trigger input selection 7 1 DMACFG DMACFG DMA configuration register 0x48 32 read-write n 0x0 0x0 DMATA DMA transfer access start address 0 5 DMATC DMA transfer count 8 5 DMAINTEN DMAINTEN DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 CH0DEN Channel 0 capture/compare DMA request enable 9 1 CH0IE Channel 0 capture/compare interrupt enable 1 1 CH1DEN Channel 1 capture/compare DMA request enable 10 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 CH2DEN Channel 2 capture/compare DMA request enable 11 1 CH2IE Channel 2 capture/compare interrupt enable 3 1 CH3DEN Channel 3 capture/compare DMA request enable 12 1 CH3IE Channel 3 capture/compare interrupt enable 4 1 TRGDEN Trigger DMA request enable 14 1 TRGIE Trigger interrupt enable 6 1 UPDEN Update DMA request enable 8 1 UPIE Update interrupt enable 0 1 DMATB DMATB DMA transfer buffer register 0x4C 32 read-write n 0x0 0x0 DMATB DMA transfer buffer 0 16 INTF INTF interrupt flag register 0x10 32 read-write n 0x0 0x0 CH0IF Channel 0 capture/compare interrupt flag 1 1 CH0OF Channel 0 over capture flag 9 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH1OF Channel 1 over capture flag 10 1 CH2IF Channel 2 capture/compare interrupt enable 3 1 CH2OF Channel 2 over capture flag 11 1 CH3IF Channel 3 capture/compare interrupt enable 4 1 CH3OF Channel 3 over capture flag 12 1 TRGIF Trigger interrupt flag 6 1 UPIF Update interrupt flag 0 1 IRMP IRMP Input remap register 0x50 32 read-write n 0x0 0x0 CI3_RMP Channel 3 input remap 6 2 ITI1_RMP Internal trigger input1 remap 10 2 PSC PSC Prescaler register 0x28 32 read-write n 0x0 0x0 PSC Prescaler value of the counter clock 0 16 SMCFG SMCFG slave mode control register 0x8 32 read-write n 0x0 0x0 ETFC External trigger filter control 8 4 ETP External trigger polarity 15 1 ETPSC External trigger prescaler 12 2 MSM Master-slave mode 7 1 SMC Slave mode control 0 3 SMC1 Part of SMC for enable External clock mode1 14 1 TRGS Trigger selection 4 3 SWEVG SWEVG event generation register 0x14 32 write-only n 0x0 0x0 CH0G Channel 0 capture or compare event generation 1 1 CH1G Channel 1 capture or compare event generation 2 1 CH2G Channel 2 capture or compare event generation 3 1 CH3G Channel 3 capture or compare event generation 4 1 TRGG Trigger event generation 6 1 UPG Update generation 0 1 TIMER10 General-purpose-timers TIMER 0x0 0x0 0x400 registers n TIMER0_TRG_CMT_TIMER10 26 CAR CAR Counter auto reload register 0x2C 32 read-write n 0x0 0x0 CARL Counter auto reload value 0 16 CFG CFG configuration register 0xFC 32 read-write n 0x0 0x0 CHVSEL Write CHxVAL register selection 1 1 CH0CV CH0CV Channel 0 capture/compare value register 0x34 32 read-write n 0x0 0x0 CH0VAL Capture or compare value of channel 0 0 16 CHCTL0_Input CHCTL0_Input Channel control register 0 ( (input mode) CHCTL0_Output 0x18 32 read-write n 0x0 0x0 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 32 read-write n 0x0 0x0 CH0COMCTL Channel 0 compare output control 4 3 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0MS Channel 0 I/O mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 32 read-write n 0x0 0x0 CH0EN Channel 0 capture/compare function enable 0 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare polarity 1 1 CNT CNT Counter register 0x24 32 read-write n 0x0 0x0 CNT current counter value 0 16 CTL0 CTL0 control register 1 0x0 32 read-write n 0x0 0x0 ARSE Auto-reload shadow enable 7 1 CEN Counter enable 0 1 CKDIV Clock division 8 2 UPDIS Update disable 1 1 UPS Update source 2 1 DMAINTEN DMAINTEN DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 32 read-write n 0x0 0x0 CH0IF Channel 0 capture/compare interrupt flag 1 1 CH0OF Channel 0 over capture flag 9 1 UPIF Update interrupt flag 0 1 IRMP IRMP channel input remap register 0x50 32 read-write n 0x0 0x0 ITI1_RMP Internal trigger input1 remap 10 2 PSC PSC Prescaler register 0x28 32 read-write n 0x0 0x0 PSC Prescaler value of the counter clock 0 16 SWEVG SWEVG event generation register 0x14 32 write-only n 0x0 0x0 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 TIMER11 General-purpose-timers TIMER 0x0 0x0 0x400 registers n TIMER7_BRK_TIMER11 43 CAR CAR Counter auto reload register 0x2C 32 read-write n 0x0 0x0 CARL Counter auto reload value 0 16 CFG CFG configuration register 0xFC 32 read-write n 0x0 0x0 CHVSEL Write CHxVAL register selection 1 1 CH0CV CH0CV Channel 0 capture/compare value register 0x34 32 read-write n 0x0 0x0 CH0VAL Capture or compare value of channel0 0 16 CH1CV CH1CV Channel 1 capture/compare value register 0x38 32 read-write n 0x0 0x0 CH1VAL Capture or compare value of channel1 0 16 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 32 read-write n 0x0 0x0 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 32 read-write n 0x0 0x0 CH0COMCTL Channel 0 compare output control 4 3 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0MS Channel 0 I/O mode selection 0 2 CH1COMCTL Channel 1 compare output control 12 3 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1MS Channel 1 mode selection 8 2 CHCTL2 CHCTL2 Channel control register 2 0x20 32 read-write n 0x0 0x0 CH0EN Channel 0 capture/compare function enable 0 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare function polarity 1 1 CH1EN Channel 1 capture/compare function enable 4 1 CH1NP Channel 1 complementary output polarity 7 1 CH1P Channel 1 capture/compare function polarity 5 1 CNT CNT Counter register 0x24 32 read-write n 0x0 0x0 CNT current counter value 0 16 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 ARSE Auto-reload shadow enable 7 1 CEN Counter enable 0 1 CKDIV Clock division 8 2 SPM Single pulse mode 3 1 UPDIS Update disable 1 1 UPS Update source 2 1 DMAINTEN DMAINTEN DMA and interrupt enable register 0xC 32 read-write n 0x0 0x0 CH0IE Channel 0 capture/compare interrupt enable 1 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 TRGIE Trigger interrupt enable 6 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 32 read-write n 0x0 0x0 CH0IF Channel 0 capture/compare interrupt flag 1 1 CH0OF Channel 0 over capture flag 9 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH1OF Channel 1 over capture flag 10 1 TRGIF Trigger interrupt flag 6 1 UPIF Update interrupt flag 0 1 PSC PSC Prescaler register 0x28 32 read-write n 0x0 0x0 PSC Prescaler value of the counter clock 0 16 SMCFG SMCFG slave mode configuration register 0x8 32 read-write n 0x0 0x0 MSM Master-slave mode 7 1 SMC Slave mode control 0 3 TRGS Trigger selection 4 3 SWEVG SWEVG event generation register 0x14 32 write-only n 0x0 0x0 CH0G Channel 0 capture or compare event generation 1 1 CH1G Channel 1 capture or compare event generation 2 1 TRGG Trigger event generation 6 1 UPG Update generation 0 1 TIMER12 General-purpose-timers TIMER 0x0 0x0 0x400 registers n TIMER7_UP_TIMER12 44 CAR CAR Counter auto reload register 0x2C 32 read-write n 0x0 0x0 CARL Counter auto reload value 0 16 CFG CFG configuration register 0xFC 32 read-write n 0x0 0x0 CHVSEL Write CHxVAL register selection 1 1 CH0CV CH0CV Channel 0 capture/compare value register 0x34 32 read-write n 0x0 0x0 CH0VAL Capture or compare value of channel 0 0 16 CHCTL0_Input CHCTL0_Input Channel control register 0 ( (input mode) CHCTL0_Output 0x18 32 read-write n 0x0 0x0 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 32 read-write n 0x0 0x0 CH0COMCTL Channel 0 compare output control 4 3 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0MS Channel 0 I/O mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 32 read-write n 0x0 0x0 CH0EN Channel 0 capture/compare function enable 0 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare polarity 1 1 CNT CNT Counter register 0x24 32 read-write n 0x0 0x0 CNT current counter value 0 16 CTL0 CTL0 control register 1 0x0 32 read-write n 0x0 0x0 ARSE Auto-reload shadow enable 7 1 CEN Counter enable 0 1 CKDIV Clock division 8 2 UPDIS Update disable 1 1 UPS Update source 2 1 DMAINTEN DMAINTEN DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 32 read-write n 0x0 0x0 CH0IF Channel 0 capture/compare interrupt flag 1 1 CH0OF Channel 0 over capture flag 9 1 UPIF Update interrupt flag 0 1 IRMP IRMP channel input remap register 0x50 32 read-write n 0x0 0x0 ITI1_RMP Internal trigger input1 remap 10 2 PSC PSC Prescaler register 0x28 32 read-write n 0x0 0x0 PSC Prescaler value of the counter clock 0 16 SWEVG SWEVG event generation register 0x14 32 write-only n 0x0 0x0 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 TIMER13 General-purpose-timers TIMER 0x0 0x0 0x400 registers n TIMER7_TRG_CMT_TIMER13 45 CAR CAR Counter auto reload register 0x2C 32 read-write n 0x0 0x0 CARL Counter auto reload value 0 16 CFG CFG configuration register 0xFC 32 read-write n 0x0 0x0 CHVSEL Write CHxVAL register selection 1 1 CH0CV CH0CV Channel 0 capture/compare value register 0x34 32 read-write n 0x0 0x0 CH0VAL Capture or compare value of channel 0 0 16 CHCTL0_Input CHCTL0_Input Channel control register 0 ( (input mode) CHCTL0_Output 0x18 32 read-write n 0x0 0x0 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 32 read-write n 0x0 0x0 CH0COMCTL Channel 0 compare output control 4 3 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0MS Channel 0 I/O mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 32 read-write n 0x0 0x0 CH0EN Channel 0 capture/compare function enable 0 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare polarity 1 1 CNT CNT Counter register 0x24 32 read-write n 0x0 0x0 CNT current counter value 0 16 CTL0 CTL0 control register 1 0x0 32 read-write n 0x0 0x0 ARSE Auto-reload shadow enable 7 1 CEN Counter enable 0 1 CKDIV Clock division 8 2 UPDIS Update disable 1 1 UPS Update source 2 1 DMAINTEN DMAINTEN DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 32 read-write n 0x0 0x0 CH0IF Channel 0 capture/compare interrupt flag 1 1 CH0OF Channel 0 over capture flag 9 1 UPIF Update interrupt flag 0 1 IRMP IRMP channel input remap register 0x50 32 read-write n 0x0 0x0 ITI1_RMP Internal trigger input1 remap 10 2 PSC PSC Prescaler register 0x28 32 read-write n 0x0 0x0 PSC Prescaler value of the counter clock 0 16 SWEVG SWEVG event generation register 0x14 32 write-only n 0x0 0x0 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 TIMER2 General-purpose-timers TIMER 0x0 0x0 0x400 registers n TIMER2 29 CAR CAR Counter auto reload register 0x2C 32 read-write n 0x0 0x0 CARL Counter auto reload value 0 32 CFG CFG Configuration 0xFC 32 read-write n 0x0 0x0 CHVSEL Write CHxVAL register selection 1 1 CH0CV CH0CV Channel 0 capture/compare value register 0x34 32 read-write n 0x0 0x0 CH0VAL Capture or compare value of channel 0 0 32 CH1CV CH1CV Channel 1 capture/compare value register 0x38 32 read-write n 0x0 0x0 CH1VAL Capture or compare value of channel1 0 32 CH2CV CH2CV Channel 2 capture/compare value register 0x3C 32 read-write n 0x0 0x0 CH2VAL Capture or compare value of channel 2 0 32 CH3CV CH3CV Channel 3 capture/compare value register 0x40 32 read-write n 0x0 0x0 CH3VAL Capture or compare value of channel 3 0 32 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 32 read-write n 0x0 0x0 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 32 read-write n 0x0 0x0 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0MS Channel 0 I/O mode selection 0 2 CH1COMCEN Channel 1 output compare clear enable 15 1 CH1COMCTL Channel 1 compare output control 12 3 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1MS Channel 1 mode selection 8 2 CHCTL1_Input CHCTL1_Input Channel control register 1 (input mode) CHCTL1_Output 0x1C 32 read-write n 0x0 0x0 CH2CAPFLT Channel 2 input capture filter control 4 4 CH2CAPPSC Channel 2 input capture prescaler 2 2 CH2MS Channel 2 mode selection 0 2 CH3CAPFLT Channel 3 input capture filter control 12 4 CH3CAPPSC Channel 3 input capture prescaler 10 2 CH3MS Channel 3 mode selection 8 2 CHCTL1_Output CHCTL1_Output Channel control register 1 (output mode) 0x1C 32 read-write n 0x0 0x0 CH2COMCEN Channel 2 output compare clear enable 7 1 CH2COMCTL Channel 2 compare output control 4 3 CH2COMFEN Channel 2 output compare fast enable 2 1 CH2COMSEN Channel 2 compare output shadow enable 3 1 CH2MS Channel 2 I/O mode selection 0 2 CH3COMCEN Channel 3 output compare clear enable 15 1 CH3COMCTL Channel 3 compare output control 12 3 CH3COMFEN Channel 3 output compare fast enable 10 1 CH3COMSEN Channel 3 output compare shadow enable 11 1 CH3MS Channel 3 mode selection 8 2 CHCTL2 CHCTL2 Channel control register 2 0x20 32 read-write n 0x0 0x0 CH0EN Channel 0 capture/compare function enable 0 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare function polarity 1 1 CH1EN Channel 1 capture/compare function enable 4 1 CH1NP Channel 1 complementary output polarity 7 1 CH1P Channel 1 capture/compare function polarity 5 1 CH2EN Channel 2 capture/compare function enable 8 1 CH2NP Channel 2 complementary output polarity 11 1 CH2P Channel 2 capture/compare function polarity 9 1 CH3EN Channel 3 capture/compare function enable 12 1 CH3P Channel 3 capture/compare function polarity 13 1 CNT CNT Counter register 0x24 32 read-write n 0x0 0x0 CNT counter value 0 32 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 ARSE Auto-reload shadow enable 7 1 CAM Counter aligns mode selection 5 2 CEN Counter enable 0 1 CKDIV Clock division 8 2 DIR Direction 4 1 SPM Single pulse mode 3 1 UPDIS Update disable 1 1 UPS Update source 2 1 CTL1 CTL1 control register 1 0x4 32 read-write n 0x0 0x0 DMAS DMA request source selection 3 1 MMC Master mode control 4 3 TI0S Channel 0 trigger input selection 7 1 DMACFG DMACFG DMA configuration register 0x48 32 read-write n 0x0 0x0 DMATA DMA transfer access start address 0 5 DMATC DMA transfer count 8 5 DMAINTEN DMAINTEN DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 CH0DEN Channel 0 capture/compare DMA request enable 9 1 CH0IE Channel 0 capture/compare interrupt enable 1 1 CH1DEN Channel 1 capture/compare DMA request enable 10 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 CH2DEN Channel 2 capture/compare DMA request enable 11 1 CH2IE Channel 2 capture/compare interrupt enable 3 1 CH3DEN Channel 3 capture/compare DMA request enable 12 1 CH3IE Channel 3 capture/compare interrupt enable 4 1 TRGDEN Trigger DMA request enable 14 1 TRGIE Trigger interrupt enable 6 1 UPDEN Update DMA request enable 8 1 UPIE Update interrupt enable 0 1 DMATB DMATB DMA transfer buffer register 0x4C 32 read-write n 0x0 0x0 DMATB DMA transfer buffer 0 16 INTF INTF interrupt flag register 0x10 32 read-write n 0x0 0x0 CH0IF Channel 0 capture/compare interrupt flag 1 1 CH0OF Channel 0 over capture flag 9 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH1OF Channel 1 over capture flag 10 1 CH2IF Channel 2 capture/compare interrupt enable 3 1 CH2OF Channel 2 over capture flag 11 1 CH3IF Channel 3 capture/compare interrupt enable 4 1 CH3OF Channel 3 over capture flag 12 1 TRGIF Trigger interrupt flag 6 1 UPIF Update interrupt flag 0 1 IRMP IRMP Input remap register 0x50 32 read-write n 0x0 0x0 CI3_RMP Channel 3 input remap 6 2 ITI1_RMP Internal trigger input1 remap 10 2 PSC PSC Prescaler register 0x28 32 read-write n 0x0 0x0 PSC Prescaler value of the counter clock 0 16 SMCFG SMCFG slave mode control register 0x8 32 read-write n 0x0 0x0 ETFC External trigger filter control 8 4 ETP External trigger polarity 15 1 ETPSC External trigger prescaler 12 2 MSM Master-slave mode 7 1 SMC Slave mode control 0 3 SMC1 Part of SMC for enable External clock mode1 14 1 TRGS Trigger selection 4 3 SWEVG SWEVG event generation register 0x14 32 write-only n 0x0 0x0 CH0G Channel 0 capture or compare event generation 1 1 CH1G Channel 1 capture or compare event generation 2 1 CH2G Channel 2 capture or compare event generation 3 1 CH3G Channel 3 capture or compare event generation 4 1 TRGG Trigger event generation 6 1 UPG Update generation 0 1 TIMER3 General-purpose-timers TIMER 0x0 0x0 0x400 registers n TIMER3 30 CAR CAR Counter auto reload register 0x2C 32 read-write n 0x0 0x0 CARL Counter auto reload value 0 32 CFG CFG Configuration 0xFC 32 read-write n 0x0 0x0 CHVSEL Write CHxVAL register selection 1 1 CH0CV CH0CV Channel 0 capture/compare value register 0x34 32 read-write n 0x0 0x0 CH0VAL Capture or compare value of channel 0 0 32 CH1CV CH1CV Channel 1 capture/compare value register 0x38 32 read-write n 0x0 0x0 CH1VAL Capture or compare value of channel1 0 32 CH2CV CH2CV Channel 2 capture/compare value register 0x3C 32 read-write n 0x0 0x0 CH2VAL Capture or compare value of channel 2 0 32 CH3CV CH3CV Channel 3 capture/compare value register 0x40 32 read-write n 0x0 0x0 CH3VAL Capture or compare value of channel 3 0 32 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 32 read-write n 0x0 0x0 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 32 read-write n 0x0 0x0 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0MS Channel 0 I/O mode selection 0 2 CH1COMCEN Channel 1 output compare clear enable 15 1 CH1COMCTL Channel 1 compare output control 12 3 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1MS Channel 1 mode selection 8 2 CHCTL1_Input CHCTL1_Input Channel control register 1 (input mode) CHCTL1_Output 0x1C 32 read-write n 0x0 0x0 CH2CAPFLT Channel 2 input capture filter control 4 4 CH2CAPPSC Channel 2 input capture prescaler 2 2 CH2MS Channel 2 mode selection 0 2 CH3CAPFLT Channel 3 input capture filter control 12 4 CH3CAPPSC Channel 3 input capture prescaler 10 2 CH3MS Channel 3 mode selection 8 2 CHCTL1_Output CHCTL1_Output Channel control register 1 (output mode) 0x1C 32 read-write n 0x0 0x0 CH2COMCEN Channel 2 output compare clear enable 7 1 CH2COMCTL Channel 2 compare output control 4 3 CH2COMFEN Channel 2 output compare fast enable 2 1 CH2COMSEN Channel 2 compare output shadow enable 3 1 CH2MS Channel 2 I/O mode selection 0 2 CH3COMCEN Channel 3 output compare clear enable 15 1 CH3COMCTL Channel 3 compare output control 12 3 CH3COMFEN Channel 3 output compare fast enable 10 1 CH3COMSEN Channel 3 output compare shadow enable 11 1 CH3MS Channel 3 mode selection 8 2 CHCTL2 CHCTL2 Channel control register 2 0x20 32 read-write n 0x0 0x0 CH0EN Channel 0 capture/compare function enable 0 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare function polarity 1 1 CH1EN Channel 1 capture/compare function enable 4 1 CH1NP Channel 1 complementary output polarity 7 1 CH1P Channel 1 capture/compare function polarity 5 1 CH2EN Channel 2 capture/compare function enable 8 1 CH2NP Channel 2 complementary output polarity 11 1 CH2P Channel 2 capture/compare function polarity 9 1 CH3EN Channel 3 capture/compare function enable 12 1 CH3P Channel 3 capture/compare function polarity 13 1 CNT CNT Counter register 0x24 32 read-write n 0x0 0x0 CNT counter value 0 32 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 ARSE Auto-reload shadow enable 7 1 CAM Counter aligns mode selection 5 2 CEN Counter enable 0 1 CKDIV Clock division 8 2 DIR Direction 4 1 SPM Single pulse mode 3 1 UPDIS Update disable 1 1 UPS Update source 2 1 CTL1 CTL1 control register 1 0x4 32 read-write n 0x0 0x0 DMAS DMA request source selection 3 1 MMC Master mode control 4 3 TI0S Channel 0 trigger input selection 7 1 DMACFG DMACFG DMA configuration register 0x48 32 read-write n 0x0 0x0 DMATA DMA transfer access start address 0 5 DMATC DMA transfer count 8 5 DMAINTEN DMAINTEN DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 CH0DEN Channel 0 capture/compare DMA request enable 9 1 CH0IE Channel 0 capture/compare interrupt enable 1 1 CH1DEN Channel 1 capture/compare DMA request enable 10 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 CH2DEN Channel 2 capture/compare DMA request enable 11 1 CH2IE Channel 2 capture/compare interrupt enable 3 1 CH3DEN Channel 3 capture/compare DMA request enable 12 1 CH3IE Channel 3 capture/compare interrupt enable 4 1 TRGDEN Trigger DMA request enable 14 1 TRGIE Trigger interrupt enable 6 1 UPDEN Update DMA request enable 8 1 UPIE Update interrupt enable 0 1 DMATB DMATB DMA transfer buffer register 0x4C 32 read-write n 0x0 0x0 DMATB DMA transfer buffer 0 16 INTF INTF interrupt flag register 0x10 32 read-write n 0x0 0x0 CH0IF Channel 0 capture/compare interrupt flag 1 1 CH0OF Channel 0 over capture flag 9 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH1OF Channel 1 over capture flag 10 1 CH2IF Channel 2 capture/compare interrupt enable 3 1 CH2OF Channel 2 over capture flag 11 1 CH3IF Channel 3 capture/compare interrupt enable 4 1 CH3OF Channel 3 over capture flag 12 1 TRGIF Trigger interrupt flag 6 1 UPIF Update interrupt flag 0 1 IRMP IRMP Input remap register 0x50 32 read-write n 0x0 0x0 CI3_RMP Channel 3 input remap 6 2 ITI1_RMP Internal trigger input1 remap 10 2 PSC PSC Prescaler register 0x28 32 read-write n 0x0 0x0 PSC Prescaler value of the counter clock 0 16 SMCFG SMCFG slave mode control register 0x8 32 read-write n 0x0 0x0 ETFC External trigger filter control 8 4 ETP External trigger polarity 15 1 ETPSC External trigger prescaler 12 2 MSM Master-slave mode 7 1 SMC Slave mode control 0 3 SMC1 Part of SMC for enable External clock mode1 14 1 TRGS Trigger selection 4 3 SWEVG SWEVG event generation register 0x14 32 write-only n 0x0 0x0 CH0G Channel 0 capture or compare event generation 1 1 CH1G Channel 1 capture or compare event generation 2 1 CH2G Channel 2 capture or compare event generation 3 1 CH3G Channel 3 capture or compare event generation 4 1 TRGG Trigger event generation 6 1 UPG Update generation 0 1 TIMER4 General-purpose-timers TIMER 0x0 0x0 0x400 registers n TIMER4 50 CAR CAR Counter auto reload register 0x2C 32 read-write n 0x0 0x0 CARL Counter auto reload value 0 32 CFG CFG Configuration 0xFC 32 read-write n 0x0 0x0 CHVSEL Write CHxVAL register selection 1 1 CH0CV CH0CV Channel 0 capture/compare value register 0x34 32 read-write n 0x0 0x0 CH0VAL Capture or compare value of channel 0 0 32 CH1CV CH1CV Channel 1 capture/compare value register 0x38 32 read-write n 0x0 0x0 CH1VAL Capture or compare value of channel1 0 32 CH2CV CH2CV Channel 2 capture/compare value register 0x3C 32 read-write n 0x0 0x0 CH2VAL Capture or compare value of channel 2 0 32 CH3CV CH3CV Channel 3 capture/compare value register 0x40 32 read-write n 0x0 0x0 CH3VAL Capture or compare value of channel 3 0 32 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 32 read-write n 0x0 0x0 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 32 read-write n 0x0 0x0 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0MS Channel 0 I/O mode selection 0 2 CH1COMCEN Channel 1 output compare clear enable 15 1 CH1COMCTL Channel 1 compare output control 12 3 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1MS Channel 1 mode selection 8 2 CHCTL1_Input CHCTL1_Input Channel control register 1 (input mode) CHCTL1_Output 0x1C 32 read-write n 0x0 0x0 CH2CAPFLT Channel 2 input capture filter control 4 4 CH2CAPPSC Channel 2 input capture prescaler 2 2 CH2MS Channel 2 mode selection 0 2 CH3CAPFLT Channel 3 input capture filter control 12 4 CH3CAPPSC Channel 3 input capture prescaler 10 2 CH3MS Channel 3 mode selection 8 2 CHCTL1_Output CHCTL1_Output Channel control register 1 (output mode) 0x1C 32 read-write n 0x0 0x0 CH2COMCEN Channel 2 output compare clear enable 7 1 CH2COMCTL Channel 2 compare output control 4 3 CH2COMFEN Channel 2 output compare fast enable 2 1 CH2COMSEN Channel 2 compare output shadow enable 3 1 CH2MS Channel 2 I/O mode selection 0 2 CH3COMCEN Channel 3 output compare clear enable 15 1 CH3COMCTL Channel 3 compare output control 12 3 CH3COMFEN Channel 3 output compare fast enable 10 1 CH3COMSEN Channel 3 output compare shadow enable 11 1 CH3MS Channel 3 mode selection 8 2 CHCTL2 CHCTL2 Channel control register 2 0x20 32 read-write n 0x0 0x0 CH0EN Channel 0 capture/compare function enable 0 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare function polarity 1 1 CH1EN Channel 1 capture/compare function enable 4 1 CH1NP Channel 1 complementary output polarity 7 1 CH1P Channel 1 capture/compare function polarity 5 1 CH2EN Channel 2 capture/compare function enable 8 1 CH2NP Channel 2 complementary output polarity 11 1 CH2P Channel 2 capture/compare function polarity 9 1 CH3EN Channel 3 capture/compare function enable 12 1 CH3P Channel 3 capture/compare function polarity 13 1 CNT CNT Counter register 0x24 32 read-write n 0x0 0x0 CNT counter value 0 32 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 ARSE Auto-reload shadow enable 7 1 CAM Counter aligns mode selection 5 2 CEN Counter enable 0 1 CKDIV Clock division 8 2 DIR Direction 4 1 SPM Single pulse mode 3 1 UPDIS Update disable 1 1 UPS Update source 2 1 CTL1 CTL1 control register 1 0x4 32 read-write n 0x0 0x0 DMAS DMA request source selection 3 1 MMC Master mode control 4 3 TI0S Channel 0 trigger input selection 7 1 DMACFG DMACFG DMA configuration register 0x48 32 read-write n 0x0 0x0 DMATA DMA transfer access start address 0 5 DMATC DMA transfer count 8 5 DMAINTEN DMAINTEN DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 CH0DEN Channel 0 capture/compare DMA request enable 9 1 CH0IE Channel 0 capture/compare interrupt enable 1 1 CH1DEN Channel 1 capture/compare DMA request enable 10 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 CH2DEN Channel 2 capture/compare DMA request enable 11 1 CH2IE Channel 2 capture/compare interrupt enable 3 1 CH3DEN Channel 3 capture/compare DMA request enable 12 1 CH3IE Channel 3 capture/compare interrupt enable 4 1 TRGDEN Trigger DMA request enable 14 1 TRGIE Trigger interrupt enable 6 1 UPDEN Update DMA request enable 8 1 UPIE Update interrupt enable 0 1 DMATB DMATB DMA transfer buffer register 0x4C 32 read-write n 0x0 0x0 DMATB DMA transfer buffer 0 16 INTF INTF interrupt flag register 0x10 32 read-write n 0x0 0x0 CH0IF Channel 0 capture/compare interrupt flag 1 1 CH0OF Channel 0 over capture flag 9 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH1OF Channel 1 over capture flag 10 1 CH2IF Channel 2 capture/compare interrupt enable 3 1 CH2OF Channel 2 over capture flag 11 1 CH3IF Channel 3 capture/compare interrupt enable 4 1 CH3OF Channel 3 over capture flag 12 1 TRGIF Trigger interrupt flag 6 1 UPIF Update interrupt flag 0 1 IRMP IRMP Input remap register 0x50 32 read-write n 0x0 0x0 CI3_RMP Channel 3 input remap 6 2 ITI1_RMP Internal trigger input1 remap 10 2 PSC PSC Prescaler register 0x28 32 read-write n 0x0 0x0 PSC Prescaler value of the counter clock 0 16 SMCFG SMCFG slave mode control register 0x8 32 read-write n 0x0 0x0 ETFC External trigger filter control 8 4 ETP External trigger polarity 15 1 ETPSC External trigger prescaler 12 2 MSM Master-slave mode 7 1 SMC Slave mode control 0 3 SMC1 Part of SMC for enable External clock mode1 14 1 TRGS Trigger selection 4 3 SWEVG SWEVG event generation register 0x14 32 write-only n 0x0 0x0 CH0G Channel 0 capture or compare event generation 1 1 CH1G Channel 1 capture or compare event generation 2 1 CH2G Channel 2 capture or compare event generation 3 1 CH3G Channel 3 capture or compare event generation 4 1 TRGG Trigger event generation 6 1 UPG Update generation 0 1 TIMER5 Basic-timers TIMER 0x0 0x0 0x400 registers n TIMER5_DAC 54 CAR CAR Counter auto reload register 0x2C 32 read-write n 0x0 0x0 CAR Counter auto reload value 0 16 CNT CNT Counter register 0x24 32 read-write n 0x0 0x0 CNT Low counter value 0 16 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 ARSE Auto-reload shadow enable 7 1 CEN Counter enable 0 1 SPM Single pulse mode 3 1 UPDIS Update disable 1 1 UPS Update source 2 1 CTL1 CTL1 control register 1 0x4 32 read-write n 0x0 0x0 MMC Master mode control 4 3 DMAINTEN DMAINTEN DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 UPDEN Update DMA request enable 8 1 UPIE Update interrupt enable 0 1 INTF INTF Interrupt flag register 0x10 32 read-write n 0x0 0x0 UPIF Update interrupt flag 0 1 PSC PSC Prescaler register 0x28 32 read-write n 0x0 0x0 PSC Prescaler value of the counter clock 0 16 SWEVG SWEVG event generation register 0x14 32 write-only n 0x0 0x0 UPG Update generation 0 1 TIMER6 Basic-timers TIMER 0x0 0x0 0x400 registers n TIMER6 55 CAR CAR Counter auto reload register 0x2C 32 read-write n 0x0 0x0 CAR Counter auto reload value 0 16 CNT CNT Counter register 0x24 32 read-write n 0x0 0x0 CNT Low counter value 0 16 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 ARSE Auto-reload shadow enable 7 1 CEN Counter enable 0 1 SPM Single pulse mode 3 1 UPDIS Update disable 1 1 UPS Update source 2 1 CTL1 CTL1 control register 1 0x4 32 read-write n 0x0 0x0 MMC Master mode control 4 3 DMAINTEN DMAINTEN DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 UPDEN Update DMA request enable 8 1 UPIE Update interrupt enable 0 1 INTF INTF Interrupt flag register 0x10 32 read-write n 0x0 0x0 UPIF Update interrupt flag 0 1 PSC PSC Prescaler register 0x28 32 read-write n 0x0 0x0 PSC Prescaler value of the counter clock 0 16 SWEVG SWEVG event generation register 0x14 32 write-only n 0x0 0x0 UPG Update generation 0 1 TIMER7 Advanced-timers TIMER 0x0 0x0 0x400 registers n TIMER7_BRK_TIMER11 43 TIMER7_UP_TIMER12 44 TIMER7_TRG_CMT_TIMER13 45 TIMER7_CC 46 CAR CAR Counter auto reload register 0x2C 32 read-write n 0x0 0x0 CAR Counter auto reload value 0 16 CCHP CCHP channel complementary protection register 0x44 32 read-write n 0x0 0x0 BRKEN Break enable 12 1 BRKP Break polarity 13 1 DTCFG Dead time configure 0 8 IOS Idle mode off-state configure 10 1 OAEN Output automatic enable 14 1 POEN Primary output enable 15 1 PROT Complementary register protect control 8 2 ROS Run mode off-state configure 11 1 CFG CFG Configuration register 0xFC 32 read-write n 0x0 0x0 CHVSEL Write CHxVAL register selection 1 1 OUTSEL The output value selection 0 1 CH0CV CH0CV Channel 0 capture/compare value register 0x34 32 read-write n 0x0 0x0 CH0VAL Capture or compare value of channel0 0 16 CH1CV CH1CV Channel 1 capture/compare value register 0x38 32 read-write n 0x0 0x0 CH1VAL Capture or compare value of channel1 0 16 CH2CV CH2CV Channel 2 capture/compare value register 0x3C 32 read-write n 0x0 0x0 CH2VAL Capture or compare value of channel 2 0 16 CH3CV CH3CV Channel 3 capture/compare value register 0x40 32 read-write n 0x0 0x0 CH3VAL Capture or compare value of channel 3 0 16 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 32 read-write n 0x0 0x0 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 32 read-write n 0x0 0x0 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0MS Channel 0 I/O mode selection 0 2 CH1COMCEN Channel 1 output compare clear enable 15 1 CH1COMCTL Channel 1 compare output control 12 3 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1MS Channel 1 mode selection 8 2 CHCTL1_Input CHCTL1_Input Channel control register 1 (input mode) CHCTL1_Output 0x1C 32 read-write n 0x0 0x0 CH2CAPFLT Channel 2 input capture filter control 4 4 CH2CAPPSC Channel 2 input capture prescaler 2 2 CH2MS Channel 2 mode selection 0 2 CH3CAPFLT Channel 3 input capture filter control 12 4 CH3CAPPSC Channel 3 input capture prescaler 10 2 CH3MS Channel 3 mode selection 8 2 CHCTL1_Output CHCTL1_Output Channel control register 1 (output mode) 0x1C 32 read-write n 0x0 0x0 CH2COMCEN Channel 2 output compare clear enable 7 1 CH2COMCTL Channel 2 compare output control 4 3 CH2COMFEN Channel 2 output compare fast enable 2 1 CH2COMSEN Channel 2 compare output shadow enable 3 1 CH2MS Channel 2 I/O mode selection 0 2 CH3COMCEN Channel 3 output compare clear enable 15 1 CH3COMCTL Channel 3 compare output control 12 3 CH3COMFEN Channel 3 output compare fast enable 10 1 CH3COMSEN Channel 3 output compare shadow enable 11 1 CH3MS Channel 3 mode selection 8 2 CHCTL2 CHCTL2 Channel control register 2 0x20 32 read-write n 0x0 0x0 CH0EN Channel 0 capture/compare function enable 0 1 CH0NEN Channel 0 complementary output enable 2 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare function polarity 1 1 CH1EN Channel 1 capture/compare function enable 4 1 CH1NEN Channel 1 complementary output enable 6 1 CH1NP Channel 1 complementary output polarity 7 1 CH1P Channel 1 capture/compare function polarity 5 1 CH2EN Channel 2 capture/compare function enable 8 1 CH2NEN Channel 2 complementary output enable 10 1 CH2NP Channel 2 complementary output polarity 11 1 CH2P Channel 2 capture/compare function polarity 9 1 CH3EN Channel 3 capture/compare function enable 12 1 CH3P Channel 3 capture/compare function polarity 13 1 CNT CNT counter 0x24 32 read-write n 0x0 0x0 CNT current counter value 0 16 CREP CREP Counter repetition register 0x30 32 read-write n 0x0 0x0 CREP Counter repetition value 0 8 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 ARSE Auto-reload shadow enable 7 1 CAM Counter aligns mode selection 5 2 CEN Counter enable 0 1 CKDIV Clock division 8 2 DIR Direction 4 1 SPM Single pulse mode 3 1 UPDIS Update disable 1 1 UPS Update source 2 1 CTL1 CTL1 control register 1 0x4 32 read-write n 0x0 0x0 CCSE Commutation control shadow enable 0 1 CCUC Commutation control shadow register update control 2 1 DMAS DMA request source selection 3 1 ISO0 Idle state of channel 0 output 8 1 ISO0N Idle state of channel 0 complementary output 9 1 ISO1 Idle state of channel 1 output 10 1 ISO1N Idle state of channel 1 complementary output 11 1 ISO2 Idle state of channel 2 output 12 1 ISO2N Idle state of channel 2 complementary output 13 1 ISO3 Idle state of channel 3 output 14 1 MMC Master mode control 4 3 TI0S Channel 0 trigger input selection 7 1 DMACFG DMACFG DMA configuration register 0x48 32 read-write n 0x0 0x0 DMATA DMA transfer access start address 0 5 DMATC DMA transfer count 8 5 DMAINTEN DMAINTEN DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 BRKIE Break interrupt enable 7 1 CH0DEN Channel 0 capture/compare DMA request enable 9 1 CH0IE Channel 0 capture/compare interrupt enable 1 1 CH1DEN Channel 1 capture/compare DMA request enable 10 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 CH2DEN Channel 2 capture/compare DMA request enable 11 1 CH2IE Channel 2 capture/compare interrupt enable 3 1 CH3DEN Channel 3 capture/compare DMA request enable 12 1 CH3IE Channel 3 capture/compare interrupt enable 4 1 CMTDEN Commutation DMA request enable 13 1 CMTIE commutation interrupt enable 5 1 TRGDEN Trigger DMA request enable 14 1 TRGIE Trigger interrupt enable 6 1 UPDEN Update DMA request enable 8 1 UPIE Update interrupt enable 0 1 DMATB DMATB DMA transfer buffer register 0x4C 32 read-write n 0x0 0x0 DMATB DMA transfer buffer 0 16 INTF INTF Interrupt flag register 0x10 32 read-write n 0x0 0x0 BRKIF Break interrupt flag 7 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 CH0OF Channel 0 over capture flag 9 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH1OF Channel 1 over capture flag 10 1 CH2IF Channel 2 capture/compare interrupt flag 3 1 CH2OF Channel 2 over capture flag 11 1 CH3IF Channel 3 capture/compare interrupt flag 4 1 CH3OF Channel 3 over capture flag 12 1 CMTIF Channel commutation interrupt flag 5 1 TRGIF Trigger interrupt flag 6 1 UPIF Update interrupt flag 0 1 PSC PSC prescaler 0x28 32 read-write n 0x0 0x0 PSC Prescaler value of the counter clock 0 16 SMCFG SMCFG slave mode configuration register 0x8 32 read-write n 0x0 0x0 ETFC External trigger filter control 8 4 ETP External trigger polarity 15 1 ETPSC External trigger prescaler 12 2 MSM Master/Slave mode 7 1 SCM1 Part of SMC for enable External clock mode1 14 1 SMC Slave mode selection 0 3 TRGS Trigger selection 4 3 SWEVG SWEVG Software event generation register 0x14 32 write-only n 0x0 0x0 BRKG Break event generation 7 1 CH0G Channel 0 capture or compare event generation 1 1 CH1G Channel 1 capture or compare event generation 2 1 CH2G Channel 2 capture or compare event generation 3 1 CH3G Channel 3 capture or compare event generation 4 1 CMTG Channel commutation event generation 5 1 TRGG Trigger event generation 6 1 UPG Update event generation 0 1 TIMER8 General-purpose-timers TIMER 0x0 0x0 0x400 registers n TIMER0_BRK_TIMER8 24 CAR CAR Counter auto reload register 0x2C 32 read-write n 0x0 0x0 CARL Counter auto reload value 0 16 CFG CFG configuration register 0xFC 32 read-write n 0x0 0x0 CHVSEL Write CHxVAL register selection 1 1 CH0CV CH0CV Channel 0 capture/compare value register 0x34 32 read-write n 0x0 0x0 CH0VAL Capture or compare value of channel0 0 16 CH1CV CH1CV Channel 1 capture/compare value register 0x38 32 read-write n 0x0 0x0 CH1VAL Capture or compare value of channel1 0 16 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 32 read-write n 0x0 0x0 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 32 read-write n 0x0 0x0 CH0COMCTL Channel 0 compare output control 4 3 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0MS Channel 0 I/O mode selection 0 2 CH1COMCTL Channel 1 compare output control 12 3 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1MS Channel 1 mode selection 8 2 CHCTL2 CHCTL2 Channel control register 2 0x20 32 read-write n 0x0 0x0 CH0EN Channel 0 capture/compare function enable 0 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare function polarity 1 1 CH1EN Channel 1 capture/compare function enable 4 1 CH1NP Channel 1 complementary output polarity 7 1 CH1P Channel 1 capture/compare function polarity 5 1 CNT CNT Counter register 0x24 32 read-write n 0x0 0x0 CNT current counter value 0 16 CTL0 CTL0 control register 0 0x0 32 read-write n 0x0 0x0 ARSE Auto-reload shadow enable 7 1 CEN Counter enable 0 1 CKDIV Clock division 8 2 SPM Single pulse mode 3 1 UPDIS Update disable 1 1 UPS Update source 2 1 DMAINTEN DMAINTEN DMA and interrupt enable register 0xC 32 read-write n 0x0 0x0 CH0IE Channel 0 capture/compare interrupt enable 1 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 TRGIE Trigger interrupt enable 6 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 32 read-write n 0x0 0x0 CH0IF Channel 0 capture/compare interrupt flag 1 1 CH0OF Channel 0 over capture flag 9 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH1OF Channel 1 over capture flag 10 1 TRGIF Trigger interrupt flag 6 1 UPIF Update interrupt flag 0 1 PSC PSC Prescaler register 0x28 32 read-write n 0x0 0x0 PSC Prescaler value of the counter clock 0 16 SMCFG SMCFG slave mode configuration register 0x8 32 read-write n 0x0 0x0 MSM Master-slave mode 7 1 SMC Slave mode control 0 3 TRGS Trigger selection 4 3 SWEVG SWEVG event generation register 0x14 32 write-only n 0x0 0x0 CH0G Channel 0 capture or compare event generation 1 1 CH1G Channel 1 capture or compare event generation 2 1 TRGG Trigger event generation 6 1 UPG Update generation 0 1 TIMER9 General-purpose-timers TIMER 0x0 0x0 0x400 registers n TIMER0_UP_TIMER9 25 CAR CAR Counter auto reload register 0x2C 32 read-write n 0x0 0x0 CARL Counter auto reload value 0 16 CFG CFG configuration register 0xFC 32 read-write n 0x0 0x0 CHVSEL Write CHxVAL register selection 1 1 CH0CV CH0CV Channel 0 capture/compare value register 0x34 32 read-write n 0x0 0x0 CH0VAL Capture or compare value of channel 0 0 16 CHCTL0_Input CHCTL0_Input Channel control register 0 ( (input mode) CHCTL0_Output 0x18 32 read-write n 0x0 0x0 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 32 read-write n 0x0 0x0 CH0COMCTL Channel 0 compare output control 4 3 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0MS Channel 0 I/O mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 32 read-write n 0x0 0x0 CH0EN Channel 0 capture/compare function enable 0 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare polarity 1 1 CNT CNT Counter register 0x24 32 read-write n 0x0 0x0 CNT current counter value 0 16 CTL0 CTL0 control register 1 0x0 32 read-write n 0x0 0x0 ARSE Auto-reload shadow enable 7 1 CEN Counter enable 0 1 CKDIV Clock division 8 2 UPDIS Update disable 1 1 UPS Update source 2 1 DMAINTEN DMAINTEN DMA/Interrupt enable register 0xC 32 read-write n 0x0 0x0 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 32 read-write n 0x0 0x0 CH0IF Channel 0 capture/compare interrupt flag 1 1 CH0OF Channel 0 over capture flag 9 1 UPIF Update interrupt flag 0 1 IRMP IRMP channel input remap register 0x50 32 read-write n 0x0 0x0 ITI1_RMP Internal trigger input1 remap 10 2 PSC PSC Prescaler register 0x28 32 read-write n 0x0 0x0 PSC Prescaler value of the counter clock 0 16 SWEVG SWEVG event generation register 0x14 32 write-only n 0x0 0x0 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 TLI TFT-LCD interface TLI 0x0 0x0 0x400 registers n TLI 88 TLI_ER 89 ASZ ASZ Active size register 0x10 32 read-write n 0x0 0x0 HASZ Size of the horizontal active area width plus back porch and synchronous pulse 16 12 VASZ Size of the vertical active area width plus back porch and synchronous pulse 0 12 BGC BGC Background color register 0x2C 32 read-write n 0x0 0x0 BVB Background value blue 0 8 BVG Background value green 8 8 BVR Background value red 16 8 BPSZ BPSZ Back-porch size register 0xC 32 read-write n 0x0 0x0 HBPSZ Size of the horizontal back porch plus synchronous pulse 16 12 VBPSZ Size of the vertical back porch plus synchronous pulse 0 12 CPPOS CPPOS Current pixel position register 0x44 32 read-only n 0x0 0x0 HPOS Horizontal position 16 16 VPOS Vertical position 0 16 CTL CLT Control register 0x18 32 read-write n 0x0 0x0 BDB Blue channel Dither Bits Number 4 3 CLKPS Pixel Clock Polarity Selection 28 1 DEPS Data Enable Polarity Selection 29 1 DFEN Dither Function Enable 16 1 GDB Green channel Dither Bits Number 8 3 HPPS Horizontal Pulse Polarity Selection 31 1 RDB Red channel Dither Bits Number 12 3 TLIEN TLI enable bit 0 1 VPPS Vertical Pulse Polarity Selection 30 1 INTC INTC Interrupt flag clear register 0x3C 32 write-only n 0x0 0x0 FEC FIFO Error Flag Clear 1 1 LCRC Layer Configuration Reloaded Flag Clear 3 1 LMC Line Mark Flag Clear 0 1 TEC Transaction Error Flag Clear 2 1 INTEN INTEN Interrupt enable register 0x34 32 read-write n 0x0 0x0 FEIE FIFO Error Interrupt Enable 1 1 LCRIE Layer Configuration Reloaded Interrupt Enable 3 1 LMIE Line Mark Interrupt Enable 0 1 TEIE Transaction Error Interrupt Enable 2 1 INTF INTF Interrupt flag register 0x38 32 read-only n 0x0 0x0 FEF FIFO Error Flag 1 1 LCRF Layer Configuration Reloaded Flag 3 1 LMF Line Mark Flag 0 1 TEF Transaction Error Flag 2 1 L0BLEND L0BLEND Layer 0 blending register 0xA0 32 read-write n 0x0 0x0 ACF1 Alpha Calculation Factor 1 of Blending Method 8 3 ACF2 Alpha Calculation Factor 2 of Blending Method 0 3 L0CKEY L0CKEY Layer 0 color key register 0x90 32 read-write n 0x0 0x0 CKEYB Color Key Blue 0 8 CKEYG Color Key Green 8 8 CKEYR Color Key Red 16 8 L0CTL L0CTL Layer 0 control register 0x84 32 read-write n 0x0 0x0 CKEYEN Color keying enable 1 1 LEN Layer enable 0 1 LUTEN LUT enable 4 1 L0DC L0DC Layer 0 default color register 0x9C 32 read-write n 0x0 0x0 DCA The default color ALPHA 24 8 DCB The default color blue 0 8 DCG The default color green 8 8 DCR The default color red 16 8 L0FBADDR L0FBADDR Layer 0 frame base address register 0xAC 32 read-write n 0x0 0x0 FBADD Frame Buffer base Address 0 32 L0FLLEN L0FLLEN Layer 0 frame line length register 0xB0 32 read-write n 0x0 0x0 FLL Frame Line Length 0 14 STDOFF Frame Buffer Stride Offset 16 14 L0FTLN L0FTLN Layer 0 frame total line number register 0xB4 32 read-write n 0x0 0x0 FTLN Frame Total Line Number 0 11 L0HPOS L0HPOS Layer 0 horizontal position parameters register 0x88 32 read-write n 0x0 0x0 WLP Window left position 0 12 WRP Window right position 16 12 L0LUT L0LUT Layer 0 look up table register 0xC4 32 read-write n 0x0 0x0 TADD Look Up Table Write Address 24 8 TB Blue channel of a LUT entry 0 8 TG Green channel of a LUT entry 8 8 TR Red Channel of a LUT entry 16 8 L0PPF L0PPF Layer 0 packeted pixel format register 0x94 32 read-write n 0x0 0x0 PPF Packeted Pixel Format 0 3 L0SA L0SA Layer 0 specified alpha register 0x98 32 read-write n 0x0 0x0 SA Specified alpha 0 8 L0VPOS L0VPOS Layer 0 vertical position parameters register 0x8C 32 read-write n 0x0 0x0 WBP Window bottom position 16 12 WTP Window top position 0 12 L1BLEND L1BLEND Layer 1 blending register 0x120 32 read-write n 0x0 0x0 ACF1 Alpha Calculation Factor 1 of Blending Method 8 3 ACF2 Alpha Calculation Factor 2 of Blending Method 0 3 L1CKEY L1CKEY Layer 1 color key register 0x110 32 read-write n 0x0 0x0 CKEYB Color Key Blue 0 8 CKEYG Color Key Green 8 8 CKEYR Color Key Red 16 8 L1CTL L1CTL Layer 1 control register 0x104 32 read-write n 0x0 0x0 CKEYEN Color keying enable 1 1 LEN Layer enable 0 1 LUTEN LUT enable 4 1 L1DC L1DC Layer 1 default color register 0x11C 32 read-write n 0x0 0x0 DCA The default color ALPHA 24 8 DCB The default color blue 0 8 DCG The default color green 8 8 DCR The default color red 16 8 L1FBADDR L1FBADDR Layer 1 frame base address register 0x12C 32 read-write n 0x0 0x0 FBADD Frame Buffer base Address 0 32 L1FLLEN L1FLLEN Layer 1 frame line length register 0x130 32 read-write n 0x0 0x0 FLL Frame Line Length 0 14 STDOFF Frame Buffer Stride Offset 16 14 L1FTLN L1FTLN Layer 1 frame total line number register 0x134 32 read-write n 0x0 0x0 FTLN Frame Total Line Number 0 11 L1HPOS L1HPOS Layer 1 horizontal position parameters register 0x108 32 read-write n 0x0 0x0 WLP Window left position 0 12 WRP Window right position 16 12 L1LUT L1LUT Layer 1 look up table register 0x144 32 read-write n 0x0 0x0 TADD Look Up Table Write Address 24 8 TB Blue channel of a LUT entry 0 8 TG Green channel of a LUT entry 8 8 TR Red channel of a LUT entry 16 8 L1PPF L1PPF Layer 1 packeted pixel format register 0x114 32 read-write n 0x0 0x0 PPF Packeted Pixel Format 0 3 L1SA L1SA Layer 1 specified alpha register 0x118 32 read-write n 0x0 0x0 SA Specified alpha 0 8 L1VPOS L1VPOS Layer 1 vertical position parameters register 0x10C 32 read-write n 0x0 0x0 WBP Window bottom position 16 12 WTP Window top position 0 12 LM LM Line mark register 0x40 32 read-write n 0x0 0x0 LM Line Mark value 0 11 RL RL Reload layer register 0x24 32 read-write n 0x0 0x0 FBR Frame Blank Reload 1 1 RQR Request Reload 0 1 SPSZ SPSZ Synchronous pulse size register 0x8 32 read-write n 0x0 0x0 HPSZ size of horizontal synchronous pluse 16 12 VPSZ size of vertical synchronous pluse 0 12 STAT STAT Status register 0x48 32 read-only n 0x0 0x0 HDE Current HDE status 1 1 HS Current HS staus of the TLI 3 1 VDE Current VDE status 0 1 VS Current VS staus of the TLI 2 1 TSZ TSZ Total size register 0x14 32 read-write n 0x0 0x0 HTSZ Horizontal total size of the display 16 12 VTSZ Vertical total size of the display 0 12 TRNG Ture random number generator TRNG 0x0 0x0 0x400 registers n TRNG 80 CTL CTL Control register 0x0 32 read-write n 0x0 0x0 IE Interrupt bit 3 1 TRNGEN TRNG enable bit 2 1 DATA DATA data register 0x8 32 read-only n 0x0 0x0 TRNDATA 32-bit random data 0 32 STAT STAT Status register 0x4 32 read-write n 0x0 0x0 CECS Clock error current status 1 1 read-only CEIF Clock error interrupt flag 5 1 read-write DRDY Random data ready status bit 0 1 read-only SECS Seed error current status 2 1 read-only SEIF Seed error interrupt flag 6 1 read-write UART3 Universal asynchronous receiver transmitter UART 0x0 0x0 0x400 registers n UART3 52 BAUD BAUD Baud rate register 0x8 32 read-write n 0x0 0x0 FRADIV Fraction part of baud-rate divider 0 4 INTDIV Integer part of baud-rate divider 4 12 CHC CHC Coherence control register 0xC0 32 read-write n 0x0 0x0 BCM Break frame coherence mode 2 1 EPERR Early parity error flag 8 1 HCM Hardware flow control coherence mode 0 1 PCM Parity check coherence mode 1 1 CTL0 CTL0 Control register 0 0xC 32 read-write n 0x0 0x0 IDLEIE IDLE line detected interrupt enable 4 1 OVSMOD Oversampling mode 15 1 PCEN Parity check function enable 10 1 PERRIE Parity error interrupt enable 8 1 PM Parity mode 9 1 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 5 1 REN Receiver enable 2 1 RWU Receiver wakeup from mute mode 1 1 SBKCMD Send break command 0 1 TBEIE Transmitter buffer empty interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 TEN Transmitter enable 3 1 UEN USART enable 13 1 WL Word length 12 1 WM Wakeup method in mute mode 11 1 CTL1 CTL1 Control register 1 0x10 32 read-write n 0x0 0x0 ADDR Address of the USART 0 4 CKEN CK pin enable 11 1 CLEN CK Length 8 1 CPH Clock phase 9 1 CPL Clock polarity 10 1 LBDIE LIN break detection interrupt enable 6 1 LBLEN LIN break frame length 5 1 LMEN LIN mode enable 14 1 STB STOP bits length 12 2 CTL2 CTL2 Control register 2 0x14 32 read-write n 0x0 0x0 CTSEN CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DENR DMA request enable for reception 6 1 DENT DMA request enable for transmission 7 1 ERRIE Error interrupt enable 0 1 HDEN Half-duplex selection 3 1 IREN IrDA mode enable 1 1 IRLP IrDA low-power 2 1 NKEN Smartcard NACK enable 4 1 OSB One sample bit method enable 11 1 RTSEN RTS enable 8 1 SCEN Smartcard mode enable 5 1 DATA DATA Data register 0x4 32 read-write n 0x0 0x0 DATA Transmit or read data value 0 9 GP GP Guard time and prescaler register 0x1C 32 read-write n 0x0 0x0 GUAT Guard time value in Smartcard mode 8 8 PSC Prescaler value 0 8 STAT0 STAT0 Status register 0 0x0 32 read-only n 0x0 0x0 CTSF CTS change flag 9 1 FERR Frame error flag 1 1 IDLEF IDLE frame detected flag 4 1 LBDF LIN break detection flag 8 1 NERR Noise error flag 2 1 ORERR Overrun error 3 1 PERR Parity error flag 0 1 RBNE Read data buffer not empty 5 1 TBE Transmit data buffer empty 7 1 TC Transmission complete 6 1 UART4 Universal asynchronous receiver transmitter UART 0x0 0x0 0x400 registers n UART4 53 BAUD BAUD Baud rate register 0x8 32 read-write n 0x0 0x0 FRADIV Fraction part of baud-rate divider 0 4 INTDIV Integer part of baud-rate divider 4 12 CHC CHC Coherence control register 0xC0 32 read-write n 0x0 0x0 BCM Break frame coherence mode 2 1 EPERR Early parity error flag 8 1 HCM Hardware flow control coherence mode 0 1 PCM Parity check coherence mode 1 1 CTL0 CTL0 Control register 0 0xC 32 read-write n 0x0 0x0 IDLEIE IDLE line detected interrupt enable 4 1 OVSMOD Oversampling mode 15 1 PCEN Parity check function enable 10 1 PERRIE Parity error interrupt enable 8 1 PM Parity mode 9 1 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 5 1 REN Receiver enable 2 1 RWU Receiver wakeup from mute mode 1 1 SBKCMD Send break command 0 1 TBEIE Transmitter buffer empty interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 TEN Transmitter enable 3 1 UEN USART enable 13 1 WL Word length 12 1 WM Wakeup method in mute mode 11 1 CTL1 CTL1 Control register 1 0x10 32 read-write n 0x0 0x0 ADDR Address of the USART 0 4 CKEN CK pin enable 11 1 CLEN CK Length 8 1 CPH Clock phase 9 1 CPL Clock polarity 10 1 LBDIE LIN break detection interrupt enable 6 1 LBLEN LIN break frame length 5 1 LMEN LIN mode enable 14 1 STB STOP bits length 12 2 CTL2 CTL2 Control register 2 0x14 32 read-write n 0x0 0x0 CTSEN CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DENR DMA request enable for reception 6 1 DENT DMA request enable for transmission 7 1 ERRIE Error interrupt enable 0 1 HDEN Half-duplex selection 3 1 IREN IrDA mode enable 1 1 IRLP IrDA low-power 2 1 NKEN Smartcard NACK enable 4 1 OSB One sample bit method enable 11 1 RTSEN RTS enable 8 1 SCEN Smartcard mode enable 5 1 DATA DATA Data register 0x4 32 read-write n 0x0 0x0 DATA Transmit or read data value 0 9 GP GP Guard time and prescaler register 0x1C 32 read-write n 0x0 0x0 GUAT Guard time value in Smartcard mode 8 8 PSC Prescaler value 0 8 STAT0 STAT0 Status register 0 0x0 32 read-only n 0x0 0x0 CTSF CTS change flag 9 1 FERR Frame error flag 1 1 IDLEF IDLE frame detected flag 4 1 LBDF LIN break detection flag 8 1 NERR Noise error flag 2 1 ORERR Overrun error 3 1 PERR Parity error flag 0 1 RBNE Read data buffer not empty 5 1 TBE Transmit data buffer empty 7 1 TC Transmission complete 6 1 UART6 Universal asynchronous receiver transmitter UART 0x0 0x0 0x400 registers n UART6 82 BAUD BAUD Baud rate register 0x8 32 read-write n 0x0 0x0 FRADIV Fraction part of baud-rate divider 0 4 INTDIV Integer part of baud-rate divider 4 12 CHC CHC Coherence control register 0xC0 32 read-write n 0x0 0x0 BCM Break frame coherence mode 2 1 EPERR Early parity error flag 8 1 HCM Hardware flow control coherence mode 0 1 PCM Parity check coherence mode 1 1 CTL0 CTL0 Control register 0 0xC 32 read-write n 0x0 0x0 IDLEIE IDLE line detected interrupt enable 4 1 OVSMOD Oversampling mode 15 1 PCEN Parity check function enable 10 1 PERRIE Parity error interrupt enable 8 1 PM Parity mode 9 1 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 5 1 REN Receiver enable 2 1 RWU Receiver wakeup from mute mode 1 1 SBKCMD Send break command 0 1 TBEIE Transmitter buffer empty interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 TEN Transmitter enable 3 1 UEN USART enable 13 1 WL Word length 12 1 WM Wakeup method in mute mode 11 1 CTL1 CTL1 Control register 1 0x10 32 read-write n 0x0 0x0 ADDR Address of the USART 0 4 CKEN CK pin enable 11 1 CLEN CK Length 8 1 CPH Clock phase 9 1 CPL Clock polarity 10 1 LBDIE LIN break detection interrupt enable 6 1 LBLEN LIN break frame length 5 1 LMEN LIN mode enable 14 1 STB STOP bits length 12 2 CTL2 CTL2 Control register 2 0x14 32 read-write n 0x0 0x0 CTSEN CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DENR DMA request enable for reception 6 1 DENT DMA request enable for transmission 7 1 ERRIE Error interrupt enable 0 1 HDEN Half-duplex selection 3 1 IREN IrDA mode enable 1 1 IRLP IrDA low-power 2 1 NKEN Smartcard NACK enable 4 1 OSB One sample bit method enable 11 1 RTSEN RTS enable 8 1 SCEN Smartcard mode enable 5 1 DATA DATA Data register 0x4 32 read-write n 0x0 0x0 DATA Transmit or read data value 0 9 GP GP Guard time and prescaler register 0x1C 32 read-write n 0x0 0x0 GUAT Guard time value in Smartcard mode 8 8 PSC Prescaler value 0 8 STAT0 STAT0 Status register 0 0x0 32 read-only n 0x0 0x0 CTSF CTS change flag 9 1 FERR Frame error flag 1 1 IDLEF IDLE frame detected flag 4 1 LBDF LIN break detection flag 8 1 NERR Noise error flag 2 1 ORERR Overrun error 3 1 PERR Parity error flag 0 1 RBNE Read data buffer not empty 5 1 TBE Transmit data buffer empty 7 1 TC Transmission complete 6 1 UART7 Universal asynchronous receiver transmitter UART 0x0 0x0 0x400 registers n UART7 83 BAUD BAUD Baud rate register 0x8 32 read-write n 0x0 0x0 FRADIV Fraction part of baud-rate divider 0 4 INTDIV Integer part of baud-rate divider 4 12 CHC CHC Coherence control register 0xC0 32 read-write n 0x0 0x0 BCM Break frame coherence mode 2 1 EPERR Early parity error flag 8 1 HCM Hardware flow control coherence mode 0 1 PCM Parity check coherence mode 1 1 CTL0 CTL0 Control register 0 0xC 32 read-write n 0x0 0x0 IDLEIE IDLE line detected interrupt enable 4 1 OVSMOD Oversampling mode 15 1 PCEN Parity check function enable 10 1 PERRIE Parity error interrupt enable 8 1 PM Parity mode 9 1 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 5 1 REN Receiver enable 2 1 RWU Receiver wakeup from mute mode 1 1 SBKCMD Send break command 0 1 TBEIE Transmitter buffer empty interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 TEN Transmitter enable 3 1 UEN USART enable 13 1 WL Word length 12 1 WM Wakeup method in mute mode 11 1 CTL1 CTL1 Control register 1 0x10 32 read-write n 0x0 0x0 ADDR Address of the USART 0 4 CKEN CK pin enable 11 1 CLEN CK Length 8 1 CPH Clock phase 9 1 CPL Clock polarity 10 1 LBDIE LIN break detection interrupt enable 6 1 LBLEN LIN break frame length 5 1 LMEN LIN mode enable 14 1 STB STOP bits length 12 2 CTL2 CTL2 Control register 2 0x14 32 read-write n 0x0 0x0 CTSEN CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DENR DMA request enable for reception 6 1 DENT DMA request enable for transmission 7 1 ERRIE Error interrupt enable 0 1 HDEN Half-duplex selection 3 1 IREN IrDA mode enable 1 1 IRLP IrDA low-power 2 1 NKEN Smartcard NACK enable 4 1 OSB One sample bit method enable 11 1 RTSEN RTS enable 8 1 SCEN Smartcard mode enable 5 1 DATA DATA Data register 0x4 32 read-write n 0x0 0x0 DATA Transmit or read data value 0 9 GP GP Guard time and prescaler register 0x1C 32 read-write n 0x0 0x0 GUAT Guard time value in Smartcard mode 8 8 PSC Prescaler value 0 8 STAT0 STAT0 Status register 0 0x0 32 read-only n 0x0 0x0 CTSF CTS change flag 9 1 FERR Frame error flag 1 1 IDLEF IDLE frame detected flag 4 1 LBDF LIN break detection flag 8 1 NERR Noise error flag 2 1 ORERR Overrun error 3 1 PERR Parity error flag 0 1 RBNE Read data buffer not empty 5 1 TBE Transmit data buffer empty 7 1 TC Transmission complete 6 1 USART0 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n USART0 37 BAUD BAUD Baud rate register 0x8 32 read-write n 0x0 0x0 FRADIV Fraction part of baud-rate divider 0 4 INTDIV Integer part of baud-rate divider 4 12 CHC CHC Coherence control register 0xC0 32 read-write n 0x0 0x0 BCM Break frame coherence mode 2 1 EPERR Early parity error flag 8 1 HCM Hardware flow control coherence mode 0 1 PCM Parity check coherence mode 1 1 CTL0 CTL0 Control register 0 0xC 32 read-write n 0x0 0x0 IDLEIE IDLE line detected interrupt enable 4 1 OVSMOD Oversampling mode 15 1 PCEN Parity check function enable 10 1 PERRIE Parity error interrupt enable 8 1 PM Parity mode 9 1 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 5 1 REN Receiver enable 2 1 RWU Receiver wakeup from mute mode 1 1 SBKCMD Send break command 0 1 TBEIE Transmitter buffer empty interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 TEN Transmitter enable 3 1 UEN USART enable 13 1 WL Word length 12 1 WM Wakeup method in mute mode 11 1 CTL1 CTL1 Control register 1 0x10 32 read-write n 0x0 0x0 ADDR Address of the USART 0 4 CKEN CK pin enable 11 1 CLEN CK Length 8 1 CPH Clock phase 9 1 CPL Clock polarity 10 1 LBDIE LIN break detection interrupt enable 6 1 LBLEN LIN break frame length 5 1 LMEN LIN mode enable 14 1 STB STOP bits length 12 2 CTL2 CTL2 Control register 2 0x14 32 read-write n 0x0 0x0 CTSEN CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DENR DMA request enable for reception 6 1 DENT DMA request enable for transmission 7 1 ERRIE Error interrupt enable 0 1 HDEN Half-duplex selection 3 1 IREN IrDA mode enable 1 1 IRLP IrDA low-power 2 1 NKEN Smartcard NACK enable 4 1 OSB One sample bit method enable 11 1 RTSEN RTS enable 8 1 SCEN Smartcard mode enable 5 1 CTL3 CTL3 Control register 3 0x80 32 read-write n 0x0 0x0 DINV Data bit level inversion 10 1 EBIE Interrupt enable bit of end of block event 5 1 MSBF Most significant bit first 11 1 RINV RX pin level inversion 8 1 RTEN Receiver timeout enable 0 1 RTIE Interrupt enable bit of receive timeout event 4 1 SCRTNUM Smartcard auto-retry number 1 3 TINV TX pin level inversion 9 1 DATA DATA Data register 0x4 32 read-write n 0x0 0x0 DATA Transmit or read data value 0 9 GP GP Guard time and prescaler register 0x1C 32 read-write n 0x0 0x0 GUAT Guard time value in Smartcard mode 8 8 PSC Prescaler value 0 8 RT RT Receiver timeout register 0x84 32 read-write n 0x0 0x0 BL Block Length 24 8 RT Receiver timeout threshold 0 24 STAT0 STAT0 Status register 0 0x0 32 read-only n 0x0 0x0 CTSF CTS change flag 9 1 FERR Frame error flag 1 1 IDLEF IDLE frame detected flag 4 1 LBDF LIN break detection flag 8 1 NERR Noise error flag 2 1 ORERR Overrun error 3 1 PERR Parity error flag 0 1 RBNE Read data buffer not empty 5 1 TBE Transmit data buffer empty 7 1 TC Transmission complete 6 1 STAT1 STAT1 Status register 1 0x88 32 read-write n 0x0 0x0 BSY Busy flag 16 1 read-only EBF End of block flag 12 1 write RTF Receiver timeout flag 11 1 write USART1 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n USART1 38 BAUD BAUD Baud rate register 0x8 32 read-write n 0x0 0x0 FRADIV Fraction part of baud-rate divider 0 4 INTDIV Integer part of baud-rate divider 4 12 CHC CHC Coherence control register 0xC0 32 read-write n 0x0 0x0 BCM Break frame coherence mode 2 1 EPERR Early parity error flag 8 1 HCM Hardware flow control coherence mode 0 1 PCM Parity check coherence mode 1 1 CTL0 CTL0 Control register 0 0xC 32 read-write n 0x0 0x0 IDLEIE IDLE line detected interrupt enable 4 1 OVSMOD Oversampling mode 15 1 PCEN Parity check function enable 10 1 PERRIE Parity error interrupt enable 8 1 PM Parity mode 9 1 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 5 1 REN Receiver enable 2 1 RWU Receiver wakeup from mute mode 1 1 SBKCMD Send break command 0 1 TBEIE Transmitter buffer empty interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 TEN Transmitter enable 3 1 UEN USART enable 13 1 WL Word length 12 1 WM Wakeup method in mute mode 11 1 CTL1 CTL1 Control register 1 0x10 32 read-write n 0x0 0x0 ADDR Address of the USART 0 4 CKEN CK pin enable 11 1 CLEN CK Length 8 1 CPH Clock phase 9 1 CPL Clock polarity 10 1 LBDIE LIN break detection interrupt enable 6 1 LBLEN LIN break frame length 5 1 LMEN LIN mode enable 14 1 STB STOP bits length 12 2 CTL2 CTL2 Control register 2 0x14 32 read-write n 0x0 0x0 CTSEN CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DENR DMA request enable for reception 6 1 DENT DMA request enable for transmission 7 1 ERRIE Error interrupt enable 0 1 HDEN Half-duplex selection 3 1 IREN IrDA mode enable 1 1 IRLP IrDA low-power 2 1 NKEN Smartcard NACK enable 4 1 OSB One sample bit method enable 11 1 RTSEN RTS enable 8 1 SCEN Smartcard mode enable 5 1 CTL3 CTL3 Control register 3 0x80 32 read-write n 0x0 0x0 DINV Data bit level inversion 10 1 EBIE Interrupt enable bit of end of block event 5 1 MSBF Most significant bit first 11 1 RINV RX pin level inversion 8 1 RTEN Receiver timeout enable 0 1 RTIE Interrupt enable bit of receive timeout event 4 1 SCRTNUM Smartcard auto-retry number 1 3 TINV TX pin level inversion 9 1 DATA DATA Data register 0x4 32 read-write n 0x0 0x0 DATA Transmit or read data value 0 9 GP GP Guard time and prescaler register 0x1C 32 read-write n 0x0 0x0 GUAT Guard time value in Smartcard mode 8 8 PSC Prescaler value 0 8 RT RT Receiver timeout register 0x84 32 read-write n 0x0 0x0 BL Block Length 24 8 RT Receiver timeout threshold 0 24 STAT0 STAT0 Status register 0 0x0 32 read-only n 0x0 0x0 CTSF CTS change flag 9 1 FERR Frame error flag 1 1 IDLEF IDLE frame detected flag 4 1 LBDF LIN break detection flag 8 1 NERR Noise error flag 2 1 ORERR Overrun error 3 1 PERR Parity error flag 0 1 RBNE Read data buffer not empty 5 1 TBE Transmit data buffer empty 7 1 TC Transmission complete 6 1 STAT1 STAT1 Status register 1 0x88 32 read-write n 0x0 0x0 BSY Busy flag 16 1 read-only EBF End of block flag 12 1 write RTF Receiver timeout flag 11 1 write USART2 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n USART2 39 BAUD BAUD Baud rate register 0x8 32 read-write n 0x0 0x0 FRADIV Fraction part of baud-rate divider 0 4 INTDIV Integer part of baud-rate divider 4 12 CHC CHC Coherence control register 0xC0 32 read-write n 0x0 0x0 BCM Break frame coherence mode 2 1 EPERR Early parity error flag 8 1 HCM Hardware flow control coherence mode 0 1 PCM Parity check coherence mode 1 1 CTL0 CTL0 Control register 0 0xC 32 read-write n 0x0 0x0 IDLEIE IDLE line detected interrupt enable 4 1 OVSMOD Oversampling mode 15 1 PCEN Parity check function enable 10 1 PERRIE Parity error interrupt enable 8 1 PM Parity mode 9 1 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 5 1 REN Receiver enable 2 1 RWU Receiver wakeup from mute mode 1 1 SBKCMD Send break command 0 1 TBEIE Transmitter buffer empty interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 TEN Transmitter enable 3 1 UEN USART enable 13 1 WL Word length 12 1 WM Wakeup method in mute mode 11 1 CTL1 CTL1 Control register 1 0x10 32 read-write n 0x0 0x0 ADDR Address of the USART 0 4 CKEN CK pin enable 11 1 CLEN CK Length 8 1 CPH Clock phase 9 1 CPL Clock polarity 10 1 LBDIE LIN break detection interrupt enable 6 1 LBLEN LIN break frame length 5 1 LMEN LIN mode enable 14 1 STB STOP bits length 12 2 CTL2 CTL2 Control register 2 0x14 32 read-write n 0x0 0x0 CTSEN CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DENR DMA request enable for reception 6 1 DENT DMA request enable for transmission 7 1 ERRIE Error interrupt enable 0 1 HDEN Half-duplex selection 3 1 IREN IrDA mode enable 1 1 IRLP IrDA low-power 2 1 NKEN Smartcard NACK enable 4 1 OSB One sample bit method enable 11 1 RTSEN RTS enable 8 1 SCEN Smartcard mode enable 5 1 CTL3 CTL3 Control register 3 0x80 32 read-write n 0x0 0x0 DINV Data bit level inversion 10 1 EBIE Interrupt enable bit of end of block event 5 1 MSBF Most significant bit first 11 1 RINV RX pin level inversion 8 1 RTEN Receiver timeout enable 0 1 RTIE Interrupt enable bit of receive timeout event 4 1 SCRTNUM Smartcard auto-retry number 1 3 TINV TX pin level inversion 9 1 DATA DATA Data register 0x4 32 read-write n 0x0 0x0 DATA Transmit or read data value 0 9 GP GP Guard time and prescaler register 0x1C 32 read-write n 0x0 0x0 GUAT Guard time value in Smartcard mode 8 8 PSC Prescaler value 0 8 RT RT Receiver timeout register 0x84 32 read-write n 0x0 0x0 BL Block Length 24 8 RT Receiver timeout threshold 0 24 STAT0 STAT0 Status register 0 0x0 32 read-only n 0x0 0x0 CTSF CTS change flag 9 1 FERR Frame error flag 1 1 IDLEF IDLE frame detected flag 4 1 LBDF LIN break detection flag 8 1 NERR Noise error flag 2 1 ORERR Overrun error 3 1 PERR Parity error flag 0 1 RBNE Read data buffer not empty 5 1 TBE Transmit data buffer empty 7 1 TC Transmission complete 6 1 STAT1 STAT1 Status register 1 0x88 32 read-write n 0x0 0x0 BSY Busy flag 16 1 read-only EBF End of block flag 12 1 write RTF Receiver timeout flag 11 1 write USART5 Universal synchronous asynchronous receiver transmitter USART 0x0 0x0 0x400 registers n USART5 71 BAUD BAUD Baud rate register 0x8 32 read-write n 0x0 0x0 FRADIV Fraction part of baud-rate divider 0 4 INTDIV Integer part of baud-rate divider 4 12 CHC CHC Coherence control register 0xC0 32 read-write n 0x0 0x0 BCM Break frame coherence mode 2 1 EPERR Early parity error flag 8 1 HCM Hardware flow control coherence mode 0 1 PCM Parity check coherence mode 1 1 CTL0 CTL0 Control register 0 0xC 32 read-write n 0x0 0x0 IDLEIE IDLE line detected interrupt enable 4 1 OVSMOD Oversampling mode 15 1 PCEN Parity check function enable 10 1 PERRIE Parity error interrupt enable 8 1 PM Parity mode 9 1 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 5 1 REN Receiver enable 2 1 RWU Receiver wakeup from mute mode 1 1 SBKCMD Send break command 0 1 TBEIE Transmitter buffer empty interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 TEN Transmitter enable 3 1 UEN USART enable 13 1 WL Word length 12 1 WM Wakeup method in mute mode 11 1 CTL1 CTL1 Control register 1 0x10 32 read-write n 0x0 0x0 ADDR Address of the USART 0 4 CKEN CK pin enable 11 1 CLEN CK Length 8 1 CPH Clock phase 9 1 CPL Clock polarity 10 1 LBDIE LIN break detection interrupt enable 6 1 LBLEN LIN break frame length 5 1 LMEN LIN mode enable 14 1 STB STOP bits length 12 2 CTL2 CTL2 Control register 2 0x14 32 read-write n 0x0 0x0 CTSEN CTS enable 9 1 CTSIE CTS interrupt enable 10 1 DENR DMA request enable for reception 6 1 DENT DMA request enable for transmission 7 1 ERRIE Error interrupt enable 0 1 HDEN Half-duplex selection 3 1 IREN IrDA mode enable 1 1 IRLP IrDA low-power 2 1 NKEN Smartcard NACK enable 4 1 OSB One sample bit method enable 11 1 RTSEN RTS enable 8 1 SCEN Smartcard mode enable 5 1 CTL3 CTL3 Control register 3 0x80 32 read-write n 0x0 0x0 DINV Data bit level inversion 10 1 EBIE Interrupt enable bit of end of block event 5 1 MSBF Most significant bit first 11 1 RINV RX pin level inversion 8 1 RTEN Receiver timeout enable 0 1 RTIE Interrupt enable bit of receive timeout event 4 1 SCRTNUM Smartcard auto-retry number 1 3 TINV TX pin level inversion 9 1 DATA DATA Data register 0x4 32 read-write n 0x0 0x0 DATA Transmit or read data value 0 9 GP GP Guard time and prescaler register 0x1C 32 read-write n 0x0 0x0 GUAT Guard time value in Smartcard mode 8 8 PSC Prescaler value 0 8 RT RT Receiver timeout register 0x84 32 read-write n 0x0 0x0 BL Block Length 24 8 RT Receiver timeout threshold 0 24 STAT0 STAT0 Status register 0 0x0 32 read-only n 0x0 0x0 CTSF CTS change flag 9 1 FERR Frame error flag 1 1 IDLEF IDLE frame detected flag 4 1 LBDF LIN break detection flag 8 1 NERR Noise error flag 2 1 ORERR Overrun error 3 1 PERR Parity error flag 0 1 RBNE Read data buffer not empty 5 1 TBE Transmit data buffer empty 7 1 TC Transmission complete 6 1 STAT1 STAT1 Status register 1 0x88 32 read-write n 0x0 0x0 BSY Busy flag 16 1 read-only EBF End of block flag 12 1 write RTF Receiver timeout flag 11 1 write WWDGT Window watchdog timer WWDGT 0x0 0x0 0x400 registers n WWDGT 0 CFG CFG Configuration register 0x4 32 read-write n 0x0 0x0 EWIE Early wakeup interrupt 9 1 PSC Prescaler 7 2 WIN 7-bit window value 0 7 CTL CTL Control register 0x0 32 read-write n 0x0 0x0 CNT 7-bit counter 0 7 WDGTEN Activation bit 7 1 STAT STAT Status register 0x8 32 read-write n 0x0 0x0 EWIF Early wakeup interrupt flag 0 1