Goodix
GMF0x
2024.05.06
GMF0x
CM0
r0p0
little
2
false
8
32
ADC
Analog-to-Digital Converter
ADC
0x0
0x0
0x400
registers
n
ADC1
ADC1 interrupt
12
AWT
AWT
ADC Analog Watchdog Threshold Register
0x20
32
read-write
n
0x0
0x0
AWTH
Analog watchdog high threshold
16
12
read-write
AWTL
Analog watchdog low threshold
0
12
read-write
CCFG
CCFG
ADC Common Configuration Register
0x308
32
read-write
n
0x0
0x0
TEMPSEN
Temperature sensor enable
23
1
read-write
VINREFEN
VINREF signal to ADC enable
22
1
read-write
CFG0
CFG0
ADC configuration Register 0
0xC
32
read-write
n
0x0
0x0
ALIGN
Alignment of data
5
1
read-write
AUTOPM
Automatic power management
15
1
read-write
AWCHSEL
Analog watchdog channel selection
26
5
read-write
AWEN
Analog watchdog enable
23
1
read-write
AWSG
Analog watchdog Single channel mode
22
1
read-write
DIR
Scanning direction of a sequence
2
1
read-write
DMAEN
Enable the DMA function of ADC
0
1
read-write
DMAMOD
Mode of DMA of ADC
1
1
read-write
EXTTRIG
External trigger selection
6
3
read-write
OVRW
Overrun write
12
1
read-write
PAUSE
Pause mode
16
1
read-write
RES
Resolution of conversion
3
2
read-write
SEQCON
Sequence continuous mode
13
1
read-write
TRIG
Trigger selection
10
2
read-write
WTRD
Wait to read mode
14
1
read-write
CFG1
CFG1
ADC Configuration Register 1
0x10
32
read-write
n
0x0
0x0
CLKSEL
ADC clock selection
30
2
read-write
CHEN
CHEN
ADC Channel Enable Register
0x28
32
read-write
n
0x0
0x0
CHEN0
Channel 0 enable
0
1
read-write
CHEN1
Channel 1 enable
1
1
read-write
CHEN16
Channel 16 enable
16
1
read-write
CHEN17
Channel 17 enable
17
1
read-write
CHEN2
Channel 2 enable
2
1
read-write
CHEN3
Channel 3 enable
3
1
read-write
CHEN4
Channel 4 enable
4
1
read-write
CHEN5
Channel 5 enable
5
1
read-write
CHEN6
Channel 6 enable
6
1
read-write
CHEN7
Channel 7 enable
7
1
read-write
CHEN8
Channel 8 enable
8
1
read-write
CHEN9
Channel 9 enable
9
1
read-write
CTL
CTL
ADC Control Register
0x8
32
read-write
n
0x0
0x0
CAL
ADC calibration command
31
1
read-write
DIS
ADC disable
1
1
read-write
EN
ADC enable
0
1
read-write
START
ADC start command
2
1
read-write
STP
ADC stop conversion command
4
1
read-write
DATA
DATA
ADC Data Register
0x40
32
read-only
n
0x0
0x0
DATA
ADC data
0
16
read-only
INT
INT
ADC Interrupt Register
0x4
32
read-write
n
0x0
0x0
AWINTEN
Analog watchdog interrupt enable
7
1
read-write
ECINTEN
End of conversion interrupt enable
2
1
read-write
ESINTEN
End of sequence interrupt enable
3
1
read-write
ESMPINTEN
End of sampling interrupt enable
1
1
read-write
OVRINTEN
Overrun interrupt enable
4
1
read-write
RDYINTEN
ADC ready interrupt enable
0
1
read-write
SMPT
SMPT
ADC Sampling time Register
0x14
32
read-write
n
0x0
0x0
SMPT
Sampling time
0
3
read-write
STAT
STAT
ADC State Register
0x0
32
read-only
n
0x0
0x0
AWF
Analog watchdog flag
7
1
read-only
ECF
End of conversion flag
2
1
read-only
ESF
End of sequence flag
3
1
read-only
ESMPF
End of sampling flag
1
1
read-only
OVRF
Overrun flag
4
1
read-only
RDYF
ADC ready flag
0
1
read-only
CRC
Cyclic redundancy check calculation unit
CRC
0x0
0x0
0x400
registers
n
CTL
CTL
CRC reset, data reverse
0x8
32
read-write
n
0x0
0x0
RID
Reverse input data
5
2
read-write
ROD
Reverse output data
7
1
read-write
RST
Reset CRC
0
1
read-write
DATA
DATA
Write new data to the CRC calculator, read CRC calculation result
0x0
32
read-write
n
0x0
0x0
DATA
CRC data register bits
0
32
read-write
INDDATA
INDDATA
A temporary storage location for one byte
0x4
32
read-write
n
0x0
0x0
INDDATA
CRC 8-bit independent data register bits
0
8
read-write
INITVAL
INITVAL
Configure CRC initial value
0x10
32
read-write
n
0x0
0x0
CRC_INITVAL
CRC initial value
0
32
read-write
DEBUG
Debug
DEBUG
0x0
0x0
0x400
registers
n
CTL
CTL
debug in low power mode
0x4
32
read-write
n
0x0
0x0
STB
Debug Standby mode
2
1
read-write
STP
Debug Stop mode
1
1
read-write
FRZ0
FRZ0
configure if clock of I2C/FWDT/WWDT/RTC/TIMER stop when the core is halted
0x8
32
read-write
n
0x0
0x0
FWDTSTP
Free running watchdog timer stopped when core is halted
12
1
read-write
I2C1_SMBUSSTP
I2C1 SMBUS timeout mode stopped when core is halted
21
1
read-write
RTCSTP
RTC counter is stopped when the core is halted
10
1
read-write
TIMERG1STP
TIMERG1 is stopped when the core is halted
1
1
read-write
TIMERG2STP
TIMERG2 is stopped when the core is halted
8
1
read-write
WWDTSTP
window watchdog timer stopped when core is halted
11
1
read-write
FRZ1
FRZ1
configure if clock of timers stop when the core is halted
0xC
32
read-write
n
0x0
0x0
TIMERA1STP
TIMERA1 counter is stopped when the core is halted
11
1
read-write
TIMERG3STP
TIMERG3 counter is stopped when the core is halted
17
1
read-write
TIMERG4STP
TIMERG4 counter is stopped when the core is halted
18
1
read-write
ID
ID
debug id code
0x0
32
read-only
n
0x0
0x0
DEV_ID
Device identifier, indicates device family
0
12
read-only
REV_ID
Revision identifier This field indicates the revision of the device
16
16
read-only
DMA
Direct Memory Access
DMA
0x0
0x0
0x400
registers
n
DMA_CH1
DMA channel 1 interrupt
9
DMA_CH2_3
DMA channel 2 and 3 interrupts
10
DMA_CH4_5
DMA channel 4 and 5 interrupts
11
CFG1
CFG1
channel 1 channel configuration
0x8
32
read-write
n
0x0
0x0
CHEN
channel enable
0
1
read-write
CINTEN
transfer complete interrupt enable
1
1
read-write
CIR
circular mode
5
1
read-write
DIR
data transfer direction
4
1
read-write
EINTEN
transfer error interrupt enable
3
1
read-write
HINTEN
half transfer interrupt enable
2
1
read-write
M2M
memory to memory mode
14
1
read-write
MEMINC
memory increment mode
7
1
read-write
MSZ
memory size
10
2
read-write
PERIINC
peripheral increment mode
6
1
read-write
PERISZ
peripheral size
8
2
read-write
PRI
channel priority level
12
2
read-write
CFG2
CFG2
channel 2 channel configuration
0x1C
32
read-write
n
0x0
0x0
CHEN
channel enable
0
1
read-write
CINTEN
transfer complete interrupt enable
1
1
read-write
CIR
circular mode
5
1
read-write
DIR
data transfer direction
4
1
read-write
EINTEN
transfer error interrupt enable
3
1
read-write
HINTEN
half transfer interrupt enable
2
1
read-write
M2M
memory to memory mode
14
1
read-write
MEMINC
memory increment mode
7
1
read-write
MSZ
memory size
10
2
read-write
PERIINC
peripheral increment mode
6
1
read-write
PERISZ
peripheral size
8
2
read-write
PRI
channel priority level
12
2
read-write
CFG3
CFG3
channel 3 channel configuration
0x30
32
read-write
n
0x0
0x0
CHEN
channel enable
0
1
read-write
CINTEN
transfer complete interrupt enable
1
1
read-write
CIR
circular mode
5
1
read-write
DIR
data transfer direction
4
1
read-write
EINTEN
transfer error interrupt enable
3
1
read-write
HINTEN
half transfer interrupt enable
2
1
read-write
M2M
memory to memory mode
14
1
read-write
MEMINC
memory increment mode
7
1
read-write
MSZ
memory size
10
2
read-write
PERIINC
peripheral increment mode
6
1
read-write
PERISZ
peripheral size
8
2
read-write
PRI
channel priority level
12
2
read-write
CFG4
CFG4
channel 4 channel configuration
0x44
32
read-write
n
0x0
0x0
CHEN
channel enable
0
1
read-write
CINTEN
transfer complete interrupt enable
1
1
read-write
CIR
circular mode
5
1
read-write
DIR
data transfer direction
4
1
read-write
EINTEN
transfer error interrupt enable
3
1
read-write
HINTEN
half transfer interrupt enable
2
1
read-write
M2M
memory to memory mode
14
1
read-write
MEMINC
memory increment mode
7
1
read-write
MSZ
memory size
10
2
read-write
PERIINC
peripheral increment mode
6
1
read-write
PERISZ
peripheral size
8
2
read-write
PRI
channel priority level
12
2
read-write
CFG5
CFG5
channel 5 channel configuration
0x58
32
read-write
n
0x0
0x0
CHEN
channel enable
0
1
read-write
CINTEN
transfer complete interrupt enable
1
1
read-write
CIR
circular mode
5
1
read-write
DIR
data transfer direction
4
1
read-write
EINTEN
transfer error interrupt enable
3
1
read-write
HINTEN
half transfer interrupt enable
2
1
read-write
M2M
memory to memory mode
14
1
read-write
MEMINC
memory increment mode
7
1
read-write
MSZ
memory size
10
2
read-write
PERIINC
peripheral increment mode
6
1
read-write
PERISZ
peripheral size
8
2
read-write
PRI
channel priority level
12
2
read-write
INTCLR
INTCLR
clear interrupt status
0x4
32
write-only
n
0x0
0x0
CINTFCLR1
channel1 transfer complete flag clear
1
1
write-only
CINTFCLR2
channel2 transfer complete flag clear
5
1
write-only
CINTFCLR3
channel3 transfer complete flag clear
9
1
write-only
CINTFCLR4
channel4 transfer complete flag clear
13
1
write-only
CINTFCLR5
channel5 transfer complete flag clear
17
1
write-only
EINTFCLR1
channel 1 transfer error flag clear
3
1
write-only
EINTFCLR2
channel 2 transfer error flag clear
7
1
write-only
EINTFCLR3
channel 3 transfer error flag clear
11
1
write-only
EINTFCLR4
channel 4 transfer error flag clear
15
1
write-only
EINTFCLR5
channel 5 transfer error flag clear
19
1
write-only
GINTFCLR1
channel1 global interrupt flag clear
0
1
write-only
GINTFCLR2
channel2 global interrupt flag clear
4
1
write-only
GINTFCLR3
channel3 global interrupt flag clear
8
1
write-only
GINTFCLR4
channel4 global interrupt flag clear
12
1
write-only
GINTFCLR5
channel5 global interrupt flag clear
16
1
write-only
HINTFCLR1
channel 1 half transfer flag clear
2
1
write-only
HINTFCLR2
channel 2 half transfer flag clear
6
1
write-only
HINTFCLR3
channel 3 half transfer flag clear
10
1
write-only
HINTFCLR4
channel 4 half transfer flag clear
14
1
write-only
HINTFCLR5
channel 5 half transfer flag clear
18
1
write-only
INTSTAT
INTSTAT
interrupt status
0x0
32
read-only
n
0x0
0x0
CINTF1
channel1 transfer complete flag
1
1
read-only
CINTF2
channel2 transfer complete flag
5
1
read-only
CINTF3
channel3 transfer complete flag
9
1
read-only
CINTF4
channel4 transfer complete flag
13
1
read-only
CINTF5
channel5 transfer complete flag
17
1
read-only
EINTF1
channel 1 transfer error flag
3
1
read-only
EINTF2
channel 2 transfer error flag
7
1
read-only
EINTF3
channel 3 transfer error flag
11
1
read-only
EINTF4
channel 4 transfer error flag
15
1
read-only
EINTF5
channel 5 transfer error flag
19
1
read-only
GINTF1
channel1 global interrupt flag
0
1
read-only
GINTF2
channel2 global interrupt flag
4
1
read-only
GINTF3
channel3 global interrupt flag
8
1
read-only
GINTF4
channel4 global interrupt flag
12
1
read-only
GINTF5
channel5 global interrupt flag
16
1
read-only
HINTF1
channel 1 half transfer flag
2
1
read-only
HINTF2
channel 2 half transfer flag
6
1
read-only
HINTF3
channel 3 half transfer flag
10
1
read-only
HINTF4
channel 4 half transfer flag
14
1
read-only
HINTF5
channel 5 half transfer flag
18
1
read-only
LEN1
LEN1
channel 1 transfer length
0xC
32
read-write
n
0x0
0x0
LEN
channel 1 number of data to transfer
0
16
read-write
LEN2
LEN2
channel 2 transfer length
0x20
32
read-write
n
0x0
0x0
LEN
channel 2 number of data to transfer
0
16
read-write
LEN3
LEN3
channel 3 transfer length
0x34
32
read-write
n
0x0
0x0
LEN
channel 3 number of data to transfer
0
16
read-write
LEN4
LEN4
channel 4 transfer length
0x48
32
read-write
n
0x0
0x0
LEN
channel 4 number of data to transfer
0
16
read-write
LEN5
LEN5
channel 5 transfer length
0x5C
32
read-write
n
0x0
0x0
LEN
channel 5 number of data to transfer
0
16
read-write
MEMADDR1
MEMADDR1
channel 1 memory address
0x14
32
read-write
n
0x0
0x0
ADDR
channel 1 memory address
0
32
read-write
MEMADDR2
MEMADDR2
channel 2 memory address
0x28
32
read-write
n
0x0
0x0
ADDR
channel 2 memory address
0
32
read-write
MEMADDR3
MEMADDR3
channel 3 memory address
0x3C
32
read-write
n
0x0
0x0
ADDR
channel 3 memory address
0
32
read-write
MEMADDR4
MEMADDR4
channel 4 memory address
0x50
32
read-write
n
0x0
0x0
ADDR
channel 4 memory address
0
32
read-write
MEMADDR5
MEMADDR5
channel 5 memory address
0x64
32
read-write
n
0x0
0x0
ADDR
channel 5 memory address
0
32
read-write
PERIADDR1
PERIADDR1
channel 1 peripheral address
0x10
32
read-write
n
0x0
0x0
ADDR
channel 1 peripheral address
0
32
read-write
PERIADDR2
PERIADDR2
channel 2 peripheral address
0x24
32
read-write
n
0x0
0x0
ADDR
channel 2 peripheral address
0
32
read-write
PERIADDR3
PERIADDR3
channel 3 peripheral address
0x38
32
read-write
n
0x0
0x0
ADDR
channel 3 peripheral address
0
32
read-write
PERIADDR4
PERIADDR4
channel 4 peripheral address
0x4C
32
read-write
n
0x0
0x0
ADDR
channel 4 peripheral address
0
32
read-write
PERIADDR5
PERIADDR5
channel 5 peripheral address
0x60
32
read-write
n
0x0
0x0
ADDR
channel 5 peripheral address
0
32
read-write
EFC
Embedded Flash Controller
EFC
0x0
0x0
0x400
registers
n
EFC
EFC interrupt
3
ADDR
ADDR
page address register
0x14
32
read-write
n
0x0
0x0
ADDR
Set by software to indicate the chosen page to erase
0
32
read-write
CFG
CFG
EFC configuration register
0x0
32
read-write
n
0x0
0x0
PRFEN
This bit enables the prefetch
4
1
read-write
PRFSTAT
Prefetch buffer status 0: not Prefetch 1: Prefetch has occurred
5
1
read-only
WAITCYCLE
The value of this bit specifies if extra wait-state is necessary to read the eflash.
0
3
read-write
CTL
CTL
EFC control register
0x10
32
read-write
n
0x0
0x0
ENDINTEN
End of operation interrupt enable
12
1
read-write
ERRINTEN
Error interrupt enable
10
1
read-write
LOCK
Write to 1 only. When it is set, it indicates that the EFC_CTL is locked. This bit is reset by hardware after detecting the unlock sequence. In the event of unsuccessful unlock operation
7
1
read-write
MER
Mass erase chosen 0: not chose main memory mass erase operation 1: chose main memory mass erase operation
2
1
read-write
OPTBER
Option byte erase chosen 0: not chose option bytes erase operation 1: chose option bytes erase operation
5
1
read-write
OPTBLDEN
Setting this bit, the software requests the reloading of Option byte and generate a system reset.
13
1
read-write
OPTBPRG
Option byte programming chosen 0: not chose option bytes program operation 1: chose option bytes program operation
4
1
read-write
OPTBWEN
When set, the option byte can be programmed. This bit is set on writing the correct key sequence to the EFC_OPTBKEY register. This bit can be reset by software
9
1
read-write
PER
Page erase chosen 0: not chose main memory page erase operation 1: chose main memory page erase operation
1
1
read-write
PRG
eflash programming chosen 0: not chose main memory program operation 1: chose main memory program operation
0
1
read-write
START
This bit triggers an erase operation when set. This bit is set only by software and reset when the BSY bit is reset
6
1
read-write
CTLKEY
CTLKEY
Control register key
0x4
32
write-only
n
0x0
0x0
CTLKEY
Control register key With a sequence of two write operations (the first one with 0x45670123 and the second one with 0xCDEF89AB), it is possible to unlock the EFC_CTL register.
0
32
write-only
OPTBKEY
OPTBKEY
OPTBWEN bit key
0x8
32
write-only
n
0x0
0x0
OPTBKEY
OPTBWEN bit key With a sequence of two write operations (the first one with 0x45670123 and the second one with 0xCDEF89AB), it is possible to unlock the OPTBWEN bit.
0
32
write-only
OPTBSTAT
OPTBSTAT
option bytes status register
0x1C
32
read-only
n
0x0
0x0
DATA0
User data byte 0
16
8
read-only
DATA1
User data byte 1
24
8
read-only
nBOOT1
Together with the BOOT0 signal, it selects the device boot mode
12
1
read-only
nRSTSTB
Power management reset chosen when enter standby mode 0: Reset generated when entering Standby mode. 1: No reset generated.
10
1
read-only
nRSTSTP
Power management reset chosen when enter stop mode 0: Reset generated when entering Stop mode 1: No reset generated
9
1
read-only
OPTBERR
Option byte error 0: not option bytes mismatch error 1: option bytes mismatch error occurred
0
1
read-only
PROTLVL
Read protection level status 00: Read protection level 0 is enabled 01: Read protection level 1 is enabled 11: Read protection level 2 is enabled
1
2
read-only
SRAMPRTYCHK
RAM parity check selection 0: RAM parity check enabled 1: RAM parity check disabled
14
1
read-only
SWFWDT
Software watchdog selection 0: Hardware watchdog 1: Software watchdog
8
1
read-only
VDDAMONTR
VDDA power supply supervisor selection 0: VDDA power supply supervisor disabled 1: VDDA power supply supervisor enabled
13
1
read-only
STAT
STAT
EFC status register
0xC
32
read-write
n
0x0
0x0
BSY
Operation in progress flag 0: no operation is in progress 1: erase/program operation is in progress
0
1
read-only
ENDF
End of program/erase 0: not end of program/erase 1: end of program/erase has occurred
5
1
read-write
PRGERR
Set by hardware when an address to be programed is not an erased value 0: no program error 1: program error occurred
2
1
read-write
WPROTERR
Set by hardware when an address to be programmed or erased is write-protected. 0: no write-protected error 1: write-protected error occurred
4
1
read-write
WPROTSTAT
WPROTSTAT
write protect status register
0x20
32
read-only
n
0x0
0x0
WPROT
Write protection
0
8
read-only
FWDT
Free watchdog
FWDT
0x0
0x0
0x400
registers
n
DIV
DIV
Prescale register
0x4
32
read-write
n
0x0
0x0
DIV
Prescale divider
0
3
read-write
KEY
KEY
Key register
0x0
32
write-only
n
0x0
0x0
KEY
watchdog key
0
16
write-only
RLD
RLD
Reload register
0x8
32
read-write
n
0x0
0x0
RLD
Watchdog counter reload value
0
12
read-write
STAT
STAT
Status register
0xC
32
read-only
n
0x0
0x0
DIVU
Prescale value update
0
1
read-only
RU
Counter reload value update
1
1
read-only
WU
Counter window value update
2
1
read-only
WIN
WIN
Window register
0x10
32
read-write
n
0x0
0x0
WIN
Counter window value
0
12
read-write
GPIOA
General-purpose input/output Group A
GPIOA
0x0
0x0
0x400
registers
n
AFSEL0
AFSEL0
Alternate function selection register 0
0x20
32
read-write
n
0x0
0x0
SEL0
select Alternate function for PIN 0
0
4
read-write
SEL1
select Alternate function for PIN 1
4
4
read-write
SEL2
select Alternate function for PIN 2
8
4
read-write
SEL3
select Alternate function for PIN 3
12
4
read-write
SEL4
select Alternate function for PIN 4
16
4
read-write
SEL5
select Alternate function for PIN 5
20
4
read-write
SEL6
select Alternate function for PIN 6
24
4
read-write
SEL7
select Alternate function for PIN 7
28
4
read-write
AFSEL1
AFSEL1
Alternate function selection register 1
0x24
32
read-write
n
0x0
0x0
SEL10
select Alternate function for PIN 10
8
4
read-write
SEL11
select Alternate function for PIN 11
12
4
read-write
SEL12
select Alternate function for PIN 12
16
4
read-write
SEL13
select Alternate function for PIN 13
20
4
read-write
SEL14
select Alternate function for PIN 14
24
4
read-write
SEL15
select Alternate function for PIN 15
28
4
read-write
SEL8
select Alternate function for PIN 8
0
4
read-write
SEL9
select Alternate function for PIN 9
4
4
read-write
BWCLR
BWCLR
reset the corresponding output data
0x28
32
write-only
n
0x0
0x0
BC0
reset the output data of PIN 0
0
1
write-only
BC1
reset the output data of PIN 1
1
1
write-only
BC10
reset the output data of PIN 10
10
1
write-only
BC11
reset the output data of PIN 11
11
1
write-only
BC12
reset the output data of PIN 12
12
1
write-only
BC13
reset the output data of PIN 13
13
1
write-only
BC14
reset the output data of PIN 14
14
1
write-only
BC15
reset the output data of PIN 15
15
1
write-only
BC2
reset the output data of PIN 2
2
1
write-only
BC3
reset the output data of PIN 3
3
1
write-only
BC4
reset the output data of PIN 4
4
1
write-only
BC5
reset the output data of PIN 5
5
1
write-only
BC6
reset the output data of PIN 6
6
1
write-only
BC7
reset the output data of PIN 7
7
1
write-only
BC8
reset the output data of PIN 8
8
1
write-only
BC9
reset the output data of PIN 9
9
1
write-only
BWSET
BWSET
set the corresponding output data bits
0x18
32
write-only
n
0x0
0x0
BS0
set the output data of PIN 0
0
1
write-only
BS1
set the output data of PIN 1
1
1
write-only
BS10
set the output data of PIN 10
10
1
write-only
BS11
set the output data of PIN 11
11
1
write-only
BS12
set the output data of PIN 12
12
1
write-only
BS13
set the output data of PIN 13
13
1
write-only
BS14
set the output data of PIN 14
14
1
write-only
BS15
set the output data of PIN 15
15
1
write-only
BS2
set the output data of PIN 2
2
1
write-only
BS3
set the output data of PIN 3
3
1
write-only
BS4
set the output data of PIN 4
4
1
write-only
BS5
set the output data of PIN 5
5
1
write-only
BS6
set the output data of PIN 6
6
1
write-only
BS7
set the output data of PIN 7
7
1
write-only
BS8
set the output data of PIN 8
8
1
write-only
BS9
set the output data of PIN 9
9
1
write-only
IN
IN
Port input data bits
0x10
32
read-only
n
0x0
0x0
I0
input data of PIN 0
0
1
read-only
I1
input data of PIN 1
1
1
read-only
I10
input data of PIN 10
10
1
read-only
I11
input data of PIN 11
11
1
read-only
I12
input data of PIN 12
12
1
read-only
I13
input data of PIN 13
13
1
read-only
I14
input data of PIN 14
14
1
read-only
I15
input data of PIN 15
15
1
read-only
I2
input data of PIN 2
2
1
read-only
I3
input data of PIN 3
3
1
read-only
I4
input data of PIN 4
4
1
read-only
I5
input data of PIN 5
5
1
read-only
I6
input data of PIN 6
6
1
read-only
I7
input data of PIN 7
7
1
read-only
I8
input data of PIN 8
8
1
read-only
I9
input data of PIN 9
9
1
read-only
LOCK
LOCK
Freeze the corresponding bits in the configuration registers(MODSEL, PPOD, OSPD, PUPD, AFSEL0 and AFSEL1)
0x1C
32
read-write
n
0x0
0x0
LK0
lock the PIN 0
0
1
read-write
LK1
lock the PIN 1
1
1
read-write
LK10
lock the PIN 10
10
1
read-write
LK11
lock the PIN 11
11
1
read-write
LK12
lock the PIN 12
12
1
read-write
LK13
lock the PIN 13
13
1
read-write
LK14
lock the PIN 14
14
1
read-write
LK15
lock the PIN 15
15
1
read-write
LK2
lock the PIN 2
2
1
read-write
LK3
lock the PIN 3
3
1
read-write
LK4
lock the PIN 4
4
1
read-write
LK5
lock the PIN 5
5
1
read-write
LK6
lock the PIN 6
6
1
read-write
LK7
lock the PIN 7
7
1
read-write
LK8
lock the PIN 8
8
1
read-write
LK9
lock the PIN 9
9
1
read-write
LKK
lock status
16
1
read-write
MODSEL
MODSEL
Configure the I/O mode
0x0
32
read-write
n
0x0
0x0
MOD0
Configure the I/O mode of PIN 0
0
2
read-write
MOD1
Configure the I/O mode of PIN 1
2
2
read-write
MOD10
Configure the I/O mode of PIN 10
20
2
read-write
MOD11
Configure the I/O mode of PIN 11
22
2
read-write
MOD12
Configure the I/O mode of PIN 12
24
2
read-write
MOD13
Configure the I/O mode of PIN 13
26
2
read-write
MOD14
Configure the I/O mode of PIN 14
28
2
read-write
MOD15
Configure the I/O mode of PIN 15
30
2
read-write
MOD2
Configure the I/O mode of PIN 2
4
2
read-write
MOD3
Configure the I/O mode of PIN 3
6
2
read-write
MOD4
Configure the I/O mode of PIN 4
8
2
read-write
MOD5
Configure the I/O mode of PIN 5
10
2
read-write
MOD6
Configure the I/O mode of PIN 6
12
2
read-write
MOD7
Configure the I/O mode of PIN 7
14
2
read-write
MOD8
Configure the I/O mode of PIN 8
16
2
read-write
MOD9
Configure the I/O mode of PIN 9
18
2
read-write
OSPD
OSPD
Configure the I/O output speed
0x8
32
read-write
n
0x0
0x0
OSPD0
Configure the I/O output speed of PIN 0
0
2
read-write
OSPD1
Configure the I/O output speed of PIN 1
2
2
read-write
OSPD10
Configure the I/O output speed of PIN 10
20
2
read-write
OSPD11
Configure the I/O output speed of PIN 11
22
2
read-write
OSPD12
Configure the I/O output speed of PIN 12
24
2
read-write
OSPD13
Configure the I/O output speed of PIN 13
26
2
read-write
OSPD14
Configure the I/O output speed of PIN 14
28
2
read-write
OSPD15
Configure the I/O output speed of PIN 15
30
2
read-write
OSPD2
Configure the I/O output speed of PIN 2
4
2
read-write
OSPD3
Configure the I/O output speed of PIN 3
6
2
read-write
OSPD4
Configure the I/O output speed of PIN 4
8
2
read-write
OSPD5
Configure the I/O output speed of PIN 5
10
2
read-write
OSPD6
Configure the I/O output speed of PIN 6
12
2
read-write
OSPD7
Configure the I/O output speed of PIN 7
14
2
read-write
OSPD8
Configure the I/O output speed of PIN 8
16
2
read-write
OSPD9
Configure the I/O output speed of PIN 9
18
2
read-write
OUT
OUT
Port output data bits
0x14
32
read-write
n
0x0
0x0
O0
output data of PIN 0
0
1
read-write
O1
output data of PIN 1
1
1
read-write
O10
output data of PIN 10
10
1
read-write
O11
output data of PIN 11
11
1
read-write
O12
output data of PIN 12
12
1
read-write
O13
output data of PIN 13
13
1
read-write
O14
output data of PIN 14
14
1
read-write
O15
output data of PIN 15
15
1
read-write
O2
output data of PIN 2
2
1
read-write
O3
output data of PIN 3
3
1
read-write
O4
output data of PIN 4
4
1
read-write
O5
output data of PIN 5
5
1
read-write
O6
output data of PIN 6
6
1
read-write
O7
output data of PIN 7
7
1
read-write
O8
output data of PIN 8
8
1
read-write
O9
output data of PIN 9
9
1
read-write
PPOD
PPOD
Configure the I/O output type of the corresponding pins
0x4
32
read-write
n
0x0
0x0
PO0
Configure the I/O output type of PIN 0
0
1
read-write
PO1
Configure the I/O output type of PIN 1
1
1
read-write
PO10
Configure the I/O output type of PIN 10
10
1
read-write
PO11
Configure the I/O output type of PIN 11
11
1
read-write
PO12
Configure the I/O output type of PIN 12
12
1
read-write
PO13
Configure the I/O output type of PIN 13
13
1
read-write
PO14
Configure the I/O output type of PIN 14
14
1
read-write
PO15
Configure the I/O output type of PIN 15
15
1
read-write
PO2
Configure the I/O output type of PIN 2
2
1
read-write
PO3
Configure the I/O output type of PIN 3
3
1
read-write
PO4
Configure the I/O output type of PIN 4
4
1
read-write
PO5
Configure the I/O output type of PIN 5
5
1
read-write
PO6
Configure the I/O output type of PIN 6
6
1
read-write
PO7
Configure the I/O output type of PIN 7
7
1
read-write
PO8
Configure the I/O output type of PIN 8
8
1
read-write
PO9
Configure the I/O output type of PIN 9
9
1
read-write
PUPD
PUPD
Configure the I/O pull-up or pull-down
0xC
32
read-write
n
0x0
0x0
PUPD0
Configure the I/O pull-up or pull-down of PIN 0
0
2
read-write
PUPD1
Configure the I/O pull-up or pull-down of PIN 1
2
2
read-write
PUPD10
Configure the I/O pull-up or pull-down of PIN 10
20
2
read-write
PUPD11
Configure the I/O pull-up or pull-down of PIN 11
22
2
read-write
PUPD12
Configure the I/O pull-up or pull-down of PIN 12
24
2
read-write
PUPD13
Configure the I/O pull-up or pull-down of PIN 13
26
2
read-write
PUPD14
Configure the I/O pull-up or pull-down of PIN 14
28
2
read-write
PUPD15
Configure the I/O pull-up or pull-down of PIN 15
30
2
read-write
PUPD2
Configure the I/O pull-up or pull-down of PIN 2
4
2
read-write
PUPD3
Configure the I/O pull-up or pull-down of PIN 3
6
2
read-write
PUPD4
Configure the I/O pull-up or pull-down of PIN 4
8
2
read-write
PUPD5
Configure the I/O pull-up or pull-down of PIN 5
10
2
read-write
PUPD6
Configure the I/O pull-up or pull-down of PIN 6
12
2
read-write
PUPD7
Configure the I/O pull-up or pull-down of PIN 7
14
2
read-write
PUPD8
Configure the I/O pull-up or pull-down of PIN 8
16
2
read-write
PUPD9
Configure the I/O pull-up or pull-down of PIN 9
18
2
read-write
GPIOB
General-purpose input/output Group B
GPIOB
0x0
0x0
0x400
registers
n
AFSEL0
AFSEL0
Alternate function selection register 0
0x20
32
read-write
n
0x0
0x0
SEL0
select Alternate function for PIN 0
0
4
read-write
SEL1
select Alternate function for PIN 1
4
4
read-write
SEL2
select Alternate function for PIN 2
8
4
read-write
SEL3
select Alternate function for PIN 3
12
4
read-write
SEL4
select Alternate function for PIN 4
16
4
read-write
SEL5
select Alternate function for PIN 5
20
4
read-write
SEL6
select Alternate function for PIN 6
24
4
read-write
SEL7
select Alternate function for PIN 7
28
4
read-write
AFSEL1
AFSEL1
Alternate function selection register 1
0x24
32
read-write
n
0x0
0x0
SEL10
select Alternate function for PIN 10
8
4
read-write
SEL11
select Alternate function for PIN 11
12
4
read-write
SEL12
select Alternate function for PIN 12
16
4
read-write
SEL13
select Alternate function for PIN 13
20
4
read-write
SEL14
select Alternate function for PIN 14
24
4
read-write
SEL15
select Alternate function for PIN 15
28
4
read-write
SEL8
select Alternate function for PIN 8
0
4
read-write
SEL9
select Alternate function for PIN 9
4
4
read-write
BWCLR
BWCLR
reset the corresponding output data
0x28
32
write-only
n
0x0
0x0
BC0
reset the output data of PIN 0
0
1
write-only
BC1
reset the output data of PIN 1
1
1
write-only
BC10
reset the output data of PIN 10
10
1
write-only
BC11
reset the output data of PIN 11
11
1
write-only
BC12
reset the output data of PIN 12
12
1
write-only
BC13
reset the output data of PIN 13
13
1
write-only
BC14
reset the output data of PIN 14
14
1
write-only
BC15
reset the output data of PIN 15
15
1
write-only
BC2
reset the output data of PIN 2
2
1
write-only
BC3
reset the output data of PIN 3
3
1
write-only
BC4
reset the output data of PIN 4
4
1
write-only
BC5
reset the output data of PIN 5
5
1
write-only
BC6
reset the output data of PIN 6
6
1
write-only
BC7
reset the output data of PIN 7
7
1
write-only
BC8
reset the output data of PIN 8
8
1
write-only
BC9
reset the output data of PIN 9
9
1
write-only
BWSET
BWSET
set the corresponding output data bits
0x18
32
write-only
n
0x0
0x0
BS0
set the output data of PIN 0
0
1
write-only
BS1
set the output data of PIN 1
1
1
write-only
BS10
set the output data of PIN 10
10
1
write-only
BS11
set the output data of PIN 11
11
1
write-only
BS12
set the output data of PIN 12
12
1
write-only
BS13
set the output data of PIN 13
13
1
write-only
BS14
set the output data of PIN 14
14
1
write-only
BS15
set the output data of PIN 15
15
1
write-only
BS2
set the output data of PIN 2
2
1
write-only
BS3
set the output data of PIN 3
3
1
write-only
BS4
set the output data of PIN 4
4
1
write-only
BS5
set the output data of PIN 5
5
1
write-only
BS6
set the output data of PIN 6
6
1
write-only
BS7
set the output data of PIN 7
7
1
write-only
BS8
set the output data of PIN 8
8
1
write-only
BS9
set the output data of PIN 9
9
1
write-only
IN
IN
Port input data bits
0x10
32
read-only
n
0x0
0x0
I0
input data of PIN 0
0
1
read-only
I1
input data of PIN 1
1
1
read-only
I10
input data of PIN 10
10
1
read-only
I11
input data of PIN 11
11
1
read-only
I12
input data of PIN 12
12
1
read-only
I13
input data of PIN 13
13
1
read-only
I14
input data of PIN 14
14
1
read-only
I15
input data of PIN 15
15
1
read-only
I2
input data of PIN 2
2
1
read-only
I3
input data of PIN 3
3
1
read-only
I4
input data of PIN 4
4
1
read-only
I5
input data of PIN 5
5
1
read-only
I6
input data of PIN 6
6
1
read-only
I7
input data of PIN 7
7
1
read-only
I8
input data of PIN 8
8
1
read-only
I9
input data of PIN 9
9
1
read-only
LOCK
LOCK
Freeze the corresponding bits in the configuration registers(MODSEL, PPOD, OSPD, PUPD, AFSEL0 and AFSEL1)
0x1C
32
read-write
n
0x0
0x0
LK0
lock the PIN 0
0
1
read-write
LK1
lock the PIN 1
1
1
read-write
LK10
lock the PIN 10
10
1
read-write
LK11
lock the PIN 11
11
1
read-write
LK12
lock the PIN 12
12
1
read-write
LK13
lock the PIN 13
13
1
read-write
LK14
lock the PIN 14
14
1
read-write
LK15
lock the PIN 15
15
1
read-write
LK2
lock the PIN 2
2
1
read-write
LK3
lock the PIN 3
3
1
read-write
LK4
lock the PIN 4
4
1
read-write
LK5
lock the PIN 5
5
1
read-write
LK6
lock the PIN 6
6
1
read-write
LK7
lock the PIN 7
7
1
read-write
LK8
lock the PIN 8
8
1
read-write
LK9
lock the PIN 9
9
1
read-write
LKK
lock status
16
1
read-write
MODSEL
MODSEL
Configure the I/O mode
0x0
32
read-write
n
0x0
0x0
MOD0
configure the I/O mode of PIN 0
0
2
read-write
MOD1
configure the I/O mode of PIN 1
2
2
read-write
MOD10
configure the I/O mode of PIN 10
20
2
read-write
MOD11
configure the I/O mode of PIN 11
22
2
read-write
MOD12
configure the I/O mode of PIN 12
24
2
read-write
MOD13
configure the I/O mode of PIN 13
26
2
read-write
MOD14
configure the I/O mode of PIN 14
28
2
read-write
MOD15
configure the I/O mode of PIN 15
30
2
read-write
MOD2
configure the I/O mode of PIN 2
4
2
read-write
MOD3
configure the I/O mode of PIN 3
6
2
read-write
MOD4
configure the I/O mode of PIN 4
8
2
read-write
MOD5
configure the I/O mode of PIN 5
10
2
read-write
MOD6
configure the I/O mode of PIN 6
12
2
read-write
MOD7
configure the I/O mode of PIN 7
14
2
read-write
MOD8
configure the I/O mode of PIN 8
16
2
read-write
MOD9
configure the I/O mode of PIN 9
18
2
read-write
OSPD
OSPD
Configure the I/O output speed
0x8
32
read-write
n
0x0
0x0
OSPD0
Configure the I/O output speed of PIN 0
0
2
read-write
OSPD1
Configure the I/O output speed of PIN 1
2
2
read-write
OSPD10
Configure the I/O output speed of PIN 10
20
2
read-write
OSPD11
Configure the I/O output speed of PIN 11
22
2
read-write
OSPD12
Configure the I/O output speed of PIN 12
24
2
read-write
OSPD13
Configure the I/O output speed of PIN 13
26
2
read-write
OSPD14
Configure the I/O output speed of PIN 14
28
2
read-write
OSPD15
Configure the I/O output speed of PIN 15
30
2
read-write
OSPD2
Configure the I/O output speed of PIN 2
4
2
read-write
OSPD3
Configure the I/O output speed of PIN 3
6
2
read-write
OSPD4
Configure the I/O output speed of PIN 4
8
2
read-write
OSPD5
Configure the I/O output speed of PIN 5
10
2
read-write
OSPD6
Configure the I/O output speed of PIN 6
12
2
read-write
OSPD7
Configure the I/O output speed of PIN 7
14
2
read-write
OSPD8
Configure the I/O output speed of PIN 8
16
2
read-write
OSPD9
Configure the I/O output speed of PIN 9
18
2
read-write
OUT
OUT
Port output data bits
0x14
32
read-write
n
0x0
0x0
O0
output data of PIN 0
0
1
read-write
O1
output data of PIN 1
1
1
read-write
O10
output data of PIN 10
10
1
read-write
O11
output data of PIN 11
11
1
read-write
O12
output data of PIN 12
12
1
read-write
O13
output data of PIN 13
13
1
read-write
O14
output data of PIN 14
14
1
read-write
O15
output data of PIN 15
15
1
read-write
O2
output data of PIN 2
2
1
read-write
O3
output data of PIN 3
3
1
read-write
O4
output data of PIN 4
4
1
read-write
O5
output data of PIN 5
5
1
read-write
O6
output data of PIN 6
6
1
read-write
O7
output data of PIN 7
7
1
read-write
O8
output data of PIN 8
8
1
read-write
O9
output data of PIN 9
9
1
read-write
PPOD
PPOD
Configure the I/O output type of the corresponding pins
0x4
32
read-write
n
0x0
0x0
PO0
Configure the I/O output type of PIN 0
0
1
read-write
PO1
Configure the I/O output type of PIN 1
1
1
read-write
PO10
Configure the I/O output type of PIN 10
10
1
read-write
PO11
Configure the I/O output type of PIN 11
11
1
read-write
PO12
Configure the I/O output type of PIN 12
12
1
read-write
PO13
Configure the I/O output type of PIN 13
13
1
read-write
PO14
Configure the I/O output type of PIN 14
14
1
read-write
PO15
Configure the I/O output type of PIN 15
15
1
read-write
PO2
Configure the I/O output type of PIN 2
2
1
read-write
PO3
Configure the I/O output type of PIN 3
3
1
read-write
PO4
Configure the I/O output type of PIN 4
4
1
read-write
PO5
Configure the I/O output type of PIN 5
5
1
read-write
PO6
Configure the I/O output type of PIN 6
6
1
read-write
PO7
Configure the I/O output type of PIN 7
7
1
read-write
PO8
Configure the I/O output type of PIN 8
8
1
read-write
PO9
Configure the I/O output type of PIN 9
9
1
read-write
PUPD
PUPD
configure the I/O pull-up or pull-down
0xC
32
read-write
n
0x0
0x0
PUPD0
configure the I/O pull-up or pull-down of PIN 0
0
2
read-write
PUPD1
configure the I/O pull-up or pull-down of PIN 1
2
2
read-write
PUPD10
configure the I/O pull-up or pull-down of PIN 10
20
2
read-write
PUPD11
configure the I/O pull-up or pull-down of PIN 11
22
2
read-write
PUPD12
configure the I/O pull-up or pull-down of PIN 12
24
2
read-write
PUPD13
configure the I/O pull-up or pull-down of PIN 13
26
2
read-write
PUPD14
configure the I/O pull-up or pull-down of PIN 14
28
2
read-write
PUPD15
configure the I/O pull-up or pull-down of PIN 15
30
2
read-write
PUPD2
configure the I/O pull-up or pull-down of PIN 2
4
2
read-write
PUPD3
configure the I/O pull-up or pull-down of PIN 3
6
2
read-write
PUPD4
configure the I/O pull-up or pull-down of PIN 4
8
2
read-write
PUPD5
configure the I/O pull-up or pull-down of PIN 5
10
2
read-write
PUPD6
configure the I/O pull-up or pull-down of PIN 6
12
2
read-write
PUPD7
configure the I/O pull-up or pull-down of PIN 7
14
2
read-write
PUPD8
configure the I/O pull-up or pull-down of PIN 8
16
2
read-write
PUPD9
configure the I/O pull-up or pull-down of PIN 9
18
2
read-write
GPIOC
General-purpose input/output Group C
GPIOC
0x0
0x0
0x400
registers
n
BWCLR
BWCLR
reset the corresponding output data
0x28
32
write-only
n
0x0
0x0
BC0
reset the output data of PIN 0
0
1
write-only
BC1
reset the output data of PIN 1
1
1
write-only
BC10
reset the output data of PIN 10
10
1
write-only
BC11
reset the output data of PIN 11
11
1
write-only
BC12
reset the output data of PIN 12
12
1
write-only
BC13
reset the output data of PIN 13
13
1
write-only
BC14
reset the output data of PIN 14
14
1
write-only
BC15
reset the output data of PIN 15
15
1
write-only
BC2
reset the output data of PIN 2
2
1
write-only
BC3
reset the output data of PIN 3
3
1
write-only
BC4
reset the output data of PIN 4
4
1
write-only
BC5
reset the output data of PIN 5
5
1
write-only
BC6
reset the output data of PIN 6
6
1
write-only
BC7
reset the output data of PIN 7
7
1
write-only
BC8
reset the output data of PIN 8
8
1
write-only
BC9
reset the output data of PIN 9
9
1
write-only
BWSET
BWSET
set the corresponding output data bits
0x18
32
write-only
n
0x0
0x0
BS0
set the output data of PIN 0
0
1
write-only
BS1
set the output data of PIN 1
1
1
write-only
BS10
set the output data of PIN 10
10
1
write-only
BS11
set the output data of PIN 11
11
1
write-only
BS12
set the output data of PIN 12
12
1
write-only
BS13
set the output data of PIN 13
13
1
write-only
BS14
set the output data of PIN 14
14
1
write-only
BS15
set the output data of PIN 15
15
1
write-only
BS2
set the output data of PIN 2
2
1
write-only
BS3
set the output data of PIN 3
3
1
write-only
BS4
set the output data of PIN 4
4
1
write-only
BS5
set the output data of PIN 5
5
1
write-only
BS6
set the output data of PIN 6
6
1
write-only
BS7
set the output data of PIN 7
7
1
write-only
BS8
set the output data of PIN 8
8
1
write-only
BS9
set the output data of PIN 9
9
1
write-only
IN
IN
Port input data bits
0x10
32
read-only
n
0x0
0x0
I0
input data of PIN 0
0
1
read-only
I1
input data of PIN 1
1
1
read-only
I10
input data of PIN 10
10
1
read-only
I11
input data of PIN 11
11
1
read-only
I12
input data of PIN 12
12
1
read-only
I13
input data of PIN 13
13
1
read-only
I14
input data of PIN 14
14
1
read-only
I15
input data of PIN 15
15
1
read-only
I2
input data of PIN 2
2
1
read-only
I3
input data of PIN 3
3
1
read-only
I4
input data of PIN 4
4
1
read-only
I5
input data of PIN 5
5
1
read-only
I6
input data of PIN 6
6
1
read-only
I7
input data of PIN 7
7
1
read-only
I8
input data of PIN 8
8
1
read-only
I9
input data of PIN 9
9
1
read-only
MODSEL
MODSEL
Configure the I/O mode
0x0
32
read-write
n
0x0
0x0
MOD0
configure the I/O mode of PIN 0
0
2
read-write
MOD1
configure the I/O mode of PIN 1
2
2
read-write
MOD10
configure the I/O mode of PIN 10
20
2
read-write
MOD11
configure the I/O mode of PIN 11
22
2
read-write
MOD12
configure the I/O mode of PIN 12
24
2
read-write
MOD13
configure the I/O mode of PIN 13
26
2
read-write
MOD14
configure the I/O mode of PIN 14
28
2
read-write
MOD15
configure the I/O mode of PIN 15
30
2
read-write
MOD2
configure the I/O mode of PIN 2
4
2
read-write
MOD3
configure the I/O mode of PIN 3
6
2
read-write
MOD4
configure the I/O mode of PIN 4
8
2
read-write
MOD5
configure the I/O mode of PIN 5
10
2
read-write
MOD6
configure the I/O mode of PIN 6
12
2
read-write
MOD7
configure the I/O mode of PIN 7
14
2
read-write
MOD8
configure the I/O mode of PIN 8
16
2
read-write
MOD9
configure the I/O mode of PIN 9
18
2
read-write
OSPD
OSPD
Configure the I/O output speed
0x8
32
read-write
n
0x0
0x0
OSPD0
Configure the I/O output speed of PIN 0
0
2
read-write
OSPD1
Configure the I/O output speed of PIN 1
2
2
read-write
OSPD10
Configure the I/O output speed of PIN 10
20
2
read-write
OSPD11
Configure the I/O output speed of PIN 11
22
2
read-write
OSPD12
Configure the I/O output speed of PIN 12
24
2
read-write
OSPD13
Configure the I/O output speed of PIN 13
26
2
read-write
OSPD14
Configure the I/O output speed of PIN 14
28
2
read-write
OSPD15
Configure the I/O output speed of PIN 15
30
2
read-write
OSPD2
Configure the I/O output speed of PIN 2
4
2
read-write
OSPD3
Configure the I/O output speed of PIN 3
6
2
read-write
OSPD4
Configure the I/O output speed of PIN 4
8
2
read-write
OSPD5
Configure the I/O output speed of PIN 5
10
2
read-write
OSPD6
Configure the I/O output speed of PIN 6
12
2
read-write
OSPD7
Configure the I/O output speed of PIN 7
14
2
read-write
OSPD8
Configure the I/O output speed of PIN 8
16
2
read-write
OSPD9
Configure the I/O output speed of PIN 9
18
2
read-write
OUT
OUT
Port output data bits
0x14
32
read-write
n
0x0
0x0
O0
output data of PIN 0
0
1
read-write
O1
output data of PIN 1
1
1
read-write
O10
output data of PIN 10
10
1
read-write
O11
output data of PIN 11
11
1
read-write
O12
output data of PIN 12
12
1
read-write
O13
output data of PIN 13
13
1
read-write
O14
output data of PIN 14
14
1
read-write
O15
output data of PIN 15
15
1
read-write
O2
output data of PIN 2
2
1
read-write
O3
output data of PIN 3
3
1
read-write
O4
output data of PIN 4
4
1
read-write
O5
output data of PIN 5
5
1
read-write
O6
output data of PIN 6
6
1
read-write
O7
output data of PIN 7
7
1
read-write
O8
output data of PIN 8
8
1
read-write
O9
output data of PIN 9
9
1
read-write
PPOD
PPOD
Configure the I/O output type of the corresponding pins
0x4
32
read-write
n
0x0
0x0
PO0
Configure the I/O output type of PIN 0
0
1
read-write
PO1
Configure the I/O output type of PIN 1
1
1
read-write
PO10
Configure the I/O output type of PIN 10
10
1
read-write
PO11
Configure the I/O output type of PIN 11
11
1
read-write
PO12
Configure the I/O output type of PIN 12
12
1
read-write
PO13
Configure the I/O output type of PIN 13
13
1
read-write
PO14
Configure the I/O output type of PIN 14
14
1
read-write
PO15
Configure the I/O output type of PIN 15
15
1
read-write
PO2
Configure the I/O output type of PIN 2
2
1
read-write
PO3
Configure the I/O output type of PIN 3
3
1
read-write
PO4
Configure the I/O output type of PIN 4
4
1
read-write
PO5
Configure the I/O output type of PIN 5
5
1
read-write
PO6
Configure the I/O output type of PIN 6
6
1
read-write
PO7
Configure the I/O output type of PIN 7
7
1
read-write
PO8
Configure the I/O output type of PIN 8
8
1
read-write
PO9
Configure the I/O output type of PIN 9
9
1
read-write
PUPD
PUPD
configure the I/O pull-up or pull-down
0xC
32
read-write
n
0x0
0x0
PUPD0
configure the I/O pull-up or pull-down of PIN 0
0
2
read-write
PUPD1
configure the I/O pull-up or pull-down of PIN 1
2
2
read-write
PUPD10
configure the I/O pull-up or pull-down of PIN 10
20
2
read-write
PUPD11
configure the I/O pull-up or pull-down of PIN 11
22
2
read-write
PUPD12
configure the I/O pull-up or pull-down of PIN 12
24
2
read-write
PUPD13
configure the I/O pull-up or pull-down of PIN 13
26
2
read-write
PUPD14
configure the I/O pull-up or pull-down of PIN 14
28
2
read-write
PUPD15
configure the I/O pull-up or pull-down of PIN 15
30
2
read-write
PUPD2
configure the I/O pull-up or pull-down of PIN 2
4
2
read-write
PUPD3
configure the I/O pull-up or pull-down of PIN 3
6
2
read-write
PUPD4
configure the I/O pull-up or pull-down of PIN 4
8
2
read-write
PUPD5
configure the I/O pull-up or pull-down of PIN 5
10
2
read-write
PUPD6
configure the I/O pull-up or pull-down of PIN 6
12
2
read-write
PUPD7
configure the I/O pull-up or pull-down of PIN 7
14
2
read-write
PUPD8
configure the I/O pull-up or pull-down of PIN 8
16
2
read-write
PUPD9
configure the I/O pull-up or pull-down of PIN 9
18
2
read-write
GPIOF
General-purpose input/output Group F
GPIOF
0x0
0x0
0x400
registers
n
BWCLR
BWCLR
reset the corresponding output data
0x28
32
write-only
n
0x0
0x0
BC0
reset the output data of PIN 0
0
1
write-only
BC1
reset the output data of PIN 1
1
1
write-only
BC10
reset the output data of PIN 10
10
1
write-only
BC11
reset the output data of PIN 11
11
1
write-only
BC12
reset the output data of PIN 12
12
1
write-only
BC13
reset the output data of PIN 13
13
1
write-only
BC14
reset the output data of PIN 14
14
1
write-only
BC15
reset the output data of PIN 15
15
1
write-only
BC2
reset the output data of PIN 2
2
1
write-only
BC3
reset the output data of PIN 3
3
1
write-only
BC4
reset the output data of PIN 4
4
1
write-only
BC5
reset the output data of PIN 5
5
1
write-only
BC6
reset the output data of PIN 6
6
1
write-only
BC7
reset the output data of PIN 7
7
1
write-only
BC8
reset the output data of PIN 8
8
1
write-only
BC9
reset the output data of PIN 9
9
1
write-only
BWSET
BWSET
set the corresponding output data bits
0x18
32
write-only
n
0x0
0x0
BS0
set the output data of PIN 0
0
1
write-only
BS1
set the output data of PIN 1
1
1
write-only
BS10
set the output data of PIN 10
10
1
write-only
BS11
set the output data of PIN 11
11
1
write-only
BS12
set the output data of PIN 12
12
1
write-only
BS13
set the output data of PIN 13
13
1
write-only
BS14
set the output data of PIN 14
14
1
write-only
BS15
set the output data of PIN 15
15
1
write-only
BS2
set the output data of PIN 2
2
1
write-only
BS3
set the output data of PIN 3
3
1
write-only
BS4
set the output data of PIN 4
4
1
write-only
BS5
set the output data of PIN 5
5
1
write-only
BS6
set the output data of PIN 6
6
1
write-only
BS7
set the output data of PIN 7
7
1
write-only
BS8
set the output data of PIN 8
8
1
write-only
BS9
set the output data of PIN 9
9
1
write-only
IN
IN
Port input data bits
0x10
32
read-only
n
0x0
0x0
I0
input data of PIN 0
0
1
read-only
I1
input data of PIN 1
1
1
read-only
I10
input data of PIN 10
10
1
read-only
I11
input data of PIN 11
11
1
read-only
I12
input data of PIN 12
12
1
read-only
I13
input data of PIN 13
13
1
read-only
I14
input data of PIN 14
14
1
read-only
I15
input data of PIN 15
15
1
read-only
I2
input data of PIN 2
2
1
read-only
I3
input data of PIN 3
3
1
read-only
I4
input data of PIN 4
4
1
read-only
I5
input data of PIN 5
5
1
read-only
I6
input data of PIN 6
6
1
read-only
I7
input data of PIN 7
7
1
read-only
I8
input data of PIN 8
8
1
read-only
I9
input data of PIN 9
9
1
read-only
MODSEL
MODSEL
Configure the I/O mode
0x0
32
read-write
n
0x0
0x0
MOD0
configure the I/O mode of PIN 0
0
2
read-write
MOD1
configure the I/O mode of PIN 1
2
2
read-write
MOD10
configure the I/O mode of PIN 10
20
2
read-write
MOD11
configure the I/O mode of PIN 11
22
2
read-write
MOD12
configure the I/O mode of PIN 12
24
2
read-write
MOD13
configure the I/O mode of PIN 13
26
2
read-write
MOD14
configure the I/O mode of PIN 14
28
2
read-write
MOD15
configure the I/O mode of PIN 15
30
2
read-write
MOD2
configure the I/O mode of PIN 2
4
2
read-write
MOD3
configure the I/O mode of PIN 3
6
2
read-write
MOD4
configure the I/O mode of PIN 4
8
2
read-write
MOD5
configure the I/O mode of PIN 5
10
2
read-write
MOD6
configure the I/O mode of PIN 6
12
2
read-write
MOD7
configure the I/O mode of PIN 7
14
2
read-write
MOD8
configure the I/O mode of PIN 8
16
2
read-write
MOD9
configure the I/O mode of PIN 9
18
2
read-write
OSPD
OSPD
Configure the I/O output speed
0x8
32
read-write
n
0x0
0x0
OSPD0
Configure the I/O output speed of PIN 0
0
2
read-write
OSPD1
Configure the I/O output speed of PIN 1
2
2
read-write
OSPD10
Configure the I/O output speed of PIN 10
20
2
read-write
OSPD11
Configure the I/O output speed of PIN 11
22
2
read-write
OSPD12
Configure the I/O output speed of PIN 12
24
2
read-write
OSPD13
Configure the I/O output speed of PIN 13
26
2
read-write
OSPD14
Configure the I/O output speed of PIN 14
28
2
read-write
OSPD15
Configure the I/O output speed of PIN 15
30
2
read-write
OSPD2
Configure the I/O output speed of PIN 2
4
2
read-write
OSPD3
Configure the I/O output speed of PIN 3
6
2
read-write
OSPD4
Configure the I/O output speed of PIN 4
8
2
read-write
OSPD5
Configure the I/O output speed of PIN 5
10
2
read-write
OSPD6
Configure the I/O output speed of PIN 6
12
2
read-write
OSPD7
Configure the I/O output speed of PIN 7
14
2
read-write
OSPD8
Configure the I/O output speed of PIN 8
16
2
read-write
OSPD9
Configure the I/O output speed of PIN 9
18
2
read-write
OUT
OUT
Port output data bits
0x14
32
read-write
n
0x0
0x0
O0
output data of PIN 0
0
1
read-write
O1
output data of PIN 1
1
1
read-write
O10
output data of PIN 10
10
1
read-write
O11
output data of PIN 11
11
1
read-write
O12
output data of PIN 12
12
1
read-write
O13
output data of PIN 13
13
1
read-write
O14
output data of PIN 14
14
1
read-write
O15
output data of PIN 15
15
1
read-write
O2
output data of PIN 2
2
1
read-write
O3
output data of PIN 3
3
1
read-write
O4
output data of PIN 4
4
1
read-write
O5
output data of PIN 5
5
1
read-write
O6
output data of PIN 6
6
1
read-write
O7
output data of PIN 7
7
1
read-write
O8
output data of PIN 8
8
1
read-write
O9
output data of PIN 9
9
1
read-write
PPOD
PPOD
Configure the I/O output type of the corresponding pins
0x4
32
read-write
n
0x0
0x0
PO0
Configure the I/O output type of PIN 0
0
1
read-write
PO1
Configure the I/O output type of PIN 1
1
1
read-write
PO10
Configure the I/O output type of PIN 10
10
1
read-write
PO11
Configure the I/O output type of PIN 11
11
1
read-write
PO12
Configure the I/O output type of PIN 12
12
1
read-write
PO13
Configure the I/O output type of PIN 13
13
1
read-write
PO14
Configure the I/O output type of PIN 14
14
1
read-write
PO15
Configure the I/O output type of PIN 15
15
1
read-write
PO2
Configure the I/O output type of PIN 2
2
1
read-write
PO3
Configure the I/O output type of PIN 3
3
1
read-write
PO4
Configure the I/O output type of PIN 4
4
1
read-write
PO5
Configure the I/O output type of PIN 5
5
1
read-write
PO6
Configure the I/O output type of PIN 6
6
1
read-write
PO7
Configure the I/O output type of PIN 7
7
1
read-write
PO8
Configure the I/O output type of PIN 8
8
1
read-write
PO9
Configure the I/O output type of PIN 9
9
1
read-write
PUPD
PUPD
configure the I/O pull-up or pull-down
0xC
32
read-write
n
0x0
0x0
PUPD0
configure the I/O pull-up or pull-down of PIN 0
0
2
read-write
PUPD1
configure the I/O pull-up or pull-down of PIN 1
2
2
read-write
PUPD10
configure the I/O pull-up or pull-down of PIN 10
20
2
read-write
PUPD11
configure the I/O pull-up or pull-down of PIN 11
22
2
read-write
PUPD12
configure the I/O pull-up or pull-down of PIN 12
24
2
read-write
PUPD13
configure the I/O pull-up or pull-down of PIN 13
26
2
read-write
PUPD14
configure the I/O pull-up or pull-down of PIN 14
28
2
read-write
PUPD15
configure the I/O pull-up or pull-down of PIN 15
30
2
read-write
PUPD2
configure the I/O pull-up or pull-down of PIN 2
4
2
read-write
PUPD3
configure the I/O pull-up or pull-down of PIN 3
6
2
read-write
PUPD4
configure the I/O pull-up or pull-down of PIN 4
8
2
read-write
PUPD5
configure the I/O pull-up or pull-down of PIN 5
10
2
read-write
PUPD6
configure the I/O pull-up or pull-down of PIN 6
12
2
read-write
PUPD7
configure the I/O pull-up or pull-down of PIN 7
14
2
read-write
PUPD8
configure the I/O pull-up or pull-down of PIN 8
16
2
read-write
PUPD9
configure the I/O pull-up or pull-down of PIN 9
18
2
read-write
I2C
Inter-integrated circuit
I2C
0x0
0x0
0x400
registers
n
I2C1
I2C1 interrupt
23
ADDR0
ADDR0
Device address 0 configuration
0x8
32
read-write
n
0x0
0x0
DADDR0
Device address 0
0
10
read-write
DADDR0EN
Device Address 0 enable
15
1
read-write
DADDR0MOD
Device Address 0 10-bit mode
10
1
read-write
ADDR1
ADDR1
Device address 1 configuration
0xC
32
read-write
n
0x0
0x0
DADDR1
Device address 1
1
7
read-write
DADDR1EN
Device address 1 enable
15
1
read-write
DADDR1MSK
Device address 1 masks
8
3
read-write
CTL0
CTL0
i2c control register 0
0x0
32
read-write
n
0x0
0x0
ADDRINTEN
Address match interrupt enable(slave only)
3
1
read-write
ANFDIS
Analog noise filter disable
12
1
read-write
CLKSTHDIS
Clock stretching disable
17
1
read-write
DMARXEN
DMA reception requests enable
15
1
read-write
DMATXEN
DMA transmission requests enable
14
1
read-write
DNFCFG
Digital noise filter configuration
8
4
read-write
ERRINTEN
Error interrupts enable
7
1
read-write
GCEN
General call enable
19
1
read-write
I2CEN
I2C enable
0
1
read-write
NACKINTEN
Not acknowledge received interrupt enable
4
1
read-write
PECEN
PEC enable
23
1
read-write
RXINTEN
RX interrupt enable
2
1
read-write
SBCTL
Slave byte control
16
1
read-write
SMBALTEN
SMBus alert enable
22
1
read-write
SMBDADDREN
SMBus device default address enable
21
1
read-write
SMBHADDREN
SMBus Host address enable
20
1
read-write
STOPINTEN
STOP detection interrupt enable
5
1
read-write
TCINTEN
Transfer complete interrupt enable
6
1
read-write
TXINTEN
TX interrupt enable
1
1
read-write
WAKEUPEN
Wakeup from stop mode enable
18
1
read-write
CTL1
CTL1
i2c control register 1
0x4
32
read-write
n
0x0
0x0
ADDRMOD
Addressing mode (master mode)
11
1
read-write
AUTOSTOPEN
Automatic stop mode enable (master mode)
25
1
read-write
HEAD10REN
10-bit address header only read direction enable (master receiver mode)
12
1
read-write
LEN
Length of bytes
16
8
read-write
NACKGEN
NACK generation (slave mode)
15
1
read-write
PECTRANS
Packet error checking transfer
26
1
read-write
RLDEN
Reload enable
24
1
read-write
SADDR
Slave address bit
0
10
read-write
STARTGEN
Start generation
13
1
read-write
STOPGEN
Stop generation (master mode)
14
1
read-write
TRANSDIR
Transfer direction (master mode)
10
1
read-write
INTCLR
INTCLR
i2c interrupt flag clear
0x1C
32
write-only
n
0x0
0x0
ADDRFCLR
Address matched flag clear
3
1
write-only
ARLOFCLR
Arbitration Lost flag clear
9
1
write-only
BERRFCLR
Bus error flag clear
8
1
write-only
NACKFCLR
Not Acknowledge flag clear
4
1
write-only
OVRFCLR
Overrun/Underrun flag clear
10
1
write-only
PECERRFCLR
PEC Error flag clear
11
1
write-only
SMBALTFCLR
SMBUS alert flag clear
13
1
write-only
SMBTOFCLR
SMBUS timeout detection flag clear
12
1
write-only
STOPFCLR
Stop detection flag clear
5
1
write-only
INTSTAT
INTSTAT
i2c interrupt and states
0x18
32
read-write
n
0x0
0x0
ADDRF
Address matched flag (slave mode)
3
1
read-only
ARLOF
Arbitration lost flag
9
1
read-only
BERRF
Bus error flag
8
1
read-only
BSYF
Bus busy flag
15
1
read-only
NACKF
Not Acknowledge received flag
4
1
read-only
OVRF
Overrun/Underrun flag (slave mode)
10
1
read-only
PECERRF
PEC Error in reception flag
11
1
read-only
RECADDR
Received address (Slave mode)
17
7
read-only
RXNEF
Receive data register not empty flag (receivers)
2
1
read-only
SMBALTF
SMBus alert flag
13
1
read-only
SMBTOF
Timeout or tLOW detection flag
12
1
read-only
STOPF
Stop detection flag
5
1
read-only
TCF
Transfer Complete flag (master mode)
6
1
read-only
TCRF
Transfer Complete Reload flag
7
1
read-only
TRANSDIR
Transfer direction (Slave mode)
16
1
read-only
TXEF
Transmit data register empty flag (transmitters)
0
1
read-write
TXINTSTAT
Transmit interrupt status (transmitters)
1
1
read-write
PECDATA
PECDATA
Packet error checking data
0x20
32
read-only
n
0x0
0x0
PECDATA
Packet error checking data
0
8
read-only
RXDATA
RXDATA
8-bit receive data
0x24
32
read-only
n
0x0
0x0
RXDATA
8-bit receive data Data byte received from the I2C bus
0
8
read-only
SMBTO
SMBTO
SMBUS timeout configuration
0x14
32
read-write
n
0x0
0x0
EXTTO
Extend clock timeout
16
12
read-write
EXTTOEN
Extended clock timeout enable
31
1
read-write
IDLETOEN
Idle clock timeout detection
12
1
read-write
TO
Bus Timeout
0
12
read-write
TOEN
Clock timeout enable
15
1
read-write
TIMING
TIMING
I2C timing configuration
0x10
32
read-write
n
0x0
0x0
DIV
I2C CLK divider
28
4
read-write
SCLDEL
Data setup time
20
4
read-write
SCLHPRD
SCL high period (master mode)
8
8
read-write
SCLLPRD
SCL low period (master mode)
0
8
read-write
SDADEL
Data hold time
16
4
read-write
TXDATA
TXDATA
8-bit transmit data
0x28
32
read-write
n
0x0
0x0
TXDATA
8-bit transmit data
0
8
read-write
INT
interrupts
INT
0x0
0x0
0x400
registers
n
EXTI0_1
EXTI Line[1:0] interrupts
5
EXTI2_3
EXTI Line[3:2] interrupts
6
EXTI4_15
EXTI Line[15:4] interrupts
7
EVTMSK
EVTMSK
event mask
0x4
32
read-write
n
0x0
0x0
EVTMSK0
event mask on signal line 0
0
1
read-write
EVTMSK1
event mask on signal line 1
1
1
read-write
EVTMSK10
event mask on signal line 10
10
1
read-write
EVTMSK11
event mask on signal line 11
11
1
read-write
EVTMSK12
event mask on signal line 12
12
1
read-write
EVTMSK13
event mask on signal line 13
13
1
read-write
EVTMSK14
event mask on signal line 14
14
1
read-write
EVTMSK15
event mask on signal line 15
15
1
read-write
EVTMSK17
event mask on signal line 17
17
1
read-write
EVTMSK19
event mask on signal line 19
19
1
read-write
EVTMSK2
event mask on signal line 2
2
1
read-write
EVTMSK23
event mask on signal line 23
23
1
read-write
EVTMSK24
event mask on signal line 24
24
1
read-write
EVTMSK25
event mask on signal line 25
25
1
read-write
EVTMSK3
event mask on signal line 3
3
1
read-write
EVTMSK4
event mask on signal line 4
4
1
read-write
EVTMSK5
event mask on signal line 5
5
1
read-write
EVTMSK6
event mask on signal line 6
6
1
read-write
EVTMSK7
event mask on signal line 7
7
1
read-write
EVTMSK8
event mask on signal line 8
8
1
read-write
EVTMSK9
event mask on signal line 9
9
1
read-write
FDEN
FDEN
falling detection enable
0xC
32
read-write
n
0x0
0x0
FDEN0
falling detection enable on signal line 0
0
1
read-write
FDEN1
falling detection enable on signal line 1
1
1
read-write
FDEN10
falling detection enable on signal line 10
10
1
read-write
FDEN11
falling detection enable on signal line 11
11
1
read-write
FDEN12
falling detection enable on signal line 12
12
1
read-write
FDEN13
falling detection enable on signal line 13
13
1
read-write
FDEN14
falling detection enable on signal line 14
14
1
read-write
FDEN15
falling detection enable on signal line 15
15
1
read-write
FDEN17
falling detection enable on signal line 17
17
1
read-write
FDEN19
falling detection enable on signal line 19
19
1
read-write
FDEN2
falling detection enable on signal line 2
2
1
read-write
FDEN3
falling detection enable on signal line 3
3
1
read-write
FDEN4
falling detection enable on signal line 4
4
1
read-write
FDEN5
falling detection enable on signal line 5
5
1
read-write
FDEN6
falling detection enable on signal line 6
6
1
read-write
FDEN7
falling detection enable on signal line 7
7
1
read-write
FDEN8
falling detection enable on signal line 8
8
1
read-write
FDEN9
falling detection enable on signal line 9
9
1
read-write
INTMSK
INTMSK
interrupt mask
0x0
32
read-write
n
0x0
0x0
INTMSK0
interrupt mask on signal line 0
0
1
read-write
INTMSK1
interrupt mask on signal line 1
1
1
read-write
INTMSK10
interrupt mask on signal line 10
10
1
read-write
INTMSK11
interrupt mask on signal line 11
11
1
read-write
INTMSK12
interrupt mask on signal line 12
12
1
read-write
INTMSK13
interrupt mask on signal line 13
13
1
read-write
INTMSK14
interrupt mask on signal line 14
14
1
read-write
INTMSK15
interrupt mask on signal line 15
15
1
read-write
INTMSK17
interrupt mask on signal line 17
17
1
read-write
INTMSK19
interrupt mask on signal line 19
19
1
read-write
INTMSK2
interrupt mask on signal line 2
2
1
read-write
INTMSK23
interrupt mask on signal line 23
23
1
read-write
INTMSK24
interrupt mask on signal line 24
24
1
read-write
INTMSK25
interrupt mask on signal line 25
25
1
read-write
INTMSK3
interrupt mask on signal line 3
3
1
read-write
INTMSK4
interrupt mask on signal line 4
4
1
read-write
INTMSK5
interrupt mask on signal line 5
5
1
read-write
INTMSK6
interrupt mask on signal line 6
6
1
read-write
INTMSK7
interrupt mask on signal line 7
7
1
read-write
INTMSK8
interrupt mask on signal line 8
8
1
read-write
INTMSK9
interrupt mask on signal line 9
9
1
read-write
PREQ
PREQ
interrupt flag
0x14
32
read-write
n
0x0
0x0
INTF0
interrupt flag on signal line 0
0
1
read-write
INTF1
interrupt flag on signal line 1
1
1
read-write
INTF10
interrupt flag on signal line 10
10
1
read-write
INTF11
interrupt flag on signal line 11
11
1
read-write
INTF12
interrupt flag on signal line 12
12
1
read-write
INTF13
interrupt flag on signal line 13
13
1
read-write
INTF14
interrupt flag on signal line 14
14
1
read-write
INTF15
interrupt flag on signal line 15
15
1
read-write
INTF17
interrupt flag on signal line 17
17
1
read-write
INTF19
interrupt flag on signal line 19
19
1
read-write
INTF2
interrupt flag on signal line 2
2
1
read-write
INTF3
interrupt flag on signal line 3
3
1
read-write
INTF4
interrupt flag on signal line 4
4
1
read-write
INTF5
interrupt flag on signal line 5
5
1
read-write
INTF6
interrupt flag on signal line 6
6
1
read-write
INTF7
interrupt flag on signal line 7
7
1
read-write
INTF8
interrupt flag on signal line 8
8
1
read-write
INTF9
interrupt flag on signal line 9
9
1
read-write
RDEN
RDEN
rising detection enable
0x8
32
read-write
n
0x0
0x0
RDEN0
rising detection enable on signal line 0
0
1
read-write
RDEN1
rising detection enable on signal line 1
1
1
read-write
RDEN10
rising detection enable on signal line 10
10
1
read-write
RDEN11
rising detection enable on signal line 11
11
1
read-write
RDEN12
rising detection enable on signal line 12
12
1
read-write
RDEN13
rising detection enable on signal line 13
13
1
read-write
RDEN14
rising detection enable on signal line 14
14
1
read-write
RDEN15
rising detection enable on signal line 15
15
1
read-write
RDEN17
rising detection enable on signal line 17
17
1
read-write
RDEN19
rising detection enable on signal line 19
19
1
read-write
RDEN2
rising detection enable on signal line 2
2
1
read-write
RDEN3
rising detection enable on signal line 3
3
1
read-write
RDEN4
rising detection enable on signal line 4
4
1
read-write
RDEN5
rising detection enable on signal line 5
5
1
read-write
RDEN6
rising detection enable on signal line 6
6
1
read-write
RDEN7
rising detection enable on signal line 7
7
1
read-write
RDEN8
rising detection enable on signal line 8
8
1
read-write
RDEN9
rising detection enable on signal line 9
9
1
read-write
SWINTEVT
SWINTEVT
Software interrupt event trigger
0x10
32
read-write
n
0x0
0x0
SWINTEVT0
Software interrupt event trigger on signal line 0
0
1
read-write
SWINTEVT1
Software interrupt event trigger on signal line 1
1
1
read-write
SWINTEVT10
Software interrupt event trigger on signal line 10
10
1
read-write
SWINTEVT11
Software interrupt event trigger on signal line 11
11
1
read-write
SWINTEVT12
Software interrupt event trigger on signal line 12
12
1
read-write
SWINTEVT13
Software interrupt event trigger on signal line 13
13
1
read-write
SWINTEVT14
Software interrupt event trigger on signal line 14
14
1
read-write
SWINTEVT15
Software interrupt event trigger on signal line 15
15
1
read-write
SWINTEVT17
Software interrupt event trigger on signal line 17
17
1
read-write
SWINTEVT19
Software interrupt event trigger on signal line 19
19
1
read-write
SWINTEVT2
Software interrupt event trigger on signal line 2
2
1
read-write
SWINTEVT3
Software interrupt event trigger on signal line 3
3
1
read-write
SWINTEVT4
Software interrupt event trigger on signal line 4
4
1
read-write
SWINTEVT5
Software interrupt event trigger on signal line 5
5
1
read-write
SWINTEVT6
Software interrupt event trigger on signal line 6
6
1
read-write
SWINTEVT7
Software interrupt event trigger on signal line 7
7
1
read-write
SWINTEVT8
Software interrupt event trigger on signal line 8
8
1
read-write
SWINTEVT9
Software interrupt event trigger on signal line 9
9
1
read-write
PMU
Power Management Unit
PMU
0x0
0x0
0x400
registers
n
CTL
CTL
PMU Control Register
0x0
32
read-write
n
0x0
0x0
CLRSTBF
Clear standby flag
3
1
read-write
CLRWUF
Clear wakeup flag
2
1
read-write
DISPROT
Disable RTC write protection
8
1
read-write
RGLP
Regulator in Low-power deep-sleep mode
0
1
read-write
STBEN
Standby enable
1
1
read-write
STAT
STAT
PMU State Register
0x4
32
read-write
n
0x0
0x0
STBF
Standby flag
1
1
read-only
WU0EN
Enable WKUP pin 0
8
1
read-write
WU1EN
Enable WKUP pin 1
9
1
read-write
WUF
Wakeup flag
0
1
read-only
RCC
Reset and Clock Control
RCC
0x0
0x0
0x400
registers
n
RCC
RCC interrupt
4
AHBPERIEN
AHBPERIEN
AHB peripheral clock enable
0x14
32
read-write
n
0x0
0x0
CRCEN
CRC clock enable
6
1
read-write
DMAEN
DMA clock enable
0
1
read-write
EFCEN
FLASH clock enable
4
1
read-write
GPIOAEN
GPIO PORT A clock enable
17
1
read-write
GPIOBEN
GPIO PORT B clock enable
18
1
read-write
GPIOCEN
GPIO PORT C clock enable
19
1
read-write
GPIOFEN
GPIO PORT F clock enable
22
1
read-write
SRAMEN
SRAM clock enable
2
1
read-write
AHBPERIRST
AHBPERIRST
AHB peripheral reset
0x28
32
read-write
n
0x0
0x0
GPIOARST
GPIO PORT A reset
17
1
read-write
GPIOBRST
GPIO PORT B reset
18
1
read-write
GPIOCRST
GPIO PORT C reset
19
1
read-write
GPIOFRST
GPIO PORT F reset
22
1
read-write
TSCRST
touch reset if touch exist , this bit shall reset both ADC and touch otherwise, this bit is inaccessible
31
1
read-write
APB1PERIEN
APB1PERIEN
APB peripheral clock enable 1
0x1C
32
read-write
n
0x0
0x0
I2C1EN
I2C1 clock enable
21
1
read-write
PMUEN
PMU clock enable
28
1
read-write
TIMERG1EN
TIMERG1 clock enable
1
1
read-write
TIMERG2EN
TIMERG2 clock enable
8
1
read-write
WWDTEN
WWDT clock enable
11
1
read-write
APB1RST
APB1RST
APB peripheral reset register 1
0x10
32
read-write
n
0x0
0x0
I2C1RST
I2C1 reset
21
1
read-write
PMURST
PMU reset
28
1
read-write
TIMERG1RST
TIMERG1 reset
1
1
read-write
TIMERG2RST
TIMERG2 reset
8
1
read-write
WWDTRST
WWDT reset
11
1
read-write
APB2PERIEN
APB2PERIEN
APB peripheral clock enable 2
0x18
32
read-write
n
0x0
0x0
ADCEN
ADC clock enable
9
1
read-write
DBGEN
DBG clock enable
22
1
read-write
SPI1EN
SPI1 clock enable
12
1
read-write
SYSCFGEN
SYSCFG clock enable
0
1
read-write
TIMERA1EN
TIMERA1 clock enable
11
1
read-write
TIMERG3EN
TIMERG3 clock enable
17
1
read-write
TIMERG4EN
TIMERG4 clock enable
18
1
read-write
USART1EN
USART1 clock enable
14
1
read-write
APB2RST
APB2RST
APB peripheral reset register 2
0xC
32
read-write
n
0x0
0x0
ADCRST
ADC reset
9
1
read-write
DBGRST
debug register reset
22
1
read-write
SPI1RST
SPI1 reset
12
1
read-write
SYSCFGRST
SYSCFG reset
0
1
read-write
TIMERA1RST
TIMERA1 reset
11
1
read-write
TIMERG3RST
TIMERG3 reset
17
1
read-write
TIMERG4RST
TIMERG4 reset
18
1
read-write
USART1RST
USART1 reset
14
1
read-write
CFG0
CFG0
RCC configuration register 0
0x4
32
read-write
n
0x0
0x0
AHBPDIV
AHB clock prescale
4
4
read-write
APBPDIV
APB clock prescale
8
3
read-write
CLKO
microcontroller clock output
24
4
read-write
CLKOPDIV
microcontroller clock output prescale
28
3
read-write
PLLDIVCLKO
PLL clock not divided for MCO
31
1
read-write
PLLHXOSCPDIV
HXOSC clock div for PLL
17
1
read-write
PLLMULT
PLL multiplication factor
18
4
read-write
PLLSRCCLK
PLL CLOCK SOURCE
16
1
read-write
SYSCLKSTAT
system clock source status
2
2
read-only
SYSCLKSW
system clock source
0
2
read-write
CFG1
CFG1
RCC configuration register 1
0x2C
32
read-write
n
0x0
0x0
PLLPDIV
PLL division factor
0
4
read-write
CFG2
CFG2
RCC configuration register 2
0x30
32
read-write
n
0x0
0x0
I2C1SEL
I2C1 clock source
4
1
read-write
USART1SEL
USART1 clock source
0
2
read-write
CTL0
CTL0
RCC control register 0
0x0
32
read-write
n
0x0
0x0
CLKSECEN
clock security system enable
19
1
read-write
HXOSCBYP
HXOSC clock BYPASS enable
18
1
read-write
HXOSCEN
HXOSC clock ready flag
16
1
read-write
HXOSCRDY
HXOSC clock ready flag
17
1
read-only
PLLEN
PLL clock enable
24
1
read-write
RC8MCAL
RC8M calibration data which are saved in flash
8
8
read-only
RC8MEN
RC8M clock enable
0
1
read-write
RC8MRDY
RC8M clock ready flag
1
1
read-only
RC8MTRIM
RC8M clock trim
3
5
read-write
CTL1
CTL1
RCC control register 1
0x34
32
read-write
n
0x0
0x0
RC14MCAL
RC14M clock calibration
8
8
read-only
RC14MDISADC
disable ADC request for RC14M clock
2
1
read-write
RC14MEN
RC14M clock enable
0
1
read-write
RC14MRDY
RC14M clock stable
1
1
read-only
RC14MTRIM
RC14M clock trimming, which is added to ro_RC14M_cal
3
5
read-write
INTCTL
INTCTL
RCC interrupt control register
0x8
32
read-write
n
0x0
0x0
CLKSECCLR
CLKSEC interrupt flag clear
23
1
write-only
CLKSECF
CSSHXOSC interrupt flag
7
1
read-only
HXOSCRDYCLR
HXOSC ready interrupt flag clear
19
1
write-only
HXOSCRDYF
HXOSC ready interrupt flag
3
1
read-only
HXOSCRDYINTEN
HXOSC ready interrupt flag enable
11
1
read-write
LXOSCRDYCLR
LXOSC ready interrupt flag clear
17
1
write-only
LXOSCRDYF
LXOSC ready interrupt flag
1
1
read-only
LXOSCRDYINTEN
LXOSC ready interrupt flag enable
9
1
read-write
RC14MRDYCLR
RC14M ready interrupt flag clear
21
1
write-only
RC14MRDYF
RC14M ready interrupt flag
5
1
read-only
RC14MRDYINTEN
RC14M ready interrupt flag enable
13
1
read-write
RC40KRDYCLR
RC40K ready interrupt flag clear
16
1
write-only
RC40KRDYF
RC40K ready interrupt flag
0
1
read-only
RC40KRDYINTEN
RC40K interrupt flag enable
8
1
read-write
RC8MRDYCLR
RC8M ready interrupt flag clear
18
1
write-only
RC8MRDYF
RC8M ready interrupt flag
2
1
read-only
RC8MRDYINTEN
RC8M ready interrupt flag enable
10
1
read-write
RTCCTL
RTCCTL
RCC RTC domain control register
0x20
32
read-write
n
0x0
0x0
LXOSCBYP
LXOSC clock bypass enable
2
1
read-write
LXOSCDRV
LXOSC clock drive capability
3
2
read-write
LXOSCEN
LXOSC clock enable
0
1
read-write
LXOSCRDY
LXOSC clock enable
1
1
read-only
RTCEN
RTC clock enable
15
1
read-write
RTCRST
RTC domain software reset
16
1
read-write
RTCSRCSEL
RTC clock source
8
2
read-write
STAT
STAT
RCC status register
0x24
32
read-write
n
0x0
0x0
CLRRSTF
remove reset flag
24
1
write-only
EXPINRSTF
pin reset flag
26
1
read-only
FWDTRSTF
FWDT reset flag
29
1
read-only
LPWRRSTF
low power management reset flag
31
1
read-only
OPTBLDENRSTF
option byte load reset flag
25
1
read-only
PMURSTF
VDD for core power up flag, including POWER ON and STDBY EXIT
23
1
read-only
PORRSTF
POR reset flag
27
1
read-only
RC40KEN
RC40K enable
0
1
read-write
RC40KRDY
LXOSC clock enable
1
1
read-only
SFTRSTF
CPU software reset flag
28
1
read-only
TSCCLKEN
touch clock enable if touch exist , this bit shall enable the clocks of both ADC and touch otherwise, this bit is inaccessible
16
1
read-write
WWDTRSTF
WWDT reset flag
30
1
read-only
RTC
Real Time Clock
RTC
0x0
0x0
0x400
registers
n
RTC
RTC interrupt
2
ALR0
ALR0
alarm 0 register
0x1C
32
read-write
n
0x0
0x0
DATET
Date tens in BCD format.
28
2
read-write
DATEU
Date units or day in BCD format.
24
4
read-write
DMSK
Alarm 0 date mask
31
1
read-write
HMSK
Alarm 0 hours mask
23
1
read-write
HRT
Hour tens in BCD format.
20
2
read-write
HRU
Hour units in BCD format.
16
4
read-write
MMSK
Alarm 0 minutes mask
15
1
read-write
MNT
Minute tens in BCD format.
12
3
read-write
MNU
Minute units in BCD format.
8
4
read-write
PM
AM/PM notation
22
1
read-write
SECT
Second tens in BCD format.
4
3
read-write
SECU
Second units in BCD format.
0
4
read-write
SMSK
Alarm 0 seconds mask
7
1
read-write
WDSEL
Week day selection
30
1
read-write
ALR0SS
ALR0SS
Alarm 0 subsecond
0x44
32
read-write
n
0x0
0x0
SS
Alarm 0 Sub seconds value
0
15
read-write
SSMSK
Mask the most-significant bits starting at this bit
24
4
read-write
CAL
CAL
calibration register
0x3C
32
read-write
n
0x0
0x0
INC
Increase frequency of RTC by 488.5 ppm
15
1
read-write
RED
Calibration reduce
0
9
read-write
WIN16
Use a 16-second calibration cycle period
13
1
read-write
WIN8
Use an 8-second calibration cycle period
14
1
read-write
CTL
CTL
control register
0x8
32
read-write
n
0x0
0x0
ADD1H
Add 1 hour (summer time change)
16
1
write-only
ALR0EN
Alarm 0 enable
8
1
read-write
ALR0INTEN
Alarm 0 interrupt enable
12
1
read-write
BYP
Bypass the shadow registers
5
1
read-write
CALOEN
Calibration output enable
23
1
read-write
CALSEL
Calibration output selection
19
1
read-write
DSBKP
daylight saving Backup
18
1
read-write
HRFMT
Hour format
6
1
read-write
OPOL
Output polarity
20
1
read-write
OSEL
Output selection
21
2
read-write
REFEN
RTC_REFEN reference clock detection enable (50 or 60 Hz)
4
1
read-write
SUB1H
Subtract 1 hour (winter time change)
17
1
write-only
TSEDGE
Time-stamp event active edge
3
1
read-write
TSEN
timestamp enable
11
1
read-write
TSINTEN
Time-stamp interrupt enable
15
1
read-write
DATE
DATE
date of calendar
0x4
32
read-write
n
0x0
0x0
DAYT
Date tens in BCD format
4
2
read-write
DAYU
Date units in BCD format
0
4
read-write
MTHT
Month tens in BCD format
12
1
read-write
MTHU
Month units in BCD format
8
4
read-write
WD
Week day
13
3
read-write
YRT
Year tens in BCD format
20
4
read-write
YRU
Year units in BCD format
16
4
read-write
DIV
DIV
prescale factor
0x10
32
read-write
n
0x0
0x0
DIVASYNC
asynchronous division factor
16
7
read-write
DIVSYNC
synchronous division factor
0
15
read-write
INITSTAT
INITSTAT
initialization and status
0xC
32
read-write
n
0x0
0x0
ALR0F
Alarm 0 flag
8
1
read-write
ALR0WF
Alarm 0 write flag
0
1
read-only
CALPF
calibration pending Flag
16
1
read-only
INIT
Initialization mode
7
1
read-write
INITF
Initialization flag
6
1
read-only
INITSTAT
Initialization status flag
4
1
read-only
SECSHPF
second Shift operation pending
3
1
read-only
SYNCF
shadow Registers synchronization flag
5
1
read-write
TAMP0F
RTC_TAMP0 detection flag
13
1
read-write
TAMP1F
RTC_TAMP1 detection flag
14
1
read-write
TSF
Time-stamp flag
11
1
read-write
TSOVF
Time-stamp overflow flag
12
1
read-write
SECSH
SECSH
second shift
0x2C
32
write-only
n
0x0
0x0
ADD1S
Add one second
31
1
write-only
SUBSS
Subtract a fraction of a second
0
15
write-only
SS
SS
Sub second of calendar
0x28
32
read-only
n
0x0
0x0
SS
Sub second value
0
16
read-only
TAMPCFG
TAMPCFG
tamper and other configuration
0x40
32
read-write
n
0x0
0x0
EN0
RTC_TAMP0 input detection enable
0
1
read-write
EN1
RTC_TAMP1 input detection enable
3
1
read-write
FLT
RTC_TAMPx filter count
11
2
read-write
FREQ
Tamper sampling frequency
8
3
read-write
INTEN
Tamper interrupt enable
2
1
read-write
PC13MOD
PC13 mode
19
1
read-write
PC13VAL
RTC_ALARM output type/PC13 value
18
1
read-write
PC14MOD
PC14 mode
21
1
read-write
PC14VAL
PC14 value
20
1
read-write
PC15MOD
PC15 mode
23
1
read-write
PC15VAL
PC15 value
22
1
read-write
PRCH
RTC_TAMPx precharge duration
13
2
read-write
PUDIS
RTC_TAMPx pull-up disable
15
1
read-write
TRIG0
Active level for RTC_TAMP0 input
1
1
read-write
TRIG1
Active level for RTC_TAMP1 input
4
1
read-write
TS
Activate timestamp on tamper detection event
7
1
read-write
TIME
TIME
time of calendar
0x0
32
read-write
n
0x0
0x0
HRT
Hour tens in BCD format
20
2
read-write
HRU
Hour units in BCD format
16
4
read-write
MNT
Minute tens in BCD format
12
3
read-write
MNU
Minute units in BCD format
8
4
read-write
PM
AM/PM notation or 24-hour format
22
1
read-write
SECT
Second tens in BCD format
4
3
read-write
SECU
Second units in BCD format
0
4
read-write
TSDATE
TSDATE
date of timestamp
0x34
32
read-only
n
0x0
0x0
DAYT
Day tens in BCD format
4
2
read-only
DAYU
Day units in BCD format
0
4
read-only
MTHT
Month tens in BCD format
12
1
read-only
MTHU
Month units in BCD format
8
4
read-only
WD
Week day
13
3
read-only
TSSS
TSSS
Sub second of timestamp
0x38
32
read-only
n
0x0
0x0
SS
Sub second value when timestamp occur
0
16
read-only
TSTIME
TSTIME
time of timestamp
0x30
32
read-only
n
0x0
0x0
HRT
Hour tens in BCD format.
20
2
read-only
HRU
Hour units in BCD format.
16
4
read-only
MNT
Minute tens in BCD format.
12
3
read-only
MNU
Minute units in BCD format.
8
4
read-only
PM
AM/PM notation
22
1
read-only
SECT
Second tens in BCD format
4
3
read-only
SECU
Second units in BCD format
0
4
read-only
WPROT
WPROT
Write protection key
0x24
32
write-only
n
0x0
0x0
WPROTKEY
Write protection key
0
8
write-only
SPI
Serial peripheral interface / inter-IC sound
SPI
0x0
0x0
0x400
registers
n
SPI1
SPI1 interrupt
25
CRCPOL
CRCPOL
SPI CRC polynomial register
0x10
32
read-write
n
0x0
0x0
CRCPOL
CRC polynomial
0
16
read-write
CTL0
CTL0
SPI control register 0
0x0
32
read-write
n
0x0
0x0
BRDIV
Baud rate control
3
3
read-write
CPHA
Clock phase
0
1
read-write
CPOL
Clock polarity
1
1
read-write
CRCEN
Hardware CRC calculation enable
13
1
read-write
CRCLEN
CRC length
11
1
read-write
CRCTRIG
CRC transfer next
12
1
read-write
HFDUPDIR
Output enable in bidirectional mode
14
1
read-write
HFDUPEN
Bidirectional data mode enable
15
1
read-write
INCS
Internal slave select
8
1
read-write
LSBFIRST
Frame format
7
1
read-write
MASTER
Master selection
2
1
read-write
SDUPDIR
Receive only mode enable
10
1
read-write
SPIEN
SPI enable
6
1
read-write
SWCS
Software slave management
9
1
read-write
CTL1
CTL1
SPI control register 1
0x4
32
read-write
n
0x0
0x0
CSOEN
SS output enable
2
1
read-write
CSPEN
NSS pulse management
3
1
read-write
DMARXEN
RX buffer DMA enable
0
1
read-write
DMARXLB
Last DMA transfer for reception
13
1
read-write
DMATXEN
TX buffer DMA enable
1
1
read-write
DMATXLB
Last DMA transfer for transmission
14
1
read-write
ERRINTEN
Error interrupt enable
5
1
read-write
FRMLEN
Data size
8
4
read-write
RXNEINTEN
RX buffer not empty interrupt enable
6
1
read-write
RXTH
FIFO reception threshold
12
1
read-write
TIMOD
Frame format
4
1
read-write
TXEINTEN
TX buffer empty interrupt enable
7
1
read-write
DATA
DATA
SPI data register
0xC
32
read-write
n
0x0
0x0
DATA
Data register
0
16
read-write
I2SCFG
I2SCFG
I2S configuration register
0x1C
32
read-write
n
0x0
0x0
CHLEN
Channel length
0
1
read-write
CLKPOL
Inactive state clock polarity
3
1
read-write
DATALEN
Data length to be transferred
1
2
read-write
I2SCFG
I2S configuration mode
8
2
read-write
I2SEN
I2S enable
10
1
read-write
I2SMOD
I2S mode selection
11
1
read-write
I2SSTD
I2S standard selection
4
2
read-write
PCMSYNC
PCM frame synchronization
7
1
read-write
I2SDIV
I2SDIV
I2S prescale register
0x20
32
read-write
n
0x0
0x0
DIV
I2S linear prescale
0
8
read-write
MCLKEN
Master clock output enable
9
1
read-write
ODD
Odd factor for the prescale
8
1
read-write
RXCRC
RXCRC
SPI RX CRC register
0x14
32
read-only
n
0x0
0x0
RXCRC
RX CRC register
0
16
read-only
STAT
STAT
SPI status register
0x8
32
read-only
n
0x0
0x0
BSYF
Busy flag
7
1
read-only
CHF
Channel side
2
1
read-only
CRCERRF
CRC error flag
4
1
read-only
FRMERRF
Frame Error
8
1
read-only
FRVOL
FIFO reception level
9
2
read-only
FTVOL
FIFO Transmission Level
11
2
read-only
MODERRF
Mode fault
5
1
read-only
OVRF
Overrun flag
6
1
read-only
RXNE
Receive buffer not empty
0
1
read-only
TXE
Transmit buffer empty
1
1
read-only
UDRF
Underrun flag
3
1
read-only
TXCRC
TXCRC
SPI TX CRC register
0x18
32
read-only
n
0x0
0x0
TXCRC
TX CRC register
0
16
read-only
SYSCFG
System configuration controller
SYSCFG
0x0
0x0
0x400
registers
n
CFG0
CFG0
memory configuration, DMA request remap and I/O features control
0x0
32
read-write
n
0x0
0x0
ADCRMPDMA
ADC DMA request remapping
8
1
read-write
I2C1FMPEN
I2C1 FM+ driving capability activation
20
1
read-write
I2CFMPENPA10
I2C PA10 FM+ driving capability activation
23
1
read-write
I2CFMPENPA9
I2C PA9 FM+ driving capability activation
22
1
read-write
I2CFMPENPB6
I2C PB6 FM+ driving capability activation
16
1
read-write
I2CFMPENPB7
I2C PB7 FM+ driving capability activation
17
1
read-write
I2CFMPENPB8
I2C PB8 FM+ driving capability activation
18
1
read-write
I2CFMPENPB9
I2C PB9 FM+ driving capability activation
19
1
read-write
MEMMAPSEL
memory mapping selection
0
2
read-write
TIMERG3RMPDMA
TIMERG3 DMA request remapping
11
1
read-write
TIMERG4RMPDMA
TIMERG4 DMA request remapping
12
1
read-write
USART1RXRMPDMA
USART1 RX DMA request remapping
10
1
read-write
USART1TXRMPDMA
USART1 TX DMA request remapping
9
1
read-write
CFG1
CFG1
error signal route, error flag
0x18
32
read-write
n
0x0
0x0
LOCKUPS
Cortex-M0 LOCKUP signal route
0
1
read-write
OPAMP1EN
OPAMP1 enable
16
1
read-write
OPAMP2EN
OPAMP2 enable
17
1
read-write
SRAMPEF
SRAM parity error flag
8
1
read-write
SRAMPES
SRAM parity error signal route
1
1
read-write
EXTISS0
EXTISS0
EXTI 0-3 source select
0x8
32
read-write
n
0x0
0x0
EXTI0SS
EXTI 0 source select
0
4
read-write
EXTI1SS
EXTI 1 source select
4
4
read-write
EXTI2SS
EXTI 2 source select
8
4
read-write
EXTI3SS
EXTI 3 source select
12
4
read-write
EXTISS1
EXTISS1
EXTI 4-7 source select
0xC
32
read-write
n
0x0
0x0
EXTI4SS
EXTI 4 source select
0
4
read-write
EXTI5SS
EXTI 5 source select
4
4
read-write
EXTI6SS
EXTI 6 source select
8
4
read-write
EXTI7SS
EXTI 7 source select
12
4
read-write
EXTISS2
EXTISS2
EXTI 8-11 source select
0x10
32
read-write
n
0x0
0x0
EXTI10SS
EXTI 10 source select
8
4
read-write
EXTI11SS
EXTI 11 source select
12
4
read-write
EXTI8SS
EXTI 8 source select
0
4
read-write
EXTI9SS
EXTI 9 source select
4
4
read-write
EXTISS3
EXTISS3
EXTI 12-15 source select
0x14
32
read-write
n
0x0
0x0
EXTI12SS
EXTI 12 source select
0
4
read-write
EXTI13SS
EXTI 13 source select
4
4
read-write
EXTI14SS
EXTI 14 source select
8
4
read-write
EXTI15SS
EXTI 15 source select
12
4
read-write
TIMERA1
Advanced Timer 1
TIMERA1
0x0
0x0
0x400
registers
n
TIMERA1_BRK_UP_TRIG_COM
TIMERA1 break, update, trigger and commutation interrupts
13
TIMERA1_C
TIMERA1 capture or compare interrupt
14
CCMP0
CCMP0
capture/compare counter value 0
0x34
32
read-write
n
0x0
0x0
CCMP0
capture/compare counter value 0
0
16
read-write
CCMP1
CCMP1
capture/compare counter value 1
0x38
32
read-write
n
0x0
0x0
CCMP1
capture/compare counter value 1
0
16
read-write
CCMP2
CCMP2
capture/compare counter value 2
0x3C
32
read-write
n
0x0
0x0
CCMP2
capture/compare counter value 2
0
16
read-write
CCMP3
CCMP3
capture/compare counter value 3
0x40
32
read-write
n
0x0
0x0
CCMP3
capture/compare counter value 3
0
16
read-write
CCTL0_input
CCTL0_input
capture/compare control register 0
CCTL0_output
0x18
32
read-write
n
0x0
0x0
ICS0DIV
input capture signal 0 division
2
2
read-write
ICS0FLT
input capture signal 0 filter
4
4
read-write
ICS0SRC
input capture signal 0 source
0
2
read-write
ICS1DIV
input capture signal 1 division
10
2
read-write
ICS1FLT
input capture signal 1 filter
12
4
read-write
ICS1SRC
input capture signal 1 source
8
2
read-write
CCTL0_output
CCTL0_output
capture/compare control register 0
0x18
32
read-write
n
0x0
0x0
ICS0SRC
input capture signal 0 source
0
2
read-write
ICS1SRC
input capture signal 1 source
8
2
read-write
OCS0CLR
output compare signal 0 clear
7
1
read-write
OCS0FMEN
output compare signal 0 Fast Mode enable
2
1
read-write
OCS0MOD
output compare signal 0 mode
4
3
read-write
OCS0PRLDEN
output compare signal 0 preload enable
3
1
read-write
OCS1CLR
output compare signal 1 clear
15
1
read-write
OCS1FMEN
output compare signal 1 Fast Mode enable
10
1
read-write
OCS1MOD
output compare signal 1 mode
12
3
read-write
OCS1PRLDEN
output compare signal 1 preload enable
11
1
read-write
CCTL1_input
CCTL1_input
capture/compare control register 1
CCTL1_output
0x1C
32
read-write
n
0x0
0x0
ICS2DIV
input capture signal 2 division
2
2
read-write
ICS2FLT
input capture signal 2 filter
4
4
read-write
ICS2SRC
input capture signal 2 source
0
2
read-write
ICS3DIV
input capture signal 3division
10
2
read-write
ICS3FLT
input capture signal 3 filter
12
4
read-write
ICS3SRC
input capture signal 3 source
8
2
read-write
CCTL1_output
CCTL1_output
capture/compare control register 1
0x1C
32
read-write
n
0x0
0x0
ICS2SRC
input capture signal 2 source
0
2
read-write
ICS3SRC
input capture signal 3 source
8
2
read-write
OCS2CLR
output compare signal 2 clear
7
1
read-write
OCS2FMEN
output compare signal 2 Fast mode enable
2
1
read-write
OCS2MOD
output compare signal 2 mode
4
3
read-write
OCS2PRLDEN
output compare signal2 preload enable
3
1
read-write
OCS3CLR
output compare signal 3 clear
15
1
read-write
OCS3FMEN
output compare signal 3 Fast Mode enable
10
1
read-write
OCS3MOD
output compare signal 3 mode
12
3
read-write
OCS3PRLDEN
output compare signal 3 preload enable
11
1
read-write
CCTL2
CCTL2
capture/compare control register 2
0x20
32
read-write
n
0x0
0x0
CS0EN
capture/compare signal 0 enable
0
1
read-write
CS0POL
capture/compare signal 0 polarity level
1
1
read-write
CS0REN
capture/compare signal 0 reverse enable
2
1
read-write
CS0RPOL
capture/compare signal 0 reverse polarity level
3
1
read-write
CS1EN
capture/compare signal 1 enable
4
1
read-write
CS1POL
capture/compare signal 1 polarity level
5
1
read-write
CS1REN
capture/compare signal 1 reverse enable
6
1
read-write
CS1RPOL
capture/compare signal 1 reverse polarity level
7
1
read-write
CS2EN
capture/compare signal 2 enable
8
1
read-write
CS2POL
capture/compare signal 2 polarity level
9
1
read-write
CS2REN
capture/compare signal 2 reverse enable
10
1
read-write
CS2RPOL
capture/compare signal 2 reverse polarity level
11
1
read-write
CS3EN
capture/compare signal 3 enable
12
1
read-write
CS3POL
capture/compare signal 3 polarity level
13
1
read-write
CS3RPOL
capture/compare signal 3 reverse polarity level
15
1
read-write
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
ALIGNMOD
align mode
5
2
read-write
CLKDIV
clock division
8
2
read-write
CNTDIR
count direction
4
1
read-write
EN
Counter enable
0
1
read-write
RLDPRLDEN
reload preload enable
7
1
read-write
SGLPLSMOD
single pulse mode
3
1
read-write
UDIS
Update disable
1
1
read-write
USRC
Update source
2
1
read-write
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
CUSRC
capture/compare update source
2
1
read-write
IS0SRC
input signal 0 source
7
1
read-write
OC0IDLRSTAT
output compare 0 idle mode reversed status
9
1
read-write
OC0IDLSTAT
output compare 0 idle mode status
8
1
read-write
OC1IDLRSTAT
output compare 1 idle mode reversed status
11
1
read-write
OC1IDLSTAT
output compare 1 idle mode status
10
1
read-write
OC2IDLRSTAT
output compare 2 idle mode reversed status
13
1
read-write
OC2IDLSTAT
output compare 2 idle mode status
12
1
read-write
OC3IDLSTAT
output compare 3 idle mode status
14
1
read-write
OCDMASRC
output compare DMA source
3
1
read-write
OCPRLDEN
output compare control preload enable
0
1
read-write
TRIGOSRC
trigger out source
4
3
read-write
DATA
DATA
timer' current data
0x24
32
read-write
n
0x0
0x0
DATA
timer data
0
16
read-write
DIV
DIV
timer' divisions
0x28
32
read-write
n
0x0
0x0
DIV
timer divisions
0
16
read-write
DMACFG
DMACFG
DMA configuration register
0x48
32
read-write
n
0x0
0x0
BASEADDR
DMA base address
0
5
read-write
BSTLEN
DMA burst length
8
5
read-write
DMARMP
DMARMP
DMA remap register
0x4C
32
read-write
n
0x0
0x0
RMP
DMA burst remap address
0
16
read-write
EVTSET
EVTSET
event set register
0x14
32
write-only
n
0x0
0x0
BRK
break event set
7
1
write-only
C0
capture/compare 0 event set
1
1
write-only
C1
capture/compare 1 event set
2
1
write-only
C2
capture/compare 2 event set
3
1
write-only
C3
capture/compare 3 event set
4
1
write-only
COM
commutation event set
5
1
write-only
TRIGI
trigger input event set
6
1
write-only
UPDATE
update event set
0
1
write-only
INTDMAEN
INTDMAEN
interrupt/DMA enable register
0xC
32
read-write
n
0x0
0x0
BRKINTEN
break interrupt enable
7
1
read-write
C0DMAEN
capture/compare 0 DMA enable
9
1
read-write
C0INTEN
capture/compare 0 interrupt enable
1
1
read-write
C1DMAEN
capture/compare 1 DMA enable
10
1
read-write
C1INTEN
capture/compare 1 interrupt enable
2
1
read-write
C2DMAEN
capture/compare 2 DMA enable
11
1
read-write
C2INTEN
capture/compare 2 interrupt enable
3
1
read-write
C3DMAEN
capture/compare 3 DMA enable
12
1
read-write
C3INTEN
capture/compare 3 interrupt enable
4
1
read-write
COMDMAEN
commutation DMA enable
13
1
read-write
COMINTEN
commutation interrupt enable
5
1
read-write
TRIGIDMAEN
trigger input DMA enable
14
1
read-write
TRIGIINTEN
trigger input interrupt enable
6
1
read-write
UDMAEN
update DMA enable
8
1
read-write
UINTEN
update interrupt enable
0
1
read-write
PROTCFG
PROTCFG
protect configuration register
0x44
32
read-write
n
0x0
0x0
AOCEN
automatic output compare enable
14
1
read-write
BRKEN
break enable
12
1
read-write
BRKPOL
break input signal polarity level
13
1
read-write
DT
dead time
0
8
read-write
FRZ
freeze function
8
2
read-write
OCEN
output compare enable
15
1
read-write
OCIDLEN
output compare idle mode off-state enable
10
1
read-write
OCRUNEN
output compare running mode off-state enable
11
1
read-write
REPT
REPT
timer' repetitions
0x30
32
read-write
n
0x0
0x0
REPT
timer repetitions
0
8
read-write
RLD
RLD
timer' reload
0x2C
32
read-write
n
0x0
0x0
RLD
timer reload
0
16
read-write
SLVMODCTL
SLVMODCTL
slave control register
0x8
32
read-write
n
0x0
0x0
EXTDIV
external signal division
12
2
read-write
EXTEN
external signal enable
14
1
read-write
EXTFLT
external signal filter
8
4
read-write
EXTPOL
external signal polarity level
15
1
read-write
PREOUTCLR
preout clear
3
1
read-write
SLVMOD
Slave mode
0
3
read-write
SYNCEN
sync enable
7
1
read-write
TRIGISRC
trigger input source
4
3
read-write
STAT
STAT
status register
0x10
32
read-write
n
0x0
0x0
BRKF
break flag
7
1
read-write
C0F
capture/compare 0 flag
1
1
read-write
C1F
capture/compare 1 flag
2
1
read-write
C2F
capture/compare 2 flag
3
1
read-write
C3F
capture/compare 3 flag
4
1
read-write
COMF
commutation flag
5
1
read-write
OVC0F
over capture 0 flag
9
1
read-write
OVC1F
over capture 1 flag
10
1
read-write
OVC2F
over capture 2 flag
11
1
read-write
OVC3F
over capture 3 flag
12
1
read-write
TRIGIF
trigger input flag
6
1
read-write
UF
update flag
0
1
read-write
TIMERG1
General Timer 1
TIMERG1
0x0
0x0
0x400
registers
n
TIMERG1
TIMERG1 interrupt
16
CCMP0
CCMP0
capture/compare counter value 0
0x34
32
read-write
n
0x0
0x0
CCMP0
capture/compare counter value 0
0
16
read-write
CCMP1
CCMP1
capture/compare counter value 1
0x38
32
read-write
n
0x0
0x0
CCMP1
capture/compare counter value 1
0
16
read-write
CCMP2
CCMP2
capture/compare counter value 2
0x3C
32
read-write
n
0x0
0x0
CCMP2
capture/compare counter value 2
0
16
read-write
CCMP3
CCMP3
capture/compare counter value 3
0x40
32
read-write
n
0x0
0x0
CCMP3
capture/compare counter value 3
0
16
read-write
CCTL0_input
CCTL0_input
capture/compare control register 0
CCTL0_output
0x18
32
read-write
n
0x0
0x0
ICS0DIV
input capture signal 0 division
2
2
read-write
ICS0FLT
input capture signal 0 filter
4
4
read-write
ICS0SRC
input capture signal 0 source
0
2
read-write
ICS1DIV
input capture signal 1 division
10
2
read-write
ICS1FLT
input capture signal 1 filter
12
4
read-write
ICS1SRC
input capture signal 1 source
8
2
read-write
CCTL0_output
CCTL0_output
capture/compare control register 0
0x18
32
read-write
n
0x0
0x0
ICS0SRC
input capture signal 0 source
0
2
read-write
ICS1SRC
input capture signal 1 source
8
2
read-write
OCS0FMEN
output compare signal 0 Fast Mode enable
2
1
read-write
OCS0MOD
output compare signal 0 mode
4
3
read-write
OCS0PRLDEN
output compare signal 0 preload enable
3
1
read-write
OCS1FMEN
output compare signal 1 Fast Mode enable
10
1
read-write
OCS1MOD
output compare signal 1 mode
12
3
read-write
OCS1PRLDEN
output compare signal 1 preload enable
11
1
read-write
CCTL1_input
CCTL1_input
capture/compare control register 1
CCTL1_output
0x1C
32
read-write
n
0x0
0x0
ICS2DIV
input capture signal 2 division
2
2
read-write
ICS2FLT
input capture signal 2 filter
4
4
read-write
ICS2SRC
input capture signal 2 source
0
2
read-write
ICS3DIV
input capture signal 3division
10
2
read-write
ICS3FLT
input capture signal 3 filter
12
4
read-write
ICS3SRC
input capture signal 3 source
8
2
read-write
CCTL1_output
CCTL1_output
capture/compare control register 1
0x1C
32
read-write
n
0x0
0x0
ICS2SRC
input capture signal 2 source
0
2
read-write
ICS3SRC
input capture signal 3 source
8
2
read-write
OCS2FMEN
output compare signal 2 Fast mode enable
2
1
read-write
OCS2MOD
output compare signal 2 mode
4
3
read-write
OCS2PRLDEN
output compare signal2 preload enable
3
1
read-write
OCS3FMEN
output compare signal 3 Fast Mode enable
10
1
read-write
OCS3MOD
output compare signal 3 mode
12
3
read-write
OCS3PRLDEN
output compare signal 3 preload enable
11
1
read-write
CCTL2
CCTL2
capture/compare control register 2
0x20
32
read-write
n
0x0
0x0
CS0EN
capture/compare signal 0 enable
0
1
read-write
CS0POL
capture/compare signal 0 polarity level
1
1
read-write
CS0RPOL
capture/compare signal 0 reverse polarity level
3
1
read-write
CS1EN
capture/compare signal 1 enable
4
1
read-write
CS1POL
capture/compare signal 1 polarity level
5
1
read-write
CS1RPOL
capture/compare signal 1 reverse polarity level
7
1
read-write
CS2EN
capture/compare signal 2 enable
8
1
read-write
CS2POL
capture/compare signal 2 polarity level
9
1
read-write
CS2RPOL
capture/compare signal 2 reverse polarity level
11
1
read-write
CS3EN
capture/compare signal 3 enable
12
1
read-write
CS3POL
capture/compare signal 3 polarity level
13
1
read-write
CS3RPOL
capture/compare signal 3 reverse polarity level
15
1
read-write
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
ALIGNMOD
align mode
5
2
read-write
CLKDIV
clock division
8
2
read-write
CNTDIR
count direction
4
1
read-write
EN
Counter enable
0
1
read-write
RLDPRLDEN
reload preload enable
7
1
read-write
SGLPLSMOD
single pulse mode
3
1
read-write
UDIS
Update disable
1
1
read-write
USRC
Update source
2
1
read-write
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
IS0SRC
input signal 0 source
7
1
read-write
OCDMASRC
output compare DMA source
3
1
read-write
TRIGOSRC
trigger out source
4
3
read-write
DATA
DATA
timer' current data
0x24
32
read-write
n
0x0
0x0
DATA
timer data
0
16
read-write
DIV
DIV
timer' divisions
0x28
32
read-write
n
0x0
0x0
DIV
timer divisions
0
16
read-write
DMACFG
DMACFG
DMA configuration register
0x48
32
read-write
n
0x0
0x0
BASEADDR
DMA base address
0
5
read-write
BSTLEN
DMA burst length
8
5
read-write
DMARMP
DMARMP
DMA remap register
0x4C
32
read-write
n
0x0
0x0
RMP
DMA burst remap address
0
16
read-write
EVTSET
EVTSET
event set register
0x14
32
write-only
n
0x0
0x0
C0
capture/compare 0 event set
1
1
write-only
C1
capture/compare 1 event set
2
1
write-only
C2
capture/compare 2 event set
3
1
write-only
C3
capture/compare 3 event set
4
1
write-only
TRIGI
trigger input event set
6
1
write-only
UPDATE
update event set
0
1
write-only
INTDMAEN
INTDMAEN
interrupt/DMA enable register
0xC
32
read-write
n
0x0
0x0
C0DMAEN
capture/compare 0 DMA enable
9
1
read-write
C0INTEN
capture/compare 0 interrupt enable
1
1
read-write
C1DMAEN
capture/compare 1 DMA enable
10
1
read-write
C1INTEN
capture/compare 1 interrupt enable
2
1
read-write
C2DMAEN
capture/compare 2 DMA enable
11
1
read-write
C2INTEN
capture/compare 2 interrupt enable
3
1
read-write
C3DMAEN
capture/compare 3 DMA enable
12
1
read-write
C3INTEN
capture/compare 3 interrupt enable
4
1
read-write
TRIGIDMAEN
trigger input DMA enable
14
1
read-write
TRIGIINTEN
trigger input interrupt enable
6
1
read-write
UDMAEN
update DMA enable
8
1
read-write
UINTEN
update interrupt enable
0
1
read-write
RLD
RLD
timer' reload
0x2C
32
read-write
n
0x0
0x0
RLD
timer reload
0
16
read-write
SLVMODCTL
SLVMODCTL
slave control register
0x8
32
read-write
n
0x0
0x0
PREOUTCLR
preout clear
3
1
read-write
SLVMOD
Slave mode
0
3
read-write
SYNCEN
sync enable
7
1
read-write
TRIGISRC
trigger input source
4
3
read-write
STAT
STAT
status register
0x10
32
read-write
n
0x0
0x0
C0F
capture/compare 0 flag
1
1
read-write
C1F
capture/compare 1 flag
2
1
read-write
C2F
capture/compare 2 flag
3
1
read-write
C3F
capture/compare 3 flag
4
1
read-write
OVC0F
over capture 0 flag
9
1
read-write
OVC1F
over capture 1 flag
10
1
read-write
OVC2F
over capture 2 flag
11
1
read-write
OVC3F
over capture 3 flag
12
1
read-write
TRIGIF
trigger input flag
6
1
read-write
UF
update flag
0
1
read-write
TIMERG2
General Timer 2
TIMERG2
0x0
0x0
0x400
registers
n
TIMERG2
TIMERG2 interrupt
19
CCMP0
CCMP0
capture/compare counter value 0
0x34
32
read-write
n
0x0
0x0
CCMP0
capture/compare counter value 0
0
16
read-write
CCTL0_input
CCTL0_input
capture/compare control register 0
CCTL0_output
0x18
32
read-write
n
0x0
0x0
ICS0DIV
input capture signal 0 division
2
2
read-write
ICS0FLT
input capture signal 0 filter
4
4
read-write
ICS0SRC
input capture signal 0 source
0
2
read-write
CCTL0_output
CCTL0_output
capture/compare control register 0
0x18
32
read-write
n
0x0
0x0
ICS0SRC
input capture signal 0 source
0
2
read-write
OCS0FMEN
output compare signal 0 Fast Mode enable
2
1
read-write
OCS0MOD
output compare signal 0 mode
4
3
read-write
OCS0PRLDEN
output compare signal 0 preload enable
3
1
read-write
CCTL2
CCTL2
capture/compare control register 2
0x20
32
read-write
n
0x0
0x0
CS0EN
capture/compare signal 0 enable
0
1
read-write
CS0POL
capture/compare signal 0 polarity level
1
1
read-write
CS0RPOL
capture/compare signal 0 reverse polarity level
3
1
read-write
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
CLKDIV
clock division
8
2
read-write
EN
Counter enable
0
1
read-write
RLDPRLDEN
reload preload enable
7
1
read-write
UDIS
Update disable
1
1
read-write
USRC
Update source
2
1
read-write
DATA
DATA
timer' current data
0x24
32
read-write
n
0x0
0x0
DATA
timer data
0
16
read-write
DIV
DIV
timer' divisions
0x28
32
read-write
n
0x0
0x0
DIV
timer divisions
0
16
read-write
EVTSET
EVTSET
event set register
0x14
32
write-only
n
0x0
0x0
C0
capture/compare 0 event set
1
1
write-only
UPDATE
update event set
0
1
write-only
INTDMAEN
INTDMAEN
interrupt/DMA enable register
0xC
32
read-write
n
0x0
0x0
C0INTEN
capture/compare 0 interrupt enable
1
1
read-write
UINTEN
update interrupt enable
0
1
read-write
OPTRMP
OPTRMP
option remap register
0x50
32
read-write
n
0x0
0x0
IS0RMP
input signal 0 option remap
0
2
read-write
RLD
RLD
timer' reload
0x2C
32
read-write
n
0x0
0x0
RLD
timer reload
0
16
read-write
STAT
STAT
status register
0x10
32
read-write
n
0x0
0x0
C0F
capture/compare 0 flag
1
1
read-write
OVC0F
over capture 0 flag
9
1
read-write
UF
update flag
0
1
read-write
TIMERG3
General Timer 3
TIMERG3
0x0
0x0
0x400
registers
n
TIMERG3
TIMERG3 interrupt
21
CCMP0
CCMP0
capture/compare counter value 0
0x34
32
read-write
n
0x0
0x0
CCMP0
capture/compare counter value 0
0
16
read-write
CCTL0_input
CCTL0_input
capture/compare control register 0
CCTL0_output
0x18
32
read-write
n
0x0
0x0
ICS0DIV
input capture signal 0 division
2
2
read-write
ICS0FLT
input capture signal 0 filter
4
4
read-write
ICS0SRC
input capture signal 0 source
0
2
read-write
CCTL0_output
CCTL0_output
capture/compare control register 0
0x18
32
read-write
n
0x0
0x0
ICS0SRC
input capture signal 0 source
0
2
read-write
OCS0FMEN
output compare signal 0 Fast Mode enable
2
1
read-write
OCS0MOD
output compare signal 0 mode
4
3
read-write
OCS0PRLDEN
output compare signal 0 preload enable
3
1
read-write
CCTL2
CCTL2
capture/compare control register 2
0x20
32
read-write
n
0x0
0x0
CS0EN
capture/compare signal 0 enable
0
1
read-write
CS0POL
capture/compare signal 0 polarity level
1
1
read-write
CS0REN
capture/compare signal 0 reverse enable
2
1
read-write
CS0RPOL
capture/compare signal 0 reverse polarity level
3
1
read-write
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
CLKDIV
clock division
8
2
read-write
EN
Counter enable
0
1
read-write
RLDPRLDEN
reload preload enable
7
1
read-write
SGLPLSMOD
single pulse mode
3
1
read-write
UDIS
Update disable
1
1
read-write
USRC
Update source
2
1
read-write
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
CUSRC
capture/compare update source
2
1
read-write
OC0IDLRSTAT
output compare 0 idle mode reversed status
9
1
read-write
OC0IDLSTAT
output compare 0 idle mode status
8
1
read-write
OCDMASRC
output compare DMA source
3
1
read-write
OCPRLDEN
output compare control preload enable
0
1
read-write
DATA
DATA
timer' current data
0x24
32
read-write
n
0x0
0x0
DATA
timer data
0
16
read-write
DIV
DIV
timer' divisions
0x28
32
read-write
n
0x0
0x0
DIV
timer divisions
0
16
read-write
DMACFG
DMACFG
DMA configuration register
0x48
32
read-write
n
0x0
0x0
BASEADDR
DMA base address
0
5
read-write
BSTLEN
DMA burst length
8
5
read-write
DMARMP
DMARMP
DMA remap register
0x4C
32
read-write
n
0x0
0x0
RMP
DMA burst remap address
0
16
read-write
EVTSET
EVTSET
event set register
0x14
32
write-only
n
0x0
0x0
BRK
break event set
7
1
write-only
C0
capture/compare 0 event set
1
1
write-only
COM
commutation event set
5
1
write-only
UPDATE
update event set
0
1
write-only
INTDMAEN
INTDMAEN
interrupt/DMA enable register
0xC
32
read-write
n
0x0
0x0
BRKINTEN
break interrupt enable
7
1
read-write
C0DMAEN
capture/compare 0 DMA enable
9
1
read-write
C0INTEN
capture/compare 0 interrupt enable
1
1
read-write
COMINTEN
commutation interrupt enable
5
1
read-write
UDMAEN
update DMA enable
8
1
read-write
UINTEN
update interrupt enable
0
1
read-write
PROTCFG
PROTCFG
protect configuration register
0x44
32
read-write
n
0x0
0x0
AOCEN
automatic output compare enable
14
1
read-write
BRKEN
break enable
12
1
read-write
BRKPOL
break input signal polarity level
13
1
read-write
DT
dead time
0
8
read-write
FRZ
freeze function
8
2
read-write
OCEN
output compare enable
15
1
read-write
OCIDLEN
output compare idle mode off-state enable
10
1
read-write
OCRUNEN
output compare running mode off-state enable
11
1
read-write
REPT
REPT
timer' repetitions
0x30
32
read-write
n
0x0
0x0
REPT
timer repetitions
0
8
read-write
RLD
RLD
timer' reload
0x2C
32
read-write
n
0x0
0x0
RLD
timer reload
0
16
read-write
STAT
STAT
status register
0x10
32
read-write
n
0x0
0x0
BRKF
break flag
7
1
read-write
C0F
capture/compare 0 flag
1
1
read-write
COMF
commutation flag
5
1
read-write
OVC0F
over capture 0 flag
9
1
read-write
UF
update flag
0
1
read-write
TIMERG4
General Timer 4
TIMERG4
0x0
0x0
0x400
registers
n
TIMERG4
TIMERG4 interrupt
22
CCMP0
CCMP0
capture/compare counter value 0
0x34
32
read-write
n
0x0
0x0
CCMP0
capture/compare counter value 0
0
16
read-write
CCTL0_input
CCTL0_input
capture/compare control register 0
CCTL0_output
0x18
32
read-write
n
0x0
0x0
ICS0DIV
input capture signal 0 division
2
2
read-write
ICS0FLT
input capture signal 0 filter
4
4
read-write
ICS0SRC
input capture signal 0 source
0
2
read-write
CCTL0_output
CCTL0_output
capture/compare control register 0
0x18
32
read-write
n
0x0
0x0
ICS0SRC
input capture signal 0 source
0
2
read-write
OCS0FMEN
output compare signal 0 Fast Mode enable
2
1
read-write
OCS0MOD
output compare signal 0 mode
4
3
read-write
OCS0PRLDEN
output compare signal 0 preload enable
3
1
read-write
CCTL2
CCTL2
capture/compare control register 2
0x20
32
read-write
n
0x0
0x0
CS0EN
capture/compare signal 0 enable
0
1
read-write
CS0POL
capture/compare signal 0 polarity level
1
1
read-write
CS0REN
capture/compare signal 0 reverse enable
2
1
read-write
CS0RPOL
capture/compare signal 0 reverse polarity level
3
1
read-write
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
CLKDIV
clock division
8
2
read-write
EN
Counter enable
0
1
read-write
RLDPRLDEN
reload preload enable
7
1
read-write
SGLPLSMOD
single pulse mode
3
1
read-write
UDIS
Update disable
1
1
read-write
USRC
Update source
2
1
read-write
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
CUSRC
capture/compare update source
2
1
read-write
OC0IDLRSTAT
output compare 0 idle mode reversed status
9
1
read-write
OC0IDLSTAT
output compare 0 idle mode status
8
1
read-write
OCDMASRC
output compare DMA source
3
1
read-write
OCPRLDEN
output compare control preload enable
0
1
read-write
DATA
DATA
timer' current data
0x24
32
read-write
n
0x0
0x0
DATA
timer data
0
16
read-write
DIV
DIV
timer' divisions
0x28
32
read-write
n
0x0
0x0
DIV
timer divisions
0
16
read-write
DMACFG
DMACFG
DMA configuration register
0x48
32
read-write
n
0x0
0x0
BASEADDR
DMA base address
0
5
read-write
BSTLEN
DMA burst length
8
5
read-write
DMARMP
DMARMP
DMA remap register
0x4C
32
read-write
n
0x0
0x0
RMP
DMA burst remap address
0
16
read-write
EVTSET
EVTSET
event set register
0x14
32
write-only
n
0x0
0x0
BRK
break event set
7
1
write-only
C0
capture/compare 0 event set
1
1
write-only
COM
commutation event set
5
1
write-only
UPDATE
update event set
0
1
write-only
INTDMAEN
INTDMAEN
interrupt/DMA enable register
0xC
32
read-write
n
0x0
0x0
BRKINTEN
break interrupt enable
7
1
read-write
C0DMAEN
capture/compare 0 DMA enable
9
1
read-write
C0INTEN
capture/compare 0 interrupt enable
1
1
read-write
COMINTEN
commutation interrupt enable
5
1
read-write
UDMAEN
update DMA enable
8
1
read-write
UINTEN
update interrupt enable
0
1
read-write
PROTCFG
PROTCFG
protect configuration register
0x44
32
read-write
n
0x0
0x0
AOCEN
automatic output compare enable
14
1
read-write
BRKEN
break enable
12
1
read-write
BRKPOL
break input signal polarity level
13
1
read-write
DT
dead time
0
8
read-write
FRZ
freeze function
8
2
read-write
OCEN
output compare enable
15
1
read-write
OCIDLEN
output compare idle mode off-state enable
10
1
read-write
OCRUNEN
output compare running mode off-state enable
11
1
read-write
REPT
REPT
timer' repetitions
0x30
32
read-write
n
0x0
0x0
REPT
timer repetitions
0
8
read-write
RLD
RLD
timer' reload
0x2C
32
read-write
n
0x0
0x0
RLD
timer reload
0
16
read-write
STAT
STAT
status register
0x10
32
read-write
n
0x0
0x0
BRKF
break flag
7
1
read-write
C0F
capture/compare 0 flag
1
1
read-write
COMF
commutation flag
5
1
read-write
OVC0F
over capture 0 flag
9
1
read-write
UF
update flag
0
1
read-write
TSC
Touch registers
TSC
0x0
0x0
0x400
registers
n
TSC
TSC interrupt
8
BASCLKCFG
BASCLKCFG
Configuration register
0xE8
32
read-write
n
0x0
0x0
BASCLKDIV
Set the division factor of Base Timer
0
16
read-write
CCCFG0
CCCFG0
Configuration register
0x44
32
read-write
n
0x0
0x0
CANCCSEL0
Set the value of Cancel Capacitance In Channel0
0
9
read-write
CANCCSEL1
Set the value of Cancel Capacitance In Channel1
16
9
read-write
CCCFG1
CCCFG1
Configuration register
0x48
32
read-write
n
0x0
0x0
CANCCSEL2
Set the value of Cancel Capacitance In Channel2
0
9
read-write
CANCCSEL3
Set the value of Cancel Capacitance In Channel3
16
9
read-write
CCCFG10
CCCFG10
Configuration register
0x6C
32
read-write
n
0x0
0x0
CANCCSEL20
Set the value of Cancel Capacitance In Channel20
0
9
read-write
CANCCSEL21
Set the value of Cancel Capacitance In Channel21
16
9
read-write
CCCFG11
CCCFG11
Configuration register
0x70
32
read-write
n
0x0
0x0
CANCCSEL22
Set the value of Cancel Capacitance In Channel22
0
9
read-write
CANCCSEL23
Set the value of Cancel Capacitance In Channel23
16
9
read-write
CCCFG2
CCCFG2
Configuration register
0x4C
32
read-write
n
0x0
0x0
CANCCSEL4
Set the value of Cancel Capacitance In Channel4
0
9
read-write
CANCCSEL5
Set the value of Cancel Capacitance In Channel5
16
9
read-write
CCCFG3
CCCFG3
Configuration register
0x50
32
read-write
n
0x0
0x0
CANCCSEL6
Set the value of Cancel Capacitance In Channel6
0
9
read-write
CANCCSEL7
Set the value of Cancel Capacitance In Channel7
16
9
read-write
CCCFG4
CCCFG4
Configuration register
0x54
32
read-write
n
0x0
0x0
CANCCSEL8
Set the value of Cancel Capacitance In Channel8
0
9
read-write
CANCCSEL9
Set the value of Cancel Capacitance In Channel9
16
9
read-write
CCCFG5
CCCFG5
Configuration register
0x58
32
read-write
n
0x0
0x0
CANCCSEL10
Set the value of Cancel Capacitance In Channel10
0
9
read-write
CANCCSEL11
Set the value of Cancel Capacitance In Channel11
16
9
read-write
CCCFG6
CCCFG6
Configuration register
0x5C
32
read-write
n
0x0
0x0
CANCCSEL12
Set the value of Cancel Capacitance In Channel12
0
9
read-write
CANCCSEL13
Set the value of Cancel Capacitance In Channel13
16
9
read-write
CCCFG7
CCCFG7
Configuration register
0x60
32
read-write
n
0x0
0x0
CANCCSEL14
Set the value of Cancel Capacitance In Channel14
0
9
read-write
CANCCSEL15
Set the value of Cancel Capacitance In Channel15
16
9
read-write
CCCFG8
CCCFG8
Configuration register
0x64
32
read-write
n
0x0
0x0
CANCCSEL16
Set the value of Cancel Capacitance In Channel16
0
9
read-write
CANCCSEL17
Set the value of Cancel Capacitance In Channel17
16
9
read-write
CCCFG9
CCCFG9
Configuration register
0x68
32
read-write
n
0x0
0x0
CANCCSEL18
Set the value of Cancel Capacitance In Channel18
0
9
read-write
CANCCSEL19
Set the value of Cancel Capacitance In Channel19
16
9
read-write
CFG0
CFG0
Configuration register
0x0
32
read-write
n
0x0
0x0
ADCSMPTIMES
ADC sample times
8
4
read-write
CFG1
CFG1
Configuration register
0x20
32
read-write
n
0x0
0x0
DISCHGTIME
configure the time of discharge
0
4
read-write
SHDTIME
configure the time of charge shielding channel
8
4
read-write
CFG2
CFG2
Configuration register
0x3C
32
read-write
n
0x0
0x0
CCI
set the current of cancel capacitance
12
4
read-write
SHDEN
Enable shielding function
3
1
read-write
CHCFG0
CHCFG0
Configuration register
0x24
32
read-write
n
0x0
0x0
CH0CFGGRP
set the index of channel0 parameter
0
2
read-write
CH10CFGGRP
set the index of channel10 parameter
20
2
read-write
CH11CFGGRP
set the index of channel11 parameter
22
2
read-write
CH12CFGGRP
set the index of channel12 parameter
24
2
read-write
CH13CFGGRP
set the index of channel13 parameter
26
2
read-write
CH14CFGGRP
set the index of channel14 parameter
28
2
read-write
CH15CFGGRP
set the index of channel15 parameter
30
2
read-write
CH1CFGGRP
set the index of channel1 parameter
2
2
read-write
CH2CFGGRP
set the index of channel2 parameter
4
2
read-write
CH3CFGGRP
set the index of channel3 parameter
6
2
read-write
CH4CFGGRP
set the index of channel4 parameter
8
2
read-write
CH5CFGGRP
set the index of channel5 parameter
10
2
read-write
CH6CFGGRP
set the index of channel6 parameter
12
2
read-write
CH7CFGGRP
set the index of channel7 parameter
14
2
read-write
CH8CFGGRP
set the index of channel8 parameter
16
2
read-write
CH9CFGGRP
set the index of channel9 parameter
18
2
read-write
CHCFG1
CHCFG1
Configuration register
0x28
32
read-write
n
0x0
0x0
CH16CFGGRP
set the index of channel16 parameter
0
2
read-write
CH17CFGGRP
set the index of channel17 parameter
2
2
read-write
CH18CFGGRP
set the index of channel18 parameter
4
2
read-write
CH19CFGGRP
set the index of channel19 parameter
6
2
read-write
CH20CFGGRP
set the index of channel20 parameter
8
2
read-write
CH21CFGGRP
set the index of channel21 parameter
10
2
read-write
CH22CFGGRP
set the index of channel22 parameter
12
2
read-write
CH23CFGGRP
set the index of channel23 parameter
14
2
read-write
CHRMP0
CHRMP0
Configuration register
0x8
32
read-write
n
0x0
0x0
CHRMP0
Remap the Channel0
0
5
read-write
CHRMP1
Remap the Channel1
8
5
read-write
CHRMP2
Remap the Channel2
16
5
read-write
CHRMP3
Remap the Channel3
24
5
read-write
CHRMP1
CHRMP1
Configuration register
0xC
32
read-write
n
0x0
0x0
CHRMP4
Remap the Channel4
0
5
read-write
CHRMP5
Remap the Channel5
8
5
read-write
CHRMP6
Remap the Channel6
16
5
read-write
CHRMP7
Remap the Channel7
24
5
read-write
CHRMP2
CHRMP2
Configuration register
0x10
32
read-write
n
0x0
0x0
CHRMP10
Remap the Channel10
16
5
read-write
CHRMP11
Remap the Channel11
24
5
read-write
CHRMP8
Remap the Channel8
0
5
read-write
CHRMP9
Remap the Channel9
8
5
read-write
CHRMP3
CHRMP3
Configuration register
0x14
32
read-write
n
0x0
0x0
CHRMP12
Remap the Channel12
0
5
read-write
CHRMP13
Remap the Channel13
8
5
read-write
CHRMP14
Remap the Channel14
16
5
read-write
CHRMP15
Remap the Channel15
24
5
read-write
CHRMP4
CHRMP4
Configuration register
0x18
32
read-write
n
0x0
0x0
CHRMP16
Remap the Channel16
0
5
read-write
CHRMP17
Remap the Channel17
8
5
read-write
CHRMP18
Remap the Channel18
16
5
read-write
CHRMP19
Remap the Channel19
24
5
read-write
CHRMP5
CHRMP5
Configuration register
0x1C
32
read-write
n
0x0
0x0
CHRMP20
Remap the Channel20
0
5
read-write
CHRMP21
Remap the Channel21
8
5
read-write
CHRMP22
Remap the Channel22
16
5
read-write
CHRMP23
Remap the Channel23
24
5
read-write
CHTH0
CHTH0
Configuration register
0x100
32
read-write
n
0x0
0x0
HTH
set the high threshold value for the 1st hardware detect channel
16
12
read-write
LTH
set the low threshold value for the 1st hardware detect channel
0
12
read-write
CHTH1
CHTH1
Configuration register
0x104
32
read-write
n
0x0
0x0
HTH
set the high threshold value for the 2nd hardware detect channel
16
12
read-write
LTH
set the low threshold value for the 2nd hardware detect channel
0
12
read-write
CHTH2
CHTH2
Configuration register
0x108
32
read-write
n
0x0
0x0
HTH
set the high threshold value for the 3rd hardware detect channel
16
12
read-write
LTH
set the low threshold value for the 3rd hardware detect channel
0
12
read-write
CHTH3
CHTH3
Configuration register
0x10C
32
read-write
n
0x0
0x0
HTH
set the high threshold value for the 4th hardware detect channel
16
12
read-write
LTH
set the low threshold value for the 4th hardware detect channel
0
12
read-write
CTL0
CTL0
Control register
0x4
32
read-write
n
0x0
0x0
CHEN
Enable 24 Channels
0
24
read-write
MODSEL
select the work mode
28
1
read-write
TSCEN
Enable Touch function
24
1
read-write
CTL1
CTL1
Control register
0x164
32
read-write
n
0x0
0x0
DETBYP
Enable bypass hardware detect
0
1
read-write
DISTSCRDY
the state of close touch function
8
1
read-only
SLTIMER
From FastTimer mode switch to slowTimer mode
1
1
read-write
SMPT
The cycle of ADC capture Data
4
3
read-write
CTL2
CTL2
Control register
0x168
32
read-write
n
0x0
0x0
CHSEL
selection touch channels
0
24
read-write
DATA0
DATA0
RawData register
0x80
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel0
0
16
read-only
DATA1
DATA1
RawData register
0x84
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel1
0
16
read-only
DATA10
DATA10
RawData register
0xA8
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel10
0
16
read-only
DATA11
DATA11
RawData register
0xAC
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel11
0
16
read-only
DATA12
DATA12
RawData register
0xB0
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel12
0
16
read-only
DATA13
DATA13
RawData register
0xB4
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel13
0
16
read-only
DATA14
DATA14
RawData register
0xB8
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel14
0
16
read-only
DATA15
DATA15
RawData register
0xBC
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel15
0
16
read-only
DATA16
DATA16
RawData register
0xC0
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel16
0
16
read-only
DATA17
DATA17
RawData register
0xC4
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel17
0
16
read-only
DATA18
DATA18
RawData register
0xC8
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel18
0
16
read-only
DATA19
DATA19
RawData register
0xCC
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel19
0
16
read-only
DATA2
DATA2
RawData register
0x88
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel2
0
16
read-only
DATA20
DATA20
RawData register
0xD0
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel20
0
16
read-only
DATA21
DATA21
RawData register
0xD4
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel21
0
16
read-only
DATA22
DATA22
RawData register
0xD8
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel22
0
16
read-only
DATA23
DATA23
RawData register
0xDC
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel23
0
16
read-only
DATA3
DATA3
RawData register
0x8C
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel3
0
16
read-only
DATA4
DATA4
RawData register
0x90
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel4
0
16
read-only
DATA5
DATA5
RawData register
0x94
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel5
0
16
read-only
DATA6
DATA6
RawData register
0x98
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel6
0
16
read-only
DATA7
DATA7
RawData register
0x9C
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel7
0
16
read-only
DATA8
DATA8
RawData register
0xA0
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel8
0
16
read-only
DATA9
DATA9
RawData register
0xA4
32
read-only
n
0x0
0x0
DATA
Get the RawData of Channel9
0
16
read-only
FSTSLCLKCFG
FSTSLCLKCFG
Configuration register
0xEC
32
read-write
n
0x0
0x0
FSTCLKDIV
Set the division factor of Fast Timer
0
8
read-write
SLCLKDIV
Set the division factor of slow Timer
8
8
read-write
HWDETCTL
HWDETCTL
Control register
0x160
32
read-write
n
0x0
0x0
DETALLNUM
set the number of all rawdata
28
3
read-write
DETEN
Enable the Hardware detect in channels
0
24
read-write
DETOKNUM
set the number of rawdata in threshold
24
3
read-write
INTCTL
INTCTL
Interrupt control register
0xE4
32
read-write
n
0x0
0x0
CPLTINTEN
Enable Touch interrupt
0
1
read-write
TOINTEN
Enable Touch error Interrupt
4
1
read-write
INTGTIMES
INTGTIMES
Configuration register
0x2C
32
read-write
n
0x0
0x0
INTGTIMES0
set 1st group integrate times
0
8
read-write
INTGTIMES1
set 2nd group integrate times
8
8
read-write
INTGTIMES2
set 3rd group integrate times
16
8
read-write
INTGTIMES3
set 4th group integrate times
24
8
read-write
ISCACFG
ISCACFG
Configuration register
0x38
32
read-write
n
0x0
0x0
ISCA0
set 1st group I1/I2 scale
0
4
read-write
ISCA1
set 2nd group I1/I2 scale
4
4
read-write
ISCA2
set 3rd group I1/I2 scale
8
4
read-write
ISCA3
set 4th group I1/I2 scale
12
4
read-write
STAT
STAT
Touch status register
0xE0
32
read-write
n
0x0
0x0
CPLTF
The flag of touch work finished
0
1
read-write
FSTMODF
SlowTimer or FastTimer work mode
8
1
read-only
TOF
The flag of timeout error
4
1
read-write
USART
Universal Synchronous Asynchronous Receiver Transmitter
USART
0x0
0x0
0x400
registers
n
USART1
USART1 interrupt
27
BR
BR
baud rate register
0xC
32
read-write
n
0x0
0x0
BRDIV
baud rate division
0
16
read-write
CTL0
CTL0
control register 0
0x0
32
read-write
n
0x0
0x0
CLEN
char length
12
1
read-write
CMINTEN
character match interrupt enable
14
1
read-write
DEAT
Driver Enable assertion time
21
5
read-write
DEDT
Driver Enable de-assertion time
16
5
read-write
IDLEINTEN
idle interrupt enable
4
1
read-write
MMODEN
mute mode enable
13
1
read-write
OVS8
oversample by 8 enable
15
1
read-write
PEN
parity control enable
10
1
read-write
PINTEN
parity interrupt enable
8
1
read-write
PSEL
parity selection
9
1
read-write
RXEN
receive enable
2
1
read-write
RXNEINTEN
RXNE interrupt enable
5
1
read-write
RXTOINTEN
receive timeout interrupt enable
26
1
read-write
TXCINTEN
transfer complete interrupt enable
6
1
read-write
TXEINTEN
transfer empty interrupt enable
7
1
read-write
TXEN
transmit enable
3
1
read-write
UEN
USART enable
0
1
read-write
USMODEN
USART enable in stop mode
1
1
read-write
WUMMOD
mute mode wakeup method
11
1
read-write
CTL1
CTL1
control register 1
0x4
32
read-write
n
0x0
0x0
ABREN
auto baud rate enable
20
1
read-write
ABRMOD
auto baud rate mode
21
2
read-write
ADDR
address of the USART node
24
8
read-write
ADDRM
address detection mode
4
1
read-write
CLKEN
clock enable
11
1
read-write
CPHA
clock phase
9
1
read-write
CPOL
clock polarity
10
1
read-write
DATINV
data and parity bit are inverted
18
1
read-write
LBCLK
last bit clock pulse
8
1
read-write
LBDINTEN
LIN break detection interrupt enable
6
1
read-write
LBDLEN
LIN break detection length
5
1
read-write
LINEN
LIN mode enable
14
1
read-write
MSBFST
MSB first
19
1
read-write
RXINV
RX pin signals are inverted
16
1
read-write
RXTOEN
receiver timeout enable
23
1
read-write
STOPBIT
stop bits
12
2
read-write
SWAPTXRX
Swap TX/RX pins
15
1
read-write
TXINV
TX pin signals are inverted
17
1
read-write
CTL2
CTL2
control register 2
0x8
32
read-write
n
0x0
0x0
CTSEN
CTS enable
9
1
read-write
CTSINTEN
CTS interrupt enable
10
1
read-write
DDRE
DMA disable on reception error
13
1
read-write
DEEN
driver enable mode
14
1
read-write
DEPSEL
DE signal polarity
15
1
read-write
DMARXEN
DMA enable receiver
6
1
read-write
DMATXEN
DMA enable transmitter
7
1
read-write
ERRINTEN
error interrupt enable
0
1
read-write
HFDUPSEL
half duplex selection
3
1
read-write
IRMODEN
IrDA mode enable
1
1
read-write
IRMODLP
IrDA low power mode enable
2
1
read-write
ONEBITEN
one bit enable
11
1
read-write
OVRDIS
overrun disable
12
1
read-write
RTSEN
RTS enable
8
1
read-write
WUSTPMOD
wakeup from stop mode
20
2
read-write
WUSTPMODINTEN
wakeup from stop mode interrupt enable
22
1
read-write
INTCLR
INTCLR
Interrupts clear register
0x20
32
write-only
n
0x0
0x0
CMFCLR
character match clear flag
17
1
write-only
CTSINTFCLR
CTS clear flag
9
1
write-only
FERRCLR
framing error clear flag
1
1
write-only
IDLEFCLR
idle line detected clear flag
4
1
write-only
LBDFCLR
LIN break detection clear flag
8
1
write-only
NERRCLR
noise detected clear flag
2
1
write-only
OVRERRCLR
overrun error clear flag
3
1
write-only
PERRCLR
parity error clear flag
0
1
write-only
RXTOFCLR
receive timeout clear flag
11
1
write-only
TXCFCLR
transmission complete clear flag
6
1
write-only
WUSTPMODFCLR
wakeup from stop mode clear flag
20
1
write-only
PRS
PRS
IrDA prescale register
0x10
32
read-write
n
0x0
0x0
PRDIV
prescale division
0
8
read-write
REQ
REQ
request register
0x18
32
write-only
n
0x0
0x0
ABRREQ
auto baud rate request
0
1
write-only
MMODREQ
mute mode request
2
1
write-only
RXFREQ
receive data flush request
3
1
write-only
SBRKREQ
send break request
1
1
write-only
RTO
RTO
receiver timeout value register
0x14
32
read-write
n
0x0
0x0
RXTOVAL
receiver timeout value
0
24
read-write
RXDATA
RXDATA
receive data register
0x24
32
read-only
n
0x0
0x0
RXDATA
RX buffer data
0
9
read-only
STAT
STAT
Interrupt status register
0x1C
32
read-only
n
0x0
0x0
ABRERRF
auto baud rate err flag
14
1
read-only
ABRF
auto baud rate success flag
15
1
read-only
BSYF
busy flag
16
1
read-only
CMF
character match flag
17
1
read-only
CTSF
CTS flag
10
1
read-only
CTSINTF
CTS interrupt flag
9
1
read-only
FERRF
framing error flag
1
1
read-only
IDLEF
idle line detect
4
1
read-only
LBDF
LIN break detection flag
8
1
read-only
NERRF
noise error flag
2
1
read-only
OVRERRF
overrun error flag
3
1
read-only
PERRF
parity error flag
0
1
read-only
REACK
RE is taken into account
22
1
read-only
RXNEF
read data register not empty flag
5
1
read-only
RXTOF
receive timeout flag
11
1
read-only
RXWUF
receiver wakeup from mute mode flag
19
1
read-only
SBRKF
send break flag
18
1
read-only
TEACK
TE is taken into account
21
1
read-only
TXCF
transmit complete flag
6
1
read-only
TXEF
transmit data register empty flag
7
1
read-only
WUSTPMODF
wake up from stop mode flag
20
1
read-only
TXDATA
TXDATA
transmit data register
0x28
32
read-write
n
0x0
0x0
TXDATA
TX buffer data
0
9
read-write
WWDT
System window watchdog
WWDT
0x0
0x0
0x400
registers
n
WWDT
Window Watchdog interrupt
0
CFG
CFG
Configuration register
0x4
32
read-write
n
0x0
0x0
DIV
Timer base
7
2
read-write
EWINTEN
Early wakeup interrupt
9
1
read-write
WIN
7-bit window value
0
7
read-write
CTL
CTL
Control register
0x0
32
read-write
n
0x0
0x0
COUNT
7-bit counter
0
7
read-write
WDTEN
watchdog enable
7
1
read-write
STAT
STAT
Status register
0x8
32
read-write
n
0x0
0x0
EWINTF
Early wakeup interrupt flag.
0
1
read-write