Goodix GR551x 2024.10.22 GR551x CM4 r0p0 little 2 false 8 32 AES Advanced Encryption Standard AES 0xA0015400 0x0 0x84 registers n AES AES interrupt 16 CFG CFG AES Configuration Register 0x4 32 read-write n 0x0 0xFFFFFFFF DEC_ENC_SEL Selection for encryption/decryption 0x0: Decryption(default) 0x1: Encryption 4 1 read-write ENDIAN Selection for data endian ctrl 0x0: Reverse to big_endian(default) 0x1: No reverse 7 1 read-write FIRST_BLK This register should be set to 1 before starting the first block in normal CBC and DMA CBC mode, and this register will be cleared by itself. 6 1 write-only FULL_MASK_EN Full mask enable signal 0x0: Disable (default) 0x1: Enable (DPA Resistance) 3 1 read-write KEY_MODE Key mode selection for encryption / decryption 0x0: 128 bits (default) 0x1: 192 bits 0x2: 256 bits 0x3: Reserved 0 2 read-write KEY_TYPE key type selection for encryption / decryption 0x0: Configured by MCU(default) 0x1: Fetched through AHB interface 0x2: Fetched through key port 0x3: Reserved 11 2 read-write LOAD_SEED Load seed for LFSR, seed for LFSR will be reloaded when this register was written with 1. This register can be cleared by itself. 5 1 write-only OPT_MODE Selection for operation mode 0x0: Electronic codebook (ECB) mode 0x1: Cipher block chaining (CBC) mode 0x2 ~ 0x7: Reserved for future application 8 3 read-write CTRL CTRL AES Controller Register 0x0 32 read-write n 0x0 0xFFFFFFFF DMA_MODE_EN DMA mode start enable: DMA mode start N block data encryption or decryption. 2 1 read-write FKEY_EN Enable AES fetch key by itself through AHBAHB master interface or key port. This register can be cleared by itself when key_valid is set to 1. 3 1 write-only MCU_MODE_EN MCU mode start enable: MCU mode start a block data encryption or decryption. This signal should be clear to zero before a new block input data is ready to start. 1 1 read-write DATA_IN0 DATA_IN0 AES Data Input 0 Register 0x70 32 write-only n 0x0 0xFFFFFFFF DATA_IN0 Input data[127:96] for encryption or decryption. This register is valid in MUC mode. 0 32 write-only DATA_IN1 DATA_IN1 AES Data Input 1 Register 0x74 32 write-only n 0x0 0xFFFFFFFF DATA_IN1 Input data[95:64] for encryption or decryption. This register is valid in MUC mode. 0 32 write-only DATA_IN2 DATA_IN2 AES Data Input 2 Register 0x78 32 write-only n 0x0 0xFFFFFFFF DATA_IN2 Input data[63:32] for encryption or decryption. This register is valid in MUC mode. 0 32 write-only DATA_IN3 DATA_IN3 AES Data Input 3 Register 0x7C 32 write-only n 0x0 0xFFFFFFFF DATA_IN3 Input data[31:0] for encryption or decryption. This register is valid in MUC mode. 0 32 write-only DATA_OUT0 DATA_OUT0 AES Data Output 0 Register 0x20 32 read-only n 0x0 0xFFFFFFFF DATA_OUT0 AES result data[127:96] 0 32 read-only DATA_OUT1 DATA_OUT1 AES Data Output 1 Register 0x24 32 read-only n 0x0 0xFFFFFFFF DATA_OUT1 AES result data[95:64] 0 32 read-only DATA_OUT2 DATA_OUT2 AES Data Output 2 Register 0x28 32 read-only n 0x0 0xFFFFFFFF DATA_OUT2 AES result data[63:32] 0 32 read-only DATA_OUT3 DATA_OUT3 AES Data Output 3 Register 0x2C 32 read-only n 0x0 0xFFFFFFFF DATA_OUT3 AES result data[31:0] 0 32 read-only INIT_SSI INIT_SSI AES Sbox Initial Seed Input Register 0x50 32 read-write n 0x0 0xFFFFFFFF SEED Sbox initial seed input 0 32 read-write INIT_SSO INIT_SSO AES Sbox Initial Seed Output Register 0x54 32 read-write n 0x0 0xFFFFFFFF SEED Sbox initial seed onput 0 32 read-write INIT_V0 INIT_V0 AES Initialization Vector 0 Register 0x60 32 write-only n 0x0 0xFFFFFFFF VECTOR Initialization vector[127:96] for CBC mode 0 32 write-only INIT_V1 INIT_V1 AES Initialization Vector 1 Register 0x64 32 write-only n 0x0 0xFFFFFFFF VECTOR Initialization vector[95:64] for CBC mode 0 32 write-only INIT_V2 INIT_V2 AES Initialization Vector 2 Register 0x68 32 write-only n 0x0 0xFFFFFFFF VECTOR Initialization vector[63:32] for CBC mode 0 32 write-only INIT_V3 INIT_V3 AES Initialization Vector 3 Register 0x6C 32 write-only n 0x0 0xFFFFFFFF VECTOR Initialization vector[31:0] for CBC mode 0 32 write-only INT INT AES Interrupt Register 0xC 32 read-write n 0x0 0xFFFFFFFF CPLT_INT_EN AES result data complete interrupt 0x0: Disable 0x1: Enable 1 1 read-write CPLT_INT_FLAG AES result data complete interrupt flag. Write 1 to clear. Read 0x0: Not interrupt 0x1: Interrupt Write 0x0: Not effect 0x1: Clear 0 1 read-write KEY0 KEY0 AES Key 0 Register 0x30 32 write-only n 0x0 0xFFFFFFFF KEY0 AES key[255:224] 0 32 write-only KEY1 KEY1 AES Key 1 Register 0x34 32 write-only n 0x0 0xFFFFFFFF KEY1 AES key[223:192] 0 32 write-only KEY2 KEY2 AES Key 2 Register 0x38 32 write-only n 0x0 0xFFFFFFFF KEY2 AES key[191:160] 0 32 write-only KEY3 KEY3 AES Key 3 Register 0x3C 32 write-only n 0x0 0xFFFFFFFF KEY3 AES key[159:128] 0 32 write-only KEY4 KEY4 AES Key 4 Register 0x40 32 write-only n 0x0 0xFFFFFFFF KEY4 AES key[127:96] 0 32 write-only KEY5 KEY5 AES Key 5 Register 0x44 32 write-only n 0x0 0xFFFFFFFF KEY5 AES key[95:64] 0 32 write-only KEY6 KEY6 AES Key 6 Register 0x48 32 write-only n 0x0 0xFFFFFFFF KEY6 AES key[63:32] 0 32 write-only KEY7 KEY7 AES Key 7 Register 0x4C 32 write-only n 0x0 0xFFFFFFFF KEY7 AES key[31:0] 0 32 write-only KEYPORT_MASK KEYPORT_MASK AES Keyport Mask Register 0x80 32 write-only n 0x0 0xFFFFFFFF MASK Mask for key from keyport 0 32 write-only KEY_ADDR KEY_ADDR AES Key Address Register 0x1C 32 read-write n 0x0 0xFFFFFFFF ADDR AES Key Address Register 0 32 read-write MASK_SSI MASK_SSI AES Sbox Seed Input Mask Register 0x58 32 read-write n 0x0 0xFFFFFFFF MASK Sbox initial seed input mask 0 32 read-write MASK_SSO MASK_SSO AES Sbox Seed Input Mask Register 0x5C 32 read-write n 0x0 0xFFFFFFFF MASK Sbox initial seed output mask 0 32 read-write RD_START_ADDR RD_START_ADDR AES Read Start Address Register 0x14 32 read-write n 0x0 0xFFFFFFFF ADDR DMA mode, read start address of transfer 0 32 read-write STAT STAT AES Status Register 0x8 32 read-only n 0x0 0xFFFFFFFF DMA_XFE_CPLT DMA transfer complete 0x0: Not complete 0x1: Complete 1 1 read-only DMA_XFE_ERR DMA transfer error, Write 1 to clear 0x0: Not ready 0x1: Ready 2 1 read-only KEY_STAT Key status, key is ready to read or not 0x0: Not ready 0x1: Ready 3 1 read-only READY AES result data out ready or not. This signal may be cleared when MCU_MODE_EN(CTRL[1]) is disabled. 0x0: Not ready 0x1 : Ready 0 1 read-only WR_START_ADDR WR_START_ADDR AES Write Start Address Register 0x18 32 read-write n 0x0 0xFFFFFFFF ADDR DMA mode, write start address of transfer 0 32 read-write XFE_SIZE XFE_SIZE AES Transfer Size Register 0x10 32 read-write n 0x0 0xFFFFFFFF SIZE Total transfer size, up to 32KB 0x000f: 1 block 0x001f: 2 block 0x002f: 3 block -- 0x7fff: 2048 block 0 15 read-write AON Always-on Domain AON 0xA000C500 0x0 0x98 registers n RTC_CTRL RTC_CTRL RTC Control Register 0x18 32 read-write n 0x2100 0xFFFFFFFF ALARM_INT_EN Timer alarm interrupt enable. 12 1 read-write ALARM_VAL_LOAD Alarm value load. Write 1 to load the value 2 1 write-only CLK_SEL Timer clock select. 8 3 read-write EN Calendar timer enable 0 1 read-write VAL_LOAD Up-counter value load. Write 1 to load the value 1 1 write-only WRAP_COUNT Wrap-around counter. 4 4 read-only WRAP_INT_EN Wrap-around interrupt enable 13 1 read-write VAL_RD VAL_RD Timer Value Read Register 0x94 32 read-only n 0x0 0xFFFFFFFF VAL_RD This register is shared with multiple timers. To read desired value. 0 32 read-only VAL_SET VAL_SET Timer Value Set Register 0x90 32 read-write n 0x0 0xFFFFFFFF VAL_SET This register is shared with multiple timers. To apply the value, set the value then assert corresponding load registers. 0 32 read-write WDT_CTRL WDT_CTRL AON WDT Control Register 0x58 32 read-write n 0xA0010001 0xFFFFFFFF ALARM_VAL Alarm values 27 5 read-write AON_WDT_EN WDT Enable 24 1 read-write AON_WDT_RELOAD Load the value in timer value to the AONWDT down-counter. 25 1 write-only AON_WDT_RUNNING WDT Runing enable 26 1 read-only EXTERNAL_WAKEUP_TYPE WDT type 16 8 read-write INVERT_EXTERNAL_WAKEUP Invert external wakeup 8 8 read-write SRC_EN External wakeup source enable 0 8 read-write DMA Direct Memory Access DMA 0xA0013000 0x0 0x1E8 registers n DMA DMA Interrupt 3 CFG_CH0_HIGH CFG_CH0_HIGH Configuration Register for Channel 0 High 32 bit 0x44 32 read-write n 0x4 0xFFFFFFFF DEST_PER Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFGx.HSG_SEL_DST field is 0 otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 11 4 read-write FIFO_MODE FIFO Mode Select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0x0: Space/data available for single AHB transfer of the specified transfer width 0x1: Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. 1 1 read-write FLOW_CTRL_MODE Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0x0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled 0x1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. 0 1 read-write PROT_CTRL Protection Control bits used to drive the AHB HPROT[3:1] bus. The AMBA Specification recommends that the default of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows: • 0x1 to HPROT[0] • CFGx.PROTCTL[1] to HPROT[1] • CFGx.PROTCTL[2] to HPROT[2] • CFGx.PROTCTL[3] to HPROT[3] 2 3 read-write SRC_PER Source Hardware Interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0 otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 7 4 read-write CFG_CH0_LOW CFG_CH0_LOW Configuration Register for Channel 0 Low 32 bit 0x40 32 read-write n 0xE00 0xFFFFFFFF CH_PRIOR Channel Priority. A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the range 0 to 3. A programmed value outside this range will cause erroneous behavior. 0x0: Channel priority is 0 0x1: Channel priority is 1 0x2: Channel priority is 2 0x3: Channel priority is 3 5 3 read-write CH_SUSP Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFG_CHx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0x0: DMA transfer from the source is not suspended 0x1: Suspend DMA transfer from the source 8 1 read-write DEST_HSG_POL Destination Handshaking Interface Polarity. 0x0: Destination Handshaking Interface Polarity is Active high 0x1: Destination Handshaking Interface Polarity is Active low 18 1 read-write FIFO_EMPTY Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty 9 1 read-only HSG_SEL_DEST Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, then this bit is ignored. 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored. 10 1 read-write HSG_SEL_SRC Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFG_CHx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty 11 1 read-write RELOAD_DEST Automatic Destination Reload. The DEST_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Destination Reload Disabled. 0x1: Destination Reload Enabled 31 1 read-write RELOAD_SRC Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Source Reload Disabled 0x1: Source Reload Enabled 30 1 read-write SRC_HSG_POL Source Handshaking Interface Polarity. 0x0: Source Handshaking Interface Polarity is Active high 0x1: Source Handshaking Interface Polarity is Active low 19 1 read-write CFG_CH1_HIGH CFG_CH1_HIGH Configuration Register for Channel 1 High 32 bit 0x9C 32 read-write n 0x4 0xFFFFFFFF DEST_PER Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFGx.HSG_SEL_DST field is 0 otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 11 4 read-write FIFO_MODE FIFO Mode Select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0x0: Space/data available for single AHB transfer of the specified transfer width 0x1: Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. 1 1 read-write FLOW_CTRL_MODE Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0x0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled 0x1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. 0 1 read-write PROT_CTRL Protection Control bits used to drive the AHB HPROT[3:1] bus. The AMBA Specification recommends that the default of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows: • 0x1 to HPROT[0] • CFGx.PROTCTL[1] to HPROT[1] • CFGx.PROTCTL[2] to HPROT[2] • CFGx.PROTCTL[3] to HPROT[3] 2 3 read-write SRC_PER Source Hardware Interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0 otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 7 4 read-write CFG_CH1_LOW CFG_CH1_LOW Configuration Register for Channel 1 Low 32 bit 0x98 32 read-write n 0xE20 0xFFFFFFFF CH_PRIOR Channel Priority. A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the range 0 to 3. A programmed value outside this range will cause erroneous behavior. 0x0: Channel priority is 0 0x1: Channel priority is 1 0x2: Channel priority is 2 0x3: Channel priority is 3 5 3 read-write CH_SUSP Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFG_CHx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0x0: DMA transfer from the source is not suspended 0x1: Suspend DMA transfer from the source 8 1 read-write DEST_HSG_POL Destination Handshaking Interface Polarity. 0x0: Destination Handshaking Interface Polarity is Active high 0x1: Destination Handshaking Interface Polarity is Active low 18 1 read-write FIFO_EMPTY Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty 9 1 read-only HSG_SEL_DEST Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, then this bit is ignored. 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored. 10 1 read-write HSG_SEL_SRC Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFG_CHx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty 11 1 read-write RELOAD_DEST Automatic Destination Reload. The DEST_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Destination Reload Disabled. 0x1: Destination Reload Enabled 31 1 read-write RELOAD_SRC Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Source Reload Disabled 0x1: Source Reload Enabled 30 1 read-write SRC_HSG_POL Source Handshaking Interface Polarity. 0x0: Source Handshaking Interface Polarity is Active high 0x1: Source Handshaking Interface Polarity is Active low 19 1 read-write CFG_CH2_HIGH CFG_CH2_HIGH Configuration Register for Channel 2 High 32 bit 0xF4 32 read-write n 0x4 0xFFFFFFFF DEST_PER Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFGx.HSG_SEL_DST field is 0 otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 11 4 read-write FIFO_MODE FIFO Mode Select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0x0: Space/data available for single AHB transfer of the specified transfer width 0x1: Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. 1 1 read-write FLOW_CTRL_MODE Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0x0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled 0x1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. 0 1 read-write PROT_CTRL Protection Control bits used to drive the AHB HPROT[3:1] bus. The AMBA Specification recommends that the default of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows: • 0x1 to HPROT[0] • CFGx.PROTCTL[1] to HPROT[1] • CFGx.PROTCTL[2] to HPROT[2] • CFGx.PROTCTL[3] to HPROT[3] 2 3 read-write SRC_PER Source Hardware Interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0 otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 7 4 read-write CFG_CH2_LOW CFG_CH2_LOW Configuration Register for Channel 2 Low 32 bit 0xF0 32 read-write n 0xE40 0xFFFFFFFF CH_PRIOR Channel Priority. A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the range 0 to 3. A programmed value outside this range will cause erroneous behavior. 0x0: Channel priority is 0 0x1: Channel priority is 1 0x2: Channel priority is 2 0x3: Channel priority is 3 5 3 read-write CH_SUSP Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFG_CHx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0x0: DMA transfer from the source is not suspended 0x1: Suspend DMA transfer from the source 8 1 read-write DEST_HSG_POL Destination Handshaking Interface Polarity. 0x0: Destination Handshaking Interface Polarity is Active high 0x1: Destination Handshaking Interface Polarity is Active low 18 1 read-write FIFO_EMPTY Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty 9 1 read-only HSG_SEL_DEST Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, then this bit is ignored. 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored. 10 1 read-write HSG_SEL_SRC Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFG_CHx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty 11 1 read-write RELOAD_DEST Automatic Destination Reload. The DEST_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Destination Reload Disabled. 0x1: Destination Reload Enabled 31 1 read-write RELOAD_SRC Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Source Reload Disabled 0x1: Source Reload Enabled 30 1 read-write SRC_HSG_POL Source Handshaking Interface Polarity. 0x0: Source Handshaking Interface Polarity is Active high 0x1: Source Handshaking Interface Polarity is Active low 19 1 read-write CFG_CH3_HIGH CFG_CH3_HIGH Configuration Register for Channel 3 High 32 bit 0x14C 32 read-write n 0x4 0xFFFFFFFF DEST_PER Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFGx.HSG_SEL_DST field is 0 otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 11 4 read-write FIFO_MODE FIFO Mode Select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0x0: Space/data available for single AHB transfer of the specified transfer width 0x1: Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. 1 1 read-write FLOW_CTRL_MODE Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0x0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled 0x1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. 0 1 read-write PROT_CTRL Protection Control bits used to drive the AHB HPROT[3:1] bus. The AMBA Specification recommends that the default of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows: • 0x1 to HPROT[0] • CFGx.PROTCTL[1] to HPROT[1] • CFGx.PROTCTL[2] to HPROT[2] • CFGx.PROTCTL[3] to HPROT[3] 2 3 read-write SRC_PER Source Hardware Interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0 otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 7 4 read-write CFG_CH3_LOW CFG_CH3_LOW Configuration Register for Channel 3 Low 32 bit 0x148 32 read-write n 0xE60 0xFFFFFFFF CH_PRIOR Channel Priority. A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the range 0 to 3. A programmed value outside this range will cause erroneous behavior. 0x0: Channel priority is 0 0x1: Channel priority is 1 0x2: Channel priority is 2 0x3: Channel priority is 3 5 3 read-write CH_SUSP Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFG_CHx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0x0: DMA transfer from the source is not suspended 0x1: Suspend DMA transfer from the source 8 1 read-write DEST_HSG_POL Destination Handshaking Interface Polarity. 0x0: Destination Handshaking Interface Polarity is Active high 0x1: Destination Handshaking Interface Polarity is Active low 18 1 read-write FIFO_EMPTY Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty 9 1 read-only HSG_SEL_DEST Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, then this bit is ignored. 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored. 10 1 read-write HSG_SEL_SRC Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFG_CHx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty 11 1 read-write RELOAD_DEST Automatic Destination Reload. The DEST_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Destination Reload Disabled. 0x1: Destination Reload Enabled 31 1 read-write RELOAD_SRC Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Source Reload Disabled 0x1: Source Reload Enabled 30 1 read-write SRC_HSG_POL Source Handshaking Interface Polarity. 0x0: Source Handshaking Interface Polarity is Active high 0x1: Source Handshaking Interface Polarity is Active low 19 1 read-write CFG_CH4_HIGH CFG_CH4_HIGH Configuration Register for Channel 4 High 32 bit 0x1A4 32 read-write n 0x4 0xFFFFFFFF DEST_PER Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFGx.HSG_SEL_DST field is 0 otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 11 4 read-write FIFO_MODE FIFO Mode Select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0x0: Space/data available for single AHB transfer of the specified transfer width 0x1: Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. 1 1 read-write FLOW_CTRL_MODE Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0x0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled 0x1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. 0 1 read-write PROT_CTRL Protection Control bits used to drive the AHB HPROT[3:1] bus. The AMBA Specification recommends that the default of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows • 0x1 to HPROT[0] • CFGx.PROTCTL[1] to HPROT[1] • CFGx.PROTCTL[2] to HPROT[2] • CFGx.PROTCTL[3] to HPROT[3] 2 3 read-write SRC_PER Source Hardware Interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0 otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 7 4 read-write CFG_CH4_LOW CFG_CH4_LOW Configuration Register for Channel 4 Low 32 bit 0x1A0 32 read-write n 0xE80 0xFFFFFFFF CH_PRIOR Channel Priority. A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the range 0 to 3. A programmed value outside this range will cause erroneous behavior. 0x0: Channel priority is 0 0x1: Channel priority is 1 0x2: Channel priority is 2 0x3: Channel priority is 3 5 3 read-write CH_SUSP Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFG_CHx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0x0: DMA transfer from the source is not suspended 0x1: Suspend DMA transfer from the source 8 1 read-write DEST_HSG_POL Destination Handshaking Interface Polarity. 0x0: Destination Handshaking Interface Polarity is Active high 0x1: Destination Handshaking Interface Polarity is Active low 18 1 read-write FIFO_EMPTY Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty 9 1 read-only HSG_SEL_DEST Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, then this bit is ignored. 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored. 10 1 read-write HSG_SEL_SRC Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFG_CHx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty 11 1 read-write RELOAD_DEST Automatic Destination Reload. The DEST_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Destination Reload Disabled. 0x1: Destination Reload Enabled 31 1 read-write RELOAD_SRC Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Source Reload Disabled 0x1: Source Reload Enabled 30 1 read-write SRC_HSG_POL Source Handshaking Interface Polarity. 0x0: Source Handshaking Interface Polarity is Active high 0x1: Source Handshaking Interface Polarity is Active low 19 1 read-write CFG_CH5_HIGH CFG_CH5_HIGH Configuration Register for Channel 5 High 32 bit 0x1FC 32 read-write n 0x4 0xFFFFFFFF DEST_PER Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFGx.HSG_SEL_DST field is 0 otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 11 4 read-write FIFO_MODE FIFO Mode Select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0x0: Space/data available for single AHB transfer of the specified transfer width 0x1: Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. 1 1 read-write FLOW_CTRL_MODE Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0x0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled 0x1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. 0 1 read-write PROT_CTRL Protection Control bits used to drive the AHB HPROT[3:1] bus. The AMBA Specification recommends that the default of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows • 0x1 to HPROT[0] • CFGx.PROTCTL[1] to HPROT[1] • CFGx.PROTCTL[2] to HPROT[2] • CFGx.PROTCTL[3] to HPROT[3] 2 3 read-write SRC_PER Source Hardware Interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0 otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 7 4 read-write CFG_CH5_LOW CFG_CH5_LOW Configuration Register for Channel 5 Low 32 bit 0x1F8 32 read-write n 0xEA0 0xFFFFFFFF CH_PRIOR Channel Priority. A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the range 0 to 3. A programmed value outside this range will cause erroneous behavior. 0x0: Channel priority is 0 0x1: Channel priority is 1 0x2: Channel priority is 2 0x3: Channel priority is 3 5 3 read-write CH_SUSP Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFG_CHx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0x0: DMA transfer from the source is not suspended 0x1: Suspend DMA transfer from the source 8 1 read-write DEST_HSG_POL Destination Handshaking Interface Polarity. 0x0: Destination Handshaking Interface Polarity is Active high 0x1: Destination Handshaking Interface Polarity is Active low 18 1 read-write FIFO_EMPTY Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty 9 1 read-only HSG_SEL_DEST Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, then this bit is ignored. 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored. 10 1 read-write HSG_SEL_SRC Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFG_CHx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty 11 1 read-write RELOAD_DEST Automatic Destination Reload. The DEST_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Destination Reload Disabled. 0x1: Destination Reload Enabled 31 1 read-write RELOAD_SRC Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Source Reload Disabled 0x1: Source Reload Enabled 30 1 read-write SRC_HSG_POL Source Handshaking Interface Polarity. 0x0: Source Handshaking Interface Polarity is Active high 0x1: Source Handshaking Interface Polarity is Active low 19 1 read-write CFG_CH6_HIGH CFG_CH6_HIGH Configuration Register for Channel 6 High 32 bit 0x254 32 read-write n 0x4 0xFFFFFFFF DEST_PER Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFGx.HSG_SEL_DST field is 0 otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 11 4 read-write FIFO_MODE FIFO Mode Select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0x0: Space/data available for single AHB transfer of the specified transfer width 0x1: Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. 1 1 read-write FLOW_CTRL_MODE Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0x0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled 0x1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. 0 1 read-write PROT_CTRL Protection Control bits used to drive the AHB HPROT[3:1] bus. The AMBA Specification recommends that the default of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows • 0x1 to HPROT[0] • CFGx.PROTCTL[1] to HPROT[1] • CFGx.PROTCTL[2] to HPROT[2] • CFGx.PROTCTL[3] to HPROT[3] 2 3 read-write SRC_PER Source Hardware Interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0 otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 7 4 read-write CFG_CH6_LOW CFG_CH6_LOW Configuration Register for Channel 6 low 32 bit 0x250 32 read-write n 0xEC0 0xFFFFFFFF CH_PRIOR Channel Priority. A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the range 0 to 3. A programmed value outside this range will cause erroneous behavior. 0x0: Channel priority is 0 0x1: Channel priority is 1 0x2: Channel priority is 2 0x3: Channel priority is 3 5 3 read-write CH_SUSP Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFG_CHx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0x0: DMA transfer from the source is not suspended 0x1: Suspend DMA transfer from the source 8 1 read-write DEST_HSG_POL Destination Handshaking Interface Polarity. 0x0: Destination Handshaking Interface Polarity is Active high 0x1: Destination Handshaking Interface Polarity is Active low 18 1 read-write FIFO_EMPTY Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty 9 1 read-only HSG_SEL_DEST Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, then this bit is ignored. 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored. 10 1 read-write HSG_SEL_SRC Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFG_CHx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty 11 1 read-write RELOAD_DEST Automatic Destination Reload. The DEST_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Destination Reload Disabled. 0x1: Destination Reload Enabled 31 1 read-write RELOAD_SRC Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Source Reload Disabled 0x1: Source Reload Enabled 30 1 read-write SRC_HSG_POL Source Handshaking Interface Polarity. 0x0: Source Handshaking Interface Polarity is Active high 0x1: Source Handshaking Interface Polarity is Active low 19 1 read-write CFG_CH7_HIGH CFG_CH7_HIGH Configuration Register for Channel 7 High 32 bit 0x2AC 32 read-write n 0x4 0xFFFFFFFF DEST_PER Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFGx.HSG_SEL_DST field is 0 otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 11 4 read-write FIFO_MODE FIFO Mode Select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0x0: Space/data available for single AHB transfer of the specified transfer width 0x1: Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. 1 1 read-write FLOW_CTRL_MODE Flow Control Mode. Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0x0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled 0x1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. 0 1 read-write PROT_CTRL Protection Control bits used to drive the AHB HPROT[3:1] bus. The AMBA Specification recommends that the default of HPROT indicates a non-cached, non-buffered, privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows • 0x1 to HPROT[0] • CFGx.PROTCTL[1] to HPROT[1] • CFGx.PROTCTL[2] to HPROT[2] • CFGx.PROTCTL[3] to HPROT[3] 2 3 read-write SRC_PER Source Hardware Interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0 otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. NOTE1: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. 7 4 read-write CFG_CH7_LOW CFG_CH7_LOW Configuration Register for Channel 7 Low 32 bit 0x2A8 32 read-write n 0xEE0 0xFFFFFFFF CH_PRIOR Channel Priority. A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the range 0 to 3. A programmed value outside this range will cause erroneous behavior. 0x0: Channel priority is 0 0x1: Channel priority is 1 0x2: Channel priority is 2 0x3: Channel priority is 3 5 3 read-write CH_SUSP Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFG_CHx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0x0: DMA transfer from the source is not suspended 0x1: Suspend DMA transfer from the source 8 1 read-write DEST_HSG_POL Destination Handshaking Interface Polarity. 0x0: Destination Handshaking Interface Polarity is Active high 0x1: Destination Handshaking Interface Polarity is Active low 18 1 read-write FIFO_EMPTY Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty 9 1 read-only HSG_SEL_DEST Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, then this bit is ignored. 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored. 10 1 read-write HSG_SEL_SRC Channel FIFO status. Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFG_CHx.CH_SUSP to cleanly disable a channel. 0x0: Channel FIFO is not empty 0x1: Channel FIFO is empty 11 1 read-write RELOAD_DEST Automatic Destination Reload. The DEST_ADDR_CHx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Destination Reload Disabled. 0x1: Destination Reload Enabled 31 1 read-write RELOAD_SRC Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. 0x0: Source Reload Disabled 0x1: Source Reload Enabled 30 1 read-write SRC_HSG_POL Source Handshaking Interface Polarity. 0x0: Source Handshaking Interface Polarity is Active high 0x1: Source Handshaking Interface Polarity is Active low 19 1 read-write CFG_HIGH CFG_HIGH DMA Configuration Register High 32 bit 0x39C 32 read-write n 0x0 0xFFFFFFFF CFG_LOW CFG_LOW DMA Configuration Register Low 32 bit 0x398 32 read-write n 0x0 0xFFFFFFFF DMA_EN DMA Enable bit. 0x0: DMA Disabled 0x1: DMA Enabled Volatile: true 0 1 read-write CH_EN_HIGH CH_EN_HIGH DMA Channel Enable Register High 32 bit 0x3A4 32 read-write n 0x0 0xFFFFFFFF CH_EN_LOW CH_EN_LOW DMA Channel Enable Register Low 32 bit 0x3A0 32 read-write n 0x0 0xFFFFFFFF CH_EN Channel Enable. The CH_EN.CH_EN bit is automatically cleared by hardware to disable the channel after the last AMBA transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer. 0x0: Disable the channel 0x1: Enable the channel Volatile: true 0 4 read-write CH_EN_WE Channel enable register Volatile: true 8 4 write-only CTRL_CH0_HIGH CTRL_CH0_HIGH Control Register for Channel 0 High 32 bit 0x1C 32 read-write n 0x2 0xFFFFFFFF BLOCK_XFE_SIZE Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_TR_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what is the flow controller. When the source or destination peripheral is assigned as the flow controller, then the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true 0 5 read-write DONE Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx [63:32], is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer is complete. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize=2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. For more information, refer to Multi-Block Transfers . Volatile: true 12 1 read-write CTRL_CH0_LOW CTRL_CH0_LOW Control Register for Channel 0 Low 32 bit 0x18 32 read-write n 0x304801 0xFFFFFFFF DEST_ADDR_INC Destination Address Increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No Change . 0x0: Increments the destination address 0x1: Decrements the destination address 0x2: No change in the destination address 0x3: No change in the destination address Volatile: true 7 2 read-write DEST_MSIZE Destination Burst Transaction Length. Number of data items, each of width CTRL_CHx.DEST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true 11 3 read-write DEST_XFE_WIDTH Destination Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. 0x0: Destination transfer width is 8 bits 0x1: Destination transfer width is 16 bits 0x2: Destination transfer width is 32 bits Volatile: true 1 3 read-write INT_EN Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel raw* interrupt registers still assert if CTRLx.INT_EN=0. 0x0: Interrupt is disabled 0x1: Interrupt is enabled Volatile: true 0 1 read-write SRC_ADDR_INC Source Address Increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change . 0x0: Increments the source address 0x1: Decrements the source address 0x2: No change in the source address 0x3: No change in the source address Volatile: true 9 2 read-write SRC_MSIZE Source Burst Transaction Length. Number of data items, each of width CTRL_CHx.SRC_TR_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true 14 3 read-write SRC_XFE_WIDTH Source Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. 0x0: Source transfer width is 8 bits 0x1: Source transfer width is 16 bits 0x2: Source transfer width is 32 bits Volatile: true 4 3 read-write XFE_TYPE_FC Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. • 0x0: Transfer type is Memory to Memory and Flow Controller is DMA • 0x1: Transfer type is Memory to Peripheral and Flow Controller is DMA • 0x2: Transfer type is Peripheral to Memory and Flow Controller is DMA • 0x3: Transfer type is Peripheral to Peripheral and Flow Controller is DMA Volatile: true 20 3 read-write CTRL_CH1_HIGH CTRL_CH1_HIGH Control Register for Channel 1 High 32 bit 0x74 32 read-write n 0x2 0xFFFFFFFF BLOCK_XFE_SIZE Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_TR_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what is the flow controller. When the source or destination peripheral is assigned as the flow controller, then the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true 0 5 read-write DONE Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx [63:32], is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer is complete. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize=2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. For more information, refer to Multi-Block Transfers . Volatile: true 12 1 read-write CTRL_CH1_LOW CTRL_CH1_LOW Control Register for Channel 1 Low 32 bit 0x70 32 read-write n 0x304801 0xFFFFFFFF DEST_ADDR_INC Destination Address Increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No Change . 0x0: Increments the destination address 0x1: Decrements the destination address 0x2: No change in the destination address 0x3: No change in the destination address Volatile: true 7 2 read-write DEST_MSIZE Destination Burst Transaction Length. Number of data items, each of width CTRL_CHx.DEST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true 11 3 read-write DEST_XFE_WIDTH Destination Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. 0x0: Destination transfer width is 8 bits 0x1: Destination transfer width is 16 bits 0x2: Destination transfer width is 32 bits Volatile: true 1 3 read-write INT_EN Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel raw* interrupt registers still assert if CTRLx.INT_EN=0. 0x0: Interrupt is disabled 0x1: Interrupt is enabled Volatile: true 0 1 read-write SRC_ADDR_INC Source Address Increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change . 0x0: Increments the source address 0x1: Decrements the source address 0x2: No change in the source address 0x3: No change in the source address Volatile: true 9 2 read-write SRC_MSIZE Source Burst Transaction Length. Number of data items, each of width CTRL_CHx.SRC_TR_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true 14 3 read-write SRC_XFE_WIDTH Source Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. 0x0: Source transfer width is 8 bits 0x1: Source transfer width is 16 bits 0x2: Source transfer width is 32 bits Volatile: true 4 3 read-write XFE_TYPE_FC Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. • 0x0: Transfer type is Memory to Memory and Flow Controller is DMA • 0x1: Transfer type is Memory to Peripheral and Flow Controller is DMA • 0x2: Transfer type is Peripheral to Memory and Flow Controller is DMA • 0x3: Transfer type is Peripheral to Peripheral and Flow Controller is DMA Volatile: true 20 3 read-write CTRL_CH2_HIGH CTRL_CH2_HIGH Control Register for Channel 2 High 32 bit 0xCC 32 read-write n 0x2 0xFFFFFFFF BLOCK_XFE_SIZE Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_TR_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what is the flow controller. When the source or destination peripheral is assigned as the flow controller, then the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true 0 5 read-write DONE Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx [63:32], is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer is complete. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize=2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. For more information, refer to Multi-Block Transfers . Volatile: true 12 1 read-write CTRL_CH2_LOW CTRL_CH2_LOW Control Register for Channel 2 Low 32 bit 0xC8 32 read-write n 0x304801 0xFFFFFFFF DEST_ADDR_INC Destination Address Increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No Change . 0x0: Increments the destination address 0x1: Decrements the destination address 0x2: No change in the destination address 0x3: No change in the destination address Volatile: true 7 2 read-write DEST_MSIZE Destination Burst Transaction Length. Number of data items, each of width CTRL_CHx.DEST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true 11 3 read-write DEST_XFE_WIDTH Destination Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. 0x0: Destination transfer width is 8 bits 0x1: Destination transfer width is 16 bits 0x2: Destination transfer width is 32 bits Volatile: true 1 3 read-write INT_EN Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel raw* interrupt registers still assert if CTRLx.INT_EN=0. 0x0: Interrupt is disabled 0x1: Interrupt is enabled Volatile: true 0 1 read-write SRC_ADDR_INC Source Address Increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change . 0x0: Increments the source address 0x1: Decrements the source address 0x2: No change in the source address 0x3: No change in the source address Volatile: true 9 2 read-write SRC_MSIZE Source Burst Transaction Length. Number of data items, each of width CTRL_CHx.SRC_TR_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true 14 3 read-write SRC_XFE_WIDTH Source Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. 0x0: Source transfer width is 8 bits 0x1: Source transfer width is 16 bits 0x2: Source transfer width is 32 bits Volatile: true 4 3 read-write XFE_TYPE_FC Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. • 0x0: Transfer type is Memory to Memory and Flow Controller is DMA • 0x1: Transfer type is Memory to Peripheral and Flow Controller is DMA • 0x2: Transfer type is Peripheral to Memory and Flow Controller is DMA • 0x3: Transfer type is Peripheral to Peripheral and Flow Controller is DMA Volatile: true 20 3 read-write CTRL_CH3_HIGH CTRL_CH3_HIGH Control Register for Channel 3 High 32 bit 0x124 32 read-write n 0x2 0xFFFFFFFF BLOCK_XFE_SIZE Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_TR_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what is the flow controller. When the source or destination peripheral is assigned as the flow controller, then the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true 0 5 read-write DONE Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx [63:32], is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer is complete. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize=2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. For more information, refer to Multi-Block Transfers . Volatile: true 12 1 read-write CTRL_CH3_LOW CTRL_CH3_LOW Control Register for Channel 3 Low 32 bit 0x120 32 read-write n 0x304801 0xFFFFFFFF DEST_ADDR_INC Destination Address Increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No Change . 0x0: Increments the destination address 0x1: Decrements the destination address 0x2: No change in the destination address 0x3: No change in the destination address Volatile: true 7 2 read-write DEST_MSIZE Destination Burst Transaction Length. Number of data items, each of width CTRL_CHx.DEST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true 11 3 read-write DEST_XFE_WIDTH Destination Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. 0x0: Destination transfer width is 8 bits 0x1: Destination transfer width is 16 bits 0x2: Destination transfer width is 32 bits Volatile: true 1 3 read-write INT_EN Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel raw* interrupt registers still assert if CTRLx.INT_EN=0. 0x0: Interrupt is disabled 0x1: Interrupt is enabled Volatile: true 0 1 read-write SRC_ADDR_INC Source Address Increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change . 0x0: Increments the source address 0x1: Decrements the source address 0x2: No change in the source address 0x3: No change in the source address Volatile: true 9 2 read-write SRC_MSIZE Source Burst Transaction Length. Number of data items, each of width CTRL_CHx.SRC_TR_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true 14 3 read-write SRC_XFE_WIDTH Source Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. 0x0: Source transfer width is 8 bits 0x1: Source transfer width is 16 bits 0x2: Source transfer width is 32 bits Volatile: true 4 3 read-write XFE_TYPE_FC Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. • 0x0: Transfer type is Memory to Memory and Flow Controller is DMA • 0x1: Transfer type is Memory to Peripheral and Flow Controller is DMA • 0x2: Transfer type is Peripheral to Memory and Flow Controller is DMA • 0x3: Transfer type is Peripheral to Peripheral and Flow Controller is DMA Volatile: true 20 3 read-write CTRL_CH4_HIGH CTRL_CH4_HIGH Control Register for Channel 4 High 32 bit 0x17C 32 read-write n 0x2 0xFFFFFFFF BLOCK_XFE_SIZE Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_TR_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what is the flow controller. When the source or destination peripheral is assigned as the flow controller, then the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true 0 5 read-write DONE Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx [63:32], is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer is complete. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize=2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. For more information, refer to Multi-Block Transfers . Volatile: true 12 1 read-write CTRL_CH4_LOW CTRL_CH4_LOW Control Register for Channel 4 Low 32 bit 0x178 32 read-write n 0x304801 0xFFFFFFFF DEST_ADDR_INC Destination Address Increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No Change . 0x0: Increments the destination address 0x1: Decrements the destination address 0x2: No change in the destination address 0x3: No change in the destination address Volatile: true 7 2 read-write DEST_MSIZE Destination Burst Transaction Length. Number of data items, each of width CTRL_CHx.DEST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true 11 3 read-write DEST_XFE_WIDTH Destination Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. 0x0: Destination transfer width is 8 bits 0x1: Destination transfer width is 16 bits 0x2: Destination transfer width is 32 bits Volatile: true 1 3 read-write INT_EN Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel raw* interrupt registers still assert if CTRLx.INT_EN=0. 0x0: Interrupt is disabled 0x1: Interrupt is enabled Volatile: true 0 1 read-write SRC_ADDR_INC Source Address Increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change . 0x0: Increments the source address 0x1: Decrements the source address 0x2: No change in the source address 0x3: No change in the source address Volatile: true 9 2 read-write SRC_MSIZE Source Burst Transaction Length. Number of data items, each of width CTRL_CHx.SRC_TR_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true 14 3 read-write SRC_XFE_WIDTH Source Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. 0x0: Source transfer width is 8 bits 0x1: Source transfer width is 16 bits 0x2: Source transfer width is 32 bits Volatile: true 4 3 read-write XFE_TYPE_FC Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. • 0x0: Transfer type is Memory to Memory and Flow Controller is DMA • 0x1: Transfer type is Memory to Peripheral and Flow Controller is DMA • 0x2: Transfer type is Peripheral to Memory and Flow Controller is DMA • 0x3: Transfer type is Peripheral to Peripheral and Flow Controller is DMA Volatile: true 20 3 read-write CTRL_CH5_HIGH CTRL_CH5_HIGH Control Register for Channel 5 High 32 bit 0x1D4 32 read-write n 0x2 0xFFFFFFFF BLOCK_XFE_SIZE Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_TR_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what is the flow controller. When the source or destination peripheral is assigned as the flow controller, then the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true 0 5 read-write DONE Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx [63:32], is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer is complete. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize=2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. For more information, refer to Multi-Block Transfers . Volatile: true 12 1 read-write CTRL_CH5_LOW CTRL_CH5_LOW Control Register for Channel 5 Low 32 bit 0x1D0 32 read-write n 0x304801 0xFFFFFFFF DEST_ADDR_INC Destination Address Increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No Change . 0x0: Increments the destination address 0x1: Decrements the destination address 0x2: No change in the destination address 0x3: No change in the destination address Volatile: true 7 2 read-write DEST_MSIZE Destination Burst Transaction Length. Number of data items, each of width CTRL_CHx.DEST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true 11 3 read-write DEST_XFE_WIDTH Destination Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. 0x0: Destination transfer width is 8 bits 0x1: Destination transfer width is 16 bits 0x2: Destination transfer width is 32 bits Volatile: true 1 3 read-write INT_EN Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel raw* interrupt registers still assert if CTRLx.INT_EN=0. 0x0: Interrupt is disabled 0x1: Interrupt is enabled Volatile: true 0 1 read-write SRC_ADDR_INC Source Address Increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change . 0x0: Increments the source address 0x1: Decrements the source address 0x2: No change in the source address 0x3: No change in the source address Volatile: true 9 2 read-write SRC_MSIZE Source Burst Transaction Length. Number of data items, each of width CTRL_CHx.SRC_TR_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true 14 3 read-write SRC_XFE_WIDTH Source Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. 0x0: Source transfer width is 8 bits 0x1: Source transfer width is 16 bits 0x2: Source transfer width is 32 bits Volatile: true 4 3 read-write XFE_TYPE_FC Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. • 0x0: Transfer type is Memory to Memory and Flow Controller is DMA • 0x1: Transfer type is Memory to Peripheral and Flow Controller is DMA • 0x2: Transfer type is Peripheral to Memory and Flow Controller is DMA • 0x3: Transfer type is Peripheral to Peripheral and Flow Controller is DMA Volatile: true 20 3 read-write CTRL_CH6_HIGH CTRL_CH6_HIGH Control Register for Channel 6 High 32 bit 0x22C 32 read-write n 0x2 0xFFFFFFFF BLOCK_XFE_SIZE Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_TR_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what is the flow controller. When the source or destination peripheral is assigned as the flow controller, then the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true 0 5 read-write DONE Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx [63:32], is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer is complete. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize=2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. For more information, refer to Multi-Block Transfers . Volatile: true 12 1 read-write CTRL_CH6_LOW CTRL_CH6_LOW Control Register for Channel 6 Low 32 bit 0x228 32 read-write n 0x4801 0xFFFFFFFF DEST_ADDR_INC Destination Address Increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No Change . 0x0: Increments the destination address 0x1: Decrements the destination address 0x2: No change in the destination address 0x3: No change in the destination address Volatile: true 7 2 read-write DEST_MSIZE Destination Burst Transaction Length. Number of data items, each of width CTRL_CHx.DEST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true 11 3 read-write DEST_XFE_WIDTH Destination Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. 0x0: Destination transfer width is 8 bits 0x1: Destination transfer width is 16 bits 0x2: Destination transfer width is 32 bits Volatile: true 1 3 read-write INT_EN Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel raw* interrupt registers still assert if CTRLx.INT_EN=0. 0x0: Interrupt is disabled 0x1: Interrupt is enabled Volatile: true 0 1 read-write SRC_ADDR_INC Source Address Increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change . 0x0: Increments the source address 0x1: Decrements the source address 0x2: No change in the source address 0x3: No change in the source address Volatile: true 9 2 read-write SRC_MSIZE Source Burst Transaction Length. Number of data items, each of width CTRL_CHx.SRC_TR_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true 14 3 read-write SRC_XFE_WIDTH Source Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. 0x0: Source transfer width is 8 bits 0x1: Source transfer width is 16 bits 0x2: Source transfer width is 32 bits Volatile: true 4 3 read-write XFE_TYPE_FC Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. • 0x0: Transfer type is Memory to Memory and Flow Controller is DMA • 0x1: Transfer type is Memory to Peripheral and Flow Controller is DMA • 0x2: Transfer type is Peripheral to Memory and Flow Controller is DMA • 0x3: Transfer type is Peripheral to Peripheral and Flow Controller is DMA Volatile: true 20 3 read-write CTRL_CH7_HIGH CTRL_CH7_HIGH Control Register for Channel 7 High 32 bit 0x284 32 read-write n 0x2 0xFFFFFFFF BLOCK_XFE_SIZE Block Transfer Size. When the DMA is the flow controller, the user writes this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_TR_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what is the flow controller. When the source or destination peripheral is assigned as the flow controller, then the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true 0 5 read-write DONE Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx [63:32], is written to the control register location of the Linked List Item (LLI) in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer is complete. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize=2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. For more information, refer to Multi-Block Transfers . Volatile: true 12 1 read-write CTRL_CH7_LOW CTRL_CH7_LOW Control Register for Channel 7 Low 32 bit 0x280 32 read-write n 0x304801 0xFFFFFFFF DEST_ADDR_INC Destination Address Increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to No Change . 0x0: Increments the destination address 0x1: Decrements the destination address 0x2: No change in the destination address 0x3: No change in the destination address Volatile: true 7 2 read-write DEST_MSIZE Destination Burst Transaction Length. Number of data items, each of width CTRL_CHx.DEST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true 11 3 read-write DEST_XFE_WIDTH Destination Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. 0x0: Destination transfer width is 8 bits 0x1: Destination transfer width is 16 bits 0x2: Destination transfer width is 32 bits Volatile: true 1 3 read-write INT_EN Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel raw* interrupt registers still assert if CTRLx.INT_EN=0. 0x0: Interrupt is disabled 0x1: Interrupt is enabled Volatile: true 0 1 read-write SRC_ADDR_INC Source Address Increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change . 0x0: Increments the source address 0x1: Decrements the source address 0x2: No change in the source address 0x3: No change in the source address Volatile: true 9 2 read-write SRC_MSIZE Source Burst Transaction Length. Number of data items, each of width CTRL_CHx.SRC_TR_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. NOTE: This value is not related to the AHB bus master HBURST bus. 0x0: Number of data items to be transferred is 1 0x1: Number of data items to be transferred is 4 0x2: Number of data items to be transferred is 8 Volatile: true 14 3 read-write SRC_XFE_WIDTH Source Transfer Width. Mapped to AHB bus hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. 0x0: Source transfer width is 8 bits 0x1: Source transfer width is 16 bits 0x2: Source transfer width is 32 bits Volatile: true 4 3 read-write XFE_TYPE_FC Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. • 0x0: Transfer type is Memory to Memory and Flow Controller is DMA • 0x1: Transfer type is Memory to Peripheral and Flow Controller is DMA • 0x2: Transfer type is Peripheral to Memory and Flow Controller is DMA • 0x3: Transfer type is Peripheral to Peripheral and Flow Controller is DMA Volatile: true 20 3 read-write DEST_ADDR_CH0_HIGH DEST_ADDR_CH0_HIGH Destination Address Register for Channel 0 High 32 bit 0xC 32 read-write n 0x0 0xFFFFFFFF DEST_ADDR_CH0_LOW DEST_ADDR_CH0_LOW Destination Address Register for Channel 0 Low 32 bit 0x8 32 read-write n 0x0 0xFFFFFFFF DEST_ADDR Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true 0 32 read-write DEST_ADDR_CH1_HIGH DEST_ADDR_CH1_HIGH Destination Address Register for Channel 1 High 32 bit 0x64 32 read-write n 0x0 0xFFFFFFFF DEST_ADDR_CH1_LOW DEST_ADDR_CH1_LOW Destination Address Register for Channel 1 Low 32 bit 0x60 32 read-write n 0x0 0xFFFFFFFF DEST_ADDR Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true 0 32 read-write DEST_ADDR_CH2_HIGH DEST_ADDR_CH2_HIGH Destination Address Register for Channel 2 High 32 bit 0xBC 32 read-write n 0x0 0xFFFFFFFF DEST_ADDR_CH2_LOW DEST_ADDR_CH2_LOW Destination Address Register for Channel 2 Low 32 bit 0xB8 32 read-write n 0x0 0xFFFFFFFF DEST_ADDR Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true 0 32 read-write DEST_ADDR_CH3_HIGH DEST_ADDR_CH3_HIGH Destination Address Register for Channel 3 High 32 bit 0x114 32 read-write n 0x0 0xFFFFFFFF DEST_ADDR_CH3_LOW DEST_ADDR_CH3_LOW Destination Address Register for Channel 3 Low 32 bit 0x110 32 read-write n 0x0 0xFFFFFFFF DEST_ADDR Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true 0 32 read-write DEST_ADDR_CH4_HIGH DEST_ADDR_CH4_HIGH Destination Address Register for Channel 4 High 32 bit 0x16C 32 read-write n 0x0 0xFFFFFFFF DEST_ADDR_CH4_LOW DEST_ADDR_CH4_LOW Destination Address Register for Channel 4 Low 32 bit 0x168 32 read-write n 0x0 0xFFFFFFFF DEST_ADDR Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true 0 32 read-write DEST_ADDR_CH5_HIGH DEST_ADDR_CH5_HIGH Destination Address Register for Channel 5 High 32 bit 0x1C4 32 read-write n 0x0 0xFFFFFFFF DEST_ADDR_CH5_LOW DEST_ADDR_CH5_LOW Destination Address Register for Channel 5 Low 32 bit 0x1C0 32 read-write n 0x0 0xFFFFFFFF DEST_ADDR Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true 0 32 read-write DEST_ADDR_CH6_HIGH DEST_ADDR_CH6_HIGH Destination Address Register for Channel 6 High 32bit 0x21C 32 read-write n 0x0 0xFFFFFFFF DEST_ADDR_CH6_LOW DEST_ADDR_CH6_LOW Destination Address Register for Channel 6 Low 32bit 0x218 32 read-write n 0x0 0xFFFFFFFF DEST_ADDR Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true 0 32 read-write DEST_ADDR_CH7_HIGH DEST_ADDR_CH7_HIGH Destination Address Register for Channel 7 High 32 bit 0x274 32 read-write n 0x0 0xFFFFFFFF DEST_ADDR_CH7_LOW DEST_ADDR_CH7_LOW Destination Address Register for Channel 7 Low 32 bit 0x270 32 read-write n 0x0 0xFFFFFFFF DEST_ADDR Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true 0 32 read-write INT_CLR_BTC_HIGH INT_CLR_BTC_HIGH Clear for Block Transfer Complete Interrupt High 32 bit 0x344 32 read-write n 0x0 0xFFFFFFFF INT_CLR_BTC_LOW INT_CLR_BTC_LOW Clear for Block Transfer Complete Interrupt Low 32 bit 0x340 32 write-only n 0x0 0xFFFFFFFF CLR Clear for Block Transfer Complete Interrupt Volatile: true 0 4 write-only INT_CLR_DTC_HIGH INT_CLR_DTC_HIGH Clear for Destination Transaction Complete Interrupt High 32 bit 0x354 32 read-write n 0x0 0xFFFFFFFF INT_CLR_DTC_LOW INT_CLR_DTC_LOW Clear for Destination Transaction Complete Interrupt Low 32 bit 0x350 32 write-only n 0x0 0xFFFFFFFF CLR Clear for Destination Transaction Complete Interrupt 0x0: No effect 0x1: Clears interrupts Volatile: true 0 4 write-only INT_CLR_ERR_HIGH INT_CLR_ERR_HIGH Clear for Error Interrupt High 32 bit 0x35C 32 read-write n 0x0 0xFFFFFFFF INT_CLR_ERR_LOW INT_CLR_ERR_LOW Clear for Error Interrupt Low 32 bit 0x358 32 write-only n 0x0 0xFFFFFFFF CLR Clear for Error Interrupt 0x0: No effect 0x1: Clears interrupts Volatile: true 0 4 write-only INT_CLR_STC_HIGH INT_CLR_STC_HIGH Clear for Source Transaction Complete Interrupt High 32 bit 0x34C 32 read-write n 0x0 0xFFFFFFFF INT_CLR_STC_LOW INT_CLR_STC_LOW Clear for Source Transaction Complete Interrupt Low 32 bit 0x348 32 write-only n 0x0 0xFFFFFFFF CLR Clear for Source Transaction Complete Interrupt 0x0: No effect 0x1: Clears interrupts Volatile: true 0 4 write-only INT_CLR_TC_HIGH INT_CLR_TC_HIGH Clear for Transfer Complete Interrupt High 32 bit 0x33C 32 read-write n 0x0 0xFFFFFFFF INT_CLR_TC_LOW INT_CLR_TC_LOW Clear for Transfer Complete Interrupt Low 32 bit 0x338 32 write-only n 0x0 0xFFFFFFFF CLR Clear for Transfer Complete Interrupt 0x0: No effect 0x1: Clears interrupts Volatile: true 0 4 write-only INT_MASK_BTC_HIGH INT_MASK_BTC_HIGH Mask for Block Transfer Complete Interrupt High 32 bit 0x31C 32 read-write n 0x0 0xFFFFFFFF INT_MASK_BTC_LOW INT_MASK_BTC_LOW Mask for Block Transfer Complete Interrupt Low 32 bit 0x318 32 read-write n 0x0 0xFFFFFFFF INT_MASK Mask for Block Transfer Complete Interrupt 0x0: Mask the interrupts 0x1: Unmask the interrupts 0 4 read-write INT_MASK_WE Interrupt Mask Write Enable 0x0: Interrupt mask write disable 0x1: Interrupt mask write enable 8 4 write-only INT_MASK_DTC_HIGH INT_MASK_DTC_HIGH Mask for Destination Transaction Complete Interrupt High 32 bit 0x32C 32 read-write n 0x0 0xFFFFFFFF INT_MASK_DTC_LOW INT_MASK_DTC_LOW Mask for Destination Transaction Complete Interrupt Low 32 bit 0x328 32 read-write n 0x0 0xFFFFFFFF INT_MASK Mask for Destination Transaction Complete Interrupt 0x0: Mask the interrupts 0x1: Unmask the interrupts 0 4 read-write INT_MASK_WE Interrupt Mask Write Enable 0x0: Interrupt mask write disable 0x1: Interrupt mask write enable 8 4 write-only INT_MASK_ERR_HIGH INT_MASK_ERR_HIGH Mask for Error Interrupt High 32 bit 0x334 32 read-write n 0x0 0xFFFFFFFF INT_MASK_ERR_LOW INT_MASK_ERR_LOW Mask for Error Interrupt Low 32 bit 0x330 32 read-write n 0x0 0xFFFFFFFF INT_MASK Mask for Error Interrupt 0x0: Mask the interrupts 0x1: Unmask the interrupts 0 4 read-write INT_MASK_WE Interrupt Mask Write Enable 0x0: Interrupt mask write disable 0x1: Interrupt mask write enable 8 4 write-only INT_MASK_STC_HIGH INT_MASK_STC_HIGH Mask for Source Transaction Complete Interrupt High 32 bit 0x324 32 read-write n 0x0 0xFFFFFFFF INT_MASK_STC_LOW INT_MASK_STC_LOW Mask for Source Transaction Complete Interrupt Low 32 bit 0x320 32 read-write n 0x0 0xFFFFFFFF INT_MASK Mask for Source Transaction Complete Interrupt 0x0: Mask the interrupts 0x1: Unmask the interrupts 0 4 read-write INT_MASK_WE Interrupt Mask Write Enable 0x0: Interrupt mask write disable 0x1: Interrupt mask write enable 8 4 write-only INT_MASK_TC_HIGH INT_MASK_TC_HIGH Mask for Transfer Complete Interrupt High 32 bit 0x314 32 read-write n 0x0 0xFFFFFFFF INT_MASK_TC_LOW INT_MASK_TC_LOW Mask for Transfer Complete Interrupt Low 32 bit 0x310 32 read-write n 0x0 0xFFFFFFFF INT_MASK Mask for Transfer Complete Interrupt 0x0: Mask the interrupts 0x1: Unmask the interrupts 0 4 read-write INT_MASK_WE Interrupt Mask Write Enable 0x0: Interrupt mask write disable 0x1: Interrupt mask write enable 8 4 write-only INT_RSTAT_BTC_HIGH INT_RSTAT_BTC_HIGH Raw Status for Block Transfer Complete Interrupt High 32 bit 0x2CC 32 read-write n 0x0 0xFFFFFFFF INT_RSTAT_BTC_LOW INT_RSTAT_BTC_LOW Raw Status for Block Transfer Complete Interrupt Low 32 bit 0x2C8 32 read-write n 0x0 0xFFFFFFFF RAW Raw Status for Block Transfer Complete Interrupt 0x0: Inactive Raw Interrupt Status 0x1: Active Raw Interrupt Status Volatile: true 0 4 read-write INT_RSTAT_DTC_HIGH INT_RSTAT_DTC_HIGH Raw Status for Destination Transaction Complete Interrupt High 32 bit 0x2DC 32 read-write n 0x0 0xFFFFFFFF INT_RSTAT_DTC_LOW INT_RSTAT_DTC_LOW Raw Status for Destination Transaction Complete Interrupt Low 32 bit 0x2D8 32 read-write n 0x0 0xFFFFFFFF RAW Raw Status for Destination Transaction Complete Interrupt 0x0: Inactive Raw Interrupt Status 0x1: Active Raw Interrupt Status 0 4 read-write INT_RSTAT_ERR_HIGH INT_RSTAT_ERR_HIGH Raw Status for Error Interrupt High 32 bit 0x2E4 32 read-write n 0x0 0xFFFFFFFF INT_RSTAT_ERR_LOW INT_RSTAT_ERR_LOW Raw Status for Error Interrupt Low 32 bit 0x2E0 32 read-write n 0x0 0xFFFFFFFF RAW Raw Status for Error Interrupt 0x0: Inactive Raw Interrupt Status 0x1: Active Raw Interrupt Status Volatile: true 0 4 read-write INT_RSTAT_STC_HIGH INT_RSTAT_STC_HIGH Raw Status for Source Transaction Complete Interrupt High 32 bit 0x2D4 32 read-write n 0x0 0xFFFFFFFF INT_RSTAT_STC_LOW INT_RSTAT_STC_LOW Raw Status for Source Transaction Complete Interrupt Low 32 bit 0x2D0 32 read-write n 0x0 0xFFFFFFFF RAW Raw Status for Source Transaction Complete Interrupt 0x0: Inactive Raw Interrupt Status 0x1: Active Raw Interrupt Status Volatile: true 0 4 read-write INT_RSTAT_TC_HIGH INT_RSTAT_TC_HIGH Raw Status for Transfer Complete Interrupt High 32 bit 0x2C4 32 read-write n 0x0 0xFFFFFFFF INT_RSTAT_TC_LOW INT_RSTAT_TC_LOW Raw Status for Transfer Complete Interrupt Low 32 bit 0x2C0 32 read-write n 0x0 0xFFFFFFFF RAW Raw Status for Transfer Complete Interrupt 0x0: Inactive Raw Interrupt Status 0x1: Active Raw Interrupt Status Volatile: true 0 4 read-write INT_STAT_BTC_HIGH INT_STAT_BTC_HIGH Status for Block Transfer Complete Interrupt High 32 bit 0x2F4 32 read-write n 0x0 0xFFFFFFFF INT_STAT_BTC_LOW INT_STAT_BTC_LOW Status for Block Transfer Complete Interrupt Low 32 bit 0x2F0 32 read-only n 0x0 0xFFFFFFFF STAT Status for Block Transfer Complete Interrupt 0x0: Inactive Interrupt Status 0x1: Active Interrupt Status Volatile: true 0 4 read-only INT_STAT_DTC_HIGH INT_STAT_DTC_HIGH Status for Destination Transaction Complete Interrupt High 32 bit 0x304 32 read-write n 0x0 0xFFFFFFFF INT_STAT_DTC_LOW INT_STAT_DTC_LOW Status for Destination Transaction Complete Interrupt Low 32 bit 0x300 32 read-only n 0x0 0xFFFFFFFF STAT Status for Destination Transaction Complete Interrupt 0x0: Inactive Interrupt Status 0x1: Active Interrupt Status 0 4 read-only INT_STAT_ERR_HIGH INT_STAT_ERR_HIGH Status for Error Interrupt High 32 bit 0x30C 32 read-write n 0x0 0xFFFFFFFF INT_STAT_ERR_LOW INT_STAT_ERR_LOW Status for Error Interrupt Low 32 bit 0x308 32 read-only n 0x0 0xFFFFFFFF STAT Status for Error Interrupt 0x0: Inactive Interrupt Status 0x1: Active Interrupt Status Volatile: true 0 4 read-only INT_STAT_ET_HIGH INT_STAT_ET_HIGH Status for each Interrupt type High 32 bit 0x364 32 read-write n 0x0 0xFFFFFFFF INT_STAT_ET_LOW INT_STAT_ET_LOW Status for each Interrupt type Low 32 bit 0x360 32 read-only n 0x0 0xFFFFFFFF BLK_XFE_CPLT OR of the contents of INT_STAT_BTC register 0x0: OR of the contents of INT_STAT_BTC register is 0 0x1: OR of the contents of INT_STAT_BTC register is 1 Volatile: true 1 1 read-only DEST_XFE_CPLT OR of the contents of INT_STAT_DTC register 0x0: OR of the contents of INT_STAT_DTC register is 0 0x1: OR of the contents of INT_STAT_DTC register is 1 Volatile: true 3 1 read-only ERR OR of the contents of INT_STAT_ERR register 0x0: OR of the contents of INT_STAT_ERR register is 0 0x1: OR of the contents of INT_STAT_ERR register is 1 Volatile: true 4 1 read-only SRC_XFE_CPLT OR of the contents of INT_STAT_STC register 0x0: OR of the contents of INT_STAT_STC register is 0 0x1: OR of the contents of INT_STAT_STC register is 1 Volatile: true 2 1 read-only XFE_CPLT OR of the contents of INT_STAT_TC register 0x0: OR of the contents of INT_STAT_TC register is 0 0x1: OR of the contents of INT_STAT_TC register is 1 Volatile: true 0 1 read-only INT_STAT_STC_HIGH INT_STAT_STC_HIGH Status for Source Transaction Complete Interrupt High 32 bit 0x2FC 32 read-write n 0x0 0xFFFFFFFF INT_STAT_STC_LOW INT_STAT_STC_LOW Status for Source Transaction Complete Interrupt Low 32 bit 0x2F8 32 read-only n 0x0 0xFFFFFFFF STAT Status for Source Transaction Complete Interrupt 0x0: Inactive Interrupt Status 0x1: Active Interrupt Status Volatile: true 0 4 read-only INT_STAT_TC_HIGH INT_STAT_TC_HIGH Status for Transfer Complete Interrupt High 32 bit 0x2EC 32 read-write n 0x0 0xFFFFFFFF INT_STAT_TC_LOW INT_STAT_TC_LOW Status for Transfer Complete Interrupt Low 32 bit 0x2E8 32 read-only n 0x0 0xFFFFFFFF STAT Status for Transfer Complete Interrupt 0x0: Inactive Interrupt Status 0x1: Active Interrupt Status Volatile:true 0 4 read-only REQ_DST_HIGH REQ_DST_HIGH Destination Software Transaction Request register High 32 bit 0x374 32 read-write n 0x0 0xFFFFFFFF REQ_DST_LOW REQ_DST_LOW Destination Software Transaction Request register Low 32 bit 0x370 32 read-write n 0x0 0xFFFFFFFF DEST_REQ Destination Software Transaction Request 0x0: Destination request is not active 0x1: Destination request is active 0 4 read-write DEST_REQ_WE Destination Software Transaction Request write enable 0x0: Destination request write Disable 0x1: Destination request write Enable 8 4 read-write REQ_LST_DT_HIGH REQ_LST_DT_HIGH Destination Last Transaction Request register High 32 bit 0x394 32 read-write n 0x0 0xFFFFFFFF REQ_LST_DT_LOW REQ_LST_DT_LOW Destination Last Transaction Request register Low 32 bit 0x390 32 read-write n 0x0 0xFFFFFFFF LST_DEST Destination Last Transaction Request 0x0: Not last transaction in current block 0x1: Last transaction in current block 0 4 read-write LST_DEST_WE Source Last Transaction Request write enable 0x0: Destination last transaction request write disable 0x1: Destination last transaction request write enable 8 4 read-write REQ_LST_ST_HIGH REQ_LST_ST_HIGH Source Last Transaction Request register High 32 bit 0x38C 32 read-write n 0x0 0xFFFFFFFF REQ_LST_ST_LOW REQ_LST_ST_LOW Source Last Transaction Request register Low 32 bit 0x388 32 read-write n 0x0 0xFFFFFFFF LST_SRC Source Last Transaction Request register 0x0: Not last transaction in current block 0x1: Last transaction in current block 0 4 read-write LST_SRC_WE Source Last Transaction Request write enable 0x0: Source last transaction request write disable 0x1: Source last transaction request write enable 8 4 read-write REQ_SGL_DT_HIGH REQ_SGL_DT_HIGH Destination Single Transaction Request register High 32 bit 0x384 32 read-write n 0x0 0xFFFFFFFF REQ_SGL_DT_LOW REQ_SGL_DT_LOW Destination Single Transaction Request register Low 32 bit 0x380 32 read-write n 0x0 0xFFFFFFFF DEST_SGL_REQ Destination Single Transaction Request 0x0: Destination Single or burst request is not active 0x1: Destination Single or burst request is active 0 4 read-write DST_SGL_REQ_WE Destination Single Transaction Request write enable 0x0: Destination write Disable 0x1: Destination write Enable 8 4 read-write REQ_SGL_ST_HIGH REQ_SGL_ST_HIGH Source Single Transaction Request register High 32 bit 0x37C 32 read-write n 0x0 0xFFFFFFFF REQ_SGL_ST_LOW REQ_SGL_ST_LOW Source Single Transaction Request register Low 32 bit 0x378 32 read-write n 0x0 0xFFFFFFFF SRC_SGL_REQ Source Single Transaction Request 0x0: Source request is not active 0x1: Source request is active 0 4 read-write SRC_SGL_REQ_WE Source Single Transaction Request write enable 0x0: Single write Disable 0x1: Single write Enable 8 4 read-write REQ_SST_HIGH REQ_SST_HIGH Source Software Transaction Request register High 32 bit 0x36C 32 read-write n 0x0 0xFFFFFFFF REQ_SST_LOW REQ_SST_LOW Source Software Transaction Request register Low 32 bit 0x368 32 read-write n 0x0 0xFFFFFFFF SRC_REQ Source Software Transaction Request 0x0: Source request is not active 0x1: Source request is active 0 4 read-write SRC_REQ_WE Source Software Transaction Request write enable 0x0: Source request write Disable 0x1: Source request write Enable 8 4 read-write SRC_ADDR_CH0_HIGH SRC_ADDR_CH0_HIGH Source Address for Channel 0 High 32 bit 0x4 32 read-write n 0x0 0xFFFFFFFF SRC_ADDR_CH0_LOW SRC_ADDR_CH0_LOW Source Address for Channel 0 LOW 32 bit 0x0 32 read-write n 0x0 0xFFFFFFFF SRC_ADDR Current Source Address of DMA transfer. Updated after each source transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true 0 32 read-write SRC_ADDR_CH1_HIGH SRC_ADDR_CH1_HIGH Source Address for Channel 1 High 32 bit 0x5C 32 read-write n 0x0 0xFFFFFFFF SRC_ADDR_CH1_LOW SRC_ADDR_CH1_LOW Source Address for Channel 1 LOW 32 bit 0x58 32 read-write n 0x0 0xFFFFFFFF SRC_ADDR Current Source Address of DMA transfer. Updated after each source transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true 0 32 read-write SRC_ADDR_CH2_HIGH SRC_ADDR_CH2_HIGH Source Address for Channel 2 High 32 bit 0xB4 32 read-write n 0x0 0xFFFFFFFF SRC_ADDR_CH2_LOW SRC_ADDR_CH2_LOW Source Address for Channel 2 LOW 32 bit 0xB0 32 read-write n 0x0 0xFFFFFFFF SRC_ADDR Current Source Address of DMA transfer. Updated after each source transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true 0 32 read-write SRC_ADDR_CH3_HIGH SRC_ADDR_CH3_HIGH Source Address for Channel 3 High 32 bit 0x10C 32 read-write n 0x0 0xFFFFFFFF SRC_ADDR_CH3_LOW SRC_ADDR_CH3_LOW Source Address for Channel 3 LOW 32 bit 0x108 32 read-write n 0x0 0xFFFFFFFF SRC_ADDR Current Source Address of DMA transfer. Updated after each source transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true 0 32 read-write SRC_ADDR_CH4_HIGH SRC_ADDR_CH4_HIGH Source Address for Channel 4 High 32 bit 0x164 32 read-write n 0x0 0xFFFFFFFF SRC_ADDR_CH4_LOW SRC_ADDR_CH4_LOW Source Address for Channel 4 LOW 32 bit 0x160 32 read-write n 0x0 0xFFFFFFFF SRC_ADDR Current Source Address of DMA transfer. Updated after each source transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true 0 32 read-write SRC_ADDR_CH5_LOW SRC_ADDR_CH5_LOW Source Address for Channel 5 LOW 32 bit 0x1B8 32 read-write n 0x0 0xFFFFFFFF SRC_ADDR Current Source Address of DMA transfer. Updated after each source transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true 0 32 read-write SRC_ADDR_CH5__HIGH SRC_ADDR_CH5__HIGH Source Address for Channel 5 High 32 bit 0x1BC 32 read-write n 0x0 0xFFFFFFFF SRC_ADDR_CH6_HIGH SRC_ADDR_CH6_HIGH Source Address for Channel 6 High 32 bit 0x214 32 read-write n 0x0 0xFFFFFFFF SRC_ADDR_CH6_LOW SRC_ADDR_CH6_LOW Source Address for Channel 6 Low 32 bit 0x210 32 read-write n 0x0 0xFFFFFFFF SRC_ADDR Current Source Address of DMA transfer. Updated after each source transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true 0 32 read-write SRC_ADDR_CH7_HIGH SRC_ADDR_CH7_HIGH Source Address for Channel 7 High 32 bit 0x26C 32 read-write n 0x0 0xFFFFFFFF SRC_ADDR_CH7_LOW SRC_ADDR_CH7_LOW Source Address for Channel 7 Low 32 bit 0x268 32 read-write n 0x0 0xFFFFFFFF SRC_ADDR Current Source Address of DMA transfer. Updated after each source transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true 0 32 read-write DUAL_TIMER0 Dual-Timer DUAL_TIMER 0xA0002000 0x0 0x18 registers n CTRL CTRL Dula-Timer Control Register 0x8 32 read-write n 0x20 0xFFFFFFFF COUNT_MODE Selects one-shot or wrapping counter mode: 0x0: Wrapping mode, default. 0x1: One-shot mode. 0 1 read-write EN Timer Enable 0x0: Timer disabled, default. 0x1: Timer enabled. 7 1 read-write INT_EN Interrupt Enable 0x0: Timer Interrupt disabled. 0x1: Timer Interrupt enabled, default. 5 1 read-write MODE Timer Mode 0x0: Timer is in free-running mode, default. 0x1: Timer is in periodic mode. 6 1 read-write PRE Prescale bits: 0x00: 0 stages of prescale, clock is divided by 1, default. 0x01: 4 stages of prescale, clock is divided by 16. 0x10: 8 stages of prescale, clock is divided by 256. 0x11: Undefined, do not use. 2 2 read-write SIZE Selects 16-bit or 32-bit counter operation: 0x0: 16-bit counter, default. 0x1: 32-bit counter 1 1 read-write INT_CLR INT_CLR Dula-Timer Interrupt Clear Register 0xC 32 write-only n 0x0 0xFFFFFFFF STAT Clear the Dual-Timer interrupt event. 0 32 write-only INT_RSTAT INT_RSTAT Dula-Timer Raw Interrupt Status Register 0x10 32 read-write n 0x0 0xFFFFFFFF STAT Raw interrupt status from the counter. 0 1 read-write INT_STAT INT_STAT Dula-Timer Raw Interrupt Status Register 0x14 32 read-write n 0x0 0xFFFFFFFF STAT Enable interrupt status from the counter. 0 1 read-write LOAD LOAD Dula-Timer Load Register 0x0 32 read-write n 0x0 0xFFFFFFFF COUNT Reload value. Write to this register sets the current value 0 32 read-write VAL VAL Dula-Timer Current Value Register 0x4 32 read-only n 0xFFFFFFFF 0xFFFFFFFF COUNT Current value. 0 32 read-only DUAL_TIMER1 Dual-Timer DUAL_TIMER 0xA0002020 0x0 0x18 registers n CTRL CTRL Dula-Timer Control Register 0x8 32 read-write n 0x20 0xFFFFFFFF COUNT_MODE Selects one-shot or wrapping counter mode: 0x0: Wrapping mode, default. 0x1: One-shot mode. 0 1 read-write EN Timer Enable 0x0: Timer disabled, default. 0x1: Timer enabled. 7 1 read-write INT_EN Interrupt Enable 0x0: Timer Interrupt disabled. 0x1: Timer Interrupt enabled, default. 5 1 read-write MODE Timer Mode 0x0: Timer is in free-running mode, default. 0x1: Timer is in periodic mode. 6 1 read-write PRE Prescale bits: 0x00: 0 stages of prescale, clock is divided by 1, default. 0x01: 4 stages of prescale, clock is divided by 16. 0x10: 8 stages of prescale, clock is divided by 256. 0x11: Undefined, do not use. 2 2 read-write SIZE Selects 16-bit or 32-bit counter operation: 0x0: 16-bit counter, default. 0x1: 32-bit counter 1 1 read-write INT_CLR INT_CLR Dula-Timer Interrupt Clear Register 0xC 32 write-only n 0x0 0xFFFFFFFF STAT Clear the Dual-Timer interrupt event. 0 32 write-only INT_RSTAT INT_RSTAT Dula-Timer Raw Interrupt Status Register 0x10 32 read-write n 0x0 0xFFFFFFFF STAT Raw interrupt status from the counter. 0 1 read-write INT_STAT INT_STAT Dula-Timer Raw Interrupt Status Register 0x14 32 read-write n 0x0 0xFFFFFFFF STAT Enable interrupt status from the counter. 0 1 read-write LOAD LOAD Dula-Timer Load Register 0x0 32 read-write n 0x0 0xFFFFFFFF COUNT Reload value. Write to this register sets the current value 0 32 read-write VAL VAL Dula-Timer Current Value Register 0x4 32 read-only n 0xFFFFFFFF 0xFFFFFFFF COUNT Current value. 0 32 read-only GPIO0 General Purpose Input Output GPIO 0xA0010000 0x0 0x34 registers n EXT0 GPIO_0~GPIO15 interrupts 6 EXT1 GPIO_16~GPIO31 interrupts 7 GPIOx_ALTFUNC_CLR GPIOx_ALTFUNC_CLR GPIO alternative function enable clear register 0x1C 32 read-write n 0x0 0xFFFFFFFF CLR GPIO alternative function enable clear: Write 0x1: Clears the ALTFUNC bit. 0x0: No effect. Read 0x0: For I/O. 0x1: For an alternate function. 0 16 read-write GPIOx_ALTFUNC_EN GPIOx_ALTFUNC_EN GPIO alternative function enable register 0x18 32 read-write n 0x0 0xFFFFFFFF EN GPIO alternative function enable: Write: 0x1: Sets the ALTFUNC bit. 0x0: No effect. Read: 0x0: For I/O. 0x1: For an alternate function. 0 16 read-write GPIOx_DATA GPIOx_DATA GPIO data value register 0x0 32 read-write n 0x0 0xFFFFFFFF DATA GPIO read value: Read: Sampled at pin. Write: To data output register. Read back value goes through double flip-flop synchronization logic with a delay of two cycles. 0 16 read-write GPIOx_DATA_OUT GPIOx_DATA_OUT GPIO data output value register 0x4 32 read-write n 0x0 0xFFFFFFFF DATA_OUT GPIO output value: Read: Current value of data output register. Write: To data output register. 0 16 read-write GPIOx_INT_CLR GPIOx_INT_CLR GPIO interrupt enable clear register 0x24 32 read-write n 0x0 0xFFFFFFFF CLR GPIO interrupt enable clear: Write: 0x1: Clear the enable bit. 0x0: No effect. Read: 0x0: Interrupt disabled. 0x1: Interrupt enabled. 0 16 read-write GPIOx_INT_EN GPIOx_INT_EN GPIO interrupt enable register 0x20 32 read-write n 0x0 0xFFFFFFFF EN GPIO interrupt enable: Write: 0x1: Sets the enable bit. 0x0: No effect. Read: 0x0: Interrupt disabled. 0x1: Interrupt enabled. 0 16 read-write GPIOx_INT_POL_CLR GPIOx_INT_POL_CLR GPIO polarity-level, edge IRQ configuration clear register 0x34 32 read-write n 0x0 0xFFFFFFFF EN GPIO polarity-level, edge IRQ enable clear: Write 0x1: Clears the interrupt polarity bit. 0x0: No effect. Read 0x0: For LOW level or falling edge. 0x1: For HIGH level or rising edge. 0 16 read-write GPIOx_INT_POL_EN GPIOx_INT_POL_EN GPIO polarity-level, edge IRQ configuration register 0x30 32 read-write n 0x0 0xFFFFFFFF EN GPIO polarity-level, edge IRQ enable: Write 0x1: Sets the interrupt polarity bit. 0x0: No effect. Read 0x0: For LOW level or falling edge. 0x1: For HIGH level or rising edge. 0 16 read-write GPIOx_INT_STAT GPIOx_INT_STAT GPIO IRQ status register 0x38 32 read-write n 0x0 0xFFFFFFFF STAT_CLR Write one to clear interrupt. Read one to get interrupt status. Write 0x1: To clear the interrupt request. 0x0: No effect. Read IRQ status Register. 0 16 read-write GPIOx_INT_TYPE_CLR GPIOx_INT_TYPE_CLR GPIO interrupt type enable clear register 0x2C 32 read-write n 0x0 0xFFFFFFFF CLR GPIO interrupt type enable clear: Write: 0x1: Clears the interrupt type bit. 0x0: No effect. Read: 0x0: For LOW or HIGH level. 0x1: For falling edge or rising edge. 0 16 read-write GPIOx_INT_TYPE_EN GPIOx_INT_TYPE_EN GPIO interrupt type enable register 0x28 32 read-write n 0x0 0xFFFFFFFF EN GPIO interrupt type enable: Write 0x1: Sets the interrupt type bit. 0x0: No effect. Read 0x0: For LOW or HIGH level. 0x1: For falling edge or rising edge. 0 16 read-write GPIOx_OUT_CLR GPIOx_OUT_CLR GPIO output enable clear register 0x14 32 read-write n 0x0 0xFFFFFFFF CLR GPIO output enable clear: Write: 0x1: Clears the output enable bit. 0x0: No effect. Read: 0x0: Indicates the signal, direction as input. 0x1: Indicates the signal, direction as output. 0 16 read-write GPIOx_OUT_EN GPIOx_OUT_EN GPIO output enable register 0x10 32 read-write n 0x0 0xFFFFFFFF EN GPIO output enable: Write 0x1: Set the output enable bit. 0x0: No effect. Read 0x0: Indicates the signal, direction as input. 0x1: Indicates the signal, direction as output. 0 16 read-write GPIO1 General Purpose Input Output GPIO 0xA0011000 0x0 0x34 registers n EXT0 GPIO_0~GPIO15 interrupts 6 EXT1 GPIO_16~GPIO31 interrupts 7 GPIOx_ALTFUNC_CLR GPIOx_ALTFUNC_CLR GPIO alternative function enable clear register 0x1C 32 read-write n 0x0 0xFFFFFFFF CLR GPIO alternative function enable clear: Write 0x1: Clears the ALTFUNC bit. 0x0: No effect. Read 0x0: For I/O. 0x1: For an alternate function. 0 16 read-write GPIOx_ALTFUNC_EN GPIOx_ALTFUNC_EN GPIO alternative function enable register 0x18 32 read-write n 0x0 0xFFFFFFFF EN GPIO alternative function enable: Write: 0x1: Sets the ALTFUNC bit. 0x0: No effect. Read: 0x0: For I/O. 0x1: For an alternate function. 0 16 read-write GPIOx_DATA GPIOx_DATA GPIO data value register 0x0 32 read-write n 0x0 0xFFFFFFFF DATA GPIO read value: Read: Sampled at pin. Write: To data output register. Read back value goes through double flip-flop synchronization logic with a delay of two cycles. 0 16 read-write GPIOx_DATA_OUT GPIOx_DATA_OUT GPIO data output value register 0x4 32 read-write n 0x0 0xFFFFFFFF DATA_OUT GPIO output value: Read: Current value of data output register. Write: To data output register. 0 16 read-write GPIOx_INT_CLR GPIOx_INT_CLR GPIO interrupt enable clear register 0x24 32 read-write n 0x0 0xFFFFFFFF CLR GPIO interrupt enable clear: Write: 0x1: Clear the enable bit. 0x0: No effect. Read: 0x0: Interrupt disabled. 0x1: Interrupt enabled. 0 16 read-write GPIOx_INT_EN GPIOx_INT_EN GPIO interrupt enable register 0x20 32 read-write n 0x0 0xFFFFFFFF EN GPIO interrupt enable: Write: 0x1: Sets the enable bit. 0x0: No effect. Read: 0x0: Interrupt disabled. 0x1: Interrupt enabled. 0 16 read-write GPIOx_INT_POL_CLR GPIOx_INT_POL_CLR GPIO polarity-level, edge IRQ configuration clear register 0x34 32 read-write n 0x0 0xFFFFFFFF EN GPIO polarity-level, edge IRQ enable clear: Write 0x1: Clears the interrupt polarity bit. 0x0: No effect. Read 0x0: For LOW level or falling edge. 0x1: For HIGH level or rising edge. 0 16 read-write GPIOx_INT_POL_EN GPIOx_INT_POL_EN GPIO polarity-level, edge IRQ configuration register 0x30 32 read-write n 0x0 0xFFFFFFFF EN GPIO polarity-level, edge IRQ enable: Write 0x1: Sets the interrupt polarity bit. 0x0: No effect. Read 0x0: For LOW level or falling edge. 0x1: For HIGH level or rising edge. 0 16 read-write GPIOx_INT_STAT GPIOx_INT_STAT GPIO IRQ status register 0x38 32 read-write n 0x0 0xFFFFFFFF STAT_CLR Write one to clear interrupt. Read one to get interrupt status. Write 0x1: To clear the interrupt request. 0x0: No effect. Read IRQ status Register. 0 16 read-write GPIOx_INT_TYPE_CLR GPIOx_INT_TYPE_CLR GPIO interrupt type enable clear register 0x2C 32 read-write n 0x0 0xFFFFFFFF CLR GPIO interrupt type enable clear: Write: 0x1: Clears the interrupt type bit. 0x0: No effect. Read: 0x0: For LOW or HIGH level. 0x1: For falling edge or rising edge. 0 16 read-write GPIOx_INT_TYPE_EN GPIOx_INT_TYPE_EN GPIO interrupt type enable register 0x28 32 read-write n 0x0 0xFFFFFFFF EN GPIO interrupt type enable: Write 0x1: Sets the interrupt type bit. 0x0: No effect. Read 0x0: For LOW or HIGH level. 0x1: For falling edge or rising edge. 0 16 read-write GPIOx_OUT_CLR GPIOx_OUT_CLR GPIO output enable clear register 0x14 32 read-write n 0x0 0xFFFFFFFF CLR GPIO output enable clear: Write: 0x1: Clears the output enable bit. 0x0: No effect. Read: 0x0: Indicates the signal, direction as input. 0x1: Indicates the signal, direction as output. 0 16 read-write GPIOx_OUT_EN GPIOx_OUT_EN GPIO output enable register 0x10 32 read-write n 0x0 0xFFFFFFFF EN GPIO output enable: Write 0x1: Set the output enable bit. 0x0: No effect. Read 0x0: Indicates the signal, direction as input. 0x1: Indicates the signal, direction as output. 0 16 read-write HMAC Hash Message Authentication Code HMAC 0xA0015800 0x0 0x6C registers n HMAC HMAC interrupt 17 CFG CFG HMAC Configuration Register 0x4 32 read-write n 0x0 0xFFFFFFFF CALC_TYPE Select calculation type 0x0: HMAC 0x1: SHA 4 1 read-write ENDIAN Selection for endian ctrl 0x0: Reverse to big_endian(default) 0x1: No reverse 1 1 read-write HASH Select enable for user define hash 0x0: initial hash from standard(default) 0x1: user defined initial hash enable 0 1 read-write KEY_TYPE Select key type 0x0: Configured by MCU 0x1: Fetched through AHB interface 0x2: Fetched through key port 0x3: Reserved 2 2 read-write PRIVT_MOD To resist DPA, need to select private mode 0x0: Standard mode 0x1: Private mode 5 1 read-write CTRL CTRL HMAC Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF DMA_START DMA mode start enable. Starting DMA transfer, this signal should be cleared after DMA have finished all transfer 1 1 read-write EN HMAC enable, high valid for whole HMAC processing, user must disable it once all block HMAC completes. This signal should be asserted until all blocks completes 0 1 read-write KEY_EN Enable HMAC fetch key by itself through AHB master interface or key port. This signal may be cleared by itself when aes_key_valid was set 2 1 write-only LST_TX Last block in MCU model or last DMA transfer. This signal may be cleared by itself when hmac_ready was set 3 1 write-only DATA_IN DATA_IN HMAC Data Input Register 0x44 32 write-only n 0x0 0xFFFFFFFF DATA MCU mode, user can configure input data with this register: 32-bit data should be sent 16/17 times. 0 32 write-only DATA_OUT DATA_OUT HMAC Data Output Register 0x40 32 read-only n 0x0 0xFFFFFFFF DATA MCU mode, user can read out result with this register: When all blocks of message were processed, 256 bit HMAC data should be read out 8/9 times. And HMAC data can be read when hmac_ready is valid. 0 32 read-only INT INT HMAC Interrupt Register 0x10 32 read-write n 0x0 0xFFFFFFFF DONE HMAC result data complete interrupt flag. Write 1 to clear. Read 0x0: Not interrupt 0x1: Interrupt Write 0x0: Not effect 0x1: Clear 0 1 read-write EN HMAC result data complete interrupt enable. 0x0: Disable 0x1: Enable 1 1 read-write KEY0 KEY0 HMAC Key 0 Register 0x48 32 write-only n 0x0 0xFFFFFFFF KEY0 Key was set as 256 bits (8 WORDs ), WORD_0 0 32 write-only KEY1 KEY1 HMAC Key 1 Register 0x4C 32 write-only n 0x0 0xFFFFFFFF KEY1 Key was set as 256 bits (8 WORDs ), WORD_1 0 32 write-only KEY2 KEY2 HMAC Key 2 Register 0x50 32 write-only n 0x0 0xFFFFFFFF KEY2 Key was set as 256 bits (8 WORDs ), WORD_2 0 32 write-only KEY3 KEY3 HMAC Key 3 Register 0x54 32 write-only n 0x0 0xFFFFFFFF KEY3 Key was set as 256 bits (8 WORDs ), WORD_3 0 32 write-only KEY4 KEY4 HMAC Key 4 Register 0x58 32 write-only n 0x0 0xFFFFFFFF KEY4 Key was set as 256 bits (8 WORDs ), WORD_4 0 32 write-only KEY5 KEY5 HMAC Key 5 Register 0x5C 32 write-only n 0x0 0xFFFFFFFF KEY5 Key was set as 256 bits (8 WORDs ), WORD_5 0 32 write-only KEY6 KEY6 HMAC Key 6 Register 0x60 32 write-only n 0x0 0xFFFFFFFF KEY6 Key was set as 256 bits (8 WORDs ), WORD_6 0 32 write-only KEY7 KEY7 HMAC Key 7 Register 0x64 32 write-only n 0x0 0xFFFFFFFF KEY7 Key was set as 256 bits (8 WORDs ), WORD_7 0 32 write-only KEYPORT_MASK KEYPORT_MASK HMAC Keyport Mask Register 0x6C 32 write-only n 0x0 0xFFFFFFFF MASK Mask for key from keyport 0 32 write-only KEY_ADDR KEY_ADDR HMAC Key Addr Register 0x68 32 read-write n 0x0 0xFFFFFFFF KEY_ADDR HMAC key address in memory 0 32 read-write RD_START_ADDR RD_START_ADDR HMAC Read Start Address Register 0x14 32 read-write n 0x0 0xFFFFFFFF ADDR DMA mode, read start address of transfer 0 32 read-write STAT STAT HMAC Status Register 0x8 32 read-write n 0x0 0xFFFFFFFF DMA_MSG_DONE If the number of all block message bigger than transfer size, it indicates all block message was sent when this signal was set 1 1 read-only DMA_TX_DONE HMAC dma transfer done or not 5 1 read-write DMA_TX_ERR HMAC DMA transfer error. Write 1 to clear 2 1 read-write HASH_READY Hash process status 0x0: Result data is not ready 0x1: Result data is valid 0 1 read-only HMAC_READY HMAC process status 0x0: Result data is not ready 0x1: Result data is valid 4 1 read-write KEY_VALID Hmac has fetched key or not 3 1 read-only USER_HASH_0 USER_HASH_0 HMAC User Hash 0 Register 0x20 32 read-write n 0x0 0xFFFFFFFF HASH_0 If HASH is selected, you can configure user defined hash with USER_HASH_0 /1/2/3/4/5/6/7. User defined hash value[255:224] 0 32 read-write USER_HASH_1 USER_HASH_1 HMAC User Hash 1 Register 0x24 32 read-write n 0x0 0xFFFFFFFF HASH_1 If HASH is selected, you can configure user defined hash with USER_HASH_0/1/2/3/4/5/6/7. User defined hash value[223:192] 0 32 read-write USER_HASH_2 USER_HASH_2 HMAC User Hash 2 Register 0x28 32 read-write n 0x0 0xFFFFFFFF HASH_2 If HASH is selected, you can configure user defined hash with USER_HASH_0 /1/2/3/4/5/6/7. User defined hash value[191:160] 0 32 read-write USER_HASH_3 USER_HASH_3 HMAC User Hash 3 Register 0x2C 32 read-write n 0x0 0xFFFFFFFF HASH_3 If HASH is selected, you can configure user defined hash with USER_HASH_0 /1/2/3/4/5/6/7. User defined hash value[159:128] 0 32 read-write USER_HASH_4 USER_HASH_4 HMAC User Hash 4 Register 0x30 32 read-write n 0x0 0xFFFFFFFF HASH_4 If HASH is selected, you can configure user defined hash with USER_HASH_0 /1/2/3/4/5/6/7. User defined hash value[127:96] 0 32 read-write USER_HASH_5 USER_HASH_5 HMAC User Hash 5 Register 0x34 32 read-write n 0x0 0xFFFFFFFF HASH_5 If HASH is selected, you can configure user defined hash with USER_HASH_0 /1/2/3/4/5/6/7. User defined hash value[95:64] 0 32 read-write USER_HASH_6 USER_HASH_6 HMAC User Hash 6 Register 0x38 32 read-write n 0x0 0xFFFFFFFF HASH_6 If HASH is selected, you can configure user defined hash with USER_HASH_0 /1/2/3/4/5/6/7. User defined hash value[63:32] 0 32 read-write USER_HASH_7 USER_HASH_7 HMAC User Hash 7 Register 0x3C 32 read-write n 0x0 0xFFFFFFFF HASH_7 If HASH is selected, you can configure user defined hash with USER_HASH_0 /1/2/3/4/5/6/7. User defined hash value[31:0] 0 32 read-write WR_START_ADDR WR_START_ADDR HMAC Write Start Address Register 0x18 32 read-write n 0x0 0xFFFFFFFF ADDR DMA mode, write start address of transfer 0 32 read-write XFE_SIZE XFE_SIZE HMAC Transfer Size Register 0xC 32 read-write n 0x0 0xFFFFFFFF SIZE Total transfer size, up to 32KB 0x003F: 1 block 0x007F: 2 block 0x00BF: 3 block - 0x7FFF: 512 block 0 15 read-write I2C0 The Inter-Integrated Circuit (I2C) bus is a two-wire serial interface I2C 0xA000C300 0x0 0xA4 registers n I2C0 I2C0 interrupt 14 I2C1 I2C1 interrupt 15 ACK_GEN_CALL ACK_GEN_CALL I2C ACK General Call Register 0x98 32 read-write n 0x1 0xFFFFFFFF ACK_GEN_CALL ACK General Call. When set to 1, I2C responds with an ACK (by asserting data_oe) when it receives a General Call. Otherwise, I2C responds with a NACK (by negating data_oe). 0x0: Generate NACK for General Call 0x1: Generate ACK for a General Call 0 1 read-write CLR_ACTIVITY CLR_ACTIVITY Clear ACTIVITY Interrupt Register 0x5C 32 read-only n 0x0 0xFFFFFFFF CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the RAW_INT_STAT register. 0 1 read-only CLR_GEN_CALL CLR_GEN_CALL Clear GEN_CALL Interrupt Register 0x68 32 read-only n 0x0 0xFFFFFFFF CLR_GEN_CALL Read this register to clear the GEN_CALL interrupt (bit 11) of RAW_INT_STAT register. 0 1 read-only CLR_INT CLR_INT Clear Combined and Individual Interrupt Register 0x40 32 read-only n 0x0 0xFFFFFFFF CLR_INT Read this register to clear the combined interrupt, all individual interrupts, and the TX_ABORT_SRC register. This bit does not clear hardware clearable interrupts but software clearable interrupts. 0 1 read-only CLR_RD_REQ CLR_RD_REQ Clear RD_REQ Interrupt Register 0x50 32 read-only n 0x0 0xFFFFFFFF CLR_RD_REQ Read this register to clear the RD_REQ interrupt (bit 5) of the RAW_INT_STAT register. 0 1 read-only CLR_RX_DONE CLR_RX_DONE Clear RX_DONE Interrupt Register 0x58 32 read-only n 0x0 0xFFFFFFFF CLR_RX_DONE Read this register to clear the RX_DONE interrupt (bit 7) of the RAW_INT_STAT register. 0 1 read-only CLR_RX_OVER CLR_RX_OVER Clear RX_OVER Interrupt Register 0x48 32 read-only n 0x0 0xFFFFFFFF CLR_RX_OVER Read this register to clear the RX_OVER interrupt (bit 1) of the RAW_INT_STAT register 0 1 read-only CLR_RX_UNDER CLR_RX_UNDER Clear RX_UNDER Interrupt Register 0x44 32 read-only n 0x0 0xFFFFFFFF CLR_RX_UNDER Read this register to clear the RX_UNDER interrupt (bit 0) of the RAW_INT_STAT register 0 1 read-only CLR_START_DET CLR_START_DET Clear START_DET Interrupt Register 0x64 32 read-only n 0x0 0xFFFFFFFF CLR_START_DET Read this register to clear the START_DET interrupt (bit 10) of the RAW_INT_STAT register. 0 1 read-only CLR_STOP_DET CLR_STOP_DET Clear STOP_DET Interrupt Register 0x60 32 read-only n 0x0 0xFFFFFFFF CLR_STOP_DET Read this register to clear the STOP_DET interrupt (bit 9) of the RAW_INT_STAT register. 0 1 read-only CLR_TX_ABORT CLR_TX_ABORT Clear TX_ABORT Interrupt Register 0x54 32 read-only n 0x0 0xFFFFFFFF CLR_TX_ABORT Read this register to clear the TX_ABORT interrupt (bit 6) of the RAW_INT_STAT register, and the TX_ABORT_SRC register. 0 1 read-only CLR_TX_OVER CLR_TX_OVER Clear TX_OVER Interrupt Register 0x4C 32 read-only n 0x0 0xFFFFFFFF CLR_TX_OVER Read this register to clear the TX_OVER interrupt (bit 2) of the RAW_INT_STAT register 0 1 read-only CTRL CTRL I2C Control Register 0x0 32 read-write n 0x7F 0xFFFFFFFF ADDR_BIT_M When acting as a master, this bit controls whether the I2C starts its transfers in 7-bit or 10-bit addressing mode. 0x0: Master 7Bit addressing mode 0x1: Master 10Bit addressing mode 4 1 read-write ADDR_BIT_S When acting as a slave, this bit controls whether the I2C responds to 7- or 10-bit addresses. 0x0: Slave 7Bit addressing 0x1: Slave 10Bit addressing 3 1 read-write M_MODE This bit controls whether the I2C master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. 0x0: Master mode is disabled 0x1: Master mode is enabled 0 1 read-write RESTART_EN Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions however, RESTART conditions are used in several I2C operations. When RESTART is disabled, the master is prohibited from performing the following functions: • Sending a START BYTE • Performing any high-speed mode operation • High-speed mode operation • Performing direction changes in combined format mode • Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple I2C transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABORT) of the RAW_INTR_STAT register. 0x0: Master restart disabled 0x1: Master restart enabled 5 1 read-write SPEED These bits control at which speed the I2C operates its setting is relevant only if one is operating the I2C in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to 3. 0x1: Standard Speed mode of operation(100 kbit/s) 0x2: Fast( ≤400 kbit/s) or Fast Plus(≤1000Kbit/s) mode of operation 0x3: High Speed mode of operation(3.4 Mbit/s) 1 2 read-write STOP_DET_INT In slave mode 0x0: Issues the STOP_DET irrespective of whether it's addressed or not 0x1: Issues the STOP_DET interrrupt only when it is addressed NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_INT = 1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (S_ADDR). 0x0: Slave issues STOP_DET intr always 0x1: Slave issues STOP_DET intr only if addressed 7 1 read-write STOP_DET_M_ACTIVE In Master mode 0x1: issues the STOP_DET interrupt only when master is active. 0x0: issues the STOP_DET irrespective of whether master is active or not. 0x1: Master issues the STOP_DET interrupt only when master is active 0x0: Master issues the STOP_DET interrupt irrespective of whether master is active or not 10 1 read-write S_DIS This bit controls whether I2C has its slave disabled. By default, the slave is always disabled (in reset state as well). If you need to enable it after reset, set this bit to 0. If this bit is set (slave is disabled), I2C functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. Value: 0x0: Slave mode is enabled 0x1: Slave mode is disabled 6 1 read-write TX_EMPTY_CTRL This bit controls the generation of the TX_EMPTY interrupt, as described in the RAW_INTR_STAT register. 0x0: Default disable behaviour of TX_EMPTY interrupt 0x1: Controlled enable generation of TX_EMPTY interrupt 8 1 read-write DATA_CMD DATA_CMD I2C RX/TX Data Buffer and Command Register 0x10 32 read-write n 0x0 0xFFFFFFFF CMD This bit controls whether a read or a write is performed. This bit does not control the direction when the I2C acts as a slave. It controls only the direction when it acts as a master. 0x0: Master Write command 0x1: Master Read command 8 1 read-write DATA This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DATA) are ignored by the I2C. However, when you read this register, these bits return the value of data received on the I2C interface. 0 8 read-write DMA_CTRL DMA_CTRL DMA Control Register 0x88 32 read-write n 0x0 0xFFFFFFFF RX_EN Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. 0x0: Receive FIFO DMA channel disabled 0x1: Receive FIFO DMA channel enabled 0 1 read-write TX_EN Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. 0x0: Transmit FIFO DMA channel disabled 0x1: Transmit FIFO DMA channel enabled 1 1 read-write DMA_RX_LEVEL DMA_RX_LEVEL DMA Receive Data Level Register 0x90 32 read-write n 0x0 0xFFFFFFFF LEVEL Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. 0 3 read-write DMA_TX_LEVEL DMA_TX_LEVEL DMA Transmit Data Level Register 0x8C 32 read-write n 0x0 0xFFFFFFFF LEVEL Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. 0 3 read-write EN EN I2C ENABLE Register 0x6C 32 read-write n 0x0 0xFFFFFFFF ABORT When set, the controller initiates the transfer abort. The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the TX FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. 0x0: ABORT operation not in progress 0x1: ABORT operation in progress 1 1 read-write ACTIVITY Controls whether the I2C is enabled. Software can disable I2C while it is active. However, it is important that care be taken to ensure that I2C is disabled properly. A recommended procedure is described in Disabling I2C . When I2C is disabled, the following occurs: The TX FIFO and RX FIFO get flushed. Status bits in the INTR_STAT register are still active until I2C goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the I2C stops the current transfer at the end of the current byte and does not acknowledge the transfer. 0x0: I2C is disabled 0x1: I2C is enabled 0 1 read-only TX_CMD_BLOCK In Master mode 0x0: TX Command execution not blocked 0x1: TX Command execution blocked 2 1 read-write EN_STAT EN_STAT I2C Enable Status Register 0x9C 32 read-only n 0x0 0xFFFFFFFF EN EN Status. This bit always reflects the value driven on the output port en. When read as 1, I2C is deemed to be in an enabled state. When read as 0, I2C is deemed completely inactive. Note:The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read S_RX_DATA_LOST (bit 2) and S_DIS_BUSY (bit 1). 0x0: I2C disabled 0x1: I2C enabled 0 1 read-only S_DIS_BUSY Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the ENregister from 1 to 0. This bit is set when the CPU writes a 0 to the EN register while • I2C is receiving the address byte of the Slave-Transmitter operation from a remote master or • Address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, I2C is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in I2C (S_ADDR register) OR if the transfer is completed before ENABLE is set to 0 but has not taken effect. Note: If the remote I2C master terminates the transfer with a STOP condition before the I2C has a chance to NACK a transfer, and EN[0] has been set to 0, then this bit will also be set to 1. When read as 0, I2C is deemed to have been disabled when there is master activity, or when the I2C bus is idle. Note: The CPU can safely read this bit when EN (bit 0) is read as 0. 0x0: Slave is disabled when it is idle 0x1: Slave is disabled when it is active 1 1 read-only S_RX_DATA_LOST Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of EN from 1 to 0. When read as 1, I2C is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. Note: If the remote I2C master terminates the transfer with a STOP condition before the I2C has a chance to NACK a transfer, and EN[0] has been set to 0, then this bit is also set to 1. When read as 0, I2C is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. Note: The CPU can safely read this bit when EN (bit 0) is read as 0. 0x0: Slave RX Data is not lost 0x1: Slave RX Data is lost 2 1 read-only FS_CLK_HCOUNT FS_CLK_HCOUNT Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register 0x1C 32 read-write n 0x3C 0xFFFFFFFF COUNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set. 0 16 read-write FS_CLK_LCOUNT FS_CLK_LCOUNT Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register 0x20 32 read-write n 0x82 0xFFFFFFFF COUNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted results in 8 being set. 0 16 read-write FS_SPKLEN FS_SPKLEN I2C SS, FS or FM+ spike suppression limit 0xA0 32 read-write n 0x5 0xFFFFFFFF FS_SPKLEN This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in clock cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1 hardware prevents values less than this being written, and if attempted results in 1 being set. 0 8 read-write HS_CLK_HCOUNT HS_CLK_HCOUNT High Speed I2C Clock SCL High Count Register 0x24 32 read-write n 0x6 0xFFFFFFFF COUNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. The SCL High time depends on the loading of the bus. For 100pF loading, the SCL High time is 60ns for 400pF loading, the SCL High time is 120ns. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set. 0 16 read-write HS_CLK_LCOUNT HS_CLK_LCOUNT High Speed I2C Clock SCL Low Count Register 0x28 32 read-write n 0x10 0xFFFFFFFF COUNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. The SCL low time depends on the loading of the bus. For 100pF loading, the SCL low time is 160ns for 400pF loading, the SCL low time is 320ns. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. 0 16 read-write HS_SPKLEN HS_SPKLEN I2C HS spike suppression limit register 0xA4 32 read-write n 0x1 0xFFFFFFFF HS_SPKLEN This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in clock cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic for more information, refer to Spike Suppression This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1 hardware prevents values less than this being written, and if attempted results in 1 being set. 0 8 read-write INT_MASK INT_MASK I2C Interrupt Mask Register 0x30 32 read-write n 0x8FF 0xFFFFFFFF MASK_ACTIVITY This bit masks the RAW_ACTIVITY interrupt in INT_STAT register. 0x0: ACTIVITY interrupt is masked 0x1: ACTIVITY interrupt is unmasked 8 1 read-write MASK_GEN_CALL This bit masks the RAW_GEN_CALL interrupt in INT_STAT register. 0x0: GEN_CALL interrupt is masked 0x1: GEN_CALL interrupt is unmasked 11 1 read-write MASK_RD_REQ This bit masks the RAW_RD_REQ interrupt in INT_STAT register. 0x0: RD_REQ interrupt is masked 0x1: RD_REQ interrupt is unmasked 5 1 read-write MASK_RX_DONE This bit masks the RAW_RX_DONE interrupt in INT_STAT register. 0x0: RX_DONE interrupt is masked 0x1: RX_DONE interrupt is unmasked 7 1 read-write MASK_RX_FULL This bit masks the RAW_RX_FULL interrupt in INT_STAT register. 0x0: RX_FULL interrupt is masked 0x1: RX_FULL interrupt is unmasked 2 1 read-write MASK_RX_OVER This bit masks the RAW_RX_OVER interrupt in INT_STAT register. 0x0: RX_OVER interrupt is masked 0x1: RX_OVER interrupt is unmasked 1 1 read-write MASK_RX_UNDER This bit masks the RAW_RX_UNDER interrupt in INT_STAT register. 0x0: RX_UNDER interrupt is masked 0x1: RX_UNDER interrupt is unmasked 0 1 read-write MASK_START_DET This bit masks the RAW_START_DET interrupt in INT_STAT register. 0x0: START_DET interrupt is masked 0x1: START_DET interrupt is unmasked 10 1 read-write MASK_STOP_DET This bit masks the RAW_STOP_DET interrupt in INT_STAT register. 0x0: STOP_DET interrupt is masked 0x1: STOP_DET interrupt is unmasked 9 1 read-write MASK_TX_ABORT This bit masks the RAW_TX_ABORT interrupt in INT_STAT register. 0x0: TX_ABORT interrupt is masked 0x1: TX_ABORT interrupt is unmasked 6 1 read-write MASK_TX_EMPTY This bit masks the RAW_TX_EMPTY interrupt in INT_STAT register. 0x0: TX_EMPTY interrupt is masked 0x1: TX_EMPTY interrupt is unmasked 4 1 read-write MASK_TX_OVER This bit masks the RAW_TX_OVER interrupt in INT_STAT register. 0x0: TX_OVER interrupt is masked 0x1: TX_OVER interrupt is unmasked 3 1 read-write INT_STAT INT_STAT I2C Interrupt Status Register 0x2C 32 read-only n 0x0 0xFFFFFFFF RAW_ACTIVITY See RAW_INT_STAT for a detailed description of ACTIVITY bit. 0x0: RAW_ACTIVITY interrupt is inactive 0x1: RAW_ACTIVITY interrupt is active 8 1 read-only RAW_GEN_CALL See RAW_INT_STAT for a detailed description of GEN_CALL bit. 0x0: RAW_GEN_CALL interrupt is inactive 0x1: RAW_GEN_CALL interrupt is active 11 1 read-only RAW_M_HOLD See RAW_INT_STAT for a detailed description of M_HOLD bit. 0x0: RAW_M_HOLD interrupt is inactive 0x1: RAW_M_HOLD interrupt is active 13 1 read-only RAW_RD_REQ See RAW_INT_STAT for a detailed description of RD_REQ bit. 0x0: RAW_RD_REQ interrupt is inactive 0x1: RAW_RD_REQ interrupt is active 5 1 read-only RAW_RESTART_DET See RAW_INT_STAT for a detailed description of RESTART_DET bit. 0x0: RAW_RESTART_DET interrupt is inactive 0x1: RAW_RESTART_DET interrupt is active 12 1 read-only RAW_RX_DONE See RAW_INT_STAT for a detailed description of RX_DONE bit. 0x0: RAW_RX_DONE interrupt is inactive 0x1: RAW_RX_DONE interrupt is active 7 1 read-only RAW_RX_FULL See RAW_INT_STAT for a detailed description of RX_FULL bit. 0x0: RAW_RX_FULL interrupt is inactive 0x1: RAW_RX_FULL interrupt is active 2 1 read-only RAW_RX_OVER See RAW_INT_STAT for a detailed description of RX_OVER bit. 0x0: RAW_RX_OVER interrupt is inactive 0x1: RAW_RX_OVER interrupt is active 1 1 read-only RAW_RX_UNDER See RAW_INT_STAT for a detailed description of RX_UNDER bit. 0x0: RAW_RX_UNDER interrupt is inactive 0x1: RAW_RX_UNDER interrupt is active 0 1 read-only RAW_START_DET See RAW_INT_STAT for a detailed description of START_DET bit. 0x0: RAW_START_DET interrupt is inactive 0x1: RAW_START_DET interrupt is active 10 1 read-only RAW_STOP_DET See RAW_INT_STAT for a detailed description of STOP_DET bit. 0x0: RAW_STOP_DET interrupt is inactive 0x1: RAW_STOP_DET interrupt is active 9 1 read-only RAW_TX_ABORT See RAW_INT_STAT for a detailed description of TX_ABORT bit. 0x0: RAW_TX_ABORT interrupt is inactive 0x1: RAW_TX_ABORT interrupt is active 6 1 read-only RAW_TX_EMPTY See RAW_INT_STAT for a detailed description of TX_EMPTY bit. 0x0: RAW_TX_EMPTY interrupt is inactive 0x1: RAW_TX_EMPTY interrupt is active 4 1 read-only RAW_TX_OVER See RAW_INT_STAT for a detailed description of TX_OVER bit. 0x0: RAW_TX_OVER interrupt is inactive 0x1: RAW_TX_OVER interrupt is active 3 1 read-only M_HS_ADDR M_HS_ADDR I2C High-Speed Master Mode Code Address Register 0xC 32 read-write n 0x1 0xFFFFFFFF HS_ADDR This bit field holds the value of the I2C High Speed mode master code. High Speed mode master codes are reserved 8-bit codes (00001xxx) that are not used for slave addressing or other purposes. Each master has its unique master code up to eight high-speed mode masters can be present on the same I2C bus system. Valid values are from 0 to 7. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. 0 3 read-write RAW_INT_STAT RAW_INT_STAT I2C Raw Interrupt Status Register 0x34 32 read-only n 0x0 0xFFFFFFFF ACTIVITY This bit captures I2C activity and stays set until it is cleared. There are four ways to clear it. Disabling the I2C Reading the CLR_ACTIVITY register Reading the CLR_INT register System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the I2C module is idle, this bit remains set until cleared, indicating that there was activity on the bus. 0x0: RAW_INT_ACTIVITY interrupt is inactive 0x1: RAW_INT_ACTIVITY interrupt is active 8 1 read-only GEN_CALL Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling I2C or when the CPU reads bit 0 of the CLR_GEN_CALL register. I2C stores the received data in the RX buffer. 0x0: GEN_CALL interrupt is inactive 0x1: GEN_CALL interrupt is active 11 1 read-only M_HOLD Indicates whether master is holding the bus and TX FIFO is empty. 0x0: MASTER_ON_HOLD interrupt is inactive 0x1: MASTER_ON_HOLD interrupt is active 13 1 read-only RD_REQ This bit is set to 1 when I2C is acting as a slave and another I2C master is attempting to read data from I2C. The I2C holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the DATA_CMD register. This bit is set to 0 just after the processor reads the CLR_RD_REQ register. Value: 0x0: RD_REQ interrupt is inactive 0x1: RD_REQ interrupt is active 5 1 read-only RESTART_DET Indicates whether a RESTART condition has occurred on the I2C interface when I2C is operating in Slave mode and the slave is being addressed. Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore I2C does not generate the RESTART_DET interrupt. 0x0: RESTART_DET interrupt is inactive 0x1: RESTART_DET interrupt is active 12 1 read-only RX_DONE When the I2C is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. 0x0: RX_DONE interrupt is inactive 0x1: RX_DONE interrupt is active 7 1 read-only RX_FULL Set when the receive buffer reaches or goes above the FIFO_THD threshold in the RX_FIFO_THD register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (EN[0]=0), the RX FIFO is flushed and held in reset therefore the RX FIFO is not full. So this bit is cleared once the ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. 0x0: RX_FULL interrupt is inactive 0x1: RX_FULL interrupt is active 2 1 read-only RX_OVER Set if the receive buffer is completely filled to 8 and an additional byte is received from an external I2C device. The I2C acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (EN[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when en goes to 0, this interrupt is cleared. 0x0: RX_OVER interrupt is inactive 0x1: RX_OVER interrupt is active 1 1 read-only RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the DATA_CMD register. If the module is disabled (EN[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when en goes to 0, this interrupt is cleared. 0x0: RX_UNDER interrupt is inactive 0x1: RX_UNDER interrupt is active 0 1 read-only START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether I2C is operating in slave or master mode. 0x0: START_DET interrupt is inactive 0x1: START_DET interrupt is active 10 1 read-only STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether I2C is operating in slave or master mode. In Slave Mode: If CTRL[7] = 0x1 (STOP_DET_INT), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_INT = 0x1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (S_ADDR). If CTRL[7] = 0x0 (STOP_DET_INT), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: If CTRL[10] = 0x1 (STOP_DET_M_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. If CTRL[10] = 0x0 (STOP_DET_M_ACTIVE),the STOP_DET interrupt will be issued irrespective of whether master is active or not. 0x0: STOP_DET interrupt is inactive 0x1: STOP_DET interrupt is active 9 1 read-only TX_ABORT This bit indicates if I2C, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the TX_ABORT_SRC register indicates the reason why the transmit abort takes places. Note: The I2C flushes/resets/empties only the TX_FIFO whenever there is a transmit abort caused by any of the events tracked by the TX_ABORT_SRC register. The TX FIFO remains in this flushed state until the register CLR_TX_ABORT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface. 0x0: TX_ABORT interrupt is inactive 0x1: TX_ABORT interrupt is active 6 1 read-only TX_EMPTY The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the CTRL register. When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the TX_TL register. When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the TX_FIFO_THD register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When EN[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with en=0, this bit is set to 0. Value: 0x0: TX_EMPTY interrupt is inactive 0x1: TX_EMPTY interrupt is active 4 1 read-only TX_OVER Set during transmit if the transmit buffer is filled to 8 and the processor attempts to issue another I2C command by writing to the DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when en goes to 0, this interrupt is cleared. Value: 0x0: TX_OVER interrupt is inactive 0x1: TX_OVER interrupt is active 3 1 read-only RX_FIFO_LEVEL RX_FIFO_LEVEL I2C Receive FIFO Level Register 0x78 32 read-only n 0x0 0xFFFFFFFF LEVEL Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. 0 4 read-only RX_FIFO_THD RX_FIFO_THD I2C Receive FIFO Threshold Register 0x38 32 read-write n 0x0 0xFFFFFFFF THD Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in RAW_INT_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. 0 8 read-write SDA_HOLD SDA_HOLD I2C SDA Hold Time Length Register 0x7C 32 read-write n 0x1 0xFFFFFFFF RX_HOLD Sets the required SDA hold time in units of clock period, when I2C acts as a receiver. 16 8 read-write TX_HOLD Sets the required SDA hold time in units of clock period, when I2C acts as a transmitter. 0 16 read-write SDA_SETUP SDA_SETUP I2C SDA Setup Register 0x94 32 read-write n 0x64 0xFFFFFFFF SETUP SDA Setup. It is recommended that if the required delay is 1000ns, then for a clk frequency of 10 MHz, SDA_SETUP should be programmed to a value of 11. SDA_SETUP must be programmed with a minimum value of 2 0 8 read-write SS_CLK_HCOUNT SS_CLK_HCOUNT Standard Speed I2C Clock SCL High Count Register 0x14 32 read-write n 0x190 0xFFFFFFFF COUNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set. NOTE: This register must not be programmed to a value higher than 65525, because I2C uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of COUNT + 10. 0 16 read-write SS_CLK_LCOUNT SS_CLK_LCOUNT Standard Speed I2C Clock SCL Low Count Register 0x18 32 read-write n 0x1D6 0xFFFFFFFF COUNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted, results in 8 being set. 0 16 read-write STAT STAT I2C STATUS Register 0x70 32 read-only n 0x6 0xFFFFFFFF ACTIVITY I2C Activity Status. 0x0: I2C is idle 0x1: I2C is active 0 1 read-only M_ACTIVITY Master Activity Status. When the Master is not in the IDLE state, this bit is set. Note: STAS[0], ACTIVITY bit,-is the OR of S_ACTIVITY and M_ACTIVITY bits. 0x0: Master is idle 0x1: Master not idle 5 1 read-only RX_FIFO_CF Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0x0: RX FIFO not full 0x1: RX FIFO is full 4 1 read-only RX_FIFO_NE Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries it is cleared when the receive FIFO is empty. 0x0: RX FIFO is empty 0x1: RX FIFO not empty 3 1 read-only S_ACTIVITY Slave Activity Status. When the Slaveis not in the IDLE state, this bit is set. 0x0: Slave is idle 0x1: Slave not idle 6 1 read-only TX_FIFO_CE Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0x0: TX FIFO not empty 0x1: TX FIFO is empty 2 1 read-only TX_FIFO_NF Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0x0: TX FIFO is full 0x1: TX FIFO not full 1 1 read-only S_ADDR S_ADDR I2C Slave Address Register 0x8 32 read-write n 0x55 0xFFFFFFFF S_ADDR The S_ADDR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only S_ADDR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. Note:The default values cannot be any of the reserved address locations: 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the S_ADDR or TARGET to a reserved value. Refer to Table 10 7 I2C Definition of bits in first byte for a complete list of these reserved values. 0 10 read-write TARGET_ADDR TARGET_ADDR I2C Target Address Register 0x4 32 read-write n 0x55 0xFFFFFFFF SPECIAL This bit indicates whether software performs a Device-ID or General Call or START BYTE command. 0x0: Disables programming of GENERAL_CALL or START_BYTE transmission 0x1: Enables programming of GENERAL_CALL or START_BYTE transmission 11 1 read-write TARGET This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the TARGET and S_ADDR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself it can transmit to only a slave 0 10 read-write TX_CTRL If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the I2C. 0x0: GENERAL_CALL byte transmission 0x1: START byte transmission 10 1 read-write TX_ABORT_SRC TX_ABORT_SRC I2C SDA Hold Time Length Register 0x80 32 read-only n 0x0 0xFFFFFFFF ABORT_10B1_NOACK This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Role of I2C: Master-Transmitter or Master-Receiver 0x0: This abort is not generated 0x1: Byte 1 of 10Bit Address not ACKed by any slave 1 1 read-only ABORT_10B2_NOACK This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Role of I2C: Master-Transmitter or Master-Receiver 0x0: This abort is not generated 0x1: Byte 2 of 10Bit Address not ACKed by any slave 2 1 read-only ABORT_10B_RD_NORSTR This field indicates that the restart is disabled (RESTART_EN bit (CON[5]) =0) and the master sends a read command in 10-bit addressing mode. Role of I2C: Master-Receiver Value: 0x0: Master not trying to read in 10Bit addressing mode when RESTART disabled 0x1: Master trying to read in 10Bit addressing mode when RESTART disabled 10 1 read-only ABORT_7B_NOACK his field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Role of I2C: Master-Transmitter or Master-Receiver 0x0: This abort is not generated 0x1: This abort is generated because of NACK for 7-bit address 0 1 read-only ABORT_GCALL_NOACK This field indicates that I2C in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Role of I2C: Master-Transmitter 0x0: GCALL not ACKed by any slave-scenario not present 0x1: GCALL not ACKed by any slave 4 1 read-only ABORT_GCALL_RD This field indicates that I2C in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (DATA_CMD[9] is set to 1). Role of I2C: Master-Transmitter 0x0: GCALL is followed by read from bus-scenario not present 0x1: GCALL is followed by read from bus 5 1 read-only ABORT_HS_ACKDET This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Role of I2C: Master 0x0: HS Master code ACKed in HS Mode- scenario not present 0x1: HS Master code ACKed in HS Mode 6 1 read-only ABORT_HS_NORSTRT This field indicates that the restart is disabled (RESTART_EN bit (CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. Role of I2C: Master-Transmitter or Master-Receiver 0x0: User trying to switch Master to HS mode when RESTART disabled- scenario not present 0x1: User trying to switch Master to HS mode when RESTART disabled 8 1 read-only ABORT_LOST This field specifies that the Master has lost arbitration, or if TX_ABORT_SRC[14] is also set, then the slave transmitter has lost arbitration. Role of I2C: Master-Transmitter or Slave-Transmitter 0x0: Master or Slave-Transmitter lost arbitration- scenario not present 0x1: Master or Slave-Transmitter lost arbitration 12 1 read-only ABORT_MASTER_DIS This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Role of I2C: Master-Transmitter or Master-Receiver 0x: User initiating master operation when MASTER disabled- scenario not present 0x1: User intitating master operation when MASTER disabled 11 1 read-only ABORT_SBYTE_ACKDET This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Role of I2C: Master 0x0: ACK detected for START byte- scenario not present 0x1: ACK detected for START byte 7 1 read-only ABORT_SBYTE_NORSTRT To clear Bit 9, the source of the ABORT_SBYTE_NORSTRT must be fixed first restart must be enabled (CTRL[5]=1), the SPECIAL bit must be cleared (TARGET[11]), or the GC_OR_START bit must be cleared TARGET[10]). Once the source of the ABORT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABORT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (RESTART_EN bit (CTRL[5]) =0) and the user is trying to send a START Byte. Role of I2C: Master 0x0: User trying to send START byte when RESTART disabled- scenario not present 0x1: User trying to send START byte when RESTART disabled 9 1 read-only ABORT_SLVFLUSH_TXFIFO This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABORT interrupt to flush old data in TX FIFO. Role of I2C: Slave-Transmitter 0x0: Slave flushes existing data in TX-FIFO upon getting read command- scenario not present 0x1: Slave flushes existing data in TX-FIFO upon getting read command 13 1 read-only ABORT_SLVRD_INTX When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of DATA_CMD register. Role of I2C: Slave-Transmitter 0x0: Slave trying to transmit to remote master in read mode- scenario not present 0x1: Slave trying to transmit to remote master in read mode 15 1 read-only ABORT_S_ARBLOST This field indicates that a Slave has lost the bus while transmitting data to a remote master. TX_ABORT_SRC[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then I2C no longer own the bus. Role of I2C: Slave-Transmitter 0x0: Slave lost arbitration to remote master- scenario not present 0x1 : Slave lost arbitration to remote master 14 1 read-only ABORT_TX_NOACK This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Role of I2C:Master-Transmitter 0x0: Transmitted data non-ACKed by addressed slave-scenario not present 0x1 : Transmitted data not ACKed by addressed slave 3 1 read-only ABORT_USER_ABORT This is a master-mode-only bit. Master has detected the transfer abort (EN[1]) Role of I2C: Master-Transmitter 0x0: Transfer abort detected by master- scenario not present 0x1: Transfer abort detected by master 16 1 read-only TX_FLUSH_CNT This field indicates the number of TX FIFO Data Commands which are flushed due to TX_ABORT interrupt. It is cleared whenever I2C is disabled. Role of I2C: Master-Transmitter or Slave-Transmitter 23 9 read-only TX_FIFO_LEVEL TX_FIFO_LEVEL I2C Transmit FIFO Level Register 0x74 32 read-only n 0x0 0xFFFFFFFF LEVEL Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. 0 4 read-only TX_FIFO_THD TX_FIFO_THD I2C Transmit FIFO Threshold Register 0x3C 32 read-write n 0x0 0xFFFFFFFF THD Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in RAW_INT_STAT register). The valid range is 0 ~ 255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. 0 8 read-write I2C1 The Inter-Integrated Circuit (I2C) bus is a two-wire serial interface I2C 0xA000C400 0x0 0xA4 registers n I2C0 I2C0 interrupt 14 I2C1 I2C1 interrupt 15 ACK_GEN_CALL ACK_GEN_CALL I2C ACK General Call Register 0x98 32 read-write n 0x1 0xFFFFFFFF ACK_GEN_CALL ACK General Call. When set to 1, I2C responds with an ACK (by asserting data_oe) when it receives a General Call. Otherwise, I2C responds with a NACK (by negating data_oe). 0x0: Generate NACK for General Call 0x1: Generate ACK for a General Call 0 1 read-write CLR_ACTIVITY CLR_ACTIVITY Clear ACTIVITY Interrupt Register 0x5C 32 read-only n 0x0 0xFFFFFFFF CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the RAW_INT_STAT register. 0 1 read-only CLR_GEN_CALL CLR_GEN_CALL Clear GEN_CALL Interrupt Register 0x68 32 read-only n 0x0 0xFFFFFFFF CLR_GEN_CALL Read this register to clear the GEN_CALL interrupt (bit 11) of RAW_INT_STAT register. 0 1 read-only CLR_INT CLR_INT Clear Combined and Individual Interrupt Register 0x40 32 read-only n 0x0 0xFFFFFFFF CLR_INT Read this register to clear the combined interrupt, all individual interrupts, and the TX_ABORT_SRC register. This bit does not clear hardware clearable interrupts but software clearable interrupts. 0 1 read-only CLR_RD_REQ CLR_RD_REQ Clear RD_REQ Interrupt Register 0x50 32 read-only n 0x0 0xFFFFFFFF CLR_RD_REQ Read this register to clear the RD_REQ interrupt (bit 5) of the RAW_INT_STAT register. 0 1 read-only CLR_RX_DONE CLR_RX_DONE Clear RX_DONE Interrupt Register 0x58 32 read-only n 0x0 0xFFFFFFFF CLR_RX_DONE Read this register to clear the RX_DONE interrupt (bit 7) of the RAW_INT_STAT register. 0 1 read-only CLR_RX_OVER CLR_RX_OVER Clear RX_OVER Interrupt Register 0x48 32 read-only n 0x0 0xFFFFFFFF CLR_RX_OVER Read this register to clear the RX_OVER interrupt (bit 1) of the RAW_INT_STAT register 0 1 read-only CLR_RX_UNDER CLR_RX_UNDER Clear RX_UNDER Interrupt Register 0x44 32 read-only n 0x0 0xFFFFFFFF CLR_RX_UNDER Read this register to clear the RX_UNDER interrupt (bit 0) of the RAW_INT_STAT register 0 1 read-only CLR_START_DET CLR_START_DET Clear START_DET Interrupt Register 0x64 32 read-only n 0x0 0xFFFFFFFF CLR_START_DET Read this register to clear the START_DET interrupt (bit 10) of the RAW_INT_STAT register. 0 1 read-only CLR_STOP_DET CLR_STOP_DET Clear STOP_DET Interrupt Register 0x60 32 read-only n 0x0 0xFFFFFFFF CLR_STOP_DET Read this register to clear the STOP_DET interrupt (bit 9) of the RAW_INT_STAT register. 0 1 read-only CLR_TX_ABORT CLR_TX_ABORT Clear TX_ABORT Interrupt Register 0x54 32 read-only n 0x0 0xFFFFFFFF CLR_TX_ABORT Read this register to clear the TX_ABORT interrupt (bit 6) of the RAW_INT_STAT register, and the TX_ABORT_SRC register. 0 1 read-only CLR_TX_OVER CLR_TX_OVER Clear TX_OVER Interrupt Register 0x4C 32 read-only n 0x0 0xFFFFFFFF CLR_TX_OVER Read this register to clear the TX_OVER interrupt (bit 2) of the RAW_INT_STAT register 0 1 read-only CTRL CTRL I2C Control Register 0x0 32 read-write n 0x7F 0xFFFFFFFF ADDR_BIT_M When acting as a master, this bit controls whether the I2C starts its transfers in 7-bit or 10-bit addressing mode. 0x0: Master 7Bit addressing mode 0x1: Master 10Bit addressing mode 4 1 read-write ADDR_BIT_S When acting as a slave, this bit controls whether the I2C responds to 7- or 10-bit addresses. 0x0: Slave 7Bit addressing 0x1: Slave 10Bit addressing 3 1 read-write M_MODE This bit controls whether the I2C master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. 0x0: Master mode is disabled 0x1: Master mode is enabled 0 1 read-write RESTART_EN Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions however, RESTART conditions are used in several I2C operations. When RESTART is disabled, the master is prohibited from performing the following functions: • Sending a START BYTE • Performing any high-speed mode operation • High-speed mode operation • Performing direction changes in combined format mode • Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple I2C transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABORT) of the RAW_INTR_STAT register. 0x0: Master restart disabled 0x1: Master restart enabled 5 1 read-write SPEED These bits control at which speed the I2C operates its setting is relevant only if one is operating the I2C in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to 3. 0x1: Standard Speed mode of operation(100 kbit/s) 0x2: Fast( ≤400 kbit/s) or Fast Plus(≤1000Kbit/s) mode of operation 0x3: High Speed mode of operation(3.4 Mbit/s) 1 2 read-write STOP_DET_INT In slave mode 0x0: Issues the STOP_DET irrespective of whether it's addressed or not 0x1: Issues the STOP_DET interrrupt only when it is addressed NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_INT = 1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (S_ADDR). 0x0: Slave issues STOP_DET intr always 0x1: Slave issues STOP_DET intr only if addressed 7 1 read-write STOP_DET_M_ACTIVE In Master mode 0x1: issues the STOP_DET interrupt only when master is active. 0x0: issues the STOP_DET irrespective of whether master is active or not. 0x1: Master issues the STOP_DET interrupt only when master is active 0x0: Master issues the STOP_DET interrupt irrespective of whether master is active or not 10 1 read-write S_DIS This bit controls whether I2C has its slave disabled. By default, the slave is always disabled (in reset state as well). If you need to enable it after reset, set this bit to 0. If this bit is set (slave is disabled), I2C functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. Value: 0x0: Slave mode is enabled 0x1: Slave mode is disabled 6 1 read-write TX_EMPTY_CTRL This bit controls the generation of the TX_EMPTY interrupt, as described in the RAW_INTR_STAT register. 0x0: Default disable behaviour of TX_EMPTY interrupt 0x1: Controlled enable generation of TX_EMPTY interrupt 8 1 read-write DATA_CMD DATA_CMD I2C RX/TX Data Buffer and Command Register 0x10 32 read-write n 0x0 0xFFFFFFFF CMD This bit controls whether a read or a write is performed. This bit does not control the direction when the I2C acts as a slave. It controls only the direction when it acts as a master. 0x0: Master Write command 0x1: Master Read command 8 1 read-write DATA This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DATA) are ignored by the I2C. However, when you read this register, these bits return the value of data received on the I2C interface. 0 8 read-write DMA_CTRL DMA_CTRL DMA Control Register 0x88 32 read-write n 0x0 0xFFFFFFFF RX_EN Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. 0x0: Receive FIFO DMA channel disabled 0x1: Receive FIFO DMA channel enabled 0 1 read-write TX_EN Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. 0x0: Transmit FIFO DMA channel disabled 0x1: Transmit FIFO DMA channel enabled 1 1 read-write DMA_RX_LEVEL DMA_RX_LEVEL DMA Receive Data Level Register 0x90 32 read-write n 0x0 0xFFFFFFFF LEVEL Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. 0 3 read-write DMA_TX_LEVEL DMA_TX_LEVEL DMA Transmit Data Level Register 0x8C 32 read-write n 0x0 0xFFFFFFFF LEVEL Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. 0 3 read-write EN EN I2C ENABLE Register 0x6C 32 read-write n 0x0 0xFFFFFFFF ABORT When set, the controller initiates the transfer abort. The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the TX FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. 0x0: ABORT operation not in progress 0x1: ABORT operation in progress 1 1 read-write ACTIVITY Controls whether the I2C is enabled. Software can disable I2C while it is active. However, it is important that care be taken to ensure that I2C is disabled properly. A recommended procedure is described in Disabling I2C . When I2C is disabled, the following occurs: The TX FIFO and RX FIFO get flushed. Status bits in the INTR_STAT register are still active until I2C goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the I2C stops the current transfer at the end of the current byte and does not acknowledge the transfer. 0x0: I2C is disabled 0x1: I2C is enabled 0 1 read-only TX_CMD_BLOCK In Master mode 0x0: TX Command execution not blocked 0x1: TX Command execution blocked 2 1 read-write EN_STAT EN_STAT I2C Enable Status Register 0x9C 32 read-only n 0x0 0xFFFFFFFF EN EN Status. This bit always reflects the value driven on the output port en. When read as 1, I2C is deemed to be in an enabled state. When read as 0, I2C is deemed completely inactive. Note:The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read S_RX_DATA_LOST (bit 2) and S_DIS_BUSY (bit 1). 0x0: I2C disabled 0x1: I2C enabled 0 1 read-only S_DIS_BUSY Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the ENregister from 1 to 0. This bit is set when the CPU writes a 0 to the EN register while • I2C is receiving the address byte of the Slave-Transmitter operation from a remote master or • Address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, I2C is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in I2C (S_ADDR register) OR if the transfer is completed before ENABLE is set to 0 but has not taken effect. Note: If the remote I2C master terminates the transfer with a STOP condition before the I2C has a chance to NACK a transfer, and EN[0] has been set to 0, then this bit will also be set to 1. When read as 0, I2C is deemed to have been disabled when there is master activity, or when the I2C bus is idle. Note: The CPU can safely read this bit when EN (bit 0) is read as 0. 0x0: Slave is disabled when it is idle 0x1: Slave is disabled when it is active 1 1 read-only S_RX_DATA_LOST Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of EN from 1 to 0. When read as 1, I2C is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. Note: If the remote I2C master terminates the transfer with a STOP condition before the I2C has a chance to NACK a transfer, and EN[0] has been set to 0, then this bit is also set to 1. When read as 0, I2C is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. Note: The CPU can safely read this bit when EN (bit 0) is read as 0. 0x0: Slave RX Data is not lost 0x1: Slave RX Data is lost 2 1 read-only FS_CLK_HCOUNT FS_CLK_HCOUNT Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register 0x1C 32 read-write n 0x3C 0xFFFFFFFF COUNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set. 0 16 read-write FS_CLK_LCOUNT FS_CLK_LCOUNT Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register 0x20 32 read-write n 0x82 0xFFFFFFFF COUNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted results in 8 being set. 0 16 read-write FS_SPKLEN FS_SPKLEN I2C SS, FS or FM+ spike suppression limit 0xA0 32 read-write n 0x5 0xFFFFFFFF FS_SPKLEN This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in clock cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1 hardware prevents values less than this being written, and if attempted results in 1 being set. 0 8 read-write HS_CLK_HCOUNT HS_CLK_HCOUNT High Speed I2C Clock SCL High Count Register 0x24 32 read-write n 0x6 0xFFFFFFFF COUNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. The SCL High time depends on the loading of the bus. For 100pF loading, the SCL High time is 60ns for 400pF loading, the SCL High time is 120ns. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set. 0 16 read-write HS_CLK_LCOUNT HS_CLK_LCOUNT High Speed I2C Clock SCL Low Count Register 0x28 32 read-write n 0x10 0xFFFFFFFF COUNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. The SCL low time depends on the loading of the bus. For 100pF loading, the SCL low time is 160ns for 400pF loading, the SCL low time is 320ns. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. 0 16 read-write HS_SPKLEN HS_SPKLEN I2C HS spike suppression limit register 0xA4 32 read-write n 0x1 0xFFFFFFFF HS_SPKLEN This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in clock cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic for more information, refer to Spike Suppression This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1 hardware prevents values less than this being written, and if attempted results in 1 being set. 0 8 read-write INT_MASK INT_MASK I2C Interrupt Mask Register 0x30 32 read-write n 0x8FF 0xFFFFFFFF MASK_ACTIVITY This bit masks the RAW_ACTIVITY interrupt in INT_STAT register. 0x0: ACTIVITY interrupt is masked 0x1: ACTIVITY interrupt is unmasked 8 1 read-write MASK_GEN_CALL This bit masks the RAW_GEN_CALL interrupt in INT_STAT register. 0x0: GEN_CALL interrupt is masked 0x1: GEN_CALL interrupt is unmasked 11 1 read-write MASK_RD_REQ This bit masks the RAW_RD_REQ interrupt in INT_STAT register. 0x0: RD_REQ interrupt is masked 0x1: RD_REQ interrupt is unmasked 5 1 read-write MASK_RX_DONE This bit masks the RAW_RX_DONE interrupt in INT_STAT register. 0x0: RX_DONE interrupt is masked 0x1: RX_DONE interrupt is unmasked 7 1 read-write MASK_RX_FULL This bit masks the RAW_RX_FULL interrupt in INT_STAT register. 0x0: RX_FULL interrupt is masked 0x1: RX_FULL interrupt is unmasked 2 1 read-write MASK_RX_OVER This bit masks the RAW_RX_OVER interrupt in INT_STAT register. 0x0: RX_OVER interrupt is masked 0x1: RX_OVER interrupt is unmasked 1 1 read-write MASK_RX_UNDER This bit masks the RAW_RX_UNDER interrupt in INT_STAT register. 0x0: RX_UNDER interrupt is masked 0x1: RX_UNDER interrupt is unmasked 0 1 read-write MASK_START_DET This bit masks the RAW_START_DET interrupt in INT_STAT register. 0x0: START_DET interrupt is masked 0x1: START_DET interrupt is unmasked 10 1 read-write MASK_STOP_DET This bit masks the RAW_STOP_DET interrupt in INT_STAT register. 0x0: STOP_DET interrupt is masked 0x1: STOP_DET interrupt is unmasked 9 1 read-write MASK_TX_ABORT This bit masks the RAW_TX_ABORT interrupt in INT_STAT register. 0x0: TX_ABORT interrupt is masked 0x1: TX_ABORT interrupt is unmasked 6 1 read-write MASK_TX_EMPTY This bit masks the RAW_TX_EMPTY interrupt in INT_STAT register. 0x0: TX_EMPTY interrupt is masked 0x1: TX_EMPTY interrupt is unmasked 4 1 read-write MASK_TX_OVER This bit masks the RAW_TX_OVER interrupt in INT_STAT register. 0x0: TX_OVER interrupt is masked 0x1: TX_OVER interrupt is unmasked 3 1 read-write INT_STAT INT_STAT I2C Interrupt Status Register 0x2C 32 read-only n 0x0 0xFFFFFFFF RAW_ACTIVITY See RAW_INT_STAT for a detailed description of ACTIVITY bit. 0x0: RAW_ACTIVITY interrupt is inactive 0x1: RAW_ACTIVITY interrupt is active 8 1 read-only RAW_GEN_CALL See RAW_INT_STAT for a detailed description of GEN_CALL bit. 0x0: RAW_GEN_CALL interrupt is inactive 0x1: RAW_GEN_CALL interrupt is active 11 1 read-only RAW_M_HOLD See RAW_INT_STAT for a detailed description of M_HOLD bit. 0x0: RAW_M_HOLD interrupt is inactive 0x1: RAW_M_HOLD interrupt is active 13 1 read-only RAW_RD_REQ See RAW_INT_STAT for a detailed description of RD_REQ bit. 0x0: RAW_RD_REQ interrupt is inactive 0x1: RAW_RD_REQ interrupt is active 5 1 read-only RAW_RESTART_DET See RAW_INT_STAT for a detailed description of RESTART_DET bit. 0x0: RAW_RESTART_DET interrupt is inactive 0x1: RAW_RESTART_DET interrupt is active 12 1 read-only RAW_RX_DONE See RAW_INT_STAT for a detailed description of RX_DONE bit. 0x0: RAW_RX_DONE interrupt is inactive 0x1: RAW_RX_DONE interrupt is active 7 1 read-only RAW_RX_FULL See RAW_INT_STAT for a detailed description of RX_FULL bit. 0x0: RAW_RX_FULL interrupt is inactive 0x1: RAW_RX_FULL interrupt is active 2 1 read-only RAW_RX_OVER See RAW_INT_STAT for a detailed description of RX_OVER bit. 0x0: RAW_RX_OVER interrupt is inactive 0x1: RAW_RX_OVER interrupt is active 1 1 read-only RAW_RX_UNDER See RAW_INT_STAT for a detailed description of RX_UNDER bit. 0x0: RAW_RX_UNDER interrupt is inactive 0x1: RAW_RX_UNDER interrupt is active 0 1 read-only RAW_START_DET See RAW_INT_STAT for a detailed description of START_DET bit. 0x0: RAW_START_DET interrupt is inactive 0x1: RAW_START_DET interrupt is active 10 1 read-only RAW_STOP_DET See RAW_INT_STAT for a detailed description of STOP_DET bit. 0x0: RAW_STOP_DET interrupt is inactive 0x1: RAW_STOP_DET interrupt is active 9 1 read-only RAW_TX_ABORT See RAW_INT_STAT for a detailed description of TX_ABORT bit. 0x0: RAW_TX_ABORT interrupt is inactive 0x1: RAW_TX_ABORT interrupt is active 6 1 read-only RAW_TX_EMPTY See RAW_INT_STAT for a detailed description of TX_EMPTY bit. 0x0: RAW_TX_EMPTY interrupt is inactive 0x1: RAW_TX_EMPTY interrupt is active 4 1 read-only RAW_TX_OVER See RAW_INT_STAT for a detailed description of TX_OVER bit. 0x0: RAW_TX_OVER interrupt is inactive 0x1: RAW_TX_OVER interrupt is active 3 1 read-only M_HS_ADDR M_HS_ADDR I2C High-Speed Master Mode Code Address Register 0xC 32 read-write n 0x1 0xFFFFFFFF HS_ADDR This bit field holds the value of the I2C High Speed mode master code. High Speed mode master codes are reserved 8-bit codes (00001xxx) that are not used for slave addressing or other purposes. Each master has its unique master code up to eight high-speed mode masters can be present on the same I2C bus system. Valid values are from 0 to 7. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. 0 3 read-write RAW_INT_STAT RAW_INT_STAT I2C Raw Interrupt Status Register 0x34 32 read-only n 0x0 0xFFFFFFFF ACTIVITY This bit captures I2C activity and stays set until it is cleared. There are four ways to clear it. Disabling the I2C Reading the CLR_ACTIVITY register Reading the CLR_INT register System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the I2C module is idle, this bit remains set until cleared, indicating that there was activity on the bus. 0x0: RAW_INT_ACTIVITY interrupt is inactive 0x1: RAW_INT_ACTIVITY interrupt is active 8 1 read-only GEN_CALL Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling I2C or when the CPU reads bit 0 of the CLR_GEN_CALL register. I2C stores the received data in the RX buffer. 0x0: GEN_CALL interrupt is inactive 0x1: GEN_CALL interrupt is active 11 1 read-only M_HOLD Indicates whether master is holding the bus and TX FIFO is empty. 0x0: MASTER_ON_HOLD interrupt is inactive 0x1: MASTER_ON_HOLD interrupt is active 13 1 read-only RD_REQ This bit is set to 1 when I2C is acting as a slave and another I2C master is attempting to read data from I2C. The I2C holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the DATA_CMD register. This bit is set to 0 just after the processor reads the CLR_RD_REQ register. Value: 0x0: RD_REQ interrupt is inactive 0x1: RD_REQ interrupt is active 5 1 read-only RESTART_DET Indicates whether a RESTART condition has occurred on the I2C interface when I2C is operating in Slave mode and the slave is being addressed. Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore I2C does not generate the RESTART_DET interrupt. 0x0: RESTART_DET interrupt is inactive 0x1: RESTART_DET interrupt is active 12 1 read-only RX_DONE When the I2C is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. 0x0: RX_DONE interrupt is inactive 0x1: RX_DONE interrupt is active 7 1 read-only RX_FULL Set when the receive buffer reaches or goes above the FIFO_THD threshold in the RX_FIFO_THD register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (EN[0]=0), the RX FIFO is flushed and held in reset therefore the RX FIFO is not full. So this bit is cleared once the ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. 0x0: RX_FULL interrupt is inactive 0x1: RX_FULL interrupt is active 2 1 read-only RX_OVER Set if the receive buffer is completely filled to 8 and an additional byte is received from an external I2C device. The I2C acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (EN[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when en goes to 0, this interrupt is cleared. 0x0: RX_OVER interrupt is inactive 0x1: RX_OVER interrupt is active 1 1 read-only RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the DATA_CMD register. If the module is disabled (EN[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when en goes to 0, this interrupt is cleared. 0x0: RX_UNDER interrupt is inactive 0x1: RX_UNDER interrupt is active 0 1 read-only START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether I2C is operating in slave or master mode. 0x0: START_DET interrupt is inactive 0x1: START_DET interrupt is active 10 1 read-only STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether I2C is operating in slave or master mode. In Slave Mode: If CTRL[7] = 0x1 (STOP_DET_INT), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_INT = 0x1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (S_ADDR). If CTRL[7] = 0x0 (STOP_DET_INT), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: If CTRL[10] = 0x1 (STOP_DET_M_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. If CTRL[10] = 0x0 (STOP_DET_M_ACTIVE),the STOP_DET interrupt will be issued irrespective of whether master is active or not. 0x0: STOP_DET interrupt is inactive 0x1: STOP_DET interrupt is active 9 1 read-only TX_ABORT This bit indicates if I2C, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the TX_ABORT_SRC register indicates the reason why the transmit abort takes places. Note: The I2C flushes/resets/empties only the TX_FIFO whenever there is a transmit abort caused by any of the events tracked by the TX_ABORT_SRC register. The TX FIFO remains in this flushed state until the register CLR_TX_ABORT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface. 0x0: TX_ABORT interrupt is inactive 0x1: TX_ABORT interrupt is active 6 1 read-only TX_EMPTY The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the CTRL register. When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the TX_TL register. When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the TX_FIFO_THD register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When EN[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with en=0, this bit is set to 0. Value: 0x0: TX_EMPTY interrupt is inactive 0x1: TX_EMPTY interrupt is active 4 1 read-only TX_OVER Set during transmit if the transmit buffer is filled to 8 and the processor attempts to issue another I2C command by writing to the DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when en goes to 0, this interrupt is cleared. Value: 0x0: TX_OVER interrupt is inactive 0x1: TX_OVER interrupt is active 3 1 read-only RX_FIFO_LEVEL RX_FIFO_LEVEL I2C Receive FIFO Level Register 0x78 32 read-only n 0x0 0xFFFFFFFF LEVEL Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. 0 4 read-only RX_FIFO_THD RX_FIFO_THD I2C Receive FIFO Threshold Register 0x38 32 read-write n 0x0 0xFFFFFFFF THD Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in RAW_INT_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. 0 8 read-write SDA_HOLD SDA_HOLD I2C SDA Hold Time Length Register 0x7C 32 read-write n 0x1 0xFFFFFFFF RX_HOLD Sets the required SDA hold time in units of clock period, when I2C acts as a receiver. 16 8 read-write TX_HOLD Sets the required SDA hold time in units of clock period, when I2C acts as a transmitter. 0 16 read-write SDA_SETUP SDA_SETUP I2C SDA Setup Register 0x94 32 read-write n 0x64 0xFFFFFFFF SETUP SDA Setup. It is recommended that if the required delay is 1000ns, then for a clk frequency of 10 MHz, SDA_SETUP should be programmed to a value of 11. SDA_SETUP must be programmed with a minimum value of 2 0 8 read-write SS_CLK_HCOUNT SS_CLK_HCOUNT Standard Speed I2C Clock SCL High Count Register 0x14 32 read-write n 0x190 0xFFFFFFFF COUNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set. NOTE: This register must not be programmed to a value higher than 65525, because I2C uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of COUNT + 10. 0 16 read-write SS_CLK_LCOUNT SS_CLK_LCOUNT Standard Speed I2C Clock SCL Low Count Register 0x18 32 read-write n 0x1D6 0xFFFFFFFF COUNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register can be written only when the I2C interface is disabled which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted, results in 8 being set. 0 16 read-write STAT STAT I2C STATUS Register 0x70 32 read-only n 0x6 0xFFFFFFFF ACTIVITY I2C Activity Status. 0x0: I2C is idle 0x1: I2C is active 0 1 read-only M_ACTIVITY Master Activity Status. When the Master is not in the IDLE state, this bit is set. Note: STAS[0], ACTIVITY bit,-is the OR of S_ACTIVITY and M_ACTIVITY bits. 0x0: Master is idle 0x1: Master not idle 5 1 read-only RX_FIFO_CF Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0x0: RX FIFO not full 0x1: RX FIFO is full 4 1 read-only RX_FIFO_NE Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries it is cleared when the receive FIFO is empty. 0x0: RX FIFO is empty 0x1: RX FIFO not empty 3 1 read-only S_ACTIVITY Slave Activity Status. When the Slaveis not in the IDLE state, this bit is set. 0x0: Slave is idle 0x1: Slave not idle 6 1 read-only TX_FIFO_CE Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0x0: TX FIFO not empty 0x1: TX FIFO is empty 2 1 read-only TX_FIFO_NF Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0x0: TX FIFO is full 0x1: TX FIFO not full 1 1 read-only S_ADDR S_ADDR I2C Slave Address Register 0x8 32 read-write n 0x55 0xFFFFFFFF S_ADDR The S_ADDR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only S_ADDR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the EN[0] register being set to 0. Writes at other times have no effect. Note:The default values cannot be any of the reserved address locations: 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the S_ADDR or TARGET to a reserved value. Refer to Table 10 7 I2C Definition of bits in first byte for a complete list of these reserved values. 0 10 read-write TARGET_ADDR TARGET_ADDR I2C Target Address Register 0x4 32 read-write n 0x55 0xFFFFFFFF SPECIAL This bit indicates whether software performs a Device-ID or General Call or START BYTE command. 0x0: Disables programming of GENERAL_CALL or START_BYTE transmission 0x1: Enables programming of GENERAL_CALL or START_BYTE transmission 11 1 read-write TARGET This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the TARGET and S_ADDR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself it can transmit to only a slave 0 10 read-write TX_CTRL If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the I2C. 0x0: GENERAL_CALL byte transmission 0x1: START byte transmission 10 1 read-write TX_ABORT_SRC TX_ABORT_SRC I2C SDA Hold Time Length Register 0x80 32 read-only n 0x0 0xFFFFFFFF ABORT_10B1_NOACK This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Role of I2C: Master-Transmitter or Master-Receiver 0x0: This abort is not generated 0x1: Byte 1 of 10Bit Address not ACKed by any slave 1 1 read-only ABORT_10B2_NOACK This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Role of I2C: Master-Transmitter or Master-Receiver 0x0: This abort is not generated 0x1: Byte 2 of 10Bit Address not ACKed by any slave 2 1 read-only ABORT_10B_RD_NORSTR This field indicates that the restart is disabled (RESTART_EN bit (CON[5]) =0) and the master sends a read command in 10-bit addressing mode. Role of I2C: Master-Receiver Value: 0x0: Master not trying to read in 10Bit addressing mode when RESTART disabled 0x1: Master trying to read in 10Bit addressing mode when RESTART disabled 10 1 read-only ABORT_7B_NOACK his field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Role of I2C: Master-Transmitter or Master-Receiver 0x0: This abort is not generated 0x1: This abort is generated because of NACK for 7-bit address 0 1 read-only ABORT_GCALL_NOACK This field indicates that I2C in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Role of I2C: Master-Transmitter 0x0: GCALL not ACKed by any slave-scenario not present 0x1: GCALL not ACKed by any slave 4 1 read-only ABORT_GCALL_RD This field indicates that I2C in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (DATA_CMD[9] is set to 1). Role of I2C: Master-Transmitter 0x0: GCALL is followed by read from bus-scenario not present 0x1: GCALL is followed by read from bus 5 1 read-only ABORT_HS_ACKDET This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Role of I2C: Master 0x0: HS Master code ACKed in HS Mode- scenario not present 0x1: HS Master code ACKed in HS Mode 6 1 read-only ABORT_HS_NORSTRT This field indicates that the restart is disabled (RESTART_EN bit (CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. Role of I2C: Master-Transmitter or Master-Receiver 0x0: User trying to switch Master to HS mode when RESTART disabled- scenario not present 0x1: User trying to switch Master to HS mode when RESTART disabled 8 1 read-only ABORT_LOST This field specifies that the Master has lost arbitration, or if TX_ABORT_SRC[14] is also set, then the slave transmitter has lost arbitration. Role of I2C: Master-Transmitter or Slave-Transmitter 0x0: Master or Slave-Transmitter lost arbitration- scenario not present 0x1: Master or Slave-Transmitter lost arbitration 12 1 read-only ABORT_MASTER_DIS This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Role of I2C: Master-Transmitter or Master-Receiver 0x: User initiating master operation when MASTER disabled- scenario not present 0x1: User intitating master operation when MASTER disabled 11 1 read-only ABORT_SBYTE_ACKDET This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Role of I2C: Master 0x0: ACK detected for START byte- scenario not present 0x1: ACK detected for START byte 7 1 read-only ABORT_SBYTE_NORSTRT To clear Bit 9, the source of the ABORT_SBYTE_NORSTRT must be fixed first restart must be enabled (CTRL[5]=1), the SPECIAL bit must be cleared (TARGET[11]), or the GC_OR_START bit must be cleared TARGET[10]). Once the source of the ABORT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABORT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (RESTART_EN bit (CTRL[5]) =0) and the user is trying to send a START Byte. Role of I2C: Master 0x0: User trying to send START byte when RESTART disabled- scenario not present 0x1: User trying to send START byte when RESTART disabled 9 1 read-only ABORT_SLVFLUSH_TXFIFO This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABORT interrupt to flush old data in TX FIFO. Role of I2C: Slave-Transmitter 0x0: Slave flushes existing data in TX-FIFO upon getting read command- scenario not present 0x1: Slave flushes existing data in TX-FIFO upon getting read command 13 1 read-only ABORT_SLVRD_INTX When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of DATA_CMD register. Role of I2C: Slave-Transmitter 0x0: Slave trying to transmit to remote master in read mode- scenario not present 0x1: Slave trying to transmit to remote master in read mode 15 1 read-only ABORT_S_ARBLOST This field indicates that a Slave has lost the bus while transmitting data to a remote master. TX_ABORT_SRC[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then I2C no longer own the bus. Role of I2C: Slave-Transmitter 0x0: Slave lost arbitration to remote master- scenario not present 0x1 : Slave lost arbitration to remote master 14 1 read-only ABORT_TX_NOACK This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Role of I2C:Master-Transmitter 0x0: Transmitted data non-ACKed by addressed slave-scenario not present 0x1 : Transmitted data not ACKed by addressed slave 3 1 read-only ABORT_USER_ABORT This is a master-mode-only bit. Master has detected the transfer abort (EN[1]) Role of I2C: Master-Transmitter 0x0: Transfer abort detected by master- scenario not present 0x1: Transfer abort detected by master 16 1 read-only TX_FLUSH_CNT This field indicates the number of TX FIFO Data Commands which are flushed due to TX_ABORT interrupt. It is cleared whenever I2C is disabled. Role of I2C: Master-Transmitter or Slave-Transmitter 23 9 read-only TX_FIFO_LEVEL TX_FIFO_LEVEL I2C Transmit FIFO Level Register 0x74 32 read-only n 0x0 0xFFFFFFFF LEVEL Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. 0 4 read-only TX_FIFO_THD TX_FIFO_THD I2C Transmit FIFO Threshold Register 0x3C 32 read-write n 0x0 0xFFFFFFFF THD Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in RAW_INT_STAT register). The valid range is 0 ~ 255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. 0 8 read-write I2S_M Inter—IC Sound I2S 0xA000CA00 0x0 0x70 registers n I2S_M I2S_M interrupt 29 I2S_S I2S_S interrupt 30 CLK_CFG CLK_CFG I2S Clock Configure Register 0x268 32 read-write n 0x40008 0xFFFFFFFF CLK_SRC_SEL clock divider source select 0: 96M, 1: 32M 18 1 read-write DIV ratio = 1/(div + 2). Duty cycle is not 50 when the number is odd. For example: div = 0, ratio = 1/2 0 12 read-write DIV_EN enable i2s clock divider 16 1 read-write CLK_EN CLK_EN Clock Enable Register 0xC 32 read-write n 0x0 0xFFFFFFFF CLK_EN Clock Generation enable/disable. This bit enables or disables the clock generation signals when I2S is a master. • 0x0: Clock generation disabled • 0x1: Clock generation enabled Note: When the I2S is configured as a slave, this register serves no purpose. 0 1 read-write EN EN I2S Enable Register 0x0 32 read-write n 0x0 0xFFFFFFFF I2S_EN I2S enable. This bit enables or disables I2S. A disable on this bit overrides any other block or channel enables and flushes all FIFOs. Value: 0x0: I2S disabled. 0x1: I2S enabled 0 1 read-write INT_MASK INT_MASK Interrupt Mask Register 0x3C 32 read-write n 0x13 0xFFFFFFFF RX_DAM Mask RX FIFO Data Available interrupt. This bit masks or unmasks an RX FIFO Data Available interrupt. • 0x1: Disable RX FIFO data available interrupt • 0x0: Enable RX FIFO data available interrupt 0 1 read-write RX_FOM Mask RX FIFO Overrun interrupt. This bit masks or unmasks an RX FIFO Overrun interrupt. • 0x1: Disable RX FIFO Overrun interrupt • 0x0: Enable RX FIFO Overrun interrupt 1 1 read-write TX_FEM Mask TX FIFO Empty interrupt. This bit masks or unmasks a TX FIFO Empty interrupt. • 0x1: Disable TX FIFO Empty interrupt • 0x0: Enable TX FIFO Empty interrupt 4 1 read-write TX_FOM Mask TX FIFO Overrun interrupt. This bit masks or unmasks a TX FIFO overrun interrupt. • 0x1: Disable TX FIFO Overrun interrupt • 0x0: Enable TX FIFO Overrun interrupt 5 1 read-write INT_STAT INT_STAT Interrupt status Register 0x38 32 read-only n 0x10 0xFFFFFFFF RX_DATA_AVL Status of Receive Data Available interrupt. This bit denotes the status of the RX FIFO trigger level. • 0x1: RX FIFO trigger level is reached • 0x0: RX FIFO trigger level is not reached 0 1 read-only RX_FIFO_OVER Status of Data Overrun interrupt for the RX channel. Incoming data lost due to a full RX FIFO. • 0x0: RX FIFO write valid • 0x1: RX FIFO write overrun 1 1 read-only TX_FIFO_EMPTY Status of Transmit Empty Trigger interrupt. This bit specifies whether the TX FIFO trigger level has reached or not. TX FIFO is empty. • 0x0: TX FIFO trigger level is reached • 0x1: TX FIFO trigger level is not reached 4 1 read-only TX_FIFO_OVER Status of Data Overrun interrupt for the TX channel. This bit specifies whether the TX FIFO write is valid or an overrun. Attempt to write to full TX FIFO. • 0x0: TX FIFO write valid • 0x1: TX FIFO write overrun 5 1 read-only LEFT_RX_BUF LEFT_RX_BUF Left Receive Buffer Register 0x20 32 read-only n 0x0 0xFFFFFFFF LEFT_RX_BUF The left stereo data received serially from the receive channel input (sdi). If the RX FIFO is full and the two-stage read operation (for instance, a read from LEFT_RX_BUF register followed by a read from RIGHT_RX_BUF register) is not performed before the start of the next stereo pair, then the new data is lost and an overrun interrupt occurs. (data already in the RX FIFO is preserved.) Note: Before reading this register again, the right stereo data must be read from RRBRx or the status/interrupts will not be valid. 0 32 read-only LEFT_TX_HDG LEFT_TX_HDG Left Transmit Holding Register LEFT_RX_BUF 0x20 32 write-only n 0x0 0xFFFFFFFF LEFT_TX_HDG The left stereo data to be transmitted serially through the transmit channel output (sdo) is written through this register. Writing is a two-stage process: 1. A write to this register passes the left stereo sample to the transmitter. 2. This MUST be followed by writing the right stereo sample to the RIGHT_TX_HDG register. Data must only be written to the FIFO when it is not full. Any attempt to write to a full FIFO results in that data being lost and an overrun interrupt being generated. 0 32 write-only RIGHT_RX_BUF RIGHT_RX_BUF Right Receive Buffer Register 0x24 32 read-only n 0x0 0xFFFFFFFF RIGHT_RX_BUF The right stereo data received serially from the receive channel input (sdi) is read through this register. If the RX FIFO is full and the two-stage read operation (for instance, read from LEFT_RX_BUF register followed by a read from RIGHT_RX_BUF register) is not performed before the start of the next stereo pair, then the new data is lost and an overrun interrupt occurs. (Data already in the RX FIFO is preserved.) Note: Prior to reading this register, the left stereo data MUST be read from LEFT_RX_BUF register, or the status/interrupts will not be valid. 0 32 read-only RIGHT_TX_HDG RIGHT_TX_HDG Right Transmit Holding Register RIGHT_RX_BUF 0x24 32 write-only n 0x0 0xFFFFFFFF RIGHT_TX_HDG The right stereo data to be transmitted serially through the transmit channel output (sdo) is written through this register. Writing is a two-stage process: 1. A left stereo sample MUST be written to the LTHR register. 2. A write to this register passes the right stereo sample to the transmitter. Data should only be written to the FIFO when it is not full. Any attempt to write to a full FIFO results in that data being lost and an overrun interrupt being generated. 0 32 write-only RST_RX_DMA RST_RX_DMA Reset Receiver Block DMA Register 0x1C4 32 write-only n 0x0 0xFFFFFFFF RST_RX_DMA Reset Receiver Block DMA Register. Writing a 1 to this self-clearing register resets the RXDMA register mid-cycle to point to the enabled Receive channel. • 0x0: No effect. • 0x1: Reset receiver block DMA register. 0 1 write-only RST_TX_DMA RST_TX_DMA Reset Transmitter Block DMA Register 0x1CC 32 write-only n 0x0 0xFFFFFFFF RST_TX_DMA Reset Transmitter Block DMA Register. Writing a 1 to this self-clearing register resets the TXDMA register mid-cycle to point to the enabled Transmit channel. • 0x0: No effect. • 0x1: Reset transmitter block DMA register. 0 1 write-only RX_CFG RX_CFG Receive Configuration Register 0x30 32 read-write n 0x5 0xFFFFFFFF WORD_LEN These bits are used to program the desired data resolution of the receiver and enables the LSB of the incoming left (or right) word to be placed in the LSB of the LEFT_RX_BUF (or RIGHT_RX_BUF) register. Programmed data resolution must be less than or equal to 0x5. If the selected resolution is greater than the 0x5, the receive channel defaults back to 0x5. The channel must be disabled prior to any changes in this value(RX_EN[0] = 0). • 0x0: Ignore the word length • 0x1: 12-bit data resolution of the receiver. • 0x2: 16-bit data resolution of the receiver. • 0x3: 20-bit data resolution of the receiver. • 0x4: 24-bit data resolution of the receiver. • 0x5: 32-bit data resolution of the receiver. 0 3 read-write RX_CH_EN RX_CH_EN Receive Enable Register 0x28 32 read-write n 0x1 0xFFFFFFFF RX_CH_EN Receive channel enable. This bit enables/disables a receive channel. On enable, the channel begins receiving on the next left stereo cycle. A global disable of I2S (EN[0] = 0) or the Receiver block (RX_EN[0] = 0) overrides this value. • 0x0: Receive Channel Disable • 0x1: Receive Channel Enable 0 1 read-write RX_DMA RX_DMA Receiver Block DMA Register 0x1C0 32 read-write n 0x0 0xFFFFFFFF RX_DMA Receiver Block DMA Register. These bits are used to cycle repeatedly through the enabled receive channel, reading stereo data pairs. 0 1 read-write RX_EN RX_EN I2S Receiver Block Enable Register 0x4 32 read-write n 0x0 0xFFFFFFFF RX_EN Receiver block enable. This bit enables or disables the receiver. A disable on this bit overrides any individual receive channel enables. Value: • 0x0: Receiver disabled • 0x1: Receiver enabled 0 1 read-write RX_FIFO_CFG RX_FIFO_CFG Receive FIFO Configuration Register 0x48 32 read-write n 0x8 0xFFFFFFFF RX_FIFO_TL These bits program the trigger level in the RX FIFO at which the Received Data Available interrupt is generated. Trigger Level = Programmed Value + 1 • 0x0: Interrupt trigger when FIFO level is 1. • 0x1: Interrupt trigger when FIFO level is 2. • 0x2: Interrupt trigger when FIFO level is 3. • 0x3: Interrupt trigger when FIFO level is 4. • 0x4: Interrupt trigger when FIFO level is 5. • 0x5: Interrupt trigger when FIFO level is 6. • 0x6: Interrupt trigger when FIFO level is 7. • 0x7: Interrupt trigger when FIFO level is 8. • 0x8: Interrupt trigger when FIFO level is 9. • 0x9: Interrupt trigger when FIFO level is 10. • 0xA: Interrupt trigger when FIFO level is 11. • 0xB: Interrupt trigger when FIFO level is 12. • 0xC: Interrupt trigger when FIFO level is 13. • 0xD: Interrupt trigger when FIFO level is 14. • 0xE: Interrupt trigger when FIFO level is 15. • 0xF: Interrupt trigger when FIFO level is 16. 0 4 read-write RX_FIFO_FLUSH RX_FIFO_FLUSH Receive FIFO Flush Register 0x50 32 write-only n 0x0 0xFFFFFFFF RX_FIFO_RST Receive Channel FIFO Reset. Writing a 1 to this register flushes an individual RX FIFO (This is a self clearing bit.). A RX channel or block must be disabled prior to writing to this bit. • 0x0: Does not flush an individual RX FIFO. • 0x1: Flushes an individual RX FIFO. 0 1 write-only RX_FIFO_RST RX_FIFO_RST Receiver Block FIFO Reset Register 0x14 32 write-only n 0x0 0xFFFFFFFF RX_FIFO_RST Receiver FIFO Reset. Writing a 1 to this register flushes all the RX FIFOs (this is a self clearing bit). The Receiver Block must be disabled before writing to this bit. • 0x0: Does not flush the RX FIFO • 0x1: Flushes the RX FIFO 0 1 write-only RX_OVER RX_OVER Receive Overrun Register 0x40 32 read-only n 0x0 0xFFFFFFFF RX_CLR_FDO Read this bit to clear the RX FIFO Data Overrun interrupt. • 0x0: RX FIFO write valid • 0x1: RX FIFO write overrun 0 1 read-only SCLK_CFG SCLK_CFG Clock Configuration Register 0x10 32 read-write n 0x0 0xFFFFFFFF SCLK_GAT These bits are used to program the gating of sclk. The programmed gating value must be less than or equal to the largest configured/programmed audio resolution to prevent the truncating of RX/TX data. The I2S Clock Generation block must be disabled (CLK_EN[0] = 0) before making any changes in this value. • 0x0 (NO_CLOCK_GATING): Clock gating is disabled • 0x1 (CLOCK_CYCLES_12): Gating after 12 sclk cycles • 0x2 (CLOCK_CYCLES_16): Gating after 16 sclk cycles • 0x3 (CLOCK_CYCLES_20): Gating after 20 sclk cycles • 0x4 (CLOCK_CYCLES_24): Gating after 24 sclk cycles Exists: This register is only relevant when component is configured to be a master (I2S_MODE_EN = 1). 0 3 read-write WS_SCLK These bits are used to program the number of sclk cycles for which the word select line (ws_out) stays in the left or right sample mode. The I2S Clock Generation block must be disabled (CLK_EN[0] = 0) prior to any changes in this value. • 0x0: 16 sclk cycles • 0x1: 24 sclk cycles • 0x2: 32 sclk cycles Exists: This register is only relevant when component is configured to be a master (I2S_MODE_EN = 1). 3 2 read-write TX_CFG TX_CFG Transmit Configuration Register 0x34 32 read-write n 0x5 0xFFFFFFFF WORD_LEN These bits are used to program the data resolution of the transmitter and ensures the MSB of the data is transmitted first. Programmed resolution must be less than or equal to 0x5. If the selected resolution is greater than 0x5, the transmit channel defaults back to 0x5. The channel must be disabled prior to any changes in this value(TX_EN[0] = 0). • 0x0: Ignore the word length • 0x1: 12-bit data resolution of the transmitter. • 0x2: 16-bit data resolution of the transmitter. • 0x3: 20-bit data resolution of the transmitter. • 0x4: 24-bit data resolution of the transmitter. • 0x5: 32-bit data resolution of the transmitter. 0 3 read-write TX_CH_EN TX_CH_EN Transmit Enable Register 0x2C 32 read-write n 0x1 0xFFFFFFFF TX_CH_EN Transmit channel enable. This bit enables/disables a transmit channel. On enable, the channel begins transmitting on the next left stereo cycle. A global disable of I2S (EN[0] = 0) or Transmitter block (TX_EN[0] = 0) overrides this value. • 0x0: Transmit Channel Disable • 0x1: Transmit Channel Enable 0 1 read-write TX_DMA TX_DMA Transmitter Block DMA Register 0x1C8 32 read-write n 0x0 0xFFFFFFFF TX_DMA Transmitter Block DMA Register. These bits are used to cycle repeatedly through the enabled transmit channel to allow writing of stereo data pairs. 0 1 read-write TX_EN TX_EN I2S Transmitter Block Enable Register 0x8 32 read-write n 0x0 0xFFFFFFFF TX_EN Transmitter block enable. This bit enables or disables the transmitter. A disable on this bit overrides any individual transmit channel enables. Value: • 0x0: Transmitter disabled • 0x1: Transmitter enabled 0 1 read-write TX_FIFO_CFG TX_FIFO_CFG Transmit FIFO Configuration Register 0x4C 32 read-write n 0x8 0xFFFFFFFF TX_FIFO_TL These bits program the trigger level in the RX FIFO at which the Received Data Available interrupt is generated. Trigger Level = Programmed Value + 1 • 0x0: Interrupt trigger when FIFO level is 1. • 0x1: Interrupt trigger when FIFO level is 2. • 0x2: Interrupt trigger when FIFO level is 3. • 0x3: Interrupt trigger when FIFO level is 4. • 0x4: Interrupt trigger when FIFO level is 5. • 0x5: Interrupt trigger when FIFO level is 6. • 0x6: Interrupt trigger when FIFO level is 7. • 0x7: Interrupt trigger when FIFO level is 8. • 0x8: Interrupt trigger when FIFO level is 9. • 0x9: Interrupt trigger when FIFO level is 10. • 0xA: Interrupt trigger when FIFO level is 11. • 0xB: Interrupt trigger when FIFO level is 12. • 0xC: Interrupt trigger when FIFO level is 13. • 0xD: Interrupt trigger when FIFO level is 14. • 0xE: Interrupt trigger when FIFO level is 15. • 0xF: Interrupt trigger when FIFO level is 16. 0 4 read-write TX_FIFO_FLUSH TX_FIFO_FLUSH Transmit FIFO Flush Register 0x54 32 write-only n 0x0 0xFFFFFFFF TX_FIFO_RST Transmit Channel FIFO Reset. Writing a 1 to this register flushes an individual TX FIFO (This is a self clearing bit.). A TX channel or block must be disabled prior to writing to this bit. Value: • 0x0: Does not flush an individual TX FIFO. • 0x1: Flushes an individual TX FIFO. 0 1 write-only TX_FIFO_RST TX_FIFO_RST Transmitter Block FIFO Reset Register 0x18 32 write-only n 0x0 0xFFFFFFFF TX_FIFO_RST Transmitter FIFO Reset. Writing a 1 to this register flushes all the TX FIFOs (this is a self clearing bit). The Transmitter Block must be disabled prior to writing this bit. Value: • 0x0: Does not flush the TX FIFO • 0x1: Flushes the TX FIFO 0 1 write-only TX_OVER TX_OVER Transmit Overrun Register 0x44 32 read-only n 0x0 0xFFFFFFFF TX_CLR_FDO Read this bit to clear the TX FIFO Data Overrun interrupt. • 0x0: TX FIFO write valid • 0x1: TX FIFO write overrun 0 1 read-only I2S_S Inter—IC Sound I2S 0xA000F000 0x0 0x70 registers n I2S_M I2S_M interrupt 29 I2S_S I2S_S interrupt 30 CLK_CFG CLK_CFG I2S Clock Configure Register 0x268 32 read-write n 0x40008 0xFFFFFFFF CLK_SRC_SEL clock divider source select 0: 96M, 1: 32M 18 1 read-write DIV ratio = 1/(div + 2). Duty cycle is not 50 when the number is odd. For example: div = 0, ratio = 1/2 0 12 read-write DIV_EN enable i2s clock divider 16 1 read-write CLK_EN CLK_EN Clock Enable Register 0xC 32 read-write n 0x0 0xFFFFFFFF CLK_EN Clock Generation enable/disable. This bit enables or disables the clock generation signals when I2S is a master. • 0x0: Clock generation disabled • 0x1: Clock generation enabled Note: When the I2S is configured as a slave, this register serves no purpose. 0 1 read-write EN EN I2S Enable Register 0x0 32 read-write n 0x0 0xFFFFFFFF I2S_EN I2S enable. This bit enables or disables I2S. A disable on this bit overrides any other block or channel enables and flushes all FIFOs. Value: 0x0: I2S disabled. 0x1: I2S enabled 0 1 read-write INT_MASK INT_MASK Interrupt Mask Register 0x3C 32 read-write n 0x13 0xFFFFFFFF RX_DAM Mask RX FIFO Data Available interrupt. This bit masks or unmasks an RX FIFO Data Available interrupt. • 0x1: Disable RX FIFO data available interrupt • 0x0: Enable RX FIFO data available interrupt 0 1 read-write RX_FOM Mask RX FIFO Overrun interrupt. This bit masks or unmasks an RX FIFO Overrun interrupt. • 0x1: Disable RX FIFO Overrun interrupt • 0x0: Enable RX FIFO Overrun interrupt 1 1 read-write TX_FEM Mask TX FIFO Empty interrupt. This bit masks or unmasks a TX FIFO Empty interrupt. • 0x1: Disable TX FIFO Empty interrupt • 0x0: Enable TX FIFO Empty interrupt 4 1 read-write TX_FOM Mask TX FIFO Overrun interrupt. This bit masks or unmasks a TX FIFO overrun interrupt. • 0x1: Disable TX FIFO Overrun interrupt • 0x0: Enable TX FIFO Overrun interrupt 5 1 read-write INT_STAT INT_STAT Interrupt status Register 0x38 32 read-only n 0x10 0xFFFFFFFF RX_DATA_AVL Status of Receive Data Available interrupt. This bit denotes the status of the RX FIFO trigger level. • 0x1: RX FIFO trigger level is reached • 0x0: RX FIFO trigger level is not reached 0 1 read-only RX_FIFO_OVER Status of Data Overrun interrupt for the RX channel. Incoming data lost due to a full RX FIFO. • 0x0: RX FIFO write valid • 0x1: RX FIFO write overrun 1 1 read-only TX_FIFO_EMPTY Status of Transmit Empty Trigger interrupt. This bit specifies whether the TX FIFO trigger level has reached or not. TX FIFO is empty. • 0x0: TX FIFO trigger level is reached • 0x1: TX FIFO trigger level is not reached 4 1 read-only TX_FIFO_OVER Status of Data Overrun interrupt for the TX channel. This bit specifies whether the TX FIFO write is valid or an overrun. Attempt to write to full TX FIFO. • 0x0: TX FIFO write valid • 0x1: TX FIFO write overrun 5 1 read-only LEFT_RX_BUF LEFT_RX_BUF Left Receive Buffer Register 0x20 32 read-only n 0x0 0xFFFFFFFF LEFT_RX_BUF The left stereo data received serially from the receive channel input (sdi). If the RX FIFO is full and the two-stage read operation (for instance, a read from LEFT_RX_BUF register followed by a read from RIGHT_RX_BUF register) is not performed before the start of the next stereo pair, then the new data is lost and an overrun interrupt occurs. (data already in the RX FIFO is preserved.) Note: Before reading this register again, the right stereo data must be read from RRBRx or the status/interrupts will not be valid. 0 32 read-only LEFT_TX_HDG LEFT_TX_HDG Left Transmit Holding Register LEFT_RX_BUF 0x20 32 write-only n 0x0 0xFFFFFFFF LEFT_TX_HDG The left stereo data to be transmitted serially through the transmit channel output (sdo) is written through this register. Writing is a two-stage process: 1. A write to this register passes the left stereo sample to the transmitter. 2. This MUST be followed by writing the right stereo sample to the RIGHT_TX_HDG register. Data must only be written to the FIFO when it is not full. Any attempt to write to a full FIFO results in that data being lost and an overrun interrupt being generated. 0 32 write-only RIGHT_RX_BUF RIGHT_RX_BUF Right Receive Buffer Register 0x24 32 read-only n 0x0 0xFFFFFFFF RIGHT_RX_BUF The right stereo data received serially from the receive channel input (sdi) is read through this register. If the RX FIFO is full and the two-stage read operation (for instance, read from LEFT_RX_BUF register followed by a read from RIGHT_RX_BUF register) is not performed before the start of the next stereo pair, then the new data is lost and an overrun interrupt occurs. (Data already in the RX FIFO is preserved.) Note: Prior to reading this register, the left stereo data MUST be read from LEFT_RX_BUF register, or the status/interrupts will not be valid. 0 32 read-only RIGHT_TX_HDG RIGHT_TX_HDG Right Transmit Holding Register RIGHT_RX_BUF 0x24 32 write-only n 0x0 0xFFFFFFFF RIGHT_TX_HDG The right stereo data to be transmitted serially through the transmit channel output (sdo) is written through this register. Writing is a two-stage process: 1. A left stereo sample MUST be written to the LTHR register. 2. A write to this register passes the right stereo sample to the transmitter. Data should only be written to the FIFO when it is not full. Any attempt to write to a full FIFO results in that data being lost and an overrun interrupt being generated. 0 32 write-only RST_RX_DMA RST_RX_DMA Reset Receiver Block DMA Register 0x1C4 32 write-only n 0x0 0xFFFFFFFF RST_RX_DMA Reset Receiver Block DMA Register. Writing a 1 to this self-clearing register resets the RXDMA register mid-cycle to point to the enabled Receive channel. • 0x0: No effect. • 0x1: Reset receiver block DMA register. 0 1 write-only RST_TX_DMA RST_TX_DMA Reset Transmitter Block DMA Register 0x1CC 32 write-only n 0x0 0xFFFFFFFF RST_TX_DMA Reset Transmitter Block DMA Register. Writing a 1 to this self-clearing register resets the TXDMA register mid-cycle to point to the enabled Transmit channel. • 0x0: No effect. • 0x1: Reset transmitter block DMA register. 0 1 write-only RX_CFG RX_CFG Receive Configuration Register 0x30 32 read-write n 0x5 0xFFFFFFFF WORD_LEN These bits are used to program the desired data resolution of the receiver and enables the LSB of the incoming left (or right) word to be placed in the LSB of the LEFT_RX_BUF (or RIGHT_RX_BUF) register. Programmed data resolution must be less than or equal to 0x5. If the selected resolution is greater than the 0x5, the receive channel defaults back to 0x5. The channel must be disabled prior to any changes in this value(RX_EN[0] = 0). • 0x0: Ignore the word length • 0x1: 12-bit data resolution of the receiver. • 0x2: 16-bit data resolution of the receiver. • 0x3: 20-bit data resolution of the receiver. • 0x4: 24-bit data resolution of the receiver. • 0x5: 32-bit data resolution of the receiver. 0 3 read-write RX_CH_EN RX_CH_EN Receive Enable Register 0x28 32 read-write n 0x1 0xFFFFFFFF RX_CH_EN Receive channel enable. This bit enables/disables a receive channel. On enable, the channel begins receiving on the next left stereo cycle. A global disable of I2S (EN[0] = 0) or the Receiver block (RX_EN[0] = 0) overrides this value. • 0x0: Receive Channel Disable • 0x1: Receive Channel Enable 0 1 read-write RX_DMA RX_DMA Receiver Block DMA Register 0x1C0 32 read-write n 0x0 0xFFFFFFFF RX_DMA Receiver Block DMA Register. These bits are used to cycle repeatedly through the enabled receive channel, reading stereo data pairs. 0 1 read-write RX_EN RX_EN I2S Receiver Block Enable Register 0x4 32 read-write n 0x0 0xFFFFFFFF RX_EN Receiver block enable. This bit enables or disables the receiver. A disable on this bit overrides any individual receive channel enables. Value: • 0x0: Receiver disabled • 0x1: Receiver enabled 0 1 read-write RX_FIFO_CFG RX_FIFO_CFG Receive FIFO Configuration Register 0x48 32 read-write n 0x8 0xFFFFFFFF RX_FIFO_TL These bits program the trigger level in the RX FIFO at which the Received Data Available interrupt is generated. Trigger Level = Programmed Value + 1 • 0x0: Interrupt trigger when FIFO level is 1. • 0x1: Interrupt trigger when FIFO level is 2. • 0x2: Interrupt trigger when FIFO level is 3. • 0x3: Interrupt trigger when FIFO level is 4. • 0x4: Interrupt trigger when FIFO level is 5. • 0x5: Interrupt trigger when FIFO level is 6. • 0x6: Interrupt trigger when FIFO level is 7. • 0x7: Interrupt trigger when FIFO level is 8. • 0x8: Interrupt trigger when FIFO level is 9. • 0x9: Interrupt trigger when FIFO level is 10. • 0xA: Interrupt trigger when FIFO level is 11. • 0xB: Interrupt trigger when FIFO level is 12. • 0xC: Interrupt trigger when FIFO level is 13. • 0xD: Interrupt trigger when FIFO level is 14. • 0xE: Interrupt trigger when FIFO level is 15. • 0xF: Interrupt trigger when FIFO level is 16. 0 4 read-write RX_FIFO_FLUSH RX_FIFO_FLUSH Receive FIFO Flush Register 0x50 32 write-only n 0x0 0xFFFFFFFF RX_FIFO_RST Receive Channel FIFO Reset. Writing a 1 to this register flushes an individual RX FIFO (This is a self clearing bit.). A RX channel or block must be disabled prior to writing to this bit. • 0x0: Does not flush an individual RX FIFO. • 0x1: Flushes an individual RX FIFO. 0 1 write-only RX_FIFO_RST RX_FIFO_RST Receiver Block FIFO Reset Register 0x14 32 write-only n 0x0 0xFFFFFFFF RX_FIFO_RST Receiver FIFO Reset. Writing a 1 to this register flushes all the RX FIFOs (this is a self clearing bit). The Receiver Block must be disabled before writing to this bit. • 0x0: Does not flush the RX FIFO • 0x1: Flushes the RX FIFO 0 1 write-only RX_OVER RX_OVER Receive Overrun Register 0x40 32 read-only n 0x0 0xFFFFFFFF RX_CLR_FDO Read this bit to clear the RX FIFO Data Overrun interrupt. • 0x0: RX FIFO write valid • 0x1: RX FIFO write overrun 0 1 read-only SCLK_CFG SCLK_CFG Clock Configuration Register 0x10 32 read-write n 0x0 0xFFFFFFFF SCLK_GAT These bits are used to program the gating of sclk. The programmed gating value must be less than or equal to the largest configured/programmed audio resolution to prevent the truncating of RX/TX data. The I2S Clock Generation block must be disabled (CLK_EN[0] = 0) before making any changes in this value. • 0x0 (NO_CLOCK_GATING): Clock gating is disabled • 0x1 (CLOCK_CYCLES_12): Gating after 12 sclk cycles • 0x2 (CLOCK_CYCLES_16): Gating after 16 sclk cycles • 0x3 (CLOCK_CYCLES_20): Gating after 20 sclk cycles • 0x4 (CLOCK_CYCLES_24): Gating after 24 sclk cycles Exists: This register is only relevant when component is configured to be a master (I2S_MODE_EN = 1). 0 3 read-write WS_SCLK These bits are used to program the number of sclk cycles for which the word select line (ws_out) stays in the left or right sample mode. The I2S Clock Generation block must be disabled (CLK_EN[0] = 0) prior to any changes in this value. • 0x0: 16 sclk cycles • 0x1: 24 sclk cycles • 0x2: 32 sclk cycles Exists: This register is only relevant when component is configured to be a master (I2S_MODE_EN = 1). 3 2 read-write TX_CFG TX_CFG Transmit Configuration Register 0x34 32 read-write n 0x5 0xFFFFFFFF WORD_LEN These bits are used to program the data resolution of the transmitter and ensures the MSB of the data is transmitted first. Programmed resolution must be less than or equal to 0x5. If the selected resolution is greater than 0x5, the transmit channel defaults back to 0x5. The channel must be disabled prior to any changes in this value(TX_EN[0] = 0). • 0x0: Ignore the word length • 0x1: 12-bit data resolution of the transmitter. • 0x2: 16-bit data resolution of the transmitter. • 0x3: 20-bit data resolution of the transmitter. • 0x4: 24-bit data resolution of the transmitter. • 0x5: 32-bit data resolution of the transmitter. 0 3 read-write TX_CH_EN TX_CH_EN Transmit Enable Register 0x2C 32 read-write n 0x1 0xFFFFFFFF TX_CH_EN Transmit channel enable. This bit enables/disables a transmit channel. On enable, the channel begins transmitting on the next left stereo cycle. A global disable of I2S (EN[0] = 0) or Transmitter block (TX_EN[0] = 0) overrides this value. • 0x0: Transmit Channel Disable • 0x1: Transmit Channel Enable 0 1 read-write TX_DMA TX_DMA Transmitter Block DMA Register 0x1C8 32 read-write n 0x0 0xFFFFFFFF TX_DMA Transmitter Block DMA Register. These bits are used to cycle repeatedly through the enabled transmit channel to allow writing of stereo data pairs. 0 1 read-write TX_EN TX_EN I2S Transmitter Block Enable Register 0x8 32 read-write n 0x0 0xFFFFFFFF TX_EN Transmitter block enable. This bit enables or disables the transmitter. A disable on this bit overrides any individual transmit channel enables. Value: • 0x0: Transmitter disabled • 0x1: Transmitter enabled 0 1 read-write TX_FIFO_CFG TX_FIFO_CFG Transmit FIFO Configuration Register 0x4C 32 read-write n 0x8 0xFFFFFFFF TX_FIFO_TL These bits program the trigger level in the RX FIFO at which the Received Data Available interrupt is generated. Trigger Level = Programmed Value + 1 • 0x0: Interrupt trigger when FIFO level is 1. • 0x1: Interrupt trigger when FIFO level is 2. • 0x2: Interrupt trigger when FIFO level is 3. • 0x3: Interrupt trigger when FIFO level is 4. • 0x4: Interrupt trigger when FIFO level is 5. • 0x5: Interrupt trigger when FIFO level is 6. • 0x6: Interrupt trigger when FIFO level is 7. • 0x7: Interrupt trigger when FIFO level is 8. • 0x8: Interrupt trigger when FIFO level is 9. • 0x9: Interrupt trigger when FIFO level is 10. • 0xA: Interrupt trigger when FIFO level is 11. • 0xB: Interrupt trigger when FIFO level is 12. • 0xC: Interrupt trigger when FIFO level is 13. • 0xD: Interrupt trigger when FIFO level is 14. • 0xE: Interrupt trigger when FIFO level is 15. • 0xF: Interrupt trigger when FIFO level is 16. 0 4 read-write TX_FIFO_FLUSH TX_FIFO_FLUSH Transmit FIFO Flush Register 0x54 32 write-only n 0x0 0xFFFFFFFF TX_FIFO_RST Transmit Channel FIFO Reset. Writing a 1 to this register flushes an individual TX FIFO (This is a self clearing bit.). A TX channel or block must be disabled prior to writing to this bit. Value: • 0x0: Does not flush an individual TX FIFO. • 0x1: Flushes an individual TX FIFO. 0 1 write-only TX_FIFO_RST TX_FIFO_RST Transmitter Block FIFO Reset Register 0x18 32 write-only n 0x0 0xFFFFFFFF TX_FIFO_RST Transmitter FIFO Reset. Writing a 1 to this register flushes all the TX FIFOs (this is a self clearing bit). The Transmitter Block must be disabled prior to writing this bit. Value: • 0x0: Does not flush the TX FIFO • 0x1: Flushes the TX FIFO 0 1 write-only TX_OVER TX_OVER Transmit Overrun Register 0x44 32 read-only n 0x0 0xFFFFFFFF TX_CLR_FDO Read this bit to clear the TX FIFO Data Overrun interrupt. • 0x0: TX FIFO write valid • 0x1: TX FIFO write overrun 0 1 read-only ISO7816 SIM Interface block （ISO/IEC 7816-3 ） ISO7816 0xA000F200 0x0 0x24 registers n ISO7816 ISO7816 Interrupt 31 ADDR ADDR Address Register 0x18 32 read-only n 0x0 0xFFFFFFFF ADDR • Address. • Current address relative to base_addr. 2 18 read-only ADDR_FRAC Address Fraction. Byte selection. 0 2 read-only CLK_CFG CLK_CFG Clock Configuration Register 0x8 32 read-write n 0x2F0173 0xFFFFFFFF CLK_DIV • Clock Division. • Divide system clock by this value + 1. 16 8 read-write CLK_STOP_SEL Clock Stop Select. Value of the clock output during stopped clock. 0x0: Low 0x1: High 31 1 read-write ETU_DIV Divide SIM clock by this value+1 to define ETU length. The reset value is the one, needed for the ATR. 0 10 read-write CTRL CTRL Control Register 0x0 32 write-only n 0x0 0xFFFFFFFF ACTION 0x0: Do Nothing. 0x1: Switch off. 0x2: Stop the clock. 0x3: Switch on and receive ATR. Re-enable clock if clock is stoped. 0x4: Trigger warm reset and receive ATR. 0x5: Receive. 0x6: Transmit. 0x7: Transmit, followed by RX 0 3 write-only IRQ_DMA_EC Interrupt source dma_err clear. This register clears interrupt source ‘STAT.INT_DMA_ERR’. 0x0: No effect 0x1: Clear 23 1 write-only IRQ_DONE_CLR Interrupt source done clear. This register clears interrupt source ‘STAT.INT_DONE’. 0x0: No effect 0x1: Clear 20 1 write-only IRQ_PRESENCE_CLR Interrupt source presence clear. This register clears interrupt source ‘STAT.INT_PRESENCE’. 0x0: No effect 0x1: Clear 25 1 write-only IRQ_RETYR_EC Interrupt source retry_err clear. This register clears interrupt source ‘STAT.IRQ_RETYR_ERR’. 0x0: No effect 0x1: Clear 22 1 write-only IRQ_RX_EC Interrupt source rx_err clear. This register clears interrupt source ‘STAT.INT_RX_ERR’. 0x0: No effect 0x1: Clear 21 1 write-only IRQ_STAT_EC Interrupt source state_err clear. This register clears interrupt source ‘STAT.INT_STAT_ERR’. 0x0: No effect 0x1: Clear 24 1 write-only IRQ_TEST_CLR Interrupt Test Clear. This register clears test interrupt (has higher priority than ‘INT_TEST_SET’) 0x0: No effect 0x1: Clear 30 1 write-only IRQ_TEST_SET Interrupt Test Set. This register sets test interrupt 0x0: No effect 0x1: Set 31 1 write-only RX_RETYR_MC Receive Retries Maximum Clear. This register clears ‘STAT.RX_RETRY_MAX’. 0x0: No effect 0x1: Clear 8 1 write-only TX_RETYR_MC Transmit Retries Maximum Clear. This register clears ‘STAT.TX_RETRY_MAX’. 0x0: No effect 0x1: Clear 12 1 write-only DATA_CFG DATA_CFG Data Configuration Register 0x14 32 read-write n 0x2 0xFFFFFFFF CODING Coding Convention. 0x0: Default. High = 1, LSB first. 0x1: Inverse. High = 0, MSB first. 0 1 read-write DETECT_CODING Detect Coding Convention. Automatically detect coding convention during ATR receiption. 0x0: Disable 0x1: Enable 1 1 read-write RETRY_LIMIT • Retries Limit. • Maximum number of issued retries before giving up. 4 3 read-write RX_END_ADDR RX_END_ADDR RX End Address Register 0x20 32 read-only n 0x0 0xFFFFFFFF RX_END_ADDR • RX End Address. • End address of receive buffer, relative to base_addr. 2 18 read-only RX_END_AF RX End Address Fraction. Byte selection. 0 2 read-only START_ADDR START_ADDR Start Address Register 0x1C 32 read-write n 0x0 0xFFFFFFFF BASE_ADDR Base Address. Base Address for RX and TX Buffer. 20 12 read-write START_ADDR • Address. • Current address relative to base_addr. 2 18 read-write STAT STAT Status Register 0x4 32 read-only n 0x20000 0xFFFFFFFF BUSY Status of SIM interface. 0x0: Idle 0x1: Busy 16 1 read-only IO_STAT Receive Retries Maximum Clear. This register clears ‘STAT.RX_RETRY_MAX’. 0x0: No effect 0x1: Clear 4 3 read-only IRQ_DMA_ERR Interrupt DMA Error. DMA read/write operation could not be issued. 0x0: No interrupt 0x1: Active 23 1 read-only IRQ_DONE Interrupt Done. Requeted operation has been completed. 0x0: No interrupt 0x1: Active 20 1 read-only IRQ_PRESENCE Interrupt Presence. SIM card presence changed. Inserted or removed. 0x0: No interrupt 0x1: Active 25 1 read-only IRQ_RETRY_ERR Interrupt Retry Error. Maximum number of retries exceeded. 0x0: No interrupt 0x1: Active 22 1 read-only IRQ_RX_ERR Interrupt RX Error. No or incomplete or unexpected data. 0x0: No interrupt 0x1: Active 21 1 read-only IRQ_STAT_ERR Interrupt State Error. Action rerquested while busy or unsupported transition. 0x0: No interrupt 0x1: Active 24 1 read-only IRQ_TEST Interrupt Test. Test interrupt for connection check. 0x0: No interrupt 0x1: Active 30 1 read-only PRESENCE_STAT Status of presence IO. 0x0: Absent 0x1: Presence 17 1 read-only PWR_STAT Power States. 0x0: SIM is unpowered. 0x1: Power up SIM. RST asserted(low). Clock stopped. IO is tristate. 0x2: Power up SIM. RST asserted(low). Clock is running. IO is high. 0x3: Power up SIM. RST asserted(low). Clock is running. IO is tristate. 0x4: Power up SIM. RST asserted(low). Clock stopped. IO is low. 0x5: Preparing clock stop. 0x6: Clock stopped. 0x7: Exiting clock stop 0x8: SIM is idle, no communication is ongoing. 0x9: RX TS Character. 0xA: RX TS Character. 0XB: Receive. 0xC: Transmit. 0xD: Transmit and Receive 0 4 read-only RX_RETRY_MAX Receive Retries Maximum. Maximum number of seen receive retries after parity error. 8 3 read-only TX_RETRY_MAX Transmit Retries Maximum. Maximum number of seen transmit retries after error signaling by SIM. 12 3 read-only TIMES_CFG TIMES_CFG Times Configuration Register 0x10 32 read-write n 0x6B000 0xFFFFFFFF GUARD_TIME Guard time in [ETU]. Time between the leading edges of two consecutive characters. 0 10 read-write WAIT_TIME • Wait time in [ETU]. • Maximum card response time (leading edge to leading edge). 12 18 read-write TX_END_ADDR TX_END_ADDR TX End Address Register 0x24 32 read-only n 0x0 0xFFFFFFFF TX_END_ADDR TX End Address. • End address of transmit buffer, relative to base_addr. 2 18 read-only TX_END_AF TX End Address Fraction. Byte selection. 0 2 read-only PIN_MUX pin multiplexing PIN_MUX 0xA000C530 0x0 0x38 registers n ANO_PAD_CTRL0 ANO_PAD_CTRL0 AON PAD control 0 Register 0x20 32 read-write n 0x0 0xFFFFFFFF AON_MCU_OVE Use the setting from MCU domain, Only valid when MCU domain is ON 0x0: Disable AONx digital setting 0x1: Enable AONx digital setting 16 8 read-write AON_R_EN Always on PAD resister enable 0x0: Enable AONx resistor 0x1: Disable AONx resistor 0 8 read-write AON_R_TYPE Always on PAD resistor type 0x0: Pull down 0x1: Pull up 8 8 read-write TIMER_CLK_SEL comm timer clock select 0x0: rng_osc_clk 0x1: rtc_osc_clk 0x2, 0x3: rng_2_osc_clk (an rng clock with better ppm) 28 2 read-write ANO_PAD_CTRL1 ANO_PAD_CTRL1 AON PAD control 0 Register 0x2C 32 read-write n 0xFF 0xFFFFFFFF AON_OUT_EN Always on PAD output enable (active low) 0x0: Enable AONx output 0x1: Disable AONx output 0 8 read-write AON_OUT_VAL AON PAD output value (valid when oe_n = 0) 0x0: Drive AONx low 0x1: Drive AONx high 8 8 read-write OVR_EN Enable override for all stdby_n and vdd_iso_n value 25 1 read-write TIMER_RD_SEL Select which timer value to read 0x0: calendar timer 0x1: always on watchdog timer 0x2: sleep timer 0x3: Calendar timer alarm value 30 2 read-write AON_PAD_MUX_CTRL AON_PAD_MUX_CTRL Always-on PAD mux control register 0x1D60 32 read-write n 0x777770 0xFFFFFFFF AON_PAD_MUX_SEL_01 Mode for AON PAD [1] 4 3 read-write AON_PAD_MUX_SEL_02 Mode for AON PAD [2] 8 3 read-write AON_PAD_MUX_SEL_03 Mode for AON PAD [3] 12 3 read-write AON_PAD_MUX_SEL_04 Mode for AON PAD [4] 16 3 read-write AON_PAD_MUX_SEL_05 Mode for AON PAD [5] 20 3 read-write DPAD_IN_EN DPAD_IN_EN Resistor enable active lO inputs to the RETENTION PAD 0x1CD8 32 read-write n 0x0 0xFFFFFFFF DPAD_IN_EN Resistor enable active lO inputs to the RETENTION PAD 0x0: Enable resistor inputs to pad (GPIO_0 – GPIO_31) 0x1: Disable resistor inputs to pad (GPIO_ 0 – GPIO_31) 0 32 read-write DPAD_MUX_CTRL_00_07 DPAD_MUX_CTRL_00_07 DPAD mux control GPIO_0 – GPIO_7 register 0x1D10 32 read-write n 0x77777700 0xFFFFFFFF DPAD_MUX_SEL_00 Mode for DPAD 0 0 4 read-write DPAD_MUX_SEL_01 Mode for DPAD 1 4 4 read-write DPAD_MUX_SEL_02 Mode for DPAD 2 8 4 read-write DPAD_MUX_SEL_03 Mode for DPAD 3 12 4 read-write DPAD_MUX_SEL_04 Mode for DPAD 4 16 4 read-write DPAD_MUX_SEL_05 Mode for DPAD 5 20 4 read-write DPAD_MUX_SEL_06 Mode for DPAD 6 24 4 read-write DPAD_MUX_SEL_07 Mode for DPAD 7 28 4 read-write DPAD_MUX_CTRL_08_15 DPAD_MUX_CTRL_08_15 DPAD mux control GPIO_8 – GPIO_15 register 0x1D14 32 read-write n 0x77777777 0xFFFFFFFF DPAD_MUX_SEL_08 Mode for DPAD 8 0 4 read-write DPAD_MUX_SEL_09 Mode for DPAD 9 4 4 read-write DPAD_MUX_SEL_10 Mode for DPAD 10 8 4 read-write DPAD_MUX_SEL_11 Mode for DPAD 11 12 4 read-write DPAD_MUX_SEL_12 Mode for DPAD 12 16 4 read-write DPAD_MUX_SEL_13 Mode for DPAD 13 20 4 read-write DPAD_MUX_SEL_14 Mode for DPAD 14 24 4 read-write DPAD_MUX_SEL_15 Mode for DPAD 15 28 4 read-write DPAD_MUX_CTRL_16_23 DPAD_MUX_CTRL_16_23 DPAD mux control GPIO_16 – GPIO_23 register 0x1D18 32 read-write n 0x77777777 0xFFFFFFFF DPAD_MUX_SELL_22 Mode for DPAD 22 24 4 read-write DPAD_MUX_SEL_16 Mode for DPAD 16 0 4 read-write DPAD_MUX_SEL_17 Mode for DPAD 17 4 4 read-write DPAD_MUX_SEL_18 Mode for DPAD 18 8 4 read-write DPAD_MUX_SEL_19 Mode for DPAD 19 12 4 read-write DPAD_MUX_SEL_20 Mode for DPAD 20 16 4 read-write DPAD_MUX_SEL_21 Mode for DPAD 21 20 4 read-write DPAD_MUX_SEL_23 Mode for DPAD 23 28 4 read-write DPAD_MUX_CTRL_24_31 DPAD_MUX_CTRL_24_31 DPAD mux control GPIO_24– GPIO_31 register 0x1D1C 32 read-write n 0x77777777 0xFFFFFFFF DPAD_MUX_SEL_24 Mode for DPAD 24 0 4 read-write DPAD_MUX_SEL_25 Mode for DPAD 25 4 4 read-write DPAD_MUX_SEL_26 Mode for DPAD 26 8 4 read-write DPAD_MUX_SEL_27 Mode for DPAD 27 12 4 read-write DPAD_MUX_SEL_28 Mode for DPAD 28 16 4 read-write DPAD_MUX_SEL_29 Mode for DPAD 29 20 4 read-write DPAD_MUX_SEL_30 Mode for DPAD 30 24 4 read-write DPAD_MUX_SEL_31 Mode for DPAD 31 28 4 read-write DPAD_OUT_EN DPAD_OUT_EN Output enable active lO inputs to the RETENTION PAD 0x1CE8 32 read-write n 0x0 0xFFFFFFFF DPAD_OUT_EN Output enable active lO inputs to the RETENTION PAD 0x0: Enable output. 0x1: Disable output. 0 32 read-write DPAD_PULL_TYPE DPAD_PULL_TYPE Resistor type inputs to the RETENTION PAD. 0x1CE0 32 read-write n 0x0 0xFFFFFFFF DPAD_R_TYPE Resistor type inputs to the RETENTION PAD. 0x0: Pull down (when DPAD_IN_EN = 0) 0x1: Pull up (when DPAD_IN_EN = 0) 0 32 read-write MSIO_PAD_CFG0 MSIO_PAD_CFG0 MISO PAD Configuration 0 Register 0xC 32 read-write n 0x0 0xFFFFFFFF MSIO_IN_EN MSIO input enable (active low) 0x0: Enable MSIOx input 0x1: Disable MSIOx input 16 5 read-write MSIO_OUT MSIO Drive value (valid in output mode) 0x0: Drive MSIOx low 0x1: Drive MSIOx high 8 5 read-write MSIO_OUT_EN MSIO output enable (active low) 0x0: Enable MSIOx output 0x1: Disable MSIOx output 24 5 read-write MSIO_R_EN MSIO resistor enable (active low) 0x0: Enable MSIOx resistor 0x1: Disable MSIOx resistor 0 5 read-write MSIO_PAD_CFG1 MSIO_PAD_CFG1 MISO PAD Configuration 1 Register 0x10 32 read-write n 0x0 0xFFFFFFFF DEP_CTRL_RD deep sleep control comm timer register read bit 15 1 read-only DEP_CTRL_WR deep sleep control comm timer register write bit 16 6 read-write MSIO_A_EN Analog enable control for MSIO Pad 0x0: Analog mode 0x1: Digital mode 0 5 read-write MSIO_MCU_OVE Use the setting from MCU domain, Only valid when MCU domain is ON 0x0: Disable MSIOx digital setting 0x1: Enable MSIOx digital setting 22 5 read-write MSIO_R_TYPE MSIO resistor type 0x0: Pull down 0x1: Pull up 8 5 read-write SADC_CLK_EN ADC clock Enable 0x0: Disable ADC clock 0x1: Enable ADC clock 31 1 read-write SADC_CLK_SEL ADC clock select 0x0: 16 M 0x1: 8 M 0x2: 4 M 0x3: 2 M 0x4, 0x6: 1.6 M 0x5, 0x7: 1 M 28 3 read-write MSIO_PAD_MUX_CTRL MSIO_PAD_MUX_CTRL Always-on PAD mux control register 0x1D64 32 read-write n 0x77777 0xFFFFFFFF MSIO_PAD_MUX_SELL_01 Mode for MSIO PAD [1] 4 3 read-write MSIO_PAD_MUX_SEL_00 Mode for MSIO PAD [0] 0 3 read-write MSIO_PAD_MUX_SEL_02 Mode for MSIO PAD [2] 8 3 read-write MSIO_PAD_MUX_SEL_03 Mode for MSIO PAD [3] 12 3 read-write MSIO_PAD_MUX_SEL_04 Mode for MSIO PAD [4] 16 3 read-write MSIO_VAL MSIO_VAL MSIO Digital value register 0x1CF0 32 read-write n 0x0 0xFFFFFFFF MSIO_VAL MSIO Digital value (when MSIO_PAD_CFG1.MSIO_A_EN = 1) 0 5 read-write PKC Public Key Cryptography PKC 0xA0014000 0x0 0x84 registers n PKC PKC interrupt 21 CFG0 CFG0 PKC Configuration 0 Register 0x4 32 read-write n 0x100000 0xFFFFFFFF K_POINT K point in sp_ram 0 9 read-write R_POINT R point in sp_ram 16 9 read-write CFG1 CFG1 PKC Configuration 1 Register 0x8 32 read-write n 0x280020 0xFFFFFFFF P_POINT p point in sp_ram 0 9 read-write R2_POINT R^2 point in sp_ram 16 9 read-write CFG10 CFG10 PKC Configuration 10 Register 0x2C 32 read-write n 0xB800B0 0xFFFFFFFF X1_POINT X1 point in sp_ram 0 9 read-write X2_POINT X2 point in sp_ram 16 9 read-write CFG11 CFG11 PKC Configuration 11 Register 0x30 32 read-write n 0xC800C0 0xFFFFFFFF KT_POINT software compute 2^256 mod point and write to sp_ram 16 9 read-write MIT_POINT Only used in hardware mode, mi point in sp_ram 0 9 read-write CFG12 CFG12 PKC Configuration 12 Register 0x34 32 read-write n 0xD800D0 0xFFFFFFFF A_POINT Curve parameter a in Montgomery field 0 9 read-write B_POINT Curve parameter b in Montgomery field 16 9 read-write CFG13 CFG13 PKC Configuration 13 Register 0x38 32 read-write n 0x1 0xFFFFFFFF CONSTQ Constant used in Montgomery Multiplication 0 32 read-write CFG2 CFG2 PKC Configuration 2 Register 0xC 32 read-write n 0x380030 0xFFFFFFFF GX_POINT Gx point in sp_ram 0 9 read-write GY_POINT Gy point in sp_ram 16 9 read-write CFG3 CFG3 PKC Configuration 3 Register 0x10 32 read-write n 0x480040 0xFFFFFFFF GZ_POINT Gz point in sp_ram 0 9 read-write R0X_POINT R0x point in sp_ram 16 9 read-write CFG4 CFG4 PKC Configuration 4 Register 0x14 32 read-write n 0x580050 0xFFFFFFFF R0Y_POINT R0y point in sp_ram 0 9 read-write R0Z_POINT R0z point in sp_ram 16 9 read-write CFG5 CFG5 PKC Configuration 5 Register 0x18 32 read-write n 0x680060 0xFFFFFFFF R1X_POINT R1x point in sp_ram 0 9 read-write R1Y_POINT R1y point in sp_ram 16 9 read-write CFG6 CFG6 PKC Configuration 6 Register 0x1C 32 read-write n 0x780070 0xFFFFFFFF R1Z_POINT R1z point in sp_ram 0 9 read-write TEMP1_POINT temp1 point in sp_ram 16 9 read-write CFG7 CFG7 PKC Configuration 7 Register 0x20 32 read-write n 0x880080 0xFFFFFFFF TEMP2_POINT temp2 point in sp_ram 0 9 read-write TEMP3_POINT temp3 point in sp_ram 16 9 read-write CFG8 CFG8 PKC Configuration 8 Register 0x24 32 read-write n 0x980090 0xFFFFFFFF TEMP4_POINT temp4 point in sp_ram 0 9 read-write TEMP5_POINT temp5 point in sp_ram 16 9 read-write CFG9 CFG9 PKC Configuration 9 Register 0x28 32 read-write n 0xA800A0 0xFFFFFFFF CONT1_POINT constant 1 point in sp_ram 16 9 read-write TEMP6_POINT temp6 point in sp_ram 0 9 read-write CTRL CTRL PKC Controller Register 0x0 32 read-write n 0x0 0xFFFFFFFF EN pkc core enable 0x0: disable PKC 0x1: enable PKC 0 1 read-write RST Write 0 and then write 1 to this bit, force PKC core to reset 8 1 read-write START Only used in hardware mode. After MCU configure all parameters, write 0 and then write 1 to this bit, PKC start to work 1 1 read-write SW_CTRL Only used in hardware mode. After MCU configure all parameters, write 0 and then write 1 to this bit, PKC start to work 4 1 read-write INT_EN INT_EN PKC Interrupt Enable Register 0x84 32 read-write n 0x0 0xFFFFFFFF BIAO_INT_EN PKC big integer add overflow interrupt enable 2 1 read-write CPLT_INT_EN PKC complete interrupt enable 0 1 read-write ERR_INT_EN PKC error interrupt enable 1 1 read-write INT_STAT INT_STAT PKC Interrupt Status Register 0x80 32 read-write n 0x0 0xFFFFFFFF BIAO_INT_FLAG PKC big integer add overflow flag, write 1 to clear 2 1 read-write CPLT_INT_FLAG PKC complete interrupt flag, write 1 to clear 0 1 read-write ERR_INT_FLAG PKC error interrupt flag, write 1 to clear 1 1 read-write STAT STAT PKC Status Register 0x88 32 read-only n 0x0 0xFFFFFFFF BUSY PKC busy status 0 1 read-only SW_CFG0 SW_CFG0 PKC Software Configuration 0 Register 0x44 32 read-write n 0x80000 0xFFFFFFFF MMA_POINT Modular multiplication A point in sp_ram 0 9 read-write MMB_POINT Modular multiplication B point in sp_ram 16 9 read-write SW_CFG1 SW_CFG1 PKC Software Configuration 1 Register 0x48 32 read-write n 0x180010 0xFFFFFFFF MMC_POINT Modular multiplication C point in sp_ram 16 9 read-write MMP_POINT Modular multiplication P point in sp_ram 0 9 read-write SW_CFG10 SW_CFG10 PKC Software Configuration 10 Register 0x6C 32 read-write n 0x780070 0xFFFFFFFF BMA_POINT Big multiplication A point in sp_ram 0 9 read-write BMB_POINT Big multiplication B point in sp_ram 16 9 read-write SW_CFG11 SW_CFG11 PKC Software Configuration 11 Register 0x70 32 read-write n 0x880080 0xFFFFFFFF BAA_POINT Big addition A point in sp_ram 16 9 read-write BMC_POINT Big multiplication C point in sp_ram 0 9 read-write SW_CFG12 SW_CFG12 PKC Software Configuration 12 Register 0x74 32 read-write n 0x980090 0xFFFFFFFF BAB_POINT Big addition B point in sp_ram 0 9 read-write BAC_POINT Big addition C point in sp_ram 16 9 read-write SW_CFG13 SW_CFG13 PKC Software Configuration 13 Register 0x78 32 read-write n 0x11223344 0xFFFFFFFF RCG_SEED Random clock gating seed 0 32 read-write SW_CFG2 SW_CFG2 PKC Software Configuration 2 Register 0x4C 32 read-write n 0x280020 0xFFFFFFFF MASA_POINT Modular addition/subtraction A point in sp_ram 0 9 read-write MASB_POINT Modular addition/subtraction B point in sp_ram 16 9 read-write SW_CFG3 SW_CFG3 PKC Software Configuration 3 Register 0x50 32 read-write n 0x380030 0xFFFFFFFF MASC_POINT Modular addition/subtraction C point in sp_ram 16 9 read-write MASP_POINT Modular addition/subtraction P point in sp_ram 0 9 read-write SW_CFG4 SW_CFG4 PKC Software Configuration 4 Register 0x54 32 read-write n 0x480040 0xFFFFFFFF MIU_POINT Modular invertion U point in sp_ram 0 9 read-write MIV_POINT Modular invertion V point in sp_ram 16 9 read-write SW_CFG5 SW_CFG5 PKC Software Configuration 5 Register 0x58 32 read-write n 0x580050 0xFFFFFFFF MIX1_POINT Modular invertion X1 point in sp_ram 0 9 read-write MIX2_POINT Modular invertion X2 point in sp_ram 16 9 read-write SW_CFG6 SW_CFG6 PKC Software Configuration 6 Register 0x5C 32 read-write n 0x60 0xFFFFFFFF MIT_POINT Modular invertion TEMP point in sp_ram 0 9 read-write SW_CFG7 SW_CFG7 PKC Software Configuration 7 Register 0x60 32 read-write n 0x7 0xFFFFFFFF LEN Operator word length configuration, in software mode: 0x07: 256bits 0x08: 288bits - 0x3F: 2048bits In hardware mode fixed to 0x07 0 9 read-write SW_CFG8 SW_CFG8 PKC Software Configuration 8 Register 0x64 32 read-only n 0x0 0xFFFFFFFF MIK_OUT K out in modular invertion operation 0 13 read-only SW_CFG9 SW_CFG9 PKC Software Configuration 9 Register 0x68 32 read-write n 0xAABBCCDD 0xFFFFFFFF RDM_SEED Random dummy multiplication seed 0 32 read-write SW_CTRL SW_CTRL PKC Software Controller Register 0x40 32 read-write n 0x0 0xFFFFFFFF DM_EN Enable dummy multiplication 0x0: Disable 0x1: Enable 8 1 read-write MODE Only used in software mode. 0x0: Montgomery Multiplication 0x1: Mod Inversion 0x2: Mod Addition 0x3: Mod Subtraction 0x4: Mod Comparison 0x5: Mod Shift 0x6: Big Integer Multiplication 0x7: Bit Integer Addition 4 3 read-write RCG_EN Enable random clock gating 0x0: Disable 0x1: Enable 9 1 read-write START Only used in software mode. MCU write 0 to this bit and then write 1 to this bit to start PKC 0 1 read-write PWM0 Pulse Width Modulation PWM 0xA000C900 0x0 0x30 registers n AQ_CTRL AQ_CTRL Action Qualifler Control Regiser 0x24 32 read-write n 0x0 0xFFFFFFFF AQ_CTRL_A0 Action of event CNT_CMPA0 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle 0 2 read-write AQ_CTRL_A1 Action of event CNT_CMPA1 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle 2 2 read-write AQ_CTRL_B0 Action of event CNT_CMPB0 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle 4 2 read-write AQ_CTRL_B1 Action of event CNT_CMPB1 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle 6 2 read-write AQ_CTRL_C0 Action of event CNT_CMPC0 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle 8 2 read-write AQ_CTRL_C1 Action of event CNT_CMPC1 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle 10 2 read-write BREATH_PRD BREATH_PRD Breath Period Register 0x28 32 read-write n 0x0 0xFFFFFFFF BREATH_PRD Breath period register, i.e. the required time (number of clock) that the duty changes from 0% to 100% in breath mode. 0 32 read-write COMPA0 COMPA0 Compare A0 Register 0xC 32 read-write n 0x0 0xFFFFFFFF COMPA0 PWM_A duty control register0 0 32 read-write COMPA1 COMPA1 Compare A1 Register 0x10 32 read-write n 0x0 0xFFFFFFFF COMPA1 PWM_A duty control register1 0 32 read-write COMPB0 COMPB0 Compare B0 Register 0x14 32 read-write n 0x0 0xFFFFFFFF COMPB0 PWM_B duty control register0 0 32 read-write COMPB1 COMPB1 Compare B1 Register 0x18 32 read-write n 0x0 0xFFFFFFFF COMP_B1 PWM_B duty control register1 0 32 read-write COMPC0 COMPC0 Compare C0 Register 0x1C 32 read-write n 0x0 0xFFFFFFFF COMPC0 PWM_C duty control register0 0 32 read-write COMPC1 COMPC1 Compare C1 Register 0x20 32 read-write n 0x0 0xFFFFFFFF COMPC1 PWM_C duty control register1 0 32 read-write HOLD HOLD Compare B1 Register 0x2C 32 read-write n 0x0 0xFFFFFFFF HOLD Breath hold control register. The value should be the required number of clock in breath hold state. 0 24 read-write MODE MODE Mode Register 0x0 32 read-write n 0x0 0xFFFFFFFF BREATH_EN Breath mode enable. 0x0: flicker mode 0x1: breath mode 2 1 read-write EN Enable PWM. 0x0: Disable 0x1: Enable 0 1 read-write PAUSE PWM pause signal. 0x0: Ongoing 0x1: Pause 1 1 read-write PD_A_EN PWM_A positive-drive mode enable. 0x0: negative-drive mode 0x1: positive-drive mode 3 1 read-write PD_B_EN PWM_B positive-drive mode enable. 0x0: negative-drive mode 0x1: positive-drive mode 4 1 read-write PD_C_EN PWM_C positive-drive mode enable. 0x0: negative-drive mode 0x1: positive-drive mode 5 1 read-write PRD PRD Period Register 0x8 32 read-write n 0x0 0xFFFFFFFF PRD The period of PWM output, PRD=fCLK/fPWM 0 32 read-write UPDATE UPDATE Update Register 0x4 32 read-write n 0x0 0xFFFFFFFF UPDATE_SYNC_AE All synchronous update enable 0x0: Disable 0x1: Enable 1 1 read-write UPDATE_SYNC_AG All synchronous update ongoing 0x0: Not ongoing 0x1: Ongoing 0 1 read-only UPDATE_SYNC_SAQCTRL synchronous separate update enable of AQCTRL(action qualifler control) 0x0: Disable 0x1: Enable 18 1 read-write UPDATE_SYNC_SBRPRD synchronous separate update enable of BRPRD(breath period) 0x0: Disable 0x1: Enable 16 1 read-write UPDATE_SYNC_SCMPA0 synchronous separate update enable of CMPA0 0x0: Disable 0x1: Enable 9 1 read-write UPDATE_SYNC_SCMPA1 synchronous separate update enable of CMPA1 0x0: Disable 0x1: Enable 10 1 read-write UPDATE_SYNC_SCMPB0 synchronous separate update enable of CMPB0 0x0: Disable 0x1: Enable 11 1 read-write UPDATE_SYNC_SCMPB1 synchronous separate update enable of CMPB1 0x0: Disable 0x1: Enable 12 1 read-write UPDATE_SYNC_SCMPC0 synchronous separate update enable of CMPC0 0x0: Disable 0x1: Enable 13 1 read-write UPDATE_SYNC_SCMPC1 synchronous separate update enable of CMPC1 0x0: Disable 0x1: Enable 14 1 read-write UPDATE_SYNC_SHOLD synchronous separate update enable of HOLD(hold period) 0x0: Disable 0x1: Enable 17 1 read-write UPDATE_SYNC_SPAUSE synchronous separate update enable of PAUSE 0x0: Disable 0x1: Enable 15 1 read-write UPDATE_SYNC_SPRD synchronous separate update enable of PRD(period) 0x0: Disable 0x1: Enable 8 1 read-write PWM1 Pulse Width Modulation PWM 0xA000CC00 0x0 0x30 registers n AQ_CTRL AQ_CTRL Action Qualifler Control Regiser 0x24 32 read-write n 0x0 0xFFFFFFFF AQ_CTRL_A0 Action of event CNT_CMPA0 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle 0 2 read-write AQ_CTRL_A1 Action of event CNT_CMPA1 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle 2 2 read-write AQ_CTRL_B0 Action of event CNT_CMPB0 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle 4 2 read-write AQ_CTRL_B1 Action of event CNT_CMPB1 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle 6 2 read-write AQ_CTRL_C0 Action of event CNT_CMPC0 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle 8 2 read-write AQ_CTRL_C1 Action of event CNT_CMPC1 control register. 0x0: do nothing 0x1: clear 0x2: set 0x3:toogle 10 2 read-write BREATH_PRD BREATH_PRD Breath Period Register 0x28 32 read-write n 0x0 0xFFFFFFFF BREATH_PRD Breath period register, i.e. the required time (number of clock) that the duty changes from 0% to 100% in breath mode. 0 32 read-write COMPA0 COMPA0 Compare A0 Register 0xC 32 read-write n 0x0 0xFFFFFFFF COMPA0 PWM_A duty control register0 0 32 read-write COMPA1 COMPA1 Compare A1 Register 0x10 32 read-write n 0x0 0xFFFFFFFF COMPA1 PWM_A duty control register1 0 32 read-write COMPB0 COMPB0 Compare B0 Register 0x14 32 read-write n 0x0 0xFFFFFFFF COMPB0 PWM_B duty control register0 0 32 read-write COMPB1 COMPB1 Compare B1 Register 0x18 32 read-write n 0x0 0xFFFFFFFF COMP_B1 PWM_B duty control register1 0 32 read-write COMPC0 COMPC0 Compare C0 Register 0x1C 32 read-write n 0x0 0xFFFFFFFF COMPC0 PWM_C duty control register0 0 32 read-write COMPC1 COMPC1 Compare C1 Register 0x20 32 read-write n 0x0 0xFFFFFFFF COMPC1 PWM_C duty control register1 0 32 read-write HOLD HOLD Compare B1 Register 0x2C 32 read-write n 0x0 0xFFFFFFFF HOLD Breath hold control register. The value should be the required number of clock in breath hold state. 0 24 read-write MODE MODE Mode Register 0x0 32 read-write n 0x0 0xFFFFFFFF BREATH_EN Breath mode enable. 0x0: flicker mode 0x1: breath mode 2 1 read-write EN Enable PWM. 0x0: Disable 0x1: Enable 0 1 read-write PAUSE PWM pause signal. 0x0: Ongoing 0x1: Pause 1 1 read-write PD_A_EN PWM_A positive-drive mode enable. 0x0: negative-drive mode 0x1: positive-drive mode 3 1 read-write PD_B_EN PWM_B positive-drive mode enable. 0x0: negative-drive mode 0x1: positive-drive mode 4 1 read-write PD_C_EN PWM_C positive-drive mode enable. 0x0: negative-drive mode 0x1: positive-drive mode 5 1 read-write PRD PRD Period Register 0x8 32 read-write n 0x0 0xFFFFFFFF PRD The period of PWM output, PRD=fCLK/fPWM 0 32 read-write UPDATE UPDATE Update Register 0x4 32 read-write n 0x0 0xFFFFFFFF UPDATE_SYNC_AE All synchronous update enable 0x0: Disable 0x1: Enable 1 1 read-write UPDATE_SYNC_AG All synchronous update ongoing 0x0: Not ongoing 0x1: Ongoing 0 1 read-only UPDATE_SYNC_SAQCTRL synchronous separate update enable of AQCTRL(action qualifler control) 0x0: Disable 0x1: Enable 18 1 read-write UPDATE_SYNC_SBRPRD synchronous separate update enable of BRPRD(breath period) 0x0: Disable 0x1: Enable 16 1 read-write UPDATE_SYNC_SCMPA0 synchronous separate update enable of CMPA0 0x0: Disable 0x1: Enable 9 1 read-write UPDATE_SYNC_SCMPA1 synchronous separate update enable of CMPA1 0x0: Disable 0x1: Enable 10 1 read-write UPDATE_SYNC_SCMPB0 synchronous separate update enable of CMPB0 0x0: Disable 0x1: Enable 11 1 read-write UPDATE_SYNC_SCMPB1 synchronous separate update enable of CMPB1 0x0: Disable 0x1: Enable 12 1 read-write UPDATE_SYNC_SCMPC0 synchronous separate update enable of CMPC0 0x0: Disable 0x1: Enable 13 1 read-write UPDATE_SYNC_SCMPC1 synchronous separate update enable of CMPC1 0x0: Disable 0x1: Enable 14 1 read-write UPDATE_SYNC_SHOLD synchronous separate update enable of HOLD(hold period) 0x0: Disable 0x1: Enable 17 1 read-write UPDATE_SYNC_SPAUSE synchronous separate update enable of PAUSE 0x0: Disable 0x1: Enable 15 1 read-write UPDATE_SYNC_SPRD synchronous separate update enable of PRD(period) 0x0: Disable 0x1: Enable 8 1 read-write QSPI0 Serial Peripheral Interface QSPI 0xA000C200 0x0 0x64 registers n QSPI0 QSPI0 interrupts 11 QSPI1 QSPI1 interrupt 23 BAUD BAUD Baud Rate Register 0x14 32 read-write n 0x0 0xFFFFFFFF SSI_CLK_DIV SSI Clock Divider. The LSB for this field is always set to 0 and is unaffected by a write operation, which ensures an even value is held in this register. If the value is 0, the serial output clock (sclk_out) is disabled. The frequency of the sclk_out is derived from the following equation: Fsclk_out = Fssi_clk/SSI_CLK_DIV Note: When the SPI is configured as a slave, this register serves no purpose. 0 16 read-write CTRL0 CTRL0 Control Register 0 0x0 32 read-write n 0x1070000 0xFFFFFFFF CTRL_FRAME_SIZE Control Frame Size. Selects the length of the control word for the Microwire frame format. 0x0 (SIZE_01_BIT): 1-bit Control Word 0x1 (SIZE_02_BIT): 2-bit Control Word 0x2 (SIZE_03_BIT): 3-bit Control Word 0x3 (SIZE_04_BIT): 4-bit Control Word 0x4 (SIZE_05_BIT): 5-bit Control Word 0x5 (SIZE_06_BIT): 6-bit Control Word 0x6 (SIZE_07_BIT): 7-bit Control Word 0x7 (SIZE_08_BIT): 8-bit Control Word 0x8 (SIZE_09_BIT): 9-bit Control Word 0x9 (SIZE_10_BIT): 10-bit Control Word 0xa (SIZE_11_BIT): 11-bit Control Word 0xb (SIZE_12_BIT): 12-bit Control Word 0xc (SIZE_13_BIT): 13-bit Control Word 0xd (SIZE_14_BIT): 14-bit Control Word 0xe (SIZE_15_BIT): 15-bit Control Word 0xf (SIZE_16_BIT): 16-bit Control Word 12 4 read-write DATA_FRAME_SIZE Data Frame Size in 32-bit transfer size mode. Used to select the data frame size in 32-bit transfer mode. When the data frame size is programmed to be less than 32 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You are responsible for making sure that transmit data is right-justified before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data. Note: When SPI_FRAME_FORMAT is not set to 0x0. - DFS value should be multiple of 2 if SPI_FRAME_FORMAT = 0x01, - DFS value should be multiple of 4 if SPI_FRAME_FORMAT = 0x10. 0x3 (FRAME_04BITS): 4-bit serial data transfer 0x4 (FRAME_05BITS): 5-bit serial data transfer 0x5 (FRAME_06BITS): 6-bit serial data transfer 0x6 (FRAME_07BITS): 7-bit serial data transfer 0x7 (FRAME_08BITS): 8-bit serial data transfer 0x8 (FRAME_09BITS): 9-bit serial data transfer 0x9 (FRAME_10BITS): 10-bit serial data transfer 0xa (FRAME_11BITS): 11-bit serial data transfer 0xb (FRAME_12BITS): 12-bit serial data transfer 0xc (FRAME_13BITS): 13-bit serial data transfer 0xd (FRAME_14BITS): 14-bit serial data transfer 0xe (FRAME_15BITS): 15-bit serial data transfer 0xf (FRAME_16BITS): 16-bit serial data transfer 0x10 (FRAME_17BITS): 17-bit serial data transfer 0x11 (FRAME_18BITS): 18-bit serial data transfer 0x12 (FRAME_19BITS): 19-bit serial data transfer 0x13 (FRAME_20BITS): 20-bit serial data transfer 0x14 (FRAME_21BITS): 21-bit serial data transfer 0x15 (FRAME_22BITS): 22-bit serial data transfer 0x16 (FRAME_23BITS): 23-bit serial data transfer 0x17 (FRAME_24BITS): 24-bit serial data transfer 0x18 (FRAME_25BITS): 25-bit serial data transfer 0x19 (FRAME_26BITS): 26-bit serial data transfer 0x1a (FRAME_27BITS): 27-bit serial data transfer 0x1b (FRAME_28BITS): 28-bit serial data transfer 0x1c (FRAME_29BITS): 29-bit serial data transfer 0x1d (FRAME_30BITS): 30-bit serial data transfer 0x1e (FRAME_31BITS): 31-bit serial data transfer 0x1f (FRAME_32BITS): 32-bit serial data transfer 16 5 read-write FRAME_FORMAT Frame Format. Selects which serial protocol transfers the data. 0x0 (MOTOROLA_SPI): Motorolla SPI Frame Format 0x1 (TEXAS_SSP): Texas Instruments SSP Frame Format 0x2 (NS_MICROWIRE): National Microwire Frame Format 0x3 (RESERVED): Reserved value 4 2 read-write SERIAL_CLK_PHASE Serial Clock Phase. Valid when the frame format (FRAME_FORMAT) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SERIAL_CLK_PHASE = 0, data are captured on the first edge of the serial clock. When SERIAL_CLK_PHASE = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data are captured on the second edge of the serial clock. 0x0 (SERIAL_CLK_PHASE_MIDDLE): Serial clock toggles in middle of first data bit 0x1 (SERIAL_CLK_PHASE_START): Serial clock toggles at start of first data bit 6 1 read-write SERIAL_CLK_POL Serial Clock Polarity. Valid when the frame format (FRAME_FORMAT) is set to Motorola SPI. Used to select the polarity of the inactive serial clock, which is held inactive when the SPI master is not actively transferring data on the serial bus. 0x0 (SCLK_LOW): Inactive state of serial clock is low 0x1 (SCLK_HIGH): Inactive state of serial clock is high 7 1 read-write SHIFT_REG_LOOP Shift Register Loop. Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input. 0x0 (NORMAL_MODE): Normal mode operation 0x1 (TESTING_MODE): Test mode: TX and RX shift reg connected 11 1 read-write SPI_FRAME_FORMAT SPI Frame Format: Selects data frame format for Transmitting/Receiving the data Bits. 0x0 (STD_SPI_FRAME_FORMAT): Standard SPI Frame Format 0x1 (DUAL_SPI_FRAME_FORMAT): Dual SPI Frame Format 0x2 (QUAD_SPI_FRAME_FORMAT): Quad SPI Frame Format 0x3: Reserved 21 2 read-write S_ST_EN Slave Select Toggle Enable. When operating in SPI mode with clock phase (SERIAL_CLK_PHASE) set to 0, this register controls the behavior of the slave select line (CS) between data frames. If this register field is set to 1 the CS line will toggle between consecutive data frames, with the serial clock (sclk) being held to its default value while CS is high if this register field is set to 0 the CS will stay low and sclk will run continuously for the duration of the transfer. Note: When the SPI is configured as a slave, this register serves no purpose. 24 1 read-write XFE_MODE Transfer Mode. This transfer mode is only valid when the SPI is configured as master device. 0x0 - Transmit and Receive 0x1 - Transmit Only 0x2 - Receive Only 0x3 - EEPROM Read When SPI_FRF is not set to 2'b00. There are only two valid combinations: 0x1 - Write 0x2 - Read 0x0 (TX_AND_RX): Transmit and receive 0x1 (TX_ONLY): Transmit only mode or Write (SPI_FRAME_FORMAT != 0x0) 0x2 (RX_ONLY): Receive only mode or Read (SPI_FRAME_FORMAT!= 0x0) 0x3 (EEPROM_READ): EEPROM Read mode 8 2 read-write CTRL1 CTRL1 Control Register 1 0x4 32 read-write n 0x0 0xFFFFFFFF NUM_DATA_FRAME Number of Data Frames. When XFE_MODE = 0x2 or XFE_MODE = 0x3, this register field sets the number of data frames to be continuously received by the SPI. The SPI continues to receive serial data until the number of data frames received is equal to thisregister value plus 1, which enables you to receive up to 64KB of data in a continuous transfer. Note: When the SPI is configured as a slave, this register serves no purpose. 0 16 read-write DATA DATA Data Register 0x60 32 read-write n 0x0 0xFFFFFFFF DATA Data Register. When writing to this register, you must right-justify the data. Read data are automatically right-justified. 0 32 read-write DMA_CTRL DMA_CTRL DMA Control Register 0x4C 32 read-write n 0x0 0xFFFFFFFF RX_DMA_EN Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel 0x0 (DISABLE): Receive DMA disabled 0x1 (ENABLED): Receive DMA enabled 0 1 read-write TX_DMA_EN Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. 0x0 (DISABLE): Transmit DMA disabled 0x1 (ENABLED): Transmit DMA enabled 1 1 read-write DMA_RX_DL DMA_RX_DL DMA Receive Data Level Register 0x54 32 read-write n 0x0 0xFFFFFFFF DMA_RX_DL Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level =DMA_RX_DL+1 that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or above this field value + 1, and RX_DMA_EN=1. 0 3 read-write DMA_TX_DL DMA_TX_DL DMA Transmit Data Level Register 0x50 32 read-write n 0x0 0xFFFFFFFF DMA_TX_DL Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TX_DMA_EN = 1. 0 3 read-write INT_CLR INT_CLR Interrupt Clear Register 0x48 32 read-only n 0x0 0xFFFFFFFF INT_CLR Clear Interrupts. This register is set if any of the interrupts below are active. A read clears the txo_intr, rxu_intr, rxo_intr, and the mst_intr interrupts. Writing to this register has no effect. 0 1 read-only INT_MASK INT_MASK Interrupt Mask Register 0x2C 32 read-write n 0x3F 0xFFFFFFFF MULTI_M_CIM Multi-Master Contention Interrupt Mask. 0x0 (MASKED): Disable mst_intr interrupt 0x1 (UNMASKED): Enable mst_intr interrupt 5 1 read-write RX_FIFO_FIS Receive FIFO Full Interrupt Mask 0x0 (MASKED): Disable rxf_intr interrupt 0x1 (UNMASKED): Enable rxf_intr interrupt 4 1 read-write RX_FIFO_OIS Receive FIFO Overflow Interrupt Mask 0x0 (MASKED): Disable rxo_intr interrupt 0x1 (UNMASKED): Enable rxo_intr interrupt 3 1 read-write RX_FIFO_UIS Receive FIFO Underflow Interrupt Mask 0x0 (MASKED): Disable rxu_intr interrupt 0x1 (UNMASKED): Enable rxu_intr interrupt 2 1 read-write TX_FIFO_EIS Transmit FIFO Empty Interrupt Mask 0x0 (MASKED): Disable txe_intr interrupt 0x1 (UNMASKED): Enable txe_intr interrupt 0 1 read-write TX_FIFO_OIS Transmit FIFO Overflow Interrupt Mask 0x0 (MASKED): Disable txo_intr interrupt 0x1 (UNMASKED): Enable txo_intr interrupt 1 1 read-write INT_STAT INT_STAT Interrupt Status Register 0x30 32 read-only n 0x0 0xFFFFFFFF MULTI_M_CIS Multi-Master Contention Interrupt Status 0x0 (INACTIVE): mst_intr interrupt is not active after be enabled 0x1 (ACTIVE): mst_intr interrupt is full after be enabled 5 1 read-only RX_FIFO_FIS Receive FIFO Full Interrupt Status 0x0 (INACTIVE): rxf_intr interrupt is not active after be enabled 0x1 (ACTIVE): rxf_intr interrupt is full after be enabled 4 1 read-only RX_FIFO_OIS Receive FIFO Overflow Interrupt Status 0x0 (INACTIVE): rxo_intr interrupt is not active after be enabled 0x1 (ACTIVE): rxo_intr interrupt is active after be enabled 3 1 read-only RX_FIFO_UIS Receive FIFO Underflow Interrupt Status 0x0 (INACTIVE): rxu_intr interrupt is not active after be enabled 0x1 (ACTIVE): rxu_intr interrupt is active after be enabled 2 1 read-only TX_FIFO_EIS Transmit FIFO Empty Interrupt Status 0x0 (INACTIVE): txe_intr interrupt is not active after be enabled 0x1 (ACTIVE): txe_intr interrupt is active after be enabled 0 1 read-only TX_FIFO_OIS Transmit FIFO Overflow Interrupt Status 0x0 (INACTIVE): txo_intr interrupt is not active after be enabled 0x1 (ACTIVE): txo_intr interrupt is active after be enabled 1 1 read-only MULTI_M_IC MULTI_M_IC Multi-Master Interrupt Clear Register 0x44 32 read-only n 0x0 0xFFFFFFFF MULTI_M_IC Clear Multi-Master Contention Interrupt. This register reflects the status of the interrupt. A read from this register clears the mst_intr interrupt writing has no effect. 0 1 read-only MW_CTRL MW_CTRL Microwire Control Register 0xC 32 read-write n 0x0 0xFFFFFFFF MW_DIR_DW Microwire Control. Defines the direction of the data word when the Microwire serial protocol is used. 0x0 (RECEIVE): SPI receives data 0x1 (TRANSMIT): SPI transmits data 1 1 read-write MW_HSG Microwire Handshaking. Used to enable and disable the busy/ready handshaking interface for the Microwire protocol. When enabled, the SPI checks for a ready status from the target slave, after the transfer of the last data/control bit, before clearing the SSI_BUSY status in the DATA register. 0x0 (DISABLE): Handshaking interface is disabled 0x1 (ENABLED): Handshaking interface is enabled Note: When the SPI is configured as a slave, this register serves no purpose. 2 1 read-write MW_XFE_MODE Microwire Transfer Mode. Defines whether the Microwire transfer is sequential or non-sequential. When sequential mode is used, only one control word is needed to transmit or receive a block of data words. When non-sequential mode is used, there must be a control word for each data word that is transmitted or received. 0x0 (NON_SEQUENTIAL): Non-Sequential Microwire Transfer 0x1 (SEQUENTIAL): Sequential Microwire Transfer 0 1 read-write RAW_INT_STAT RAW_INT_STAT Raw Interrupt Status Register 0x34 32 read-only n 0x0 0xFFFFFFFF MULTI_M_CRIS Multi-Master Contention Raw Interrupt Status 0x0 (INACTIVE): mst_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): mst_intr interrupt is full prior to be enabled 5 1 read-only RX_FIFO_FRIS Receive FIFO Full Raw Interrupt Status 0x0 (INACTIVE): rxf_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): rxf_intr interrupt is active prior to be enabled 4 1 read-only RX_FIFO_ORIS Receive FIFO Overflow Raw Interrupt Status 0x1 (ACTIVE): rxo_intr interrupt is not active prior to be enabled 0x0 (INACTIVE): rxo_intr interrupt is active prior be enabled 3 1 read-only RX_FIFO_URIS Receive FIFO Underflow Raw Interrupt Status 0x0 (INACTIVE): rxu_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): rxu_intr interrupt is active prior to be enabled 2 1 read-only TX_FIFO_ERIS Transmit FIFO Empty Raw Interrupt Status 0x0 (INACTIVE): txe_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): txe_intr interrupt is active prior be enabled 0 1 read-only TX_FIFO_ORIS Transmit FIFO Overflow Raw Interrupt Status 0x0 (INACTIVE): txo_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): txo_intr interrupt is active prior be enabled 1 1 read-only RX_FIFO_LEVEL RX_FIFO_LEVEL Receive FIFO Level Register 0x24 32 read-only n 0x0 0xFFFFFFFF RX_FIFO_LEVEL Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. 0 4 read-only RX_FIFO_OIC RX_FIFO_OIC Receive FIFO Overflow Interrupt Clear Register 0x3C 32 read-only n 0x0 0xFFFFFFFF RX_FIFO_OIC Clear Receive FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the rxo_intr interrupt writing has no effect. 0 1 read-only RX_FIFO_TL RX_FIFO_TL Receive FIFO Threshold Level 0x1C 32 read-write n 0x0 0xFFFFFFFF RX_FIFO_THD Receive FIFO Threshold. Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256. This register is sized to the number of address bits needed to access the FIFO. If you attempt to set this value greater than the depth of the FIFO, this field is not written and retains its current value. When the number of receive FIFO entries is greater than or equal to this value + 1, the receive FIFO full interrupt is triggered. 0 3 read-write RX_FIFO_UIC RX_FIFO_UIC Receive FIFO Underflow Interrupt Clear Register 0x40 32 read-only n 0x0 0xFFFFFFFF RX_FIFO_UIC Clear Receive FIFO Underflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the rxu_intr interrupt writing has no effect. 0 1 read-only RX_SMP_DLY RX_SMP_DLY Receive Sample Delay Register 0xF0 32 read-write n 0x0 0xFFFFFFFF RX_SMP_DLY RX Sample Delay. This register is used to delay the sample of the rxd input port. Each value represents a single ssi_clk delay on the sample of rxd. The maximum value is 7. Note: When the SPI is configured as a slave, this register serves no purpose. 0 8 read-write SPI_CTRL SPI_CTRL SPI Control Register 0xF4 32 read-write n 0x200 0xFFFFFFFF ADDR_LEN Address Length. This bit defines Length of Address to be transmitted. Only after this much bits are programmed in to the FIFO the transfer can begin. 0x0 (ADDR_LEN_0): 0-bit Address Width 0x1 (ADDR_LEN_1): 4-bit Address Width 0x2 (ADDR_LEN_2): 8-bit Address Width 0x3 (ADDR_LEN_3): 12-bit Address Width 0x4 (ADDR_LEN_4): 16-bit Address Width 0x5 (ADDR_LEN_5): 20-bit Address Width 0x6 (ADDR_LEN_6): 24-bit Address Width 0x7 (ADDR_LEN_7): 28-bit Address Width 0x8 (ADDR_LEN_8): 32-bit Address Width 0x9 (ADDR_LEN_9): 36-bit Address Width 0xa (ADDR_LEN_10): 40-bit Address Width 0xb (ADDR_LEN_11): 44-bit Address Width 0xc (ADDR_LEN_12): 48-bit Address Width 0xd (ADDR_LEN_13): 52-bit Address Width 0xe (ADDR_LEN_14): 56-bit Address Width 0xf (ADDR_LEN_15): 60-bit Address Width 2 4 read-write INST_LEN 0x0 (INST_LEN_0): 0-bit (No Instruction) 0x1 (INST_LEN_1): 4-bit Instruction 0x2 (INST_LEN_2): 8-bit Instruction 0x3 (INST_LEN_3): 16-bit Instruction 8 2 read-write WAIT_CYCLES Wait cycles Number of wait cycles in Dual/Quad mode between control frames transmit and data reception. This value is specified as number of SPI clock cycles. 11 5 read-write XFE_FORMAT_AI Address and instruction transfer format. Selects whether QSPI will transmit instruction/address either in Standard SPI mode or the SPI mode selected in CTRL0.SPI_FRAME_FORMATfield. Value: 0x0 - Instruction and Address will be sent in Standard SPI Mode. 0x1 - Instruction will be sent in Standard SPI Mode and Address will be sent in the mode specified by CTRL0.SPI_FRAME_FORMAT. 0x2 - Both Instruction and Address will be sent in the mode specified by SPI_FRAME_FORMAT. 0x3 - Reserved. 0 2 read-write SSI_EN SSI_EN SSI Enable Register 0x8 32 read-write n 0x1 0xFFFFFFFF SSI_EN SSI Enable. Enables and disables all SPI operations. When disabled, all serial transfers are halted immediately. Transmit and receive FIFO buffers are cleared when the device is disabled. 0x0 (DISABLE): Disables Serial Transfer 0x1 (ENABLED): Enables Serial Transfer 0 1 read-write STAT STAT Status Register 0x28 32 read-only n 0x6 0xFFFFFFFF DATA_COLN_ERR Data Collision Error. This bit will be set if MISO input is asserted by other master, when the SPI master is in the middle of the transfer. This informs the processor that the last data transfer was halted before completion. This bit is cleared when read. 6 1 read-only RX_FIFO_FULL Receive FIFO Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0x0 (NOT_FULL): Receive FIFO is not full 0x1 (FULL): Receive FIFO is full 4 1 read-only RX_FIFO_NE Receive FIFO Not Empty. Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO. 0x0 (EMPTY): Receive FIFO is empty 0x1 (NOT_EMPTY): Receive FIFO is not empty 3 1 read-only SSI_BUSY SSI Busy Flag. When set, indicates that a serial transfer is in progress when cleared indicates that the SPI is idle or disabled. 0x0 (INACTIVE): SPI is idle or disabled 0x1 (ACTIVE): SPI is actively transferring data 0 1 read-only TX_ERR Transmission Error. Set if the transmit FIFO is empty when a transfer is started. Data from the previous transmission is resent on the txd line. This bit is cleared when read. 0x0 (NO_ERROR): No Error 0x1 (TX_ERROR): Transmission Error Note: When the SPI is configured as a master, this register serves no purpose. 5 1 read-only TX_FIFO_EMPTY Transmit FIFO Empty. When the transmit FIFO is completely empty, this bit is set. When the transmit FIFO contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0x0 (NOT_EMPTY): Transmit FIFO is not empty 0x1 (EMPTY): Transmit FIFO is empty 2 1 read-only TX_FIFO_NF Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0x0 (FULL): Transmit FIFO is full 0x1 (NOT_FULL): Transmit FIFO is not Full 1 1 read-only S_EN S_EN Slave Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF S_SEL_EN Slave Select Enable. Each bit in this register corresponds to a slave select line (CSn) from the SPI master. 0x0 (NOT_SELECTED): No slave selected 0x1 (SELECTED): Slave is selected Note: When the SPI is configured as a slave, this register serves no purpose. 0 2 read-write TX_FIFO_LEVEL TX_FIFO_LEVEL Transmit FIFO Level Register 0x20 32 read-only n 0x0 0xFFFFFFFF TX_FIFO_LEVEL Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. 0 4 read-only TX_FIFO_OIC TX_FIFO_OIC Transmit FIFO Overflow Interrupt Clear Register 0x38 32 read-only n 0x0 0xFFFFFFFF TX_FIFO_OIC Clear Transmit FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the txo_intr interrupt writing has no effect. 0 1 read-only TX_FIFO_TL TX_FIFO_TL Transmit FIFO Threshold Level Register 0x18 32 read-write n 0x0 0xFFFFFFFF TX_FIFO_THD Transmit FIFO Threshold. Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256 this register is sized to the number of address bits needed to access the FIFO. If you attempt to set this value greater than or equal to the depth of the FIFO, this field is not written and retains its current value.When the number of transmit FIFO entries is less than or equal to this value, the transmit FIFO empty interrupt is triggered. 0 3 read-write QSPI1 Serial Peripheral Interface QSPI 0xA000C800 0x0 0x64 registers n QSPI0 QSPI0 interrupts 11 QSPI1 QSPI1 interrupt 23 BAUD BAUD Baud Rate Register 0x14 32 read-write n 0x0 0xFFFFFFFF SSI_CLK_DIV SSI Clock Divider. The LSB for this field is always set to 0 and is unaffected by a write operation, which ensures an even value is held in this register. If the value is 0, the serial output clock (sclk_out) is disabled. The frequency of the sclk_out is derived from the following equation: Fsclk_out = Fssi_clk/SSI_CLK_DIV Note: When the SPI is configured as a slave, this register serves no purpose. 0 16 read-write CTRL0 CTRL0 Control Register 0 0x0 32 read-write n 0x1070000 0xFFFFFFFF CTRL_FRAME_SIZE Control Frame Size. Selects the length of the control word for the Microwire frame format. 0x0 (SIZE_01_BIT): 1-bit Control Word 0x1 (SIZE_02_BIT): 2-bit Control Word 0x2 (SIZE_03_BIT): 3-bit Control Word 0x3 (SIZE_04_BIT): 4-bit Control Word 0x4 (SIZE_05_BIT): 5-bit Control Word 0x5 (SIZE_06_BIT): 6-bit Control Word 0x6 (SIZE_07_BIT): 7-bit Control Word 0x7 (SIZE_08_BIT): 8-bit Control Word 0x8 (SIZE_09_BIT): 9-bit Control Word 0x9 (SIZE_10_BIT): 10-bit Control Word 0xa (SIZE_11_BIT): 11-bit Control Word 0xb (SIZE_12_BIT): 12-bit Control Word 0xc (SIZE_13_BIT): 13-bit Control Word 0xd (SIZE_14_BIT): 14-bit Control Word 0xe (SIZE_15_BIT): 15-bit Control Word 0xf (SIZE_16_BIT): 16-bit Control Word 12 4 read-write DATA_FRAME_SIZE Data Frame Size in 32-bit transfer size mode. Used to select the data frame size in 32-bit transfer mode. When the data frame size is programmed to be less than 32 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You are responsible for making sure that transmit data is right-justified before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data. Note: When SPI_FRAME_FORMAT is not set to 0x0. - DFS value should be multiple of 2 if SPI_FRAME_FORMAT = 0x01, - DFS value should be multiple of 4 if SPI_FRAME_FORMAT = 0x10. 0x3 (FRAME_04BITS): 4-bit serial data transfer 0x4 (FRAME_05BITS): 5-bit serial data transfer 0x5 (FRAME_06BITS): 6-bit serial data transfer 0x6 (FRAME_07BITS): 7-bit serial data transfer 0x7 (FRAME_08BITS): 8-bit serial data transfer 0x8 (FRAME_09BITS): 9-bit serial data transfer 0x9 (FRAME_10BITS): 10-bit serial data transfer 0xa (FRAME_11BITS): 11-bit serial data transfer 0xb (FRAME_12BITS): 12-bit serial data transfer 0xc (FRAME_13BITS): 13-bit serial data transfer 0xd (FRAME_14BITS): 14-bit serial data transfer 0xe (FRAME_15BITS): 15-bit serial data transfer 0xf (FRAME_16BITS): 16-bit serial data transfer 0x10 (FRAME_17BITS): 17-bit serial data transfer 0x11 (FRAME_18BITS): 18-bit serial data transfer 0x12 (FRAME_19BITS): 19-bit serial data transfer 0x13 (FRAME_20BITS): 20-bit serial data transfer 0x14 (FRAME_21BITS): 21-bit serial data transfer 0x15 (FRAME_22BITS): 22-bit serial data transfer 0x16 (FRAME_23BITS): 23-bit serial data transfer 0x17 (FRAME_24BITS): 24-bit serial data transfer 0x18 (FRAME_25BITS): 25-bit serial data transfer 0x19 (FRAME_26BITS): 26-bit serial data transfer 0x1a (FRAME_27BITS): 27-bit serial data transfer 0x1b (FRAME_28BITS): 28-bit serial data transfer 0x1c (FRAME_29BITS): 29-bit serial data transfer 0x1d (FRAME_30BITS): 30-bit serial data transfer 0x1e (FRAME_31BITS): 31-bit serial data transfer 0x1f (FRAME_32BITS): 32-bit serial data transfer 16 5 read-write FRAME_FORMAT Frame Format. Selects which serial protocol transfers the data. 0x0 (MOTOROLA_SPI): Motorolla SPI Frame Format 0x1 (TEXAS_SSP): Texas Instruments SSP Frame Format 0x2 (NS_MICROWIRE): National Microwire Frame Format 0x3 (RESERVED): Reserved value 4 2 read-write SERIAL_CLK_PHASE Serial Clock Phase. Valid when the frame format (FRAME_FORMAT) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SERIAL_CLK_PHASE = 0, data are captured on the first edge of the serial clock. When SERIAL_CLK_PHASE = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data are captured on the second edge of the serial clock. 0x0 (SERIAL_CLK_PHASE_MIDDLE): Serial clock toggles in middle of first data bit 0x1 (SERIAL_CLK_PHASE_START): Serial clock toggles at start of first data bit 6 1 read-write SERIAL_CLK_POL Serial Clock Polarity. Valid when the frame format (FRAME_FORMAT) is set to Motorola SPI. Used to select the polarity of the inactive serial clock, which is held inactive when the SPI master is not actively transferring data on the serial bus. 0x0 (SCLK_LOW): Inactive state of serial clock is low 0x1 (SCLK_HIGH): Inactive state of serial clock is high 7 1 read-write SHIFT_REG_LOOP Shift Register Loop. Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input. 0x0 (NORMAL_MODE): Normal mode operation 0x1 (TESTING_MODE): Test mode: TX and RX shift reg connected 11 1 read-write SPI_FRAME_FORMAT SPI Frame Format: Selects data frame format for Transmitting/Receiving the data Bits. 0x0 (STD_SPI_FRAME_FORMAT): Standard SPI Frame Format 0x1 (DUAL_SPI_FRAME_FORMAT): Dual SPI Frame Format 0x2 (QUAD_SPI_FRAME_FORMAT): Quad SPI Frame Format 0x3: Reserved 21 2 read-write S_ST_EN Slave Select Toggle Enable. When operating in SPI mode with clock phase (SERIAL_CLK_PHASE) set to 0, this register controls the behavior of the slave select line (CS) between data frames. If this register field is set to 1 the CS line will toggle between consecutive data frames, with the serial clock (sclk) being held to its default value while CS is high if this register field is set to 0 the CS will stay low and sclk will run continuously for the duration of the transfer. Note: When the SPI is configured as a slave, this register serves no purpose. 24 1 read-write XFE_MODE Transfer Mode. This transfer mode is only valid when the SPI is configured as master device. 0x0 - Transmit and Receive 0x1 - Transmit Only 0x2 - Receive Only 0x3 - EEPROM Read When SPI_FRF is not set to 2'b00. There are only two valid combinations: 0x1 - Write 0x2 - Read 0x0 (TX_AND_RX): Transmit and receive 0x1 (TX_ONLY): Transmit only mode or Write (SPI_FRAME_FORMAT != 0x0) 0x2 (RX_ONLY): Receive only mode or Read (SPI_FRAME_FORMAT!= 0x0) 0x3 (EEPROM_READ): EEPROM Read mode 8 2 read-write CTRL1 CTRL1 Control Register 1 0x4 32 read-write n 0x0 0xFFFFFFFF NUM_DATA_FRAME Number of Data Frames. When XFE_MODE = 0x2 or XFE_MODE = 0x3, this register field sets the number of data frames to be continuously received by the SPI. The SPI continues to receive serial data until the number of data frames received is equal to thisregister value plus 1, which enables you to receive up to 64KB of data in a continuous transfer. Note: When the SPI is configured as a slave, this register serves no purpose. 0 16 read-write DATA DATA Data Register 0x60 32 read-write n 0x0 0xFFFFFFFF DATA Data Register. When writing to this register, you must right-justify the data. Read data are automatically right-justified. 0 32 read-write DMA_CTRL DMA_CTRL DMA Control Register 0x4C 32 read-write n 0x0 0xFFFFFFFF RX_DMA_EN Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel 0x0 (DISABLE): Receive DMA disabled 0x1 (ENABLED): Receive DMA enabled 0 1 read-write TX_DMA_EN Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. 0x0 (DISABLE): Transmit DMA disabled 0x1 (ENABLED): Transmit DMA enabled 1 1 read-write DMA_RX_DL DMA_RX_DL DMA Receive Data Level Register 0x54 32 read-write n 0x0 0xFFFFFFFF DMA_RX_DL Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level =DMA_RX_DL+1 that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or above this field value + 1, and RX_DMA_EN=1. 0 3 read-write DMA_TX_DL DMA_TX_DL DMA Transmit Data Level Register 0x50 32 read-write n 0x0 0xFFFFFFFF DMA_TX_DL Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TX_DMA_EN = 1. 0 3 read-write INT_CLR INT_CLR Interrupt Clear Register 0x48 32 read-only n 0x0 0xFFFFFFFF INT_CLR Clear Interrupts. This register is set if any of the interrupts below are active. A read clears the txo_intr, rxu_intr, rxo_intr, and the mst_intr interrupts. Writing to this register has no effect. 0 1 read-only INT_MASK INT_MASK Interrupt Mask Register 0x2C 32 read-write n 0x3F 0xFFFFFFFF MULTI_M_CIM Multi-Master Contention Interrupt Mask. 0x0 (MASKED): Disable mst_intr interrupt 0x1 (UNMASKED): Enable mst_intr interrupt 5 1 read-write RX_FIFO_FIS Receive FIFO Full Interrupt Mask 0x0 (MASKED): Disable rxf_intr interrupt 0x1 (UNMASKED): Enable rxf_intr interrupt 4 1 read-write RX_FIFO_OIS Receive FIFO Overflow Interrupt Mask 0x0 (MASKED): Disable rxo_intr interrupt 0x1 (UNMASKED): Enable rxo_intr interrupt 3 1 read-write RX_FIFO_UIS Receive FIFO Underflow Interrupt Mask 0x0 (MASKED): Disable rxu_intr interrupt 0x1 (UNMASKED): Enable rxu_intr interrupt 2 1 read-write TX_FIFO_EIS Transmit FIFO Empty Interrupt Mask 0x0 (MASKED): Disable txe_intr interrupt 0x1 (UNMASKED): Enable txe_intr interrupt 0 1 read-write TX_FIFO_OIS Transmit FIFO Overflow Interrupt Mask 0x0 (MASKED): Disable txo_intr interrupt 0x1 (UNMASKED): Enable txo_intr interrupt 1 1 read-write INT_STAT INT_STAT Interrupt Status Register 0x30 32 read-only n 0x0 0xFFFFFFFF MULTI_M_CIS Multi-Master Contention Interrupt Status 0x0 (INACTIVE): mst_intr interrupt is not active after be enabled 0x1 (ACTIVE): mst_intr interrupt is full after be enabled 5 1 read-only RX_FIFO_FIS Receive FIFO Full Interrupt Status 0x0 (INACTIVE): rxf_intr interrupt is not active after be enabled 0x1 (ACTIVE): rxf_intr interrupt is full after be enabled 4 1 read-only RX_FIFO_OIS Receive FIFO Overflow Interrupt Status 0x0 (INACTIVE): rxo_intr interrupt is not active after be enabled 0x1 (ACTIVE): rxo_intr interrupt is active after be enabled 3 1 read-only RX_FIFO_UIS Receive FIFO Underflow Interrupt Status 0x0 (INACTIVE): rxu_intr interrupt is not active after be enabled 0x1 (ACTIVE): rxu_intr interrupt is active after be enabled 2 1 read-only TX_FIFO_EIS Transmit FIFO Empty Interrupt Status 0x0 (INACTIVE): txe_intr interrupt is not active after be enabled 0x1 (ACTIVE): txe_intr interrupt is active after be enabled 0 1 read-only TX_FIFO_OIS Transmit FIFO Overflow Interrupt Status 0x0 (INACTIVE): txo_intr interrupt is not active after be enabled 0x1 (ACTIVE): txo_intr interrupt is active after be enabled 1 1 read-only MULTI_M_IC MULTI_M_IC Multi-Master Interrupt Clear Register 0x44 32 read-only n 0x0 0xFFFFFFFF MULTI_M_IC Clear Multi-Master Contention Interrupt. This register reflects the status of the interrupt. A read from this register clears the mst_intr interrupt writing has no effect. 0 1 read-only MW_CTRL MW_CTRL Microwire Control Register 0xC 32 read-write n 0x0 0xFFFFFFFF MW_DIR_DW Microwire Control. Defines the direction of the data word when the Microwire serial protocol is used. 0x0 (RECEIVE): SPI receives data 0x1 (TRANSMIT): SPI transmits data 1 1 read-write MW_HSG Microwire Handshaking. Used to enable and disable the busy/ready handshaking interface for the Microwire protocol. When enabled, the SPI checks for a ready status from the target slave, after the transfer of the last data/control bit, before clearing the SSI_BUSY status in the DATA register. 0x0 (DISABLE): Handshaking interface is disabled 0x1 (ENABLED): Handshaking interface is enabled Note: When the SPI is configured as a slave, this register serves no purpose. 2 1 read-write MW_XFE_MODE Microwire Transfer Mode. Defines whether the Microwire transfer is sequential or non-sequential. When sequential mode is used, only one control word is needed to transmit or receive a block of data words. When non-sequential mode is used, there must be a control word for each data word that is transmitted or received. 0x0 (NON_SEQUENTIAL): Non-Sequential Microwire Transfer 0x1 (SEQUENTIAL): Sequential Microwire Transfer 0 1 read-write RAW_INT_STAT RAW_INT_STAT Raw Interrupt Status Register 0x34 32 read-only n 0x0 0xFFFFFFFF MULTI_M_CRIS Multi-Master Contention Raw Interrupt Status 0x0 (INACTIVE): mst_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): mst_intr interrupt is full prior to be enabled 5 1 read-only RX_FIFO_FRIS Receive FIFO Full Raw Interrupt Status 0x0 (INACTIVE): rxf_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): rxf_intr interrupt is active prior to be enabled 4 1 read-only RX_FIFO_ORIS Receive FIFO Overflow Raw Interrupt Status 0x1 (ACTIVE): rxo_intr interrupt is not active prior to be enabled 0x0 (INACTIVE): rxo_intr interrupt is active prior be enabled 3 1 read-only RX_FIFO_URIS Receive FIFO Underflow Raw Interrupt Status 0x0 (INACTIVE): rxu_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): rxu_intr interrupt is active prior to be enabled 2 1 read-only TX_FIFO_ERIS Transmit FIFO Empty Raw Interrupt Status 0x0 (INACTIVE): txe_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): txe_intr interrupt is active prior be enabled 0 1 read-only TX_FIFO_ORIS Transmit FIFO Overflow Raw Interrupt Status 0x0 (INACTIVE): txo_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): txo_intr interrupt is active prior be enabled 1 1 read-only RX_FIFO_LEVEL RX_FIFO_LEVEL Receive FIFO Level Register 0x24 32 read-only n 0x0 0xFFFFFFFF RX_FIFO_LEVEL Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. 0 4 read-only RX_FIFO_OIC RX_FIFO_OIC Receive FIFO Overflow Interrupt Clear Register 0x3C 32 read-only n 0x0 0xFFFFFFFF RX_FIFO_OIC Clear Receive FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the rxo_intr interrupt writing has no effect. 0 1 read-only RX_FIFO_TL RX_FIFO_TL Receive FIFO Threshold Level 0x1C 32 read-write n 0x0 0xFFFFFFFF RX_FIFO_THD Receive FIFO Threshold. Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256. This register is sized to the number of address bits needed to access the FIFO. If you attempt to set this value greater than the depth of the FIFO, this field is not written and retains its current value. When the number of receive FIFO entries is greater than or equal to this value + 1, the receive FIFO full interrupt is triggered. 0 3 read-write RX_FIFO_UIC RX_FIFO_UIC Receive FIFO Underflow Interrupt Clear Register 0x40 32 read-only n 0x0 0xFFFFFFFF RX_FIFO_UIC Clear Receive FIFO Underflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the rxu_intr interrupt writing has no effect. 0 1 read-only RX_SMP_DLY RX_SMP_DLY Receive Sample Delay Register 0xF0 32 read-write n 0x0 0xFFFFFFFF RX_SMP_DLY RX Sample Delay. This register is used to delay the sample of the rxd input port. Each value represents a single ssi_clk delay on the sample of rxd. The maximum value is 7. Note: When the SPI is configured as a slave, this register serves no purpose. 0 8 read-write SPI_CTRL SPI_CTRL SPI Control Register 0xF4 32 read-write n 0x200 0xFFFFFFFF ADDR_LEN Address Length. This bit defines Length of Address to be transmitted. Only after this much bits are programmed in to the FIFO the transfer can begin. 0x0 (ADDR_LEN_0): 0-bit Address Width 0x1 (ADDR_LEN_1): 4-bit Address Width 0x2 (ADDR_LEN_2): 8-bit Address Width 0x3 (ADDR_LEN_3): 12-bit Address Width 0x4 (ADDR_LEN_4): 16-bit Address Width 0x5 (ADDR_LEN_5): 20-bit Address Width 0x6 (ADDR_LEN_6): 24-bit Address Width 0x7 (ADDR_LEN_7): 28-bit Address Width 0x8 (ADDR_LEN_8): 32-bit Address Width 0x9 (ADDR_LEN_9): 36-bit Address Width 0xa (ADDR_LEN_10): 40-bit Address Width 0xb (ADDR_LEN_11): 44-bit Address Width 0xc (ADDR_LEN_12): 48-bit Address Width 0xd (ADDR_LEN_13): 52-bit Address Width 0xe (ADDR_LEN_14): 56-bit Address Width 0xf (ADDR_LEN_15): 60-bit Address Width 2 4 read-write INST_LEN 0x0 (INST_LEN_0): 0-bit (No Instruction) 0x1 (INST_LEN_1): 4-bit Instruction 0x2 (INST_LEN_2): 8-bit Instruction 0x3 (INST_LEN_3): 16-bit Instruction 8 2 read-write WAIT_CYCLES Wait cycles Number of wait cycles in Dual/Quad mode between control frames transmit and data reception. This value is specified as number of SPI clock cycles. 11 5 read-write XFE_FORMAT_AI Address and instruction transfer format. Selects whether QSPI will transmit instruction/address either in Standard SPI mode or the SPI mode selected in CTRL0.SPI_FRAME_FORMATfield. Value: 0x0 - Instruction and Address will be sent in Standard SPI Mode. 0x1 - Instruction will be sent in Standard SPI Mode and Address will be sent in the mode specified by CTRL0.SPI_FRAME_FORMAT. 0x2 - Both Instruction and Address will be sent in the mode specified by SPI_FRAME_FORMAT. 0x3 - Reserved. 0 2 read-write SSI_EN SSI_EN SSI Enable Register 0x8 32 read-write n 0x1 0xFFFFFFFF SSI_EN SSI Enable. Enables and disables all SPI operations. When disabled, all serial transfers are halted immediately. Transmit and receive FIFO buffers are cleared when the device is disabled. 0x0 (DISABLE): Disables Serial Transfer 0x1 (ENABLED): Enables Serial Transfer 0 1 read-write STAT STAT Status Register 0x28 32 read-only n 0x6 0xFFFFFFFF DATA_COLN_ERR Data Collision Error. This bit will be set if MISO input is asserted by other master, when the SPI master is in the middle of the transfer. This informs the processor that the last data transfer was halted before completion. This bit is cleared when read. 6 1 read-only RX_FIFO_FULL Receive FIFO Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0x0 (NOT_FULL): Receive FIFO is not full 0x1 (FULL): Receive FIFO is full 4 1 read-only RX_FIFO_NE Receive FIFO Not Empty. Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO. 0x0 (EMPTY): Receive FIFO is empty 0x1 (NOT_EMPTY): Receive FIFO is not empty 3 1 read-only SSI_BUSY SSI Busy Flag. When set, indicates that a serial transfer is in progress when cleared indicates that the SPI is idle or disabled. 0x0 (INACTIVE): SPI is idle or disabled 0x1 (ACTIVE): SPI is actively transferring data 0 1 read-only TX_ERR Transmission Error. Set if the transmit FIFO is empty when a transfer is started. Data from the previous transmission is resent on the txd line. This bit is cleared when read. 0x0 (NO_ERROR): No Error 0x1 (TX_ERROR): Transmission Error Note: When the SPI is configured as a master, this register serves no purpose. 5 1 read-only TX_FIFO_EMPTY Transmit FIFO Empty. When the transmit FIFO is completely empty, this bit is set. When the transmit FIFO contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0x0 (NOT_EMPTY): Transmit FIFO is not empty 0x1 (EMPTY): Transmit FIFO is empty 2 1 read-only TX_FIFO_NF Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0x0 (FULL): Transmit FIFO is full 0x1 (NOT_FULL): Transmit FIFO is not Full 1 1 read-only S_EN S_EN Slave Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF S_SEL_EN Slave Select Enable. Each bit in this register corresponds to a slave select line (CSn) from the SPI master. 0x0 (NOT_SELECTED): No slave selected 0x1 (SELECTED): Slave is selected Note: When the SPI is configured as a slave, this register serves no purpose. 0 2 read-write TX_FIFO_LEVEL TX_FIFO_LEVEL Transmit FIFO Level Register 0x20 32 read-only n 0x0 0xFFFFFFFF TX_FIFO_LEVEL Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. 0 4 read-only TX_FIFO_OIC TX_FIFO_OIC Transmit FIFO Overflow Interrupt Clear Register 0x38 32 read-only n 0x0 0xFFFFFFFF TX_FIFO_OIC Clear Transmit FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the txo_intr interrupt writing has no effect. 0 1 read-only TX_FIFO_TL TX_FIFO_TL Transmit FIFO Threshold Level Register 0x18 32 read-write n 0x0 0xFFFFFFFF TX_FIFO_THD Transmit FIFO Threshold. Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256 this register is sized to the number of address bits needed to access the FIFO. If you attempt to set this value greater than or equal to the depth of the FIFO, this field is not written and retains its current value.When the number of transmit FIFO entries is less than or equal to this value, the transmit FIFO empty interrupt is triggered. 0 3 read-write RNG True Random Number Generator RNG 0xA0017800 0x0 0x28 registers n RNG RNG interrupt 19 CFG CFG TRNG Configuration Register 0x14 32 read-write n 0xB246 0xFFFFFFFF FRO_EN Ring oscillator TRNG enabled signal. 0x0: Disabled 0x1: Enabled 15 1 read-write HW_INT_EN TRNG hardware interrupt enable. 13 1 read-write LFSR_MODE_CFG LFSR configuration mode- 0x0: 59 bit LFSR 0x1: 128 bit LFSR 9 1 read-write LFSR_SEED_CFG LFSR seed configuration mode, select source of LFSR seed. 0x0: LFSR seed is from the switching current s0 0x1: LFSR seed is from the switching current s1 0x2: LFSR seed is from the switching current s2 0x3: LFSR seed is from the switching current s3 0x4: LFSR seed is from the oscillator s0 0x5: LFSR seed is from the Low Frequency Sampling s0 0x6: LFSR seed is configured by users 0x7: Random numbers do not use LFSR and completely use true random mode Value is limited to 0x4 or 0x6 in GR551x. 10 3 read-write LFSR_XOR_SEL In Output mode 8, select TRNG with LFSR XOR 0x4: LFSR ⊕ Ring Oscillator s0 ( the ⊕ means XOR.) Value is limited to 0x4 in GR551x. 4 3 read-write LFS_EN Low frequency sampling TRNG enabled signal. 0x0: Disabled 0x1: Enabled Reserved in GR551x. 14 1 read-write OUT_MODE Select TRNG Output mode. 0x4: Digital TRNG direct output, ring oscillator s0 0x6: LFSR and TRNG cyclic sampling and parity generation 0x7: LFSR and TRNG cyclic sampling 0x8: LFSR ⊕ TRNG 0x9: LFSR direct output Value is limited to 0x4, 0x6, 0x7, 0x8 or 0x9 in GR551x. 0 4 read-write P_MODE_CFG TRNG post-process configuration. 0x0: No post process 0x1: bit skipping 0x2: bit counting 0x3: Von-Neumann 7 2 read-write CTRL CTRL TRNG Controller Register 0x0 32 read-write n 0x0 0xFFFFFFFF RUN TRNG work enabled signal, valid at HIGH 0x0: disable RNG module 0x1: TRNG starts working to execute a operation of reading random number 0 1 read-write DATA DATA TRNG Data Register 0x8 32 read-only n 0x0 0xFFFFFFFF DATA TRNG data This register is automatically cleared by hardware after read 0 32 read-only FRO_CFG FRO_CFG TRNG FRO Configuration Register 0x1C 32 read-write n 0xFFFF 0xFFFFFFFF CHAIN_EN Enable signal of each Chain in ring oscillator module It is valid when FROEN is HIGH. 0 8 read-write TEST_IN Test input signal of each Chain for FRO The default value is 1. 8 8 read-write LONG_RUN_CFG LONG_RUN_CFG TRNG Long Run Configuration Register 0x24 32 read-write n 0x35 0xFFFFFFFF LONG_RUN_THD Test input signal of each Chain for FRO The default value is 1. 1 5 read-write THD_LR_TEST Threshold configuration of RNG long run test. The run which is greater or equal to this value will be detected. Default value is 26 and the maximum value is 31. 0 1 read-write LONG_RUN_STAT LONG_RUN_STAT TRNG Long Run Status Register 0x10 32 read-only n 0x0 0xFFFFFFFF LONG_RUN_COUNT Counts of TRNG long run test. This value is incremented by 1 for every long run detected by TRNG. After TRNG being disabled or reset, the register is cleared. 1 8 read-only LONG_RUN_FLAG Flag of TRNG long run test 0x0: Long run never occurred. 0x1: Long run was occurred in random number sequence After TRNG being disabled or reset, this register is cleared 0 1 read-only SRC_CFG SRC_CFG TRNG Source Configuration Register 0x18 32 read-write n 0x7864 0xFFFFFFFF FRO_CHAIN_SEL Selection of Chain4- Chain7 for FRO- 0x0: select long ring 0x1: select short ring 11 4 read-write WAIT_TIME The waiting time that TRNG input reaches stable. Default value is 100 time cycles. 0 8 read-write STAT STAT TRNG Status Register 0x4 32 read-write n 0x0 0xFFFFFFFF READY TRNG status flag bit, queried by CPU 0x0: TRNG output data is not valid. 0x1: TRNG output data is valid. This register is automatically cleared by hardware after READY is set HIGH. This register is automatically cleared by hardware after read DATA 0 1 read-write USER_SEED USER_SEED TRNG User Seed Register 0x20 32 write-only n 0x0 0xFFFFFFFF USER_SEED RNG seed configured by user. Write four times to user_seed[58:0] to configure a 59-bit random number. 0 16 write-only SADC Sense Analog-to-Digital Converter SADC 0xA000E000 0x0 0x14 registers n CFG CFG Sense ADC Configuration Register 0x8 32 read-write n 0x708070A 0xFFFFFFFF BIAS_REF_CTRL Buffered internal reference 0x0: 0.5V 0x1: 0.6V 0x2: 0.7V 0x3: 0.8V - 0xF: 2.0V Note: For any specific reference value (Vref), the maximum ADC input is supposed to be 2xVref. 0 4 read-write CH_N Used to define input for channel N 0x0: MSIO0 as input 0x1: MSIO1 as input 0x2: MSIO2 as input 0x3: MSIO3 as input 0x4: MSIO4 as input 0x5: Temperature sensor as input 0x6: Battery sensor as input 16 3 read-write CH_P Used to define input for channel P 0x0: MSIO0 as input 0x1: MSIO1 as input 0x2: MSIO2 as input 0x3: MSIO3 as input 0x4: MSIO4 as input 0x5: Temperature sensor as input 0x6: Battery sensor as input 19 3 read-write CODE_IN Used to define dynamic range of ADC. Default set to <0x7>, for higher input signal frequencies close to nyquist rate use <0x1> 8 3 read-write EN Enable ADC 0x0: Disable ADC 0x1: Enable ADC 30 1 read-write EN_CAL Used to swap inputs of comparator for offset calibration. 0x0: Disable 0x1: Enable 12 1 read-write EN_TMP Enable temperature sensor 0x0: Disable 0x1: Enable 15 1 read-write EN_VBAT Enable battery sensor 0x0: Disable 0x1: Enable 14 1 read-write MODE Used to define opertation either single ended or differential. 0x0: Diff 0x1: Single 13 1 read-write REF_HP_MODE Used to define current in the reference circuit :Default-<0x0> at 100KS/s and <0x7> at 1MS/s 24 3 read-write REF_SEL Reference Voltage Select 0x0: Buffered internal reference 0x1: Reserved 0x2: Reserved 0x3: Using MSIO0 as reference 0x4: Using MSIO1 as a reference 0x5: Using MSIO2 as a reference 0x6: Using MSIO3 as a reference 0x7: Reserved Note: Because the maximum input for any MSIO is supposed to be VBATT. So in this case, there is no benefit from using an external input higher than VBATT/2. 27 3 read-write RST Reset ADC 0x0: None 0x1: Reset 31 1 read-write CLK CLK Sense ADC Clock Register 0x40 32 read-write n 0x0 0xFFFFFFFF CLK_EN Enable ADC clock 0x0: Disable 0x1: Enable 31 1 read-write CLK_SEL ADC clock select 0x0: 16 MHz 0x1: 8 MHz 0x2: 4 MHz 0x3: 2 MHz 0x4: 1.6 MHz 0x5: 1 MHz 0x6: 1.6 MHz 0x7: 1 MHz 28 3 read-write FIFO_RD FIFO_RD Sense ADC Read FIFO Register 0x1B00 32 read-only n 0x0 0xFFFFFFFF DATA When the register is read, data in the FIFO buffer is accessed. 0 32 read-only FIFO_STAT FIFO_STAT Sense ADC Status Register 0x1C04 32 read-only n 0x0 0xFFFFFFFF COUNT Sense ADC FIFO Count, number of 32 bits words in the FIFO. Maximum value is 0x40 or decimal 64 0 7 read-only VAL Identify whether FIFO is empty 0x0: FIFO is empty 0x1: FIFO is not empty 8 1 read-only FIFO_THD FIFO_THD Sense ADC FIFO Threshold Register 0x1C00 32 read-write n 0x0 0xFFFFFFFF THD This is used to set the threshold at which the DMA request is made to the hardware handshake mechanism. 0 6 read-write SPIM Serial Peripheral Interface SPI 0xA000C000 0x0 0x5C registers n SPI_M SPI_M Interrupt 4 SPI_S SPI_S Interrupt 5 BAUD BAUD Baud Rate Register 0x14 32 read-write n 0x0 0xFFFFFFFF SSI_CLK_DIV SSI Clock Divider. The LSB for this field is always set to 0 and is unaffected by a write operation, which ensures an even value is held in this register. If the value is 0, the serial output clock (sclk_out) is disabled. The frequency of the sclk_out is derived from the following equation: Fsclk_out = Fssi_clk/SSI_CLK_DIV Note: When the SPI is configured as a slave, this register serves no purpose. 0 16 read-write CTRL0 CTRL0 SPI Control Register 0 0x0 32 read-write n 0x1070000 0xFFFFFFFF CTRL_FRAME_SIZE Control Frame Size. Selects the length of the control word for the Microwire frame format. 0x0 (SIZE_01_BIT): 1-bit Control Word 0x1 (SIZE_02_BIT): 2-bit Control Word 0x2 (SIZE_03_BIT): 3-bit Control Word 0x3 (SIZE_04_BIT): 4-bit Control Word 0x4 (SIZE_05_BIT): 5-bit Control Word 0x5 (SIZE_06_BIT): 6-bit Control Word 0x6 (SIZE_07_BIT): 7-bit Control Word 0x7 (SIZE_08_BIT): 8-bit Control Word 0x8 (SIZE_09_BIT): 9-bit Control Word 0x9 (SIZE_10_BIT): 10-bit Control Word 0xa (SIZE_11_BIT): 11-bit Control Word 0xb (SIZE_12_BIT): 12-bit Control Word 0xc (SIZE_13_BIT): 13-bit Control Word 0xd (SIZE_14_BIT): 14-bit Control Word 0xe (SIZE_15_BIT): 15-bit Control Word 0xf (SIZE_16_BIT): 16-bit Control Word 12 4 read-write DATA_FRAME_SIZE Data Frame Size in 32-bit transfer size mode. Used to select the data frame size in 32-bit transfer mode. When the data frame size is programmed to be less than 32 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You are responsible for making sure that transmit data is right-justified before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data. 0x3 (FRAME_04BITS): 4-bit serial data transfer 0x4 (FRAME_05BITS): 5-bit serial data transfer 0x5 (FRAME_06BITS): 6-bit serial data transfer 0x6 (FRAME_07BITS): 7-bit serial data transfer 0x7 (FRAME_08BITS): 8-bit serial data transfer 0x8 (FRAME_09BITS): 9-bit serial data transfer 0x9 (FRAME_10BITS): 10-bit serial data transfer 0xa (FRAME_11BITS): 11-bit serial data transfer 0xb (FRAME_12BITS): 12-bit serial data transfer 0xc (FRAME_13BITS): 13-bit serial data transfer 0xd (FRAME_14BITS): 14-bit serial data transfer 0xe (FRAME_15BITS): 15-bit serial data transfer 0xf (FRAME_16BITS): 16-bit serial data transfer 0x10 (FRAME_17BITS): 17-bit serial data transfer 0x11 (FRAME_18BITS): 18-bit serial data transfer 0x12 (FRAME_19BITS): 19-bit serial data transfer 0x13 (FRAME_20BITS): 20-bit serial data transfer 0x14 (FRAME_21BITS): 21-bit serial data transfer 0x15 (FRAME_22BITS): 22-bit serial data transfer 0x16 (FRAME_23BITS): 23-bit serial data transfer 0x17 (FRAME_24BITS): 24-bit serial data transfer 0x18 (FRAME_25BITS): 25-bit serial data transfer 0x19 (FRAME_26BITS): 26-bit serial data transfer 0x1a (FRAME_27BITS): 27-bit serial data transfer 0x1b (FRAME_28BITS): 28-bit serial data transfer 0x1c (FRAME_29BITS): 29-bit serial data transfer 0x1d (FRAME_30BITS): 30-bit serial data transfer 0x1e (FRAME_31BITS): 31-bit serial data transfer 0x1f (FRAME_32BITS): 32-bit serial data transfer 16 5 read-write FRAME_FORMAT Frame Format. Selects which serial protocol transfers the data. 0x0 (MOTOROLA_SPI): Motorolla SPI Frame Format 0x1 (TEXAS_SSP): Texas Instruments SSP Frame Format 0x2 (NS_MICROWIRE): National Microwire Frame Format 0x3 (RESERVED): Reserved value 4 2 read-write SERIAL_CLK_PHASE Serial Clock Phase. Valid when the frame format (FRAME_FORMAT) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SERIAL_CLK_PHASE = 0, data are captured on the first edge of the serial clock. When SERIAL_CLK_PHASE = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data are captured on the second edge of the serial clock. 0x0 (SERIAL_CLK_PHASE_MIDDLE): Serial clock toggles in middle of first data bit 0x1 (SERIAL_CLK_PHASE_START): Serial clock toggles at start of first data bit 6 1 read-write SERIAL_CLK_POL Serial Clock Polarity. Valid when the frame format (FRAME_FORMAT) is set to Motorola SPI. Used to select the polarity of the inactive serial clock, which is held inactive when the SPI master is not actively transferring data on the serial bus. 0x0 (SCLK_LOW): Inactive state of serial clock is low 0x1 (SCLK_HIGH): Inactive state of serial clock is high 7 1 read-write SHIFT_REG_LOOP Shift Register Loop. Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input. 0x0 (NORMAL_MODE): Normal mode operation 0x1 (TESTING_MODE): Test mode: TX and RX shift reg connected 11 1 read-write S_OUT_EN Slave Output Enable. Relevant only when the SPI is configured as a serial-slave device. When configured as a serial master, this bit field has no functionality. 0x0 (ENABLED): Slave Output is enabled 0x1 (DISABLED): Slave Output is disabled Note: When the SPI is configured as a master, this register serves no purpose. 10 1 read-write S_ST_EN Slave Select Toggle Enable. When operating in SPI mode with clock phase (SERIAL_CLK_PHASE) set to 0, this register controls the behavior of the slave select line (CS) between data frames. If this register field is set to 1 the CS line will toggle between consecutive data frames, with the serial clock (sclk) being held to its default value while CS is high if this register field is set to 0 the CS will stay low and sclk will run continuously for the duration of the transfer. Note: When the SPI is configured as a slave, this register serves no purpose 24 1 read-write XFE_MODE Transfer Mode. This transfer mode is only valid when the SPI is configured as master device. 0x0 - Transmit and Receive 0x1 - Transmit Only 0x2 - Receive Only 0x3 - EEPROM Read 0x0 (TX_AND_RX): Transmit and receive 0x1 (TX_ONLY): Transmit only mode 0x2 (RX_ONLY): Receive only mode 0x3 (EEPROM_READ): EEPROM Read mode 8 2 read-write CTRL1 CTRL1 SPI Control Register 1 0x4 32 read-write n 0x0 0xFFFFFFFF NUM_DATA_FRAME Number of Data Frames. When XFE_MODE = 10 or XFE_MODE = 11, this register field sets thenumber of data frames to be continuously received by the SPI. The SPI continues to receive serialdata until the number of data frames received is equal to thisregister value plus 1, which enables you to receive up to 64KB of data in a continuous transfer. Note: When the SPI is configured as a slave, this register serves no purpose. 0 16 read-write DATA DATA Data Register 0x60 32 read-write n 0x0 0xFFFFFFFF DATA Data Register. When writing to this register, you must right-justify the data. Read data are automatically right-justified. 0 32 read-write DMA_CTRL DMA_CTRL DMA Control Register 0x4C 32 read-write n 0x0 0xFFFFFFFF RX_DMA_EN Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel 0x0 (DISABLE): Receive DMA disabled 0x1 (ENABLED): Receive DMA enabled 0 1 read-write TX_DMA_EN Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. 0x0 (DISABLE): Transmit DMA disabled 0x1 (ENABLED): Transmit DMA enabled 1 1 read-write DMA_RX_DL DMA_RX_DL DMA Receive Data Level Register 0x54 32 read-write n 0x0 0xFFFFFFFF DMA_RX_DL Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMA_RX_DL+1 that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or above this field value + 1, and RX_DMA_EN=1. 0 3 read-write DMA_TX_DL DMA_TX_DL DMA Transmit Data Level Register 0x50 32 read-write n 0x0 0xFFFFFFFF DMA_TX_DL Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TX_DMA_EN = 1. 0 3 read-write INT_CLR INT_CLR Interrupt Clear Register 0x48 32 read-only n 0x0 0xFFFFFFFF INT_CLR Clear Interrupts. This register is set if any of the interrupts below are active. A read clears the txo_intr, rxu_intr, rxo_intr, and the mst_intr interrupts. Writing to this register has no effect. 0 1 read-only INT_MASK INT_MASK Interrupt Mask Register 0x2C 32 read-write n 0x3F 0xFFFFFFFF MULTI_M_CIM Multi-Master Contention Interrupt Mask. 0x0 (MASKED): Disable mst_intr interrupt 0x1 (UNMASKED): Enable mst_intr interrupt Note: When the SPI is configured as a slave, this register serves no purpose. 5 1 read-write RX_FIFO_FIM Receive FIFO Full Interrupt Mask 0x0 (MASKED): Disable rxf_intr interrupt 0x1 (UNMASKED): Enable rxf_intr interrupt 4 1 read-write RX_FIFO_OIM Receive FIFO Overflow Interrupt Mask 0x0 (MASKED): Disable rxo_intr interrupt 0x1 (UNMASKED): Enable rxo_intr interrupt 3 1 read-write RX_FIFO_UIM Receive FIFO Underflow Interrupt Mask 0x0 (MASKED): Disable rxu_intr interrupt 0x1 (UNMASKED): Enable rxu_intr interrupt 2 1 read-write TX_FIFO_EIM Transmit FIFO Empty Interrupt Mask 0x0 (MASKED): Disable txe_intr interrupt 0x1 (UNMASKED): Enable txe_intr interrupt 0 1 read-write TX_FIFO_OIM Transmit FIFO Overflow Interrupt Mask 0x0 (MASKED): Disable txo_intr interrupt 0x1 (UNMASKED): Enable txo_intr interrupt 1 1 read-write INT_STAT INT_STAT Interrupt Status Register 0x30 32 read-only n 0x0 0xFFFFFFFF MULTI_M_CIS Multi-Master Contention Interrupt Status 0x0 (INACTIVE): mst_intr interrupt is not active after be enabled 0x1 (ACTIVE): mst_intr interrupt is full after be enabled 5 1 read-only RX_FIFO_FIS Receive FIFO Full Interrupt Status 0x0 (INACTIVE): rxf_intr interrupt is not active after be enabled 0x1 (ACTIVE): rxf_intr interrupt is full after be enabled 4 1 read-only RX_FIFO_OIS Receive FIFO Overflow Interrupt Status 0x0 (INACTIVE): rxo_intr interrupt is not active after be enabled 0x1 (ACTIVE): rxo_intr interrupt is active after be enabled 3 1 read-only RX_FIFO_UIS Receive FIFO Underflow Interrupt Status 0x0 (INACTIVE): rxu_intr interrupt is not active after be enabled 0x1 (ACTIVE): rxu_intr interrupt is active after be enabled 2 1 read-only TX_FIFO_EIS Transmit FIFO Empty Interrupt Status 0x0 (INACTIVE): txe_intr interrupt is not active after be enabled 0x1 (ACTIVE): txe_intr interrupt is active after be enabled 0 1 read-only TX_FIFO_OIS Transmit FIFO Overflow Interrupt Status 0x0 (INACTIVE): txo_intr interrupt is not active after be enabled 0x1 (ACTIVE): txo_intr interrupt is active after be enabled 1 1 read-only MULTI_M_IC MULTI_M_IC Multi-Master Interrupt Clear Register 0x44 32 read-only n 0x0 0xFFFFFFFF MULTI_M_IC Clear Multi-Master Contention Interrupt. This register reflects the status of the interrupt. A read from this register clears the mst_intr interrupt writing has no effect. 0 1 read-only MW_CTRL MW_CTRL Microwire Control Register 0xC 32 read-write n 0x0 0xFFFFFFFF MW_DIR_DW Microwire Control. Defines the direction of the data word when the Microwire serial protocol is used. 0x0 (RECEIVE): SPI receives data 0x1 (TRANSMIT): SPI transmits data 1 1 read-write MW_HSG Microwire Handshaking. Used to enable and disable the busy/ready handshaking interface for the Microwire protocol. When enabled, the SPI checks for a ready status from the target slave, after the transfer of the last data/control bit, before clearing the SSI_BUSY status in the STAT register. 0x0 (DISABLE): Handshaking interface is disabled 0x1 (ENABLED): Handshaking interface is enabled Note: When the SPI is configured as a slave, this register serves no purpose. 2 1 read-write MW_XFE_MODE Microwire Transfer Mode. Defines whether the Microwire transfer is sequential or non-sequential. When sequential mode is used, only one control word is needed to transmit or receive a block of data words. When non-sequential mode is used, there must be a control word for each data word that is transmitted or received. 0x0 (NON_SEQUENTIAL): Non-Sequential Microwire Transfer 0x1 (SEQUENTIAL): Sequential Microwire Transfer 0 1 read-write RAW_INT_STAT RAW_INT_STAT Raw Interrupt Status Register 0x34 32 read-only n 0x0 0xFFFFFFFF MULTI_M_CRIS Multi-Master Contention Raw Interrupt Status 0x0 (INACTIVE): mst_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): mst_intr interrupt is full prior to be enabled 5 1 read-only RX_FIFO_FRIS Receive FIFO Full Raw Interrupt Status 0x0 (INACTIVE): rxf_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): rxf_intr interrupt is active prior to be enabled 4 1 read-only RX_FIFO_ORIS Receive FIFO Overflow Raw Interrupt Status 0x1 (ACTIVE): rxo_intr interrupt is not active prior to be enabled 0x0 (INACTIVE): rxo_intr interrupt is active prior be enabled 3 1 read-only RX_FIFO_URIS Receive FIFO Underflow Raw Interrupt Status 0x0 (INACTIVE): rxu_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): rxu_intr interrupt is active prior to be enabled 2 1 read-only TX_FIFO_ERIS Transmit FIFO Empty Raw Interrupt Status 0x0 (INACTIVE): txe_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): txe_intr interrupt is active prior be enabled 0 1 read-only TX_FIFO_ORIS Transmit FIFO Overflow Raw Interrupt Status 0x0 (INACTIVE): txo_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): txo_intr interrupt is active prior be enabled 1 1 read-only RX_FIFO_LEVEL RX_FIFO_LEVEL Receive FIFO Level Register 0x24 32 read-only n 0x0 0xFFFFFFFF RX_FIFO_LEVEL Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. 0 4 read-only RX_FIFO_OIC RX_FIFO_OIC Receive FIFO Overflow Interrupt Clear Register 0x3C 32 read-only n 0x0 0xFFFFFFFF RX_FIFO_OIC Clear Receive FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the rxo_intr interrupt writing has no effect. 0 1 read-only RX_FIFO_TL RX_FIFO_TL Receive FIFO Threshold Level 0x1C 32 read-write n 0x0 0xFFFFFFFF RX_FIFO_THD Receive FIFO Threshold. Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256. This register is sized to the number of address bits needed to access the FIFO. If you attempt to set this value greater than the depth of the FIFO, this field is not written and retains its current value.When the number of receive FIFO entries is greater than or equal to this value + 1, the receive FIFO full interrupt is triggered. 0 3 read-write RX_FIFO_UIC RX_FIFO_UIC Receive FIFO Underflow Interrupt Clear Register 0x40 32 read-only n 0x0 0xFFFFFFFF RX_FIFO_UIC Clear Receive FIFO Underflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the rxu_intr interrupt writing has no effect. 0 1 read-only SSI_EN SSI_EN SSI Enable Register 0x8 32 read-write n 0x0 0xFFFFFFFF SSI_EN SSI Enable. Enables and disables all SPI operations. When disabled, all serial transfers are halted immediately. Transmit and receive FIFO buffers are cleared when the device is disabled. 0x0 (DISABLE): Disables Serial Transfer 0x1 (ENABLED): Enables Serial Transfer 0 1 read-write STAT STAT Status Register 0x28 32 read-only n 0x6 0xFFFFFFFF DATA_COLN_ERR Data Collision Error. This bit will be set if MISO input is asserted by other master, when the SPI master is in the middle of the transfer. This informs the processor that the last data transfer was halted before completion. This bit is cleared when read. Note: When the SPI is configured as a slave, this register serves no purpose. 6 1 read-only RX_FIFO_FULL Receive FIFO Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0x0 (NOT_FULL): Receive FIFO is not full 0x1 (FULL): Receive FIFO is full 4 1 read-only RX_FIFO_NE Receive FIFO Not Empty. Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO. 0x0 (EMPTY): Receive FIFO is empty 0x1 (NOT_EMPTY): Receive FIFO is not empty 3 1 read-only SSI_BUSY SSI Busy Flag. When set, indicates that a serial transfer is in progress when cleared indicates that the SPI is idle or disabled. 0x0 (INACTIVE): SPI is idle or disabled 0x1 (ACTIVE): SPI is actively transferring data 0 1 read-only TX_ERR Transmission Error. Set if the transmit FIFO is empty when a transfer is started. Data from the previous transmission is resent on the txd line. This bit is cleared when read. 0x0 (NO_ERROR): No Error 0x1 (TX_ERROR): Transmission Error Note: When the SPI is configured as a master, this register serves no purpose. 5 1 read-only TX_FIFO_EMPTY Transmit FIFO Empty. When the transmit FIFO is completely empty, this bit is set. When the transmit FIFO contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0x0 (NOT_EMPTY): Transmit FIFO is not empty 0x1 (EMPTY): Transmit FIFO is empty 2 1 read-only TX_FIFO_NF Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0x0 (FULL): Transmit FIFO is full 0x1 (NOT_FULL): Transmit FIFO is not Full 1 1 read-only S_EN S_EN Slave Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF S_SEL_EN Slave Select Enable. Each bit in this register corresponds to a slave select line (CSn) from the SPI master. 0x0 (NOT_SELECTED): No slave selected 0x1 (SELECTED): Slave is selected Note: When the SPI is configured as a slave, this register serves no purpose. 0 2 read-write TX_FIFO_LEVEL TX_FIFO_LEVEL Transmit FIFO Level Register 0x20 32 read-only n 0x0 0xFFFFFFFF TX_FIFO_LEVEL Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. 0 4 read-only TX_FIFO_OIC TX_FIFO_OIC Transmit FIFO Overflow Interrupt Clear Register 0x38 32 read-only n 0x0 0xFFFFFFFF TX_FIFO_OIC Clear Transmit FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the txo_intr interrupt writing has no effect. 0 1 read-only TX_FIFO_TL TX_FIFO_TL Transmit FIFO Threshold Level Register 0x18 32 read-write n 0x0 0xFFFFFFFF TX_FIFO_THD Transmit FIFO Threshold. Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256 this register is sized to the number of address bits needed to access the FIFO. If you attempt to set this value greater than or equal to the depth of the FIFO, this field is not written and retains its current value.When the number of transmit FIFO entries is less than or equal to this value, the transmit FIFO empty interrupt is triggered. 0 3 read-write SPIS Serial Peripheral Interface SPI 0xA000C100 0x0 0x5C registers n SPI_M SPI_M Interrupt 4 SPI_S SPI_S Interrupt 5 BAUD BAUD Baud Rate Register 0x14 32 read-write n 0x0 0xFFFFFFFF SSI_CLK_DIV SSI Clock Divider. The LSB for this field is always set to 0 and is unaffected by a write operation, which ensures an even value is held in this register. If the value is 0, the serial output clock (sclk_out) is disabled. The frequency of the sclk_out is derived from the following equation: Fsclk_out = Fssi_clk/SSI_CLK_DIV Note: When the SPI is configured as a slave, this register serves no purpose. 0 16 read-write CTRL0 CTRL0 SPI Control Register 0 0x0 32 read-write n 0x1070000 0xFFFFFFFF CTRL_FRAME_SIZE Control Frame Size. Selects the length of the control word for the Microwire frame format. 0x0 (SIZE_01_BIT): 1-bit Control Word 0x1 (SIZE_02_BIT): 2-bit Control Word 0x2 (SIZE_03_BIT): 3-bit Control Word 0x3 (SIZE_04_BIT): 4-bit Control Word 0x4 (SIZE_05_BIT): 5-bit Control Word 0x5 (SIZE_06_BIT): 6-bit Control Word 0x6 (SIZE_07_BIT): 7-bit Control Word 0x7 (SIZE_08_BIT): 8-bit Control Word 0x8 (SIZE_09_BIT): 9-bit Control Word 0x9 (SIZE_10_BIT): 10-bit Control Word 0xa (SIZE_11_BIT): 11-bit Control Word 0xb (SIZE_12_BIT): 12-bit Control Word 0xc (SIZE_13_BIT): 13-bit Control Word 0xd (SIZE_14_BIT): 14-bit Control Word 0xe (SIZE_15_BIT): 15-bit Control Word 0xf (SIZE_16_BIT): 16-bit Control Word 12 4 read-write DATA_FRAME_SIZE Data Frame Size in 32-bit transfer size mode. Used to select the data frame size in 32-bit transfer mode. When the data frame size is programmed to be less than 32 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. You are responsible for making sure that transmit data is right-justified before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data. 0x3 (FRAME_04BITS): 4-bit serial data transfer 0x4 (FRAME_05BITS): 5-bit serial data transfer 0x5 (FRAME_06BITS): 6-bit serial data transfer 0x6 (FRAME_07BITS): 7-bit serial data transfer 0x7 (FRAME_08BITS): 8-bit serial data transfer 0x8 (FRAME_09BITS): 9-bit serial data transfer 0x9 (FRAME_10BITS): 10-bit serial data transfer 0xa (FRAME_11BITS): 11-bit serial data transfer 0xb (FRAME_12BITS): 12-bit serial data transfer 0xc (FRAME_13BITS): 13-bit serial data transfer 0xd (FRAME_14BITS): 14-bit serial data transfer 0xe (FRAME_15BITS): 15-bit serial data transfer 0xf (FRAME_16BITS): 16-bit serial data transfer 0x10 (FRAME_17BITS): 17-bit serial data transfer 0x11 (FRAME_18BITS): 18-bit serial data transfer 0x12 (FRAME_19BITS): 19-bit serial data transfer 0x13 (FRAME_20BITS): 20-bit serial data transfer 0x14 (FRAME_21BITS): 21-bit serial data transfer 0x15 (FRAME_22BITS): 22-bit serial data transfer 0x16 (FRAME_23BITS): 23-bit serial data transfer 0x17 (FRAME_24BITS): 24-bit serial data transfer 0x18 (FRAME_25BITS): 25-bit serial data transfer 0x19 (FRAME_26BITS): 26-bit serial data transfer 0x1a (FRAME_27BITS): 27-bit serial data transfer 0x1b (FRAME_28BITS): 28-bit serial data transfer 0x1c (FRAME_29BITS): 29-bit serial data transfer 0x1d (FRAME_30BITS): 30-bit serial data transfer 0x1e (FRAME_31BITS): 31-bit serial data transfer 0x1f (FRAME_32BITS): 32-bit serial data transfer 16 5 read-write FRAME_FORMAT Frame Format. Selects which serial protocol transfers the data. 0x0 (MOTOROLA_SPI): Motorolla SPI Frame Format 0x1 (TEXAS_SSP): Texas Instruments SSP Frame Format 0x2 (NS_MICROWIRE): National Microwire Frame Format 0x3 (RESERVED): Reserved value 4 2 read-write SERIAL_CLK_PHASE Serial Clock Phase. Valid when the frame format (FRAME_FORMAT) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SERIAL_CLK_PHASE = 0, data are captured on the first edge of the serial clock. When SERIAL_CLK_PHASE = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data are captured on the second edge of the serial clock. 0x0 (SERIAL_CLK_PHASE_MIDDLE): Serial clock toggles in middle of first data bit 0x1 (SERIAL_CLK_PHASE_START): Serial clock toggles at start of first data bit 6 1 read-write SERIAL_CLK_POL Serial Clock Polarity. Valid when the frame format (FRAME_FORMAT) is set to Motorola SPI. Used to select the polarity of the inactive serial clock, which is held inactive when the SPI master is not actively transferring data on the serial bus. 0x0 (SCLK_LOW): Inactive state of serial clock is low 0x1 (SCLK_HIGH): Inactive state of serial clock is high 7 1 read-write SHIFT_REG_LOOP Shift Register Loop. Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input. 0x0 (NORMAL_MODE): Normal mode operation 0x1 (TESTING_MODE): Test mode: TX and RX shift reg connected 11 1 read-write S_OUT_EN Slave Output Enable. Relevant only when the SPI is configured as a serial-slave device. When configured as a serial master, this bit field has no functionality. 0x0 (ENABLED): Slave Output is enabled 0x1 (DISABLED): Slave Output is disabled Note: When the SPI is configured as a master, this register serves no purpose. 10 1 read-write S_ST_EN Slave Select Toggle Enable. When operating in SPI mode with clock phase (SERIAL_CLK_PHASE) set to 0, this register controls the behavior of the slave select line (CS) between data frames. If this register field is set to 1 the CS line will toggle between consecutive data frames, with the serial clock (sclk) being held to its default value while CS is high if this register field is set to 0 the CS will stay low and sclk will run continuously for the duration of the transfer. Note: When the SPI is configured as a slave, this register serves no purpose 24 1 read-write XFE_MODE Transfer Mode. This transfer mode is only valid when the SPI is configured as master device. 0x0 - Transmit and Receive 0x1 - Transmit Only 0x2 - Receive Only 0x3 - EEPROM Read 0x0 (TX_AND_RX): Transmit and receive 0x1 (TX_ONLY): Transmit only mode 0x2 (RX_ONLY): Receive only mode 0x3 (EEPROM_READ): EEPROM Read mode 8 2 read-write CTRL1 CTRL1 SPI Control Register 1 0x4 32 read-write n 0x0 0xFFFFFFFF NUM_DATA_FRAME Number of Data Frames. When XFE_MODE = 10 or XFE_MODE = 11, this register field sets thenumber of data frames to be continuously received by the SPI. The SPI continues to receive serialdata until the number of data frames received is equal to thisregister value plus 1, which enables you to receive up to 64KB of data in a continuous transfer. Note: When the SPI is configured as a slave, this register serves no purpose. 0 16 read-write DATA DATA Data Register 0x60 32 read-write n 0x0 0xFFFFFFFF DATA Data Register. When writing to this register, you must right-justify the data. Read data are automatically right-justified. 0 32 read-write DMA_CTRL DMA_CTRL DMA Control Register 0x4C 32 read-write n 0x0 0xFFFFFFFF RX_DMA_EN Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel 0x0 (DISABLE): Receive DMA disabled 0x1 (ENABLED): Receive DMA enabled 0 1 read-write TX_DMA_EN Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. 0x0 (DISABLE): Transmit DMA disabled 0x1 (ENABLED): Transmit DMA enabled 1 1 read-write DMA_RX_DL DMA_RX_DL DMA Receive Data Level Register 0x54 32 read-write n 0x0 0xFFFFFFFF DMA_RX_DL Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMA_RX_DL+1 that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or above this field value + 1, and RX_DMA_EN=1. 0 3 read-write DMA_TX_DL DMA_TX_DL DMA Transmit Data Level Register 0x50 32 read-write n 0x0 0xFFFFFFFF DMA_TX_DL Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TX_DMA_EN = 1. 0 3 read-write INT_CLR INT_CLR Interrupt Clear Register 0x48 32 read-only n 0x0 0xFFFFFFFF INT_CLR Clear Interrupts. This register is set if any of the interrupts below are active. A read clears the txo_intr, rxu_intr, rxo_intr, and the mst_intr interrupts. Writing to this register has no effect. 0 1 read-only INT_MASK INT_MASK Interrupt Mask Register 0x2C 32 read-write n 0x3F 0xFFFFFFFF MULTI_M_CIM Multi-Master Contention Interrupt Mask. 0x0 (MASKED): Disable mst_intr interrupt 0x1 (UNMASKED): Enable mst_intr interrupt Note: When the SPI is configured as a slave, this register serves no purpose. 5 1 read-write RX_FIFO_FIM Receive FIFO Full Interrupt Mask 0x0 (MASKED): Disable rxf_intr interrupt 0x1 (UNMASKED): Enable rxf_intr interrupt 4 1 read-write RX_FIFO_OIM Receive FIFO Overflow Interrupt Mask 0x0 (MASKED): Disable rxo_intr interrupt 0x1 (UNMASKED): Enable rxo_intr interrupt 3 1 read-write RX_FIFO_UIM Receive FIFO Underflow Interrupt Mask 0x0 (MASKED): Disable rxu_intr interrupt 0x1 (UNMASKED): Enable rxu_intr interrupt 2 1 read-write TX_FIFO_EIM Transmit FIFO Empty Interrupt Mask 0x0 (MASKED): Disable txe_intr interrupt 0x1 (UNMASKED): Enable txe_intr interrupt 0 1 read-write TX_FIFO_OIM Transmit FIFO Overflow Interrupt Mask 0x0 (MASKED): Disable txo_intr interrupt 0x1 (UNMASKED): Enable txo_intr interrupt 1 1 read-write INT_STAT INT_STAT Interrupt Status Register 0x30 32 read-only n 0x0 0xFFFFFFFF MULTI_M_CIS Multi-Master Contention Interrupt Status 0x0 (INACTIVE): mst_intr interrupt is not active after be enabled 0x1 (ACTIVE): mst_intr interrupt is full after be enabled 5 1 read-only RX_FIFO_FIS Receive FIFO Full Interrupt Status 0x0 (INACTIVE): rxf_intr interrupt is not active after be enabled 0x1 (ACTIVE): rxf_intr interrupt is full after be enabled 4 1 read-only RX_FIFO_OIS Receive FIFO Overflow Interrupt Status 0x0 (INACTIVE): rxo_intr interrupt is not active after be enabled 0x1 (ACTIVE): rxo_intr interrupt is active after be enabled 3 1 read-only RX_FIFO_UIS Receive FIFO Underflow Interrupt Status 0x0 (INACTIVE): rxu_intr interrupt is not active after be enabled 0x1 (ACTIVE): rxu_intr interrupt is active after be enabled 2 1 read-only TX_FIFO_EIS Transmit FIFO Empty Interrupt Status 0x0 (INACTIVE): txe_intr interrupt is not active after be enabled 0x1 (ACTIVE): txe_intr interrupt is active after be enabled 0 1 read-only TX_FIFO_OIS Transmit FIFO Overflow Interrupt Status 0x0 (INACTIVE): txo_intr interrupt is not active after be enabled 0x1 (ACTIVE): txo_intr interrupt is active after be enabled 1 1 read-only MULTI_M_IC MULTI_M_IC Multi-Master Interrupt Clear Register 0x44 32 read-only n 0x0 0xFFFFFFFF MULTI_M_IC Clear Multi-Master Contention Interrupt. This register reflects the status of the interrupt. A read from this register clears the mst_intr interrupt writing has no effect. 0 1 read-only MW_CTRL MW_CTRL Microwire Control Register 0xC 32 read-write n 0x0 0xFFFFFFFF MW_DIR_DW Microwire Control. Defines the direction of the data word when the Microwire serial protocol is used. 0x0 (RECEIVE): SPI receives data 0x1 (TRANSMIT): SPI transmits data 1 1 read-write MW_HSG Microwire Handshaking. Used to enable and disable the busy/ready handshaking interface for the Microwire protocol. When enabled, the SPI checks for a ready status from the target slave, after the transfer of the last data/control bit, before clearing the SSI_BUSY status in the STAT register. 0x0 (DISABLE): Handshaking interface is disabled 0x1 (ENABLED): Handshaking interface is enabled Note: When the SPI is configured as a slave, this register serves no purpose. 2 1 read-write MW_XFE_MODE Microwire Transfer Mode. Defines whether the Microwire transfer is sequential or non-sequential. When sequential mode is used, only one control word is needed to transmit or receive a block of data words. When non-sequential mode is used, there must be a control word for each data word that is transmitted or received. 0x0 (NON_SEQUENTIAL): Non-Sequential Microwire Transfer 0x1 (SEQUENTIAL): Sequential Microwire Transfer 0 1 read-write RAW_INT_STAT RAW_INT_STAT Raw Interrupt Status Register 0x34 32 read-only n 0x0 0xFFFFFFFF MULTI_M_CRIS Multi-Master Contention Raw Interrupt Status 0x0 (INACTIVE): mst_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): mst_intr interrupt is full prior to be enabled 5 1 read-only RX_FIFO_FRIS Receive FIFO Full Raw Interrupt Status 0x0 (INACTIVE): rxf_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): rxf_intr interrupt is active prior to be enabled 4 1 read-only RX_FIFO_ORIS Receive FIFO Overflow Raw Interrupt Status 0x1 (ACTIVE): rxo_intr interrupt is not active prior to be enabled 0x0 (INACTIVE): rxo_intr interrupt is active prior be enabled 3 1 read-only RX_FIFO_URIS Receive FIFO Underflow Raw Interrupt Status 0x0 (INACTIVE): rxu_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): rxu_intr interrupt is active prior to be enabled 2 1 read-only TX_FIFO_ERIS Transmit FIFO Empty Raw Interrupt Status 0x0 (INACTIVE): txe_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): txe_intr interrupt is active prior be enabled 0 1 read-only TX_FIFO_ORIS Transmit FIFO Overflow Raw Interrupt Status 0x0 (INACTIVE): txo_intr interrupt is not active prior to be enabled 0x1 (ACTIVE): txo_intr interrupt is active prior be enabled 1 1 read-only RX_FIFO_LEVEL RX_FIFO_LEVEL Receive FIFO Level Register 0x24 32 read-only n 0x0 0xFFFFFFFF RX_FIFO_LEVEL Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. 0 4 read-only RX_FIFO_OIC RX_FIFO_OIC Receive FIFO Overflow Interrupt Clear Register 0x3C 32 read-only n 0x0 0xFFFFFFFF RX_FIFO_OIC Clear Receive FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the rxo_intr interrupt writing has no effect. 0 1 read-only RX_FIFO_TL RX_FIFO_TL Receive FIFO Threshold Level 0x1C 32 read-write n 0x0 0xFFFFFFFF RX_FIFO_THD Receive FIFO Threshold. Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256. This register is sized to the number of address bits needed to access the FIFO. If you attempt to set this value greater than the depth of the FIFO, this field is not written and retains its current value.When the number of receive FIFO entries is greater than or equal to this value + 1, the receive FIFO full interrupt is triggered. 0 3 read-write RX_FIFO_UIC RX_FIFO_UIC Receive FIFO Underflow Interrupt Clear Register 0x40 32 read-only n 0x0 0xFFFFFFFF RX_FIFO_UIC Clear Receive FIFO Underflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the rxu_intr interrupt writing has no effect. 0 1 read-only SSI_EN SSI_EN SSI Enable Register 0x8 32 read-write n 0x0 0xFFFFFFFF SSI_EN SSI Enable. Enables and disables all SPI operations. When disabled, all serial transfers are halted immediately. Transmit and receive FIFO buffers are cleared when the device is disabled. 0x0 (DISABLE): Disables Serial Transfer 0x1 (ENABLED): Enables Serial Transfer 0 1 read-write STAT STAT Status Register 0x28 32 read-only n 0x6 0xFFFFFFFF DATA_COLN_ERR Data Collision Error. This bit will be set if MISO input is asserted by other master, when the SPI master is in the middle of the transfer. This informs the processor that the last data transfer was halted before completion. This bit is cleared when read. Note: When the SPI is configured as a slave, this register serves no purpose. 6 1 read-only RX_FIFO_FULL Receive FIFO Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0x0 (NOT_FULL): Receive FIFO is not full 0x1 (FULL): Receive FIFO is full 4 1 read-only RX_FIFO_NE Receive FIFO Not Empty. Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO. 0x0 (EMPTY): Receive FIFO is empty 0x1 (NOT_EMPTY): Receive FIFO is not empty 3 1 read-only SSI_BUSY SSI Busy Flag. When set, indicates that a serial transfer is in progress when cleared indicates that the SPI is idle or disabled. 0x0 (INACTIVE): SPI is idle or disabled 0x1 (ACTIVE): SPI is actively transferring data 0 1 read-only TX_ERR Transmission Error. Set if the transmit FIFO is empty when a transfer is started. Data from the previous transmission is resent on the txd line. This bit is cleared when read. 0x0 (NO_ERROR): No Error 0x1 (TX_ERROR): Transmission Error Note: When the SPI is configured as a master, this register serves no purpose. 5 1 read-only TX_FIFO_EMPTY Transmit FIFO Empty. When the transmit FIFO is completely empty, this bit is set. When the transmit FIFO contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0x0 (NOT_EMPTY): Transmit FIFO is not empty 0x1 (EMPTY): Transmit FIFO is empty 2 1 read-only TX_FIFO_NF Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0x0 (FULL): Transmit FIFO is full 0x1 (NOT_FULL): Transmit FIFO is not Full 1 1 read-only S_EN S_EN Slave Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF S_SEL_EN Slave Select Enable. Each bit in this register corresponds to a slave select line (CSn) from the SPI master. 0x0 (NOT_SELECTED): No slave selected 0x1 (SELECTED): Slave is selected Note: When the SPI is configured as a slave, this register serves no purpose. 0 2 read-write TX_FIFO_LEVEL TX_FIFO_LEVEL Transmit FIFO Level Register 0x20 32 read-only n 0x0 0xFFFFFFFF TX_FIFO_LEVEL Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. 0 4 read-only TX_FIFO_OIC TX_FIFO_OIC Transmit FIFO Overflow Interrupt Clear Register 0x38 32 read-only n 0x0 0xFFFFFFFF TX_FIFO_OIC Clear Transmit FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the txo_intr interrupt writing has no effect. 0 1 read-only TX_FIFO_TL TX_FIFO_TL Transmit FIFO Threshold Level Register 0x18 32 read-write n 0x0 0xFFFFFFFF TX_FIFO_THD Transmit FIFO Threshold. Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256 this register is sized to the number of address bits needed to access the FIFO. If you attempt to set this value greater than or equal to the depth of the FIFO, this field is not written and retains its current value.When the number of transmit FIFO entries is less than or equal to this value, the transmit FIFO empty interrupt is triggered. 0 3 read-write TIMER0 Analog-to-Digital Converter TIMER 0xA0000000 0x0 0x10 registers n TIMER0 Timer0 interrupts 8 TIMER1 Timer1 interrupts 9 DUAL_TIMER DUAL_TIMER interrupts 10 SLEEP_TIMER Sleep Timer Interrupt 26 CTRL CTRL Timer Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF EN Enable the timer 0 1 read-write INT_EN Timer interrupt enable 3 1 read-write RSVD Reserved bits 1 2 read-only INT_STAT INT_STAT Timer Interrupt Status Register 0xC 32 read-write n 0x0 0xFFFFFFFF STAT Timer interrupt. Write one to clear. 0 1 read-write RELOAD RELOAD Timer Reload Register 0x8 32 read-write n 0x0 0xFFFFFFFF COUNT Reload value. 0 32 read-write VAL VAL Timer Value Register 0x4 32 read-write n 0x0 0xFFFFFFFF COUNT Current value. 0 32 read-write TIMER1 Analog-to-Digital Converter TIMER 0xA0001000 0x0 0x10 registers n TIMER0 Timer0 interrupts 8 TIMER1 Timer1 interrupts 9 DUAL_TIMER DUAL_TIMER interrupts 10 SLEEP_TIMER Sleep Timer Interrupt 26 CTRL CTRL Timer Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF EN Enable the timer 0 1 read-write INT_EN Timer interrupt enable 3 1 read-write RSVD Reserved bits 1 2 read-only INT_STAT INT_STAT Timer Interrupt Status Register 0xC 32 read-write n 0x0 0xFFFFFFFF STAT Timer interrupt. Write one to clear. 0 1 read-write RELOAD RELOAD Timer Reload Register 0x8 32 read-write n 0x0 0xFFFFFFFF COUNT Reload value. 0 32 read-write VAL VAL Timer Value Register 0x4 32 read-write n 0x0 0xFFFFFFFF COUNT Current value. 0 32 read-write UART0 UART UART 0xA000C600 0x0 0x70 registers n DIV_LATCH_FRACTION DIV_LATCH_FRACTION UART DMA Software Acknowledge Register 0xC0 32 read-write n 0x0 0xFFFFFFFF DIV_LATCH_FRACTION Fractional part of divisor 0 4 read-write DIV_LATCH_HIGH DIV_LATCH_HIGH UART Divisor Latch High Register 0x4 32 read-write n 0x0 0xFFFFFFFF DLH Divisor Latch (high). 0 8 read-write DIV_LATCH_LOW DIV_LATCH_LOW UART Divisor Latch (Low)Register RX_BUF 0x0 32 read-write n 0x0 0xFFFFFFFF DIV_LATCH_LOW Divisor Latch (Low). 0 8 read-write DMA_SW_ACK DMA_SW_ACK UART DMA Software Acknowledge Register 0xA8 32 write-only n 0x0 0xFFFFFFFF DMA_SW_ACK DMA Software Acknowledge. 0 1 write-only FIFO_ACCESS FIFO_ACCESS UART FIFO Access Register 0x70 32 read-only n 0x0 0xFFFFFFFF FIFO_ACCESS_EN This register is use to enable a FIFO access mode 0 1 read-only FIFO_CTRL FIFO_CTRL UART FIFO Control Register 0x8 32 write-only n 0x0 0xFFFFFFFF DMA_MODE DMA Mode 3 1 write-only FIFO_EN FIFO Enable 0 1 write-only RX_FIFO_RST RCVR FIFO Reset 1 1 write-only RX_FIFO_TRG RCVR Trigger 6 2 write-only TX_EMPTY_TRG TX Empty Trigger 4 2 write-only TX_FIFO_RST XMIT FIFO Reset 2 1 write-only HALT_TX HALT_TX UART Halt TX Register 0xA4 32 read-write n 0x0 0xFFFFFFFF HALT_TX Halt TX 0 1 read-write INT_EN INT_EN UART Interrupt Enable Register DIV_LATCH_HIGH 0x4 32 read-write n 0x0 0xFFFFFFFF INT_GTHEE This is used to enable/disable the generation of TX_HDG_EMPTY Interrupt 7 1 read-write INT_MSE Enable Modem Status Interrupt. 3 1 read-write INT_RX_EN Enable Received Data Available Interrupt. 0 1 read-write INT_RX_LSE Enable Receiver Line Status Interrupt. 2 1 read-write INT_TX_HE Enable Transmit Holding Register Empty Interrupt 1 1 read-write INT_ID INT_ID UART Interrupt Identification Register FIFO_CTRL 0x8 32 read-only n 0x1 0xFFFFFFFF FIFO_EN This is used to indicate whether the FIFOs are enabled or disabled. 6 2 read-only INT_PRIOR This indicates the highest priority pending interrupt 0 4 read-only LINE_CTRL LINE_CTRL UART Line Control Register 0xC 32 read-write n 0x0 0xFFFFFFFF BREAK_CTRL_BIT Break Control Bit. 6 1 read-write DATA_LEN_SEL Data Length Select 0 2 read-write DIV_LATCH_AB Divisor Latch Access Bit 7 1 read-write EVEN_PARITY_SEL Even Parity Select. 4 1 read-write PARITY_EN Parity Enable. 3 1 read-write STICK_PARITY Stick Parity. 5 1 read-write STOP_BITS Number of stop bits 2 1 read-write LINE_STAT LINE_STAT UART Line Status Register 0x14 32 read-only n 0x60 0xFFFFFFFF BREAK_INT Break Interrupt bit 4 1 read-only DATA_READY Data Ready bit. 0 1 read-only FRAMING_ERR Framing Error bit. 3 1 read-only OVER_ERR Overrun error bit. 1 1 read-only PARITY_ERR Parity Error bit. 2 1 read-only RX_FIFO_ERR Receiver FIFO Error bit. 7 1 read-only TX_EMPTY Transmitter Empty bit 6 1 read-only TX_HDG_EMPTY Transmit Holding Register Empty bit 5 1 read-only MODEM_CTRL MODEM_CTRL UART Modem Control Register 0x10 32 read-write n 0x0 0xFFFFFFFF LOOP_BACK LoopBack Bit 4 1 read-write REQ_TO_SEND Request to Send 1 1 read-write MODEM_STAT MODEM_STAT UART Modem Status Register 0x18 32 read-only n 0x0 0xFFFFFFFF CLR_SEND Clear to Send 4 1 read-only DELTA_CLR_SEND Delta Clear to Send. 0 1 read-only RX_BUF RX_BUF UART Receive Buffer Register 0x0 32 read-only n 0x0 0xFFFFFFFF RX_BUF Receive Buffer Register. 0 8 read-only RX_FIFO_LEVEL RX_FIFO_LEVEL UART Receive FIFO Level Register 0x84 32 read-only n 0x0 0xFFFFFFFF RX_FIFO_LEVEL Receive FIFO Level. 0 8 read-only SCRATCHPAD SCRATCHPAD UART Scratchpad Register 0x1C 32 read-write n 0x0 0xFFFFFFFF SCR This register is for programmers to use as a temporary storage space 0 8 read-write SHADOW_BREAK_CTRL SHADOW_BREAK_CTRL UART Shadow Break Control Register 0x90 32 read-write n 0x0 0xFFFFFFFF SHADOW_BREAK_CB Shadow Break Control Bit. 0 1 read-write SHADOW_DMA_MODE SHADOW_DMA_MODE UART Shadow DMA Mode Register 0x94 32 read-write n 0x0 0xFFFFFFFF SHADOW_DMA_MODE Shadow DMA Mode. 0 1 read-write SHADOW_FIFO_EN SHADOW_FIFO_EN UART Shadow FIFO Enable Register 0x98 32 read-write n 0x0 0xFFFFFFFF SHADOW_FIFO_EN Shadow FIFO Enable. 0 1 read-write SHADOW_REQ_SEND SHADOW_REQ_SEND UART Shadow Request to Send Register 0x8C 32 read-write n 0x0 0xFFFFFFFF SHADOW_REQUEST_SEND Shadow Request to Send. 0 1 read-write SHADOW_RX_BUFx SHADOW_RX_BUFx UART Shadow Receive Buffer Register 0x30 32 read-only n 0x0 0xFFFFFFFF SHADOW_RX_BUFn Shadow Receive Buffer Register n. 0 8 read-only SHADOW_RX_TRG SHADOW_RX_TRG UART Shadow RCVR Trigger Register 0x9C 32 read-write n 0x0 0xFFFFFFFF SHADOW_RX_TRG Shadow RCVR Trigger. 0 2 read-write SHADOW_TX_HDGx SHADOW_TX_HDGx UART Shadow Transmit Holding Register SHADOW_RX_BUFx 0x30 32 write-only n 0x0 0xFFFFFFFF SHADOW_TX_HDGn Shadow Transmit Holding Register n 0 8 write-only SHADOW_TX_TRG SHADOW_TX_TRG UART Shadow TX Empty Trigger Register 0xA0 32 read-write n 0x0 0xFFFFFFFF SHADOW_TX_TRG Shadow TX Empty Trigger. 0 2 read-write STAT STAT UART Status Register 0x7C 32 read-only n 0x6 0xFFFFFFFF RX_FIFO_EMPTY Receive FIFO Not Empty. 3 1 read-only RX_FIFO_FULL Receive FIFO Full. 4 1 read-only TX_FIFO_EMPTY Transmit FIFO Empty. 2 1 read-only TX_FIFO_FULL Transmit FIFO Not Full 1 1 read-only SW_RST SW_RST UART Software Reset Register 0x88 32 write-only n 0x0 0xFFFFFFFF RX_FIFO_RST RCVR FIFO Reset. 1 1 write-only TX_FIFO_RST XMIT FIFO Reset. 2 1 write-only UART_RST UART Reset 0 1 write-only TX_FIFO_LEVEL TX_FIFO_LEVEL UART Transmit FIFO Level Register 0x80 32 read-only n 0x0 0xFFFFFFFF TX_FIFO_LEVEL Transmit FIFO Level. 0 8 read-only TX_HDG TX_HDG UART Transmit Holding Register DIV_LATCH_LOW 0x0 32 write-only n 0x0 0xFFFFFFFF TX_HDG Transmit Holding Register. 0 8 write-only UART1 UART UART 0xA000C700 0x0 0x70 registers n DIV_LATCH_FRACTION DIV_LATCH_FRACTION UART DMA Software Acknowledge Register 0xC0 32 read-write n 0x0 0xFFFFFFFF DIV_LATCH_FRACTION Fractional part of divisor 0 4 read-write DIV_LATCH_HIGH DIV_LATCH_HIGH UART Divisor Latch High Register 0x4 32 read-write n 0x0 0xFFFFFFFF DLH Divisor Latch (high). 0 8 read-write DIV_LATCH_LOW DIV_LATCH_LOW UART Divisor Latch (Low)Register RX_BUF 0x0 32 read-write n 0x0 0xFFFFFFFF DIV_LATCH_LOW Divisor Latch (Low). 0 8 read-write DMA_SW_ACK DMA_SW_ACK UART DMA Software Acknowledge Register 0xA8 32 write-only n 0x0 0xFFFFFFFF DMA_SW_ACK DMA Software Acknowledge. 0 1 write-only FIFO_ACCESS FIFO_ACCESS UART FIFO Access Register 0x70 32 read-only n 0x0 0xFFFFFFFF FIFO_ACCESS_EN This register is use to enable a FIFO access mode 0 1 read-only FIFO_CTRL FIFO_CTRL UART FIFO Control Register 0x8 32 write-only n 0x0 0xFFFFFFFF DMA_MODE DMA Mode 3 1 write-only FIFO_EN FIFO Enable 0 1 write-only RX_FIFO_RST RCVR FIFO Reset 1 1 write-only RX_FIFO_TRG RCVR Trigger 6 2 write-only TX_EMPTY_TRG TX Empty Trigger 4 2 write-only TX_FIFO_RST XMIT FIFO Reset 2 1 write-only HALT_TX HALT_TX UART Halt TX Register 0xA4 32 read-write n 0x0 0xFFFFFFFF HALT_TX Halt TX 0 1 read-write INT_EN INT_EN UART Interrupt Enable Register DIV_LATCH_HIGH 0x4 32 read-write n 0x0 0xFFFFFFFF INT_GTHEE This is used to enable/disable the generation of TX_HDG_EMPTY Interrupt 7 1 read-write INT_MSE Enable Modem Status Interrupt. 3 1 read-write INT_RX_EN Enable Received Data Available Interrupt. 0 1 read-write INT_RX_LSE Enable Receiver Line Status Interrupt. 2 1 read-write INT_TX_HE Enable Transmit Holding Register Empty Interrupt 1 1 read-write INT_ID INT_ID UART Interrupt Identification Register FIFO_CTRL 0x8 32 read-only n 0x1 0xFFFFFFFF FIFO_EN This is used to indicate whether the FIFOs are enabled or disabled. 6 2 read-only INT_PRIOR This indicates the highest priority pending interrupt 0 4 read-only LINE_CTRL LINE_CTRL UART Line Control Register 0xC 32 read-write n 0x0 0xFFFFFFFF BREAK_CTRL_BIT Break Control Bit. 6 1 read-write DATA_LEN_SEL Data Length Select 0 2 read-write DIV_LATCH_AB Divisor Latch Access Bit 7 1 read-write EVEN_PARITY_SEL Even Parity Select. 4 1 read-write PARITY_EN Parity Enable. 3 1 read-write STICK_PARITY Stick Parity. 5 1 read-write STOP_BITS Number of stop bits 2 1 read-write LINE_STAT LINE_STAT UART Line Status Register 0x14 32 read-only n 0x60 0xFFFFFFFF BREAK_INT Break Interrupt bit 4 1 read-only DATA_READY Data Ready bit. 0 1 read-only FRAMING_ERR Framing Error bit. 3 1 read-only OVER_ERR Overrun error bit. 1 1 read-only PARITY_ERR Parity Error bit. 2 1 read-only RX_FIFO_ERR Receiver FIFO Error bit. 7 1 read-only TX_EMPTY Transmitter Empty bit 6 1 read-only TX_HDG_EMPTY Transmit Holding Register Empty bit 5 1 read-only MODEM_CTRL MODEM_CTRL UART Modem Control Register 0x10 32 read-write n 0x0 0xFFFFFFFF LOOP_BACK LoopBack Bit 4 1 read-write REQ_TO_SEND Request to Send 1 1 read-write MODEM_STAT MODEM_STAT UART Modem Status Register 0x18 32 read-only n 0x0 0xFFFFFFFF CLR_SEND Clear to Send 4 1 read-only DELTA_CLR_SEND Delta Clear to Send. 0 1 read-only RX_BUF RX_BUF UART Receive Buffer Register 0x0 32 read-only n 0x0 0xFFFFFFFF RX_BUF Receive Buffer Register. 0 8 read-only RX_FIFO_LEVEL RX_FIFO_LEVEL UART Receive FIFO Level Register 0x84 32 read-only n 0x0 0xFFFFFFFF RX_FIFO_LEVEL Receive FIFO Level. 0 8 read-only SCRATCHPAD SCRATCHPAD UART Scratchpad Register 0x1C 32 read-write n 0x0 0xFFFFFFFF SCR This register is for programmers to use as a temporary storage space 0 8 read-write SHADOW_BREAK_CTRL SHADOW_BREAK_CTRL UART Shadow Break Control Register 0x90 32 read-write n 0x0 0xFFFFFFFF SHADOW_BREAK_CB Shadow Break Control Bit. 0 1 read-write SHADOW_DMA_MODE SHADOW_DMA_MODE UART Shadow DMA Mode Register 0x94 32 read-write n 0x0 0xFFFFFFFF SHADOW_DMA_MODE Shadow DMA Mode. 0 1 read-write SHADOW_FIFO_EN SHADOW_FIFO_EN UART Shadow FIFO Enable Register 0x98 32 read-write n 0x0 0xFFFFFFFF SHADOW_FIFO_EN Shadow FIFO Enable. 0 1 read-write SHADOW_REQ_SEND SHADOW_REQ_SEND UART Shadow Request to Send Register 0x8C 32 read-write n 0x0 0xFFFFFFFF SHADOW_REQUEST_SEND Shadow Request to Send. 0 1 read-write SHADOW_RX_BUFx SHADOW_RX_BUFx UART Shadow Receive Buffer Register 0x30 32 read-only n 0x0 0xFFFFFFFF SHADOW_RX_BUFn Shadow Receive Buffer Register n. 0 8 read-only SHADOW_RX_TRG SHADOW_RX_TRG UART Shadow RCVR Trigger Register 0x9C 32 read-write n 0x0 0xFFFFFFFF SHADOW_RX_TRG Shadow RCVR Trigger. 0 2 read-write SHADOW_TX_HDGx SHADOW_TX_HDGx UART Shadow Transmit Holding Register SHADOW_RX_BUFx 0x30 32 write-only n 0x0 0xFFFFFFFF SHADOW_TX_HDGn Shadow Transmit Holding Register n 0 8 write-only SHADOW_TX_TRG SHADOW_TX_TRG UART Shadow TX Empty Trigger Register 0xA0 32 read-write n 0x0 0xFFFFFFFF SHADOW_TX_TRG Shadow TX Empty Trigger. 0 2 read-write STAT STAT UART Status Register 0x7C 32 read-only n 0x6 0xFFFFFFFF RX_FIFO_EMPTY Receive FIFO Not Empty. 3 1 read-only RX_FIFO_FULL Receive FIFO Full. 4 1 read-only TX_FIFO_EMPTY Transmit FIFO Empty. 2 1 read-only TX_FIFO_FULL Transmit FIFO Not Full 1 1 read-only SW_RST SW_RST UART Software Reset Register 0x88 32 write-only n 0x0 0xFFFFFFFF RX_FIFO_RST RCVR FIFO Reset. 1 1 write-only TX_FIFO_RST XMIT FIFO Reset. 2 1 write-only UART_RST UART Reset 0 1 write-only TX_FIFO_LEVEL TX_FIFO_LEVEL UART Transmit FIFO Level Register 0x80 32 read-only n 0x0 0xFFFFFFFF TX_FIFO_LEVEL Transmit FIFO Level. 0 8 read-only TX_HDG TX_HDG UART Transmit Holding Register DIV_LATCH_LOW 0x0 32 write-only n 0x0 0xFFFFFFFF TX_HDG Transmit Holding Register. 0 8 write-only WDT System Watchdog WDT 0xA0008000 0x0 0x1C registers n WDT Watchdog interrupt 0 AON_WDT AON_WDT interrupt 28 CTRL CTRL System Watchdog Control Register 0x8 32 read-write n 0x0 0xFFFFFFFF INT_EN Enable the interrupt event. 0 1 read-write RST_EN Enable watchdog reset output 1 1 read-write INT_CLR INT_CLR System Watchdog Clear Interrupt Register 0xC 32 write-only n 0x0 0xFFFFFFFF CLR Clear the watchdog interrupt event. 0 32 write-only INT_RAW_STAT INT_RAW_STAT System Watchdog Raw Interrupt Status Register 0x10 32 read-only n 0x0 0xFFFFFFFF RAW_STAT Raw interrupt status from the counter 0 1 read-only INT_STAT INT_STAT System Watchdog Interrupt Status Register 0x14 32 read-only n 0x0 0xFFFFFFFF RO Reserved bits 1 31 read-only STAT Enable interrupt status from the counter. 0 1 read-only LOAD LOAD System Watchdog Load Register 0x0 32 read-write n 0xFFFFFFFF 0xFFFFFFFF COUNT Reload value. A write to this register sets the current value. 0 32 read-write LOCK LOCK System Watchdog Lock Register 0xC00 32 read-write n 0x0 0xFFFFFFFF WR_EN Enable write access to all other registers by writing 0x1ACCE551. Disable write access by writing any other value. 1 31 read-write WR_EN_STAT Register write enable status 0 1 read-write VAL VAL System Watchdog Value Register 0x4 32 read-only n 0xFFFFFFFF 0xFFFFFFFF COUNT Current value of the watchdog counter 0 32 read-only XQSPI XIP_Cache Register XQSPI 0xA000D000 0x0 0x90 registers n CACHE_CRTL1 CACHE_CRTL1 XQSPI cache Control 1 Register 0x4 32 read-write n 0x110 0xFFFFFFFF BIAS_TRIM Bias Trim signal 4 4 read-write BUS_MUX_EN Debug bus Mux Enable/Disable. 0x0: enable 0x1: disable 11 1 read-write BUS_MUX_SRC Select 1 of 8 debugbus configurations Debug bus is 8-bit bus. 8 3 read-write RD_MARGIN Read margin 0 1 read-write RW_MARGIN_CTRL Read write margin control 2 2 read-write WR_MARGIN Write margin 1 1 read-write CACHE_CTRL0 CACHE_CTRL0 XQSPI cache Control 0 Register 0x0 32 read-write n 0x11 0xFFFFFFFF CACHE_EN 0x0: Cache_enabled 0x1: Cache_disabled 0 1 read-write FIFO_CLR Clear LFU FIFO. 0x0: FIFO in Normal Mode 0x1: FIFO in Clear Mode 3 1 read-write HIT_MISS_CLR Clear Hit/Miss Counters. 0x0: Hit/Miss Counters in Normal Mode 0x1: Hit/Miss Counters in Clear Mode 4 1 read-write TAG_FLUSH_EN Enable tag memory Flush Out of reset. Tag memory will get flushed unless tag_ret is enabled (Tag_ret signal lives in cpu register space). 0x0: Tag memory Flush is disabled 0x1: Tag memory Flush is enabled. 1 1 read-write CACHE_HIT_COUNT CACHE_HIT_COUNT XQSPI cache Hits Counter Register 0x8 32 read-only n 0x0 0xFFFFFFFF HIT_COUNT Hits Counter 0 32 read-only CACHE_MISS_COUNT CACHE_MISS_COUNT XQSPI cache Miss Counter Register 0xC 32 read-only n 0x0 0xFFFFFFFF MISS_COUNT Cache miss counter 0 32 read-only CACHE_STAT CACHE_STAT XQSPI cache Status Register 0x10 32 read-only n 0x0 0xFFFFFFFF STAT Tag_flush_busy status. 0x0: Idle 0x1: Busy 0 1 read-only XIP_CTRL0 XIP_CTRL0 XIP Control 0 Register 0xC00 32 read-write n 0x3 0xFFFFFFFF XIP_CFG_CMD XIP configuration read command. 0x03: Read 0x0B: Fast Read 0x3B: Fast Dual Out Read 0x6B: Fast Quad Out Read 0xBB: Fast Dual I/O Read 0xEB: Fast Quad I/O Read All others reserved 0 8 read-write XIP_CTRL1 XIP_CTRL1 XIP Control 1 Register 0xC04 32 read-write n 0x102 0xFFFFFFFF XIP_CFG_ADDR4 XIP configuration 4-Byte Address mode. 0x0: XIP issues 3-Byte Address 0x1: XIP issues 4-Byte SPI Address 7 1 read-write XIP_CFG_CPHA XIP configuration CPHA mode. 0x0: CPHA mode 0 0x1: CPHA mode 1 5 1 read-write XIP_CFG_CPOL XIP configuration CPOL mode. 0x0: CPOL mode 0 0x1: CPOL mode 1 6 1 read-write XIP_CFG_HPME XIP configuration High Performance Mode. 0x0: HP mode disable 0x1: HP mode enable 0 1 read-write XIP_CFG_LE32 XIP configuration 32-bit Little-Endian Arrangement of Read Data. 0x0: Read Data is Big Endian 0x1: Read Data is 32-bit Little Endian 8 1 read-write XIP_CFG_SS XIP configuration slave select . 0x1: slave select 0 0x2: slave select 1 0x4: slave select 2 0x8: slave select 3 All other reserved 1 4 read-write XIP_CTRL2 XIP_CTRL2 XIP Control 2 Register 0xC08 32 read-write n 0xA3 0xFFFFFFFF XIP_CFG_DC Used to configure the number of dummy cycles used by the core for Fast Read, Fast Read Dual Output, Fast Read Quad Ouput. Fast Read Dual I/O: 4 x value + 4 Fast Read Quad I/O: 2 x value + 2 Fast Read Quad Output: 8 x value 8 4 read-write XIP_CFG_HPED Configure the number of dummy cycles necessary to terminate high performance mode. This is used by the core when existing XIP mode after performing high-performance transfers to ensure that FLASH device is not still in HP mode. For Dual mode, this value is multiplied by 4 to get the actual number of dummy cycles. For Quad mode, this value is multiplied by 2 to get the actual number of dummy cycle 12 2 read-write XIP_CFG_HPM XIP Mode Command Byte. This byte is transferred from core to QSPI FLASH memory. It is the value specified by different QSPI FLASH memory vendor to enter into its status register to activate HP mode in dual I/O and Quad I/O access 0 8 read-write XIP_CTRL3 XIP_CTRL3 XIP Control 3 Register 0xC0C 32 read-write n 0x0 0xFFFFFFFF XIP_EN_REQ XIP Enable Request. 0x0: Disable XIP mode 0x1: Enable XIP mode When set to 1’b1, do not access QSPI address space. Wait until XIP_EN_OUT is 1’b1. When set to 1’b0, do not access QSPI address space. Wait until XIP_EN_OUT is 1’b0. 0 1 read-write XIP_SOFT_RST XIP_SOFT_RST XIP Soft Reset Register 0xC28 32 read-write n 0x1 0xFFFFFFFF SOFT_RST Soft reset IP by writing 1’b0, internal logic generates active low reset for one HCLK cycle 0 1 read-write XIP_STAT XIP_STAT XIP Status Register 0xC10 32 read-only n 0x0 0xFFFFFFFF XIP_EN_OUT XIP Enable Status. 0x0: XIP mode is disabled 0x1: XIP mode is enabled 0 1 read-only