Infineon IMC300A_0128 2024.04.29 IMC300A_0128 Cortex-M0 r1p0 little 3 false PPB Cortex-M0 Private Peripheral Block PPB 0x0 0x0 0x1000 registers n AIRCR Application Interrupt and Reset Control Register 0xD0C 32 read-write n 0x0 0x0 ENDIANNESS Data Endianness 15 read-only value1 Little-endian #0 SYSRESETREQ System Reset Request 2 write-only value1 No effect. #0 value2 Requests a system level reset. #1 VECTKEY Register Key 16 15 read-write CCR Configuration and Control Register 0xD14 32 read-write n 0x0 0x0 STKALIGN Stack Alignment 9 read-only UNALIGN_TRP Unaligned Access Traps 3 read-only CPUID CPUID Base Register 0xD00 32 read-write n 0x0 0x0 Architecture Architecture 16 3 read-only value1 ARMv6-M 0xC Implementer Implementer Code 24 7 read-only value1 ARM 0x41 PartNo Part Number of the Processor 4 11 read-only value1 Cortex-M0 0xC20 Revision Revision Number 0 3 read-only value1 Patch 0 0x0 Variant Variant Number 20 3 read-only value1 Revision 0 0x0 ICSR Interrupt Control and State Register 0xD04 32 read-write n 0x0 0x0 ISRPENDING Interrupt Pending Flag 22 read-only value1 Interrupt not pending #0 value2 Interrupt pending. #1 PENDSTCLR SysTick Exception Clear-pending 25 write-only value1 No effect #0 value2 removes the pending state from the SysTick exception. #1 PENDSTSET SysTick Exception Set-pending 26 read-write value1 SysTick exception is not pending 0 value2 SysTick exception is pending. 1 PENDSVCLR PendSV Clear Pending 27 write-only value1 Do not clear. #0 value2 Removes pending state from PendSV exception. #1 PENDSVSET PendSV Set Pending 28 read-write value1 PendSV exception is not pending. #0 value2 PendSV excepton is pending. #1 VECTACTIVE Active Exception Number 0 5 read-only value1 Thread mode 0x00 VECTPENDING Pending Exception Number 12 5 read-only value1 No pending exceptions 0x0 NVIC_ICER IInterrupt Clear-enable Register 0x180 32 read-write n 0x0 0x0 CLRENA Interrupt Node Clear-enable 0 31 read-write value1 Read: Interrupt node disabled. Write: No effect #0 value2 Read: Interrupt node enabled. Write: Disable interrupt node. #1 NVIC_ICPR Interrupt Clear-pending Register 0x280 32 read-write n 0x0 0x0 CLRPEND Interrupt Node Clear-pending 0 31 read-write value1 Interrupt node not pending #0 value2 Interrupt node pending #1 NVIC_IPR0 Interrupt Priority Register 0 0x400 32 read-write n 0x0 0x0 PRI_0 Priority, Byte Offset 0 0 7 read-write PRI_1 Priority, Byte Offset 1 8 7 read-write PRI_2 Priority, Byte Offset 2 16 7 read-write PRI_3 Priority, Byte Offset 3 24 7 read-write NVIC_IPR1 Interrupt Priority Register 1 0x404 32 read-write n 0x0 0x0 PRI_0 Priority, Byte Offset 0 0 7 read-write PRI_1 Priority, Byte Offset 1 8 7 read-write PRI_2 Priority, Byte Offset 2 16 7 read-write PRI_3 Priority, Byte Offset 3 24 7 read-write NVIC_IPR2 Interrupt Priority Register 2 0x408 32 read-write n 0x0 0x0 PRI_0 Priority, Byte Offset 0 0 7 read-write PRI_1 Priority, Byte Offset 1 8 7 read-write PRI_2 Priority, Byte Offset 2 16 7 read-write PRI_3 Priority, Byte Offset 3 24 7 read-write NVIC_IPR3 Interrupt Priority Register 3 0x40C 32 read-write n 0x0 0x0 PRI_0 Priority, Byte Offset 0 0 7 read-write PRI_1 Priority, Byte Offset 1 8 7 read-write PRI_2 Priority, Byte Offset 2 16 7 read-write PRI_3 Priority, Byte Offset 3 24 7 read-write NVIC_IPR4 Interrupt Priority Register 4 0x410 32 read-write n 0x0 0x0 PRI_0 Priority, Byte Offset 0 0 7 read-write PRI_1 Priority, Byte Offset 1 8 7 read-write PRI_2 Priority, Byte Offset 2 16 7 read-write PRI_3 Priority, Byte Offset 3 24 7 read-write NVIC_IPR5 Interrupt Priority Register 5 0x414 32 read-write n 0x0 0x0 PRI_0 Priority, Byte Offset 0 0 7 read-write PRI_1 Priority, Byte Offset 1 8 7 read-write PRI_2 Priority, Byte Offset 2 16 7 read-write PRI_3 Priority, Byte Offset 3 24 7 read-write NVIC_IPR6 Interrupt Priority Register 6 0x418 32 read-write n 0x0 0x0 PRI_0 Priority, Byte Offset 0 0 7 read-write PRI_1 Priority, Byte Offset 1 8 7 read-write PRI_2 Priority, Byte Offset 2 16 7 read-write PRI_3 Priority, Byte Offset 3 24 7 read-write NVIC_IPR7 Interrupt Priority Register 7 0x41C 32 read-write n 0x0 0x0 PRI_0 Priority, Byte Offset 0 0 7 read-write PRI_1 Priority, Byte Offset 1 8 7 read-write PRI_2 Priority, Byte Offset 2 16 7 read-write PRI_3 Priority, Byte Offset 3 24 7 read-write NVIC_ISER Interrupt Set-enable Register 0x100 32 read-write n 0x0 0x0 SETENA Interrupt Node Set-enable 0 31 read-write value1 Read: Interrupt node disabled. Write: No effect. #0 value2 Read: Interrupt node enabled. Write: Enable interrupt node #1 NVIC_ISPR Interrupt Set-pending Register 0x200 32 read-write n 0x0 0x0 SETPEND Interrupt Node Set-pending 0 31 read-write value1 Interrupt node not pending #0 value2 Interrupt node pending #1 SCR System Control Register 0xD10 32 read-write n 0x0 0x0 SEVONPEND Send Event on Pending bit 4 read-write value1 Wakeup only by enabled interrupts or events #0 value2 Wakeup by enabled events and all interrupts #1 SLEEPDEEP Low Power Sleep Mode 2 read-write value1 Sleep #0 value2 Deep sleep #1 SLEEPONEXIT Sleep-on-exit 1 read-write value1 Do not sleep when returning to Thread mode. #0 value2 Enter sleep, or deep sleep, on return from an ISR to Thread mode. #1 SHCSR System Handler Control and State Register 0xD24 32 read-write n 0x0 0x0 SVCALLPENDED SVCall Pending bit 15 read-write value1 SVCall is not pending. #0 value2 SVCall is pending. #1 SHPR2 System Handler Priority Register 2 0xD1C 32 read-write n 0x0 0x0 PRI_11 Priority of System Handler 11 24 7 read-write SHPR3 System Handler Priority Register 3 0xD20 32 read-write n 0x0 0x0 PRI_14 Priority of System Handler 14 16 7 read-write PRI_15 Priority of System Handler 15 24 7 read-write SYST_CALIB SysTick Calibration Value Register 0x1C 32 read-write n 0x0 0x0 NOREF Reference Clock 31 read-only SKEW Clock Skew 30 read-only TENMS 10 Milliseconds 0 23 read-only SYST_CSR SysTick Control and Status Register 0x10 32 read-write n 0x0 0x0 CLKSOURCE Clock Source 2 read-write value1 External clock. #0 value2 Processor clock. #1 COUNTFLAG Counter Flag 16 read-write ENABLE Counter Enable 0 read-write value1 Counter disabled. #0 value2 Counter enabled. #1 TICKINT SysTick Exception Request 1 read-write value1 Counting down to zero does not assert the SysTick exception request. #0 value2 Counting down to zero to assert the SysTick exception request. #1 SYST_CVR SysTick Current Value Register 0x18 32 read-write n 0x0 0x0 CURRENT SysTick Counter Current Value 0 23 read-write SYST_RVR SysTick Reload Value Register 0x14 32 read-write n 0x0 0x0 RELOAD Reload Value 0 23 read-write