Infineon MB9AFB4xL 2024.04.28 MB9AFB4xL 8 32 ADC0 ADC0 Registers ADC0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x4 registers n 0x20 0x1 registers n 0x24 0x1 registers n 0x26 0x2 registers n 0x28 0x2 registers n 0x2C 0x2 registers n 0x30 0x2 registers n 0x34 0x1 registers n 0x38 0x2 registers n 0x3C 0x2 registers n 0x8 0x2 registers n 0xC 0x4 registers n ADC0 25 ADCEN A/D Operation Enable Setup Register 0x3C 16 read-write n 0x0 0x0 ENBL A/D operation enable bit 0 read-write ENBLTIME Basic cycle selection bit 8 7 read-write READY A/D operation enable state bit 1 read-only ADCR A/D Control Register 0x1 8 read-write n 0x0 0x0 CMPIE Conversion result comparison interrupt enable bit 1 read-write CMPIF Conversion result comparison interrupt request bit 5 read-write OVRIE FIFO overrun interrupt enable bit 0 read-write PCIE Priority conversion interrupt enable bit 2 read-write PCIF Priority conversion interrupt request bit 6 read-write SCIE Scan conversion interrupt enable bit 3 read-write SCIF Scan conversion interrupt request bit 7 read-write ADCT Comparison Time Setup Register 0x34 8 read-write n 0x0 0x0 CT Compare clock frequency division ratio setting bits 0 7 read-write ADSR A/D Status Register 0x0 8 read-write n 0x0 0x0 ADSTP A/D conversion forced stop bit 7 read-write FDAS FIFO data placement selection bit 6 read-write PCNS Priority conversion pending flag 2 read-write PCS Priority conversion status flag 1 read-write SCS Scan conversion status flag 0 read-write ADSS0 Sampling Time Selection Register 0 0x2C 8 read-write n 0x0 0x0 TS0 Bit0 of ADSS0 0 read-write TS1 Bit1 of ADSS0 1 read-write TS2 Bit2 of ADSS0 2 read-write TS3 Bit3 of ADSS0 3 read-write TS4 Bit4 of ADSS0 4 read-write TS5 Bit5 of ADSS0 5 read-write TS6 Bit6 of ADSS0 6 read-write TS7 Bit7 of ADSS0 7 read-write ADSS1 Sampling Time Selection Register 1 0x2D 8 read-write n 0x0 0x0 TS10 Bit2 of ADSS1 2 read-write TS11 Bit3 of ADSS1 3 read-write TS12 Bit4 of ADSS1 4 read-write TS13 Bit5 of ADSS1 5 read-write TS14 Bit6 of ADSS1 6 read-write TS15 Bit7 of ADSS1 7 read-write TS8 Bit0 of ADSS1 0 read-write TS9 Bit1 of ADSS1 1 read-write ADSS2 Sampling Time Selection Register 2 0x28 8 read-write n 0x0 0x0 TS16 Bit0 of ADSS2 0 read-write TS17 Bit1 of ADSS2 1 read-write TS18 Bit2 of ADSS2 2 read-write TS19 Bit3 of ADSS2 3 read-write TS20 Bit4 of ADSS2 4 read-write TS21 Bit5 of ADSS2 5 read-write TS22 Bit6 of ADSS2 6 read-write TS23 Bit7 of ADSS2 7 read-write ADSS3 Sampling Time Selection Register 3 0x29 8 read-write n 0x0 0x0 TS24 Bit0 of ADSS3 0 read-write TS25 Bit1 of ADSS3 1 read-write TS26 Bit2 of ADSS3 2 read-write TS27 Bit3 of ADSS3 3 read-write TS28 Bit4 of ADSS3 4 read-write TS29 Bit5 of ADSS3 5 read-write TS30 Bit6 of ADSS3 6 read-write TS31 Bit7 of ADSS3 7 read-write ADST0 Sampling Time Setup Register 0 0x31 8 read-write n 0x0 0x0 ST Sampling time setting bits 0 4 read-write ST0 Sampling time setting bits 0 4 read-write STX0 Sampling time N times setting bits 5 2 read-write ADST1 Sampling Time Setup Register 1 0x30 8 read-write n 0x0 0x0 ST Sampling time setting bits 0 4 read-write ST1 Sampling time setting bits 0 4 read-write STX1 Sampling time N times setting bits 5 2 read-write CMPCR A/D Comparison Control Register 0x24 8 read-write n 0x0 0x0 CCH Comparison mode 0 0 4 read-write CMD Comparison mode 1 5 1 read-write CMD0 Comparison mode 0 5 read-write CMD1 Comparison mode 1 6 read-write CMPEN Conversion result comparison function operation enable bit 7 read-write CMPD A/D Comparison Value Setup Register 0x26 16 read-write n 0x0 0x0 CMAD A/D conversion result value setting bits 6 9 read-write PCCR Priority Conversion Control Register 0x19 8 read-write n 0x0 0x0 ESCE External trigger analog input selection bit 3 read-write PEEN Priority conversion external start enable bit 2 read-write PEMP Priority conversion FIFO empty bit 7 read-only PFCLR Priority conversion FIFO clear bit 4 read-write PFUL Priority conversion FIFO full bit 6 read-only PHEN Priority conversion timer start enable bit 1 read-write POVR Priority conversion overrun flag 5 read-write PSTR Priority conversion start bit 0 read-write PCFD Priority Conversion FIFO Data Register 0x1C 32 read-only n 0x0 0x0 INVL A/D conversion result disable bit 12 read-only PC Conversion input channel bits 0 4 read-only PD Priority conversion result 20 11 read-only RS Scan conversion start factor 8 1 read-only PCIS Priority Conversion Input Selection Register 0x20 8 read-write n 0x0 0x0 P1A Priority level 1 analog input selection 0 2 read-write P2A Priority level 2 analog input selection 3 4 read-write PFNS Priority Conversion FIFO Stage Count Setup Register 0x18 8 read-write n 0x0 0x0 PFS Priority conversion FIFO stage count setting bits 0 1 read-write TEST Test bits 4 1 read-only PRTSL Priority Conversion Timer Trigger Selection Register 0x38 8 read-write n 0x0 0x0 PRTSL Priority conversion timer trigger selection bit 0 3 read-write SCCR Scan Conversion Control Register 0x9 8 read-write n 0x0 0x0 RPT Scan conversion repeat bit 2 read-write SEMP Scan conversion FIFO empty bit 7 read-only SFCLR Scan conversion FIFO clear bit 4 read-write SFUL Scan conversion FIFO full bit 6 read-only SHEN Scan conversion timer start enable bit 1 read-write SOVR Scan conversion overrun flag 5 read-write SSTR Scan conversion start bit 0 read-write SCFD Scan Conversion FIFO Data Register 0xC 32 read-only n 0x0 0x0 CS Conversion input channel bits 0 4 read-only INVL A/D conversion result disable bit 12 read-only RS Scan conversion start factor 8 1 read-only SC Conversion input channel bits 0 4 read-only SD Scan conversion result 20 11 read-only SCIS0 Scan Conversion Input Selection Register 0 0x14 8 read-write n 0x0 0x0 AN0 Bit0 of SCIS0 0 read-write AN1 Bit1 of SCIS0 1 read-write AN2 Bit2 of SCIS0 2 read-write AN3 Bit3 of SCIS0 3 read-write AN4 Bit4 of SCIS0 4 read-write AN5 Bit5 of SCIS0 5 read-write AN6 Bit6 of SCIS0 6 read-write AN7 Bit7 of SCIS0 7 read-write SCIS1 Scan Conversion Input Selection Register 1 0x15 8 read-write n 0x0 0x0 AN10 Bit2 of SCIS1 2 read-write AN11 Bit3 of SCIS1 3 read-write AN12 Bit4 of SCIS1 4 read-write AN13 Bit5 of SCIS1 5 read-write AN14 Bit6 of SCIS1 6 read-write AN15 Bit7 of SCIS1 7 read-write AN8 Bit0 of SCIS1 0 read-write AN9 Bit1 of SCIS1 1 read-write SCIS2 Scan Conversion Input Selection Register 2 0x10 8 read-write n 0x0 0x0 AN16 Bit0 of SCIS2 0 read-write AN17 Bit1 of SCIS2 1 read-write AN18 Bit2 of SCIS2 2 read-write AN19 Bit3 of SCIS2 3 read-write AN20 Bit4 of SCIS2 4 read-write AN21 Bit5 of SCIS2 5 read-write AN22 Bit6 of SCIS2 6 read-write AN23 Bit7 of SCIS2 7 read-write SCIS3 Scan Conversion Input Selection Register 3 0x11 8 read-write n 0x0 0x0 AN24 Bit0 of SCIS3 0 read-write AN25 Bit1 of SCIS3 1 read-write AN26 Bit2 of SCIS3 2 read-write AN27 Bit3 of SCIS3 3 read-write AN28 Bit4 of SCIS3 4 read-write AN29 Bit5 of SCIS3 5 read-write AN30 Bit6 of SCIS3 6 read-write AN31 Bit7 of SCIS3 7 read-write SCTSL Scan Conversion Timer Trigger Selection Register 0x39 8 read-write n 0x0 0x0 SCTSL Scan conversion timer trigger selection bit 0 3 read-write SFNS Scan Conversion FIFO Stage Count Setup Register 0x8 8 read-write n 0x0 0x0 SFS Scan conversion FIFO stage count setting bit 0 3 read-write ADC1 ADC0 Registers ADC0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x4 registers n 0x20 0x1 registers n 0x24 0x1 registers n 0x26 0x2 registers n 0x28 0x2 registers n 0x2C 0x2 registers n 0x30 0x2 registers n 0x34 0x1 registers n 0x38 0x2 registers n 0x3C 0x2 registers n 0x8 0x2 registers n 0xC 0x4 registers n ADC1 26 ADCEN A/D Operation Enable Setup Register 0x3C 16 read-write n 0x0 0x0 ENBL A/D operation enable bit 0 read-write ENBLTIME Basic cycle selection bit 8 7 read-write READY A/D operation enable state bit 1 read-only ADCR A/D Control Register 0x1 8 read-write n 0x0 0x0 CMPIE Conversion result comparison interrupt enable bit 1 read-write CMPIF Conversion result comparison interrupt request bit 5 read-write OVRIE FIFO overrun interrupt enable bit 0 read-write PCIE Priority conversion interrupt enable bit 2 read-write PCIF Priority conversion interrupt request bit 6 read-write SCIE Scan conversion interrupt enable bit 3 read-write SCIF Scan conversion interrupt request bit 7 read-write ADCT Comparison Time Setup Register 0x34 8 read-write n 0x0 0x0 CT Compare clock frequency division ratio setting bits 0 7 read-write ADSR A/D Status Register 0x0 8 read-write n 0x0 0x0 ADSTP A/D conversion forced stop bit 7 read-write FDAS FIFO data placement selection bit 6 read-write PCNS Priority conversion pending flag 2 read-write PCS Priority conversion status flag 1 read-write SCS Scan conversion status flag 0 read-write ADSS0 Sampling Time Selection Register 0 0x2C 8 read-write n 0x0 0x0 TS0 Bit0 of ADSS0 0 read-write TS1 Bit1 of ADSS0 1 read-write TS2 Bit2 of ADSS0 2 read-write TS3 Bit3 of ADSS0 3 read-write TS4 Bit4 of ADSS0 4 read-write TS5 Bit5 of ADSS0 5 read-write TS6 Bit6 of ADSS0 6 read-write TS7 Bit7 of ADSS0 7 read-write ADSS1 Sampling Time Selection Register 1 0x2D 8 read-write n 0x0 0x0 TS10 Bit2 of ADSS1 2 read-write TS11 Bit3 of ADSS1 3 read-write TS12 Bit4 of ADSS1 4 read-write TS13 Bit5 of ADSS1 5 read-write TS14 Bit6 of ADSS1 6 read-write TS15 Bit7 of ADSS1 7 read-write TS8 Bit0 of ADSS1 0 read-write TS9 Bit1 of ADSS1 1 read-write ADSS2 Sampling Time Selection Register 2 0x28 8 read-write n 0x0 0x0 TS16 Bit0 of ADSS2 0 read-write TS17 Bit1 of ADSS2 1 read-write TS18 Bit2 of ADSS2 2 read-write TS19 Bit3 of ADSS2 3 read-write TS20 Bit4 of ADSS2 4 read-write TS21 Bit5 of ADSS2 5 read-write TS22 Bit6 of ADSS2 6 read-write TS23 Bit7 of ADSS2 7 read-write ADSS3 Sampling Time Selection Register 3 0x29 8 read-write n 0x0 0x0 TS24 Bit0 of ADSS3 0 read-write TS25 Bit1 of ADSS3 1 read-write TS26 Bit2 of ADSS3 2 read-write TS27 Bit3 of ADSS3 3 read-write TS28 Bit4 of ADSS3 4 read-write TS29 Bit5 of ADSS3 5 read-write TS30 Bit6 of ADSS3 6 read-write TS31 Bit7 of ADSS3 7 read-write ADST0 Sampling Time Setup Register 0 0x31 8 read-write n 0x0 0x0 ST Sampling time setting bits 0 4 read-write ST0 Sampling time setting bits 0 4 read-write STX0 Sampling time N times setting bits 5 2 read-write ADST1 Sampling Time Setup Register 1 0x30 8 read-write n 0x0 0x0 ST Sampling time setting bits 0 4 read-write ST1 Sampling time setting bits 0 4 read-write STX1 Sampling time N times setting bits 5 2 read-write CMPCR A/D Comparison Control Register 0x24 8 read-write n 0x0 0x0 CCH Comparison mode 0 0 4 read-write CMD Comparison mode 1 5 1 read-write CMD0 Comparison mode 0 5 read-write CMD1 Comparison mode 1 6 read-write CMPEN Conversion result comparison function operation enable bit 7 read-write CMPD A/D Comparison Value Setup Register 0x26 16 read-write n 0x0 0x0 CMAD A/D conversion result value setting bits 6 9 read-write PCCR Priority Conversion Control Register 0x19 8 read-write n 0x0 0x0 ESCE External trigger analog input selection bit 3 read-write PEEN Priority conversion external start enable bit 2 read-write PEMP Priority conversion FIFO empty bit 7 read-only PFCLR Priority conversion FIFO clear bit 4 read-write PFUL Priority conversion FIFO full bit 6 read-only PHEN Priority conversion timer start enable bit 1 read-write POVR Priority conversion overrun flag 5 read-write PSTR Priority conversion start bit 0 read-write PCFD Priority Conversion FIFO Data Register 0x1C 32 read-only n 0x0 0x0 INVL A/D conversion result disable bit 12 read-only PC Conversion input channel bits 0 4 read-only PD Priority conversion result 20 11 read-only RS Scan conversion start factor 8 1 read-only PCIS Priority Conversion Input Selection Register 0x20 8 read-write n 0x0 0x0 P1A Priority level 1 analog input selection 0 2 read-write P2A Priority level 2 analog input selection 3 4 read-write PFNS Priority Conversion FIFO Stage Count Setup Register 0x18 8 read-write n 0x0 0x0 PFS Priority conversion FIFO stage count setting bits 0 1 read-write TEST Test bits 4 1 read-only PRTSL Priority Conversion Timer Trigger Selection Register 0x38 8 read-write n 0x0 0x0 PRTSL Priority conversion timer trigger selection bit 0 3 read-write SCCR Scan Conversion Control Register 0x9 8 read-write n 0x0 0x0 RPT Scan conversion repeat bit 2 read-write SEMP Scan conversion FIFO empty bit 7 read-only SFCLR Scan conversion FIFO clear bit 4 read-write SFUL Scan conversion FIFO full bit 6 read-only SHEN Scan conversion timer start enable bit 1 read-write SOVR Scan conversion overrun flag 5 read-write SSTR Scan conversion start bit 0 read-write SCFD Scan Conversion FIFO Data Register 0xC 32 read-only n 0x0 0x0 CS Conversion input channel bits 0 4 read-only INVL A/D conversion result disable bit 12 read-only RS Scan conversion start factor 8 1 read-only SC Conversion input channel bits 0 4 read-only SD Scan conversion result 20 11 read-only SCIS0 Scan Conversion Input Selection Register 0 0x14 8 read-write n 0x0 0x0 AN0 Bit0 of SCIS0 0 read-write AN1 Bit1 of SCIS0 1 read-write AN2 Bit2 of SCIS0 2 read-write AN3 Bit3 of SCIS0 3 read-write AN4 Bit4 of SCIS0 4 read-write AN5 Bit5 of SCIS0 5 read-write AN6 Bit6 of SCIS0 6 read-write AN7 Bit7 of SCIS0 7 read-write SCIS1 Scan Conversion Input Selection Register 1 0x15 8 read-write n 0x0 0x0 AN10 Bit2 of SCIS1 2 read-write AN11 Bit3 of SCIS1 3 read-write AN12 Bit4 of SCIS1 4 read-write AN13 Bit5 of SCIS1 5 read-write AN14 Bit6 of SCIS1 6 read-write AN15 Bit7 of SCIS1 7 read-write AN8 Bit0 of SCIS1 0 read-write AN9 Bit1 of SCIS1 1 read-write SCIS2 Scan Conversion Input Selection Register 2 0x10 8 read-write n 0x0 0x0 AN16 Bit0 of SCIS2 0 read-write AN17 Bit1 of SCIS2 1 read-write AN18 Bit2 of SCIS2 2 read-write AN19 Bit3 of SCIS2 3 read-write AN20 Bit4 of SCIS2 4 read-write AN21 Bit5 of SCIS2 5 read-write AN22 Bit6 of SCIS2 6 read-write AN23 Bit7 of SCIS2 7 read-write SCIS3 Scan Conversion Input Selection Register 3 0x11 8 read-write n 0x0 0x0 AN24 Bit0 of SCIS3 0 read-write AN25 Bit1 of SCIS3 1 read-write AN26 Bit2 of SCIS3 2 read-write AN27 Bit3 of SCIS3 3 read-write AN28 Bit4 of SCIS3 4 read-write AN29 Bit5 of SCIS3 5 read-write AN30 Bit6 of SCIS3 6 read-write AN31 Bit7 of SCIS3 7 read-write SCTSL Scan Conversion Timer Trigger Selection Register 0x39 8 read-write n 0x0 0x0 SCTSL Scan conversion timer trigger selection bit 0 3 read-write SFNS Scan Conversion FIFO Stage Count Setup Register 0x8 8 read-write n 0x0 0x0 SFS Scan conversion FIFO stage count setting bit 0 3 read-write BT0 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n BTIM0_7 31 PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT1 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT2 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT3 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT4 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT5 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT6 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT7 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BTIOSEL03 Base Timer I/O Select BTIOSEL03 0x0 0x0 0x2 registers n BTSEL0123 I/O Select Register 0x0 16 read-write n 0x0 0x0 SEL01_ I/O select bits for Ch.0/Ch.1 8 3 read-write SEL23_ I/O select bits for Ch.2/Ch.3 12 3 read-write BTIOSEL47 Base Timer I/O Select BTIOSEL47 0x0 0x0 0x2 registers n BTSEL4567 I/O Select Register 0x0 16 read-write n 0x0 0x0 SEL45_ I/O select bits for Ch.4/Ch.5 8 3 read-write SEL67_ I/O select bits for Ch.6/Ch.7 12 3 read-write CRC CRC Registers CRC 0x0 0x0 0x1 registers n 0x4 0x4 registers n 0x4 0x1 registers n 0x8 0x4 registers n 0xC 0x4 registers n CRCCR CRC Control Register 0x0 8 read-write n 0x0 0x0 CRC32 Byte-order setting bit 1 read-write CRCLSF Final XOR control bit 5 read-write CRCLTE CRC result bit-order setting bit 4 read-write FXOR Initialization bit 6 read-write INIT CRC mode selection bit 0 read-write LSBFST CRC result byte-order setting bit 3 read-write LTLEND Bit-order setting bit 2 read-write CRCIN Input Data Register 0x8 32 read-write n 0x0 0x0 D Input data 0 31 read-write CRCINIT Initial Value Register 0x4 32 read-write n 0x0 0x0 D Initial value 0 31 read-write CRCR CRC Register 0xC 32 read-only n 0x0 0x0 D CRC Data 0 31 read-only CRG Clock Unit Registers CRG 0x0 0x0 0x1 registers n 0x10 0x1 registers n 0x14 0x1 registers n 0x18 0x1 registers n 0x1C 0x1 registers n 0x20 0x1 registers n 0x28 0x1 registers n 0x30 0x1 registers n 0x34 0x1 registers n 0x38 0x1 registers n 0x3C 0x1 registers n 0x4 0x1 registers n 0x40 0x2 registers n 0x44 0x1 registers n 0x48 0x2 registers n 0x4C 0x2 registers n 0x50 0x2 registers n 0x54 0x1 registers n 0x60 0x1 registers n 0x64 0x1 registers n 0x68 0x1 registers n 0x8 0x6 registers n CSV 0 OSC_PLL_WC_RTC 24 APBC0_PSR APB0 Prescaler Register 0x14 8 read-write n 0x0 0x0 APBC0 APB0 bus clock frequency division ratio setting bit 0 1 read-write APBC1_PSR APB1 Prescaler Register 0x18 8 read-write n 0x0 0x0 APBC1 APB1 bus clock frequency division ratio setting bit 0 1 read-write APBC1EN APB1 clock enable bit 7 read-write APBC1RST APB1 bus reset control bit 4 read-write APBC2_PSR APB2 Prescaler Register 0x1C 8 read-write n 0x0 0x0 APBC2 APB2 bus clock frequency division ratio setting bit 0 1 read-write APBC2EN APB2 clock enable bit 7 read-write APBC2RST APB2 bus reset control bit 4 read-write BSC_PSR Base Clock Prescaler Register 0x10 8 read-write n 0x0 0x0 BSR Base clock frequency division ratio setting bit 0 2 read-write CSV_CTL CSV control register 0x40 16 read-write n 0x0 0x0 FCD FCS count cycle setting bits 12 2 read-write FCSDE FCS function enable bit 8 read-write FCSRE FCS reset output enable bit 9 read-write MCSVE Main CSV function enable bit 0 read-write SCSVE Sub CSV function enable bit 1 read-write CSV_STR CSV status register 0x44 8 read-only n 0x0 0x0 MCMF Main clock failure detection flag 0 read-only SCMF Sub clock failure detection flag 1 read-only CSW_TMR Clock Stabilization Wait Time Register 0x30 8 read-write n 0x0 0x0 MOWT Main clock stabilization wait time setup bit 0 3 read-write SOWT Sub clock stabilization wait time setup bit 4 2 read-write DBWDT_CTL Debug Break Watchdog Timer Control Register 0x54 8 read-write n 0x0 0x0 DPHWBE HW-WDG debug mode break bit 7 read-write DPSWBE SW-WDG debug mode break bit 5 read-write FCSWD_CTL Frequency detection counter register 0x50 16 read-only n 0x0 0x0 FCSWH_CTL Frequency detection window setting register 0x48 16 read-write n 0x0 0x0 FCSWL_CTL Frequency detection window setting register 0x4C 16 read-write n 0x0 0x0 INT_CLR Interrupt Clear Register 0x68 8 write-only n 0x0 0x0 FCSC Anomalous frequency detection interrupt cause clear bit 5 write-only MCSC Main oscillation stabilization completion interrupt cause clear bit 0 write-only PCSC PLL oscillation stabilization completion interrupt cause clear bit 2 write-only SCSC Sub oscillation stabilization completion interrupt cause clear bit 1 write-only INT_ENR Interrupt Enable Register 0x60 8 read-write n 0x0 0x0 FCSE Anomalous frequency detection interrupt enable bit 5 read-write MCSE Main oscillation stabilization completion interrupt enable bit 0 read-write PCSE PLL oscillation stabilization completion interrupt enable bit 2 read-write SCSE Sub oscillation stabilization completion interrupt enable bit 1 read-write INT_STR Interrupt Status Register 0x64 8 read-only n 0x0 0x0 FCSI Anomalous frequency detection interrupt status bit 5 read-only MCSI Main oscillation stabilization completion interrupt status bit 0 read-only PCSI PLL oscillation stabilization completion interrupt status bit 2 read-only SCSI Sub oscillation stabilization completion interrupt status bit 1 read-only PLL_CTL1 PLL Control Register 1 0x38 8 read-write n 0x0 0x0 PLLK PLL input clock frequency division ratio setting bit 4 3 read-write PLLM PLL VCO clock frequency division ratio setting bit 0 3 read-write PLL_CTL2 PLL Control Register 2 0x3C 8 read-write n 0x0 0x0 PLLN PLL feedback frequency division ratio setting bit 0 5 read-write PSW_TMR PLL Clock Stabilization Wait Time Setup Register 0x34 8 read-write n 0x0 0x0 PINC PLL input clock select bit 4 read-write POWT PLL clock stabilization wait time setup bit 0 2 read-write RST_STR Reset Cause Register 0xC 16 read-only n 0x0 0x0 CSVR Clock failure detection reset flag 6 read-only FCSR Flag for anomalous frequency detection reset 7 read-only HWDG Hardware watchdog reset flag 5 read-only HWDT Hardware watchdog reset flag 5 read-only INITX INITX pin input reset flag 1 read-only PONR Power-on reset/low-voltage detection reset flag 0 read-only SRST Software reset flag 8 read-only SWDG Software watchdog reset flag 4 read-only SWDT Software watchdog reset flag 4 read-only SCM_CTL System Clock Mode Control Register 0x0 8 read-write n 0x0 0x0 MOSCE Main clock oscillation enable bit 1 read-write PLLE PLL oscillation enable bit 4 read-write RCS Master clock switch control bits 5 2 read-write SOSCE Sub clock oscillation enable bit 3 read-write SCM_STR System Clock Mode Status Register 0x4 8 read-only n 0x0 0x0 MORDY Main clock oscillation stable bit 1 read-only PLRDY PLL oscillation stable bit 4 read-only RCM Master clock selection bits 5 2 read-only SORDY Sub clock oscillation stable bit 3 read-only STB_CTL Standby Mode Control Register 0x8 32 read-write n 0x0 0x0 DSTM Deep standby mode select bit 2 read-write KEY Standby mode control write control bit 16 15 read-write SPL Standby pin level setting bit 4 read-write STM Standby mode selection bit 0 1 read-write SWC_PSR Software Watchdog Clock Prescaler Register 0x20 8 read-write n 0x0 0x0 SWDS Software watchdog clock frequency division ratio setting bit 0 1 read-write TESTB TEST bit 7 read-write TTC_PSR Trace Clock Prescaler Register 0x28 8 read-write n 0x0 0x0 TTC Trace clock frequency division ratio setting bit 0 1 read-write CRTRIM CR Trimming Registers CRTRIM 0x0 0x0 0x1 registers n 0x4 0x2 registers n 0xC 0x4 registers n MCR_FTRM High-speed CR oscillation Frequency Trimming Register 0x4 16 read-write n 0x0 0x0 TRD Frequency trimming setup bits 0 9 read-write MCR_PSR High-speed CR oscillation Frequency Division Setup Register 0x0 8 read-write n 0x0 0x0 CSR High-speed CR oscillation frequency division ratio setting bits 0 1 read-write MCR_RLR High-Speed CR Oscillation Register Write-Protect Register 0xC 32 read-write n 0x0 0x0 TRMLCK Register write-protect bits 0 31 read-write DMAC DMAC Registers DMAC 0x0 0x0 0x4 registers n 0x10 0x80 registers n DMAC0 38 DMAC1 39 DMAC2 40 DMAC3 41 DMAC4 42 DMAC5 43 DMAC6 44 DMAC7 45 DMACA0 Configuration A Register 0x10 32 read-write n 0x0 0x0 BC Block Count 16 3 read-write EB Enable bit (individual-channel operation enable bit) 31 read-write IS Input Select 23 5 read-write PB Pause bit (individual-channel pause bit) 30 read-write ST Software Trigger 29 read-write TC Transfer Count 0 15 read-write DMACA1 Configuration A Register 1 0x20 read-write n 0x0 0x0 DMACA2 Configuration A Register 2 0x30 read-write n 0x0 0x0 DMACA3 Configuration A Register 3 0x40 read-write n 0x0 0x0 DMACA4 Configuration A Register 4 0x50 read-write n 0x0 0x0 DMACA5 Configuration A Register 5 0x60 read-write n 0x0 0x0 DMACA6 Configuration A Register 6 0x70 read-write n 0x0 0x0 DMACA7 Configuration A Register 7 0x80 read-write n 0x0 0x0 DMACB0 Configuration B Register 0x14 32 read-write n 0x0 0x0 CI Completion Interrupt (successful transfer completion interrupt enable) 19 read-write EI Error Interrupt (unsuccessful transfer completion interrupt enable) 20 read-write EM Enable bit Mask (EB bit clear mask) 0 read-write FD Fixed Destination 24 read-write FS Fixed Source 25 read-write MS Mode Select 28 1 read-write RC Reload Count (BC/TC reload) 23 read-write RD Reload Destination 21 read-write RS Reload Source 22 read-write SS Stop Status (stop status notification) 16 2 read-write TW Transfer Width 26 1 read-write DMACB1 Configuration B Register 1 0x24 read-write n 0x0 0x0 DMACB2 Configuration B Register 2 0x34 read-write n 0x0 0x0 DMACB3 Configuration B Register 3 0x44 read-write n 0x0 0x0 DMACB4 Configuration B Register 4 0x54 read-write n 0x0 0x0 DMACB5 Configuration B Register 5 0x64 read-write n 0x0 0x0 DMACB6 Configuration B Register 6 0x74 read-write n 0x0 0x0 DMACB7 Configuration B Register 7 0x84 read-write n 0x0 0x0 DMACDA0 Transfer Destination Address Register 0x1C 32 read-write n 0x0 0x0 DMACDA1 Transfer Destination Address Register 1 0x2C read-write n 0x0 0x0 DMACDA2 Transfer Destination Address Register 2 0x3C read-write n 0x0 0x0 DMACDA3 Transfer Destination Address Register 3 0x4C read-write n 0x0 0x0 DMACDA4 Transfer Destination Address Register 4 0x5C read-write n 0x0 0x0 DMACDA5 Transfer Destination Address Register 5 0x6C read-write n 0x0 0x0 DMACDA6 Transfer Destination Address Register 6 0x7C read-write n 0x0 0x0 DMACDA7 Transfer Destination Address Register 7 0x8C read-write n 0x0 0x0 DMACR Entire DMAC Configuration Register 0x0 32 read-write n 0x0 0x0 DE DMA Enable (all-channel operation enable bit) 31 read-write DH DMA Halt (All-channel pause bit) 24 3 read-write DS DMA Stop 30 read-write PR Priority Rotation 28 read-write DMACSA0 Transfer Source Address Register 0x18 32 read-write n 0x0 0x0 DMACSA1 Transfer Source Address Register 1 0x28 read-write n 0x0 0x0 DMACSA2 Transfer Source Address Register 2 0x38 read-write n 0x0 0x0 DMACSA3 Transfer Source Address Register 3 0x48 read-write n 0x0 0x0 DMACSA4 Transfer Source Address Register 4 0x58 read-write n 0x0 0x0 DMACSA5 Transfer Source Address Register 5 0x68 read-write n 0x0 0x0 DMACSA6 Transfer Source Address Register 6 0x78 read-write n 0x0 0x0 DMACSA7 Transfer Source Address Register 7 0x88 read-write n 0x0 0x0 DS Low Power Consumption Mode DS 0x0 0x0 0x1 registers n 0x4 0x1 registers n 0x700 0x1 registers n 0x704 0x1 registers n 0x708 0x2 registers n 0x70C 0x2 registers n 0x710 0x1 registers n 0x714 0x1 registers n 0x800 0x16 registers n BUR01 Backup Registers from 1 0x800 8 read-write n 0x0 0x0 BUR02 Backup Registers from 2 0x801 8 read-write n 0x0 0x0 BUR03 Backup Registers from 3 0x802 8 read-write n 0x0 0x0 BUR04 Backup Registers from 4 0x803 8 read-write n 0x0 0x0 BUR05 Backup Registers from 5 0x804 8 read-write n 0x0 0x0 BUR06 Backup Registers from 6 0x805 8 read-write n 0x0 0x0 BUR07 Backup Registers from 7 0x806 8 read-write n 0x0 0x0 BUR08 Backup Registers from 8 0x807 8 read-write n 0x0 0x0 BUR09 Backup Registers from 9 0x808 8 read-write n 0x0 0x0 BUR10 Backup Registers from 10 0x809 8 read-write n 0x0 0x0 BUR11 Backup Registers from 11 0x80A 8 read-write n 0x0 0x0 BUR12 Backup Registers from 12 0x80B 8 read-write n 0x0 0x0 BUR13 Backup Registers from 13 0x80C 8 read-write n 0x0 0x0 BUR14 Backup Registers from 14 0x80D 8 read-write n 0x0 0x0 BUR15 Backup Registers from 15 0x80E 8 read-write n 0x0 0x0 BUR16 Backup Registers from 16 0x80F 8 read-write n 0x0 0x0 DSRAMR Deep Standby RAM Retention Register 0x714 8 read-write n 0x0 0x0 SRAMR On-chip SRAM retention control bits 0 1 read-write PMD_CTL RTC Mode Control Register 0x700 8 read-write n 0x0 0x0 RTCE RTC mode control bit 0 read-write RCK_CTL Sub Clock Control Register 0x4 8 read-write n 0x0 0x0 CECCKE CEC clock control bit 1 read-write RTCCKE RTC clock control bit 0 read-write REG_CTL Sub Oscillation Circuit Power Supply Control Register 0x0 8 read-write n 0x0 0x0 ISUBSEL Sub oscillation circuit current setting bits 1 1 read-write WIER Deep Standby Return Enable Register 0x70C 16 read-write n 0x0 0x0 WCEC0E HDMI-CEC/ Remote Control Reception ch.0 interrupt return enable bit 8 read-write WCEC1E HDMI-CEC/ Remote Control Reception ch.1 interrupt return enable bit 9 read-write WLVDE LVD interrupt return enable bit 1 read-write WRTCE RTC interrupt return enable bit 0 read-write WUI1E WKUP pin input return enable bit 1 3 read-write WUI2E WKUP pin input return enable bit 2 4 read-write WUI3E WKUP pin input return enable bit 3 5 read-write WIFSR Deep Standby Return Cause Register 2 0x708 16 read-only n 0x0 0x0 WCEC0I CEC ch.0 interrupt return bit 8 read-only WCEC1I CEC ch.1 interrupt return bit 9 read-only WLVDI LVD interrupt return bit 1 read-only WRTCI RTC interrupt return bit 0 read-only WUI0 WKUP pin input return bit 0 2 read-only WUI1 WKUP pin input return bit 1 3 read-only WUI2 WKUP pin input return bit 2 4 read-only WUI3 WKUP pin input return bit 3 5 read-only WILVR WKUP Pin Input Level Register 0x710 8 read-write n 0x0 0x0 WUI1LV WKUP pin input level select bit 1 0 read-write WUI2LV WKUP pin input level select bit 2 1 read-write WUI3LV WKUP pin input level select bit 3 2 read-write WRFSR Deep Standby Return Cause Register 1 0x704 8 read-write n 0x0 0x0 WINITX INITX pin input reset return bit 0 read-write WLVDH Low-voltage detection reset return bit 1 read-write DTIM Dual Timer DTIM 0x0 0x0 0x1C registers n 0x20 0x1C registers n DTIM_QDU 6 TIMER1BGLOAD Background Load Register 0x18 32 read-write n 0x0 0x0 TIMER1CONTROL Control Register 0x8 32 read-write n 0x0 0x0 IntEnable Interrupt enable bit 5 read-write OneShot One-shot mode bit 0 read-write TimerEn Enable bit 7 read-write TimerMode Mode bit 6 read-write TimerPre Prescale bits 2 1 read-write TimerSize Counter size bit 1 read-write TIMER1INTCLR Interrupt Clear Register 0xC 32 write-only n 0x0 0x0 TIMER1LOAD Load Register DualTimer1 0x0 32 read-write n 0x0 0x0 TIMER1MIS Masked Interrupt Status Register 0x14 32 read-only n 0x0 0x0 TIMER1MIS Masked Interrupt Status bit 0 read-only TIMER1RIS Interrupt Status Register 0x10 32 read-only n 0x0 0x0 TIMER1RIS Interrupt Status Register bit 0 read-only TIMER1VALUE Value Register 0x4 32 read-only n 0x0 0x0 TIMER2BGLOAD Background Load Register 0x38 read-write n 0x0 0x0 TIMER2CONTROL Control Register 0x28 read-write n 0x0 0x0 TIMER2INTCLR Interrupt Clear Register 0x2C read-write n 0x0 0x0 TIMER2LOAD Load Register 0x20 read-write n 0x0 0x0 TIMER2MIS Masked Interrupt Status Register 0x34 read-write n 0x0 0x0 TIMER2RIS Interrupt Status Register 0x30 read-write n 0x0 0x0 TIMER2VALUE Value Register 0x24 read-write n 0x0 0x0 EXTI External Interrupt and NMI Control EXTI 0x0 0x0 0x2 registers n 0x14 0x1 registers n 0x18 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x4 registers n EXTINT0_7 4 EXTINT8_15 5 EICL External Interrupt Clear Register 0x8 16 read-write n 0x0 0x0 ECL0 Bit0 of EICL 0 read-write ECL1 Bit1 of EICL 1 read-write ECL15 Bit15 of EICL 15 read-write ECL2 Bit2 of EICL 2 read-write ECL3 Bit3 of EICL 3 read-write ECL4 Bit4 of EICL 4 read-write ECL5 Bit5 of EICL 5 read-write ECL6 Bit6 of EICL 6 read-write EIRR External Interrupt Request Register 0x4 16 read-only n 0x0 0x0 ER0 Bit0 of EIRR 0 read-only ER1 Bit1 of EIRR 1 read-only ER15 Bit15 of EIRR 15 read-only ER2 Bit2 of EIRR 2 read-only ER3 Bit3 of EIRR 3 read-only ER4 Bit4 of EIRR 4 read-only ER5 Bit5 of EIRR 5 read-only ER6 Bit6 of EIRR 6 read-only ELVR External Interrupt Level Register 0xC 32 read-write n 0x0 0x0 LA0 Bit0 of ELVR 0 read-write LA1 Bit2 of ELVR 2 read-write LA15 Bit30 of ELVR 30 read-write LA2 Bit4 of ELVR 4 read-write LA3 Bit6 of ELVR 6 read-write LA4 Bit8 of ELVR 8 read-write LA5 Bit10 of ELVR 10 read-write LA6 Bit12 of ELVR 12 read-write LB0 Bit1 of ELVR 1 read-write LB1 Bit3 of ELVR 3 read-write LB15 Bit31 of ELVR 31 read-write LB2 Bit5 of ELVR 5 read-write LB3 Bit7 of ELVR 7 read-write LB4 Bit9 of ELVR 9 read-write LB5 Bit11 of ELVR 11 read-write LB6 Bit13 of ELVR 13 read-write ENIR Enable Interrupt Request Register 0x0 16 read-write n 0x0 0x0 EN0 Bit0 of ENIR 0 read-write EN1 Bit1 of ENIR 1 read-write EN15 Bit15 of ENIR 15 read-write EN2 Bit2 of ENIR 2 read-write EN3 Bit3 of ENIR 3 read-write EN4 Bit4 of ENIR 4 read-write EN5 Bit5 of ENIR 5 read-write EN6 Bit6 of ENIR 6 read-write NMICL Non Maskable Interrupt Clear Register 0x18 8 read-write n 0x0 0x0 NCL NMI interrupt cause clear bit 0 read-write NMIRR Non Maskable Interrupt Request Register 0x14 8 read-only n 0x0 0x0 NR NMI interrupt request detection bit 0 read-only FLASH_IF Flash Memory FLASH_IF 0x0 0x100 0x4 registers n 0x20 0xC registers n 0x4 0x8 registers n CRTRMM CR Trimming Data Mirror Register 0x100 32 read-only n 0x0 0x0 TRMM CR Trimming Data Mirror 0 9 read-only FICLR Flash Interrupt Clear Register 0x28 32 write-only n 0x0 0x0 HANGC HANG Interrupt Clear 1 read-write RDYC RDY Interrupt Clear 0 read-write FICR Flash Interrupt Control Register 0x20 32 read-write n 0x0 0x0 HANGIE HANG Interrupt Enable 1 read-write RDYIE RDY Interrupt Enable 0 read-write FISR Flash Interrupt Status Register 0x24 32 read-write n 0x0 0x0 HANGIF HANG Interrupt Flag 1 read-write RDYIF RDY Interrupt Flag 0 read-write FRWTR Flash Read Wait Register 0x4 32 read-write n 0x0 0x0 RWT Read Wait Cycle 0 1 read-write FSTR Flash Status Register 0x8 32 read-only n 0x0 0x0 CERS Flash Chip Erase Status 2 read-only ESPS Flash Erase Suspend Status 3 read-only HNG Flash Hang flag 1 read-only PGMS Flash Program Status 5 read-only RDY Flash Rdy 0 read-only SERS Flash Sector Erase Status 4 read-only GPIO General-purpose I/O ports GPIO 0x0 0x0 0x740 registers n ADE Analog input setting register 0x500 32 read-write n 0x0 0x0 AN0 Bit0 of ADE 0 read-write AN1 Bit1 of ADE 1 read-write AN16 Bit16 of ADE 16 read-write AN17 Bit17 of ADE 17 read-write AN18 Bit18 of ADE 18 read-write AN2 Bit2 of ADE 2 read-write AN3 Bit3 of ADE 3 read-write AN4 Bit4 of ADE 4 read-write AN5 Bit5 of ADE 5 read-write AN7 Bit7 of ADE 7 read-write AN8 Bit8 of ADE 8 read-write AN9 Bit9 of ADE 9 read-write DDR0 Port input/output direction setting register 0 0x200 32 read-write n 0x0 0x0 P0 Bit0 of DDR0 0 read-write P1 Bit1 of DDR0 1 read-write P2 Bit2 of DDR0 2 read-write P3 Bit3 of DDR0 3 read-write P4 Bit4 of DDR0 4 read-write PA Bit10 of DDR0 10 read-write PB Bit11 of DDR0 11 read-write PC Bit12 of DDR0 12 read-write PD Bit13 of DDR0 13 read-write PE Bit14 of DDR0 14 read-write PF Bit15 of DDR0 15 read-write DDR1 Port input/output direction setting register 1 0x204 read-write n 0x0 0x0 DDR2 Port input/output direction setting register 2 0x208 read-write n 0x0 0x0 DDR3 Port input/output direction setting register 3 0x20C read-write n 0x0 0x0 DDR4 Port input/output direction setting register 4 0x210 read-write n 0x0 0x0 DDR5 Port input/output direction setting register 5 0x214 read-write n 0x0 0x0 DDR6 Port input/output direction setting register 6 0x218 read-write n 0x0 0x0 DDR8 Port input/output direction setting register 8 0x220 read-write n 0x0 0x0 DDRE Port input/output direction setting register E 0x238 read-write n 0x0 0x0 EPFR00 Extended pin function setting register 00 0x600 32 read-write n 0x0 0x0 CROUTE Internal high-speed CR oscillation output function select bit 1 1 read-write JTAGEN0B JTAG function select bit0 16 read-write JTAGEN1S JTAG function select bit1 17 read-write NMIS NMIX function select bit 0 read-write RTCCOE RTC clock output select bit 4 1 read-write SUBOUTE Sub clock divide output function select bit 6 1 read-write USBP0E USBch0 function select bit 9 read-write EPFR04 Extended pin function setting register 04 0x610 32 read-write n 0x0 0x0 TIOA0E TIOA0 output select bit 2 1 read-write TIOA1E TIOA1E output select bit 10 1 read-write TIOA1S TIOA1 input select bit 8 1 read-write TIOA2E TIOA2 output select bit 18 1 read-write TIOA3E TIOA3E output select bit 26 1 read-write TIOA3S TIOA3 input select bit 24 1 read-write TIOB0S TIOB0 input select bit 4 2 read-write TIOB1S TIOB1 input select bit 12 1 read-write TIOB2S TIOB2 input select bit 20 1 read-write TIOB3S TIOB3 input select bit 28 1 read-write EPFR05 Extended pin function setting register 05 0x614 32 read-write n 0x0 0x0 TIOA4E TIOA4 output select bit 2 1 read-write TIOA5E TIOA5E output select bit 10 1 read-write TIOA5S TIOA5 input select bit 8 1 read-write TIOA6E TIOA6 output select bit 18 1 read-write TIOA7E TIOA7E output select bit 26 1 read-write TIOA7S TIOA7 input select bit 24 1 read-write TIOB4S TIOB4 input select bit 4 1 read-write TIOB5S TIOB5 input select bit 12 1 read-write TIOB6S TIOB6 input select bit 20 1 read-write TIOB7S TIOB7 input select Bit 28 1 read-write EPFR06 Extended pin function setting register 06 0x618 32 read-write n 0x0 0x0 EINT00S External interrupt 0 input select bit 0 1 read-write EINT01S External interrupt 1 input select bit 2 1 read-write EINT02S External interrupt 2 input select bit 4 1 read-write EINT03S External interrupt 3 input select bit 6 1 read-write EINT04S External interrupt 4 input select bit 8 1 read-write EINT05S External interrupt 5 input select bit 10 1 read-write EINT06S External interrupt 6 input select bit 12 1 read-write EINT15S External interrupt 15 input select bit 30 1 read-write EPFR07 Extended pin function setting register 07 0x61C 32 read-write n 0x0 0x0 SCK0B SCK0 input/output select bit 8 1 read-write SCK1B SCK1 input/output select bit 14 1 read-write SCK2B SCK2 input/output select bit 20 1 read-write SCK3B SCK3 input/output select bit 26 1 read-write SIN0S SIN0S input select bit 4 1 read-write SIN1S SIN1S input select bit 10 1 read-write SIN2S SIN2S input select bit 16 1 read-write SIN3S SIN3S input select bit 22 1 read-write SOT0B SOT0B input/output select bit 6 1 read-write SOT1B SCK1B input/output select bit 12 1 read-write SOT2B SOT2B input/output select bit 18 1 read-write SOT3B SOT3B input/output select bit 24 1 read-write EPFR08 Extended pin function setting register 08 0x620 32 read-write n 0x0 0x0 SCK4B SCK4 input/output select bit 8 1 read-write SCK5B SCK5 input/output select bit 14 1 read-write SCK6B SCK6 input/output select bit 20 1 read-write SCK7B SCK7 input/output select bit 26 1 read-write SIN4S SIN4S input select bit 4 1 read-write SIN5S SIN5S input select bit 10 1 read-write SIN6S SIN6S input select bit 16 1 read-write SIN7S SIN7S input select bit 22 1 read-write SOT4B SOT4B input/output select bit 6 1 read-write SOT5B SOT5B input/output select bit 12 1 read-write SOT6B SOT6B input/output select bit 18 1 read-write SOT7B SOT7B input/output select bit 24 1 read-write EPFR09 Extended pin function setting register 09 0x624 32 read-write n 0x0 0x0 ADTRG0S ADTRG0 input select bit 12 3 read-write ADTRG1S ADTRG1 input select bit 16 3 read-write EPFR14 Extended pin function setting register 14 0x638 32 read-write n 0x0 0x0 CEC0B CEC0 Input/Output Select bit 30 read-write CEC1B CEC1 Input/Output Select bit 31 read-write PCR0 Pull-up Setting Register 0 0x100 read-write n 0x0 0x0 PCR1 Pull-up Setting Register 1 0x104 read-write n 0x0 0x0 PCR2 Pull-up Setting Register 2 0x108 read-write n 0x0 0x0 PCR3 Pull-up Setting Register 3 0x10C read-write n 0x0 0x0 PCR4 Pull-up Setting Register 4 0x110 read-write n 0x0 0x0 PCR5 Pull-up Setting Register 5 0x114 read-write n 0x0 0x0 PCR6 Pull-up Setting Register 6 0x118 read-write n 0x0 0x0 PCRE Pull-up Setting Register E 0x138 read-write n 0x0 0x0 PDIR0 Port input data register 0 0x300 read-write n 0x0 0x0 PDIR1 Port input data register 1 0x304 read-write n 0x0 0x0 PDIR2 Port input data register 2 0x308 read-write n 0x0 0x0 PDIR3 Port input data register 3 0x30C read-write n 0x0 0x0 PDIR4 Port input data register 4 0x310 read-write n 0x0 0x0 PDIR5 Port input data register 5 0x314 read-write n 0x0 0x0 PDIR6 Port input data register 6 0x318 read-write n 0x0 0x0 PDIR8 Port input data register 8 0x320 read-write n 0x0 0x0 PDIRE Port input data register E 0x338 read-write n 0x0 0x0 PDOR0 Port output data register 0 0x400 read-write n 0x0 0x0 PDOR1 Port output data register 1 0x404 read-write n 0x0 0x0 PDOR2 Port output data register 2 0x408 read-write n 0x0 0x0 PDOR3 Port output data register 3 0x40C read-write n 0x0 0x0 PDOR4 Port output data register 4 0x410 read-write n 0x0 0x0 PDOR5 Port output data register 5 0x414 read-write n 0x0 0x0 PDOR6 Port output data register 6 0x418 read-write n 0x0 0x0 PDOR8 Port output data register 8 0x420 read-write n 0x0 0x0 PDORE Port output data register E 0x438 read-write n 0x0 0x0 PFR0 Port function setting register 0 0x0 32 read-write n 0x0 0x0 P0 Bit0 of PFR0 0 read-write P1 Bit1 of PFR0 1 read-write P2 Bit2 of PFR0 2 read-write P3 Bit3 of PFR0 3 read-write P4 Bit4 of PFR0 4 read-write PA Bit10 of PFR0 10 read-write PB Bit11 of PFR0 11 read-write PC Bit12 of PFR0 12 read-write PD Bit13 of PFR0 13 read-write PE Bit14 of PFR0 14 read-write PF Bit15 of PFR0 15 read-write PFR1 Port function setting register 1 0x4 32 read-write n 0x0 0x0 P0 Bit0 of PFR1 0 read-write P1 Bit1 of PFR1 1 read-write P2 Bit2 of PFR1 2 read-write P3 Bit3 of PFR1 3 read-write P4 Bit4 of PFR1 4 read-write P5 Bit5 of PFR1 5 read-write P7 Bit7 of PFR1 7 read-write P8 Bit8 of PFR1 8 read-write P9 Bit9 of PFR1 9 read-write PFR2 Port function setting register 2 0x8 32 read-write n 0x0 0x0 P1 Bit1 of PFR2 1 read-write P2 Bit2 of PFR2 2 read-write P3 Bit3 of PFR2 3 read-write PFR3 Port function setting register 3 0xC 32 read-write n 0x0 0x0 P0 Bit0 of PFR3 0 read-write P1 Bit1 of PFR3 1 read-write P2 Bit2 of PFR3 2 read-write P3 Bit3 of PFR3 3 read-write P9 Bit9 of PFR3 9 read-write PA Bit10 of PFR3 10 read-write PB Bit11 of PFR3 11 read-write PC Bit12 of PFR3 12 read-write PD Bit13 of PFR3 13 read-write PE Bit14 of PFR3 14 read-write PF Bit15 of PFR3 15 read-write PFR4 Port function setting register 4 0x10 32 read-write n 0x0 0x0 P6 Bit6 of PFR4 6 read-write P7 Bit7 of PFR4 7 read-write P9 Bit9 of PFR4 9 read-write PA Bit10 of PFR4 10 read-write PB Bit11 of PFR4 11 read-write PC Bit12 of PFR4 12 read-write PD Bit13 of PFR4 13 read-write PE Bit14 of PFR4 14 read-write PFR5 Port function setting register 5 0x14 32 read-write n 0x0 0x0 P0 Bit0 of PFR5 0 read-write P1 Bit1 of PFR5 1 read-write P2 Bit2 of PFR5 2 read-write PFR6 Port function setting register 6 0x18 32 read-write n 0x0 0x0 P0 Bit0 of PFR6 0 read-write P1 Bit1 of PFR6 1 read-write P2 Bit2 of PFR6 2 read-write PFR8 Port function setting register 8 0x20 32 read-write n 0x0 0x0 P0 Bit0 of PFR8 0 read-write P1 Bit1 of PFR8 1 read-write PFRE Port function setting register E 0x38 32 read-write n 0x0 0x0 P0 Bit0 of PFRE 0 read-write P2 Bit2 of PFRE 2 read-write P3 Bit3 of PFRE 3 read-write PZR0 Port Pseudo Open Drain Setting Register 0 0x700 32 read-write n 0x0 0x0 PA Bit10 of PZR0 10 read-write PB Bit11 of PZR0 11 read-write PC Bit12 of PZR0 12 read-write PZR4 Port Pseudo Open Drain Setting Register 4 0x710 32 read-write n 0x0 0x0 PC Bit12 of PZR4 12 read-write PD Bit13 of PZR4 13 read-write PE Bit14 of PZR4 14 read-write PZR6 Port Pseudo Open Drain Setting Register 6 0x718 32 read-write n 0x0 0x0 P0 Bit0 of PZR6 0 read-write SPSR Special port setting register 0x580 32 read-write n 0x0 0x0 MAINXC Main clock(oscillation) pin setting bit 2 1 read-write SUBXC Sub clock(oscillation) pin setting bit 0 1 read-write USB0C USBch0 pin setting bit 4 read-write HDMICEC0 HDMI-CEC ch.0 HDMICEC0 0x0 0x0 0x1 registers n 0x4 0x1 registers n 0x40 0x2 registers n 0x44 0x2 registers n 0x49 0x1 registers n 0x4C 0x2 registers n 0x50 0x2 registers n 0x54 0x2 registers n 0x58 0x2 registers n 0x5C 0x2 registers n 0x61 0x1 registers n 0x64 0x2 registers n 0x8 0x1 registers n 0xC 0x1 registers n HDMICEC0 36 RCADR1 Device Address Setting Register 1 0x4D 8 read-write n 0x0 0x0 RCADR1 Device Address 1 0 4 read-write RCADR2 Device Address Setting Register 2 0x4C 8 read-write n 0x0 0x0 RCADR2 Device Address 2 0 4 read-write RCCKD Clock Division Setting Register 0x58 16 read-write n 0x0 0x0 CKDIV Operating clock division setting bits 0 11 read-write CKSEL Operating clock selection bit 12 read-write RCCR Reception Control Register 0x41 8 read-write n 0x0 0x0 ADRCE Address comparison enable bit 3 read-write EN Operation enable bit 0 read-write MOD0 Operation mode setting bits 1 read-write MOD1 Operation mode setting bits 2 read-write THSEL Threshold selection bit 7 read-write RCDAHW H Width Setting Register A 0x44 8 read-write n 0x0 0x0 RCDAHW H Width Setting A 0 7 read-write RCDBHW H Width Setting Register B 0x49 8 read-write n 0x0 0x0 RCDBHW H Width Setting B 0 7 read-write RCDTHH Data Save Register (High-High) 0x51 8 read-only n 0x0 0x0 RCDTHH RCDTHH 0 7 read-only RCDTHL Data Save Register (High-Low) 0x50 8 read-only n 0x0 0x0 RCDTHL RCDTHL 0 7 read-only RCDTLH Data Save Register (Low-High) 0x55 8 read-only n 0x0 0x0 RCDTLH RCDTLH 0 7 read-only RCDTLL Data Save Register (Low-Low) 0x54 8 read-only n 0x0 0x0 RCDTLL RCDTLL 0 7 read-only RCLE Data Bit Width Violation Control Register 0x61 8 read-write n 0x0 0x0 EPE Error pulse output enable bit 3 read-write LEL Maximum data bit width violation detection flag bit 1 read-write LELE Maximum data bit width violation detection enable bit 5 read-write LELIE Maximum data bit width violation interrupt enable bit 7 read-write LES Minimum data bit width violation detection flag bit 0 read-write LESE Minimum data bit width violation detection enable bit 4 read-write LESIE Minimum data bit width violation interrupt enable bit 6 read-write RCLELW Maximum Data Bit Width Setting Register 0x65 8 read-write n 0x0 0x0 RCLELW Maximum data bit width setting bits 0 7 read-write RCLESW Minimum Data Bit Width Setting Register 0x64 8 read-write n 0x0 0x0 RCLESW Minimum data bit width setting bits 0 7 read-write RCRC Repeat Code Interrupt Control Register 0x5D 8 read-write n 0x0 0x0 RC Repeat code detection flag bit 0 read-write RCIE Repeat Code Interrupt enable bit 4 read-write RCRHW Repeat Code H Width Setting Register 0x5C 8 read-write n 0x0 0x0 RCRHW Repeat code H width setting bits 0 7 read-write RCSHW Start Bit H Width Setting Register 0x45 8 read-write n 0x0 0x0 RCSHW Start Bit H Width Setting 0 7 read-write RCST Reception Interrupt Control Register 0x40 8 read-write n 0x0 0x0 ACK ACK: ACK detection bit 2 read-write ACKIE ACK interrupt enable bit 6 read-write EOM EOM detection bit 1 read-write OVF Counter overflow detection bit 0 read-write OVFIE Counter overflow interrupt enable bit 5 read-write OVFSEL Counter overflow detection condition setting bit 4 read-write ST Start bit detection bit 3 read-write STIE Start bit interrupt enable bit 7 read-write SFREE Signal Free Time Setting Register 0xC 8 read-write n 0x0 0x0 SFREE Signal free time setting bits 0 3 read-write TXCTRL Transmission Control Register 0x0 8 read-write n 0x0 0x0 EOM EOM setting bit 3 read-write IBREN Bus error detection interrupt enable bit 5 read-write ITSTEN transmission status interrupt enable bit 4 read-write START START setting bit 2 read-write TXEN Transmission operation enable bit 0 read-write TXDATA Transmission Data Register 0x4 8 read-write n 0x0 0x0 TXDATA Transmission Data 0 7 read-write TXSTS Transmission Status Register 0x8 8 read-write n 0x0 0x0 ACKSV ACK cycle value bit 0 read-write IBR Bus error detection interrupt request bit 5 read-write ITST Transmission status interrupt request bit 4 read-write HDMICEC1 HDMI-CEC ch.0 HDMICEC0 0x0 0x0 0x1 registers n 0x4 0x1 registers n 0x40 0x2 registers n 0x44 0x2 registers n 0x49 0x1 registers n 0x4C 0x2 registers n 0x50 0x2 registers n 0x54 0x2 registers n 0x58 0x2 registers n 0x5C 0x2 registers n 0x61 0x1 registers n 0x64 0x2 registers n 0x8 0x1 registers n 0xC 0x1 registers n HDMICEC1 37 RCADR1 Device Address Setting Register 1 0x4D 8 read-write n 0x0 0x0 RCADR1 Device Address 1 0 4 read-write RCADR2 Device Address Setting Register 2 0x4C 8 read-write n 0x0 0x0 RCADR2 Device Address 2 0 4 read-write RCCKD Clock Division Setting Register 0x58 16 read-write n 0x0 0x0 CKDIV Operating clock division setting bits 0 11 read-write CKSEL Operating clock selection bit 12 read-write RCCR Reception Control Register 0x41 8 read-write n 0x0 0x0 ADRCE Address comparison enable bit 3 read-write EN Operation enable bit 0 read-write MOD0 Operation mode setting bits 1 read-write MOD1 Operation mode setting bits 2 read-write THSEL Threshold selection bit 7 read-write RCDAHW H Width Setting Register A 0x44 8 read-write n 0x0 0x0 RCDAHW H Width Setting A 0 7 read-write RCDBHW H Width Setting Register B 0x49 8 read-write n 0x0 0x0 RCDBHW H Width Setting B 0 7 read-write RCDTHH Data Save Register (High-High) 0x51 8 read-only n 0x0 0x0 RCDTHH RCDTHH 0 7 read-only RCDTHL Data Save Register (High-Low) 0x50 8 read-only n 0x0 0x0 RCDTHL RCDTHL 0 7 read-only RCDTLH Data Save Register (Low-High) 0x55 8 read-only n 0x0 0x0 RCDTLH RCDTLH 0 7 read-only RCDTLL Data Save Register (Low-Low) 0x54 8 read-only n 0x0 0x0 RCDTLL RCDTLL 0 7 read-only RCLE Data Bit Width Violation Control Register 0x61 8 read-write n 0x0 0x0 EPE Error pulse output enable bit 3 read-write LEL Maximum data bit width violation detection flag bit 1 read-write LELE Maximum data bit width violation detection enable bit 5 read-write LELIE Maximum data bit width violation interrupt enable bit 7 read-write LES Minimum data bit width violation detection flag bit 0 read-write LESE Minimum data bit width violation detection enable bit 4 read-write LESIE Minimum data bit width violation interrupt enable bit 6 read-write RCLELW Maximum Data Bit Width Setting Register 0x65 8 read-write n 0x0 0x0 RCLELW Maximum data bit width setting bits 0 7 read-write RCLESW Minimum Data Bit Width Setting Register 0x64 8 read-write n 0x0 0x0 RCLESW Minimum data bit width setting bits 0 7 read-write RCRC Repeat Code Interrupt Control Register 0x5D 8 read-write n 0x0 0x0 RC Repeat code detection flag bit 0 read-write RCIE Repeat Code Interrupt enable bit 4 read-write RCRHW Repeat Code H Width Setting Register 0x5C 8 read-write n 0x0 0x0 RCRHW Repeat code H width setting bits 0 7 read-write RCSHW Start Bit H Width Setting Register 0x45 8 read-write n 0x0 0x0 RCSHW Start Bit H Width Setting 0 7 read-write RCST Reception Interrupt Control Register 0x40 8 read-write n 0x0 0x0 ACK ACK: ACK detection bit 2 read-write ACKIE ACK interrupt enable bit 6 read-write EOM EOM detection bit 1 read-write OVF Counter overflow detection bit 0 read-write OVFIE Counter overflow interrupt enable bit 5 read-write OVFSEL Counter overflow detection condition setting bit 4 read-write ST Start bit detection bit 3 read-write STIE Start bit interrupt enable bit 7 read-write SFREE Signal Free Time Setting Register 0xC 8 read-write n 0x0 0x0 SFREE Signal free time setting bits 0 3 read-write TXCTRL Transmission Control Register 0x0 8 read-write n 0x0 0x0 EOM EOM setting bit 3 read-write IBREN Bus error detection interrupt enable bit 5 read-write ITSTEN transmission status interrupt enable bit 4 read-write START START setting bit 2 read-write TXEN Transmission operation enable bit 0 read-write TXDATA Transmission Data Register 0x4 8 read-write n 0x0 0x0 TXDATA Transmission Data 0 7 read-write TXSTS Transmission Status Register 0x8 8 read-write n 0x0 0x0 ACKSV ACK cycle value bit 0 read-write IBR Bus error detection interrupt request bit 5 read-write ITST Transmission status interrupt request bit 4 read-write HWWDT Hardware Watchdog Timer HWWDT 0x0 0x0 0x4 registers n 0x10 0x1 registers n 0x4 0x4 registers n 0x8 0x4 registers n 0xC 0x1 registers n 0xC00 0x4 registers n WDG_CTL Hardware Watchdog Timer Control Register 0x8 32 read-write n 0x0 0x0 INTEN Hardware watchdog interrupt and counter enable bit 0 read-write RESEN Hardware watchdog reset enable bit 1 read-write WDG_ICL Hardware Watchdog Timer Clear Register 0xC 8 read-write n 0x0 0x0 WDG_LCK Hardware Watchdog Timer Lock Register 0xC00 32 read-write n 0x0 0x0 WDG_LDR Hardware Watchdog Timer Load Register 0x0 32 read-write n 0x0 0x0 WDG_RIS Hardware Watchdog Timer Interrupt Status Register 0x10 1 read-only n 0x0 0x0 RIS Hardware watchdog interrupt status bit 0 read-only WDG_VLR Hardware Watchdog Timer Value Register 0x4 32 read-only n 0x0 0x0 INTREQ Interrupts INTREQ 0x0 0x0 0x4 registers n 0x10 0xC4 registers n 0x210 0x8 registers n 0xB 0x1 registers n 0xC 0x4 registers n DRQSEL DMA Request Selection Register 0x0 32 read-write n 0x0 0x0 ADCSCAN0 The scan conversion interrupt signal of the A/D converter unit 0 is output as a transfer request to the DMAC. 5 read-write ADCSCAN1 The scan conversion interrupt signal of the A/D converter unit 1 is output as a transfer request to the DMAC. 6 read-write ADCSCAN2 The scan conversion interrupt signal of the A/D converter unit 2 is output as a transfer request to the DMAC. 7 read-write EXINT0 The interrupt signal of the external interrupt ch.0 is output as a transfer request to the DMAC (including extension). 28 read-write EXINT1 The interrupt signal of the external interrupt ch.1 is output as a transfer request to the DMAC (including extension). 29 read-write EXINT2 The interrupt signal of the external interrupt ch.2 is output as a transfer request to the DMAC (including extension). 30 read-write EXINT3 The interrupt signal of the external interrupt ch.3 is output as a transfer request to the DMAC (including extension). 31 read-write IRQ0BT0 The IRQ0 interrupt signal of the base timer ch.0 is output as a transfer request to the DMAC. 8 read-write IRQ0BT2 The IRQ0 interrupt signal of the base timer ch.3 is output as a transfer request to the DMAC. 9 read-write IRQ0BT4 The IRQ0 interrupt signal of the base timer ch.4 is output as a transfer request to the DMAC. 10 read-write IRQ0BT6 The IRQ0 interrupt signal of the base timer ch.6 is output as a transfer request to the DMAC. 11 read-write MFS0RX The reception interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC (including extension). 12 read-write MFS0TX The transmission interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC (including extension). 13 read-write MFS1RX The reception interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC (including extension). 14 read-write MFS1TX The transmission interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC (including extension). 15 read-write MFS2RX The reception interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC (including extension). 16 read-write MFS2TX The transmission interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC (including extension). 17 read-write MFS3RX The reception interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC (including extension). 18 read-write MFS3TX The transmission interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC (including extension). 19 read-write MFS4RX The reception interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC (including extension). 20 read-write MFS4TX The transmission interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC (including extension). 21 read-write MFS5RX The reception interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC (including extension). 22 read-write MFS5TX The transmission interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC (including extension). 23 read-write MFS6RX The reception interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC (including extension). 24 read-write MFS6TX The transmission interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC (including extension). 25 read-write MFS7RX The reception interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC (including extension). 26 read-write MFS7TX The transmission interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC (including extension). 27 read-write USBEP1 The EP1 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC. 0 read-write USBEP2 The EP2 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC. 1 read-write USBEP3 The EP3 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC. 2 read-write USBEP4 The EP4 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC. 3 read-write USBEP5 The EP5 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC. 4 read-write EXC02MON EXC02 batch read register 0x10 32 read-only n 0x0 0x0 HWINT Hardware watchdog timer interrupt request 1 read-only NMI External NMIX pin interrupt request 0 read-only IRQ00MON IRQ00 Batch Read Register 0x14 32 read-only n 0x0 0x0 FCSINT Anomalous frequency detection by CSV interrupt request 0 read-only IRQ01MON IRQ01 Batch Read Register 0x18 32 read-only n 0x0 0x0 SWWDTINT Software watchdog timer interrupt request 0 read-only IRQ02MON IRQ02 Batch Read Register 0x1C 32 read-only n 0x0 0x0 LVDINT Low voltage detection (LVD) interrupt request 0 read-only IRQ04MON IRQ04 Batch Read Register 0x24 32 read-only n 0x0 0x0 EXTINT0 Interrupt request on external interrupt ch.0 0 read-only EXTINT1 Interrupt request on external interrupt ch.1 1 read-only EXTINT2 Interrupt request on external interrupt ch.2 2 read-only EXTINT3 Interrupt request on external interrupt ch.3 3 read-only EXTINT4 Interrupt request on external interrupt ch.4 4 read-only EXTINT5 Interrupt request on external interrupt ch.5 5 read-only EXTINT6 Interrupt request on external interrupt ch.6 6 read-only IRQ05MON IRQ05 Batch Read Register 0x28 32 read-only n 0x0 0x0 EXTINT7 Interrupt request on external interrupt ch.15 7 read-only IRQ06MON IRQ06 Batch Read Register 0x2C 32 read-only n 0x0 0x0 TIMINT1 Dual timer 1 interrupt request 0 read-only TIMINT2 Dual timer 2 interrupt request 1 read-only IRQ07MON IRQ07 Batch Read Register 0x30 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.0 0 read-only IRQ08MON IRQ08 Batch Read Register 0x34 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.0 0 read-only MFSINT1 Status interrupt request on MFS ch.0 1 read-only IRQ09MON IRQ09 Batch Read Register 0x38 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.1 0 read-only IRQ10MON IRQ10 Batch Read Register 0x3C 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.1 0 read-only MFSINT1 Status interrupt request on MFS ch.1 1 read-only IRQ11MON IRQ11 Batch Read Register 0x40 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.2 0 read-only IRQ12MON IRQ12 Batch Read Register 0x44 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.2 0 read-only MFSINT1 Status interrupt request on MFS ch.2 1 read-only IRQ13MON IRQ13 Batch Read Register 0x48 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.3 0 read-only IRQ14MON IRQ14 Batch Read Register 0x4C 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.3 0 read-only MFSINT1 Status interrupt request on MFS ch.3 1 read-only IRQ15MON IRQ15 Batch Read Register 0x50 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.4 0 read-only IRQ16MON IRQ16 Batch Read Register 0x54 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.4 0 read-only MFSINT1 Status interrupt request on MFS ch.4 1 read-only IRQ17MON IRQ17 Batch Read Register 0x58 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.5 0 read-only IRQ18MON IRQ18 Batch Read Register 0x5C 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.5 0 read-only MFSINT1 Status interrupt request on MFS ch.5 1 read-only IRQ19MON IRQ19 Batch Read Register 0x60 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.6 0 read-only IRQ20MON IRQ20 Batch Read Register 0x64 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.6 0 read-only MFSINT1 Status interrupt request on MFS ch.6 1 read-only IRQ21MON IRQ21 Batch Read Register 0x68 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.7 0 read-only IRQ22MON IRQ22 Batch Read Register 0x6C 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.7 0 read-only MFSINT1 Status interrupt request on MFS ch.7 1 read-only IRQ24MON IRQ24 Batch Read Register 0x74 32 read-only n 0x0 0x0 MOSCINT Stabilization wait completion interrupt request for main clock oscillation 0 read-only MPLLINT Stabilization wait completion interrupt request for main PLL oscillation 2 read-only RTCINT RTC interrupt request 5 read-only SOSCINT Stabilization wait completion interrupt request for sub-clock oscillation 1 read-only UPLLINT Stabilization wait completion interrupt request for USB or USB/Ethernet PLL oscillation. 3 read-only WCINT Watch counter interrupt request 4 read-only IRQ25MON IRQ25 Batch Read Register 0x78 32 read-only n 0x0 0x0 ADCINT0 Priority conversion interrupt request in the corresponding A/D unit 0. 0 read-only ADCINT1 Scan conversion interrupt request in the corresponding A/D unit 0. 1 read-only ADCINT2 FIFO overrun interrupt request in the corresponding A/D unit 0. 2 read-only ADCINT3 Conversion result comparison interrupt request in the corresponding A/D unit 0. 3 read-only IRQ26MON IRQ26 Batch Read Register 0x7C 32 read-only n 0x0 0x0 ADCINT0 Priority conversion interrupt request in the corresponding A/D unit 1 0 read-only ADCINT1 Scan conversion interrupt request in the corresponding A/D unit 1 1 read-only ADCINT2 FIFO overrun interrupt request in the corresponding A/D unit 1 2 read-only ADCINT3 Conversion result comparison interrupt request in the corresponding A/D unit 1 3 read-only IRQ27MON IRQ27 Batch Read Register 0x80 32 read-only n 0x0 0x0 LCDCINT LCDC interrupt request for LCD controller 4 read-only IRQ31MON IRQ31 Batch Read Register 0x90 32 read-only n 0x0 0x0 BTINT0 IRQ0 interrupt request on the base timer ch.0 0 read-only BTINT1 IRQ1 interrupt request on the base timer ch.0 1 read-only BTINT10 IRQ0 interrupt request on the base timer ch.5 10 read-only BTINT11 IRQ1 interrupt request on the base timer ch.5 11 read-only BTINT12 IRQ0 interrupt request on the base timer ch.6 12 read-only BTINT13 IRQ1 interrupt request on the base timer ch.6 13 read-only BTINT14 IRQ0 interrupt request on the base timer ch.7 14 read-only BTINT15 IRQ1 interrupt request on the base timer ch.7 15 read-only BTINT2 IRQ0 interrupt request on the base timer ch.1 2 read-only BTINT3 IRQ1 interrupt request on the base timer ch.1 3 read-only BTINT4 IRQ0 interrupt request on the base timer ch.2 4 read-only BTINT5 IRQ1 interrupt request on the base timer ch.2 5 read-only BTINT6 IRQ0 interrupt request on the base timer ch.3 6 read-only BTINT7 IRQ1 interrupt request on the base timer ch.3 7 read-only BTINT8 IRQ0 interrupt request on the base timer ch.4 8 read-only BTINT9 IRQ1 interrupt request on the base timer ch.4 9 read-only IRQ34MON IRQ34 Batch Read Register 0x9C 32 read-only n 0x0 0x0 USB0INT0 Endpoint 1 DRQ interrupt request on the USB ch.0 0 read-only USB0INT1 Endpoint 2 DRQ interrupt request on the USB ch.0 1 read-only USB0INT2 Endpoint 3 DRQ interrupt request on the USB ch.0 2 read-only USB0INT3 Endpoint 4 DRQ interrupt request on the USB ch.0 3 read-only USB0INT4 Endpoint 5 DRQ interrupt request on the USB ch.0 4 read-only IRQ35MON IRQ35 Batch Read Register 0xA0 32 read-only n 0x0 0x0 USB0INT0 Endpoint 0 DRQI interrupt request on the USB ch.0 0 read-only USB0INT1 Endpoint 0 DRQO interrupt request on the USB ch.0 1 read-only USB0INT2 Status (SUSP, SOF, BRST, CONF, WKUP) interrupt request on the USB ch.0 2 read-only USB0INT3 Status (SPK) interrupt request on the USB ch.0 3 read-only USB0INT4 Status (DIRQ, URIRQ, RWKIRQ, CNNIRQ) interrupt request on the USB ch.0 4 read-only USB0INT5 Status (SOFIRQ, CMPIRO) interrupt request on the USB ch.0 5 read-only IRQ36MON IRQ36 Batch Read Register 0xA4 32 read-only n 0x0 0x0 RCEC0INT Interrupt request for HDMI-CEC/Remote Control Reception ch.0 5 read-only IRQ37MON IRQ37 Batch Read Register 0xA8 32 read-only n 0x0 0x0 RCEC1INT Interrupt request for HDMI-CEC/Remote Control Reception ch.1 6 read-only IRQ38MON IRQ38 Batch Read Register 0xAC 32 read-only n 0x0 0x0 DMAINT Interrupt request on DMA ch.0. 0 read-only IRQ39MON IRQ39 Batch Read Register 0xB0 32 read-only n 0x0 0x0 DMAINT Interrupt request on DMA ch.1. 0 read-only IRQ40MON IRQ40 Batch Read Register 0xB4 32 read-only n 0x0 0x0 DMAINT Interrupt request on DMA ch.2. 0 read-only IRQ41MON IRQ41 Batch Read Register 0xB8 32 read-only n 0x0 0x0 DMAINT Interrupt request on DMA ch.3. 0 read-only IRQ42MON IRQ42 Batch Read Register 0xBC 32 read-only n 0x0 0x0 DMAINT Interrupt request on DMA ch.4. 0 read-only IRQ43MON IRQ43 Batch Read Register 0xC0 32 read-only n 0x0 0x0 DMAINT Interrupt request on DMA ch.5. 0 read-only IRQ44MON IRQ44 Batch Read Register 0xC4 32 read-only n 0x0 0x0 DMAINT Interrupt request on DMA ch.6. 0 read-only IRQ45MON IRQ45 Batch Read Register 0xC8 32 read-only n 0x0 0x0 DMAINT Interrupt request on DMA ch.7. 0 read-only IRQ47MON IRQ47 Batch Read Register 0xD0 32 read-only n 0x0 0x0 FLASHINT RDY, HANG interrupt request for flash 11 read-only IRQCMODE Interrupt Factor Vector Relocate Setting Register 0xC 32 read-write n 0x0 0x0 IRQCMODE Interrupt Factor Vector Relocate Setting 0 read-write ODDPKS USB ch.0 Odd Packet Size DMA Enable Register 0xB 8 read-write n 0x0 0x0 ODDPKS0 When the transfer destination address of DMAC is USB.EP1DT, the bit width of the last transfer data is converted to Byte. 0 read-write ODDPKS1 When the transfer destination address of DMAC is USB.EP2DT, the bit width of the last transfer data is converted to Byte. 1 read-write ODDPKS2 When the transfer destination address of DMAC is USB.EP3DT, the bit width of the last transfer data is converted to Byte. 2 read-write ODDPKS3 When the transfer destination address of DMAC is USB.EP4DT, the bit width of the last transfer data is converted to Byte. 3 read-write ODDPKS4 When the transfer destination address of DMAC is USB.EP5DT, the bit width of the last transfer data is converted to Byte. 4 read-write RCINTSEL0 Interrupt Factor Selection Register 0 0x210 32 read-write n 0x0 0x0 INTSEL0 select the interrupt factor of the interrupt vector No.19. 0 7 read-write INTSEL1 select the interrupt factor of the interrupt vector No.20. 8 7 read-write INTSEL2 select the interrupt factor of the interrupt vector No.21. 16 7 read-write INTSEL3 select the interrupt factor of the interrupt vector No.22. 24 7 read-write RCINTSEL1 Interrupt Factor Selection Register 1 0x214 32 read-write n 0x0 0x0 INTSEL4 select the interrupt factor of the interrupt vector No.23. 0 7 read-write INTSEL5 select the interrupt factor of the interrupt vector No.24. 8 7 read-write INTSEL6 select the interrupt factor of the interrupt vector No.25. 16 7 read-write INTSEL7 select the interrupt factor of the interrupt vector No.26. 24 7 read-write LCDC LCD Controller LCDC 0x0 0x0 0x3 registers n 0x10 0x1 registers n 0x14 0x2 registers n 0x1C 0x28 registers n 0x4 0x4 registers n 0x8 0x1 registers n 0xC 0x4 registers n LCDC 27 BLINK LCDC Blink Setting Register 0x14 16 read-write n 0x0 0x0 BLD00 Blink operation control bit 0 0 read-write BLD01 Blink operation control bit 1 1 read-write BLD02 Blink operation control bit 2 2 read-write BLD03 Blink operation control bit 3 3 read-write BLD04 Blink operation control bit 4 4 read-write BLD05 Blink operation control bit 5 5 read-write BLD06 Blink operation control bit 6 6 read-write BLD07 Blink operation control bit 7 7 read-write BLD08 Blink operation control bit 8 8 read-write BLD09 Blink operation control bit 9 9 read-write BLD10 Blink operation control bit 10 10 read-write BLD11 Blink operation control bit 11 11 read-write BLD12 Blink operation control bit 12 12 read-write BLD13 Blink operation control bit 13 13 read-write BLD14 Blink operation control bit 14 14 read-write BLD15 Blink operation control bit 15 15 read-write COMEN LCDC COM Output Enable Register 0x8 8 read-write n 0x0 0x0 COM0 Dual purpose COM port control bit 0 read-write COM1 Dual purpose COM port control bit 1 read-write COM2 Dual purpose COM port control bit 2 read-write COM3 Dual purpose COM port control bit 3 read-write COM4 Dual purpose COM/SEG port control bits 4 read-write COM5 Dual purpose COM/SEG port control bits 5 read-write COM6 Dual purpose COM/SEG port control bits 6 read-write COM7 Dual purpose COM/SEG port control bits 7 read-write LCDCC1 LCDC Control Register 1 0x0 8 read-write n 0x0 0x0 LCDEN Timer mode operation enable bit 6 read-write MS LCD controller display mode selection bits 2 2 read-write VSEL LCD drive power control bit 5 read-write LCDCC2 LCDC Control Register 2 0x1 8 read-write n 0x0 0x0 BK Blank display control bit 2 read-write BLS8 8 COM mode bias selection bit 4 read-write INV Reverse display control bit 3 read-write LCDIEN Interrupt enable bit 1 read-write LCDIF Interrupt request detection bit 0 read-write RSEL Divider resistor value selection bit 5 read-write LCDCC3 LCDC Control Register 3 0x2 8 read-write n 0x0 0x0 BLSEL Blink interval selection bit 6 read-write PICTL I/O port input control bit 7 read-write VE0 VV0 selection bit 1 read-write VE1 VV1 selection bit 2 read-write VE2 VV2 selection bit 3 read-write VE3 VV3 selection bit 4 read-write VE4 VV4 selection bit 5 read-write LCDRAM00 Display Data Memory Register 00 0x1C 8 read-write n 0x0 0x0 LCDRAM Display Data 00 0 7 read-write LCDRAM01 Display Data Memory Register 01 0x1D 8 read-write n 0x0 0x0 LCDRAM Display Data 01 0 7 read-write LCDRAM02 Display Data Memory Register 02 0x1E 8 read-write n 0x0 0x0 LCDRAM Display Data 02 0 7 read-write LCDRAM03 Display Data Memory Register 03 0x1F 8 read-write n 0x0 0x0 LCDRAM Display Data 03 0 7 read-write LCDRAM04 Display Data Memory Register 04 0x20 8 read-write n 0x0 0x0 LCDRAM Display Data 04 0 7 read-write LCDRAM05 Display Data Memory Register 05 0x21 8 read-write n 0x0 0x0 LCDRAM Display Data 05 0 7 read-write LCDRAM06 Display Data Memory Register 06 0x22 8 read-write n 0x0 0x0 LCDRAM Display Data 06 0 7 read-write LCDRAM07 Display Data Memory Register 07 0x23 8 read-write n 0x0 0x0 LCDRAM Display Data 07 0 7 read-write LCDRAM08 Display Data Memory Register 08 0x24 8 read-write n 0x0 0x0 LCDRAM Display Data 08 0 7 read-write LCDRAM09 Display Data Memory Register 09 0x25 8 read-write n 0x0 0x0 LCDRAM Display Data 09 0 7 read-write LCDRAM10 Display Data Memory Register 10 0x26 8 read-write n 0x0 0x0 LCDRAM Display Data 10 0 7 read-write LCDRAM11 Display Data Memory Register 11 0x27 8 read-write n 0x0 0x0 LCDRAM Display Data 11 0 7 read-write LCDRAM12 Display Data Memory Register 12 0x28 8 read-write n 0x0 0x0 LCDRAM Display Data 12 0 7 read-write LCDRAM13 Display Data Memory Register 13 0x29 8 read-write n 0x0 0x0 LCDRAM Display Data 13 0 7 read-write LCDRAM14 Display Data Memory Register 14 0x2A 8 read-write n 0x0 0x0 LCDRAM Display Data 14 0 7 read-write LCDRAM15 Display Data Memory Register 15 0x2B 8 read-write n 0x0 0x0 LCDRAM Display Data 15 0 7 read-write LCDRAM16 Display Data Memory Register 16 0x2C 8 read-write n 0x0 0x0 LCDRAM Display Data 16 0 7 read-write LCDRAM17 Display Data Memory Register 17 0x2D 8 read-write n 0x0 0x0 LCDRAM Display Data 17 0 7 read-write LCDRAM18 Display Data Memory Register 18 0x2E 8 read-write n 0x0 0x0 LCDRAM Display Data 18 0 7 read-write LCDRAM19 Display Data Memory Register 19 0x2F 8 read-write n 0x0 0x0 LCDRAM Display Data 19 0 7 read-write LCDRAM20 Display Data Memory Register 20 0x30 8 read-write n 0x0 0x0 LCDRAM Display Data 20 0 7 read-write LCDRAM21 Display Data Memory Register 21 0x31 8 read-write n 0x0 0x0 LCDRAM Display Data 21 0 7 read-write LCDRAM22 Display Data Memory Register 22 0x32 8 read-write n 0x0 0x0 LCDRAM Display Data 22 0 7 read-write LCDRAM23 Display Data Memory Register 23 0x33 8 read-write n 0x0 0x0 LCDRAM Display Data 23 0 7 read-write LCDRAM24 Display Data Memory Register 24 0x34 8 read-write n 0x0 0x0 LCDRAM Display Data 24 0 7 read-write LCDRAM25 Display Data Memory Register 25 0x35 8 read-write n 0x0 0x0 LCDRAM Display Data 25 0 7 read-write LCDRAM26 Display Data Memory Register 26 0x36 8 read-write n 0x0 0x0 LCDRAM Display Data 26 0 7 read-write LCDRAM27 Display Data Memory Register 27 0x37 8 read-write n 0x0 0x0 LCDRAM Display Data 27 0 7 read-write LCDRAM28 Display Data Memory Register 28 0x38 8 read-write n 0x0 0x0 LCDRAM Display Data 28 0 7 read-write LCDRAM29 Display Data Memory Register 29 0x39 8 read-write n 0x0 0x0 LCDRAM Display Data 29 0 7 read-write LCDRAM30 Display Data Memory Register 30 0x3A 8 read-write n 0x0 0x0 LCDRAM Display Data 30 0 7 read-write LCDRAM31 Display Data Memory Register 31 0x3B 8 read-write n 0x0 0x0 LCDRAM Display Data 31 0 7 read-write LCDRAM32 Display Data Memory Register 32 0x3C 8 read-write n 0x0 0x0 LCDRAM Display Data 32 0 7 read-write LCDRAM33 Display Data Memory Register 33 0x3D 8 read-write n 0x0 0x0 LCDRAM Display Data 33 0 7 read-write LCDRAM34 Display Data Memory Register 34 0x3E 8 read-write n 0x0 0x0 LCDRAM Display Data 34 0 7 read-write LCDRAM35 Display Data Memory Register 35 0x3F 8 read-write n 0x0 0x0 LCDRAM Display Data 35 0 7 read-write LCDRAM36 Display Data Memory Register 36 0x40 8 read-write n 0x0 0x0 LCDRAM Display Data 36 0 7 read-write LCDRAM37 Display Data Memory Register 37 0x41 8 read-write n 0x0 0x0 LCDRAM Display Data 37 0 7 read-write LCDRAM38 Display Data Memory Register 38 0x42 8 read-write n 0x0 0x0 LCDRAM Display Data 38 0 7 read-write LCDRAM39 Display Data Memory Register 39 0x43 8 read-write n 0x0 0x0 LCDRAM Display Data 39 0 7 read-write PSR LCDC Clock Prescaler Register 0x4 32 read-write n 0x0 0x0 CLKDIV LCDC clock division ratio setting bit 0 21 read-write CLKSEL Source clock selection bit 22 read-write SEGEN1 LCDC SEG Output Enable Register 1 0xC 32 read-write n 0x0 0x0 SEG00 Segment 0 0 read-write SEG01 Segment 1 1 read-write SEG11 Segment 11 11 read-write SEG12 Segment 12 12 read-write SEG13 Segment 13 13 read-write SEG19 Segment 19 19 read-write SEG20 Segment 20 20 read-write SEG21 Segment 21 21 read-write SEG23 Segment 23 23 read-write SEG24 Segment 24 24 read-write SEG25 Segment 25 25 read-write SEG26 Segment 26 26 read-write SEG27 Segment 27 27 read-write SEG28 Segment 28 28 read-write SEG29 Segment 29 29 read-write SEG30 Segment 30 30 read-write SEG31 Segment 31 31 read-write SEGEN2 LCDC SEG Output Enable Register 2 0x10 8 read-write n 0x0 0x0 SEG35 Segment 35 3 read-write SEG36 Segment 36 4 read-write SEG37 Segment 37 5 read-write LVD Low-voltage Detection LVD 0x0 0x0 0x2 registers n 0x4 0x1 registers n 0x8 0x1 registers n 0xC 0x5 registers n LVD 2 CLR Low-voltage Detection Interrupt Clear Register 0x8 8 read-write n 0x0 0x0 LVDCL Low-voltage detection interrupt clear bit 7 read-write CTL Low-voltage Detection Voltage Control Register 0x0 16 read-write n 0x0 0x0 LVDIE Low-voltage detection interrupt enable bit 7 read-write LVDRE Low-voltage detection reset operation enable bit 15 read-write SVHI Low-voltage detection interrupt voltage setting bits 2 4 read-write SVHR Low-voltage detection reset voltage setting bits 10 4 read-write RLR Low-voltage Detection Voltage Protection Register 0xC 32 read-write n 0x0 0x0 LVDLCK Low-voltage Detection Voltage Control Register protection bits 0 31 read-write STR Low-voltage Detection Interrupt Register 0x4 8 read-only n 0x0 0x0 LVDIR Low-voltage detection interrupt bit 7 read-only STR2 Low-voltage Detection Circuit Status Register 0x10 8 read-only n 0x0 0x0 LVDIRDY Low-voltage detection interrupt status flag 7 read-only LVDRRDY Low-voltage detection reset status flag 6 read-only MFS0 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x1D 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS0RX 7 MFS0TX 8 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write n 0x0 0x0 BEC Bus error control bit 0 read-write SCLC SCL output control bit 2 read-write SCLS SCL status bit 4 read-write SDAC SDA output control bit 3 read-write SDAS SDA status bit 5 read-write SOCE Serial output enabled bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS1 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x1D 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS1RX 9 MFS1TX 10 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write n 0x0 0x0 BEC Bus error control bit 0 read-write SCLC SCL output control bit 2 read-write SCLS SCL status bit 4 read-write SDAC SDA output control bit 3 read-write SDAS SDA status bit 5 read-write SOCE Serial output enabled bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS2 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x1D 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS2RX 11 MFS2TX 12 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write n 0x0 0x0 BEC Bus error control bit 0 read-write SCLC SCL output control bit 2 read-write SCLS SCL status bit 4 read-write SDAC SDA output control bit 3 read-write SDAS SDA status bit 5 read-write SOCE Serial output enabled bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS3 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x1D 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS3RX 13 MFS3TX 14 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write n 0x0 0x0 BEC Bus error control bit 0 read-write SCLC SCL output control bit 2 read-write SCLS SCL status bit 4 read-write SDAC SDA output control bit 3 read-write SDAS SDA status bit 5 read-write SOCE Serial output enabled bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS4 Multi-function Serial Interface 4 MFS4 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1D 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS4RX 15 MFS4TX 16 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_FBYTE1 FIFO Byte Register 1 CSIO 0x18 8 read-write n 0x0 0x0 CSIO_FBYTE2 FIFO Byte Register 2 CSIO 0x19 8 read-write n 0x0 0x0 CSIO_FCR0 FIFO Control Register 0 CSIO 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write CSIO_FCR1 FIFO Control Register 1 CSIO 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write n 0x0 0x0 BEC Bus error control bit 0 read-write SCLC SCL output control bit 2 read-write SCLS SCL status bit 4 read-write SDAC SDA output control bit 3 read-write SDAS SDA status bit 5 read-write SOCE Serial output enabled bit 1 read-write I2C_FBYTE1 FIFO Byte Register 1 I2C 0x18 8 read-write n 0x0 0x0 I2C_FBYTE2 FIFO Byte Register 2 I2C 0x19 8 read-write n 0x0 0x0 I2C_FCR0 FIFO Control Register 0 I2C 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write I2C_FCR1 FIFO Control Register 1 I2C 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_FBYTE1 FIFO Byte Register 1 UART 0x18 8 read-write n 0x0 0x0 UART_FBYTE2 FIFO Byte Register 2 UART 0x19 8 read-write n 0x0 0x0 UART_FCR0 FIFO Control Register 0 UART 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write UART_FCR1 FIFO Control Register 1 UART 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS5 Multi-function Serial Interface 4 MFS4 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1D 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS5RX 17 MFS5TX 18 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_FBYTE1 FIFO Byte Register 1 CSIO 0x18 8 read-write n 0x0 0x0 CSIO_FBYTE2 FIFO Byte Register 2 CSIO 0x19 8 read-write n 0x0 0x0 CSIO_FCR0 FIFO Control Register 0 CSIO 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write CSIO_FCR1 FIFO Control Register 1 CSIO 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write n 0x0 0x0 BEC Bus error control bit 0 read-write SCLC SCL output control bit 2 read-write SCLS SCL status bit 4 read-write SDAC SDA output control bit 3 read-write SDAS SDA status bit 5 read-write SOCE Serial output enabled bit 1 read-write I2C_FBYTE1 FIFO Byte Register 1 I2C 0x18 8 read-write n 0x0 0x0 I2C_FBYTE2 FIFO Byte Register 2 I2C 0x19 8 read-write n 0x0 0x0 I2C_FCR0 FIFO Control Register 0 I2C 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write I2C_FCR1 FIFO Control Register 1 I2C 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_FBYTE1 FIFO Byte Register 1 UART 0x18 8 read-write n 0x0 0x0 UART_FBYTE2 FIFO Byte Register 2 UART 0x19 8 read-write n 0x0 0x0 UART_FCR0 FIFO Control Register 0 UART 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write UART_FCR1 FIFO Control Register 1 UART 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS6 Multi-function Serial Interface 4 MFS4 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1D 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS6RX 19 MFS6TX 20 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_FBYTE1 FIFO Byte Register 1 CSIO 0x18 8 read-write n 0x0 0x0 CSIO_FBYTE2 FIFO Byte Register 2 CSIO 0x19 8 read-write n 0x0 0x0 CSIO_FCR0 FIFO Control Register 0 CSIO 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write CSIO_FCR1 FIFO Control Register 1 CSIO 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write n 0x0 0x0 BEC Bus error control bit 0 read-write SCLC SCL output control bit 2 read-write SCLS SCL status bit 4 read-write SDAC SDA output control bit 3 read-write SDAS SDA status bit 5 read-write SOCE Serial output enabled bit 1 read-write I2C_FBYTE1 FIFO Byte Register 1 I2C 0x18 8 read-write n 0x0 0x0 I2C_FBYTE2 FIFO Byte Register 2 I2C 0x19 8 read-write n 0x0 0x0 I2C_FCR0 FIFO Control Register 0 I2C 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write I2C_FCR1 FIFO Control Register 1 I2C 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_FBYTE1 FIFO Byte Register 1 UART 0x18 8 read-write n 0x0 0x0 UART_FBYTE2 FIFO Byte Register 2 UART 0x19 8 read-write n 0x0 0x0 UART_FCR0 FIFO Control Register 0 UART 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write UART_FCR1 FIFO Control Register 1 UART 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS7 Multi-function Serial Interface 4 MFS4 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1D 0x1 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS7RX 21 MFS7TX 22 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_FBYTE1 FIFO Byte Register 1 CSIO 0x18 8 read-write n 0x0 0x0 CSIO_FBYTE2 FIFO Byte Register 2 CSIO 0x19 8 read-write n 0x0 0x0 CSIO_FCR0 FIFO Control Register 0 CSIO 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write CSIO_FCR1 FIFO Control Register 1 CSIO 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_EIBCR Extension I2C Bus Control Register I2C 0x1D 8 read-write n 0x0 0x0 BEC Bus error control bit 0 read-write SCLC SCL output control bit 2 read-write SCLS SCL status bit 4 read-write SDAC SDA output control bit 3 read-write SDAS SDA status bit 5 read-write SOCE Serial output enabled bit 1 read-write I2C_FBYTE1 FIFO Byte Register 1 I2C 0x18 8 read-write n 0x0 0x0 I2C_FBYTE2 FIFO Byte Register 2 I2C 0x19 8 read-write n 0x0 0x0 I2C_FCR0 FIFO Control Register 0 I2C 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write I2C_FCR1 FIFO Control Register 1 I2C 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_FBYTE1 FIFO Byte Register 1 UART 0x18 8 read-write n 0x0 0x0 UART_FBYTE2 FIFO Byte Register 2 UART 0x19 8 read-write n 0x0 0x0 UART_FCR0 FIFO Control Register 0 UART 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write UART_FCR1 FIFO Control Register 1 UART 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 RTC REAL-TIME CLOCK RTC 0x0 0x0 0x13 registers n 0x15 0x3 registers n 0x19 0x2 registers n 0x1C 0x4 registers n 0x20 0x2 registers n 0x24 0x3 registers n 0x28 0x2 registers n 0x2C 0x1 registers n 0x30 0x1 registers n ALDR Alarm Date Register 0x17 8 read-write n 0x0 0x0 AD the first digit of the alarm-set date 0 3 read-write TAD the second digit of the alarm-set date 4 1 read-write ALHR Alarm Hour Register 0x16 8 read-write n 0x0 0x0 AH the first digit of the alarm-set hour 0 3 read-write TAH the second digit of the alarm-set hour 4 1 read-write ALMIR Alarm Minute Register 0x15 8 read-write n 0x0 0x0 AMI the first digit of the alarm-set minute 0 3 read-write TAMI the second digit of the alarm-set minute 4 2 read-write ALMOR Alarm Month Register 0x19 8 read-write n 0x0 0x0 AMO the first digit of the alarm-set month 0 3 read-write TAMO the second digit of the alarm-set month 4 read-write TAMO0 the second digit of the alarm-set month 4 read-write ALYR Alarm Years Register 0x1A 8 read-write n 0x0 0x0 AY the first digit of the alarm-set year 0 3 read-write TAY the second digit of the alarm-set year 4 3 read-write WTBR Counter Cycle Setting Register 0x8 32 read-write n 0x0 0x0 BR0 Bit0 of WTBR 0 read-write BR1 Bit1 of WTBR 1 read-write BR10 Bit10 of WTBR 10 read-write BR11 Bit11 of WTBR 11 read-write BR12 Bit12 of WTBR 12 read-write BR13 Bit13 of WTBR 13 read-write BR14 Bit14 of WTBR 14 read-write BR15 Bit15 of WTBR 15 read-write BR16 Bit16 of WTBR 16 read-write BR17 Bit17 of WTBR 17 read-write BR18 Bit18 of WTBR 18 read-write BR19 Bit19 of WTBR 19 read-write BR2 Bit2 of WTBR 2 read-write BR20 Bit20 of WTBR 20 read-write BR21 Bit21 of WTBR 21 read-write BR22 Bit22 of WTBR 22 read-write BR23 Bit23 of WTBR 23 read-write BR3 Bit3 of WTBR 3 read-write BR4 Bit4 of WTBR 4 read-write BR5 Bit5 of WTBR 5 read-write BR6 Bit6 of WTBR 6 read-write BR7 Bit7 of WTBR 7 read-write BR8 Bit8 of WTBR 8 read-write BR9 Bit9 of WTBR 9 read-write WTCAL Frequency Correction Value Setting Register 0x24 16 read-write n 0x0 0x0 WTCAL Frequency correction value 0 9 read-write WTCALEN Frequency Correction Enable Register 0x26 8 read-write n 0x0 0x0 WTCALEN Frequency correction enable bit 0 read-write WTCALPRD Frequency Correction Cycle Setting Register 0x2C 8 read-write n 0x0 0x0 WTCALPRD frequency correction value 0 5 read-write WTCLKM Selection Clock Status Register 0x21 8 read-only n 0x0 0x0 WTCLKM Clock selection status bit 0 1 read-only WTCLKS Clock Selection Register 0x20 8 read-write n 0x0 0x0 WTCLKS Input clock selection bit 0 read-write WTCOSEL RTCCO Output Selection Register 0x30 8 read-write n 0x0 0x0 WTCOSEL RTCCO output selection bit 0 read-write WTCR1 Control Register 1 0x0 32 read-write n 0x0 0x0 BUSY Busy bit 6 read-only DEN Alarm date register enable bit 10 read-write HEN Alarm hour register enable bit 9 read-write INTALI Alarm interrupt flag bit 21 read-write INTALIE Alarm interrupt enable bit 29 read-write INTCRI Year/month/date/hour/minute/second/day of the week counter value read completion interrupt flag bit 23 read-write INTCRIE Year/month/date/hour/minute/second/day of the week counter value read completion interrupt enable bit 31 read-write INTERI Time rewrite error interrupt flag bit 22 read-write INTERIE Time rewrite error interrupt enable bit 30 read-write INTHI 1-hour interrupt flag bit 19 read-write INTHIE 1-hour interrupt enable bit 27 read-write INTMI 1-minute interrupt flag bit 18 read-write INTMIE 1-minute interrupt enable bit 26 read-write INTSI 1-second interrupt flag bit 17 read-write INTSIE 1-second interrupt enable bit 25 read-write INTSSI 0.5-second interrupt flag bit 16 read-write INTSSIE 0.5-second interrupt enable bit 24 read-write INTTMI Timer interrupt flag bit 20 read-write INTTMIE Timer interrupt enable bit 28 read-write MIEN Alarm minute register enable bit 8 read-write MOEN Alarm month register enable bit 11 read-write RUN RTC count block operation bit 2 read-only SCRST Sub second generation/1-second generation counter reset bit 5 read-write SCST 1-second clock output stop bit 4 read-write SRST RTC reset bit 3 read-write ST Start bit 0 read-write YEN Alarm year register enable bit 12 read-write WTCR2 Control Register 2 0x4 32 read-write n 0x0 0x0 CREAD Year/month/date/hour/minute/second/day of the week counter value read control bit 0 read-write TMEN Timer counter control bit 9 read-write TMRUN Timer counter operation bit 10 read-only TMST Timer counter start bit 8 read-write WTDIV Divider Ratio Setting Register 0x28 8 read-write n 0x0 0x0 WTDIV Divider ratio 0 3 read-write WTDIVEN Divider Output Enable Register 0x29 8 read-write n 0x0 0x0 WTDIVEN Divider enable bit 0 read-write WTDIVRDY Divider status bit 1 read-only WTDR Date Register 0xF 8 read-write n 0x0 0x0 D the first digit of the date 0 3 read-write TD the second digit of the date 4 1 read-write WTDW Day of the Week Register 0x10 8 read-write n 0x0 0x0 DW Day of the week 0 2 read-write WTHR Hour register 0xE 8 read-write n 0x0 0x0 H the first digit of the hour 0 3 read-write TH the second digit of the hour 4 1 read-write WTMIR Minute Register 0xD 8 read-write n 0x0 0x0 MI the first digit of the minute 0 3 read-write TMI the second digit of the minute 4 2 read-write WTMOR Month Register 0x11 8 read-write n 0x0 0x0 MO the first digit of the month 0 3 read-write TMO the second digit in the month 4 read-write TMO0 the second digit in the month 4 read-write WTSR Second Register 0xC 8 read-write n 0x0 0x0 S the first digit of the second 0 3 read-write TS the second digit of the second 4 2 read-write WTTR Timer Setting Register 0x1C 32 read-write n 0x0 0x0 TM0 Bit0 of WTTR 0 read-write TM1 Bit1 of WTTR 1 read-write TM10 Bit10 of WTTR 10 read-write TM11 Bit11 of WTTR 11 read-write TM12 Bit12 of WTTR 12 read-write TM13 Bit13 of WTTR 13 read-write TM14 Bit14 of WTTR 14 read-write TM15 Bit15 of WTTR 15 read-write TM16 Bit16 of WTTR 16 read-write TM17 Bit17 of WTTR 17 read-write TM2 Bit2 of WTTR 2 read-write TM3 Bit3 of WTTR 3 read-write TM4 Bit4 of WTTR 4 read-write TM5 Bit5 of WTTR 5 read-write TM6 Bit6 of WTTR 6 read-write TM7 Bit7 of WTTR 7 read-write TM8 Bit8 of WTTR 8 read-write TM9 Bit9 of WTTR 9 read-write WTYR Year Register 0x12 8 read-write n 0x0 0x0 TY the second digit of the year 4 3 read-write Y the first digit of the year 0 3 read-write SBSSR Software-based Simultaneous Startup Register SBSSR 0x0 0xFC 0x2 registers n BTSSSR Software-based Simultaneous Startup Register 0xFC 16 write-only n 0x0 0x0 SSSR0 Bit0 of BTSSSR 0 write-only SSSR1 Bit1 of BTSSSR 1 write-only SSSR10 Bit10 of BTSSSR 10 write-only SSSR11 Bit11 of BTSSSR 11 write-only SSSR12 Bit12 of BTSSSR 12 write-only SSSR13 Bit13 of BTSSSR 13 write-only SSSR14 Bit14 of BTSSSR 14 write-only SSSR15 Bit15 of BTSSSR 15 write-only SSSR2 Bit2 of BTSSSR 2 write-only SSSR3 Bit3 of BTSSSR 3 write-only SSSR4 Bit4 of BTSSSR 4 write-only SSSR5 Bit5 of BTSSSR 5 write-only SSSR6 Bit6 of BTSSSR 6 write-only SSSR7 Bit7 of BTSSSR 7 write-only SSSR8 Bit8 of BTSSSR 8 write-only SSSR9 Bit9 of BTSSSR 9 write-only SWWDT Software Watchdog Timer SWWDT 0x0 0x0 0x4 registers n 0x10 0x1 registers n 0x4 0x4 registers n 0x4 0x4 registers n 0x8 0x1 registers n 0xC 0x4 registers n 0xC00 0x4 registers n SWDT 1 WDOGCONTROL Software Watchdog Timer Control Register 0x8 8 read-write n 0x0 0x0 INTEN Interrupt and counter enable bit of the software watchdog 0 read-write RESEN Reset enable bit of the software watchdog 1 read-write WDOGINTCLR Software Watchdog Timer Clear Register 0xC 32 read-write n 0x0 0x0 WDOGLOAD Software Watchdog Timer Load Register 0x0 32 read-write n 0x0 0x0 WDOGLOCK Software Watchdog Timer Lock Register 0xC00 32 read-write n 0x0 0x0 WDOGRIS Software Watchdog Timer Interrupt Status Register 0x10 8 read-only n 0x0 0x0 RIS Software watchdog interrupt status bit 0 read-only WDOGVALUE Software Watchdog Timer Value Register 0x4 32 read-only n 0x0 0x0 USB0 USB0 Function USB0 0x0 0x2100 0x2 registers n 0x2104 0x2 registers n 0x2108 0x2 registers n 0x210C 0x2 registers n 0x2110 0x2 registers n 0x2114 0x2 registers n 0x2118 0x2 registers n 0x211C 0x1 registers n 0x2120 0x2 registers n 0x2124 0x2 registers n 0x2128 0x2 registers n 0x212C 0x2 registers n 0x2130 0x2 registers n 0x2134 0x2 registers n 0x2138 0x2 registers n 0x213C 0x2 registers n 0x2140 0x2 registers n 0x2144 0x2 registers n 0x2148 0x2 registers n 0x214C 0x2 registers n 0x2150 0x2 registers n 0x2154 0x2 registers n 0x2158 0x2 registers n 0x215C 0x2 registers n 0x2160 0x2 registers n 0x2164 0x2 registers n 0x2168 0x2 registers n 0x216C 0x2 registers n 0x2170 0x2 registers n 0x2174 0x2 registers n USB0F 34 USB0F_USB0H 35 EP0C EP0 Control Register 0x2124 16 read-write n 0x0 0x0 PKS0 Packet Size Endpoint 0 Setting bits 0 6 read-write STAL Endpoint 0 Stall Setting bit 9 read-write EP0DT EP0 Data Register 0x2160 16 read-write n 0x0 0x0 BFDT Endpoint Send/Receive Buffer Data 0 15 read-write EP0IS EP0I Status Register 0x2144 16 read-write n 0x0 0x0 BFINI Send Buffer Initialization bit 15 read-write DRQI Send/Receive Data Interrupt Request bit 10 read-write DRQIIE Send Data Interrupt Enable bit 14 read-write EP0OS EP0O Status Register 0x2148 16 read-write n 0x0 0x0 BFINI Receive Buffer Initialization bit 15 read-write DRQO Receive Data Interrupt Request bit 10 read-write DRQOIE Receive Data Interrupt Enable bit 14 read-write SIZE Packet Size Indication bit 0 6 read-only SPK Short Packet Interrupt Request bit 9 read-write SPKIE Short Packet Interrupt Enable bit 13 read-write EP1C EP1 Control Register 0x2128 16 read-write n 0x0 0x0 DIR Endpoint Transfer Direction Select bit 12 read-write DMAE DMA Automatic Transfer Enable bit 11 read-write EPEN Endpoint Enable bit 15 read-write NULE Null Automatic Transfer Enable bit 10 read-write PKS Packet Size Setting bits 0 8 read-write STAL Endpoint Stall Setting bit 9 read-write TYPE Endpoint Transfer Type Select bits 13 1 read-write EP1DT EP1 Data Register 0x2164 read-write n 0x0 0x0 EP1S EP1 Status Register 0x214C 16 read-write n 0x0 0x0 BFINI Send/Receive Buffer Initialization bit 15 read-write BUSY Busy Flag bit 11 read-only DRQ Packet Transfer Interrupt Request bit 10 read-write DRQIE Packet Transfer Interrupt Enable bit 14 read-write SIZE packet SIZE 0 8 read-only SPK Short Packet Interrupt Request bit 9 read-write SPKIE Short Packet Interrupt Enable bit 13 read-write EP2C EP2 Control Register 0x212C 16 read-write n 0x0 0x0 DIR Endpoint Transfer Direction Select bit 12 read-write DMAE DMA Automatic Transfer Enable bit 11 read-write EPEN Endpoint Enable bit 15 read-write NULE Null Automatic Transfer Enable bit 10 read-write PKS Packet Size Setting bits 0 6 read-write STAL Endpoint Stall Setting bit 9 read-write TYPE Endpoint Transfer Type Select bits 13 1 read-write EP2DT EP2 Data Register 0x2168 read-write n 0x0 0x0 EP2S EP2 Status Register 0x2150 16 read-write n 0x0 0x0 BFINI Send/Receive Buffer Initialization bit 15 read-write BUSY Busy Flag bit 11 read-only DRQ Packet Transfer Interrupt Request bit 10 read-write DRQIE Packet Transfer Interrupt Enable bit 14 read-write SIZE packet SIZE 0 6 read-only SPK Short Packet Interrupt Request bit 9 read-write SPKIE Short Packet Interrupt Enable bit 13 read-write EP3C EP3 Control Register 0x2130 read-write n 0x0 0x0 EP3DT EP3 Data Register 0x216C read-write n 0x0 0x0 EP3S EP3 Status Register 0x2154 read-write n 0x0 0x0 EP4C EP4 Control Register 0x2134 read-write n 0x0 0x0 EP4DT EP4 Data Register 0x2170 read-write n 0x0 0x0 EP4S EP4 Status Register 0x2158 read-write n 0x0 0x0 EP5C EP5 Control Register 0x2138 read-write n 0x0 0x0 EP5DT EP5 Data Register 0x2174 read-write n 0x0 0x0 EP5S EP5 Status Register 0x215C read-write n 0x0 0x0 HADR Host Address Register 0x2111 8 read-write n 0x0 0x0 ADDRESS Host Address 0 6 read-write HCNT Host Control Register 0x2100 16 read-write n 0x0 0x0 CANCEL token cancellation enable bit 9 read-write CMPIRE token completion interrupt enable bit 5 read-write CNNIRE device connection detection interrupt enable bit 4 read-write DIRE device disconnection detection interrupt enable bit 3 read-write HOST host mode bit 0 read-write RETRY retry enable bit 8 read-write RWKIRE resume interrupt enable bit 7 read-write SOFIRE SOF interrupt enable bit 2 read-write SOFSTEP SOF interrupt occurrence selection bit 10 read-write URIRE bus reset interrupt enable bit 6 read-write URST bus reset bit 1 read-write HEOF EOF Setup Register 0x2114 16 read-write n 0x0 0x0 EOF0 End Frame 0 0 7 read-write EOF1 End Frame 1 8 5 read-write HERR Host Error Status Register 0x2105 8 read-write n 0x0 0x0 CRC CRC error flag 4 read-write HS handshake status flags 0 1 read-write LSTSOF lost SOF flag 7 read-write RERR receive error flag 6 read-write STUFF stuffing error flag 2 read-write TGERR toggle error flag 3 read-write TOUT timeout flag 5 read-write HFCOMP SOF Interrupt Frame Compare Register 0x2109 8 read-write n 0x0 0x0 FRAMECOMP frame compare data 0 7 read-write HFRAME Frame Setup Register 0x2118 16 read-write n 0x0 0x0 FRAME0 Frame Setup 0 0 7 read-write FRAME1 Frame Setup 1 8 2 read-write HIRQ Host Interrupt Register 0x2104 8 read-write n 0x0 0x0 CMPIRQ token completion flag 3 read-write CNNIRQ device connection detection flag 2 read-write DIRQ device disconnection detection flag 1 read-write RWKIRQ remote Wake-up end flag 5 read-write SOFIRQ SOF starting flag 0 read-write TCAN token cancellation flag 7 read-write URIRQ bus reset end flag 4 read-write HRTIMER Retry Timer Setup Register 0x210C 16 read-write n 0x0 0x0 RTIMER0 retry timer setting 0 0 7 read-write RTIMER1 retry timer setting 1 8 7 read-write HRTIMER2 Retry Timer Setup Register 2 0x2110 8 read-write n 0x0 0x0 RTIMER2 retry timer setting 2 0 1 read-write HSTATE Host Status Register 0x2108 8 read-write n 0x0 0x0 ALIVE specify the keep-alive function in the low-speed mode 5 read-write CLKSEL USB operation clock selection bit 4 read-write CSTAT connection status flag 0 read-only SOFBUSY SOF busy flag 3 read-write SUSP suspend setting bit 2 read-write TMODE transmission mode flag 1 read-only HTOKEN Host Token Endpoint Register 0x211C 8 read-write n 0x0 0x0 ENDPT endpoint bits 0 3 read-write TGGL toggle bit 7 read-write TKNEN token enable bits 4 2 read-write TMSP Time Stamp Register 0x213C 16 read-only n 0x0 0x0 TMSP Time Stamp bits 0 10 read-only UDCC UDC Control Register 0x2120 16 read-write n 0x0 0x0 HCONX Host Connection bit 5 read-write PWC Power Control bit 0 read-write RESUM Resume Setting bit 6 read-write RFBK Data Toggle Mode Select bit 1 read-write RST Function Reset bit 7 read-write STALCLREN Endpoint 1 to 5 STAL bit Clear Select bit 3 read-write USTP USB Operating Clock Stop bit 4 read-write UDCIE UDC Interrupt Enable Register 0x2141 8 read-write n 0x0 0x0 BRSTIE Bus Reset Enable bit 3 read-write CONFIE Configuration Interrupt Enable bit 0 read-write CONFN Configuration Number Indication bit 1 read-only SOFIE SOF Reception Interrupt Enable bit 4 read-write SUSPIE Suspend Interrupt Enable bit 5 read-write WKUPIE Wake-up Interrupt Enable bit 2 read-write UDCS UDC Status Register 0x2140 8 read-write n 0x0 0x0 BRST Bus Reset Detection bit 3 read-write CONF Configuration Detection bit 0 read-write SETP Setup Stage Detection bit 1 read-write SOF SOF Detection bit 4 read-write SUSP Suspend detection bit 5 read-write WKUP Wake-up Detection bit 2 read-write USBCLK USB Clock USBCLK 0x0 0x0 0x1 registers n 0x10 0x1 registers n 0x14 0x1 registers n 0x18 0x1 registers n 0x1C 0x1 registers n 0x20 0x1 registers n 0x24 0x1 registers n 0x30 0x1 registers n 0x4 0x1 registers n 0x8 0x1 registers n 0xC 0x1 registers n UCCR USB Clock Control Register 0x0 8 read-write n 0x0 0x0 UCEN USB clock output enable bit 0 read-write UCSEL USB clock selection bit 1 read-write UPCR1 USB-PLL Control Register 1 0x4 8 read-write n 0x0 0x0 UPINC USB-PLL input clock selection bit 1 read-write UPLLEN USB-PLL oscillation enable bit 0 read-write UPCR2 USB-PLL Control Register 2 0x8 8 read-write n 0x0 0x0 UPOWT USB-PLL oscillation stabilization wait time setting bit 0 2 read-write UPCR3 USB-PLL Control Register 3 0xC 8 read-write n 0x0 0x0 UPLLK Frequency division ratio (K) setting bit of the USB-PLL clock 0 4 read-write UPCR4 USB-PLL Control Register 4 0x10 8 read-write n 0x0 0x0 UPLLN Frequency division ratio (N) setting bit of the USB-PLL clock 0 4 read-write UPCR5 USB-PLL Control Register 5 0x24 8 read-write n 0x0 0x0 UPLLM Frequency division ratio (M) setting bit of the USB-PLL clock 0 3 read-write UPINT_CLR USB-PLL Interrupt Source Clear Register 0x1C 8 write-only n 0x0 0x0 UPCSC USB-PLL oscillation stabilization interrupt source clear bit 0 write-only UPINT_ENR USB-PLL Interrupt Source Enable Register 0x18 8 read-write n 0x0 0x0 UPCSE USB-PLL oscillation stabilization wait complete interrupt enable bit 0 read-write UPINT_STR USB-PLL Interrupt Source Status Register 0x20 8 read-only n 0x0 0x0 UPCSI USB-PLL interrupt source status bit 0 read-only UP_STR USB-PLL Status Register 0x14 8 read-only n 0x0 0x0 UPRDY USB-PLL oscillation stabilization bit 0 read-only USBEN USB Enable Register 0x30 8 read-write n 0x0 0x0 USBEN USB enable bit 0 read-write WC Watch Counter WC 0x0 0x0 0x3 registers n 0x10 0x2 registers n 0x14 0x1 registers n CLK_EN Division Clock Enable Register 0x14 8 read-write n 0x0 0x0 CLK_EN Division clock enable bit 0 read-write CLK_EN_R Division clock enable read bit 1 read-write CLK_SEL Clock Selection Register 0x10 16 read-write n 0x0 0x0 SEL_IN Input clock selection bit 0 read-write SEL_OUT Output clock selection bit 8 read-write WCCR Watch Counter Control Register 0x2 8 read-write n 0x0 0x0 CS Count clock select bits 2 1 read-write WCEN Watch counter operation enable bit 7 read-write WCIE Interrupt request enable bit 1 read-write WCIF Interrupt request flag bit 0 read-write WCOP Watch counter operating state flag 6 read-only WCRD Watch Counter Read Register 0x0 8 read-only n 0x0 0x0 CTR counter value 0 5 read-only WCRL Watch Counter Reload Register 0x1 8 read-write n 0x0 0x0 RLC reload value 0 5 read-write