Infineon MB9BF21xS 2024.04.28 MB9BF21xS 8 32 ADC0 ADC0 Registers ADC0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x4 registers n 0x20 0x1 registers n 0x24 0x1 registers n 0x26 0x2 registers n 0x28 0x2 registers n 0x2C 0x2 registers n 0x30 0x2 registers n 0x34 0x1 registers n 0x38 0x2 registers n 0x3C 0x1 registers n 0x8 0x2 registers n 0xC 0x4 registers n ADC0 25 ADCEN A/D Operation Enable Setup Register 0x3C 8 read-write n 0x0 0x0 CYCLSL Basic cycle selection bit 4 1 read-write ENBL A/D operation enable bit 0 read-write READY A/D operation enable state bit 1 read-only ADCR A/D Control Register 0x1 8 read-write n 0x0 0x0 CMPIE Conversion result comparison interrupt enable bit 1 read-write CMPIF Conversion result comparison interrupt request bit 5 read-write OVRIE FIFO overrun interrupt enable bit 0 read-write PCIE Priority conversion interrupt enable bit 2 read-write PCIF Priority conversion interrupt request bit 6 read-write SCIE Scan conversion interrupt enable bit 3 read-write SCIF Scan conversion interrupt request bit 7 read-write ADCT Comparison Time Setup Register 0x34 8 read-write n 0x0 0x0 CT Compare clock frequency division ratio setting bits 0 7 read-write ADSR A/D Status Register 0x0 8 read-write n 0x0 0x0 ADSTP A/D conversion forced stop bit 7 read-write FDAS FIFO data placement selection bit 6 read-write PCNS Priority conversion pending flag 2 read-write PCS Priority conversion status flag 1 read-write SCS Scan conversion status flag 0 read-write ADSS0 Sampling Time Selection Register 0 0x2C 8 read-write n 0x0 0x0 TS0 Bit0 of ADSS0 0 read-write TS1 Bit1 of ADSS0 1 read-write TS2 Bit2 of ADSS0 2 read-write TS3 Bit3 of ADSS0 3 read-write TS4 Bit4 of ADSS0 4 read-write TS5 Bit5 of ADSS0 5 read-write TS6 Bit6 of ADSS0 6 read-write TS7 Bit7 of ADSS0 7 read-write ADSS1 Sampling Time Selection Register 1 0x2D 8 read-write n 0x0 0x0 TS10 Bit2 of ADSS1 2 read-write TS11 Bit3 of ADSS1 3 read-write TS12 Bit4 of ADSS1 4 read-write TS13 Bit5 of ADSS1 5 read-write TS14 Bit6 of ADSS1 6 read-write TS15 Bit7 of ADSS1 7 read-write TS8 Bit0 of ADSS1 0 read-write TS9 Bit1 of ADSS1 1 read-write ADSS2 Sampling Time Selection Register 2 0x28 8 read-write n 0x0 0x0 TS16 Bit0 of ADSS2 0 read-write TS17 Bit1 of ADSS2 1 read-write TS18 Bit2 of ADSS2 2 read-write TS19 Bit3 of ADSS2 3 read-write TS20 Bit4 of ADSS2 4 read-write TS21 Bit5 of ADSS2 5 read-write TS22 Bit6 of ADSS2 6 read-write TS23 Bit7 of ADSS2 7 read-write ADSS3 Sampling Time Selection Register 3 0x29 8 read-write n 0x0 0x0 TS24 Bit0 of ADSS3 0 read-write TS25 Bit1 of ADSS3 1 read-write TS26 Bit2 of ADSS3 2 read-write TS27 Bit3 of ADSS3 3 read-write TS28 Bit4 of ADSS3 4 read-write TS29 Bit5 of ADSS3 5 read-write TS30 Bit6 of ADSS3 6 read-write TS31 Bit7 of ADSS3 7 read-write ADST0 Sampling Time Setup Register 0 0x31 8 read-write n 0x0 0x0 ST Sampling time setting bits 0 4 read-write ST0 Sampling time setting bits 0 4 read-write STX0 Sampling time N times setting bits 5 2 read-write ADST1 Sampling Time Setup Register 1 0x30 8 read-write n 0x0 0x0 ST Sampling time setting bits 0 4 read-write ST1 Sampling time setting bits 0 4 read-write STX1 Sampling time N times setting bits 5 2 read-write CMPCR A/D Comparison Control Register 0x24 8 read-write n 0x0 0x0 CCH Comparison mode 0 0 4 read-write CMD Comparison mode 1 5 1 read-write CMD0 Comparison mode 0 5 read-write CMD1 Comparison mode 1 6 read-write CMPEN Conversion result comparison function operation enable bit 7 read-write CMPD A/D Comparison Value Setup Register 0x26 16 read-write n 0x0 0x0 CMAD A/D conversion result value setting bits 6 9 read-write PCCR Priority Conversion Control Register 0x19 8 read-write n 0x0 0x0 ESCE External trigger analog input selection bit 3 read-write PEEN Priority conversion external start enable bit 2 read-write PEMP Priority conversion FIFO empty bit 7 read-only PFCLR Priority conversion FIFO clear bit 4 read-write PFUL Priority conversion FIFO full bit 6 read-only PHEN Priority conversion timer start enable bit 1 read-write POVR Priority conversion overrun flag 5 read-write PSTR Priority conversion start bit 0 read-write PCFD Priority Conversion FIFO Data Register 0x1C 32 read-only n 0x0 0x0 INVL A/D conversion result disable bit 12 read-only PC Conversion input channel bits 0 4 read-only PD Priority conversion result 20 11 read-only RS Scan conversion start factor 8 1 read-only PCIS Priority Conversion Input Selection Register 0x20 8 read-write n 0x0 0x0 P1A Priority level 1 analog input selection 0 2 read-write P2A Priority level 2 analog input selection 3 4 read-write PFNS Priority Conversion FIFO Stage Count Setup Register 0x18 8 read-write n 0x0 0x0 PFS Priority conversion FIFO stage count setting bits 0 1 read-write TEST Test bits 4 1 read-only PRTSL Priority Conversion Timer Trigger Selection Register 0x38 8 read-write n 0x0 0x0 PRTSL Priority conversion timer trigger selection bit 0 3 read-write SCCR Scan Conversion Control Register 0x9 8 read-write n 0x0 0x0 RPT Scan conversion repeat bit 2 read-write SEMP Scan conversion FIFO empty bit 7 read-only SFCLR Scan conversion FIFO clear bit 4 read-write SFUL Scan conversion FIFO full bit 6 read-only SHEN Scan conversion timer start enable bit 1 read-write SOVR Scan conversion overrun flag 5 read-write SSTR Scan conversion start bit 0 read-write SCFD Scan Conversion FIFO Data Register 0xC 32 read-only n 0x0 0x0 CS Conversion input channel bits 0 4 read-only INVL A/D conversion result disable bit 12 read-only RS Scan conversion start factor 8 1 read-only SC Conversion input channel bits 0 4 read-only SD Scan conversion result 20 11 read-only SCIS0 Scan Conversion Input Selection Register 0 0x14 8 read-write n 0x0 0x0 AN0 Bit0 of SCIS0 0 read-write AN1 Bit1 of SCIS0 1 read-write AN2 Bit2 of SCIS0 2 read-write AN3 Bit3 of SCIS0 3 read-write AN4 Bit4 of SCIS0 4 read-write AN5 Bit5 of SCIS0 5 read-write AN6 Bit6 of SCIS0 6 read-write AN7 Bit7 of SCIS0 7 read-write SCIS1 Scan Conversion Input Selection Register 1 0x15 8 read-write n 0x0 0x0 AN10 Bit2 of SCIS1 2 read-write AN11 Bit3 of SCIS1 3 read-write AN12 Bit4 of SCIS1 4 read-write AN13 Bit5 of SCIS1 5 read-write AN14 Bit6 of SCIS1 6 read-write AN15 Bit7 of SCIS1 7 read-write AN8 Bit0 of SCIS1 0 read-write AN9 Bit1 of SCIS1 1 read-write SCIS2 Scan Conversion Input Selection Register 2 0x10 8 read-write n 0x0 0x0 AN16 Bit0 of SCIS2 0 read-write AN17 Bit1 of SCIS2 1 read-write AN18 Bit2 of SCIS2 2 read-write AN19 Bit3 of SCIS2 3 read-write AN20 Bit4 of SCIS2 4 read-write AN21 Bit5 of SCIS2 5 read-write AN22 Bit6 of SCIS2 6 read-write AN23 Bit7 of SCIS2 7 read-write SCIS3 Scan Conversion Input Selection Register 3 0x11 8 read-write n 0x0 0x0 AN24 Bit0 of SCIS3 0 read-write AN25 Bit1 of SCIS3 1 read-write AN26 Bit2 of SCIS3 2 read-write AN27 Bit3 of SCIS3 3 read-write AN28 Bit4 of SCIS3 4 read-write AN29 Bit5 of SCIS3 5 read-write AN30 Bit6 of SCIS3 6 read-write AN31 Bit7 of SCIS3 7 read-write SCTSL Scan Conversion Timer Trigger Selection Register 0x39 8 read-write n 0x0 0x0 SCTSL Scan conversion timer trigger selection bit 0 3 read-write SFNS Scan Conversion FIFO Stage Count Setup Register 0x8 8 read-write n 0x0 0x0 SFS Scan conversion FIFO stage count setting bit 0 3 read-write ADC1 ADC0 Registers ADC0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x4 registers n 0x20 0x1 registers n 0x24 0x1 registers n 0x26 0x2 registers n 0x28 0x2 registers n 0x2C 0x2 registers n 0x30 0x2 registers n 0x34 0x1 registers n 0x38 0x2 registers n 0x3C 0x1 registers n 0x8 0x2 registers n 0xC 0x4 registers n ADC1 26 ADCEN A/D Operation Enable Setup Register 0x3C 8 read-write n 0x0 0x0 CYCLSL Basic cycle selection bit 4 1 read-write ENBL A/D operation enable bit 0 read-write READY A/D operation enable state bit 1 read-only ADCR A/D Control Register 0x1 8 read-write n 0x0 0x0 CMPIE Conversion result comparison interrupt enable bit 1 read-write CMPIF Conversion result comparison interrupt request bit 5 read-write OVRIE FIFO overrun interrupt enable bit 0 read-write PCIE Priority conversion interrupt enable bit 2 read-write PCIF Priority conversion interrupt request bit 6 read-write SCIE Scan conversion interrupt enable bit 3 read-write SCIF Scan conversion interrupt request bit 7 read-write ADCT Comparison Time Setup Register 0x34 8 read-write n 0x0 0x0 CT Compare clock frequency division ratio setting bits 0 7 read-write ADSR A/D Status Register 0x0 8 read-write n 0x0 0x0 ADSTP A/D conversion forced stop bit 7 read-write FDAS FIFO data placement selection bit 6 read-write PCNS Priority conversion pending flag 2 read-write PCS Priority conversion status flag 1 read-write SCS Scan conversion status flag 0 read-write ADSS0 Sampling Time Selection Register 0 0x2C 8 read-write n 0x0 0x0 TS0 Bit0 of ADSS0 0 read-write TS1 Bit1 of ADSS0 1 read-write TS2 Bit2 of ADSS0 2 read-write TS3 Bit3 of ADSS0 3 read-write TS4 Bit4 of ADSS0 4 read-write TS5 Bit5 of ADSS0 5 read-write TS6 Bit6 of ADSS0 6 read-write TS7 Bit7 of ADSS0 7 read-write ADSS1 Sampling Time Selection Register 1 0x2D 8 read-write n 0x0 0x0 TS10 Bit2 of ADSS1 2 read-write TS11 Bit3 of ADSS1 3 read-write TS12 Bit4 of ADSS1 4 read-write TS13 Bit5 of ADSS1 5 read-write TS14 Bit6 of ADSS1 6 read-write TS15 Bit7 of ADSS1 7 read-write TS8 Bit0 of ADSS1 0 read-write TS9 Bit1 of ADSS1 1 read-write ADSS2 Sampling Time Selection Register 2 0x28 8 read-write n 0x0 0x0 TS16 Bit0 of ADSS2 0 read-write TS17 Bit1 of ADSS2 1 read-write TS18 Bit2 of ADSS2 2 read-write TS19 Bit3 of ADSS2 3 read-write TS20 Bit4 of ADSS2 4 read-write TS21 Bit5 of ADSS2 5 read-write TS22 Bit6 of ADSS2 6 read-write TS23 Bit7 of ADSS2 7 read-write ADSS3 Sampling Time Selection Register 3 0x29 8 read-write n 0x0 0x0 TS24 Bit0 of ADSS3 0 read-write TS25 Bit1 of ADSS3 1 read-write TS26 Bit2 of ADSS3 2 read-write TS27 Bit3 of ADSS3 3 read-write TS28 Bit4 of ADSS3 4 read-write TS29 Bit5 of ADSS3 5 read-write TS30 Bit6 of ADSS3 6 read-write TS31 Bit7 of ADSS3 7 read-write ADST0 Sampling Time Setup Register 0 0x31 8 read-write n 0x0 0x0 ST Sampling time setting bits 0 4 read-write ST0 Sampling time setting bits 0 4 read-write STX0 Sampling time N times setting bits 5 2 read-write ADST1 Sampling Time Setup Register 1 0x30 8 read-write n 0x0 0x0 ST Sampling time setting bits 0 4 read-write ST1 Sampling time setting bits 0 4 read-write STX1 Sampling time N times setting bits 5 2 read-write CMPCR A/D Comparison Control Register 0x24 8 read-write n 0x0 0x0 CCH Comparison mode 0 0 4 read-write CMD Comparison mode 1 5 1 read-write CMD0 Comparison mode 0 5 read-write CMD1 Comparison mode 1 6 read-write CMPEN Conversion result comparison function operation enable bit 7 read-write CMPD A/D Comparison Value Setup Register 0x26 16 read-write n 0x0 0x0 CMAD A/D conversion result value setting bits 6 9 read-write PCCR Priority Conversion Control Register 0x19 8 read-write n 0x0 0x0 ESCE External trigger analog input selection bit 3 read-write PEEN Priority conversion external start enable bit 2 read-write PEMP Priority conversion FIFO empty bit 7 read-only PFCLR Priority conversion FIFO clear bit 4 read-write PFUL Priority conversion FIFO full bit 6 read-only PHEN Priority conversion timer start enable bit 1 read-write POVR Priority conversion overrun flag 5 read-write PSTR Priority conversion start bit 0 read-write PCFD Priority Conversion FIFO Data Register 0x1C 32 read-only n 0x0 0x0 INVL A/D conversion result disable bit 12 read-only PC Conversion input channel bits 0 4 read-only PD Priority conversion result 20 11 read-only RS Scan conversion start factor 8 1 read-only PCIS Priority Conversion Input Selection Register 0x20 8 read-write n 0x0 0x0 P1A Priority level 1 analog input selection 0 2 read-write P2A Priority level 2 analog input selection 3 4 read-write PFNS Priority Conversion FIFO Stage Count Setup Register 0x18 8 read-write n 0x0 0x0 PFS Priority conversion FIFO stage count setting bits 0 1 read-write TEST Test bits 4 1 read-only PRTSL Priority Conversion Timer Trigger Selection Register 0x38 8 read-write n 0x0 0x0 PRTSL Priority conversion timer trigger selection bit 0 3 read-write SCCR Scan Conversion Control Register 0x9 8 read-write n 0x0 0x0 RPT Scan conversion repeat bit 2 read-write SEMP Scan conversion FIFO empty bit 7 read-only SFCLR Scan conversion FIFO clear bit 4 read-write SFUL Scan conversion FIFO full bit 6 read-only SHEN Scan conversion timer start enable bit 1 read-write SOVR Scan conversion overrun flag 5 read-write SSTR Scan conversion start bit 0 read-write SCFD Scan Conversion FIFO Data Register 0xC 32 read-only n 0x0 0x0 CS Conversion input channel bits 0 4 read-only INVL A/D conversion result disable bit 12 read-only RS Scan conversion start factor 8 1 read-only SC Conversion input channel bits 0 4 read-only SD Scan conversion result 20 11 read-only SCIS0 Scan Conversion Input Selection Register 0 0x14 8 read-write n 0x0 0x0 AN0 Bit0 of SCIS0 0 read-write AN1 Bit1 of SCIS0 1 read-write AN2 Bit2 of SCIS0 2 read-write AN3 Bit3 of SCIS0 3 read-write AN4 Bit4 of SCIS0 4 read-write AN5 Bit5 of SCIS0 5 read-write AN6 Bit6 of SCIS0 6 read-write AN7 Bit7 of SCIS0 7 read-write SCIS1 Scan Conversion Input Selection Register 1 0x15 8 read-write n 0x0 0x0 AN10 Bit2 of SCIS1 2 read-write AN11 Bit3 of SCIS1 3 read-write AN12 Bit4 of SCIS1 4 read-write AN13 Bit5 of SCIS1 5 read-write AN14 Bit6 of SCIS1 6 read-write AN15 Bit7 of SCIS1 7 read-write AN8 Bit0 of SCIS1 0 read-write AN9 Bit1 of SCIS1 1 read-write SCIS2 Scan Conversion Input Selection Register 2 0x10 8 read-write n 0x0 0x0 AN16 Bit0 of SCIS2 0 read-write AN17 Bit1 of SCIS2 1 read-write AN18 Bit2 of SCIS2 2 read-write AN19 Bit3 of SCIS2 3 read-write AN20 Bit4 of SCIS2 4 read-write AN21 Bit5 of SCIS2 5 read-write AN22 Bit6 of SCIS2 6 read-write AN23 Bit7 of SCIS2 7 read-write SCIS3 Scan Conversion Input Selection Register 3 0x11 8 read-write n 0x0 0x0 AN24 Bit0 of SCIS3 0 read-write AN25 Bit1 of SCIS3 1 read-write AN26 Bit2 of SCIS3 2 read-write AN27 Bit3 of SCIS3 3 read-write AN28 Bit4 of SCIS3 4 read-write AN29 Bit5 of SCIS3 5 read-write AN30 Bit6 of SCIS3 6 read-write AN31 Bit7 of SCIS3 7 read-write SCTSL Scan Conversion Timer Trigger Selection Register 0x39 8 read-write n 0x0 0x0 SCTSL Scan conversion timer trigger selection bit 0 3 read-write SFNS Scan Conversion FIFO Stage Count Setup Register 0x8 8 read-write n 0x0 0x0 SFS Scan conversion FIFO stage count setting bit 0 3 read-write ADC2 ADC0 Registers ADC0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x4 registers n 0x20 0x1 registers n 0x24 0x1 registers n 0x26 0x2 registers n 0x28 0x2 registers n 0x2C 0x2 registers n 0x30 0x2 registers n 0x34 0x1 registers n 0x38 0x2 registers n 0x3C 0x1 registers n 0x8 0x2 registers n 0xC 0x4 registers n ADC2 27 ADCEN A/D Operation Enable Setup Register 0x3C 8 read-write n 0x0 0x0 CYCLSL Basic cycle selection bit 4 1 read-write ENBL A/D operation enable bit 0 read-write READY A/D operation enable state bit 1 read-only ADCR A/D Control Register 0x1 8 read-write n 0x0 0x0 CMPIE Conversion result comparison interrupt enable bit 1 read-write CMPIF Conversion result comparison interrupt request bit 5 read-write OVRIE FIFO overrun interrupt enable bit 0 read-write PCIE Priority conversion interrupt enable bit 2 read-write PCIF Priority conversion interrupt request bit 6 read-write SCIE Scan conversion interrupt enable bit 3 read-write SCIF Scan conversion interrupt request bit 7 read-write ADCT Comparison Time Setup Register 0x34 8 read-write n 0x0 0x0 CT Compare clock frequency division ratio setting bits 0 7 read-write ADSR A/D Status Register 0x0 8 read-write n 0x0 0x0 ADSTP A/D conversion forced stop bit 7 read-write FDAS FIFO data placement selection bit 6 read-write PCNS Priority conversion pending flag 2 read-write PCS Priority conversion status flag 1 read-write SCS Scan conversion status flag 0 read-write ADSS0 Sampling Time Selection Register 0 0x2C 8 read-write n 0x0 0x0 TS0 Bit0 of ADSS0 0 read-write TS1 Bit1 of ADSS0 1 read-write TS2 Bit2 of ADSS0 2 read-write TS3 Bit3 of ADSS0 3 read-write TS4 Bit4 of ADSS0 4 read-write TS5 Bit5 of ADSS0 5 read-write TS6 Bit6 of ADSS0 6 read-write TS7 Bit7 of ADSS0 7 read-write ADSS1 Sampling Time Selection Register 1 0x2D 8 read-write n 0x0 0x0 TS10 Bit2 of ADSS1 2 read-write TS11 Bit3 of ADSS1 3 read-write TS12 Bit4 of ADSS1 4 read-write TS13 Bit5 of ADSS1 5 read-write TS14 Bit6 of ADSS1 6 read-write TS15 Bit7 of ADSS1 7 read-write TS8 Bit0 of ADSS1 0 read-write TS9 Bit1 of ADSS1 1 read-write ADSS2 Sampling Time Selection Register 2 0x28 8 read-write n 0x0 0x0 TS16 Bit0 of ADSS2 0 read-write TS17 Bit1 of ADSS2 1 read-write TS18 Bit2 of ADSS2 2 read-write TS19 Bit3 of ADSS2 3 read-write TS20 Bit4 of ADSS2 4 read-write TS21 Bit5 of ADSS2 5 read-write TS22 Bit6 of ADSS2 6 read-write TS23 Bit7 of ADSS2 7 read-write ADSS3 Sampling Time Selection Register 3 0x29 8 read-write n 0x0 0x0 TS24 Bit0 of ADSS3 0 read-write TS25 Bit1 of ADSS3 1 read-write TS26 Bit2 of ADSS3 2 read-write TS27 Bit3 of ADSS3 3 read-write TS28 Bit4 of ADSS3 4 read-write TS29 Bit5 of ADSS3 5 read-write TS30 Bit6 of ADSS3 6 read-write TS31 Bit7 of ADSS3 7 read-write ADST0 Sampling Time Setup Register 0 0x31 8 read-write n 0x0 0x0 ST Sampling time setting bits 0 4 read-write ST0 Sampling time setting bits 0 4 read-write STX0 Sampling time N times setting bits 5 2 read-write ADST1 Sampling Time Setup Register 1 0x30 8 read-write n 0x0 0x0 ST Sampling time setting bits 0 4 read-write ST1 Sampling time setting bits 0 4 read-write STX1 Sampling time N times setting bits 5 2 read-write CMPCR A/D Comparison Control Register 0x24 8 read-write n 0x0 0x0 CCH Comparison mode 0 0 4 read-write CMD Comparison mode 1 5 1 read-write CMD0 Comparison mode 0 5 read-write CMD1 Comparison mode 1 6 read-write CMPEN Conversion result comparison function operation enable bit 7 read-write CMPD A/D Comparison Value Setup Register 0x26 16 read-write n 0x0 0x0 CMAD A/D conversion result value setting bits 6 9 read-write PCCR Priority Conversion Control Register 0x19 8 read-write n 0x0 0x0 ESCE External trigger analog input selection bit 3 read-write PEEN Priority conversion external start enable bit 2 read-write PEMP Priority conversion FIFO empty bit 7 read-only PFCLR Priority conversion FIFO clear bit 4 read-write PFUL Priority conversion FIFO full bit 6 read-only PHEN Priority conversion timer start enable bit 1 read-write POVR Priority conversion overrun flag 5 read-write PSTR Priority conversion start bit 0 read-write PCFD Priority Conversion FIFO Data Register 0x1C 32 read-only n 0x0 0x0 INVL A/D conversion result disable bit 12 read-only PC Conversion input channel bits 0 4 read-only PD Priority conversion result 20 11 read-only RS Scan conversion start factor 8 1 read-only PCIS Priority Conversion Input Selection Register 0x20 8 read-write n 0x0 0x0 P1A Priority level 1 analog input selection 0 2 read-write P2A Priority level 2 analog input selection 3 4 read-write PFNS Priority Conversion FIFO Stage Count Setup Register 0x18 8 read-write n 0x0 0x0 PFS Priority conversion FIFO stage count setting bits 0 1 read-write TEST Test bits 4 1 read-only PRTSL Priority Conversion Timer Trigger Selection Register 0x38 8 read-write n 0x0 0x0 PRTSL Priority conversion timer trigger selection bit 0 3 read-write SCCR Scan Conversion Control Register 0x9 8 read-write n 0x0 0x0 RPT Scan conversion repeat bit 2 read-write SEMP Scan conversion FIFO empty bit 7 read-only SFCLR Scan conversion FIFO clear bit 4 read-write SFUL Scan conversion FIFO full bit 6 read-only SHEN Scan conversion timer start enable bit 1 read-write SOVR Scan conversion overrun flag 5 read-write SSTR Scan conversion start bit 0 read-write SCFD Scan Conversion FIFO Data Register 0xC 32 read-only n 0x0 0x0 CS Conversion input channel bits 0 4 read-only INVL A/D conversion result disable bit 12 read-only RS Scan conversion start factor 8 1 read-only SC Conversion input channel bits 0 4 read-only SD Scan conversion result 20 11 read-only SCIS0 Scan Conversion Input Selection Register 0 0x14 8 read-write n 0x0 0x0 AN0 Bit0 of SCIS0 0 read-write AN1 Bit1 of SCIS0 1 read-write AN2 Bit2 of SCIS0 2 read-write AN3 Bit3 of SCIS0 3 read-write AN4 Bit4 of SCIS0 4 read-write AN5 Bit5 of SCIS0 5 read-write AN6 Bit6 of SCIS0 6 read-write AN7 Bit7 of SCIS0 7 read-write SCIS1 Scan Conversion Input Selection Register 1 0x15 8 read-write n 0x0 0x0 AN10 Bit2 of SCIS1 2 read-write AN11 Bit3 of SCIS1 3 read-write AN12 Bit4 of SCIS1 4 read-write AN13 Bit5 of SCIS1 5 read-write AN14 Bit6 of SCIS1 6 read-write AN15 Bit7 of SCIS1 7 read-write AN8 Bit0 of SCIS1 0 read-write AN9 Bit1 of SCIS1 1 read-write SCIS2 Scan Conversion Input Selection Register 2 0x10 8 read-write n 0x0 0x0 AN16 Bit0 of SCIS2 0 read-write AN17 Bit1 of SCIS2 1 read-write AN18 Bit2 of SCIS2 2 read-write AN19 Bit3 of SCIS2 3 read-write AN20 Bit4 of SCIS2 4 read-write AN21 Bit5 of SCIS2 5 read-write AN22 Bit6 of SCIS2 6 read-write AN23 Bit7 of SCIS2 7 read-write SCIS3 Scan Conversion Input Selection Register 3 0x11 8 read-write n 0x0 0x0 AN24 Bit0 of SCIS3 0 read-write AN25 Bit1 of SCIS3 1 read-write AN26 Bit2 of SCIS3 2 read-write AN27 Bit3 of SCIS3 3 read-write AN28 Bit4 of SCIS3 4 read-write AN29 Bit5 of SCIS3 5 read-write AN30 Bit6 of SCIS3 6 read-write AN31 Bit7 of SCIS3 7 read-write SCTSL Scan Conversion Timer Trigger Selection Register 0x39 8 read-write n 0x0 0x0 SCTSL Scan conversion timer trigger selection bit 0 3 read-write SFNS Scan Conversion FIFO Stage Count Setup Register 0x8 8 read-write n 0x0 0x0 SFS Scan conversion FIFO stage count setting bit 0 3 read-write BT0 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n BTIM0_7 31 PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT1 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT10 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT11 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT12 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT13 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT14 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT15 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT2 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT3 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT4 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT5 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT6 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT7 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT8 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BT9 Base Timer 0 BT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n PPG_PRLH HIGH Width Reload Register PPG 0x4 16 read-write n 0x0 0x0 PPG_PRLL LOW Width Reload Register PPG 0x0 16 read-write n 0x0 0x0 PPG_STC Status Control Register PPG 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PPG_TMCR Timer Control Register PPG 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PPG_TMCR2 Timer Control Register 2 PPG 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 1 read-write PPG_TMR Timer Register PPG 0x8 16 read-only n 0x0 0x0 PWC_DTBF Data Buffer Register PWC 0x4 16 read-only n 0x0 0x0 PWC_STC Status Control Register PWC 0x10 8 read-write n 0x0 0x0 EDIE Measurement completion interrupt request enable bit 6 read-write EDIR Measurement completion interrupt request bit 2 read-only ERR Error flag bit 7 read-only OVIE Overflow interrupt request enable bit 4 read-write OVIR Overflow interrupt request bit 0 read-write PWC_TMCR Timer Control Register PWC 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Measurement edge selection bits 8 2 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write T32 32-bit timer selection bit 7 read-write PWC_TMCR2 Timer Control Register 2 PWC 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_PCSR PWM Cycle Set Register PWM 0x0 16 read-write n 0x0 0x0 PWM_PDUT PWM Duty Set Register PWM 0x4 16 read-write n 0x0 0x0 PWM_STC Status Control Register PWM 0x10 8 read-write n 0x0 0x0 DTIE Duty match interrupt request enable bit 5 read-write DTIR Duty match interrupt request bit 1 read-write TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write PWM_TMCR Timer Control Register PWM 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Count operation enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write PMSK Pulse output mask bit 10 read-write RTGEN Restart enable bit 11 read-write STRG Software trigger bit 0 read-write PWM_TMCR2 Timer Control Register 2 PWM 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write PWM_TMR Timer Register PWM 0x8 16 read-only n 0x0 0x0 RT_PCSR PWM Cycle Set Register RT 0x0 16 read-write n 0x0 0x0 RT_STC Status Control Register RT 0x10 8 read-write n 0x0 0x0 TGIE Trigger interrupt request enable bit 6 read-write TGIR Trigger interrupt request bit 2 read-write UDIE Underflow interrupt request enable bit 4 read-write UDIR Underflow interrupt request bit 0 read-write RT_TMCR Timer Control Register RT 0xC 16 read-write n 0x0 0x0 CKS2_0 Count clock selection bit 12 2 read-write CTEN Timer enable bit 1 read-write EGS Trigger input edge selection bits 8 1 read-write FMD Timer function selection bits 4 2 read-write MDSE Mode selection bit 2 read-write OSEL Output polarity specification bit 3 read-write STRG Software trigger bit 0 read-write T32 32-bit timer selection bit 7 read-write RT_TMCR2 Timer Control Register 2 RT 0x11 8 read-write n 0x0 0x0 CKS3 Count clock selection bit 0 read-write RT_TMR Timer Register RT 0x8 16 read-only n 0x0 0x0 BTIOSEL03 Base Timer I/O Select BTIOSEL03 0x0 0x0 0x2 registers n BTSEL0123 I/O Select Register 0x0 16 read-write n 0x0 0x0 SEL01_ I/O select bits for Ch.0/Ch.1 8 3 read-write SEL23_ I/O select bits for Ch.2/Ch.3 12 3 read-write BTIOSEL47 Base Timer I/O Select BTIOSEL47 0x0 0x0 0x2 registers n BTSEL4567 I/O Select Register 0x0 16 read-write n 0x0 0x0 SEL45_ I/O select bits for Ch.4/Ch.5 8 3 read-write SEL67_ I/O select bits for Ch.6/Ch.7 12 3 read-write BTIOSEL8B Base Timer I/O Select BTIOSEL8B 0x0 0x0 0x2 registers n BTSEL89AB I/O Select Register 0x0 16 read-write n 0x0 0x0 SEL89_ I/O select bits for Ch.8/Ch.9 8 3 read-write SELAB_ I/O select bits for Ch.A/Ch.B 12 3 read-write BTIOSELCF Base Timer I/O Select BTIOSELCF 0x0 0x0 0x2 registers n BTSELCDEF I/O Select Register 0x0 16 read-write n 0x0 0x0 SELCD_ I/O select bits for Ch.C/Ch.D 8 3 read-write SELEF_ I/O select bits for Ch.E/Ch.F 12 3 read-write CRC CRC Registers CRC 0x0 0x0 0x1 registers n 0x4 0x4 registers n 0x4 0x1 registers n 0x8 0x4 registers n 0xC 0x4 registers n CRCCR CRC Control Register 0x0 8 read-write n 0x0 0x0 CRC32 Byte-order setting bit 1 read-write CRCLSF Final XOR control bit 5 read-write CRCLTE CRC result bit-order setting bit 4 read-write FXOR Initialization bit 6 read-write INIT CRC mode selection bit 0 read-write LSBFST CRC result byte-order setting bit 3 read-write LTLEND Bit-order setting bit 2 read-write CRCIN Input Data Register 0x8 32 read-write n 0x0 0x0 D Input data 0 31 read-write CRCINIT Initial Value Register 0x4 32 read-write n 0x0 0x0 D Initial value 0 31 read-write CRCR CRC Register 0xC 32 read-only n 0x0 0x0 D CRC Data 0 31 read-only CRG Clock Unit Registers CRG 0x0 0x0 0x1 registers n 0x10 0x1 registers n 0x14 0x1 registers n 0x18 0x1 registers n 0x1C 0x1 registers n 0x20 0x1 registers n 0x28 0x1 registers n 0x30 0x1 registers n 0x34 0x1 registers n 0x38 0x1 registers n 0x3C 0x1 registers n 0x4 0x1 registers n 0x40 0x2 registers n 0x44 0x1 registers n 0x48 0x2 registers n 0x4C 0x2 registers n 0x50 0x2 registers n 0x54 0x1 registers n 0x60 0x1 registers n 0x64 0x1 registers n 0x68 0x1 registers n 0x8 0x6 registers n CSV 0 OSC_PLL_WC 24 APBC0_PSR APB0 Prescaler Register 0x14 8 read-write n 0x0 0x0 APBC0 APB0 bus clock frequency division ratio setting bit 0 1 read-write APBC1_PSR APB1 Prescaler Register 0x18 8 read-write n 0x0 0x0 APBC1 APB1 bus clock frequency division ratio setting bit 0 1 read-write APBC1EN APB1 clock enable bit 7 read-write APBC1RST APB1 bus reset control bit 4 read-write APBC2_PSR APB2 Prescaler Register 0x1C 8 read-write n 0x0 0x0 APBC2 APB2 bus clock frequency division ratio setting bit 0 1 read-write APBC2EN APB2 clock enable bit 7 read-write APBC2RST APB2 bus reset control bit 4 read-write BSC_PSR Base Clock Prescaler Register 0x10 8 read-write n 0x0 0x0 BSR Base clock frequency division ratio setting bit 0 2 read-write CSV_CTL CSV control register 0x40 16 read-write n 0x0 0x0 FCD FCS count cycle setting bits 12 2 read-write FCSDE FCS function enable bit 8 read-write FCSRE FCS reset output enable bit 9 read-write MCSVE Main CSV function enable bit 0 read-write SCSVE Sub CSV function enable bit 1 read-write CSV_STR CSV status register 0x44 8 read-only n 0x0 0x0 MCMF Main clock failure detection flag 0 read-only SCMF Sub clock failure detection flag 1 read-only CSW_TMR Clock Stabilization Wait Time Register 0x30 8 read-write n 0x0 0x0 MOWT Main clock stabilization wait time setup bit 0 3 read-write SOWT Sub clock stabilization wait time setup bit 4 2 read-write DBWDT_CTL Debug Break Watchdog Timer Control Register 0x54 8 read-write n 0x0 0x0 DPHWBE HW-WDG debug mode break bit 7 read-write DPSWBE SW-WDG debug mode break bit 5 read-write FCSWD_CTL Frequency detection counter register 0x50 16 read-only n 0x0 0x0 FCSWH_CTL Frequency detection window setting register 0x48 16 read-write n 0x0 0x0 FCSWL_CTL Frequency detection window setting register 0x4C 16 read-write n 0x0 0x0 INT_CLR Interrupt Clear Register 0x68 8 write-only n 0x0 0x0 FCSC Anomalous frequency detection interrupt cause clear bit 5 write-only MCSC Main oscillation stabilization completion interrupt cause clear bit 0 write-only PCSC PLL oscillation stabilization completion interrupt cause clear bit 2 write-only SCSC Sub oscillation stabilization completion interrupt cause clear bit 1 write-only INT_ENR Interrupt Enable Register 0x60 8 read-write n 0x0 0x0 FCSE Anomalous frequency detection interrupt enable bit 5 read-write MCSE Main oscillation stabilization completion interrupt enable bit 0 read-write PCSE PLL oscillation stabilization completion interrupt enable bit 2 read-write SCSE Sub oscillation stabilization completion interrupt enable bit 1 read-write INT_STR Interrupt Status Register 0x64 8 read-only n 0x0 0x0 FCSI Anomalous frequency detection interrupt status bit 5 read-only MCSI Main oscillation stabilization completion interrupt status bit 0 read-only PCSI PLL oscillation stabilization completion interrupt status bit 2 read-only SCSI Sub oscillation stabilization completion interrupt status bit 1 read-only PLL_CTL1 PLL Control Register 1 0x38 8 read-write n 0x0 0x0 PLLK PLL input clock frequency division ratio setting bit 4 3 read-write PLLM PLL VCO clock frequency division ratio setting bit 0 3 read-write PLL_CTL2 PLL Control Register 2 0x3C 8 read-write n 0x0 0x0 PLLN PLL feedback frequency division ratio setting bit 0 5 read-write PSW_TMR PLL Clock Stabilization Wait Time Setup Register 0x34 8 read-write n 0x0 0x0 PINC PLL input clock select bit 4 read-write POWT PLL clock stabilization wait time setup bit 0 2 read-write RST_STR Reset Cause Register 0xC 16 read-only n 0x0 0x0 CSVR Clock failure detection reset flag 6 read-only FCSR Flag for anomalous frequency detection reset 7 read-only HWDG Hardware watchdog reset flag 5 read-only HWDT Hardware watchdog reset flag 5 read-only INITX INITX pin input reset flag 1 read-only PONR Power-on reset/low-voltage detection reset flag 0 read-only SRST Software reset flag 8 read-only SWDG Software watchdog reset flag 4 read-only SWDT Software watchdog reset flag 4 read-only SCM_CTL System Clock Mode Control Register 0x0 8 read-write n 0x0 0x0 MOSCE Main clock oscillation enable bit 1 read-write PLLE PLL oscillation enable bit 4 read-write RCS Master clock switch control bits 5 2 read-write SOSCE Sub clock oscillation enable bit 3 read-write SCM_STR System Clock Mode Status Register 0x4 8 read-only n 0x0 0x0 MORDY Main clock oscillation stable bit 1 read-only PLRDY PLL oscillation stable bit 4 read-only RCM Master clock selection bits 5 2 read-only SORDY Sub clock oscillation stable bit 3 read-only STB_CTL Standby Mode Control Register 0x8 32 read-write n 0x0 0x0 KEY Standby mode control write control bit 16 15 read-write SPL Standby pin level setting bit 4 read-write STM Standby mode selection bit 0 1 read-write SWC_PSR Software Watchdog Clock Prescaler Register 0x20 8 read-write n 0x0 0x0 SWDS Software watchdog clock frequency division ratio setting bit 0 1 read-write TESTB TEST bit 7 read-write TTC_PSR Trace Clock Prescaler Register 0x28 8 read-write n 0x0 0x0 TTC Trace clock frequency division ratio setting bit 0 1 read-write CRTRIM CR Trimming Registers CRTRIM 0x0 0x0 0x1 registers n 0x4 0x2 registers n 0xC 0x4 registers n MCR_FTRM High-speed CR oscillation Frequency Trimming Register 0x4 16 read-write n 0x0 0x0 TRD Frequency trimming setup bits 0 7 read-write MCR_PSR High-speed CR oscillation Frequency Division Setup Register 0x0 8 read-write n 0x0 0x0 CSR High-speed CR oscillation frequency division ratio setting bits 0 1 read-write MCR_RLR High-Speed CR Oscillation Register Write-Protect Register 0xC 32 read-write n 0x0 0x0 TRMLCK Register write-protect bits 0 31 read-write DMAC DMAC Registers DMAC 0x0 0x0 0x4 registers n 0x10 0x80 registers n DMAC0 38 DMAC1 39 DMAC2 40 DMAC3 41 DMAC4 42 DMAC5 43 DMAC6 44 DMAC7 45 DMACA0 Configuration A Register 0x10 32 read-write n 0x0 0x0 BC Block Count 16 3 read-write EB Enable bit (individual-channel operation enable bit) 31 read-write IS Input Select 23 5 read-write PB Pause bit (individual-channel pause bit) 30 read-write ST Software Trigger 29 read-write TC Transfer Count 0 15 read-write DMACA1 Configuration A Register 1 0x20 read-write n 0x0 0x0 DMACA2 Configuration A Register 2 0x30 read-write n 0x0 0x0 DMACA3 Configuration A Register 3 0x40 read-write n 0x0 0x0 DMACA4 Configuration A Register 4 0x50 read-write n 0x0 0x0 DMACA5 Configuration A Register 5 0x60 read-write n 0x0 0x0 DMACA6 Configuration A Register 6 0x70 read-write n 0x0 0x0 DMACA7 Configuration A Register 7 0x80 read-write n 0x0 0x0 DMACB0 Configuration B Register 0x14 32 read-write n 0x0 0x0 CI Completion Interrupt (successful transfer completion interrupt enable) 19 read-write EI Error Interrupt (unsuccessful transfer completion interrupt enable) 20 read-write EM Enable bit Mask (EB bit clear mask) 0 read-write FD Fixed Destination 24 read-write FS Fixed Source 25 read-write MS Mode Select 28 1 read-write RC Reload Count (BC/TC reload) 23 read-write RD Reload Destination 21 read-write RS Reload Source 22 read-write SS Stop Status (stop status notification) 16 2 read-write TW Transfer Width 26 1 read-write DMACB1 Configuration B Register 1 0x24 read-write n 0x0 0x0 DMACB2 Configuration B Register 2 0x34 read-write n 0x0 0x0 DMACB3 Configuration B Register 3 0x44 read-write n 0x0 0x0 DMACB4 Configuration B Register 4 0x54 read-write n 0x0 0x0 DMACB5 Configuration B Register 5 0x64 read-write n 0x0 0x0 DMACB6 Configuration B Register 6 0x74 read-write n 0x0 0x0 DMACB7 Configuration B Register 7 0x84 read-write n 0x0 0x0 DMACDA0 Transfer Destination Address Register 0x1C 32 read-write n 0x0 0x0 DMACDA1 Transfer Destination Address Register 1 0x2C read-write n 0x0 0x0 DMACDA2 Transfer Destination Address Register 2 0x3C read-write n 0x0 0x0 DMACDA3 Transfer Destination Address Register 3 0x4C read-write n 0x0 0x0 DMACDA4 Transfer Destination Address Register 4 0x5C read-write n 0x0 0x0 DMACDA5 Transfer Destination Address Register 5 0x6C read-write n 0x0 0x0 DMACDA6 Transfer Destination Address Register 6 0x7C read-write n 0x0 0x0 DMACDA7 Transfer Destination Address Register 7 0x8C read-write n 0x0 0x0 DMACR Entire DMAC Configuration Register 0x0 32 read-write n 0x0 0x0 DE DMA Enable (all-channel operation enable bit) 31 read-write DH DMA Halt (All-channel pause bit) 24 3 read-write DS DMA Stop 30 read-write PR Priority Rotation 28 read-write DMACSA0 Transfer Source Address Register 0x18 32 read-write n 0x0 0x0 DMACSA1 Transfer Source Address Register 1 0x28 read-write n 0x0 0x0 DMACSA2 Transfer Source Address Register 2 0x38 read-write n 0x0 0x0 DMACSA3 Transfer Source Address Register 3 0x48 read-write n 0x0 0x0 DMACSA4 Transfer Source Address Register 4 0x58 read-write n 0x0 0x0 DMACSA5 Transfer Source Address Register 5 0x68 read-write n 0x0 0x0 DMACSA6 Transfer Source Address Register 6 0x78 read-write n 0x0 0x0 DMACSA7 Transfer Source Address Register 7 0x88 read-write n 0x0 0x0 DTIM Dual Timer DTIM 0x0 0x0 0x1C registers n 0x20 0x1C registers n DTIM_QDU 6 TIMER1BGLOAD Background Load Register 0x18 32 read-write n 0x0 0x0 TIMER1CONTROL Control Register 0x8 32 read-write n 0x0 0x0 IntEnable Interrupt enable bit 5 read-write OneShot One-shot mode bit 0 read-write TimerEn Enable bit 7 read-write TimerMode Mode bit 6 read-write TimerPre Prescale bits 2 1 read-write TimerSize Counter size bit 1 read-write TIMER1INTCLR Interrupt Clear Register 0xC 32 write-only n 0x0 0x0 TIMER1LOAD Load Register DualTimer1 0x0 32 read-write n 0x0 0x0 TIMER1MIS Masked Interrupt Status Register 0x14 32 read-only n 0x0 0x0 TIMER1MIS Masked Interrupt Status bit 0 read-only TIMER1RIS Interrupt Status Register 0x10 32 read-only n 0x0 0x0 TIMER1RIS Interrupt Status Register bit 0 read-only TIMER1VALUE Value Register 0x4 32 read-only n 0x0 0x0 TIMER2BGLOAD Background Load Register 0x38 read-write n 0x0 0x0 TIMER2CONTROL Control Register 0x28 read-write n 0x0 0x0 TIMER2INTCLR Interrupt Clear Register 0x2C read-write n 0x0 0x0 TIMER2LOAD Load Register 0x20 read-write n 0x0 0x0 TIMER2MIS Masked Interrupt Status Register 0x34 read-write n 0x0 0x0 TIMER2RIS Interrupt Status Register 0x30 read-write n 0x0 0x0 TIMER2VALUE Value Register 0x24 read-write n 0x0 0x0 ETHERNET_CONTROL Ethernet system control ETHERNET_CONTROL 0x0 0x0 0x4 registers n 0x8 0x4 registers n ETH_CLKG Clock Gating Register 0x8 32 read-write n 0x0 0x0 MACEN Select the system clock supply to Ethernet-MAC 0 1 read-write ETH_MODE Mode Select Register 0x0 32 read-write n 0x0 0x0 IFMODE Mode selector 0 read-write RST0 reset signal against Ethernet-MAC (ch.0) 8 read-write ETHERNET_MAC0 Ethernet-MAC 0 ETHERNET_MAC0 0x0 0x0 0x1058 registers n ETHER_MAC0 32 AHBSR AHB Status Register 0x102C 32 read-only n 0x0 0x0 AHBS AHB Status 0 read-only ATNR Auxiliary Time Stamp - Nanoseconds Register 0x730 32 read-only n 0x0 0x0 ATN ATN 0 30 read-only ATSR Auxiliary Time Stamp - Seconds Register 0x734 32 read-only n 0x0 0x0 ATS ATS 0 31 read-only BMR Bus Mode Register 0x1000 32 read-write n 0x0 0x0 AAL Address-Aligned Beats 25 read-write ATDS Alternate Descriptor Size 7 read-write DA DMA Arbitration scheme 1 read-write DSL Descriptor Skip Length 2 4 read-write FB Fixed Burst 16 read-write MB Mixed Burst 26 read-write PBL Programmable Burst Length 8 5 read-write PR Rx:Tx priority ratio 14 1 read-write RPBL RxDMA PBL 17 5 read-write SWR Software Reset 0 read-write TXPR Transmit Priority 27 read-write USP Use Separate PBL 23 read-write _8XPBL 8xPBL Mode 24 read-write CHRBAR Current Host Receive Buffer Address Register 0x1054 32 read-only n 0x0 0x0 HRBAR Host Receive Buffer Address Register 0 31 read-only CHRDR Current Host Receive Descriptor Register 0x104C 32 read-only n 0x0 0x0 HRDAP Host Receive Descriptor Address Pointer 0 31 read-only CHTBAR Current Host Transmit Buffer Address Register 0x1050 32 read-only n 0x0 0x0 HTBAR Host Transmit Buffer Address Register 0 31 read-only CHTDR Current Host Transmit Descriptor Register 0x1048 32 read-only n 0x0 0x0 HTDAP Host Transmit Descriptor Address Pointer 0 31 read-only FCR Flow Control Register 0x18 32 read-write n 0x0 0x0 DZPQ Disable Zero-Quanta Pause 7 read-write FCB_BPA Flow Control Busy/Backpressure Activate 0 read-write PLT Pause Low Threshold 4 1 read-write PT Pause Time 16 15 read-write RFE Receive Flow Control Enable 2 read-write TFE Transmit Flow Control Enable 1 read-write UP Unicast Pause Frame detect 3 read-write GAR GMII/MII Address Register 0x10 32 read-write n 0x0 0x0 CR Application Clock Range 2 3 read-write GB GMII/MII Busy 0 read-write GR GMII Register 6 4 read-write GW GMII/MII Write 1 read-write PA Physical Layer Address 11 4 read-write GDR GMII/MII Data Register 0x14 32 read-write n 0x0 0x0 GD GMII/MII Data Register 0 15 read-write IER Interrupt Enable Register 0x101C 32 read-write n 0x0 0x0 AIE Abnormal Interrupt Summary Enable 15 read-write ERE Early Receive Interrupt Enable 14 read-write ETE Early Transmit Interrupt Enable 10 read-write FBE Fatal Bus Error Enable 13 read-write NIE Normal Interrupt Summary Enable 16 read-write OVE Receive Overflow Enable 4 read-only RIE Receive Interrupt Enable 6 read-write RSE Receive Process Stopped Enable 8 read-write RUE Receive Buffer Unavailable Enable 7 read-write RWE Receive Watchdog Timeout Enable 9 read-write TIE Transmit Interrupt 0 read-write TJE Transmit Jabber Timeout 3 read-write TSE Transmit Process Stopped 1 read-write TUE Transmit Buffer Unavailable 2 read-write UNE Transmit underflow Enable 5 read-write IMR Interrupt Mask Register 0x3C 32 read-write n 0x0 0x0 LPIIM LPI Interrupt Mask 6 read-write PIM PMT Interrupt Mask 3 read-write RGIM RGMII Interrupt Mask 0 read-write TSIM Time Stamp Interrupt Mask 5 read-write ISR Interrupt Status Register 0x38 32 read-only n 0x0 0x0 COIS MMC Receive Checksum Offload Interrupt Status 7 read-only LPIIS LPI Interrupt Status 10 read-only MIS MMC Interrupt Status 4 read-only PIS PMT Interrupt Status 3 read-only RGIS RGMII Interrupt Status 0 read-only RIS MMC Receive Interrupt Status 5 read-only TIS MMC Transmit Interrupt Status 6 read-only TSIS Time Stamp Interrupt Status 9 read-only LPICSR LPI Control and Status Register 0x30 32 read-write n 0x0 0x0 LPIEN LPI Enable 16 read-write LPITXA LPI TX Automate 19 read-write PLS PHY Link Status 17 read-write PLSEN PHY Link Status Enable 18 read-write RLPIEN Receive LPI Entry 2 read-only RLPIEX Receive LPI Exit 3 read-only RLPIST Receive LPI State 9 read-only TLPIEN Transmit LPI Entry 0 read-only TLPIEX Transmit LPI Exit 1 read-only TLPIST Transmit LPI State 8 read-only LPITCR LPI Timers Control Register 0x34 32 read-write n 0x0 0x0 LIT LPI LS TIMER 16 9 read-write TWT LPI TW TIMER 0 15 read-write MAR0H MAC Address0 Register (High) 0x40 32 read-write n 0x0 0x0 A32 AD[32] 0 read-write A33 AD[33] 1 read-write A34 AD[34] 2 read-write A35 AD[35] 3 read-write A36 AD[36] 4 read-write A37 AD[37] 5 read-write A38 AD[38] 6 read-write A39 AD[39] 7 read-write A40 AD[40] 8 read-write A41 AD[41] 9 read-write A42 AD[42] 10 read-write A43 AD[43] 11 read-write A44 AD[44] 12 read-write A45 AD[45] 13 read-write A46 AD[46] 14 read-write A47 AD[47] 15 read-write MO Must be one 31 read-only MAR0L MAC Address0 Register (Low) 0x44 32 read-write n 0x0 0x0 A0 AD[0] 0 read-write A1 AD[1] 1 read-write A10 AD[10] 10 read-write A11 AD[11] 11 read-write A12 AD[12] 12 read-write A13 AD[13] 13 read-write A14 AD[14] 14 read-write A15 AD[15] 15 read-write A16 AD[16] 16 read-write A17 AD[17] 17 read-write A18 AD[18] 18 read-write A19 AD[19] 19 read-write A2 AD[2] 2 read-write A20 AD[20] 20 read-write A21 AD[21] 21 read-write A22 AD[22] 22 read-write A23 AD[23] 23 read-write A24 AD[24] 24 read-write A25 AD[25] 25 read-write A26 AD[26] 26 read-write A27 AD[27] 27 read-write A28 AD[28] 28 read-write A29 AD[29] 29 read-write A3 AD[3] 3 read-write A30 AD[30] 30 read-write A31 AD[31] 31 read-write A4 AD[4] 4 read-write A5 AD[5] 5 read-write A6 AD[6] 6 read-write A7 AD[7] 7 read-write A8 AD[8] 8 read-write A9 AD[9] 9 read-write MAR10H MAC Address10 Register -High 0x90 read-write n 0x0 0x0 MAR10L MAC Address10 Register -Low 0x94 read-write n 0x0 0x0 MAR11H MAC Address11 Register -High 0x98 read-write n 0x0 0x0 MAR11L MAC Address11 Register -Low 0x9C read-write n 0x0 0x0 MAR12H MAC Address12 Register -High 0xA0 read-write n 0x0 0x0 MAR12L MAC Address12 Register -Low 0xA4 read-write n 0x0 0x0 MAR13H MAC Address13 Register -High 0xA8 read-write n 0x0 0x0 MAR13L MAC Address13 Register -Low 0xAC read-write n 0x0 0x0 MAR14H MAC Address14 Register -High 0xB0 read-write n 0x0 0x0 MAR14L MAC Address14 Register -Low 0xB4 read-write n 0x0 0x0 MAR15H MAC Address15 Register -High 0xB8 read-write n 0x0 0x0 MAR15L MAC Address15 Register -Low 0xBC read-write n 0x0 0x0 MAR16H MAC Address16 Register -High 0x800 read-write n 0x0 0x0 MAR16L MAC Address16 Register -Low 0x804 read-write n 0x0 0x0 MAR17H MAC Address17 Register -High 0x808 read-write n 0x0 0x0 MAR17L MAC Address17 Register -Low 0x80C read-write n 0x0 0x0 MAR18H MAC Address18 Register -High 0x810 read-write n 0x0 0x0 MAR18L MAC Address18 Register -Low 0x814 read-write n 0x0 0x0 MAR19H MAC Address19 Register -High 0x818 read-write n 0x0 0x0 MAR19L MAC Address19 Register -Low 0x81C read-write n 0x0 0x0 MAR1H MAC Address1 Register -High 0x48 32 read-write n 0x0 0x0 A32 AD[32] 0 read-write A33 AD[33] 1 read-write A34 AD[34] 2 read-write A35 AD[35] 3 read-write A36 AD[36] 4 read-write A37 AD[37] 5 read-write A38 AD[38] 6 read-write A39 AD[39] 7 read-write A40 AD[40] 8 read-write A41 AD[41] 9 read-write A42 AD[42] 10 read-write A43 AD[43] 11 read-write A44 AD[44] 12 read-write A45 AD[45] 13 read-write A46 AD[46] 14 read-write A47 AD[47] 15 read-write AE Address Enable 31 read-write MBC Mask Byte Control 24 5 read-write SA Source Address 30 read-write MAR1L MAC Address1 Register -Low 0x4C 32 read-write n 0x0 0x0 A0 AD[0] 0 read-write A1 AD[1] 1 read-write A10 AD[10] 10 read-write A11 AD[11] 11 read-write A12 AD[12] 12 read-write A13 AD[13] 13 read-write A14 AD[14] 14 read-write A15 AD[15] 15 read-write A16 AD[16] 16 read-write A17 AD[17] 17 read-write A18 AD[18] 18 read-write A19 AD[19] 19 read-write A2 AD[2] 2 read-write A20 AD[20] 20 read-write A21 AD[21] 21 read-write A22 AD[22] 22 read-write A23 AD[23] 23 read-write A24 AD[24] 24 read-write A25 AD[25] 25 read-write A26 AD[26] 26 read-write A27 AD[27] 27 read-write A28 AD[28] 28 read-write A29 AD[29] 29 read-write A3 AD[3] 3 read-write A30 AD[30] 30 read-write A31 AD[31] 31 read-write A4 AD[4] 4 read-write A5 AD[5] 5 read-write A6 AD[6] 6 read-write A7 AD[7] 7 read-write A8 AD[8] 8 read-write A9 AD[9] 9 read-write MAR20H MAC Address20 Register -High 0x820 read-write n 0x0 0x0 MAR20L MAC Address20 Register -Low 0x824 read-write n 0x0 0x0 MAR21H MAC Address21 Register -High 0x828 read-write n 0x0 0x0 MAR21L MAC Address21 Register -Low 0x82C read-write n 0x0 0x0 MAR22H MAC Address22 Register -High 0x830 read-write n 0x0 0x0 MAR22L MAC Address22 Register -Low 0x834 read-write n 0x0 0x0 MAR23H MAC Address23 Register -High 0x838 read-write n 0x0 0x0 MAR23L MAC Address23 Register -Low 0x83C read-write n 0x0 0x0 MAR24H MAC Address24 Register -High 0x840 read-write n 0x0 0x0 MAR24L MAC Address24 Register -Low 0x844 read-write n 0x0 0x0 MAR25H MAC Address25 Register -High 0x848 read-write n 0x0 0x0 MAR25L MAC Address25 Register -Low 0x84C read-write n 0x0 0x0 MAR26H MAC Address26 Register -High 0x850 read-write n 0x0 0x0 MAR26L MAC Address26 Register -Low 0x854 read-write n 0x0 0x0 MAR27H MAC Address27 Register -High 0x858 read-write n 0x0 0x0 MAR27L MAC Address27 Register -Low 0x85C read-write n 0x0 0x0 MAR28H MAC Address28 Register -High 0x860 read-write n 0x0 0x0 MAR28L MAC Address28 Register -Low 0x864 read-write n 0x0 0x0 MAR29H MAC Address29 Register -High 0x868 read-write n 0x0 0x0 MAR29L MAC Address29 Register -Low 0x86C read-write n 0x0 0x0 MAR2H MAC Address2 Register -High 0x50 read-write n 0x0 0x0 MAR2L MAC Address2 Register -Low 0x54 read-write n 0x0 0x0 MAR30H MAC Address30 Register -High 0x870 read-write n 0x0 0x0 MAR30L MAC Address30 Register -Low 0x874 read-write n 0x0 0x0 MAR31H MAC Address31 Register -High 0x878 read-write n 0x0 0x0 MAR31L MAC Address31 Register -Low 0x87C read-write n 0x0 0x0 MAR3H MAC Address3 Register -High 0x58 read-write n 0x0 0x0 MAR3L MAC Address3 Register -Low 0x5C read-write n 0x0 0x0 MAR4H MAC Address4 Register -High 0x60 read-write n 0x0 0x0 MAR4L MAC Address4 Register -Low 0x64 read-write n 0x0 0x0 MAR5H MAC Address5 Register -High 0x68 read-write n 0x0 0x0 MAR5L MAC Address5 Register -Low 0x6C read-write n 0x0 0x0 MAR6H MAC Address6 Register -High 0x70 read-write n 0x0 0x0 MAR6L MAC Address6 Register -Low 0x74 read-write n 0x0 0x0 MAR7H MAC Address7 Register -High 0x78 read-write n 0x0 0x0 MAR7L MAC Address7 Register -Low 0x7C read-write n 0x0 0x0 MAR8H MAC Address8 Register -High 0x80 read-write n 0x0 0x0 MAR8L MAC Address8 Register -Low 0x84 read-write n 0x0 0x0 MAR9H MAC Address9 Register -High 0x88 read-write n 0x0 0x0 MAR9L MAC Address9 Register -Low 0x8C read-write n 0x0 0x0 MCR MAC Configuration Register 0x0 32 read-write n 0x0 0x0 ACS Automatic Pad/CRC Stripping 7 read-write BE Frame Burst Enable 21 read-write BL Back-off Limit 5 1 read-write CST CRC stripping for Type frames 25 read-write DC Deferral Check 4 read-write DCRS Disable Carrier Sense During Transaction 16 read-write DM Duplex mode 11 read-write DO Disable Receive Own 13 read-write DR Disable Retry 9 read-write FES Speed 14 read-write IFG Inter-Frame GAP 17 2 read-write IPC Checksum Offload 10 read-write JD Jabber Disable 22 read-write JE Jumbo Frame Enable 20 read-write LM Loop-back Mode 12 read-write LUD Link Up/Down in RGMII 8 read-write PS Port Select 15 read-write RE Receiver Enable 2 read-write TC Transmit Configuration in RGMII 24 read-write TE Transmitter Enable 3 read-write WD Watchdog Disable 23 read-write MFBOCR Missed Frame and Buffer Overflow Counter Register 0x1020 32 read-only n 0x0 0x0 NMFF Number of Missed frame by Ethernet-MAC 17 10 read-only NMFH Number of Missed frame by HOST 0 15 read-only ONMFF Overflow NMFF 28 read-only ONMFH Overflow NMFH 16 read-only MFFR MAC Frame Filter Register 0x4 32 read-write n 0x0 0x0 DAIF DA Inverse Filtering 3 read-write DB Disable Broadcast Frames 5 read-write HMC Hash Multicast 2 read-write HPF Hash or Perfect Filter 10 read-write HUC Hash Unicast 1 read-write PCF Pass Control Frames 6 1 read-write PM Pass All Multicast 4 read-write PR Promiscuous Mode 0 read-write RA Receive All 31 read-write SAF Source Address Filter 9 read-write SAIF Source Address Inverse Filter 8 read-write MHTRH MAC Hash Table Register (High) 0x8 32 read-write n 0x0 0x0 HTH the upper 32 bits of the hash table in the HTH 0 31 read-write MHTRL MAC Hash Table Register (Low) 0xC 32 read-write n 0x0 0x0 HTL the lower 32 bits of the hash table in the HTL 0 31 read-write mmc_cntl MMC Control Register 0x100 32 read-write n 0x0 0x0 mmc_intr_mask_rx MMC Receive Interrupt Mask Register 0x10C 32 read-write n 0x0 0x0 mmc_intr_mask_tx MMC Transmit Interrupt Mask Register 0x110 32 read-write n 0x0 0x0 mmc_intr_rx Receive Interrupt Register 0x104 32 read-only n 0x0 0x0 mmc_intr_tx MMC Transmit Interrupt Register 0x108 32 read-only n 0x0 0x0 mmc_ipc_intr_mask_rx MMC Receive Checksum Offload Interrupt Mask Register 0x200 32 read-write n 0x0 0x0 mmc_ipc_intr_rx MMC Receive Checksum Offload Interrupt Register 0x208 32 read-only n 0x0 0x0 OMR Operation Mode Register 0x1018 32 read-write n 0x0 0x0 DFF Disable Flushing of Received Frames 24 read-write DT Disable Dropping of TCP/IP Checksum Error Frames 26 read-write FEF Forward Error Frames 7 read-write FTF Flush Transmit FIFO 20 read-write FUF Forward Undersized Good Frames 6 read-write OSF Operate on Second Frame 2 read-write RSF Receive Store and Forward 25 read-write RTC Receive Threshold Control 3 1 read-write SR Start/Stop Receive 1 read-write ST Start/Stop Transmission Command 13 read-write TSF Transmit Store Forward 21 read-write TTC Transmit Threshold Control 14 2 read-write PMTR PMT Register 0x2C 32 read-write n 0x0 0x0 GU Global Unicast 9 read-write MPE Magic Packet Enable 1 read-write MPR Magic Packet Received 5 read-write PD Power Down 0 read-write RWFFRPR Remote Wake-up Frame Filter Register Pointer Reset 31 read-write WFE Wake-Up Frame Enable 2 read-write WPR Wake Up Frame Receive 6 read-write PPSCR PPS Control Register 0x72C 32 read-write n 0x0 0x0 PPSCTRL Controls the frequency of the PPS output 0 3 read-only RDLAR Receive Descriptor List Address Register) 0x100C 32 read-write n 0x0 0x0 SRL10 Bit10 of RDLAR 10 read-write SRL11 Bit11 of RDLAR 11 read-write SRL12 Bit12 of RDLAR 12 read-write SRL13 Bit13 of RDLAR 13 read-write SRL14 Bit14 of RDLAR 14 read-write SRL15 Bit15 of RDLAR 15 read-write SRL16 Bit16 of RDLAR 16 read-write SRL17 Bit17 of RDLAR 17 read-write SRL18 Bit18 of RDLAR 18 read-write SRL19 Bit19 of RDLAR 19 read-write SRL2 Bit2 of RDLAR 2 read-write SRL20 Bit20 of RDLAR 20 read-write SRL21 Bit21 of RDLAR 21 read-write SRL22 Bit22 of RDLAR 22 read-write SRL23 Bit23 of RDLAR 23 read-write SRL24 Bit24 of RDLAR 24 read-write SRL25 Bit25 of RDLAR 25 read-write SRL26 Bit26 of RDLAR 26 read-write SRL27 Bit27 of RDLAR 27 read-write SRL28 Bit28 of RDLAR 28 read-write SRL29 Bit29 of RDLAR 29 read-write SRL3 Bit3 of RDLAR 3 read-write SRL30 Bit30 of RDLAR 30 read-write SRL31 Start of Receive List 31 read-write SRL4 Bit4 of RDLAR 4 read-write SRL5 Bit5 of RDLAR 5 read-write SRL6 Bit6 of RDLAR 6 read-write SRL7 Bit7 of RDLAR 7 read-write SRL8 Bit8 of RDLAR 8 read-write SRL9 Bit9 of RDLAR 9 read-write RGSR RGMII Status Register) 0xD8 32 read-only n 0x0 0x0 LM Link Mode 0 read-only LS Link Status 3 read-only LSP Link Speed 1 1 read-only RIWTR Receive Interrupt Watchdog Timer Register 0x1024 32 read-only n 0x0 0x0 RIWT RI Watchdog Timer count 0 7 read-only RPDR Receive Poll Demand Register 0x1008 32 read-write n 0x0 0x0 RPD Receive Poll Demand 0 31 read-write RWFFR Remote Wake-up Frame Filter Register 0x28 32 read-write n 0x0 0x0 RWFFR31 Remote Wake-up Frame Filter Register 0 31 read-write rx1024tomaxoctets_gb Number of good and bad frames received with length between 1024 and maxsize (inclusive) bytes, exclusive of preamble. 0x1C0 32 read-only n 0x0 0x0 rx128to255octets_gb Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. 0x1B4 32 read-only n 0x0 0x0 rx256to511octets_gb Number of good and bad frames received with length between 256 and 511 (inclusive) bytes, exclusive of preamble. 0x1B8 32 read-only n 0x0 0x0 rx512to1023octets_gb Number of good and bad frames received with length between 512 and 1023 (inclusive) bytes, exclusive of preamble. 0x1BC 32 read-only n 0x0 0x0 rx64octets_gb Number of good and bad frames received with length 64 bytes, exclusive of preamble. 0x1AC 32 read-only n 0x0 0x0 rx65to127octets_gb Number of good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble. 0x1B0 32 read-only n 0x0 0x0 rxallignmenterror Number of frames received with alignment (dribble) error. Valid only in 10/100 mode. 0x198 32 read-only n 0x0 0x0 rxbroadcastframes_g Number of good broadcast frames received. 0x18C 32 read-only n 0x0 0x0 rxcrcerror Number of frames received with CRC error. 0x194 32 read-only n 0x0 0x0 rxfifooverflow Number of missed received frames due to FIFO overflow. 0x1D4 32 read-only n 0x0 0x0 rxframecount_gb Number of good and bad frames received. 0x180 32 read-only n 0x0 0x0 rxicmp_err_frms Number of good IP datagrams whose ICMP payload has a checksum error 0x244 32 read-only n 0x0 0x0 rxicmp_err_octets Number of bytes received in an ICMP segment with checksum errors 0x284 32 read-only n 0x0 0x0 rxicmp_gd_frms Number of good IP datagrams with a good ICMP payload 0x240 32 read-only n 0x0 0x0 rxicmp_gd_octets Number of bytes received in a good ICMP segment 0x280 32 read-only n 0x0 0x0 rxipv4_frag_frms Number of good IPv4 datagrams with fragmentation 0x21C 32 read-only n 0x0 0x0 rxipv4_frag_octets Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 header's Length field is used to update this counter. 0x25C 32 read-only n 0x0 0x0 rxipv4_gd_frms Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload 0x210 32 read-only n 0x0 0x0 rxipv4_gd_octets Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter or in the octet counters listed below). 0x250 32 read-only n 0x0 0x0 rxipv4_hdrerr_frms Number of IPv4 datagrams received with header errors (checksum, length, or version mismatch) 0x214 32 read-only n 0x0 0x0 rxipv4_hdrerr_octets Number of bytes received in IPv4 datagrams with header errors (checksum, length, version mismatch). The value in the Length field of IPv4 header is used to update this counter. 0x254 32 read-only n 0x0 0x0 rxipv4_nopay_frms Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine 0x218 32 read-only n 0x0 0x0 rxipv4_nopay_octets Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 header's Length field is used to update this counter. 0x258 32 read-only n 0x0 0x0 rxipv4_udsbl_frms Number of good IPv4 datagrams received that had a UDP payload with checksum disabled 0x220 32 read-only n 0x0 0x0 rxipv4_udsbl_octets Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. 0x260 32 read-only n 0x0 0x0 rxipv6_gd_frms Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads 0x224 32 read-only n 0x0 0x0 rxipv6_gd_octets Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data 0x264 32 read-only n 0x0 0x0 rxipv6_hdrerr_frms Number of IPv6 datagrams received with header errors (length or version mismatch) 0x228 32 read-only n 0x0 0x0 rxipv6_hdrerr_octets Number of bytes received in IPv6 datagrams with header errors (length, version mismatch). The value in the IPv6 header's Length field is used to update this counter. 0x268 32 read-only n 0x0 0x0 rxipv6_nopay_frms Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers 0x22C 32 read-only n 0x0 0x0 rxipv6_nopay_octets Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 header's Length field is used to update this counter. 0x26C 32 read-only n 0x0 0x0 rxjabbererror Number of frames received with length greater than 1518 bytes with CRC error. 0x1A0 32 read-only n 0x0 0x0 rxlengtherror Number of frames received with length error (Length type field is not the frame size), for all frames with valid length field. 0x1C8 32 read-only n 0x0 0x0 rxmulticastframes_g Number of good multicast frames received. 0x190 32 read-only n 0x0 0x0 rxoctetcount_g Number of bytes received, exclusive of preamble, only in good frames. 0x188 32 read-only n 0x0 0x0 rxoctetcount_gb Number of bytes received, exclusive of preamble, in good and bad frames. 0x184 32 read-only n 0x0 0x0 rxoutofrangetype Number of frames received with length/type field not equal to the valid frame size (>1500) 0x1CC 32 read-only n 0x0 0x0 rxoversize_g Number of frames received with length greater than the maxsize without error. 0x1A8 32 read-only n 0x0 0x0 rxpauseframes Number of good and valid PAUSE frames received. 0x1D0 32 read-only n 0x0 0x0 rxrunterror Number of frames received with runt (64 bytes and CRC error) error. 0x19C 32 read-only n 0x0 0x0 rxtcp_err_frms Number of good IP datagrams whose TCP payload has a checksum error 0x23C 32 read-only n 0x0 0x0 rxtcp_err_octets Number of bytes received in a TCP segment with checksum errors 0x27C 32 read-only n 0x0 0x0 rxtcp_gd_frms Number of good IP datagrams with a good TCP payload 0x238 32 read-only n 0x0 0x0 rxtcp_gd_octets Number of bytes received in a good TCP segment 0x278 32 read-only n 0x0 0x0 rxudp_err_frms Number of good IP datagrams whose UDP payload has a checksum error 0x234 32 read-only n 0x0 0x0 rxudp_err_octets Number of bytes received in a UDP segment that had checksum errors 0x274 32 read-only n 0x0 0x0 rxudp_gd_frms Number of good IP datagrams with a good UDP payload. This counter is not updated when the rxipv4_udsbl_frms counter is incremented. 0x230 32 read-only n 0x0 0x0 rxudp_gd_octets Number of bytes received in a good UDP segment. This counter (and the counters below) does not count IP header bytes. 0x270 32 read-only n 0x0 0x0 rxundersize_g Number of frames received with length less than 64 bytes, without any errors. 0x1A4 32 read-only n 0x0 0x0 rxunicastframes_g Number of good unicast frames received. 0x1C4 32 read-only n 0x0 0x0 rxvlanframes_gb Number of good and bad VLAN frames received. 0x1D8 32 read-only n 0x0 0x0 rxwatchdogerror Number of frames received with error due to watchdog timeout error (frames with a data load larger than 2048 bytes). 0x1DC 32 read-only n 0x0 0x0 SR Status Register 0x1014 32 read-only n 0x0 0x0 AIS Abnormal Interrupt Summary 15 read-only EB Error Bits 23 2 read-only ERI Early Receive Interrupt 14 read-only ETI Early Transmit Interrupt 10 read-only FBI Fatal Bus Error Interrupt 13 read-only GLI GMAC Line interface Interrupt 26 read-only GLPII GMAC LPI Interrupt 30 read-only GMI GMAC MMC Interrupt 27 read-only GPI GMAC PMT Interrupt 28 read-only NIS Normal Interrupt Summary 16 read-only OVF Receive Overflow 4 read-only RI Receive Interrupt 6 read-only RPS Receive process Stopped 8 read-only RS Receive Process State 17 2 read-only RU Receive Buffer Unavailable 7 read-only RWT Receive Watchdog Timeout 9 read-only TI Transmit Interrupt 0 read-only TJT Transmit Jabber Timeout 3 read-only TPS Transmit Process Stopped 1 read-only TS Transmit Process State 20 2 read-only TTI Time-Stamp Trigger Interrupt 29 read-only TU Transmit Buffer Unavailable 2 read-only UNF Transmit underflow 5 read-only SSIR Sub-Second Increment Register 0x704 32 read-write n 0x0 0x0 SSINC Sub-Second Increment Value 0 7 read-write STHWSR System Time - Higher Word Seconds Register 0x724 32 read-write n 0x0 0x0 TSHWR Time Stamp Higher Word Register 0 15 read-write STNR System Time - Nanoseconds Register 0x70C 32 read-only n 0x0 0x0 TSSS Time Stamp Sub-Seconds 0 30 read-only STNUR System Time - Nanoseconds Update Register 0x714 32 read-write n 0x0 0x0 ADDSUB Add or Subtract Time 31 read-write TSSS Time Stamp Sub-Seconds 0 30 read-write STSR System Time - Seconds Register 0x708 32 read-only n 0x0 0x0 TSS Time Stamp Second 0 31 read-only STSUR System Time - Seconds Update Register 0x710 32 read-write n 0x0 0x0 TSS Time Stamp Second 0 31 read-write TDLAR Transmit Descriptor List Address Register 0x1010 32 read-write n 0x0 0x0 STL10 Bit10 of TDLAR 10 read-write STL11 Bit11 of TDLAR 11 read-write STL12 Bit12 of TDLAR 12 read-write STL13 Bit13 of TDLAR 13 read-write STL14 Bit14 of TDLAR 14 read-write STL15 Bit15 of TDLAR 15 read-write STL16 Bit16 of TDLAR 16 read-write STL17 Bit17 of TDLAR 17 read-write STL18 Bit18 of TDLAR 18 read-write STL19 Bit19 of TDLAR 19 read-write STL2 Bit2 of TDLAR 2 read-write STL20 Bit20 of TDLAR 20 read-write STL21 Bit21 of TDLAR 21 read-write STL22 Bit22 of TDLAR 22 read-write STL23 Bit23 of TDLAR 23 read-write STL24 Bit24 of TDLAR 24 read-write STL25 Bit25 of TDLAR 25 read-write STL26 Bit26 of TDLAR 26 read-write STL27 Bit27 of TDLAR 27 read-write STL28 Bit28 of TDLAR 28 read-write STL29 Bit29 of TDLAR 29 read-write STL3 Bit3 of TDLAR 3 read-write STL30 Bit30 of TDLAR 30 read-write STL31 Start of Transmit List 31 read-write STL4 Bit4 of TDLAR 4 read-write STL5 Bit5 of TDLAR 5 read-write STL6 Bit6 of TDLAR 6 read-write STL7 Bit7 of TDLAR 7 read-write STL8 Bit8 of TDLAR 8 read-write STL9 Bit9 of TDLAR 9 read-write TPDR Transmit Poll Demand Register) 0x1004 32 read-write n 0x0 0x0 TPD Transmit Poll Demand 0 31 read-write TSAR Time Stamp Addend Register 0x718 32 read-write n 0x0 0x0 TSAR Time Stamp Addend Register 0 31 read-write TSCR Time Stamp Control Register 0x700 32 read-write n 0x0 0x0 ATSFC Auxiliary Snapshot FIFO Clear 24 read-write TARU Addend Register Update 5 read-write TETSEM Enable Time Stamp Snapshot for Event Messages 14 read-write TETSP Enable Time Stamp Snapshot for PTP over Ethernet frames 11 read-write TFCU Time Stamp Fine or Coarse Update 1 read-write TITE Time Stamp Interrupt Trigger Enable 4 read-write TSDB Time Stamp Digital or Binary rollover control 9 read-write TSE Time Stamp Enable 0 read-write TSEA Enable Time Stamp for All Frames 8 read-write TSENMF Enable MAC address for PTP frame filtering 18 read-write TSI Time Stamp Initialize 2 read-write TSIP4E Enable Time Stamp Snapshot for IPv4 frames 13 read-write TSIP6E Enable Time Stamp Snapshot for IPv6 frames 12 read-write TSMRM Enable Snapshot for Messages Relevant to Master 15 read-write TSPS SelectPTP packets for taking snapshots 16 1 read-write TSU Time Stamp Update 3 read-write TSV2E Enable PTP packet snooping for version 2 format 10 read-write TSR Time Stamp Status Register 0x728 32 read-only n 0x0 0x0 ATSNS Auxiliary Time Stamp Number of Snapshots 25 2 read-only ATSSTM Auxiliary Time Stamp Snapshot Trigger Missed 24 read-only ATSTS Auxiliary Time Stamp Trigger Snapshot 2 read-only TRGTER Timestamp Target Time Error 3 read-only TSSOVF Time Stamp Seconds Overflow 0 read-only TSTART Time Stamp Target Time Reached 1 read-only TTNR Target Time Nanoseconds Register 0x720 32 read-write n 0x0 0x0 TSTR Target Time Stamp Nanoseconds Register 0 30 read-write TTSR Target Time Seconds Register 0x71C 32 read-write n 0x0 0x0 TSTR Target Time Stamp Seconds Register 0 31 read-write tx1024tomaxoctets_gb Number of good and bad frames transmitted with length between 1024 and Maxsize (inclusive) bytes, exclusive of preamble and retried frames 0x138 32 read-only n 0x0 0x0 tx128to255octets_gb Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames 0x12C 32 read-only n 0x0 0x0 tx256to511octets_gb Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames 0x130 32 read-only n 0x0 0x0 tx512to1023octets_gb Number of good and bad frames transmitted with length between 512 and 1023 (inclusive) bytes, exclusive of preamble and retried frames 0x134 32 read-only n 0x0 0x0 tx64octets_gb Number of good and bad frames transmitted with length of 64 bytes, exclusive of preamble and retried frames 0x124 32 read-only n 0x0 0x0 tx65to127octets_gb Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames 0x128 32 read-only n 0x0 0x0 txbroadcastframes_g Number of good broadcast frames transmitted 0x11C 32 read-only n 0x0 0x0 txbroadcastframes_gb Number of good and bad broadcast frames transmitted 0x144 32 read-only n 0x0 0x0 txcarriererror Number of frames aborted due to carrier sense error (no carrier or loss of carrier). 0x160 32 read-only n 0x0 0x0 txdeferred Number of successfully transmitted frames after a deferral in Half-duplex mode. 0x154 32 read-only n 0x0 0x0 txexecessdef_g Number of frames aborted due to excessive deferral error (deferred for more than two max-sized frame times). 0x16C 32 read-only n 0x0 0x0 txexesscol Number of frames aborted due to excessive (16) collision errors. 0x15C 32 read-only n 0x0 0x0 txframecount_g Number of good frames transmitted. 0x168 32 read-only n 0x0 0x0 txframecount_gb Number of good and bad frames transmitted, exclusive of retried frames 0x118 32 read-only n 0x0 0x0 txlatecol Number of frames aborted due to late collision error. 0x158 32 read-only n 0x0 0x0 txmulticastframes_g Number of good multicast frames transmitted 0x120 32 read-only n 0x0 0x0 txmulticastframes_gb Number of good and bad multicast frames transmitted 0x140 32 read-only n 0x0 0x0 txmulticol_g Number of successfully transmitted frames after more than a single collision in Half-duplex mode 0x150 32 read-only n 0x0 0x0 txoctetcount_g Number of bytes transmitted, exclusive of preamble, in good frames only. 0x164 32 read-only n 0x0 0x0 txoctetcount_gb Number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad frames 0x114 32 read-only n 0x0 0x0 txpauseframes Number of good PAUSE frames transmitted. 0x170 32 read-only n 0x0 0x0 txsinglecol_g Number of successfully transmitted frames after a single collision in Half-duplex mode 0x14C 32 read-only n 0x0 0x0 txunderflowerror Number of frames aborted due to frame underflow error 0x148 32 read-only n 0x0 0x0 txunicastframes_gb Number of good and bad unicast frames transmitted 0x13C 32 read-only n 0x0 0x0 txvlanframes_g Number of good VLAN frames transmitted, exclusive of retried frames. 0x174 32 read-only n 0x0 0x0 VTR VLAN TAG Register 0x1C 32 read-write n 0x0 0x0 ETV Enable 12-Bit VLAN Tag Comparison 16 read-write VL VLAN Tag Identifier 0 15 read-write EXBUS External Bus Interface EXBUS 0x0 0x0 0x2C registers n 0x300 0x4 registers n AREA0 Area Register 0 0x40 32 read-write n 0x0 0x0 ADDR Address 0 7 read-write MASK address mask 16 6 read-write AREA1 Area Register 1 0x44 32 read-write n 0x0 0x0 ADDR Address 0 7 read-write MASK address mask 16 6 read-write AREA2 Area Register 2 0x48 32 read-write n 0x0 0x0 ADDR Address 0 7 read-write MASK address mask 16 6 read-write AREA3 Area Register 3 0x4C 32 read-write n 0x0 0x0 ADDR Address 0 7 read-write MASK address mask 16 6 read-write AREA4 Area Register 4 0x50 32 read-write n 0x0 0x0 ADDR Address 0 7 read-write MASK address mask 16 6 read-write AREA5 Area Register 5 0x54 32 read-write n 0x0 0x0 ADDR Address 0 7 read-write MASK address mask 16 6 read-write AREA6 Area Register 6 0x58 32 read-write n 0x0 0x0 ADDR Address 0 7 read-write MASK address mask 16 6 read-write AREA7 Area Register 7 0x5C 32 read-write n 0x0 0x0 ADDR Address 0 7 read-write MASK address mask 16 6 read-write ATIM0 ALE Timing Register 0 0x60 32 read-write n 0x0 0x0 ALC Address Latch Cycle 0 3 read-write ALES Address Latch Enable Setup cycle 4 3 read-write ALEW Address Latch Enable Width 8 3 read-write ATIM1 ALE Timing Register 1 0x64 read-write n 0x0 0x0 ATIM2 ALE Timing Register 2 0x68 read-write n 0x0 0x0 ATIM3 ALE Timing Register 3 0x6C read-write n 0x0 0x0 ATIM4 ALE Timing Register 4 0x70 read-write n 0x0 0x0 ATIM5 ALE Timing Register 5 0x74 read-write n 0x0 0x0 ATIM6 ALE Timing Register 6 0x78 read-write n 0x0 0x0 ATIM7 ALE Timing Register 7 0x7C read-write n 0x0 0x0 DCLKR Division Clock Register 0x300 32 read-write n 0x0 0x0 MCLKON MCLK ON 4 read-write MDIV MCLK Division Ratio Setup 0 3 read-write MODE0 Mode Register 0 0x0 32 read-write n 0x0 0x0 ALEINV set up the polarity of the ALE signal 9 read-write MOEXEUP select how to set the MOEX width 13 read-write MPXCSOF select a CS assertion from the start of accessing to the end of address output 12 read-write MPXDOFF select whether or not the address is output to the data lines in multiplex mode 11 read-write MPXMODE select operation bus mode 8 read-write NAND NAND Flash memory mode 4 read-write PAGE NOR Flash memory page access mode 5 read-write RBMON Read Byte Mask ON 2 read-write RDY control the external RDY function 6 read-write SHRTDOUT select to which idle cycle the write data output is extended 7 read-write WDTH specify Data Width 0 1 read-write WEOFF disable the write enable signal (MWEX) operation 3 read-write MODE1 Mode Register 1 0x4 read-write n 0x0 0x0 MODE2 Mode Register 2 0x8 read-write n 0x0 0x0 MODE3 Mode Register 3 0xC read-write n 0x0 0x0 MODE4 Mode Register 4 0x10 read-write n 0x0 0x0 MODE5 Mode Register 5 0x14 read-write n 0x0 0x0 MODE6 Mode Register 6 0x18 read-write n 0x0 0x0 MODE7 Mode Register 7 0x1C read-write n 0x0 0x0 TIM0 Timing Register 0 0x20 32 read-write n 0x0 0x0 FRADC First Read Address Cycle 8 3 read-write RACC Read Access Cycle 0 3 read-write RADC Read Address Setup cycle 4 3 read-write RIDLC Read Idle Cycle 12 3 read-write WACC Write Access Cycle 16 3 read-write WADC Write Address Setup cycle 20 3 read-write WIDLC Write Idle Cycle 28 3 read-write WWEC Write Enable Cycle 24 3 read-write TIM1 Timing Register 1 0x24 read-write n 0x0 0x0 TIM2 Timing Register 2 0x28 read-write n 0x0 0x0 TIM3 Timing Register 3 0x2C read-write n 0x0 0x0 TIM4 Timing Register 4 0x30 read-write n 0x0 0x0 TIM5 Timing Register 5 0x34 read-write n 0x0 0x0 TIM6 Timing Register 6 0x38 read-write n 0x0 0x0 TIM7 Timing Register 7 0x3C read-write n 0x0 0x0 EXTI External Interrupt and NMI Control EXTI 0x0 0x0 0x4 registers n 0x10 0x4 registers n 0x14 0x1 registers n 0x18 0x1 registers n 0x4 0x4 registers n 0x8 0x4 registers n 0xC 0x4 registers n EXTINT0_7 4 EXTINT8_31 5 EICL External Interrupt Clear Register 0x8 32 read-write n 0x0 0x0 ECL0 Bit0 of EICL 0 read-write ECL1 Bit1 of EICL 1 read-write ECL10 Bit10 of EICL 10 read-write ECL11 Bit11 of EICL 11 read-write ECL12 Bit12 of EICL 12 read-write ECL13 Bit13 of EICL 13 read-write ECL14 Bit14 of EICL 14 read-write ECL15 Bit15 of EICL 15 read-write ECL16 Bit16 of EICL 16 read-write ECL17 Bit17 of EICL 17 read-write ECL18 Bit18 of EICL 18 read-write ECL19 Bit19 of EICL 19 read-write ECL2 Bit2 of EICL 2 read-write ECL20 Bit20 of EICL 20 read-write ECL21 Bit21 of EICL 21 read-write ECL22 Bit22 of EICL 22 read-write ECL23 Bit23 of EICL 23 read-write ECL24 Bit24 of EICL 24 read-write ECL25 Bit25 of EICL 25 read-write ECL26 Bit26 of EICL 26 read-write ECL27 Bit27 of EICL 27 read-write ECL28 Bit28 of EICL 28 read-write ECL29 Bit29 of EICL 29 read-write ECL3 Bit3 of EICL 3 read-write ECL30 Bit30 of EICL 30 read-write ECL31 Bit31 of EICL 31 read-write ECL4 Bit4 of EICL 4 read-write ECL5 Bit5 of EICL 5 read-write ECL6 Bit6 of EICL 6 read-write ECL7 Bit7 of EICL 7 read-write ECL8 Bit8 of EICL 8 read-write ECL9 Bit9 of EICL 9 read-write EIRR External Interrupt Request Register 0x4 32 read-only n 0x0 0x0 ER0 Bit0 of EIRR 0 read-only ER1 Bit1 of EIRR 1 read-only ER10 Bit10 of EIRR 10 read-only ER11 Bit11 of EIRR 11 read-only ER12 Bit12 of EIRR 12 read-only ER13 Bit13 of EIRR 13 read-only ER14 Bit14 of EIRR 14 read-only ER15 Bit15 of EIRR 15 read-only ER16 Bit16 of EIRR 16 read-only ER17 Bit17 of EIRR 17 read-only ER18 Bit18 of EIRR 18 read-only ER19 Bit19 of EIRR 19 read-only ER2 Bit2 of EIRR 2 read-only ER20 Bit20 of EIRR 20 read-only ER21 Bit21 of EIRR 21 read-only ER22 Bit22 of EIRR 22 read-only ER23 Bit23 of EIRR 23 read-only ER24 Bit24 of EIRR 24 read-only ER25 Bit25 of EIRR 25 read-only ER26 Bit26 of EIRR 26 read-only ER27 Bit27 of EIRR 27 read-only ER28 Bit28 of EIRR 28 read-only ER29 Bit29 of EIRR 29 read-only ER3 Bit3 of EIRR 3 read-only ER30 Bit30 of EIRR 30 read-only ER31 Bit31 of EIRR 31 read-only ER4 Bit4 of EIRR 4 read-only ER5 Bit5 of EIRR 5 read-only ER6 Bit6 of EIRR 6 read-only ER7 Bit7 of EIRR 7 read-only ER8 Bit8 of EIRR 8 read-only ER9 Bit9 of EIRR 9 read-only ELVR External Interrupt Level Register 0xC 32 read-write n 0x0 0x0 LA0 Bit0 of ELVR 0 read-write LA1 Bit2 of ELVR 2 read-write LA10 Bit20 of ELVR 20 read-write LA11 Bit22 of ELVR 22 read-write LA12 Bit24 of ELVR 24 read-write LA13 Bit26 of ELVR 26 read-write LA14 Bit28 of ELVR 28 read-write LA15 Bit30 of ELVR 30 read-write LA2 Bit4 of ELVR 4 read-write LA3 Bit6 of ELVR 6 read-write LA4 Bit8 of ELVR 8 read-write LA5 Bit10 of ELVR 10 read-write LA6 Bit12 of ELVR 12 read-write LA7 Bit14 of ELVR 14 read-write LA8 Bit16 of ELVR 16 read-write LA9 Bit18 of ELVR 18 read-write LB0 Bit1 of ELVR 1 read-write LB1 Bit3 of ELVR 3 read-write LB10 Bit21 of ELVR 21 read-write LB11 Bit23 of ELVR 23 read-write LB12 Bit25 of ELVR 25 read-write LB13 Bit27 of ELVR 27 read-write LB14 Bit29 of ELVR 29 read-write LB15 Bit31 of ELVR 31 read-write LB2 Bit5 of ELVR 5 read-write LB3 Bit7 of ELVR 7 read-write LB4 Bit9 of ELVR 9 read-write LB5 Bit11 of ELVR 11 read-write LB6 Bit13 of ELVR 13 read-write LB7 Bit15 of ELVR 15 read-write LB8 Bit17 of ELVR 17 read-write LB9 Bit19 of ELVR 19 read-write ELVR1 External Interrupt Level Register 1 0x10 32 read-write n 0x0 0x0 LA16 Bit0 of ELVR1 0 read-write LA17 Bit2 of ELVR1 2 read-write LA18 Bit4 of ELVR1 4 read-write LA19 Bit6 of ELVR1 6 read-write LA20 Bit8 of ELVR1 8 read-write LA21 Bit10 of ELVR1 10 read-write LA22 Bit12 of ELVR1 12 read-write LA23 Bit14 of ELVR1 14 read-write LA24 Bit16 of ELVR1 16 read-write LA25 Bit18 of ELVR1 18 read-write LA26 Bit20 of ELVR1 20 read-write LA27 Bit22 of ELVR1 22 read-write LA28 Bit24 of ELVR1 24 read-write LA29 Bit26 of ELVR1 26 read-write LA30 Bit28 of ELVR1 28 read-write LA31 Bit30 of ELVR1 30 read-write LB16 Bit1 of ELVR1 1 read-write LB17 Bit3 of ELVR1 3 read-write LB18 Bit5 of ELVR1 5 read-write LB19 Bit7 of ELVR1 7 read-write LB20 Bit9 of ELVR1 9 read-write LB21 Bit11 of ELVR1 11 read-write LB22 Bit13 of ELVR1 13 read-write LB23 Bit15 of ELVR1 15 read-write LB24 Bit17 of ELVR1 17 read-write LB25 Bit19 of ELVR1 19 read-write LB26 Bit21 of ELVR1 21 read-write LB27 Bit23 of ELVR1 23 read-write LB28 Bit25 of ELVR1 25 read-write LB29 Bit27 of ELVR1 27 read-write LB30 Bit29 of ELVR1 29 read-write LB31 Bit31 of ELVR1 31 read-write ENIR Enable Interrupt Request Register 0x0 32 read-write n 0x0 0x0 EN0 Bit0 of ENIR 0 read-write EN1 Bit1 of ENIR 1 read-write EN10 Bit10 of ENIR 10 read-write EN11 Bit11 of ENIR 11 read-write EN12 Bit12 of ENIR 12 read-write EN13 Bit13 of ENIR 13 read-write EN14 Bit14 of ENIR 14 read-write EN15 Bit15 of ENIR 15 read-write EN16 Bit16 of ENIR 16 read-write EN17 Bit17 of ENIR 17 read-write EN18 Bit18 of ENIR 18 read-write EN19 Bit19 of ENIR 19 read-write EN2 Bit2 of ENIR 2 read-write EN20 Bit20 of ENIR 20 read-write EN21 Bit21 of ENIR 21 read-write EN22 Bit22 of ENIR 22 read-write EN23 Bit23 of ENIR 23 read-write EN24 Bit24 of ENIR 24 read-write EN25 Bit25 of ENIR 25 read-write EN26 Bit26 of ENIR 26 read-write EN27 Bit27 of ENIR 27 read-write EN28 Bit28 of ENIR 28 read-write EN29 Bit29 of ENIR 29 read-write EN3 Bit3 of ENIR 3 read-write EN30 Bit30 of ENIR 30 read-write EN31 Bit31 of ENIR 31 read-write EN4 Bit4 of ENIR 4 read-write EN5 Bit5 of ENIR 5 read-write EN6 Bit6 of ENIR 6 read-write EN7 Bit7 of ENIR 7 read-write EN8 Bit8 of ENIR 8 read-write EN9 Bit9 of ENIR 9 read-write NMICL Non Maskable Interrupt Clear Register 0x18 8 read-write n 0x0 0x0 NCL NMI interrupt cause clear bit 0 read-write NMIRR Non Maskable Interrupt Request Register 0x14 8 read-only n 0x0 0x0 NR NMI interrupt request detection bit 0 read-only FLASH_IF Flash Memory FLASH_IF 0x0 0x0 0xC registers n 0x10 0x8 registers n 0x100 0x4 registers n CRTRMM CR Trimming Data Mirror Register 0x100 32 read-only n 0x0 0x0 TRMM CR Trimming Data Mirror 0 9 read-only FASZR Flash Access Size Register 0x0 32 read-write n 0x0 0x0 ASZ Flash Access Size 0 1 read-write FBFCR Flash Buffer Control Register 0x14 32 read-write n 0x0 0x0 BE Buffer Enable 0 read-write BS Buffer Status 1 read-only FRWTR Flash Read Wait Register 0x4 32 read-write n 0x0 0x0 RWT Read Wait Cycle 0 1 read-write FSTR Flash Status Register 0x8 32 read-only n 0x0 0x0 ERR Flash ECC Error 2 read-write HNG Flash Hang flag 1 read-only RDY Flash Rdy 0 read-only FSYNDN Flash Sync Down Register 0x10 32 read-write n 0x0 0x0 SD Flash Sync 0 2 read-write GPIO General-purpose I/O ports GPIO 0x0 0x0 0x740 registers n ADE Analog input setting register 0x500 32 read-write n 0x0 0x0 AN0 Bit0 of ADE 0 read-write AN1 Bit1 of ADE 1 read-write AN10 Bit10 of ADE 10 read-write AN11 Bit11 of ADE 11 read-write AN12 Bit12 of ADE 12 read-write AN13 Bit13 of ADE 13 read-write AN14 Bit14 of ADE 14 read-write AN15 Bit15 of ADE 15 read-write AN2 Bit2 of ADE 2 read-write AN24 Bit24 of ADE 24 read-write AN25 Bit25 of ADE 25 read-write AN26 Bit26 of ADE 26 read-write AN27 Bit27 of ADE 27 read-write AN28 Bit28 of ADE 28 read-write AN29 Bit29 of ADE 29 read-write AN3 Bit3 of ADE 3 read-write AN30 Bit30 of ADE 30 read-write AN31 Bit31 of ADE 31 read-write AN4 Bit4 of ADE 4 read-write AN5 Bit5 of ADE 5 read-write AN6 Bit6 of ADE 6 read-write AN7 Bit7 of ADE 7 read-write AN8 Bit8 of ADE 8 read-write AN9 Bit9 of ADE 9 read-write DDR0 Port input/output direction setting register 0 0x200 32 read-write n 0x0 0x0 P00 Bit0 of DDR0 0 read-write P01 Bit1 of DDR0 1 read-write P02 Bit2 of DDR0 2 read-write P03 Bit3 of DDR0 3 read-write P04 Bit4 of DDR0 4 read-write P05 Bit5 of DDR0 5 read-write P06 Bit6 of DDR0 6 read-write P07 Bit7 of DDR0 7 read-write P08 Bit8 of DDR0 8 read-write P09 Bit9 of DDR0 9 read-write P0A Bit10 of DDR0 10 read-write P0B Bit11 of DDR0 11 read-write P0C Bit12 of DDR0 12 read-write P0D Bit13 of DDR0 13 read-write P0E Bit14 of DDR0 14 read-write P0F Bit15 of DDR0 15 read-write DDR1 Port input/output direction setting register 1 0x204 read-write n 0x0 0x0 DDR2 Port input/output direction setting register 2 0x208 read-write n 0x0 0x0 DDR3 Port input/output direction setting register 3 0x20C read-write n 0x0 0x0 DDR4 Port input/output direction setting register 4 0x210 read-write n 0x0 0x0 DDR5 Port input/output direction setting register 5 0x214 read-write n 0x0 0x0 DDR6 Port input/output direction setting register 6 0x218 read-write n 0x0 0x0 DDR7 Port input/output direction setting register 7 0x21C read-write n 0x0 0x0 DDR8 Port input/output direction setting register 8 0x220 read-write n 0x0 0x0 DDRA Port input/output direction setting register A 0x228 read-write n 0x0 0x0 DDRC Port input/output direction setting register C 0x230 read-write n 0x0 0x0 DDRD Port input/output direction setting register D 0x234 read-write n 0x0 0x0 DDRE Port input/output direction setting register E 0x238 read-write n 0x0 0x0 DDRF Port input/output direction setting register F 0x23C read-write n 0x0 0x0 EPFR00 Extended pin function setting register 00 0x600 32 read-write n 0x0 0x0 CROUTE Internal high-speed CR oscillation output function select bit 1 1 read-write JTAGEN0B JTAG function select bit0 16 read-write JTAGEN1S JTAG function select bit1 17 read-write NMIS NMIX function select bit 0 read-write SUBOUTE Sub clock divide output function select bit 6 1 read-write TRC0E TRACED function select bit0 24 read-write TRC1E TRACED function select bit1 25 read-write USBP0E USBch0 function select bit 9 read-write USBP1E USBch1 function select bit 13 read-write EPFR01 Extended pin function setting register 01 0x604 32 read-write n 0x0 0x0 DTTI0C DTTIX0 function select bit 12 read-write DTTI0S DTTIX0 input select bit 16 1 read-write FRCK0S FRCK0 input select bit 18 1 read-write IC00S IC00 input select bit 20 2 read-write IC01S IC01 input select bit 23 2 read-write IC02S IC02 input select bit 26 2 read-write IC03S IC03 input select bit 29 2 read-write RTO00E RTO00E output select bit 0 1 read-write RTO01E RTO01E output select bit 2 1 read-write RTO02E RTO02E output select bit 4 1 read-write RTO03E RTO03E output select bit 6 1 read-write RTO04E RTO04E output select bit 8 1 read-write RTO05E RTO05E output select bit 10 1 read-write EPFR02 Extended pin function setting register 02 0x608 32 read-write n 0x0 0x0 DTTI1C DTTIX1 function select bit 12 read-write DTTI1S DTTIX1 input select bit 16 1 read-write FRCK1S FRCK1 input select bit 18 1 read-write IC10S IC10 input select bit 20 2 read-write IC11S IC11 input select bit 23 2 read-write IC12S IC12 input select bit 26 2 read-write IC13S IC13 input select bit 29 2 read-write RTO10E RTO10E output select bit 0 1 read-write RTO11E RTO11E output select bit 2 1 read-write RTO12E RTO12E output select bit 4 1 read-write RTO13E RTO13E output select bit 6 1 read-write RTO14E RTO14E output select bit 8 1 read-write RTO15E RTO15E output select bit 10 1 read-write EPFR03 Extended pin function setting register 03 0x60C 32 read-write n 0x0 0x0 DTTI2C DTTIX2 function select bit 12 read-write DTTI2S DTTIX2 input select bit 16 1 read-write FRCK2S FRCK2 input select bit 18 1 read-write IC20S IC20 input select bit 20 2 read-write IC21S IC21 input select bit 23 2 read-write IC22S IC22 input select bit 26 2 read-write IC23S IC23 input select bit 29 2 read-write RTO20E RTO20E output select bit 0 1 read-write RTO21E RTO21E output select bit 2 1 read-write RTO22E RTO22E output select bit 4 1 read-write RTO23E RTO23E output select bit 6 1 read-write RTO24E RTO24E output select bit 8 1 read-write RTO25E RTO25E output select bit 10 1 read-write EPFR04 Extended pin function setting register 04 0x610 32 read-write n 0x0 0x0 TIOA0E TIOA0 output select bit 2 1 read-write TIOA1E TIOA1E output select bit 10 1 read-write TIOA1S TIOA1 input select bit 8 1 read-write TIOA2E TIOA2 output select bit 18 1 read-write TIOA3E TIOA3E output select bit 26 1 read-write TIOA3S TIOA3 input select bit 24 1 read-write TIOB0S TIOB0 input select bit 4 1 read-write TIOB1S TIOB1 input select bit 12 1 read-write TIOB2S TIOB2 input select bit 20 1 read-write TIOB3S TIOB3 input select bit 28 1 read-write EPFR05 Extended pin function setting register 05 0x614 32 read-write n 0x0 0x0 TIOA4E TIOA4 output select bit 2 1 read-write TIOA5E TIOA5E output select bit 10 1 read-write TIOA5S TIOA5 input select bit 8 1 read-write TIOA6E TIOA6 output select bit 18 1 read-write TIOA7E TIOA7E output select bit 26 1 read-write TIOA7S TIOA7 input select bit 24 1 read-write TIOB4S TIOB4 input select bit 4 1 read-write TIOB5S TIOB5 input select bit 12 1 read-write TIOB6S TIOB6 input select bit 20 1 read-write TIOB7S TIOB7 input select Bit 28 1 read-write EPFR06 Extended pin function setting register 06 0x618 32 read-write n 0x0 0x0 EINT00S External interrupt 0 input select bit 0 1 read-write EINT01S External interrupt 1 input select bit 2 1 read-write EINT02S External interrupt 2 input select bit 4 1 read-write EINT03S External interrupt 3 input select bit 6 1 read-write EINT04S External interrupt 4 input select bit 8 1 read-write EINT05S External interrupt 5 input select bit 10 1 read-write EINT06S External interrupt 6 input select bit 12 1 read-write EINT07S External interrupt 7 input select bit 14 1 read-write EINT08S External interrupt 8 input select bit 16 1 read-write EINT09S External interrupt 9 input select bit 18 1 read-write EINT10S External interrupt 10 input select bit 20 1 read-write EINT11S External interrupt 11 input select bit 22 1 read-write EINT12S External interrupt 12 input select bit 24 1 read-write EINT13S External interrupt 13 input select bit 26 1 read-write EINT14S External interrupt 14 input select bit 28 1 read-write EINT15S External interrupt 15 input select bit 30 1 read-write EPFR07 Extended pin function setting register 07 0x61C 32 read-write n 0x0 0x0 SCK0B SCK0 input/output select bit 8 1 read-write SCK1B SCK1 input/output select bit 14 1 read-write SCK2B SCK2 input/output select bit 20 1 read-write SCK3B SCK3 input/output select bit 26 1 read-write SIN0S SIN0S input select bit 4 1 read-write SIN1S SIN1S input select bit 10 1 read-write SIN2S SIN2S input select bit 16 1 read-write SIN3S SIN3S input select bit 22 1 read-write SOT0B SOT0B input/output select bit 6 1 read-write SOT1B SCK1B input/output select bit 12 1 read-write SOT2B SOT2B input/output select bit 18 1 read-write SOT3B SOT3B input/output select bit 24 1 read-write EPFR08 Extended pin function setting register 08 0x620 32 read-write n 0x0 0x0 CTS4S CTS4S input select bit 2 1 read-write RTS4E RTS4E output select bit 0 1 read-write SCK4B SCK4 input/output select bit 8 1 read-write SCK5B SCK5 input/output select bit 14 1 read-write SCK6B SCK6 input/output select bit 20 1 read-write SCK7B SCK7 input/output select bit 26 1 read-write SIN4S SIN4S input select bit 4 1 read-write SIN5S SIN5S input select bit 10 1 read-write SIN6S SIN6S input select bit 16 1 read-write SIN7S SIN7S input select bit 22 1 read-write SOT4B SOT4B input/output select bit 6 1 read-write SOT5B SOT5B input/output select bit 12 1 read-write SOT6B SOT6B input/output select bit 18 1 read-write SOT7B SOT7B input/output select bit 24 1 read-write EPFR09 Extended pin function setting register 09 0x624 32 read-write n 0x0 0x0 ADTRG0S ADTRG0 input select bit 12 3 read-write ADTRG1S ADTRG1 input select bit 16 3 read-write ADTRG2S ADTRG2 input select bit 20 3 read-write QAIN0S QAIN0S input select bit 0 1 read-write QAIN1S QAIN1S input select bit 6 1 read-write QBIN0S QBIN0S input select bit 2 1 read-write QBIN1S QBIN1S input select bit 8 1 read-write QZIN0S QZIN0S input select bit 4 1 read-write QZIN1S QZIN1S input select bit 10 1 read-write EPFR10 Extended pin function setting register 10 0x628 32 read-write n 0x0 0x0 UEA08E UEA08E output select bit 15 read-write UEA09E UEA09E output select bit 16 read-write UEA10E UEA10E output select bit 17 read-write UEA11E UEA11E output select bit 18 read-write UEA12E UEA12E output select bit 19 read-write UEA13E UEA13E output select bit 20 read-write UEA14E UEA14E output select bit 21 read-write UEA15E UEA15E output select bit 22 read-write UEA16E UEA16E output select bit 23 read-write UEA17E UEA17E output select bit 24 read-write UEA18E UEA18E output select bit 25 read-write UEAOOE UEAOOE output select bit 14 read-write UECLKE UECLKE output select bit 2 read-write UECS1E UECS1E output select bit 7 read-write UECS2E UECS2E output select bit 8 read-write UECS3E UECS3E output select bit 9 read-write UECS4E UECS4E output select bit 10 read-write UECS5E UECS5E output select bit 11 read-write UECS6E UECS6E output select bit 12 read-write UECS7E UECS7E output select bit 13 read-write UEDEFB UEDEFB input/output select bit 0 read-write UEDQME UEDQME output select bit 4 read-write UEDTHB UEDTHB input/output select bit 1 read-write UEFLSE UEFLSE output select bit 6 read-write UEOEXE UEOEXE output select bit 5 read-write UEWEXE UEWEXE output select bit 3 read-write EPFR11 Extended pin function setting register 11 0x62C 32 read-write n 0x0 0x0 UEA01E UEA01E output select bit 2 read-write UEA02E UEA02E output select bit 3 read-write UEA03E UEA03E output select bit 4 read-write UEA04E UEA04E output select bit 5 read-write UEA05E UEA05E output select bit 6 read-write UEA06E UEA06E output select bit 7 read-write UEA07E UEA07E output select bit 8 read-write UEALEE UEALEE output select bit 0 read-write UECS0E UECS0E output select bit 1 read-write UED00B UED00B output select bit 9 read-write UED01B UED01B output select bit 10 read-write UED02B UED02B output select bit 11 read-write UED03B UED03B output select bit 12 read-write UED04B UED04B output select bit 13 read-write UED05B UED05B output select bit 14 read-write UED06B UED06B output select bit 15 read-write UED07B UED07B output select bit 16 read-write UED08B UED08B output select bit 17 read-write UED09B UED09B output select bit 18 read-write UED10B UED10B output select bit 19 read-write UED11B UED11B output select bit 20 read-write UED12B UED12B output select bit 21 read-write UED13B UED13B output select bit 22 read-write UED14B UED14B output select bit 23 read-write UED15B UED15B input/output select bit 24 read-write UERLC UERLC relocation select bit 25 read-write EPFR12 Extended pin function setting register 12 0x630 32 read-write n 0x0 0x0 TIOA10E TIOA10 Output Select bits 18 1 read-write TIOA11E TIOA11 Output Select bits 26 1 read-write TIOA11S TIOA11 Input Select bits 24 1 read-write TIOA8E TIOA8 Output Select bits 2 1 read-write TIOA9E TIOA9 Output Select bits 10 1 read-write TIOA9S TIOA9 Input Select bits 8 1 read-write TIOB10S TIOB10 Input Select bits 20 1 read-write TIOB11S TIOB11 Input Select bits 28 1 read-write TIOB8S TIOB8 Input Select bits 4 1 read-write TIOB9S TIOB9 Input Select bits 12 1 read-write EPFR13 Extended pin function setting register 13 0x634 32 read-write n 0x0 0x0 TIOA12E TIOA12 Output Select bits 2 1 read-write TIOA13E TIOA13 Output Select bits 10 1 read-write TIOA13S TIOA13 Input Select bits 8 1 read-write TIOA14E TIOA14 Output Select bits 18 1 read-write TIOA15E TIOA15 Output Select bits 26 1 read-write TIOA15S TIOA15 Input Select bits 24 1 read-write TIOB12S TIOB12 Input Select bits 4 1 read-write TIOB13S TIOB13 Input Select bits 12 1 read-write TIOB14S TIOB14 Input Select bits 20 1 read-write TIOB15S TIOB15 Input Select bits 28 1 read-write EPFR14 Extended pin function setting register 14 0x638 32 read-write n 0x0 0x0 E_CKE E_COUT Output Select bit 26 read-write E_MC0E E_MDC0 Output Select bit 22 read-write E_MC1B E_MDC1 I/O Select bit 23 read-write E_MD0B E_MDO0 I/O Select bit 24 read-write E_MD1B E_MDO1 I/O Select bit 25 read-write E_PSE PPS0_PPS1 Output Select bit for Ethernet 27 read-write E_SPLC Input cutoff Select bit in Standby of input Pin for Ethernet 28 1 read-write E_TD0E E_TX00, E_TX01 Output Select bit 18 read-write E_TD1E E_TX02_TX10, E_TX03_TX11 Output Select bit 19 read-write E_TE0E E_TXEN0 Output Select bit 20 read-write E_TE1E E_TXER0_TXEN1 Output Select bit 21 read-write QAIN2S QDU-ch.2 AIN Input Pin bits 0 1 read-write QBIN2S QDU-ch.2 BIN Input Pin bits 2 1 read-write QZIN2S QDU-ch.2 ZIN Input Pin bits 4 1 read-write EPFR15 Extended pin function setting register 15 0x63C 32 read-write n 0x0 0x0 EINT16S External interrupt 16 input select bit 0 1 read-write EINT17S External interrupt 17 input select bit 2 1 read-write EINT18S External interrupt 18 input select bit 4 1 read-write EINT19S External interrupt 19 input select bit 6 1 read-write EINT20S External interrupt 20 input select bit 8 1 read-write EINT21S External interrupt 21 input select bit 10 1 read-write EINT22S External interrupt 22 input select bit 12 1 read-write EINT23S External interrupt 23 input select bit 14 1 read-write EINT24S External interrupt 24 input select bit 16 1 read-write EINT25S External interrupt 25 input select bit 18 1 read-write EINT26S External interrupt 26 input select bit 20 1 read-write EINT27S External interrupt 27 input select bit 22 1 read-write EINT28S External interrupt 28 input select bit 24 1 read-write EINT29S External interrupt 29 input select bit 26 1 read-write EINT30S External interrupt 30 input select bit 28 1 read-write EINT31S External interrupt 31 input select bit 30 1 read-write PCR0 Pull-up Setting Register 0 0x100 read-write n 0x0 0x0 PCR1 Pull-up Setting Register 1 0x104 read-write n 0x0 0x0 PCR2 Pull-up Setting Register 2 0x108 read-write n 0x0 0x0 PCR3 Pull-up Setting Register 3 0x10C read-write n 0x0 0x0 PCR4 Pull-up Setting Register 4 0x110 read-write n 0x0 0x0 PCR5 Pull-up Setting Register 5 0x114 read-write n 0x0 0x0 PCR6 Pull-up Setting Register 6 0x118 read-write n 0x0 0x0 PCR7 Pull-up Setting Register 7 0x11C read-write n 0x0 0x0 PCR8 Pull-up Setting Register 8 0x120 read-write n 0x0 0x0 PCRA Pull-up Setting Register A 0x128 read-write n 0x0 0x0 PCRC Pull-up Setting Register C 0x130 read-write n 0x0 0x0 PCRD Pull-up Setting Register D 0x134 read-write n 0x0 0x0 PCRE Pull-up Setting Register E 0x138 read-write n 0x0 0x0 PCRF Pull-up Setting Register F 0x13C read-write n 0x0 0x0 PDIR0 Port input data register 0 0x300 read-write n 0x0 0x0 PDIR1 Port input data register 1 0x304 read-write n 0x0 0x0 PDIR2 Port input data register 2 0x308 read-write n 0x0 0x0 PDIR3 Port input data register 3 0x30C read-write n 0x0 0x0 PDIR4 Port input data register 4 0x310 read-write n 0x0 0x0 PDIR5 Port input data register 5 0x314 read-write n 0x0 0x0 PDIR6 Port input data register 6 0x318 read-write n 0x0 0x0 PDIR7 Port input data register 7 0x31C read-write n 0x0 0x0 PDIR8 Port input data register 8 0x320 read-write n 0x0 0x0 PDIRA Port input data register A 0x328 read-write n 0x0 0x0 PDIRC Port input data register C 0x330 read-write n 0x0 0x0 PDIRD Port input data register D 0x334 read-write n 0x0 0x0 PDIRE Port input data register E 0x338 read-write n 0x0 0x0 PDIRF Port input data register F 0x33C read-write n 0x0 0x0 PDOR0 Port output data register 0 0x400 read-write n 0x0 0x0 PDOR1 Port output data register 1 0x404 read-write n 0x0 0x0 PDOR2 Port output data register 2 0x408 read-write n 0x0 0x0 PDOR3 Port output data register 3 0x40C read-write n 0x0 0x0 PDOR4 Port output data register 4 0x410 read-write n 0x0 0x0 PDOR5 Port output data register 5 0x414 read-write n 0x0 0x0 PDOR6 Port output data register 6 0x418 read-write n 0x0 0x0 PDOR7 Port output data register 7 0x41C read-write n 0x0 0x0 PDOR8 Port output data register 8 0x420 read-write n 0x0 0x0 PDORA Port output data register A 0x428 read-write n 0x0 0x0 PDORC Port output data register C 0x430 read-write n 0x0 0x0 PDORD Port output data register D 0x434 read-write n 0x0 0x0 PDORE Port output data register E 0x438 read-write n 0x0 0x0 PDORF Port output data register F 0x43C read-write n 0x0 0x0 PFR0 Port function setting register 0 0x0 32 read-write n 0x0 0x0 P00 Bit0 of PFR0 0 read-write P01 Bit1 of PFR0 1 read-write P02 Bit2 of PFR0 2 read-write P03 Bit3 of PFR0 3 read-write P04 Bit4 of PFR0 4 read-write P05 Bit5 of PFR0 5 read-write P06 Bit6 of PFR0 6 read-write P07 Bit7 of PFR0 7 read-write P08 Bit8 of PFR0 8 read-write P09 Bit9 of PFR0 9 read-write PFR1 Port function setting register 1 0x4 32 read-write n 0x0 0x0 P10 Bit0 of PFR1 0 read-write P11 Bit1 of PFR1 1 read-write P12 Bit2 of PFR1 2 read-write P13 Bit3 of PFR1 3 read-write P14 Bit4 of PFR1 4 read-write P15 Bit5 of PFR1 5 read-write P16 Bit6 of PFR1 6 read-write P17 Bit7 of PFR1 7 read-write P18 Bit8 of PFR1 8 read-write P19 Bit9 of PFR1 9 read-write P1A Bit10 of PFR1 10 read-write P1B Bit11 of PFR1 11 read-write P1C Bit12 of PFR1 12 read-write P1D Bit13 of PFR1 13 read-write P1E Bit14 of PFR1 14 read-write P1F Bit15 of PFR1 15 read-write PFR2 Port function setting register 2 0x8 32 read-write n 0x0 0x0 P20 Bit0 of PFR2 0 read-write P21 Bit1 of PFR2 1 read-write P22 Bit2 of PFR2 2 read-write P23 Bit3 of PFR2 3 read-write P24 Bit4 of PFR2 4 read-write P25 Bit5 of PFR2 5 read-write P26 Bit6 of PFR2 6 read-write P27 Bit7 of PFR2 7 read-write P28 Bit8 of PFR2 8 read-write P29 Bit9 of PFR2 9 read-write PFR3 Port function setting register 3 0xC 32 read-write n 0x0 0x0 P36 Bit6 of PFR3 6 read-write P37 Bit7 of PFR3 7 read-write P38 Bit8 of PFR3 8 read-write P39 Bit9 of PFR3 9 read-write P3A Bit10 of PFR3 10 read-write P3B Bit11 of PFR3 11 read-write P3C Bit12 of PFR3 12 read-write P3D Bit13 of PFR3 13 read-write P3E Bit14 of PFR3 14 read-write P3F Bit15 of PFR3 15 read-write PFR4 Port function setting register 4 0x10 32 read-write n 0x0 0x0 P40 Bit0 of PFR4 0 read-write P41 Bit1 of PFR4 1 read-write P42 Bit2 of PFR4 2 read-write P43 Bit3 of PFR4 3 read-write P44 Bit4 of PFR4 4 read-write P45 Bit5 of PFR4 5 read-write P46 Bit6 of PFR4 6 read-write P47 Bit7 of PFR4 7 read-write P48 Bit8 of PFR4 8 read-write P49 Bit9 of PFR4 9 read-write P4A Bit10 of PFR4 10 read-write P4B Bit11 of PFR4 11 read-write P4C Bit12 of PFR4 12 read-write P4D Bit13 of PFR4 13 read-write P4E Bit14 of PFR4 14 read-write PFR5 Port function setting register 5 0x14 32 read-write n 0x0 0x0 P50 Bit0 of PFR5 0 read-write P51 Bit1 of PFR5 1 read-write P52 Bit2 of PFR5 2 read-write P53 Bit3 of PFR5 3 read-write P54 Bit4 of PFR5 4 read-write P55 Bit5 of PFR5 5 read-write P56 Bit6 of PFR5 6 read-write P57 Bit7 of PFR5 7 read-write P58 Bit8 of PFR5 8 read-write P59 Bit9 of PFR5 9 read-write P5A Bit10 of PFR5 10 read-write P5B Bit11 of PFR5 11 read-write PFR6 Port function setting register 6 0x18 32 read-write n 0x0 0x0 P60 Bit0 of PFR6 0 read-write P61 Bit1 of PFR6 1 read-write P62 Bit2 of PFR6 2 read-write PFR7 Port function setting register 7 0x1C 32 read-write n 0x0 0x0 P70 Bit0 of PFR7 0 read-write P71 Bit1 of PFR7 1 read-write P72 Bit2 of PFR7 2 read-write P73 Bit3 of PFR7 3 read-write P74 Bit4 of PFR7 4 read-write P75 Bit5 of PFR7 5 read-write P76 Bit6 of PFR7 6 read-write P77 Bit7 of PFR7 7 read-write P78 Bit8 of PFR7 8 read-write P79 Bit9 of PFR7 9 read-write P7A Bit10 of PFR7 10 read-write PFR8 Port function setting register 8 0x20 32 read-write n 0x0 0x0 P80 Bit0 of PFR8 0 read-write P81 Bit1 of PFR8 1 read-write P82 Bit2 of PFR8 2 read-write P83 Bit3 of PFR8 3 read-write PFRA Port function setting register A 0x28 32 read-write n 0x0 0x0 PA0 Bit0 of PFRA 0 read-write PA1 Bit1 of PFRA 1 read-write PA2 Bit2 of PFRA 2 read-write PA3 Bit3 of PFRA 3 read-write PA4 Bit4 of PFRA 4 read-write PA5 Bit5 of PFRA 5 read-write PFRC Port function setting register C 0x30 32 read-write n 0x0 0x0 PC0 Bit0 of PFRC 0 read-write PC1 Bit1 of PFRC 1 read-write PC2 Bit2 of PFRC 2 read-write PC3 Bit3 of PFRC 3 read-write PC4 Bit4 of PFRC 4 read-write PC5 Bit5 of PFRC 5 read-write PC6 Bit6 of PFRC 6 read-write PC7 Bit7 of PFRC 7 read-write PC8 Bit8 of PFRC 8 read-write PC9 Bit9 of PFRC 9 read-write PCA Bit10 of PFRC 10 read-write PCB Bit11 of PFRC 11 read-write PCC Bit12 of PFRC 12 read-write PCD Bit13 of PFRC 13 read-write PCE Bit14 of PFRC 14 read-write PCF Bit15 of PFRC 15 read-write PFRD Port function setting register D 0x34 32 read-write n 0x0 0x0 PD0 Bit0 of PFRD 0 read-write PD1 Bit1 of PFRD 1 read-write PD2 Bit2 of PFRD 2 read-write PD3 Bit3 of PFRD 3 read-write PFRE Port function setting register E 0x38 32 read-write n 0x0 0x0 PE0 Bit0 of PFRE 0 read-write PE2 Bit2 of PFRE 2 read-write PE3 Bit3 of PFRE 3 read-write PFRF Port function setting register F 0x3C 32 read-write n 0x0 0x0 PF5 Bit5 of PFRF 5 read-write PF6 Bit6 of PFRF 6 read-write PZR0 Port Pseudo Open Drain Setting Register 0 0x700 read-write n 0x0 0x0 PZR1 Port Pseudo Open Drain Setting Register 1 0x704 read-write n 0x0 0x0 PZR2 Port Pseudo Open Drain Setting Register 2 0x708 read-write n 0x0 0x0 PZR3 Port Pseudo Open Drain Setting Register 3 0x70C read-write n 0x0 0x0 PZR4 Port Pseudo Open Drain Setting Register 4 0x710 read-write n 0x0 0x0 PZR5 Port Pseudo Open Drain Setting Register 5 0x714 read-write n 0x0 0x0 PZR6 Port Pseudo Open Drain Setting Register 6 0x718 read-write n 0x0 0x0 PZR7 Port Pseudo Open Drain Setting Register 7 0x71C read-write n 0x0 0x0 PZR8 Port Pseudo Open Drain Setting Register 8 0x720 read-write n 0x0 0x0 PZRA Port Pseudo Open Drain Setting Register A 0x728 read-write n 0x0 0x0 PZRC Port Pseudo Open Drain Setting Register C 0x730 read-write n 0x0 0x0 PZRD Port Pseudo Open Drain Setting Register D 0x734 read-write n 0x0 0x0 PZRE Port Pseudo Open Drain Setting Register E 0x738 read-write n 0x0 0x0 PZRF Port Pseudo Open Drain Setting Register F 0x73C read-write n 0x0 0x0 SPSR Special port setting register 0x580 32 read-write n 0x0 0x0 MAINXC Main clock(oscillation) pin setting bit 2 read-write SUBXC Sub clock(oscillation) pin setting bit 0 read-write USB0C USBch0 pin setting bit 4 read-write USB1C USBch1 pin setting bit 5 read-write HWWDT Hardware Watchdog Timer HWWDT 0x0 0x0 0x4 registers n 0x10 0x1 registers n 0x4 0x4 registers n 0x8 0x4 registers n 0xC 0x1 registers n 0xC00 0x4 registers n WDG_CTL Hardware Watchdog Timer Control Register 0x8 32 read-write n 0x0 0x0 INTEN Hardware watchdog interrupt and counter enable bit 0 read-write RESEN Hardware watchdog reset enable bit 1 read-write WDG_ICL Hardware Watchdog Timer Clear Register 0xC 8 read-write n 0x0 0x0 WDG_LCK Hardware Watchdog Timer Lock Register 0xC00 32 read-write n 0x0 0x0 WDG_LDR Hardware Watchdog Timer Load Register 0x0 32 read-write n 0x0 0x0 WDG_RIS Hardware Watchdog Timer Interrupt Status Register 0x10 1 read-only n 0x0 0x0 RIS Hardware watchdog interrupt status bit 0 read-only WDG_VLR Hardware Watchdog Timer Value Register 0x4 32 read-only n 0x0 0x0 INTREQ Interrupts INTREQ 0x0 0x0 0x4 registers n 0x10 0xC4 registers n 0x200 0x8 registers n 0x20F 0x1 registers n 0xB 0x1 registers n DQESEL DMA Request Extended Selection Register 0x204 32 read-write n 0x0 0x0 ESEL10 Connect USB-ch1 to IDREQ [10] 0 3 read-write ESEL11 Connect USB-ch1 to IDREQ [11] 4 3 read-write ESEL24 Connect USB-ch1 to IDREQ [24] 8 3 read-write ESEL25 Connect USB-ch1 to IDREQ [25] 12 3 read-write ESEL26 Connect USB-ch1 to IDREQ [26] 16 3 read-write ESEL27 Connect USB-ch1 to IDREQ [27] 20 3 read-write ESEL30 Connect USB-ch1 to IDREQ [30] 24 3 read-write ESEL31 Connect USB-ch1 to IDREQ [31] 28 3 read-write DRQSEL DMA Request Selection Register 0x0 32 read-write n 0x0 0x0 ADCSCAN0 The scan conversion interrupt signal of the A/D converter unit 0 is output as a transfer request to the DMAC. 5 read-write ADCSCAN1 The scan conversion interrupt signal of the A/D converter unit 1 is output as a transfer request to the DMAC. 6 read-write ADCSCAN2 The scan conversion interrupt signal of the A/D converter unit 2 is output as a transfer request to the DMAC. 7 read-write EXINT0 The interrupt signal of the external interrupt ch.0 is output as a transfer request to the DMAC (including extension). 28 read-write EXINT1 The interrupt signal of the external interrupt ch.1 is output as a transfer request to the DMAC (including extension). 29 read-write EXINT2 The interrupt signal of the external interrupt ch.2 is output as a transfer request to the DMAC (including extension). 30 read-write EXINT3 The interrupt signal of the external interrupt ch.3 is output as a transfer request to the DMAC (including extension). 31 read-write IRQ0BT0 The IRQ0 interrupt signal of the base timer ch.0 is output as a transfer request to the DMAC. 8 read-write IRQ0BT2 The IRQ0 interrupt signal of the base timer ch.3 is output as a transfer request to the DMAC. 9 read-write IRQ0BT3 The IRQ0 interrupt signal of the base timer ch.3 is output as a transfer request to the DMAC. 9 read-write IRQ0BT4 The IRQ0 interrupt signal of the base timer ch.4 is output as a transfer request to the DMAC. 10 read-write IRQ0BT6 The IRQ0 interrupt signal of the base timer ch.6 is output as a transfer request to the DMAC. 11 read-write MFS0RX The reception interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC (including extension). 12 read-write MFS0TX The transmission interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC (including extension). 13 read-write MFS1RX The reception interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC (including extension). 14 read-write MFS1TX The transmission interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC (including extension). 15 read-write MFS2RX The reception interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC (including extension). 16 read-write MFS2TX The transmission interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC (including extension). 17 read-write MFS3RX The reception interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC (including extension). 18 read-write MFS3TX The transmission interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC (including extension). 19 read-write MFS4RX The reception interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC (including extension). 20 read-write MFS4TX The transmission interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC (including extension). 21 read-write MFS5RX The reception interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC (including extension). 22 read-write MFS5TX The transmission interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC (including extension). 23 read-write MFS6RX The reception interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC (including extension). 24 read-write MFS6TX The transmission interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC (including extension). 25 read-write MFS7RX The reception interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC (including extension). 26 read-write MFS7TX The transmission interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC (including extension). 27 read-write USBEP1 The EP1 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC. 0 read-write USBEP2 The EP2 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC. 1 read-write USBEP3 The EP3 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC. 2 read-write USBEP4 The EP4 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC. 3 read-write USBEP5 The EP5 DRQ interrupt signal of the USB ch.0 is output as a transfer request to the DMAC. 4 read-write DRQSEL1 DMA Request Select Register 1 0x200 32 read-write n 0x0 0x0 DRQSEL10 Interrupt signal of EP1 DRQ of USB ch.1 is output to transfer request to DMAC through extended selector 0 read-write DRQSEL11 Interrupt signal of EP2 DRQ of USB ch.1 is output to transfer request to DMAC through extended selector 1 read-write DRQSEL12 Interrupt signal of EP3 DRQ of USB ch.1 is output to transfer request to DMAC through extended selector 2 read-write DRQSEL13 Interrupt signal of EP4 DRQ of USB ch.1 is output to transfer request to DMAC through extended selector 3 read-write DRQSEL14 Interrupt signal of EP5 DRQ of USB ch.1 is output to transfer request to DMAC through extended selector 4 read-write EXC02MON EXC02 batch read register 0x10 32 read-only n 0x0 0x0 HWINT Hardware watchdog timer interrupt request 1 read-only NMI External NMIX pin interrupt request 0 read-only IRQ00MON IRQ00 Batch Read Register 0x14 32 read-only n 0x0 0x0 FCSINT Anomalous frequency detection by CSV interrupt request 0 read-only IRQ01MON IRQ01 Batch Read Register 0x18 32 read-only n 0x0 0x0 SWWDTINT Software watchdog timer interrupt request 0 read-only IRQ02MON IRQ02 Batch Read Register 0x1C 32 read-only n 0x0 0x0 LVDINT Low voltage detection (LVD) interrupt request 0 read-only IRQ03MON IRQ03 Batch Read Register 0x20 32 read-only n 0x0 0x0 WAVE0INT0 DTIF (motor emergency stop) interrupt request in MFT unit 0 0 read-only WAVE0INT1 WFG timer 10 interrupt request in MFT unit 0 1 read-only WAVE0INT2 WFG timer 32 interrupt request in MFT unit 0 2 read-only WAVE0INT3 WFG timer 54 interrupt request in MFT unit 0 3 read-only WAVE1INT0 DTIF (motor emergency stop) interrupt request in MFT unit 1 4 read-only WAVE1INT1 WFG timer 10 interrupt request in MFT unit 1 5 read-only WAVE1INT2 WFG timer 32 interrupt request in MFT unit 1 6 read-only WAVE1INT3 WFG timer 54 interrupt request in MFT unit 1 7 read-only WAVE2INT0 DTIF (motor emergency stop) interrupt request in MFT unit 2 8 read-only WAVE2INT1 WFG timer 10 interrupt request in MFT unit 2 9 read-only WAVE2INT2 WFG timer 32 interrupt request in MFT unit 2 10 read-only WAVE2INT3 WFG timer 54 interrupt request in MFT unit 2 11 read-only IRQ04MON IRQ04 Batch Read Register 0x24 32 read-only n 0x0 0x0 EXTINT0 Interrupt request on external interrupt ch.0 0 read-only EXTINT1 Interrupt request on external interrupt ch.1 1 read-only EXTINT2 Interrupt request on external interrupt ch.2 2 read-only EXTINT3 Interrupt request on external interrupt ch.3 3 read-only EXTINT4 Interrupt request on external interrupt ch.4 4 read-only EXTINT5 Interrupt request on external interrupt ch.5 5 read-only EXTINT6 Interrupt request on external interrupt ch.6 6 read-only EXTINT7 Interrupt request on external interrupt ch.7 7 read-only IRQ05MON IRQ05 Batch Read Register 0x28 32 read-only n 0x0 0x0 EXTINT0 Interrupt request on external interrupt ch.8 0 read-only EXTINT1 Interrupt request on external interrupt ch.9 1 read-only EXTINT10 Interrupt request on external interrupt ch.18 10 read-only EXTINT11 Interrupt request on external interrupt ch.19 11 read-only EXTINT12 Interrupt request on external interrupt ch.20 12 read-only EXTINT13 Interrupt request on external interrupt ch.21 13 read-only EXTINT14 Interrupt request on external interrupt ch.22 14 read-only EXTINT15 Interrupt request on external interrupt ch.23 15 read-only EXTINT16 Interrupt request on external interrupt ch.24 16 read-only EXTINT17 Interrupt request on external interrupt ch.25 17 read-only EXTINT18 Interrupt request on external interrupt ch.26 18 read-only EXTINT19 Interrupt request on external interrupt ch.27 19 read-only EXTINT2 Interrupt request on external interrupt ch.10 2 read-only EXTINT20 Interrupt request on external interrupt ch.28 20 read-only EXTINT21 Interrupt request on external interrupt ch.29 21 read-only EXTINT22 Interrupt request on external interrupt ch.30 22 read-only EXTINT23 Interrupt request on external interrupt ch.31 23 read-only EXTINT3 Interrupt request on external interrupt ch.11 3 read-only EXTINT4 Interrupt request on external interrupt ch.12 4 read-only EXTINT5 Interrupt request on external interrupt ch.13 5 read-only EXTINT6 Interrupt request on external interrupt ch.14 6 read-only EXTINT7 Interrupt request on external interrupt ch.15 7 read-only EXTINT8 Interrupt request on external interrupt ch.16 8 read-only EXTINT9 Interrupt request on external interrupt ch.17 9 read-only IRQ06MON IRQ06 Batch Read Register 0x2C 32 read-only n 0x0 0x0 QUD0INT0 PC match interrupt request on QPRC ch.0 2 read-only QUD0INT1 PC and RC match interrupt request on QPRC ch.0 3 read-only QUD0INT2 Overflow/underflow/zero index interrupt request on QPRC ch.0 4 read-only QUD0INT3 PC count invert interrupt request on QPRC ch.0 5 read-only QUD0INT4 Interrupt request detected RC out of range on QPRC ch.0 6 read-only QUD0INT5 PC match and RC match interrupt request on QPRC ch.0 7 read-only QUD1INT0 PC match interrupt request on QPRC ch.1 8 read-only QUD1INT1 PC and RC match interrupt request on QPRC ch.1 9 read-only QUD1INT2 Overflow/underflow/zero index interrupt request on QPRC ch.1 10 read-only QUD1INT3 PC count invert interrupt request on QPRC ch.1 11 read-only QUD1INT4 Interrupt request detected RC out of range on QPRC ch.1 12 read-only QUD1INT5 PC match and RC match interrupt request on QPRC ch.1 13 read-only QUD2INT0 PC match interrupt request on QPRC ch.2 14 read-only QUD2INT1 PC and RC match interrupt request on QPRC ch.2 15 read-only QUD2INT2 Overflow/underflow/zero index interrupt request on QPRC ch.2 16 read-only QUD2INT3 PC count invert interrupt request on QPRC ch.2 17 read-only QUD2INT4 Interrupt request detected RC out of range on QPRC ch.2 18 read-only QUD2INT5 PC match and RC match interrupt request on QPRC ch.2 19 read-only TIMINT1 Dual timer 1 interrupt request 0 read-only TIMINT2 Dual timer 2 interrupt request 1 read-only IRQ07MON IRQ07 Batch Read Register 0x30 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.0 0 read-only IRQ08MON IRQ08 Batch Read Register 0x34 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.0 0 read-only MFSINT1 Status interrupt request on MFS ch.0 1 read-only IRQ09MON IRQ09 Batch Read Register 0x38 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.1 0 read-only IRQ10MON IRQ10 Batch Read Register 0x3C 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.1 0 read-only MFSINT1 Status interrupt request on MFS ch.1 1 read-only IRQ11MON IRQ11 Batch Read Register 0x40 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.2 0 read-only IRQ12MON IRQ12 Batch Read Register 0x44 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.2 0 read-only MFSINT1 Status interrupt request on MFS ch.2 1 read-only IRQ13MON IRQ13 Batch Read Register 0x48 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.3 0 read-only IRQ14MON IRQ14 Batch Read Register 0x4C 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.3 0 read-only MFSINT1 Status interrupt request on MFS ch.3 1 read-only IRQ15MON IRQ15 Batch Read Register 0x50 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.4 0 read-only IRQ16MON IRQ16 Batch Read Register 0x54 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.4 0 read-only MFSINT1 Status interrupt request on MFS ch.4 1 read-only IRQ17MON IRQ17 Batch Read Register 0x58 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.5 0 read-only IRQ18MON IRQ18 Batch Read Register 0x5C 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.5 0 read-only MFSINT1 Status interrupt request on MFS ch.5 1 read-only IRQ19MON IRQ19 Batch Read Register 0x60 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.6 0 read-only IRQ20MON IRQ20 Batch Read Register 0x64 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.6 0 read-only MFSINT1 Status interrupt request on MFS ch.6 1 read-only IRQ21MON IRQ21 Batch Read Register 0x68 32 read-only n 0x0 0x0 MFSINT Reception interrupt request on MFS ch.7 0 read-only IRQ22MON IRQ22 Batch Read Register 0x6C 32 read-only n 0x0 0x0 MFSINT0 Transmission interrupt request on MFS ch.7 0 read-only MFSINT1 Status interrupt request on MFS ch.7 1 read-only IRQ23MON IRQ23 Batch Read Register 0x70 32 read-only n 0x0 0x0 PPGINT0 Interrupt request on PPG ch.0 0 read-only PPGINT1 Interrupt request on PPG ch.2 1 read-only PPGINT2 Interrupt request on PPG ch.4 2 read-only PPGINT3 Interrupt request on PPG ch.8 3 read-only PPGINT4 Interrupt request on PPG ch.10 4 read-only PPGINT5 Interrupt request on PPG ch.12 5 read-only PPGINT6 Interrupt request on PPG ch.16 6 read-only PPGINT7 Interrupt request on PPG ch.18 7 read-only PPGINT8 Interrupt request on PPG ch.20 8 read-only IRQ24MON IRQ24 Batch Read Register 0x74 32 read-only n 0x0 0x0 MOSCINT Stabilization wait completion interrupt request for main clock oscillation 0 read-only MPLLINT Stabilization wait completion interrupt request for main PLL oscillation 2 read-only SOSCINT Stabilization wait completion interrupt request for sub-clock oscillation 1 read-only UPLLINT Stabilization wait completion interrupt request for USB or USB/Ethernet PLL oscillation. 3 read-only WCINT Watch counter interrupt request 4 read-only IRQ25MON IRQ25 Batch Read Register 0x78 32 read-only n 0x0 0x0 ADCINT0 Priority conversion interrupt request in the corresponding A/D unit 0. 0 read-only ADCINT1 Scan conversion interrupt request in the corresponding A/D unit 0. 1 read-only ADCINT2 FIFO overrun interrupt request in the corresponding A/D unit 0. 2 read-only ADCINT3 Conversion result comparison interrupt request in the corresponding A/D unit 0. 3 read-only IRQ26MON IRQ26 Batch Read Register 0x7C 32 read-only n 0x0 0x0 ADCINT0 Priority conversion interrupt request in the corresponding A/D unit 1 0 read-only ADCINT1 Scan conversion interrupt request in the corresponding A/D unit 1 1 read-only ADCINT2 FIFO overrun interrupt request in the corresponding A/D unit 1 2 read-only ADCINT3 Conversion result comparison interrupt request in the corresponding A/D unit 1 3 read-only IRQ27MON IRQ27 Batch Read Register 0x80 32 read-only n 0x0 0x0 ADCINT0 Priority conversion interrupt request in the corresponding A/D unit 2 0 read-only ADCINT1 Scan conversion interrupt request in the corresponding A/D unit 2 1 read-only ADCINT2 FIFO overrun interrupt request in the corresponding A/D unit 2 2 read-only ADCINT3 Conversion result comparison interrupt request in the corresponding A/D unit 2 3 read-only IRQ28MON IRQ28 Batch Read Register 0x84 32 read-only n 0x0 0x0 FRT0INT0 Peak value detection interrupt request on the free run timer ch.0 in the MFT unit 0 0 read-only FRT0INT1 Peak value detection interrupt request on the free run timer ch.1 in the MFT unit 0 1 read-only FRT0INT2 Peak value detection interrupt request on the free run timer ch.2 in the MFT unit 0 2 read-only FRT0INT3 Zero detection interrupt request on the free run timer ch.0 in the MFT unit 0 3 read-only FRT0INT4 Zero detection interrupt request on the free run timer ch.1 in the MFT unit 0 4 read-only FRT0INT5 Zero detection interrupt request on the free run timer ch.2 in the MFT unit 0 5 read-only FRT1INT0 Peak value detection interrupt request on the free run timer ch.0 in the MFT unit 1 6 read-only FRT1INT1 Peak value detection interrupt request on the free run timer ch.1 in the MFT unit 1 7 read-only FRT1INT2 Peak value detection interrupt request on the free run timer ch.2 in the MFT unit 1 8 read-only FRT1INT3 Zero detection interrupt request on the free run timer ch.0 in the MFT unit 1 9 read-only FRT1INT4 Zero detection interrupt request on the free run timer ch.1 in the MFT unit 1 10 read-only FRT1INT5 Zero detection interrupt request on the free run timer ch.2 in the MFT unit 1 11 read-only FRT2INT0 Peak value detection interrupt request on the free run timer ch.0 in the MFT unit 2 12 read-only FRT2INT1 Peak value detection interrupt request on the free run timer ch.1 in the MFT unit 2 13 read-only FRT2INT2 Peak value detection interrupt request on the free run timer ch.2 in the MFT unit 2 14 read-only FRT2INT3 Zero detection interrupt request on the free run timer ch.0 in the MFT unit 2 15 read-only FRT2INT4 Zero detection interrupt request on the free run timer ch.1 in the MFT unit 2 16 read-only FRT2INT5 Zero detection interrupt request on the free run timer ch.2 in the MFT unit 2 17 read-only IRQ29MON IRQ29 Batch Read Register 0x88 32 read-only n 0x0 0x0 ICU0INT0 Interrupt request on the input capture ch.0 in the MFT unit 0 0 read-only ICU0INT1 Interrupt request on the input capture ch.1 in the MFT unit 0 1 read-only ICU0INT2 Interrupt request on the input capture ch.2 in the MFT unit 0 2 read-only ICU0INT3 Interrupt request on the input capture ch.3 in the MFT unit 0 3 read-only ICU1INT0 Interrupt request on the input capture ch.0 in the MFT unit 1 4 read-only ICU1INT1 Interrupt request on the input capture ch.1 in the MFT unit 1 5 read-only ICU1INT2 Interrupt request on the input capture ch.2 in the MFT unit 1 6 read-only ICU1INT3 Interrupt request on the input capture ch.3 in the MFT unit 1 7 read-only ICU2INT0 Interrupt request on the input capture ch.0 in the MFT unit 2 8 read-only ICU2INT1 Interrupt request on the input capture ch.1 in the MFT unit 2 9 read-only ICU2INT2 Interrupt request on the input capture ch.2 in the MFT unit 2 10 read-only ICU2INT3 Interrupt request on the input capture ch.3 in the MFT unit 2 11 read-only IRQ30MON IRQ30 Batch Read Register 0x8C 32 read-only n 0x0 0x0 OCU0INT0 Interrupt request on the output compare ch.0 in the MFT unit 0 0 read-only OCU0INT1 Interrupt request on the output compare ch.1 in the MFT unit 0 1 read-only OCU0INT2 Interrupt request on the output compare ch.2 in the MFT unit 0 2 read-only OCU0INT3 Interrupt request on the output compare ch.3 in the MFT unit 0 3 read-only OCU0INT4 Interrupt request on the output compare ch.4 in the MFT unit 0 4 read-only OCU0INT5 Interrupt request on the output compare ch.5 in the MFT unit 0 5 read-only OCU1INT0 Interrupt request on the output compare ch.0 in the MFT unit 1 6 read-only OCU1INT1 Interrupt request on the output compare ch.1 in the MFT unit 1 7 read-only OCU1INT2 Interrupt request on the output compare ch.2 in the MFT unit 1 8 read-only OCU1INT3 Interrupt request on the output compare ch.3 in the MFT unit 1 9 read-only OCU1INT4 Interrupt request on the output compare ch.4 in the MFT unit 1 10 read-only OCU1INT5 Interrupt request on the output compare ch.5 in the MFT unit 1 11 read-only OCU2INT0 Interrupt request on the output compare ch.0 in the MFT unit 2 12 read-only OCU2INT1 Interrupt request on the output compare ch.1 in the MFT unit 2 13 read-only OCU2INT2 Interrupt request on the output compare ch.2 in the MFT unit 2 14 read-only OCU2INT3 Interrupt request on the output compare ch.3 in the MFT unit 2 15 read-only OCU2INT4 Interrupt request on the output compare ch.4 in the MFT unit 2 16 read-only OCU2INT5 Interrupt request on the output compare ch.5 in the MFT unit 2 17 read-only IRQ31MON IRQ31 Batch Read Register 0x90 32 read-only n 0x0 0x0 BTINT0 IRQ0 interrupt request on the base timer ch.0 0 read-only BTINT1 IRQ1 interrupt request on the base timer ch.0 1 read-only BTINT10 IRQ0 interrupt request on the base timer ch.5 10 read-only BTINT11 IRQ1 interrupt request on the base timer ch.5 11 read-only BTINT12 IRQ0 interrupt request on the base timer ch.6 12 read-only BTINT13 IRQ1 interrupt request on the base timer ch.6 13 read-only BTINT14 IRQ0 interrupt request on the base timer ch.7 14 read-only BTINT15 IRQ1 interrupt request on the base timer ch.7 15 read-only BTINT2 IRQ0 interrupt request on the base timer ch.1 2 read-only BTINT3 IRQ1 interrupt request on the base timer ch.1 3 read-only BTINT4 IRQ0 interrupt request on the base timer ch.2 4 read-only BTINT5 IRQ1 interrupt request on the base timer ch.2 5 read-only BTINT6 IRQ0 interrupt request on the base timer ch.3 6 read-only BTINT7 IRQ1 interrupt request on the base timer ch.3 7 read-only BTINT8 IRQ0 interrupt request on the base timer ch.4 8 read-only BTINT9 IRQ1 interrupt request on the base timer ch.4 9 read-only IRQ32MON IRQ32 Batch Read Register 0x94 32 read-only n 0x0 0x0 MAC0LPI LPI interrupt request of Ethernet MAC ch.0 3 read-only MAC0PMI PMI interrupt request of Ethernet MAC ch.0 2 read-only MAC0SBD SBD interrupt request of Ethernet MAC ch.0 1 read-only IRQ33MON IRQ33 Batch Read Register 0x98 32 read-only n 0x0 0x0 IRQ34MON IRQ34 Batch Read Register 0x9C 32 read-only n 0x0 0x0 USB0INT0 Endpoint 1 DRQ interrupt request on the USB ch.0 0 read-only USB0INT1 Endpoint 2 DRQ interrupt request on the USB ch.0 1 read-only USB0INT2 Endpoint 3 DRQ interrupt request on the USB ch.0 2 read-only USB0INT3 Endpoint 4 DRQ interrupt request on the USB ch.0 3 read-only USB0INT4 Endpoint 5 DRQ interrupt request on the USB ch.0 4 read-only IRQ35MON IRQ35 Batch Read Register 0xA0 32 read-only n 0x0 0x0 USB0INT0 Endpoint 0 DRQI interrupt request on the USB ch.0 0 read-only USB0INT1 Endpoint 0 DRQO interrupt request on the USB ch.0 1 read-only USB0INT2 Status (SUSP, SOF, BRST, CONF, WKUP) interrupt request on the USB ch.0 2 read-only USB0INT3 Status (SPK) interrupt request on the USB ch.0 3 read-only USB0INT4 Status (DIRQ, URIRQ, RWKIRQ, CNNIRQ) interrupt request on the USB ch.0 4 read-only USB0INT5 Status (SOFIRQ, CMPIRO) interrupt request on the USB ch.0 5 read-only IRQ36MON IRQ36 Batch Read Register 0xA4 32 read-only n 0x0 0x0 USB1INT0 Endpoint 1 DRQ interrupt request on the USB ch.1 0 read-only USB1INT1 Endpoint 2 DRQ interrupt request on the USB ch.1 1 read-only USB1INT2 Endpoint 3 DRQ interrupt request on the USB ch.1 2 read-only USB1INT3 Endpoint 4 DRQ interrupt request on the USB ch.1 3 read-only USB1INT4 Endpoint 5 DRQ interrupt request on the USB ch.1 4 read-only IRQ37MON IRQ37 Batch Read Register 0xA8 32 read-only n 0x0 0x0 USB1INT0 Endpoint 0 DRQI interrupt request on the USB ch.1 0 read-only USB1INT1 Endpoint 0 DRQO interrupt request on the USB ch.1 1 read-only USB1INT2 Status (SUSP, SOF, BRST, CONF, WKUP) interrupt request on the USB ch.1 2 read-only USB1INT3 Status (SPK) interrupt request on the USB ch.1 3 read-only USB1INT4 Status (DIRQ, URIRQ, RWKIRQ, CNNIRQ) interrupt request on the USB ch.1 4 read-only USB1INT5 Status (SOFIRQ, CMPIRO) interrupt request on the USB ch.1 5 read-only IRQ38MON IRQ38 Batch Read Register 0xAC 32 read-only n 0x0 0x0 DMAINT Interrupt request on DMA ch.0. 0 read-only IRQ39MON IRQ39 Batch Read Register 0xB0 32 read-only n 0x0 0x0 DMAINT Interrupt request on DMA ch.1. 0 read-only IRQ40MON IRQ40 Batch Read Register 0xB4 32 read-only n 0x0 0x0 DMAINT Interrupt request on DMA ch.2. 0 read-only IRQ41MON IRQ41 Batch Read Register 0xB8 32 read-only n 0x0 0x0 DMAINT Interrupt request on DMA ch.3. 0 read-only IRQ42MON IRQ42 Batch Read Register 0xBC 32 read-only n 0x0 0x0 DMAINT Interrupt request on DMA ch.4. 0 read-only IRQ43MON IRQ43 Batch Read Register 0xC0 32 read-only n 0x0 0x0 DMAINT Interrupt request on DMA ch.5. 0 read-only IRQ44MON IRQ44 Batch Read Register 0xC4 32 read-only n 0x0 0x0 DMAINT Interrupt request on DMA ch.6. 0 read-only IRQ45MON IRQ45 Batch Read Register 0xC8 32 read-only n 0x0 0x0 DMAINT Interrupt request on DMA ch.7. 0 read-only IRQ46MON IRQ46 Batch Read Register 0xCC 32 read-only n 0x0 0x0 BTINT0 IRQ0 interrupt request of base timer ch.8 0 read-only BTINT1 IRQ1 interrupt request of base timer ch.8 1 read-only BTINT10 IRQ0 interrupt request of base timer ch.13 10 read-only BTINT11 IRQ1 interrupt request of base timer ch.13 11 read-only BTINT12 IRQ0 interrupt request of base timer ch.14 12 read-only BTINT13 IRQ1 interrupt request of base timer ch.14 13 read-only BTINT14 IRQ0 interrupt request of base timer ch.15 14 read-only BTINT15 IRQ1 interrupt request of base timer ch.15 15 read-only BTINT2 IRQ0 interrupt request of base timer ch.9 2 read-only BTINT3 IRQ1 interrupt request of base timer ch.9 3 read-only BTINT4 IRQ0 interrupt request of base timer ch.10 4 read-only BTINT5 IRQ1 interrupt request of base timer ch.10 5 read-only BTINT6 IRQ0 interrupt request of base timer ch.11 6 read-only BTINT7 IRQ1 interrupt request of base timer ch.11 7 read-only BTINT8 IRQ0 interrupt request of base timer ch.12 8 read-only BTINT9 IRQ1 interrupt request of base timer ch.12 9 read-only ODDPKS USB ch.0 Odd Packet Size DMA Enable Register 0xB 8 read-write n 0x0 0x0 ODDPKS0 When the transfer destination address of DMAC is USB.EP1DT, the bit width of the last transfer data is converted to Byte. 0 read-write ODDPKS1 When the transfer destination address of DMAC is USB.EP2DT, the bit width of the last transfer data is converted to Byte. 1 read-write ODDPKS2 When the transfer destination address of DMAC is USB.EP3DT, the bit width of the last transfer data is converted to Byte. 2 read-write ODDPKS3 When the transfer destination address of DMAC is USB.EP4DT, the bit width of the last transfer data is converted to Byte. 3 read-write ODDPKS4 When the transfer destination address of DMAC is USB.EP5DT, the bit width of the last transfer data is converted to Byte. 4 read-write ODDPKS1 USB ch.1 Odd Packet Size DMA Enable Register 0x20F 8 read-write n 0x0 0x0 ODDPKS10 When the transfer destination address of the DMAC is USB.EP1DT, convert the bit width of the last transfer data to byte. 0 read-write ODDPKS11 When the transfer destination address of the DMAC is USB.EP2DT, convert the bit width of the last transfer data to byte. 1 read-write ODDPKS12 When the transfer destination address of the DMAC is USB.EP3DT, convert the bit width of the last transfer data to byte. 2 read-write ODDPKS13 When the transfer destination address of the DMAC is USB.EP4DT, convert the bit width of the last transfer data to byte. 3 read-write ODDPKS14 When the transfer destination address of the DMAC is USB.EP5DT, convert the bit width of the last transfer data to byte. 4 read-write LVD Low-voltage Detection LVD 0x0 0x0 0x1 registers n 0x4 0x1 registers n 0x8 0x1 registers n 0xC 0x5 registers n LVD 2 CLR Low-voltage Detection Interrupt Clear Register 0x8 8 read-write n 0x0 0x0 LVDCL Low-voltage detection interrupt clear bit 7 read-write CTL Low-voltage Detection Voltage Control Register 0x0 8 read-write n 0x0 0x0 LVDIE Low-voltage detection interrupt enable bit 7 read-write SVHI Low-voltage detection interrupt voltage setting bits 2 3 read-write RLR Low-voltage Detection Voltage Protection Register 0xC 32 read-write n 0x0 0x0 LVDLCK Low-voltage Detection Voltage Control Register protection bits 0 31 read-write STR Low-voltage Detection Interrupt Register 0x4 8 read-only n 0x0 0x0 LVDIR Low-voltage detection interrupt bit 7 read-only STR2 Low-voltage Detection Circuit Status Register 0x10 8 read-only n 0x0 0x0 LVDIRDY Low-voltage detection interrupt status flag 7 read-only MFS0 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS0RX 7 MFS0TX 8 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write n 0x0 0x0 DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write ESBL Extended stop bit length select bit 6 read-write LBIE LIN Break field detect interrupt enable bit 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only n 0x0 0x0 LIN_SCR Serial Control Register LIN 0x1 8 read-write n 0x0 0x0 LBR LIN Break Field setting bit (valid in master mode only) 5 read-write MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data reception enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write n 0x0 0x0 MD Operation mode setting bits 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only LBD LIN Break field detection flag bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received Error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS1 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS1RX 9 MFS1TX 10 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write n 0x0 0x0 DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write ESBL Extended stop bit length select bit 6 read-write LBIE LIN Break field detect interrupt enable bit 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only n 0x0 0x0 LIN_SCR Serial Control Register LIN 0x1 8 read-write n 0x0 0x0 LBR LIN Break Field setting bit (valid in master mode only) 5 read-write MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data reception enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write n 0x0 0x0 MD Operation mode setting bits 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only LBD LIN Break field detection flag bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received Error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS2 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS2RX 11 MFS2TX 12 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write n 0x0 0x0 DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write ESBL Extended stop bit length select bit 6 read-write LBIE LIN Break field detect interrupt enable bit 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only n 0x0 0x0 LIN_SCR Serial Control Register LIN 0x1 8 read-write n 0x0 0x0 LBR LIN Break Field setting bit (valid in master mode only) 5 read-write MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data reception enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write n 0x0 0x0 MD Operation mode setting bits 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only LBD LIN Break field detection flag bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received Error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS3 Multi-function Serial Interface 0 MFS0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS3RX 13 MFS3TX 14 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write n 0x0 0x0 DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write ESBL Extended stop bit length select bit 6 read-write LBIE LIN Break field detect interrupt enable bit 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only n 0x0 0x0 LIN_SCR Serial Control Register LIN 0x1 8 read-write n 0x0 0x0 LBR LIN Break Field setting bit (valid in master mode only) 5 read-write MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data reception enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write n 0x0 0x0 MD Operation mode setting bits 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only LBD LIN Break field detection flag bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received Error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS4 Multi-function Serial Interface 4 MFS4 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS4RX 15 MFS4TX 16 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_FBYTE1 FIFO Byte Register 1 CSIO 0x18 8 read-write n 0x0 0x0 CSIO_FBYTE2 FIFO Byte Register 2 CSIO 0x19 8 read-write n 0x0 0x0 CSIO_FCR0 FIFO Control Register 0 CSIO 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write CSIO_FCR1 FIFO Control Register 1 CSIO 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_FBYTE1 FIFO Byte Register 1 I2C 0x18 8 read-write n 0x0 0x0 I2C_FBYTE2 FIFO Byte Register 2 I2C 0x19 8 read-write n 0x0 0x0 I2C_FCR0 FIFO Control Register 0 I2C 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write I2C_FCR1 FIFO Control Register 1 I2C 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write n 0x0 0x0 DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write ESBL Extended stop bit length select bit 6 read-write LBIE LIN Break field detect interrupt enable bit 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 1 read-write LIN_FBYTE1 FIFO Byte Register 1 LIN 0x18 8 read-write n 0x0 0x0 LIN_FBYTE2 FIFO Byte Register 2 LIN 0x19 8 read-write n 0x0 0x0 LIN_FCR0 FIFO Control Register 0 LIN 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write LIN_FCR1 FIFO Control Register 1 LIN 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only n 0x0 0x0 LIN_SCR Serial Control Register LIN 0x1 8 read-write n 0x0 0x0 LBR LIN Break Field setting bit (valid in master mode only) 5 read-write MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data reception enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write n 0x0 0x0 MD Operation mode setting bits 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only LBD LIN Break field detection flag bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received Error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_FBYTE1 FIFO Byte Register 1 UART 0x18 8 read-write n 0x0 0x0 UART_FBYTE2 FIFO Byte Register 2 UART 0x19 8 read-write n 0x0 0x0 UART_FCR0 FIFO Control Register 0 UART 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write UART_FCR1 FIFO Control Register 1 UART 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS5 Multi-function Serial Interface 4 MFS4 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS5RX 17 MFS5TX 18 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_FBYTE1 FIFO Byte Register 1 CSIO 0x18 8 read-write n 0x0 0x0 CSIO_FBYTE2 FIFO Byte Register 2 CSIO 0x19 8 read-write n 0x0 0x0 CSIO_FCR0 FIFO Control Register 0 CSIO 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write CSIO_FCR1 FIFO Control Register 1 CSIO 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_FBYTE1 FIFO Byte Register 1 I2C 0x18 8 read-write n 0x0 0x0 I2C_FBYTE2 FIFO Byte Register 2 I2C 0x19 8 read-write n 0x0 0x0 I2C_FCR0 FIFO Control Register 0 I2C 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write I2C_FCR1 FIFO Control Register 1 I2C 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write n 0x0 0x0 DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write ESBL Extended stop bit length select bit 6 read-write LBIE LIN Break field detect interrupt enable bit 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 1 read-write LIN_FBYTE1 FIFO Byte Register 1 LIN 0x18 8 read-write n 0x0 0x0 LIN_FBYTE2 FIFO Byte Register 2 LIN 0x19 8 read-write n 0x0 0x0 LIN_FCR0 FIFO Control Register 0 LIN 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write LIN_FCR1 FIFO Control Register 1 LIN 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only n 0x0 0x0 LIN_SCR Serial Control Register LIN 0x1 8 read-write n 0x0 0x0 LBR LIN Break Field setting bit (valid in master mode only) 5 read-write MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data reception enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write n 0x0 0x0 MD Operation mode setting bits 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only LBD LIN Break field detection flag bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received Error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_FBYTE1 FIFO Byte Register 1 UART 0x18 8 read-write n 0x0 0x0 UART_FBYTE2 FIFO Byte Register 2 UART 0x19 8 read-write n 0x0 0x0 UART_FCR0 FIFO Control Register 0 UART 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write UART_FCR1 FIFO Control Register 1 UART 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS6 Multi-function Serial Interface 4 MFS4 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS6RX 19 MFS6TX 20 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_FBYTE1 FIFO Byte Register 1 CSIO 0x18 8 read-write n 0x0 0x0 CSIO_FBYTE2 FIFO Byte Register 2 CSIO 0x19 8 read-write n 0x0 0x0 CSIO_FCR0 FIFO Control Register 0 CSIO 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write CSIO_FCR1 FIFO Control Register 1 CSIO 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_FBYTE1 FIFO Byte Register 1 I2C 0x18 8 read-write n 0x0 0x0 I2C_FBYTE2 FIFO Byte Register 2 I2C 0x19 8 read-write n 0x0 0x0 I2C_FCR0 FIFO Control Register 0 I2C 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write I2C_FCR1 FIFO Control Register 1 I2C 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write n 0x0 0x0 DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write ESBL Extended stop bit length select bit 6 read-write LBIE LIN Break field detect interrupt enable bit 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 1 read-write LIN_FBYTE1 FIFO Byte Register 1 LIN 0x18 8 read-write n 0x0 0x0 LIN_FBYTE2 FIFO Byte Register 2 LIN 0x19 8 read-write n 0x0 0x0 LIN_FCR0 FIFO Control Register 0 LIN 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write LIN_FCR1 FIFO Control Register 1 LIN 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only n 0x0 0x0 LIN_SCR Serial Control Register LIN 0x1 8 read-write n 0x0 0x0 LBR LIN Break Field setting bit (valid in master mode only) 5 read-write MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data reception enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write n 0x0 0x0 MD Operation mode setting bits 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only LBD LIN Break field detection flag bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received Error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_FBYTE1 FIFO Byte Register 1 UART 0x18 8 read-write n 0x0 0x0 UART_FBYTE2 FIFO Byte Register 2 UART 0x19 8 read-write n 0x0 0x0 UART_FCR0 FIFO Control Register 0 UART 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write UART_FCR1 FIFO Control Register 1 UART 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS7 Multi-function Serial Interface 4 MFS4 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n MFS7RX 21 MFS7TX 22 CSIO_BGR Baud Rate Generator Registers CSIO 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write CSIO_ESCR Extended Communication Control Register CSIO 0x4 8 read-write n 0x0 0x0 L Data length select bits 0 2 read-write SOP Serial output pin set bit 7 read-write WT Data transmit/received wait select bits 3 1 read-write CSIO_FBYTE1 FIFO Byte Register 1 CSIO 0x18 8 read-write n 0x0 0x0 CSIO_FBYTE2 FIFO Byte Register 2 CSIO 0x19 8 read-write n 0x0 0x0 CSIO_FCR0 FIFO Control Register 0 CSIO 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write CSIO_FCR1 FIFO Control Register 1 CSIO 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write CSIO_RDR Received Data Register CSIO 0x8 16 read-only n 0x0 0x0 CSIO_SCR Serial Control Register CSIO 0x1 8 read-write n 0x0 0x0 MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data received enable bit 1 read-write SPI SPI corresponding bit 5 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write CSIO_SMR Serial Mode Register CSIO 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bits 5 2 read-write SCINV Serial clock invert bit 3 read-write SCKE Master mode serial clock output enable bit 1 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write CSIO_SSR Serial Status Register CSIO 0x5 8 read-write n 0x0 0x0 ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only CSIO_TDR Transmit Data Register CSIO 0x8 16 write-only n 0x0 0x0 I2C_BGR Baud Rate Generator Registers I2C 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write I2C_FBYTE1 FIFO Byte Register 1 I2C 0x18 8 read-write n 0x0 0x0 I2C_FBYTE2 FIFO Byte Register 2 I2C 0x19 8 read-write n 0x0 0x0 I2C_FCR0 FIFO Control Register 0 I2C 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write I2C_FCR1 FIFO Control Register 1 I2C 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write I2C_IBCR I2C Bus Control Register I2C 0x1 8 read-write n 0x0 0x0 ACKE Data byte acknowledge enable bit 5 read-write ACT_SCC Operation flag/iteration start condition generation bit 6 read-write BER Bus error flag bit 1 read-only CNDE Condition detection interrupt enable bit 3 read-write INT interrupt flag bit 0 read-write INTE Interrupt enable bit 2 read-write MSS Master/slave select bit 7 read-write WSEL Wait selection bit 4 read-write I2C_IBSR I2C Bus Status Register I2C 0x4 8 read-write n 0x0 0x0 AL Arbitration lost bit 3 read-only BB Bus state bit 0 read-only FBT First byte bit 7 read-only RACK Acknowledge flag bit 6 read-only RSA Reserved address detection bit 5 read-only RSC Iteration start condition check bit 2 read-write SPC Stop condition check bit 1 read-write TRX Data direction bit 4 read-only I2C_ISBA 7-bit Slave Address Register I2C 0x10 8 read-write n 0x0 0x0 SA 7-bit slave address 0 6 read-write SAEN Slave address enable bit 7 read-write I2C_ISMK 7-bit Slave Address Mask Register I2C 0x11 8 read-write n 0x0 0x0 EN I2C interface operation enable bit 7 read-write SM Slave address mask bits 0 6 read-write I2C_RDR Received Data Register I2C 0x8 16 read-only n 0x0 0x0 I2C_SMR Serial Mode Register I2C 0x0 8 read-write n 0x0 0x0 MD operation mode set bits 5 2 read-write RIE Received interrupt enable bit 3 read-write TIE Transmit interrupt enable bit 2 read-write WUCR Wake-up control bit 4 read-write I2C_SSR Serial Status Register I2C 0x5 8 read-write n 0x0 0x0 DMA DMA mode enable bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag bit (Effective only when DMA mode is enabled) 0 read-only TBIE Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) 4 read-write TDRE Transmit data empty flag bit 1 read-only TSET Transmit empty flag set bit 6 read-write I2C_TDR Transmit Data Register I2C 0x8 16 write-only n 0x0 0x0 LIN_BGR Baud Rate Generator Registers LIN 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write LIN_ESCR Extended Communication Control Register LIN 0x4 8 read-write n 0x0 0x0 DEL LIN Break delimiter length select bits (valid in master mode only) 0 1 read-write ESBL Extended stop bit length select bit 6 read-write LBIE LIN Break field detect interrupt enable bit 4 read-write LBL LIN Break field length select bits (valid in master mode only) 2 1 read-write LIN_FBYTE1 FIFO Byte Register 1 LIN 0x18 8 read-write n 0x0 0x0 LIN_FBYTE2 FIFO Byte Register 2 LIN 0x19 8 read-write n 0x0 0x0 LIN_FCR0 FIFO Control Register 0 LIN 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write LIN_FCR1 FIFO Control Register 1 LIN 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write LIN_RDR Received Data Register LIN 0x8 16 read-only n 0x0 0x0 LIN_SCR Serial Control Register LIN 0x1 8 read-write n 0x0 0x0 LBR LIN Break Field setting bit (valid in master mode only) 5 read-write MS Master/Slave function select bit 6 read-write RIE Received interrupt enable bit 4 read-write RXE Data reception enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Data transmission enable bit 0 read-write UPCL Programmable clear bit 7 read-write LIN_SMR Serial Mode Register LIN 0x0 8 read-write n 0x0 0x0 MD Operation mode setting bits 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write LIN_SSR Serial Status Register LIN 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only LBD LIN Break field detection flag bit 5 read-write ORE Overrun error flag bit 3 read-only RDRF Received data full flag bit 2 read-only REC Received Error flag clear bit 7 read-write TBI Transmit bus idle flag bit 0 read-only TDRE Transmit data empty flag bit 1 read-only LIN_TDR Transmit Data Register LIN 0x8 16 write-only n 0x0 0x0 UART_BGR Baud Rate Generator Registers UART 0xC 16 read-write n 0x0 0x0 BGR0 Baud Rate Generator Registers 0 0 7 read-write BGR1 Baud Rate Generator Registers 1 8 6 read-write EXT External clock select bit 15 read-write UART_ESCR Extended Communication Control Register UART 0x4 8 read-write n 0x0 0x0 ESBL Extension stop bit length select bit 6 read-write FLWEN Flow control enable bit 7 read-write INV Inverted serial data format bit 5 read-write L Data length select bit 0 2 read-write P Parity select bit (only functions in operation mode 0) 3 read-write PEN Parity enable bit (only functions in operation mode 0) 4 read-write UART_FBYTE1 FIFO Byte Register 1 UART 0x18 8 read-write n 0x0 0x0 UART_FBYTE2 FIFO Byte Register 2 UART 0x19 8 read-write n 0x0 0x0 UART_FCR0 FIFO Control Register 0 UART 0x14 8 read-write n 0x0 0x0 FCL1 FIFO1 reset bit 2 read-write FCL2 FIFO2 reset bit 3 read-write FE1 FIFO1 operation enable bit 0 read-write FE2 FIFO2 operation enable bit 1 read-write FLD FIFO pointer reload bit 5 read-write FLST FIFO re-transmit data lost flag bit 6 read-only FSET FIFO pointer save bit 4 read-write UART_FCR1 FIFO Control Register 1 UART 0x15 8 read-write n 0x0 0x0 FDRQ Transmit FIFO data request bit 2 read-write FLSTE Re-transmission data lost detect enable bit 4 read-write FRIIE Received FIFO idle detection enable bit 3 read-write FSEL FIFO select bit 0 read-write FTIE Transmit FIFO interrupt enable bit 1 read-write UART_RDR Received Data Register UART 0x8 16 read-only n 0x0 0x0 UART_SCR Serial Control Register UART 0x1 8 read-write n 0x0 0x0 RIE Received interrupt enable bit 4 read-write RXE Received operation enable bit 1 read-write TBIE Transmit bus idle interrupt enable bit 2 read-write TIE Transmit interrupt enable bit 3 read-write TXE Transmission operation enable bit 0 read-write UPCL Programmable Clear bit 7 read-write UART_SMR Serial Mode Register UART 0x0 8 read-write n 0x0 0x0 BDS Transfer direction select bit 2 read-write MD Operation mode set bit 5 2 read-write SBL Stop bit length select bit 3 read-write SOE Serial data output enable bit 0 read-write WUCR Wake-up control bit 4 read-write UART_SSR Serial Status Register UART 0x5 8 read-write n 0x0 0x0 FRE Framing error flag bit 4 read-only ORE Overrun error flag bit 3 read-only PE Parity error flag bit (only functions in operation mode 0) 5 read-only RDRF Received data full flag bit 2 read-only REC Received error flag clear bit 7 read-write TBI Transmit bus idle flag 0 read-only TDRE Transmit data empty flag bit 1 read-only UART_TDR Transmit Data Register UART 0x8 16 write-only n 0x0 0x0 MFS_NFC I2C Auxiliary Noise Filter Setting Register MFS_NFC 0x0 0x0 0x2 registers n I2CDNF I2C Auxiliary Noise Filter Setting Register 0x0 16 read-write n 0x0 0x0 I2CDNF0 Auxiliary noise filter additional step select bits for I2C ch.0 0 1 read-write I2CDNF1 Auxiliary noise filter additional step select bits for I2C ch.1 2 1 read-write I2CDNF2 Auxiliary noise filter additional step select bits for I2C ch.2 4 1 read-write I2CDNF3 Auxiliary noise filter additional step select bits for I2C ch.3 6 1 read-write I2CDNF4 Auxiliary noise filter additional step select bits for I2C ch.4 8 1 read-write I2CDNF5 Auxiliary noise filter additional step select bits for I2C ch.5 10 1 read-write I2CDNF6 Auxiliary noise filter additional step select bits for I2C ch.6 12 1 read-write I2CDNF7 Auxiliary noise filter additional step select bits for I2C ch.7 14 1 read-write MFT0 Multifunction Timer 0 MFT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x2 registers n 0x20 0x2 registers n 0x24 0x2 registers n 0x28 0x2 registers n 0x2C 0x2 registers n 0x30 0x2 registers n 0x34 0x2 registers n 0x38 0x2 registers n 0x3C 0x2 registers n 0x4 0x2 registers n 0x40 0x2 registers n 0x44 0x2 registers n 0x48 0x2 registers n 0x4C 0x2 registers n 0x50 0x2 registers n 0x54 0x2 registers n 0x58 0x2 registers n 0x5C 0x1 registers n 0x60 0x2 registers n 0x68 0x2 registers n 0x6C 0x2 registers n 0x70 0x2 registers n 0x74 0x2 registers n 0x78 0x2 registers n 0x7C 0x2 registers n 0x8 0x2 registers n 0x80 0x2 registers n 0x84 0x2 registers n 0x88 0x2 registers n 0x8C 0x2 registers n 0x90 0x2 registers n 0x94 0x2 registers n 0x98 0x2 registers n 0x9C 0x2 registers n 0xA0 0x2 registers n 0xA4 0x2 registers n 0xA8 0x2 registers n 0xAC 0x2 registers n 0xB0 0x2 registers n 0xB4 0x2 registers n 0xB8 0x1 registers n 0xBC 0x2 registers n 0xC 0x2 registers n 0xC0 0x2 registers n WFG 3 FRTIM 28 INCAP 29 OUTCOMP 30 ADCMP_ACCP0 ADCMP ch.0 Compare Value Store Register 0xA0 16 read-write n 0x0 0x0 ADCMP_ACCP1 ADCMP ch.1 Compare Value Store Register 0xA8 read-write n 0x0 0x0 ADCMP_ACCP2 ADCMP ch.2 Compare Value Store Register 0xB0 read-write n 0x0 0x0 ADCMP_ACCPDN0 ADCMP ch.0 Compare Value Store Register 0xA4 16 read-write n 0x0 0x0 ADCMP_ACCPDN1 ADCMP ch.1 Compare Value Store Register 0xAC read-write n 0x0 0x0 ADCMP_ACCPDN2 ADCMP ch.2 Compare Value Store Register 0xB4 read-write n 0x0 0x0 ADCMP_ACSA ADCMP Control Register A 0xBC 16 read-write n 0x0 0x0 CE0 enable or disable the operation of ADCMP-ch.0 and select the FRT to be connected 0 1 read-write CE1 enable or disable the operation of ADCMP-ch.1 and select the FRT to be connected 2 1 read-write CE2 enable or disable the operation of ADCMP-ch.2 and select the FRT to be connected 4 1 read-write SEL0 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.0 8 1 read-write SEL1 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.1 10 1 read-write SEL2 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.2 12 1 read-write ADCMP_ACSB ADCMP Control Register B 0xB8 8 read-write n 0x0 0x0 BDIS0 Disables the buffer function of the ACCP0 and ACCPDN0 registers 0 read-write BDIS1 Disables the buffer function of the ACCP1 and ACCPDN1 registers 1 read-write BDIS2 Disables the buffer function of the ACCP2 and ACCPDN2 registers 2 read-write BTS0 Performs buffer transfer of the ACCP0 and ACCPDN0 registers upon Peak value detection by FRT 4 read-write BTS1 Performs buffer transfer of the ACCP1 and ACCPDN1 registers upon Peak value detection by FRT 5 read-write BTS2 Performs buffer transfer of the ACCP2 and ACCPDN2 registers upon Peak value detection by FRT 6 read-write ADCMP_ATSA ADC Start Trigger Select Register 0xC0 16 read-write n 0x0 0x0 AD0P selects the start signal to be used to start priority conversion of ADC unit0 8 1 read-write AD0S selects the start signal to be used to start the scan conversion of ADC unit0 0 1 read-write AD1P selects the start signal to be used to start priority conversion of ADC unit1 10 1 read-write AD1S selects the start signal to be used to start the scan conversion of ADC unit1 2 1 read-write AD2P selects the start signal to be used to start priority conversion of ADC unit2 12 1 read-write AD2S selects the start signal to be used to start the scan conversion of ADC unit2 4 1 read-write FRT_TCCP0 FRT-ch.0 Cycle Setting Register 0x28 16 read-write n 0x0 0x0 FRT_TCCP1 FRT-ch.1 Cycle Setting Register 0x38 read-write n 0x0 0x0 FRT_TCCP2 FRT-ch.2 Cycle Setting Register 0x48 read-write n 0x0 0x0 FRT_TCDT0 FRT-ch.0 Count Value Register 0x2C 16 read-write n 0x0 0x0 FRT_TCDT1 FRT-ch.1 Count Value Register 0x3C read-write n 0x0 0x0 FRT_TCDT2 FRT-ch.2 Count Value Register 0x4C read-write n 0x0 0x0 FRT_TCSA0 FRT-ch.0 Control Register A 0x30 16 read-write n 0x0 0x0 BFE Enables TCCP's buffer function 7 read-write CLK FRT clock cycle 0 3 read-write ECKE Uses an external input clock (FRCK) as FRT's count clock 15 read-write ICLR interrupt flag 9 read-write ICRE Generates interrupt when 1 is set to TCSA.ICLR 8 read-write IRQZE Generates interrupt, when 1 is set to TCSA.IRQZF 13 read-write IRQZF zero interrupt flag 14 read-write MODE FRT's count mode 5 read-write SCLR FRT operation state initialization request 4 write-only STOP Puts FRT in stopping state 6 read-write FRT_TCSA1 FRT-ch.1 Control Register A 0x40 read-write n 0x0 0x0 FRT_TCSA2 FRT-ch.2 Control Register A 0x50 read-write n 0x0 0x0 FRT_TCSB0 FRT-ch.0 Control Register B 0x34 16 read-write n 0x0 0x0 AD0E Outputs AD conversion start signal to ADCunit0 upon Zero value detection by FRT 0 read-write AD1E Outputs AD conversion start signal to ADCunit1 upon Zero value detection by FRT 1 read-write AD2E Outputs AD conversion start signal to ADCunit2 upon Zero value detection by FRT 2 read-write FRT_TCSB1 FRT-ch.1 Control Register B 0x44 read-write n 0x0 0x0 FRT_TCSB2 FRT-ch.2 Control Register B 0x54 read-write n 0x0 0x0 ICU_ICCP0 ICU ch.0 Capture value store register 0x68 16 read-only n 0x0 0x0 ICU_ICCP1 ICU ch.1 Capture value store register 0x6C read-write n 0x0 0x0 ICU_ICCP2 ICU ch.2 Capture value store register 0x70 read-write n 0x0 0x0 ICU_ICCP3 ICU ch.3 Capture value store register 0x74 read-write n 0x0 0x0 ICU_ICFS10 ICU ch.1,0 Connecting FRT Select Register 0x60 8 read-write n 0x0 0x0 FSI0 Connects FRT ch.x to ICU ch.(0) 0 3 read-write FSI1 Connects FRT ch.x to ICU ch.(1) 4 3 read-write ICU_ICFS32 ICU ch.3,2 Connecting FRT Select Register 0x61 -1 read-write n 0x0 0x0 ICU_ICSA10 ICU ch.1,0 Control Register A 0x78 8 read-write n 0x0 0x0 EG0 enables/disables the operation of ICU-ch.(0) and selects a valid edge(s) 0 1 read-write EG1 enables/disables the operation of ICU-ch.(1) and selects a valid edge(s) 2 1 read-write ICE0 Generates interrupt, when 1 is set to ICSA.ICP0. 4 read-write ICE1 Generates interrupt, when 1 is set to ICSA.ICP1. 5 read-write ICP0 Indicates that a valid edge has been detected at ICU ch.(0) and the capture operation has been performed 6 read-write ICP1 Indicates that a valid edge has been detected at ICU ch.(1) and the capture operation has been performed 7 read-write ICU_ICSA32 ICU ch.3,2 Control Register A 0x7C -1 read-write n 0x0 0x0 ICU_ICSB10 ICU ch.1,0 Control Register B 0x79 8 read-only n 0x0 0x0 IEI0 indicates the latest valid edge of ICU-ch.(0) 0 read-only IEI1 indicates the latest valid edge of ICU-ch.(1) 1 read-only ICU_ICSB32 ICU ch.3,2 Control Register B 0x7D -1 read-write n 0x0 0x0 OCU_OCCP0 OCU ch.0 Compare Value Store Register 0x0 16 read-write n 0x0 0x0 OCU_OCCP1 OCU ch.1 Compare Value Store Register 0x4 read-write n 0x0 0x0 OCU_OCCP2 OCU ch.2 Compare Value Store Register 0x8 read-write n 0x0 0x0 OCU_OCCP3 OCU ch.3 Compare Value Store Register 0xC read-write n 0x0 0x0 OCU_OCCP4 OCU ch.4 Compare Value Store Register 0x10 read-write n 0x0 0x0 OCU_OCCP5 OCU ch.5 Compare Value Store Register 0x14 read-write n 0x0 0x0 OCU_OCFS10 OCU ch.1,0 Connecting FRT Select Register 0x58 8 read-write n 0x0 0x0 FSO0 Connects FRT ch.x to OCU ch.0 0 3 read-write FSO1 Connects FRT ch.x to OCU ch.1 4 3 read-write OCU_OCFS32 OCU ch.3,2 Connecting FRT Select Register 0x59 -1 read-write n 0x0 0x0 OCU_OCFS54 OCU ch.5,4 Connecting FRT Select Register 0x5C -1 read-write n 0x0 0x0 OCU_OCSA10 OCU ch.1,0 Control Register A 0x18 8 read-write n 0x0 0x0 BDIS0 Disables the buffer function of the OCCP(0) register 2 read-write BDIS1 Disables the buffer function of the OCCP(1) register 3 read-write CST0 Enables the operation of OCU ch.(0) 0 read-write CST1 Enables the operation of OCU ch.(1) 1 read-write IOE0 Generates interrupt, when 1 is set to OCSA.IOP0 4 read-write IOE1 Generates interrupt, when 1 is set to OCSA.IOP1 5 read-write IOP0 Indicates that a match has already been detected between FRT's count value and OCCP(0) value at OCU ch.(0). 6 read-write IOP1 Indicates that a match has already been detected between FRT's count value and OCCP(1) value at OCU ch.(1). 7 read-write OCU_OCSA32 OCU ch.3,2 Control Register A 0x1C -1 read-write n 0x0 0x0 OCU_OCSA54 OCU ch.5,4 Control Register A 0x20 -1 read-write n 0x0 0x0 OCU_OCSB10 OCU ch.1,0 Control Register B 0x19 8 read-write n 0x0 0x0 BTS0 Performs buffer transfer of the OCCP(0) register upon Peak value detection by FRT 5 read-write BTS1 Performs buffer transfer of the OCCP(1) register upon Peak value detection by FRT 6 read-write CMOD selects OCU's operation mode in combination with OCSC.MOD0 to MOD5 4 read-write OTD0 Indicates that the RT(0) output pin is in the High-level output state. 0 read-write OTD1 Indicates that the RT(1) output pin is in the High-level output state. 1 read-write OCU_OCSB32 OCU ch.3,2 Control Register B 0x1D -1 read-write n 0x0 0x0 OCU_OCSB54 OCU ch.5,4 Control Register B 0x21 -1 read-write n 0x0 0x0 OCU_OCSC OCU Control Register C 0x24 16 read-write n 0x0 0x0 MOD0 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 8 read-write MOD1 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 9 read-write MOD2 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 10 read-write MOD3 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 11 read-write MOD4 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 12 read-write MOD5 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 13 read-write WFG_NZCL NZCL Control Register 0x9C 16 read-write n 0x0 0x0 DTIE DTIF interrupt enable 0 read-write NWS noise-canceling width of the noise-canceller for the DTTIX pin 1 2 read-write SDTI Forcibly generates DTIF interrupt 4 write-only WFG_WFIR WFG Interrupt Control Register 0x98 16 read-write n 0x0 0x0 DTIC Clears WFIR.DTIF and deasserts the DTIF interrupt signal. 1 write-only DTIF Indicates that DTIF interrupt has been generated. 0 read-only TMIC10 Clears WFIR.TMIF10 and deasserts the WFG10 timer interrupt signal. 5 write-only TMIC32 Clears WFIR.TMIF32 and deasserts the WFG32 timer interrupt signal. 9 write-only TMIC54 Clears WFIR.TMIF54 and deasserts the WFG54 timer interrupt signal. 13 write-only TMIE10 Starts the WFG10 timer 6 read-write TMIE32 Starts the WFG32 timer 10 read-write TMIE54 Starts the WFG54 timer 14 read-write TMIF10 Indicates that WFG10 timer interrupt has been generated. 4 read-only TMIF32 Indicates that WFG32 timer interrupt has been generated. 8 read-only TMIF54 Indicates that WFG54 timer interrupt has been generated. 12 read-only TMIS10 Stops the WFG10 timer 7 write-only TMIS32 Stops the WFG32 timer 11 write-only TMIS54 Stops the WFG54 timer 15 write-only WFG_WFSA10 WFG ch.10 Control Register A 0x8C 16 read-write n 0x0 0x0 DCK clock cycle of the WFG timer 0 2 read-write DMOD specifies which polarity will be used to output the non-overlap signal 12 read-write GTEN the CH_GATE signal for each channel of WFG 6 1 read-write PGEN specifies how to reflect the CH_PPG signal that is input to each channel of WFG on WFG output 10 1 read-write PSEL the PPG timer unit to be used at each channel of WFG 8 1 read-write TMD WFG's operation mode 3 2 read-write WFG_WFSA32 WFG ch.32 Control Register A 0x90 read-write n 0x0 0x0 WFG_WFSA54 WFG ch.54 Control Register A 0x94 read-write n 0x0 0x0 WFG_WFTM10 WFG ch.10 Timer Value Register 0x80 16 read-write n 0x0 0x0 WFG_WFTM32 WFG ch.32 Timer Value Register 0x84 read-write n 0x0 0x0 WFG_WFTM54 WFG ch.54 Timer Value Register 0x88 read-write n 0x0 0x0 MFT1 Multifunction Timer 0 MFT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x2 registers n 0x20 0x2 registers n 0x24 0x2 registers n 0x28 0x2 registers n 0x2C 0x2 registers n 0x30 0x2 registers n 0x34 0x2 registers n 0x38 0x2 registers n 0x3C 0x2 registers n 0x4 0x2 registers n 0x40 0x2 registers n 0x44 0x2 registers n 0x48 0x2 registers n 0x4C 0x2 registers n 0x50 0x2 registers n 0x54 0x2 registers n 0x58 0x2 registers n 0x5C 0x1 registers n 0x60 0x2 registers n 0x68 0x2 registers n 0x6C 0x2 registers n 0x70 0x2 registers n 0x74 0x2 registers n 0x78 0x2 registers n 0x7C 0x2 registers n 0x8 0x2 registers n 0x80 0x2 registers n 0x84 0x2 registers n 0x88 0x2 registers n 0x8C 0x2 registers n 0x90 0x2 registers n 0x94 0x2 registers n 0x98 0x2 registers n 0x9C 0x2 registers n 0xA0 0x2 registers n 0xA4 0x2 registers n 0xA8 0x2 registers n 0xAC 0x2 registers n 0xB0 0x2 registers n 0xB4 0x2 registers n 0xB8 0x1 registers n 0xBC 0x2 registers n 0xC 0x2 registers n 0xC0 0x2 registers n ADCMP_ACCP0 ADCMP ch.0 Compare Value Store Register 0xA0 16 read-write n 0x0 0x0 ADCMP_ACCP1 ADCMP ch.1 Compare Value Store Register 0xA8 read-write n 0x0 0x0 ADCMP_ACCP2 ADCMP ch.2 Compare Value Store Register 0xB0 read-write n 0x0 0x0 ADCMP_ACCPDN0 ADCMP ch.0 Compare Value Store Register 0xA4 16 read-write n 0x0 0x0 ADCMP_ACCPDN1 ADCMP ch.1 Compare Value Store Register 0xAC read-write n 0x0 0x0 ADCMP_ACCPDN2 ADCMP ch.2 Compare Value Store Register 0xB4 read-write n 0x0 0x0 ADCMP_ACSA ADCMP Control Register A 0xBC 16 read-write n 0x0 0x0 CE0 enable or disable the operation of ADCMP-ch.0 and select the FRT to be connected 0 1 read-write CE1 enable or disable the operation of ADCMP-ch.1 and select the FRT to be connected 2 1 read-write CE2 enable or disable the operation of ADCMP-ch.2 and select the FRT to be connected 4 1 read-write SEL0 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.0 8 1 read-write SEL1 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.1 10 1 read-write SEL2 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.2 12 1 read-write ADCMP_ACSB ADCMP Control Register B 0xB8 8 read-write n 0x0 0x0 BDIS0 Disables the buffer function of the ACCP0 and ACCPDN0 registers 0 read-write BDIS1 Disables the buffer function of the ACCP1 and ACCPDN1 registers 1 read-write BDIS2 Disables the buffer function of the ACCP2 and ACCPDN2 registers 2 read-write BTS0 Performs buffer transfer of the ACCP0 and ACCPDN0 registers upon Peak value detection by FRT 4 read-write BTS1 Performs buffer transfer of the ACCP1 and ACCPDN1 registers upon Peak value detection by FRT 5 read-write BTS2 Performs buffer transfer of the ACCP2 and ACCPDN2 registers upon Peak value detection by FRT 6 read-write ADCMP_ATSA ADC Start Trigger Select Register 0xC0 16 read-write n 0x0 0x0 AD0P selects the start signal to be used to start priority conversion of ADC unit0 8 1 read-write AD0S selects the start signal to be used to start the scan conversion of ADC unit0 0 1 read-write AD1P selects the start signal to be used to start priority conversion of ADC unit1 10 1 read-write AD1S selects the start signal to be used to start the scan conversion of ADC unit1 2 1 read-write AD2P selects the start signal to be used to start priority conversion of ADC unit2 12 1 read-write AD2S selects the start signal to be used to start the scan conversion of ADC unit2 4 1 read-write FRT_TCCP0 FRT-ch.0 Cycle Setting Register 0x28 16 read-write n 0x0 0x0 FRT_TCCP1 FRT-ch.1 Cycle Setting Register 0x38 read-write n 0x0 0x0 FRT_TCCP2 FRT-ch.2 Cycle Setting Register 0x48 read-write n 0x0 0x0 FRT_TCDT0 FRT-ch.0 Count Value Register 0x2C 16 read-write n 0x0 0x0 FRT_TCDT1 FRT-ch.1 Count Value Register 0x3C read-write n 0x0 0x0 FRT_TCDT2 FRT-ch.2 Count Value Register 0x4C read-write n 0x0 0x0 FRT_TCSA0 FRT-ch.0 Control Register A 0x30 16 read-write n 0x0 0x0 BFE Enables TCCP's buffer function 7 read-write CLK FRT clock cycle 0 3 read-write ECKE Uses an external input clock (FRCK) as FRT's count clock 15 read-write ICLR interrupt flag 9 read-write ICRE Generates interrupt when 1 is set to TCSA.ICLR 8 read-write IRQZE Generates interrupt, when 1 is set to TCSA.IRQZF 13 read-write IRQZF zero interrupt flag 14 read-write MODE FRT's count mode 5 read-write SCLR FRT operation state initialization request 4 write-only STOP Puts FRT in stopping state 6 read-write FRT_TCSA1 FRT-ch.1 Control Register A 0x40 read-write n 0x0 0x0 FRT_TCSA2 FRT-ch.2 Control Register A 0x50 read-write n 0x0 0x0 FRT_TCSB0 FRT-ch.0 Control Register B 0x34 16 read-write n 0x0 0x0 AD0E Outputs AD conversion start signal to ADCunit0 upon Zero value detection by FRT 0 read-write AD1E Outputs AD conversion start signal to ADCunit1 upon Zero value detection by FRT 1 read-write AD2E Outputs AD conversion start signal to ADCunit2 upon Zero value detection by FRT 2 read-write FRT_TCSB1 FRT-ch.1 Control Register B 0x44 read-write n 0x0 0x0 FRT_TCSB2 FRT-ch.2 Control Register B 0x54 read-write n 0x0 0x0 ICU_ICCP0 ICU ch.0 Capture value store register 0x68 16 read-only n 0x0 0x0 ICU_ICCP1 ICU ch.1 Capture value store register 0x6C read-write n 0x0 0x0 ICU_ICCP2 ICU ch.2 Capture value store register 0x70 read-write n 0x0 0x0 ICU_ICCP3 ICU ch.3 Capture value store register 0x74 read-write n 0x0 0x0 ICU_ICFS10 ICU ch.1,0 Connecting FRT Select Register 0x60 8 read-write n 0x0 0x0 FSI0 Connects FRT ch.x to ICU ch.(0) 0 3 read-write FSI1 Connects FRT ch.x to ICU ch.(1) 4 3 read-write ICU_ICFS32 ICU ch.3,2 Connecting FRT Select Register 0x61 -1 read-write n 0x0 0x0 ICU_ICSA10 ICU ch.1,0 Control Register A 0x78 8 read-write n 0x0 0x0 EG0 enables/disables the operation of ICU-ch.(0) and selects a valid edge(s) 0 1 read-write EG1 enables/disables the operation of ICU-ch.(1) and selects a valid edge(s) 2 1 read-write ICE0 Generates interrupt, when 1 is set to ICSA.ICP0. 4 read-write ICE1 Generates interrupt, when 1 is set to ICSA.ICP1. 5 read-write ICP0 Indicates that a valid edge has been detected at ICU ch.(0) and the capture operation has been performed 6 read-write ICP1 Indicates that a valid edge has been detected at ICU ch.(1) and the capture operation has been performed 7 read-write ICU_ICSA32 ICU ch.3,2 Control Register A 0x7C -1 read-write n 0x0 0x0 ICU_ICSB10 ICU ch.1,0 Control Register B 0x79 8 read-only n 0x0 0x0 IEI0 indicates the latest valid edge of ICU-ch.(0) 0 read-only IEI1 indicates the latest valid edge of ICU-ch.(1) 1 read-only ICU_ICSB32 ICU ch.3,2 Control Register B 0x7D -1 read-write n 0x0 0x0 OCU_OCCP0 OCU ch.0 Compare Value Store Register 0x0 16 read-write n 0x0 0x0 OCU_OCCP1 OCU ch.1 Compare Value Store Register 0x4 read-write n 0x0 0x0 OCU_OCCP2 OCU ch.2 Compare Value Store Register 0x8 read-write n 0x0 0x0 OCU_OCCP3 OCU ch.3 Compare Value Store Register 0xC read-write n 0x0 0x0 OCU_OCCP4 OCU ch.4 Compare Value Store Register 0x10 read-write n 0x0 0x0 OCU_OCCP5 OCU ch.5 Compare Value Store Register 0x14 read-write n 0x0 0x0 OCU_OCFS10 OCU ch.1,0 Connecting FRT Select Register 0x58 8 read-write n 0x0 0x0 FSO0 Connects FRT ch.x to OCU ch.0 0 3 read-write FSO1 Connects FRT ch.x to OCU ch.1 4 3 read-write OCU_OCFS32 OCU ch.3,2 Connecting FRT Select Register 0x59 -1 read-write n 0x0 0x0 OCU_OCFS54 OCU ch.5,4 Connecting FRT Select Register 0x5C -1 read-write n 0x0 0x0 OCU_OCSA10 OCU ch.1,0 Control Register A 0x18 8 read-write n 0x0 0x0 BDIS0 Disables the buffer function of the OCCP(0) register 2 read-write BDIS1 Disables the buffer function of the OCCP(1) register 3 read-write CST0 Enables the operation of OCU ch.(0) 0 read-write CST1 Enables the operation of OCU ch.(1) 1 read-write IOE0 Generates interrupt, when 1 is set to OCSA.IOP0 4 read-write IOE1 Generates interrupt, when 1 is set to OCSA.IOP1 5 read-write IOP0 Indicates that a match has already been detected between FRT's count value and OCCP(0) value at OCU ch.(0). 6 read-write IOP1 Indicates that a match has already been detected between FRT's count value and OCCP(1) value at OCU ch.(1). 7 read-write OCU_OCSA32 OCU ch.3,2 Control Register A 0x1C -1 read-write n 0x0 0x0 OCU_OCSA54 OCU ch.5,4 Control Register A 0x20 -1 read-write n 0x0 0x0 OCU_OCSB10 OCU ch.1,0 Control Register B 0x19 8 read-write n 0x0 0x0 BTS0 Performs buffer transfer of the OCCP(0) register upon Peak value detection by FRT 5 read-write BTS1 Performs buffer transfer of the OCCP(1) register upon Peak value detection by FRT 6 read-write CMOD selects OCU's operation mode in combination with OCSC.MOD0 to MOD5 4 read-write OTD0 Indicates that the RT(0) output pin is in the High-level output state. 0 read-write OTD1 Indicates that the RT(1) output pin is in the High-level output state. 1 read-write OCU_OCSB32 OCU ch.3,2 Control Register B 0x1D -1 read-write n 0x0 0x0 OCU_OCSB54 OCU ch.5,4 Control Register B 0x21 -1 read-write n 0x0 0x0 OCU_OCSC OCU Control Register C 0x24 16 read-write n 0x0 0x0 MOD0 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 8 read-write MOD1 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 9 read-write MOD2 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 10 read-write MOD3 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 11 read-write MOD4 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 12 read-write MOD5 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 13 read-write WFG_NZCL NZCL Control Register 0x9C 16 read-write n 0x0 0x0 DTIE DTIF interrupt enable 0 read-write NWS noise-canceling width of the noise-canceller for the DTTIX pin 1 2 read-write SDTI Forcibly generates DTIF interrupt 4 write-only WFG_WFIR WFG Interrupt Control Register 0x98 16 read-write n 0x0 0x0 DTIC Clears WFIR.DTIF and deasserts the DTIF interrupt signal. 1 write-only DTIF Indicates that DTIF interrupt has been generated. 0 read-only TMIC10 Clears WFIR.TMIF10 and deasserts the WFG10 timer interrupt signal. 5 write-only TMIC32 Clears WFIR.TMIF32 and deasserts the WFG32 timer interrupt signal. 9 write-only TMIC54 Clears WFIR.TMIF54 and deasserts the WFG54 timer interrupt signal. 13 write-only TMIE10 Starts the WFG10 timer 6 read-write TMIE32 Starts the WFG32 timer 10 read-write TMIE54 Starts the WFG54 timer 14 read-write TMIF10 Indicates that WFG10 timer interrupt has been generated. 4 read-only TMIF32 Indicates that WFG32 timer interrupt has been generated. 8 read-only TMIF54 Indicates that WFG54 timer interrupt has been generated. 12 read-only TMIS10 Stops the WFG10 timer 7 write-only TMIS32 Stops the WFG32 timer 11 write-only TMIS54 Stops the WFG54 timer 15 write-only WFG_WFSA10 WFG ch.10 Control Register A 0x8C 16 read-write n 0x0 0x0 DCK clock cycle of the WFG timer 0 2 read-write DMOD specifies which polarity will be used to output the non-overlap signal 12 read-write GTEN the CH_GATE signal for each channel of WFG 6 1 read-write PGEN specifies how to reflect the CH_PPG signal that is input to each channel of WFG on WFG output 10 1 read-write PSEL the PPG timer unit to be used at each channel of WFG 8 1 read-write TMD WFG's operation mode 3 2 read-write WFG_WFSA32 WFG ch.32 Control Register A 0x90 read-write n 0x0 0x0 WFG_WFSA54 WFG ch.54 Control Register A 0x94 read-write n 0x0 0x0 WFG_WFTM10 WFG ch.10 Timer Value Register 0x80 16 read-write n 0x0 0x0 WFG_WFTM32 WFG ch.32 Timer Value Register 0x84 read-write n 0x0 0x0 WFG_WFTM54 WFG ch.54 Timer Value Register 0x88 read-write n 0x0 0x0 MFT2 Multifunction Timer 0 MFT0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x2 registers n 0x20 0x2 registers n 0x24 0x2 registers n 0x28 0x2 registers n 0x2C 0x2 registers n 0x30 0x2 registers n 0x34 0x2 registers n 0x38 0x2 registers n 0x3C 0x2 registers n 0x4 0x2 registers n 0x40 0x2 registers n 0x44 0x2 registers n 0x48 0x2 registers n 0x4C 0x2 registers n 0x50 0x2 registers n 0x54 0x2 registers n 0x58 0x2 registers n 0x5C 0x1 registers n 0x60 0x2 registers n 0x68 0x2 registers n 0x6C 0x2 registers n 0x70 0x2 registers n 0x74 0x2 registers n 0x78 0x2 registers n 0x7C 0x2 registers n 0x8 0x2 registers n 0x80 0x2 registers n 0x84 0x2 registers n 0x88 0x2 registers n 0x8C 0x2 registers n 0x90 0x2 registers n 0x94 0x2 registers n 0x98 0x2 registers n 0x9C 0x2 registers n 0xA0 0x2 registers n 0xA4 0x2 registers n 0xA8 0x2 registers n 0xAC 0x2 registers n 0xB0 0x2 registers n 0xB4 0x2 registers n 0xB8 0x1 registers n 0xBC 0x2 registers n 0xC 0x2 registers n 0xC0 0x2 registers n ADCMP_ACCP0 ADCMP ch.0 Compare Value Store Register 0xA0 16 read-write n 0x0 0x0 ADCMP_ACCP1 ADCMP ch.1 Compare Value Store Register 0xA8 read-write n 0x0 0x0 ADCMP_ACCP2 ADCMP ch.2 Compare Value Store Register 0xB0 read-write n 0x0 0x0 ADCMP_ACCPDN0 ADCMP ch.0 Compare Value Store Register 0xA4 16 read-write n 0x0 0x0 ADCMP_ACCPDN1 ADCMP ch.1 Compare Value Store Register 0xAC read-write n 0x0 0x0 ADCMP_ACCPDN2 ADCMP ch.2 Compare Value Store Register 0xB4 read-write n 0x0 0x0 ADCMP_ACSA ADCMP Control Register A 0xBC 16 read-write n 0x0 0x0 CE0 enable or disable the operation of ADCMP-ch.0 and select the FRT to be connected 0 1 read-write CE1 enable or disable the operation of ADCMP-ch.1 and select the FRT to be connected 2 1 read-write CE2 enable or disable the operation of ADCMP-ch.2 and select the FRT to be connected 4 1 read-write SEL0 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.0 8 1 read-write SEL1 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.1 10 1 read-write SEL2 which count state FRT should be in to instruct AD conversion to be started at ADCMP-ch.2 12 1 read-write ADCMP_ACSB ADCMP Control Register B 0xB8 8 read-write n 0x0 0x0 BDIS0 Disables the buffer function of the ACCP0 and ACCPDN0 registers 0 read-write BDIS1 Disables the buffer function of the ACCP1 and ACCPDN1 registers 1 read-write BDIS2 Disables the buffer function of the ACCP2 and ACCPDN2 registers 2 read-write BTS0 Performs buffer transfer of the ACCP0 and ACCPDN0 registers upon Peak value detection by FRT 4 read-write BTS1 Performs buffer transfer of the ACCP1 and ACCPDN1 registers upon Peak value detection by FRT 5 read-write BTS2 Performs buffer transfer of the ACCP2 and ACCPDN2 registers upon Peak value detection by FRT 6 read-write ADCMP_ATSA ADC Start Trigger Select Register 0xC0 16 read-write n 0x0 0x0 AD0P selects the start signal to be used to start priority conversion of ADC unit0 8 1 read-write AD0S selects the start signal to be used to start the scan conversion of ADC unit0 0 1 read-write AD1P selects the start signal to be used to start priority conversion of ADC unit1 10 1 read-write AD1S selects the start signal to be used to start the scan conversion of ADC unit1 2 1 read-write AD2P selects the start signal to be used to start priority conversion of ADC unit2 12 1 read-write AD2S selects the start signal to be used to start the scan conversion of ADC unit2 4 1 read-write FRT_TCCP0 FRT-ch.0 Cycle Setting Register 0x28 16 read-write n 0x0 0x0 FRT_TCCP1 FRT-ch.1 Cycle Setting Register 0x38 read-write n 0x0 0x0 FRT_TCCP2 FRT-ch.2 Cycle Setting Register 0x48 read-write n 0x0 0x0 FRT_TCDT0 FRT-ch.0 Count Value Register 0x2C 16 read-write n 0x0 0x0 FRT_TCDT1 FRT-ch.1 Count Value Register 0x3C read-write n 0x0 0x0 FRT_TCDT2 FRT-ch.2 Count Value Register 0x4C read-write n 0x0 0x0 FRT_TCSA0 FRT-ch.0 Control Register A 0x30 16 read-write n 0x0 0x0 BFE Enables TCCP's buffer function 7 read-write CLK FRT clock cycle 0 3 read-write ECKE Uses an external input clock (FRCK) as FRT's count clock 15 read-write ICLR interrupt flag 9 read-write ICRE Generates interrupt when 1 is set to TCSA.ICLR 8 read-write IRQZE Generates interrupt, when 1 is set to TCSA.IRQZF 13 read-write IRQZF zero interrupt flag 14 read-write MODE FRT's count mode 5 read-write SCLR FRT operation state initialization request 4 write-only STOP Puts FRT in stopping state 6 read-write FRT_TCSA1 FRT-ch.1 Control Register A 0x40 read-write n 0x0 0x0 FRT_TCSA2 FRT-ch.2 Control Register A 0x50 read-write n 0x0 0x0 FRT_TCSB0 FRT-ch.0 Control Register B 0x34 16 read-write n 0x0 0x0 AD0E Outputs AD conversion start signal to ADCunit0 upon Zero value detection by FRT 0 read-write AD1E Outputs AD conversion start signal to ADCunit1 upon Zero value detection by FRT 1 read-write AD2E Outputs AD conversion start signal to ADCunit2 upon Zero value detection by FRT 2 read-write FRT_TCSB1 FRT-ch.1 Control Register B 0x44 read-write n 0x0 0x0 FRT_TCSB2 FRT-ch.2 Control Register B 0x54 read-write n 0x0 0x0 ICU_ICCP0 ICU ch.0 Capture value store register 0x68 16 read-only n 0x0 0x0 ICU_ICCP1 ICU ch.1 Capture value store register 0x6C read-write n 0x0 0x0 ICU_ICCP2 ICU ch.2 Capture value store register 0x70 read-write n 0x0 0x0 ICU_ICCP3 ICU ch.3 Capture value store register 0x74 read-write n 0x0 0x0 ICU_ICFS10 ICU ch.1,0 Connecting FRT Select Register 0x60 8 read-write n 0x0 0x0 FSI0 Connects FRT ch.x to ICU ch.(0) 0 3 read-write FSI1 Connects FRT ch.x to ICU ch.(1) 4 3 read-write ICU_ICFS32 ICU ch.3,2 Connecting FRT Select Register 0x61 -1 read-write n 0x0 0x0 ICU_ICSA10 ICU ch.1,0 Control Register A 0x78 8 read-write n 0x0 0x0 EG0 enables/disables the operation of ICU-ch.(0) and selects a valid edge(s) 0 1 read-write EG1 enables/disables the operation of ICU-ch.(1) and selects a valid edge(s) 2 1 read-write ICE0 Generates interrupt, when 1 is set to ICSA.ICP0. 4 read-write ICE1 Generates interrupt, when 1 is set to ICSA.ICP1. 5 read-write ICP0 Indicates that a valid edge has been detected at ICU ch.(0) and the capture operation has been performed 6 read-write ICP1 Indicates that a valid edge has been detected at ICU ch.(1) and the capture operation has been performed 7 read-write ICU_ICSA32 ICU ch.3,2 Control Register A 0x7C -1 read-write n 0x0 0x0 ICU_ICSB10 ICU ch.1,0 Control Register B 0x79 8 read-only n 0x0 0x0 IEI0 indicates the latest valid edge of ICU-ch.(0) 0 read-only IEI1 indicates the latest valid edge of ICU-ch.(1) 1 read-only ICU_ICSB32 ICU ch.3,2 Control Register B 0x7D -1 read-write n 0x0 0x0 OCU_OCCP0 OCU ch.0 Compare Value Store Register 0x0 16 read-write n 0x0 0x0 OCU_OCCP1 OCU ch.1 Compare Value Store Register 0x4 read-write n 0x0 0x0 OCU_OCCP2 OCU ch.2 Compare Value Store Register 0x8 read-write n 0x0 0x0 OCU_OCCP3 OCU ch.3 Compare Value Store Register 0xC read-write n 0x0 0x0 OCU_OCCP4 OCU ch.4 Compare Value Store Register 0x10 read-write n 0x0 0x0 OCU_OCCP5 OCU ch.5 Compare Value Store Register 0x14 read-write n 0x0 0x0 OCU_OCFS10 OCU ch.1,0 Connecting FRT Select Register 0x58 8 read-write n 0x0 0x0 FSO0 Connects FRT ch.x to OCU ch.0 0 3 read-write FSO1 Connects FRT ch.x to OCU ch.1 4 3 read-write OCU_OCFS32 OCU ch.3,2 Connecting FRT Select Register 0x59 -1 read-write n 0x0 0x0 OCU_OCFS54 OCU ch.5,4 Connecting FRT Select Register 0x5C -1 read-write n 0x0 0x0 OCU_OCSA10 OCU ch.1,0 Control Register A 0x18 8 read-write n 0x0 0x0 BDIS0 Disables the buffer function of the OCCP(0) register 2 read-write BDIS1 Disables the buffer function of the OCCP(1) register 3 read-write CST0 Enables the operation of OCU ch.(0) 0 read-write CST1 Enables the operation of OCU ch.(1) 1 read-write IOE0 Generates interrupt, when 1 is set to OCSA.IOP0 4 read-write IOE1 Generates interrupt, when 1 is set to OCSA.IOP1 5 read-write IOP0 Indicates that a match has already been detected between FRT's count value and OCCP(0) value at OCU ch.(0). 6 read-write IOP1 Indicates that a match has already been detected between FRT's count value and OCCP(1) value at OCU ch.(1). 7 read-write OCU_OCSA32 OCU ch.3,2 Control Register A 0x1C -1 read-write n 0x0 0x0 OCU_OCSA54 OCU ch.5,4 Control Register A 0x20 -1 read-write n 0x0 0x0 OCU_OCSB10 OCU ch.1,0 Control Register B 0x19 8 read-write n 0x0 0x0 BTS0 Performs buffer transfer of the OCCP(0) register upon Peak value detection by FRT 5 read-write BTS1 Performs buffer transfer of the OCCP(1) register upon Peak value detection by FRT 6 read-write CMOD selects OCU's operation mode in combination with OCSC.MOD0 to MOD5 4 read-write OTD0 Indicates that the RT(0) output pin is in the High-level output state. 0 read-write OTD1 Indicates that the RT(1) output pin is in the High-level output state. 1 read-write OCU_OCSB32 OCU ch.3,2 Control Register B 0x1D -1 read-write n 0x0 0x0 OCU_OCSB54 OCU ch.5,4 Control Register B 0x21 -1 read-write n 0x0 0x0 OCU_OCSC OCU Control Register C 0x24 16 read-write n 0x0 0x0 MOD0 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 8 read-write MOD1 OCSC.MOD0 and OCSC.MOD1 determine the operation mode of OCU ch.0/ch.1 in combination with OCSB10.CMOD 9 read-write MOD2 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 10 read-write MOD3 OCSC.MOD2 and OCSC.MOD3 determine the operation mode of OCU ch.2/ch.3 in combination with OCSB32.CMOD 11 read-write MOD4 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 12 read-write MOD5 OCSC.MOD4 and OCSC.MOD5 determine the operation mode of OCU ch.4/ch.5 in combination with OCSB54.CMOD 13 read-write WFG_NZCL NZCL Control Register 0x9C 16 read-write n 0x0 0x0 DTIE DTIF interrupt enable 0 read-write NWS noise-canceling width of the noise-canceller for the DTTIX pin 1 2 read-write SDTI Forcibly generates DTIF interrupt 4 write-only WFG_WFIR WFG Interrupt Control Register 0x98 16 read-write n 0x0 0x0 DTIC Clears WFIR.DTIF and deasserts the DTIF interrupt signal. 1 write-only DTIF Indicates that DTIF interrupt has been generated. 0 read-only TMIC10 Clears WFIR.TMIF10 and deasserts the WFG10 timer interrupt signal. 5 write-only TMIC32 Clears WFIR.TMIF32 and deasserts the WFG32 timer interrupt signal. 9 write-only TMIC54 Clears WFIR.TMIF54 and deasserts the WFG54 timer interrupt signal. 13 write-only TMIE10 Starts the WFG10 timer 6 read-write TMIE32 Starts the WFG32 timer 10 read-write TMIE54 Starts the WFG54 timer 14 read-write TMIF10 Indicates that WFG10 timer interrupt has been generated. 4 read-only TMIF32 Indicates that WFG32 timer interrupt has been generated. 8 read-only TMIF54 Indicates that WFG54 timer interrupt has been generated. 12 read-only TMIS10 Stops the WFG10 timer 7 write-only TMIS32 Stops the WFG32 timer 11 write-only TMIS54 Stops the WFG54 timer 15 write-only WFG_WFSA10 WFG ch.10 Control Register A 0x8C 16 read-write n 0x0 0x0 DCK clock cycle of the WFG timer 0 2 read-write DMOD specifies which polarity will be used to output the non-overlap signal 12 read-write GTEN the CH_GATE signal for each channel of WFG 6 1 read-write PGEN specifies how to reflect the CH_PPG signal that is input to each channel of WFG on WFG output 10 1 read-write PSEL the PPG timer unit to be used at each channel of WFG 8 1 read-write TMD WFG's operation mode 3 2 read-write WFG_WFSA32 WFG ch.32 Control Register A 0x90 read-write n 0x0 0x0 WFG_WFSA54 WFG ch.54 Control Register A 0x94 read-write n 0x0 0x0 WFG_WFTM10 WFG ch.10 Timer Value Register 0x80 16 read-write n 0x0 0x0 WFG_WFTM32 WFG ch.32 Timer Value Register 0x84 read-write n 0x0 0x0 WFG_WFTM54 WFG ch.54 Timer Value Register 0x88 read-write n 0x0 0x0 MFT_PPG PPG Configuration MFT_PPG 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x100 0x2 registers n 0x104 0x2 registers n 0x14 0x1 registers n 0x140 0x2 registers n 0x144 0x2 registers n 0x20 0x2 registers n 0x200 0x2 registers n 0x204 0x2 registers n 0x208 0x2 registers n 0x20C 0x2 registers n 0x210 0x2 registers n 0x214 0x2 registers n 0x218 0x1 registers n 0x240 0x2 registers n 0x244 0x2 registers n 0x248 0x2 registers n 0x24C 0x2 registers n 0x250 0x2 registers n 0x254 0x2 registers n 0x258 0x1 registers n 0x28 0x2 registers n 0x280 0x2 registers n 0x284 0x2 registers n 0x288 0x2 registers n 0x28C 0x2 registers n 0x290 0x2 registers n 0x294 0x2 registers n 0x298 0x1 registers n 0x2C 0x1 registers n 0x2C0 0x2 registers n 0x2C4 0x2 registers n 0x2C8 0x2 registers n 0x2CC 0x2 registers n 0x2D0 0x2 registers n 0x2D4 0x2 registers n 0x2D8 0x1 registers n 0x30 0x2 registers n 0x300 0x2 registers n 0x304 0x2 registers n 0x308 0x2 registers n 0x30C 0x2 registers n 0x310 0x2 registers n 0x314 0x2 registers n 0x318 0x1 registers n 0x34 0x1 registers n 0x340 0x2 registers n 0x344 0x2 registers n 0x348 0x2 registers n 0x34C 0x2 registers n 0x350 0x2 registers n 0x354 0x2 registers n 0x358 0x1 registers n 0x40 0x2 registers n 0x48 0x2 registers n 0x4C 0x1 registers n 0x50 0x2 registers n 0x54 0x1 registers n 0x8 0x2 registers n 0xC 0x1 registers n PPG 23 COMP0 PPG Compare Register 0 0x8 16 read-write n 0x0 0x0 COMP1 PPG Compare Register 1 0x28 read-write n 0x0 0x0 COMP10 PPG Compare Register 10 0x4C read-write n 0x0 0x0 COMP12 PPG Compare Register 12 0x50 read-write n 0x0 0x0 COMP14 PPG Compare Register 14 0x54 read-write n 0x0 0x0 COMP2 PPG Compare Register 2 0xC 8 read-write n 0x0 0x0 COMP3 PPG Compare Register 3 0x2C read-write n 0x0 0x0 COMP4 PPG Compare Register 4 0x10 read-write n 0x0 0x0 COMP5 PPG Compare Register 5 0x30 read-write n 0x0 0x0 COMP6 PPG Compare Register 6 0x14 read-write n 0x0 0x0 COMP7 PPG Compare Register 7 0x34 read-write n 0x0 0x0 COMP8 PPG Compare Register 8 0x48 read-write n 0x0 0x0 GATEC0 PPG Gate Function Control Registers 0 0x218 8 read-write n 0x0 0x0 EDGE0 Select Start Effective Level for PPG0 0 read-write EDGE2 Select Start Effective Level for PPG2 4 read-write STRG0 Select a trigger for PPG0 1 read-write STRG2 Select a trigger for PPG2 5 read-write GATEC12 PPG Gate Function Control Registers 12 0x2D8 8 read-write n 0x0 0x0 EDGE12 Select Start Effective Level for PPG12 0 read-write EDGE14 Select Start Effective Level for PPG14 4 read-write STRG12 Select a trigger for PPG12 1 read-write STRG14 Select a trigger for PPG14 5 read-write GATEC16 PPG Gate Function Control Registers 16 0x318 8 read-write n 0x0 0x0 EDGE16 Select Start Effective Level for PPG16 0 read-write EDGE18 Select Start Effective Level for PPG18 4 read-write STRG16 Select a trigger for PPG16 1 read-write STRG18 Select a trigger for PPG18 5 read-write GATEC20 PPG Gate Function Control Registers 20 0x358 8 read-write n 0x0 0x0 EDGE20 Select Start Effective Level for PPG20 0 read-write EDGE22 Select Start Effective Level for PPG22 4 read-write STRG20 Select a trigger for PPG20 1 read-write STRG22 Select a trigger for PPG22 5 read-write GATEC4 PPG Gate Function Control Registers 4 0x258 8 read-write n 0x0 0x0 EDGE4 Select Start Effective Level for PPG4 0 read-write EDGE6 Select Start Effective Level for PPG6 4 read-write STRG4 Select a trigger for PPG4 1 read-write STRG6 Select a trigger for PPG6 5 read-write GATEC8 PPG Gate Function Control Registers 8 0x298 8 read-write n 0x0 0x0 EDGE10 Select Start Effective Level for PPG10 4 read-write EDGE8 Select Start Effective Level for PPG8 0 read-write STRG10 Select a trigger for PPG10 5 read-write STRG8 Select a trigger for PPG8 1 read-write PPGC0 PPG Operation Mode Control Register 0 0x201 8 read-write n 0x0 0x0 INTM Interrupt Mode Select bit 5 read-write MD PPG Operation Mode Set bits 1 1 read-write PCS PPG DOWN Counter Operation Clock Select bits 3 1 read-write PIE PPG Interrupt Enable bit 7 read-write PUF PPG Counter Underflow bit 6 read-write TTRG PPG start trigger select bit 0 read-write PPGC1 PPG Operation Mode Control Register 1 0x200 read-write n 0x0 0x0 PPGC10 PPG Operation Mode Control Register 10 0x285 read-write n 0x0 0x0 PPGC11 PPG Operation Mode Control Register 11 0x284 read-write n 0x0 0x0 PPGC12 PPG Operation Mode Control Register 12 0x2C1 read-write n 0x0 0x0 PPGC13 PPG Operation Mode Control Register 13 0x2C0 read-write n 0x0 0x0 PPGC14 PPG Operation Mode Control Register 14 0x2C5 read-write n 0x0 0x0 PPGC15 PPG Operation Mode Control Register 15 0x2C4 read-write n 0x0 0x0 PPGC16 PPG Operation Mode Control Register 16 0x301 read-write n 0x0 0x0 PPGC17 PPG Operation Mode Control Register 17 0x300 read-write n 0x0 0x0 PPGC18 PPG Operation Mode Control Register 18 0x305 read-write n 0x0 0x0 PPGC19 PPG Operation Mode Control Register 19 0x304 read-write n 0x0 0x0 PPGC2 PPG Operation Mode Control Register 2 0x205 read-write n 0x0 0x0 PPGC20 PPG Operation Mode Control Register 20 0x341 read-write n 0x0 0x0 PPGC21 PPG Operation Mode Control Register 21 0x340 read-write n 0x0 0x0 PPGC22 PPG Operation Mode Control Register 22 0x345 read-write n 0x0 0x0 PPGC23 PPG Operation Mode Control Register 23 0x344 read-write n 0x0 0x0 PPGC3 PPG Operation Mode Control Register 3 0x204 read-write n 0x0 0x0 PPGC4 PPG Operation Mode Control Register 4 0x241 read-write n 0x0 0x0 PPGC5 PPG Operation Mode Control Register 5 0x240 read-write n 0x0 0x0 PPGC6 PPG Operation Mode Control Register 6 0x245 read-write n 0x0 0x0 PPGC7 PPG Operation Mode Control Register 7 0x244 read-write n 0x0 0x0 PPGC8 PPG Operation Mode Control Register 8 0x281 read-write n 0x0 0x0 PPGC9 PPG Operation Mode Control Register 9 0x280 read-write n 0x0 0x0 PRLH0 PPG0 Reload Registers High 0x209 8 read-write n 0x0 0x0 PRLH Reload Registers High 0 7 read-write PRLH1 PPG1 Reload Registers High 0x20D read-write n 0x0 0x0 PRLH10 PPG10 Reload Registers High 0x291 read-write n 0x0 0x0 PRLH11 PPG11 Reload Registers High 0x295 read-write n 0x0 0x0 PRLH12 PPG12 Reload Registers High 0x2C9 read-write n 0x0 0x0 PRLH13 PPG13 Reload Registers High 0x2CD read-write n 0x0 0x0 PRLH14 PPG14 Reload Registers High 0x2D1 read-write n 0x0 0x0 PRLH15 PPG15 Reload Registers High 0x2D5 read-write n 0x0 0x0 PRLH16 PPG16 Reload Registers High 0x309 read-write n 0x0 0x0 PRLH17 PPG17 Reload Registers High 0x30D read-write n 0x0 0x0 PRLH18 PPG18 Reload Registers High 0x311 read-write n 0x0 0x0 PRLH19 PPG19 Reload Registers High 0x315 read-write n 0x0 0x0 PRLH2 PPG2 Reload Registers High 0x211 read-write n 0x0 0x0 PRLH20 PPG20 Reload Registers High 0x349 read-write n 0x0 0x0 PRLH21 PPG21 Reload Registers High 0x34D read-write n 0x0 0x0 PRLH22 PPG22 Reload Registers High 0x351 read-write n 0x0 0x0 PRLH23 PPG23 Reload Registers High 0x355 read-write n 0x0 0x0 PRLH3 PPG3 Reload Registers High 0x215 read-write n 0x0 0x0 PRLH4 PPG4 Reload Registers High 0x249 read-write n 0x0 0x0 PRLH5 PPG5 Reload Registers High 0x24D read-write n 0x0 0x0 PRLH6 PPG6 Reload Registers High 0x251 read-write n 0x0 0x0 PRLH7 PPG7 Reload Registers High 0x255 read-write n 0x0 0x0 PRLH8 PPG8 Reload Registers High 0x289 read-write n 0x0 0x0 PRLH9 PPG9 Reload Registers High 0x28D read-write n 0x0 0x0 PRLL0 PPG0 Reload Registers Low 0x208 8 read-write n 0x0 0x0 PRLL Reload Registers Low 0 7 read-write PRLL1 PPG1 Reload Registers Low 0x20C read-write n 0x0 0x0 PRLL10 PPG10 Reload Registers Low 0x290 read-write n 0x0 0x0 PRLL11 PPG11 Reload Registers Low 0x294 read-write n 0x0 0x0 PRLL12 PPG12 Reload Registers Low 0x2C8 read-write n 0x0 0x0 PRLL13 PPG13 Reload Registers Low 0x2CC read-write n 0x0 0x0 PRLL14 PPG14 Reload Registers Low 0x2D0 read-write n 0x0 0x0 PRLL15 PPG15 Reload Registers Low 0x2D4 read-write n 0x0 0x0 PRLL16 PPG16 Reload Registers Low 0x308 read-write n 0x0 0x0 PRLL17 PPG17 Reload Registers Low 0x30C read-write n 0x0 0x0 PRLL18 PPG18 Reload Registers Low 0x310 read-write n 0x0 0x0 PRLL19 PPG19 Reload Registers Low 0x314 read-write n 0x0 0x0 PRLL2 PPG2 Reload Registers Low 0x210 read-write n 0x0 0x0 PRLL20 PPG20 Reload Registers Low 0x348 read-write n 0x0 0x0 PRLL21 PPG21 Reload Registers Low 0x34C read-write n 0x0 0x0 PRLL22 PPG22 Reload Registers Low 0x350 read-write n 0x0 0x0 PRLL23 PPG23 Reload Registers Low 0x354 read-write n 0x0 0x0 PRLL3 PPG3 Reload Registers Low 0x214 read-write n 0x0 0x0 PRLL4 PPG4 Reload Registers Low 0x248 read-write n 0x0 0x0 PRLL5 PPG5 Reload Registers Low 0x24C read-write n 0x0 0x0 PRLL6 PPG6 Reload Registers Low 0x250 read-write n 0x0 0x0 PRLL7 PPG7 Reload Registers Low 0x254 read-write n 0x0 0x0 PRLL8 PPG8 Reload Registers Low 0x288 read-write n 0x0 0x0 PRLL9 PPG9 Reload Registers Low 0x28C read-write n 0x0 0x0 REVC Output Reverse Register 0 0x104 16 read-write n 0x0 0x0 REV00 PPG0 Output Reverse Enable bit 0 read-write REV01 PPG1 Output Reverse Enable bit 1 read-write REV02 PPG2 Output Reverse Enable bit 2 read-write REV03 PPG3 Output Reverse Enable bit 3 read-write REV04 PPG4 Output Reverse Enable bit 4 read-write REV05 PPG5 Output Reverse Enable bit 5 read-write REV06 PPG6 Output Reverse Enable bit 6 read-write REV07 PPG7 Output Reverse Enable bit 7 read-write REV08 PPG8 Output Reverse Enable bit 8 read-write REV09 PPG9 Output Reverse Enable bit 9 read-write REV10 PPG10 Output Reverse Enable bit 10 read-write REV11 PPG11 Output Reverse Enable bit 11 read-write REV12 PPG12 Output Reverse Enable bit 12 read-write REV13 PPG13 Output Reverse Enable bit 13 read-write REV14 PPG14 Output Reverse Enable bit 14 read-write REV15 PPG15 Output Reverse Enable bit 15 read-write REVC1 Output Reverse Register 1 0x144 16 read-write n 0x0 0x0 REV16 PPG16 Output Reverse Enable bit 0 read-write REV17 PPG17 Output Reverse Enable bit 1 read-write REV18 PPG18 Output Reverse Enable bit 2 read-write REV19 PPG19 Output Reverse Enable bit 3 read-write REV20 PPG20 Output Reverse Enable bit 4 read-write REV21 PPG21 Output Reverse Enable bit 5 read-write REV22 PPG22 Output Reverse Enable bit 6 read-write REV23 PPG23 Output Reverse Enable bit 7 read-write TRG PPG Start Register 0 0x100 16 read-write n 0x0 0x0 PEN00 PPG0 Start Trigger bit 0 read-write PEN01 PPG1 Start Trigger bit 1 read-write PEN02 PPG2 Start Trigger bit 2 read-write PEN03 PPG3 Start Trigger bit 3 read-write PEN04 PPG4 Start Trigger bit 4 read-write PEN05 PPG5 Start Trigger bit 5 read-write PEN06 PPG6 Start Trigger bit 6 read-write PEN07 PPG7 Start Trigger bit 7 read-write PEN08 PPG8 Start Trigger bit 8 read-write PEN09 PPG9 Start Trigger bit 9 read-write PEN10 PPG10 Start Trigger bit 10 read-write PEN11 PPG11 Start Trigger bit 11 read-write PEN12 PPG12 Start Trigger bit 12 read-write PEN13 PPG13 Start Trigger bit 13 read-write PEN14 PPG14 Start Trigger bit 14 read-write PEN15 PPG15 Start Trigger bit 15 read-write TRG1 PPG Start Register 1 0x140 16 read-write n 0x0 0x0 PEN16 PPG16 Start Trigger bit 0 read-write PEN17 PPG17 Start Trigger bit 1 read-write PEN18 PPG18 Start Trigger bit 2 read-write PEN19 PPG19 Start Trigger bit 3 read-write PEN20 PPG20 Start Trigger bit 4 read-write PEN21 PPG21 Start Trigger bit 5 read-write PEN22 PPG22 Start Trigger bit 6 read-write PEN23 PPG23 Start Trigger bit 7 read-write TTCR0 PPG Start Trigger Control Register 0 0x0 16 read-write n 0x0 0x0 CS0 8-bit UP counter clock select bits for comparison 10 1 read-write MONI0 8-bit UP counter operation state monitor bit for comparison 9 read-only STR0 8-bit UP counter operation enable bit for comparison 8 read-write TRG0O PPG0 trigger stop bit 12 read-write TRG2O PPG2 trigger stop bit 13 read-write TRG4O PPG4 trigger stop bit 14 read-write TRG6O PPG6 trigger stop bit 15 read-write TTCR1 PPG Start Trigger Control Register 1 0x20 16 read-write n 0x0 0x0 CS1 8-bit UP counter clock select bits for comparison 10 1 read-write MONI1 8-bit UP counter operation state monitor bit for comparison 9 read-only STR1 8-bit UP counter operation enable bit for comparison 8 read-write TRG1O PPG1 trigger stop bit 12 read-write TRG3O PPG3 trigger stop bit 13 read-write TRG5O PPG5 trigger stop bit 14 read-write TRG7O PPG7 trigger stop bit 15 read-write TTCR2 PPG Start Trigger Control Register 2 0x40 16 read-write n 0x0 0x0 CS2 8-bit UP counter clock select bits for comparison 10 1 read-write MONI2 8-bit UP counter operation state monitor bit for comparison 9 read-only STR2 8-bit UP counter operation enable bit for comparison 8 read-write TRG16O PPG16 trigger stop bit 12 read-write TRG18O PPG18 trigger stop bit 13 read-write TRG20O PPG20 trigger stop bit 14 read-write TRG22O PPG22 trigger stop bit 15 read-write QPRC0 Quadrature Position/Revolution Counter 0 QPRC0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x2 registers n 0x3C 0x2 registers n 0x3E 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n QCR QPRC Control Register 0x18 16 read-write n 0x0 0x0 AES AIN detection edge selection bits 10 1 read-write BES BIN detection edge selection bits 12 1 read-write CGE Detection edge selection bits 14 1 read-write CGSC Count clear or gate selection bit 5 read-write PCM Position counter mode bits 0 1 read-write PCRM Position counter reset mask bits 8 1 read-write PSTP Position counter stop bit 4 read-write RCM Revolution counter mode bits 2 1 read-write RSEL Register function selection bit 6 read-write SWAP Swap bit 7 read-write QECR QPRC Extension Control Register 0x1C 16 read-write n 0x0 0x0 ORNGF Outrange interrupt request flag bit 1 read-write ORNGIE Outrange interrupt enable bit 2 read-write ORNGMD Outrange mode selection bit 0 read-write QICRH High-Order Bytes of QPRC Interrupt Control Register 0x15 8 read-write n 0x0 0x0 CDCF Count inversion interrupt request flag bit 1 read-write CDCIE Count inversion interrupt enable bit 0 read-write DIROU Last position counter flow direction bit 3 read-only DIRPC Last position counter direction bit 2 read-only QPCNRCMF PC match and RC match interrupt request flag bit 5 read-write QPCNRCMIE PC match and RC match interrupt enable bit 4 read-write QICRL Low-Order Bytes of QPRC Interrupt Control Register 0x14 8 read-write n 0x0 0x0 OFDF Overflow interrupt request flag bit 6 read-write OUZIE Overflow, underflow, or zero index interrupt enable bit 4 read-write QPCMF PC match interrupt request flag bit 1 read-write QPCMIE PC match interrupt enable bit 0 read-write QPRCMF PC and RC match interrupt request flag bit 3 read-write QPRCMIE PC and RC match interrupt enable bit 2 read-write UFDF Underflow interrupt request flag bit 5 read-write ZIIF Zero index interrupt request flag bit 7 read-write QMPR QPRC Maximum Position Register 0x10 16 read-write n 0x0 0x0 QPCCR QPRC Position Counter Compare Register 0x8 16 read-write n 0x0 0x0 QPCR QPRC Position Count Register 0x0 16 read-write n 0x0 0x0 QPCRR Quad counter position count Register 0x3E 16 read-write n 0x0 0x0 QPRCR QPRC Position and Revolution Counter Compare Register 0xC 16 read-write n 0x0 0x0 QRCR QPRC Revolution Count Register 0x4 16 read-write n 0x0 0x0 QRCRR Quad counter rotation count Register 0x3C 16 read-write n 0x0 0x0 QPRC1 Quadrature Position/Revolution Counter 0 QPRC0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x2 registers n 0x3C 0x2 registers n 0x3E 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n QCR QPRC Control Register 0x18 16 read-write n 0x0 0x0 AES AIN detection edge selection bits 10 1 read-write BES BIN detection edge selection bits 12 1 read-write CGE Detection edge selection bits 14 1 read-write CGSC Count clear or gate selection bit 5 read-write PCM Position counter mode bits 0 1 read-write PCRM Position counter reset mask bits 8 1 read-write PSTP Position counter stop bit 4 read-write RCM Revolution counter mode bits 2 1 read-write RSEL Register function selection bit 6 read-write SWAP Swap bit 7 read-write QECR QPRC Extension Control Register 0x1C 16 read-write n 0x0 0x0 ORNGF Outrange interrupt request flag bit 1 read-write ORNGIE Outrange interrupt enable bit 2 read-write ORNGMD Outrange mode selection bit 0 read-write QICRH High-Order Bytes of QPRC Interrupt Control Register 0x15 8 read-write n 0x0 0x0 CDCF Count inversion interrupt request flag bit 1 read-write CDCIE Count inversion interrupt enable bit 0 read-write DIROU Last position counter flow direction bit 3 read-only DIRPC Last position counter direction bit 2 read-only QPCNRCMF PC match and RC match interrupt request flag bit 5 read-write QPCNRCMIE PC match and RC match interrupt enable bit 4 read-write QICRL Low-Order Bytes of QPRC Interrupt Control Register 0x14 8 read-write n 0x0 0x0 OFDF Overflow interrupt request flag bit 6 read-write OUZIE Overflow, underflow, or zero index interrupt enable bit 4 read-write QPCMF PC match interrupt request flag bit 1 read-write QPCMIE PC match interrupt enable bit 0 read-write QPRCMF PC and RC match interrupt request flag bit 3 read-write QPRCMIE PC and RC match interrupt enable bit 2 read-write UFDF Underflow interrupt request flag bit 5 read-write ZIIF Zero index interrupt request flag bit 7 read-write QMPR QPRC Maximum Position Register 0x10 16 read-write n 0x0 0x0 QPCCR QPRC Position Counter Compare Register 0x8 16 read-write n 0x0 0x0 QPCR QPRC Position Count Register 0x0 16 read-write n 0x0 0x0 QPCRR Quad counter position count Register 0x3E 16 read-write n 0x0 0x0 QPRCR QPRC Position and Revolution Counter Compare Register 0xC 16 read-write n 0x0 0x0 QRCR QPRC Revolution Count Register 0x4 16 read-write n 0x0 0x0 QRCRR Quad counter rotation count Register 0x3C 16 read-write n 0x0 0x0 QPRC2 Quadrature Position/Revolution Counter 0 QPRC0 0x0 0x0 0x2 registers n 0x10 0x2 registers n 0x14 0x2 registers n 0x18 0x2 registers n 0x1C 0x2 registers n 0x3C 0x2 registers n 0x3E 0x2 registers n 0x4 0x2 registers n 0x8 0x2 registers n 0xC 0x2 registers n QCR QPRC Control Register 0x18 16 read-write n 0x0 0x0 AES AIN detection edge selection bits 10 1 read-write BES BIN detection edge selection bits 12 1 read-write CGE Detection edge selection bits 14 1 read-write CGSC Count clear or gate selection bit 5 read-write PCM Position counter mode bits 0 1 read-write PCRM Position counter reset mask bits 8 1 read-write PSTP Position counter stop bit 4 read-write RCM Revolution counter mode bits 2 1 read-write RSEL Register function selection bit 6 read-write SWAP Swap bit 7 read-write QECR QPRC Extension Control Register 0x1C 16 read-write n 0x0 0x0 ORNGF Outrange interrupt request flag bit 1 read-write ORNGIE Outrange interrupt enable bit 2 read-write ORNGMD Outrange mode selection bit 0 read-write QICRH High-Order Bytes of QPRC Interrupt Control Register 0x15 8 read-write n 0x0 0x0 CDCF Count inversion interrupt request flag bit 1 read-write CDCIE Count inversion interrupt enable bit 0 read-write DIROU Last position counter flow direction bit 3 read-only DIRPC Last position counter direction bit 2 read-only QPCNRCMF PC match and RC match interrupt request flag bit 5 read-write QPCNRCMIE PC match and RC match interrupt enable bit 4 read-write QICRL Low-Order Bytes of QPRC Interrupt Control Register 0x14 8 read-write n 0x0 0x0 OFDF Overflow interrupt request flag bit 6 read-write OUZIE Overflow, underflow, or zero index interrupt enable bit 4 read-write QPCMF PC match interrupt request flag bit 1 read-write QPCMIE PC match interrupt enable bit 0 read-write QPRCMF PC and RC match interrupt request flag bit 3 read-write QPRCMIE PC and RC match interrupt enable bit 2 read-write UFDF Underflow interrupt request flag bit 5 read-write ZIIF Zero index interrupt request flag bit 7 read-write QMPR QPRC Maximum Position Register 0x10 16 read-write n 0x0 0x0 QPCCR QPRC Position Counter Compare Register 0x8 16 read-write n 0x0 0x0 QPCR QPRC Position Count Register 0x0 16 read-write n 0x0 0x0 QPCRR Quad counter position count Register 0x3E 16 read-write n 0x0 0x0 QPRCR QPRC Position and Revolution Counter Compare Register 0xC 16 read-write n 0x0 0x0 QRCR QPRC Revolution Count Register 0x4 16 read-write n 0x0 0x0 QRCRR Quad counter rotation count Register 0x3C 16 read-write n 0x0 0x0 SBSSR Software-based Simultaneous Startup Register SBSSR 0x0 0xFC 0x2 registers n BTSSSR Software-based Simultaneous Startup Register 0xFC 16 write-only n 0x0 0x0 SSSR0 Bit0 of BTSSSR 0 write-only SSSR1 Bit1 of BTSSSR 1 write-only SSSR10 Bit10 of BTSSSR 10 write-only SSSR11 Bit11 of BTSSSR 11 write-only SSSR12 Bit12 of BTSSSR 12 write-only SSSR13 Bit13 of BTSSSR 13 write-only SSSR14 Bit14 of BTSSSR 14 write-only SSSR15 Bit15 of BTSSSR 15 write-only SSSR2 Bit2 of BTSSSR 2 write-only SSSR3 Bit3 of BTSSSR 3 write-only SSSR4 Bit4 of BTSSSR 4 write-only SSSR5 Bit5 of BTSSSR 5 write-only SSSR6 Bit6 of BTSSSR 6 write-only SSSR7 Bit7 of BTSSSR 7 write-only SSSR8 Bit8 of BTSSSR 8 write-only SSSR9 Bit9 of BTSSSR 9 write-only SWWDT Software Watchdog Timer SWWDT 0x0 0x0 0x4 registers n 0x10 0x1 registers n 0x4 0x4 registers n 0x4 0x4 registers n 0x8 0x1 registers n 0xC 0x4 registers n 0xC00 0x4 registers n SWDT 1 WDOGCONTROL Software Watchdog Timer Control Register 0x8 8 read-write n 0x0 0x0 INTEN Interrupt and counter enable bit of the software watchdog 0 read-write RESEN Reset enable bit of the software watchdog 1 read-write WDOGINTCLR Software Watchdog Timer Clear Register 0xC 32 read-write n 0x0 0x0 WDOGLOAD Software Watchdog Timer Load Register 0x0 32 read-write n 0x0 0x0 WDOGLOCK Software Watchdog Timer Lock Register 0xC00 32 read-write n 0x0 0x0 WDOGRIS Software Watchdog Timer Interrupt Status Register 0x10 8 read-only n 0x0 0x0 RIS Software watchdog interrupt status bit 0 read-only WDOGVALUE Software Watchdog Timer Value Register 0x4 32 read-only n 0x0 0x0 USB0 USB0 Function USB0 0x0 0x2100 0x2 registers n 0x2104 0x2 registers n 0x2108 0x2 registers n 0x210C 0x2 registers n 0x2110 0x2 registers n 0x2114 0x2 registers n 0x2118 0x2 registers n 0x211C 0x1 registers n 0x2120 0x2 registers n 0x2124 0x2 registers n 0x2128 0x2 registers n 0x212C 0x2 registers n 0x2130 0x2 registers n 0x2134 0x2 registers n 0x2138 0x2 registers n 0x213C 0x2 registers n 0x2140 0x2 registers n 0x2144 0x2 registers n 0x2148 0x2 registers n 0x214C 0x2 registers n 0x2150 0x2 registers n 0x2154 0x2 registers n 0x2158 0x2 registers n 0x215C 0x2 registers n 0x2160 0x2 registers n 0x2164 0x2 registers n 0x2168 0x2 registers n 0x216C 0x2 registers n 0x2170 0x2 registers n 0x2174 0x2 registers n USB0F 34 USB0F_USB0H 35 EP0C EP0 Control Register 0x2124 16 read-write n 0x0 0x0 PKS0 Packet Size Endpoint 0 Setting bits 0 6 read-write STAL Endpoint 0 Stall Setting bit 9 read-write EP0DT EP0 Data Register 0x2160 16 read-write n 0x0 0x0 BFDT Endpoint Send/Receive Buffer Data 0 15 read-write EP0IS EP0I Status Register 0x2144 16 read-write n 0x0 0x0 BFINI Send Buffer Initialization bit 15 read-write DRQI Send/Receive Data Interrupt Request bit 10 read-write DRQIIE Send Data Interrupt Enable bit 14 read-write EP0OS EP0O Status Register 0x2148 16 read-write n 0x0 0x0 BFINI Receive Buffer Initialization bit 15 read-write DRQO Receive Data Interrupt Request bit 10 read-write DRQOIE Receive Data Interrupt Enable bit 14 read-write SIZE Packet Size Indication bit 0 6 read-only SPK Short Packet Interrupt Request bit 9 read-write SPKIE Short Packet Interrupt Enable bit 13 read-write EP1C EP1 Control Register 0x2128 16 read-write n 0x0 0x0 DIR Endpoint Transfer Direction Select bit 12 read-write DMAE DMA Automatic Transfer Enable bit 11 read-write EPEN Endpoint Enable bit 15 read-write NULE Null Automatic Transfer Enable bit 10 read-write PKS Packet Size Setting bits 0 8 read-write STAL Endpoint Stall Setting bit 9 read-write TYPE Endpoint Transfer Type Select bits 13 1 read-write EP1DT EP1 Data Register 0x2164 read-write n 0x0 0x0 EP1S EP1 Status Register 0x214C 16 read-write n 0x0 0x0 BFINI Send/Receive Buffer Initialization bit 15 read-write BUSY Busy Flag bit 11 read-only DRQ Packet Transfer Interrupt Request bit 10 read-write DRQIE Packet Transfer Interrupt Enable bit 14 read-write SIZE packet SIZE 0 8 read-only SPK Short Packet Interrupt Request bit 9 read-write SPKIE Short Packet Interrupt Enable bit 13 read-write EP2C EP2 Control Register 0x212C 16 read-write n 0x0 0x0 DIR Endpoint Transfer Direction Select bit 12 read-write DMAE DMA Automatic Transfer Enable bit 11 read-write EPEN Endpoint Enable bit 15 read-write NULE Null Automatic Transfer Enable bit 10 read-write PKS Packet Size Setting bits 0 6 read-write STAL Endpoint Stall Setting bit 9 read-write TYPE Endpoint Transfer Type Select bits 13 1 read-write EP2DT EP2 Data Register 0x2168 read-write n 0x0 0x0 EP2S EP2 Status Register 0x2150 16 read-write n 0x0 0x0 BFINI Send/Receive Buffer Initialization bit 15 read-write BUSY Busy Flag bit 11 read-only DRQ Packet Transfer Interrupt Request bit 10 read-write DRQIE Packet Transfer Interrupt Enable bit 14 read-write SIZE packet SIZE 0 6 read-only SPK Short Packet Interrupt Request bit 9 read-write SPKIE Short Packet Interrupt Enable bit 13 read-write EP3C EP3 Control Register 0x2130 read-write n 0x0 0x0 EP3DT EP3 Data Register 0x216C read-write n 0x0 0x0 EP3S EP3 Status Register 0x2154 read-write n 0x0 0x0 EP4C EP4 Control Register 0x2134 read-write n 0x0 0x0 EP4DT EP4 Data Register 0x2170 read-write n 0x0 0x0 EP4S EP4 Status Register 0x2158 read-write n 0x0 0x0 EP5C EP5 Control Register 0x2138 read-write n 0x0 0x0 EP5DT EP5 Data Register 0x2174 read-write n 0x0 0x0 EP5S EP5 Status Register 0x215C read-write n 0x0 0x0 HADR Host Address Register 0x2111 8 read-write n 0x0 0x0 ADDRESS Host Address 0 6 read-write HCNT Host Control Register 0x2100 16 read-write n 0x0 0x0 CANCEL token cancellation enable bit 9 read-write CMPIRE token completion interrupt enable bit 5 read-write CNNIRE device connection detection interrupt enable bit 4 read-write DIRE device disconnection detection interrupt enable bit 3 read-write HOST host mode bit 0 read-write RETRY retry enable bit 8 read-write RWKIRE resume interrupt enable bit 7 read-write SOFIRE SOF interrupt enable bit 2 read-write SOFSTEP SOF interrupt occurrence selection bit 10 read-write URIRE bus reset interrupt enable bit 6 read-write URST bus reset bit 1 read-write HEOF EOF Setup Register 0x2114 16 read-write n 0x0 0x0 EOF0 End Frame 0 0 7 read-write EOF1 End Frame 1 8 5 read-write HERR Host Error Status Register 0x2105 8 read-write n 0x0 0x0 CRC CRC error flag 4 read-write HS handshake status flags 0 1 read-write LSTSOF lost SOF flag 7 read-write RERR receive error flag 6 read-write STUFF stuffing error flag 2 read-write TGERR toggle error flag 3 read-write TOUT timeout flag 5 read-write HFCOMP SOF Interrupt Frame Compare Register 0x2109 8 read-write n 0x0 0x0 FRAMECOMP frame compare data 0 7 read-write HFRAME Frame Setup Register 0x2118 16 read-write n 0x0 0x0 FRAME0 Frame Setup 0 0 7 read-write FRAME1 Frame Setup 1 8 2 read-write HIRQ Host Interrupt Register 0x2104 8 read-write n 0x0 0x0 CMPIRQ token completion flag 3 read-write CNNIRQ device connection detection flag 2 read-write DIRQ device disconnection detection flag 1 read-write RWKIRQ remote Wake-up end flag 5 read-write SOFIRQ SOF starting flag 0 read-write TCAN token cancellation flag 7 read-write URIRQ bus reset end flag 4 read-write HRTIMER Retry Timer Setup Register 0x210C 16 read-write n 0x0 0x0 RTIMER0 retry timer setting 0 0 7 read-write RTIMER1 retry timer setting 1 8 7 read-write HRTIMER2 Retry Timer Setup Register 2 0x2110 8 read-write n 0x0 0x0 RTIMER2 retry timer setting 2 0 1 read-write HSTATE Host Status Register 0x2108 8 read-write n 0x0 0x0 ALIVE specify the keep-alive function in the low-speed mode 5 read-write CLKSEL USB operation clock selection bit 4 read-write CSTAT connection status flag 0 read-only SOFBUSY SOF busy flag 3 read-write SUSP suspend setting bit 2 read-write TMODE transmission mode flag 1 read-only HTOKEN Host Token Endpoint Register 0x211C 8 read-write n 0x0 0x0 ENDPT endpoint bits 0 3 read-write TGGL toggle bit 7 read-write TKNEN token enable bits 4 2 read-write TMSP Time Stamp Register 0x213C 16 read-only n 0x0 0x0 TMSP Time Stamp bits 0 10 read-only UDCC UDC Control Register 0x2120 16 read-write n 0x0 0x0 HCONX Host Connection bit 5 read-write PWC Power Control bit 0 read-write RESUM Resume Setting bit 6 read-write RFBK Data Toggle Mode Select bit 1 read-write RST Function Reset bit 7 read-write STALCLREN Endpoint 1 to 5 STAL bit Clear Select bit 3 read-write USTP USB Operating Clock Stop bit 4 read-write UDCIE UDC Interrupt Enable Register 0x2141 8 read-write n 0x0 0x0 BRSTIE Bus Reset Enable bit 3 read-write CONFIE Configuration Interrupt Enable bit 0 read-write CONFN Configuration Number Indication bit 1 read-only SOFIE SOF Reception Interrupt Enable bit 4 read-write SUSPIE Suspend Interrupt Enable bit 5 read-write WKUPIE Wake-up Interrupt Enable bit 2 read-write UDCS UDC Status Register 0x2140 8 read-write n 0x0 0x0 BRST Bus Reset Detection bit 3 read-write CONF Configuration Detection bit 0 read-write SETP Setup Stage Detection bit 1 read-write SOF SOF Detection bit 4 read-write SUSP Suspend detection bit 5 read-write WKUP Wake-up Detection bit 2 read-write USB1 USB0 Function USB0 0x0 0x2100 0x2 registers n 0x2104 0x2 registers n 0x2108 0x2 registers n 0x210C 0x2 registers n 0x2110 0x2 registers n 0x2114 0x2 registers n 0x2118 0x2 registers n 0x211C 0x1 registers n 0x2120 0x2 registers n 0x2124 0x2 registers n 0x2128 0x2 registers n 0x212C 0x2 registers n 0x2130 0x2 registers n 0x2134 0x2 registers n 0x2138 0x2 registers n 0x213C 0x2 registers n 0x2140 0x2 registers n 0x2144 0x2 registers n 0x2148 0x2 registers n 0x214C 0x2 registers n 0x2150 0x2 registers n 0x2154 0x2 registers n 0x2158 0x2 registers n 0x215C 0x2 registers n 0x2160 0x2 registers n 0x2164 0x2 registers n 0x2168 0x2 registers n 0x216C 0x2 registers n 0x2170 0x2 registers n 0x2174 0x2 registers n USB1F 36 USB1F_USB1H 37 EP0C EP0 Control Register 0x2124 16 read-write n 0x0 0x0 PKS0 Packet Size Endpoint 0 Setting bits 0 6 read-write STAL Endpoint 0 Stall Setting bit 9 read-write EP0DT EP0 Data Register 0x2160 16 read-write n 0x0 0x0 BFDT Endpoint Send/Receive Buffer Data 0 15 read-write EP0IS EP0I Status Register 0x2144 16 read-write n 0x0 0x0 BFINI Send Buffer Initialization bit 15 read-write DRQI Send/Receive Data Interrupt Request bit 10 read-write DRQIIE Send Data Interrupt Enable bit 14 read-write EP0OS EP0O Status Register 0x2148 16 read-write n 0x0 0x0 BFINI Receive Buffer Initialization bit 15 read-write DRQO Receive Data Interrupt Request bit 10 read-write DRQOIE Receive Data Interrupt Enable bit 14 read-write SIZE Packet Size Indication bit 0 6 read-only SPK Short Packet Interrupt Request bit 9 read-write SPKIE Short Packet Interrupt Enable bit 13 read-write EP1C EP1 Control Register 0x2128 16 read-write n 0x0 0x0 DIR Endpoint Transfer Direction Select bit 12 read-write DMAE DMA Automatic Transfer Enable bit 11 read-write EPEN Endpoint Enable bit 15 read-write NULE Null Automatic Transfer Enable bit 10 read-write PKS Packet Size Setting bits 0 8 read-write STAL Endpoint Stall Setting bit 9 read-write TYPE Endpoint Transfer Type Select bits 13 1 read-write EP1DT EP1 Data Register 0x2164 read-write n 0x0 0x0 EP1S EP1 Status Register 0x214C 16 read-write n 0x0 0x0 BFINI Send/Receive Buffer Initialization bit 15 read-write BUSY Busy Flag bit 11 read-only DRQ Packet Transfer Interrupt Request bit 10 read-write DRQIE Packet Transfer Interrupt Enable bit 14 read-write SIZE packet SIZE 0 8 read-only SPK Short Packet Interrupt Request bit 9 read-write SPKIE Short Packet Interrupt Enable bit 13 read-write EP2C EP2 Control Register 0x212C 16 read-write n 0x0 0x0 DIR Endpoint Transfer Direction Select bit 12 read-write DMAE DMA Automatic Transfer Enable bit 11 read-write EPEN Endpoint Enable bit 15 read-write NULE Null Automatic Transfer Enable bit 10 read-write PKS Packet Size Setting bits 0 6 read-write STAL Endpoint Stall Setting bit 9 read-write TYPE Endpoint Transfer Type Select bits 13 1 read-write EP2DT EP2 Data Register 0x2168 read-write n 0x0 0x0 EP2S EP2 Status Register 0x2150 16 read-write n 0x0 0x0 BFINI Send/Receive Buffer Initialization bit 15 read-write BUSY Busy Flag bit 11 read-only DRQ Packet Transfer Interrupt Request bit 10 read-write DRQIE Packet Transfer Interrupt Enable bit 14 read-write SIZE packet SIZE 0 6 read-only SPK Short Packet Interrupt Request bit 9 read-write SPKIE Short Packet Interrupt Enable bit 13 read-write EP3C EP3 Control Register 0x2130 read-write n 0x0 0x0 EP3DT EP3 Data Register 0x216C read-write n 0x0 0x0 EP3S EP3 Status Register 0x2154 read-write n 0x0 0x0 EP4C EP4 Control Register 0x2134 read-write n 0x0 0x0 EP4DT EP4 Data Register 0x2170 read-write n 0x0 0x0 EP4S EP4 Status Register 0x2158 read-write n 0x0 0x0 EP5C EP5 Control Register 0x2138 read-write n 0x0 0x0 EP5DT EP5 Data Register 0x2174 read-write n 0x0 0x0 EP5S EP5 Status Register 0x215C read-write n 0x0 0x0 HADR Host Address Register 0x2111 8 read-write n 0x0 0x0 ADDRESS Host Address 0 6 read-write HCNT Host Control Register 0x2100 16 read-write n 0x0 0x0 CANCEL token cancellation enable bit 9 read-write CMPIRE token completion interrupt enable bit 5 read-write CNNIRE device connection detection interrupt enable bit 4 read-write DIRE device disconnection detection interrupt enable bit 3 read-write HOST host mode bit 0 read-write RETRY retry enable bit 8 read-write RWKIRE resume interrupt enable bit 7 read-write SOFIRE SOF interrupt enable bit 2 read-write SOFSTEP SOF interrupt occurrence selection bit 10 read-write URIRE bus reset interrupt enable bit 6 read-write URST bus reset bit 1 read-write HEOF EOF Setup Register 0x2114 16 read-write n 0x0 0x0 EOF0 End Frame 0 0 7 read-write EOF1 End Frame 1 8 5 read-write HERR Host Error Status Register 0x2105 8 read-write n 0x0 0x0 CRC CRC error flag 4 read-write HS handshake status flags 0 1 read-write LSTSOF lost SOF flag 7 read-write RERR receive error flag 6 read-write STUFF stuffing error flag 2 read-write TGERR toggle error flag 3 read-write TOUT timeout flag 5 read-write HFCOMP SOF Interrupt Frame Compare Register 0x2109 8 read-write n 0x0 0x0 FRAMECOMP frame compare data 0 7 read-write HFRAME Frame Setup Register 0x2118 16 read-write n 0x0 0x0 FRAME0 Frame Setup 0 0 7 read-write FRAME1 Frame Setup 1 8 2 read-write HIRQ Host Interrupt Register 0x2104 8 read-write n 0x0 0x0 CMPIRQ token completion flag 3 read-write CNNIRQ device connection detection flag 2 read-write DIRQ device disconnection detection flag 1 read-write RWKIRQ remote Wake-up end flag 5 read-write SOFIRQ SOF starting flag 0 read-write TCAN token cancellation flag 7 read-write URIRQ bus reset end flag 4 read-write HRTIMER Retry Timer Setup Register 0x210C 16 read-write n 0x0 0x0 RTIMER0 retry timer setting 0 0 7 read-write RTIMER1 retry timer setting 1 8 7 read-write HRTIMER2 Retry Timer Setup Register 2 0x2110 8 read-write n 0x0 0x0 RTIMER2 retry timer setting 2 0 1 read-write HSTATE Host Status Register 0x2108 8 read-write n 0x0 0x0 ALIVE specify the keep-alive function in the low-speed mode 5 read-write CLKSEL USB operation clock selection bit 4 read-write CSTAT connection status flag 0 read-only SOFBUSY SOF busy flag 3 read-write SUSP suspend setting bit 2 read-write TMODE transmission mode flag 1 read-only HTOKEN Host Token Endpoint Register 0x211C 8 read-write n 0x0 0x0 ENDPT endpoint bits 0 3 read-write TGGL toggle bit 7 read-write TKNEN token enable bits 4 2 read-write TMSP Time Stamp Register 0x213C 16 read-only n 0x0 0x0 TMSP Time Stamp bits 0 10 read-only UDCC UDC Control Register 0x2120 16 read-write n 0x0 0x0 HCONX Host Connection bit 5 read-write PWC Power Control bit 0 read-write RESUM Resume Setting bit 6 read-write RFBK Data Toggle Mode Select bit 1 read-write RST Function Reset bit 7 read-write STALCLREN Endpoint 1 to 5 STAL bit Clear Select bit 3 read-write USTP USB Operating Clock Stop bit 4 read-write UDCIE UDC Interrupt Enable Register 0x2141 8 read-write n 0x0 0x0 BRSTIE Bus Reset Enable bit 3 read-write CONFIE Configuration Interrupt Enable bit 0 read-write CONFN Configuration Number Indication bit 1 read-only SOFIE SOF Reception Interrupt Enable bit 4 read-write SUSPIE Suspend Interrupt Enable bit 5 read-write WKUPIE Wake-up Interrupt Enable bit 2 read-write UDCS UDC Status Register 0x2140 8 read-write n 0x0 0x0 BRST Bus Reset Detection bit 3 read-write CONF Configuration Detection bit 0 read-write SETP Setup Stage Detection bit 1 read-write SOF SOF Detection bit 4 read-write SUSP Suspend detection bit 5 read-write WKUP Wake-up Detection bit 2 read-write USBETHERCLK USB/Ethernet Clock USBETHERCLK 0x0 0x0 0x1 registers n 0x10 0x1 registers n 0x14 0x1 registers n 0x18 0x1 registers n 0x1C 0x1 registers n 0x20 0x1 registers n 0x24 0x1 registers n 0x28 0x1 registers n 0x2C 0x1 registers n 0x30 0x1 registers n 0x34 0x1 registers n 0x4 0x1 registers n 0x8 0x1 registers n 0xC 0x1 registers n UCCR USB/Ethernet-PLL Clock Control Register 0x0 8 read-write n 0x0 0x0 ECEN Ethernet clock output enable bit 4 read-write ECSEL0 Ethernet clock selection bit 0 6 read-write ECSEL1 Ethernet clock selection bit 1 7 read-write UCEN0 USB0 clock output enable bit 0 read-write UCEN1 USB1 clock output enable bit 3 read-write UCSEL0 USB0 clock selection bit 1 read-write UCSEL1 USB1 clock selection bit 2 read-write UPCR1 USB/Ethernet-PLL Control Register 1 0x4 8 read-write n 0x0 0x0 UPINC USB/Ethernet-PLL input clock selection bit 1 read-write UPLLEN USB/Ethernet-PLL oscillation enable bit 0 read-write UPCR2 USB/Ethernet-PLL Control Register 2 0x8 8 read-write n 0x0 0x0 UPOWT USB/Ethernet-PLL oscillation stabilization wait time setting bit 0 2 read-write UPCR3 USB/Ethernet-PLL Control Register 3 0xC 8 read-write n 0x0 0x0 UPLLK Frequency division ratio (K) setting bit of the USB/Ethernet-PLL clock 0 4 read-write UPCR4 USB/Ethernet-PLL Control Register 4 0x10 8 read-write n 0x0 0x0 UPLLN Frequency division ratio (N) setting bit of the USB/Ethernet-PLL clock 0 6 read-write UPCR5 USB/Ethernet-PLL Control Register 5 0x24 8 read-write n 0x0 0x0 UPLLM Frequency division ratio (M) setting bit of the USB/Ethernet-PLL clock 0 3 read-write UPCR6 USB/Ethernet-PLL Setting Register 6 0x28 8 read-write n 0x0 0x0 UBSR CLKPLL division ratio setting bit 0 3 read-write UPCR7 USB/Ethernet-PLL Setting Register 7 0x2C 8 read-write n 0x0 0x0 EPLLEN USB/Ethernet-PLL control bit in Timer mode 0 read-write UPINT_CLR USB/Ethernet-PLL Interrupt Source Clear Register 0x1C 8 write-only n 0x0 0x0 UPCSC USB/Ethernet-PLL oscillation stabilization interrupt source clear bit 0 write-only UPINT_ENR USB/Ethernet-PLL Interrupt Source Enable Register 0x18 8 read-write n 0x0 0x0 UPCSE USB/Ethernet-PLL oscillation stabilization wait complete interrupt enable bit 0 read-write UPINT_STR USB/Ethernet-PLL Interrupt Source Status Register 0x20 8 read-only n 0x0 0x0 UPCSI USB/Ethernet-PLL interrupt source status bit 0 read-only UP_STR USB/Ethernet-PLL Status Register 0x14 8 read-only n 0x0 0x0 UPRDY USB/Ethernet-PLL oscillation stabilization bit 0 read-only USBEN0 USB0 Enable Register 0x30 8 read-write n 0x0 0x0 USBEN0 USB0 enable bit 0 read-write USBEN1 USB1 Enable Register 0x34 8 read-write n 0x0 0x0 USBEN1 USB1 enable bit 0 read-write WC Watch Counter WC 0x0 0x0 0x3 registers n 0x10 0x2 registers n 0x14 0x1 registers n CLK_EN Division Clock Enable Register 0x14 8 read-write n 0x0 0x0 CLK_EN Division clock enable bit 0 read-write CLK_EN_R Division clock enable read bit 1 read-write CLK_SEL Clock Selection Register 0x10 16 read-write n 0x0 0x0 SEL_IN Input clock selection bit 0 read-write SEL_OUT Output clock selection bit 8 read-write WCCR Watch Counter Control Register 0x2 8 read-write n 0x0 0x0 CS Count clock select bits 2 1 read-write WCEN Watch counter operation enable bit 7 read-write WCIE Interrupt request enable bit 1 read-write WCIF Interrupt request flag bit 0 read-write WCOP Watch counter operating state flag 6 read-only WCRD Watch Counter Read Register 0x0 8 read-only n 0x0 0x0 CTR counter value 0 5 read-only WCRL Watch Counter Reload Register 0x1 8 read-write n 0x0 0x0 RLC reload value 0 5 read-write