Infineon
XMC1100-0032
2024.04.28
XMC1100-0032
Cortex-M0
r1p0
little
3
false
CCU40
Capture Compare Unit 4 - Unit 0
CCU4
0x0
0x0
0x10000
registers
n
CCU40_0
Capture Compare Unit 4 (Module 0)
21
CCU40_1
Capture Compare Unit 4 (Module 0)
22
CCU40_2
Capture Compare Unit 4 (Module 0)
23
CCU40_3
Capture Compare Unit 4 (Module 0)
24
GCSC
Global Channel Clear
0x14
32
read-write
n
0x0
0x0
S0DSC
Slice 0 Dither shadow transfer clear
1
write-only
S0PSC
Slice 0 Prescaler shadow transfer clear
2
write-only
S0SC
Slice 0 shadow transfer clear
0
write-only
S0STC
Slice 0 status bit clear
16
write-only
S1DSC
Slice 1 Dither shadow transfer clear
5
write-only
S1PSC
Slice 1 Prescaler shadow transfer clear
6
write-only
S1SC
Slice 1 shadow transfer clear
4
write-only
S1STC
Slice 1 status bit clear
17
write-only
S2DSC
Slice 2 Dither shadow transfer clear
9
write-only
S2PSC
Slice 2 Prescaler shadow transfer clear
10
write-only
S2SC
Slice 2 shadow transfer clear
8
write-only
S2STC
Slice 2 status bit clear
18
write-only
S3DSC
Slice 3 Dither shadow transfer clear
13
write-only
S3PSC
Slice 3 Prescaler shadow transfer clear
14
write-only
S3SC
Slice 3 shadow transfer clear
12
write-only
S3STC
Slice 3 status bit clear
19
write-only
GCSS
Global Channel Set
0x10
32
read-write
n
0x0
0x0
S0DSE
Slice 0 Dither shadow transfer set enable
1
write-only
S0PSE
Slice 0 Prescaler shadow transfer set enable
2
write-only
S0SE
Slice 0 shadow transfer set enable
0
write-only
S0STS
Slice 0 status bit set
16
write-only
S1DSE
Slice 1 Dither shadow transfer set enable
5
write-only
S1PSE
Slice 1 Prescaler shadow transfer set enable
6
write-only
S1SE
Slice 1 shadow transfer set enable
4
write-only
S1STS
Slice 1 status bit set
17
write-only
S2DSE
Slice 2 Dither shadow transfer set enable
9
write-only
S2PSE
Slice 2 Prescaler shadow transfer set enable
10
write-only
S2SE
Slice 2 shadow transfer set enable
8
write-only
S2STS
Slice 2 status bit set
18
write-only
S3DSE
Slice 3 Dither shadow transfer set enable
13
write-only
S3PSE
Slice 3 Prescaler shadow transfer set enable
14
write-only
S3SE
Slice 3 shadow transfer set enable
12
write-only
S3STS
Slice 3 status bit set
19
write-only
GCST
Global Channel Status
0x18
32
read-write
n
0x0
0x0
CC40ST
Slice 0 status bit
16
read-only
CC41ST
Slice 1 status bit
17
read-only
CC42ST
Slice 2 status bit
18
read-only
CC43ST
Slice 3 status bit
19
read-only
S0DSS
Slice 0 Dither shadow transfer status
1
read-only
value1
Dither shadow transfer has not been requested
#0
value2
Dither shadow transfer has been requested
#1
S0PSS
Slice 0 Prescaler shadow transfer status
2
read-only
value1
Prescaler shadow transfer has not been requested
#0
value2
Prescaler shadow transfer has been requested
#1
S0SS
Slice 0 shadow transfer status
0
read-only
value1
Shadow transfer has not been requested
#0
value2
Shadow transfer has been requested
#1
S1DSS
Slice 1 Dither shadow transfer status
5
read-only
value1
Dither shadow transfer has not been requested
#0
value2
Dither shadow transfer has been requested
#1
S1PSS
Slice 1 Prescaler shadow transfer status
6
read-only
value1
Prescaler shadow transfer has not been requested
#0
value2
Prescaler shadow transfer has been requested
#1
S1SS
Slice 1 shadow transfer status
4
read-only
value1
Shadow transfer has not been requested
#0
value2
Shadow transfer has been requested
#1
S2DSS
Slice 2 Dither shadow transfer status
9
read-only
value1
Dither shadow transfer has not been requested
#0
value2
Dither shadow transfer has been requested
#1
S2PSS
Slice 2 Prescaler shadow transfer status
10
read-only
value1
Prescaler shadow transfer has not been requested
#0
value2
Prescaler shadow transfer has been requested
#1
S2SS
Slice 2 shadow transfer status
8
read-only
value1
Shadow transfer has not been requested
#0
value2
Shadow transfer has been requested
#1
S3DSS
Slice 3 Dither shadow transfer status
13
read-only
value1
Dither shadow transfer has not been requested
#0
value2
Dither shadow transfer has been requested
#1
S3PSS
Slice 3 Prescaler shadow transfer status
14
read-only
value1
Prescaler shadow transfer has not been requested
#0
value2
Prescaler shadow transfer has been requested
#1
S3SS
Slice 3 shadow transfer status
12
read-only
value1
Shadow transfer has not been requested
#0
value2
Shadow transfer has been requested
#1
GCTRL
Global Control Register
0x0
32
read-write
n
0x0
0x0
MSDE
Multi Channel shadow transfer request configuration
14
1
read-write
value1
Only the shadow transfer for period and compare values is requested
#00
value2
Shadow transfer for the compare, period and prescaler compare values is requested
#01
value4
Shadow transfer for the compare, period, prescaler and dither compare values is requested
#11
MSE0
Slice 0 Multi Channel shadow transfer enable
10
read-write
value1
Shadow transfer can only be requested by SW
#0
value2
Shadow transfer can be requested via SW and via the CCU4x.MCSS input.
#1
MSE1
Slice 1 Multi Channel shadow transfer enable
11
read-write
value1
Shadow transfer can only be requested by SW
#0
value2
Shadow transfer can be requested via SW and via the CCU4x.MCSS input.
#1
MSE2
Slice 2 Multi Channel shadow transfer enable
12
read-write
value1
Shadow transfer can only be requested by SW
#0
value2
Shadow transfer can be requested via SW and via the CCU4x.MCSS input.
#1
MSE3
Slice 3 Multi Channel shadow transfer enable
13
read-write
value1
Shadow transfer can only be requested by SW
#0
value2
Shadow transfer can be requested via SW and via the CCU4x.MCSS input.
#1
PCIS
Prescaler Input Clock Selection
4
1
read-write
value1
Module clock
#00
value2
CCU4x.ECLKA
#01
value3
CCU4x.ECLKB
#10
value4
CCU4x.ECLKC
#11
PRBC
Prescaler Clear Configuration
0
2
read-write
value1
SW only
#000
value2
GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC40 is cleared.
#001
value3
GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC41 is cleared.
#010
value4
GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC42 is cleared.
#011
value5
GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC43 is cleared.
#100
SUSCFG
Suspend Mode Configuration
8
1
read-write
value1
Suspend request ignored. The module never enters in suspend
#00
value2
Stops all the running slices immediately. Safe stop is not applied.
#01
value3
Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied.
#10
value4
Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied.
#11
GIDLC
Global Idle Clear
0xC
32
read-write
n
0x0
0x0
CS0I
CC40 IDLE mode clear
0
write-only
CS1I
CC41 IDLE mode clear
1
write-only
CS2I
CC42 IDLE mode clear
2
write-only
CS3I
CC43 IDLE mode clear
3
write-only
SPRB
Prescaler Run Bit Set
8
write-only
GIDLS
Global Idle Set
0x8
32
read-write
n
0x0
0x0
CPRB
Prescaler Run Bit Clear
8
write-only
PSIC
Prescaler clear
9
write-only
SS0I
CC40 IDLE mode set
0
write-only
SS1I
CC41 IDLE mode set
1
write-only
SS2I
CC42 IDLE mode set
2
write-only
SS3I
CC43 IDLE mode set
3
write-only
GSTAT
Global Status Register
0x4
32
read-write
n
0x0
0x0
PRB
Prescaler Run Bit
8
read-only
value1
Prescaler is stopped
#0
value2
Prescaler is running
#1
S0I
CC40 IDLE status
0
read-only
value1
Running
#0
value2
Idle
#1
S1I
CC41 IDLE status
1
read-only
value1
Running
#0
value2
Idle
#1
S2I
CC42 IDLE status
2
read-only
value1
Running
#0
value2
Idle
#1
S3I
CC43 IDLE status
3
read-only
value1
Running
#0
value2
Idle
#1
MIDR
Module Identification
0x80
32
read-write
n
0x0
0x0
MODN
Module Number
16
15
read-only
MODR
Module Revision
0
7
read-only
MODT
Module Type
8
7
read-only
CCU40_CC40
Capture Compare Unit 4 - Unit 0
CCU4
0x0
0x0
0x100
registers
n
C0V
Capture Register 0
0x74
32
read-write
n
0x0
0x0
modifyExternal
CAPTV
Capture Value
0
15
read-only
FFL
Full Flag
20
read-only
value1
No new value was captured into the specific capture register
#0
value2
A new value was captured into the specific register
#1
FPCV
Prescaler Value
16
3
read-only
C1V
Capture Register 1
0x78
32
read-write
n
0x0
0x0
modifyExternal
CAPTV
Capture Value
0
15
read-only
FFL
Full Flag
20
read-only
value1
No new value was captured into the specific capture register
#0
value2
A new value was captured into the specific register
#1
FPCV
Prescaler Value
16
3
read-only
C2V
Capture Register 2
0x7C
32
read-write
n
0x0
0x0
modifyExternal
CAPTV
Capture Value
0
15
read-only
FFL
Full Flag
20
read-only
value1
No new value was captured into the specific capture register
#0
value2
A new value was captured into the specific register
#1
FPCV
Prescaler Value
16
3
read-only
C3V
Capture Register 3
0x80
32
read-write
n
0x0
0x0
modifyExternal
CAPTV
Capture Value
0
15
read-only
FFL
Full Flag
20
read-only
value1
No new value was captured into the specific capture register
#0
value2
A new value was captured into the specific register
#1
FPCV
Prescaler Value
16
3
read-only
CMC
Connection Matrix Control
0x4
32
read-write
n
0x0
0x0
CAP0S
External Capture 0 Functionality Selector
4
1
read-write
value1
External Capture 0 Function deactivated
#00
value2
External Capture 0 Function triggered by Event 0
#01
value3
External Capture 0 Function triggered by Event 1
#10
value4
External Capture 0 Function triggered by Event 2
#11
CAP1S
External Capture 1 Functionality Selector
6
1
read-write
value1
External Capture 1 Function deactivated
#00
value2
External Capture 1 Function triggered by Event 0
#01
value3
External Capture 1 Function triggered by Event 1
#10
value4
External Capture 1 Function triggered by Event 2
#11
CNTS
External Count Selector
14
1
read-write
value1
External Count Function deactivated
#00
value2
External Count Function triggered by Event 0
#01
value3
External Count Function triggered by Event 1
#10
value4
External Count Function triggered by Event 2
#11
ENDS
External Stop Functionality Selector
2
1
read-write
value1
External Stop Function deactivated
#00
value2
External Stop Function triggered by Event 0
#01
value3
External Stop Function triggered by Event 1
#10
value4
External Stop Function triggered by Event 2
#11
GATES
External Gate Functionality Selector
8
1
read-write
value1
External Gating Function deactivated
#00
value2
External Gating Function triggered by Event 0
#01
value3
External Gating Function triggered by Event 1
#10
value4
External Gating Function triggered by Event 2
#11
LDS
External Timer Load Functionality Selector
12
1
read-write
MOS
External Modulation Functionality Selector
18
1
read-write
OFS
Override Function Selector
16
read-write
value1
Override functionality disabled
#0
value2
Status bit trigger override connected to Event 1; Status bit value override connected to Event 2
#1
STRTS
External Start Functionality Selector
0
1
read-write
value1
External Start Function deactivated
#00
value2
External Start Function triggered by Event 0
#01
value3
External Start Function triggered by Event 1
#10
value4
External Start Function triggered by Event 2
#11
TCE
Timer Concatenation Enable
20
read-write
value1
Timer concatenation is disabled
#0
value2
Timer concatenation is enabled
#1
TS
Trap Function Selector
17
read-write
value1
Trap function disabled
#0
value2
TRAP function connected to Event 2
#1
UDS
External Up/Down Functionality Selector
10
1
read-write
value1
External Up/Down Function deactivated
#00
value2
External Up/Down Function triggered by Event 0
#01
value3
External Up/Down Function triggered by Event 1
#10
value4
External Up/Down Function triggered by Event 2
#11
CR
Timer Compare Value
0x38
32
read-write
n
0x0
0x0
CR
Compare Register
0
15
read-only
CRS
Timer Shadow Compare Value
0x3C
32
read-write
n
0x0
0x0
CRS
Compare Register
0
15
read-write
DIT
Dither Config
0x1C
32
read-write
n
0x0
0x0
DCNT
Dither counter actual value
8
3
read-only
DCV
Dither compare Value
0
3
read-only
DITS
Dither Shadow Register
0x20
32
read-write
n
0x0
0x0
DCVS
Dither Shadow Compare Value
0
3
read-write
ECRD0
Extended Read Back 0
0xB8
32
read-write
n
0x0
0x0
modifyExternal
CAPV
Timer Capture Value
0
15
read-only
FFL
Full Flag
24
read-only
value1
No new value was captured into this register
#0
value2
A new value has been captured into this register
#1
FPCV
Prescaler Capture value
16
3
read-only
LCV
Lost Capture Value
25
read-only
value1
No capture was lost
#0
value2
A capture was lost
#1
SPTR
Slice pointer
20
1
read-only
value1
CC40
#00
value2
CC41
#01
value3
CC42
#10
value4
CC43
#11
VPTR
Capture register pointer
22
1
read-only
value1
Capture register 0
#00
value2
Capture register 1
#01
value3
Capture register 2
#10
value4
Capture register 3
#11
ECRD1
Extended Read Back 1
0xBC
32
read-write
n
0x0
0x0
modifyExternal
CAPV
Timer Capture Value
0
15
read-only
FFL
Full Flag
24
read-only
value1
No new value was captured into this register
#0
value2
A new value has been captured into this register
#1
FPCV
Prescaler Capture value
16
3
read-only
LCV
Lost Capture Value
25
read-only
value1
No capture was lost
#0
value2
A capture was lost
#1
SPTR
Slice pointer
20
1
read-only
value1
CC40
#00
value2
CC41
#01
value3
CC42
#10
value4
CC43
#11
VPTR
Capture register pointer
22
1
read-only
value1
Capture register 0
#00
value2
Capture register 1
#01
value3
Capture register 2
#10
value4
Capture register 3
#11
FPC
Floating Prescaler Control
0x28
32
read-write
n
0x0
0x0
PCMP
Floating Prescaler Compare Value
0
3
read-only
PVAL
Actual Prescaler Value
8
3
read-write
FPCS
Floating Prescaler Shadow
0x2C
32
read-write
n
0x0
0x0
PCMP
Floating Prescaler Shadow Compare Value
0
3
read-write
INS
Input Selector Configuration
0x0
32
read-write
n
0x0
0x0
EV0EM
Event 0 Edge Selection
16
1
read-write
value1
No action
#00
value2
Signal active on rising edge
#01
value3
Signal active on falling edge
#10
value4
Signal active on both edges
#11
EV0IS
Event 0 signal selection
0
3
read-write
value1
CCU4x.INyA
#0000
value2
CCU4x.INyB
#0001
value3
CCU4x.INyC
#0010
value4
CCU4x.INyD
#0011
value5
CCU4x.INyE
#0100
value6
CCU4x.INyF
#0101
value7
CCU4x.INyG
#0110
value8
CCU4x.INyH
#0111
value9
CCU4x.INyI
#1000
value10
CCU4x.INyJ
#1001
value11
CCU4x.INyK
#1010
value12
CCU4x.INyL
#1011
value13
CCU4x.INyM
#1100
value14
CCU4x.INyN
#1101
value15
CCU4x.INyO
#1110
value16
CCU4x.INyP
#1111
EV0LM
Event 0 Level Selection
22
read-write
value1
Active on HIGH level
#0
value2
Active on LOW level
#1
EV1EM
Event 1 Edge Selection
18
1
read-write
value1
No action
#00
value2
Signal active on rising edge
#01
value3
Signal active on falling edge
#10
value4
Signal active on both edges
#11
EV1IS
Event 1 signal selection
4
3
read-write
value1
CCU4x.INyA
#0000
value2
CCU4x.INyB
#0001
value3
CCU4x.INyC
#0010
value4
CCU4x.INyD
#0011
value5
CCU4x.INyE
#0100
value6
CCU4x.INyF
#0101
value7
CCU4x.INyG
#0110
value8
CCU4x.INyH
#0111
value9
CCU4x.INyI
#1000
value10
CCU4x.INyJ
#1001
value11
CCU4x.INyK
#1010
value12
CCU4x.INyL
#1011
value13
CCU4x.INyM
#1100
value14
CCU4x.INyN
#1101
value15
CCU4x.INyO
#1110
value16
CCU4x.INyP
#1111
EV1LM
Event 1 Level Selection
23
read-write
value1
Active on HIGH level
#0
value2
Active on LOW level
#1
EV2EM
Event 2 Edge Selection
20
1
read-write
value1
No action
#00
value2
Signal active on rising edge
#01
value3
Signal active on falling edge
#10
value4
Signal active on both edges
#11
EV2IS
Event 2 signal selection
8
3
read-write
value1
CCU4x.INyA
#0000
value2
CCU4x.INyB
#0001
value3
CCU4x.INyC
#0010
value4
CCU4x.INyD
#0011
value5
CCU4x.INyE
#0100
value6
CCU4x.INyF
#0101
value7
CCU4x.INyG
#0110
value8
CCU4x.INyH
#0111
value9
CCU4x.INyI
#1000
value10
CCU4x.INyJ
#1001
value11
CCU4x.INyK
#1010
value12
CCU4x.INyL
#1011
value13
CCU4x.INyM
#1100
value14
CCU4x.INyN
#1101
value15
CCU4x.INyO
#1110
value16
CCU4x.INyP
#1111
EV2LM
Event 2 Level Selection
24
read-write
value1
Active on HIGH level
#0
value2
Active on LOW level
#1
LPF0M
Event 0 Low Pass Filter Configuration
25
1
read-write
value1
LPF is disabled
#00
value2
3 clock cycles of fCCU4
#01
value3
5 clock cycles of fCCU4
#10
value4
7 clock cycles of fCCU4
#11
LPF1M
Event 1 Low Pass Filter Configuration
27
1
read-write
value1
LPF is disabled
#00
value2
3 clock cycles of fCCU4
#01
value3
5 clock cycles of fCCU4
#10
value4
7 clock cycles of fCCU4
#11
LPF2M
Event 2 Low Pass Filter Configuration
29
1
read-write
value1
LPF is disabled
#00
value2
3 clock cycles of fCCU4
#01
value3
5 clock cycles of fCCU4
#10
value4
7 clock cycles of fCCU4
#11
INTE
Interrupt Enable Control
0xA4
32
read-write
n
0x0
0x0
CMDE
Compare match while counting down enable
3
read-write
value1
Compare Match while counting down interrupt is disabled
#0
value2
Compare Match while counting down interrupt is enabled
#1
CMUE
Compare match while counting up enable
2
read-write
value1
Compare Match while counting up interrupt is disabled
#0
value2
Compare Match while counting up interrupt is enabled
#1
E0AE
Event 0 interrupt enable
8
read-write
value1
Event 0 detection interrupt is disabled
#0
value2
Event 0 detection interrupt is enabled
#1
E1AE
Event 1 interrupt enable
9
read-write
value1
Event 1 detection interrupt is disabled
#0
value2
Event 1 detection interrupt is enabled
#1
E2AE
Event 2 interrupt enable
10
read-write
value1
Event 2 detection interrupt is disabled
#0
value2
Event 2 detection interrupt is enabled
#1
OME
One match while counting down enable
1
read-write
value1
One Match interrupt is disabled
#0
value2
One Match interrupt is enabled
#1
PME
Period match while counting up enable
0
read-write
value1
Period Match interrupt is disabled
#0
value2
Period Match interrupt is enabled
#1
INTS
Interrupt Status
0xA0
32
read-write
n
0x0
0x0
CMDS
Compare Match while Counting Down
3
read-only
value1
Compare match while counting down not detected
#0
value2
Compare match while counting down detected
#1
CMUS
Compare Match while Counting Up
2
read-only
value1
Compare match while counting up not detected
#0
value2
Compare match while counting up detected
#1
E0AS
Event 0 Detection Status
8
read-only
value1
Event 0 not detected
#0
value2
Event 0 detected
#1
E1AS
Event 1 Detection Status
9
read-only
value1
Event 1 not detected
#0
value2
Event 1 detected
#1
E2AS
Event 2 Detection Status
10
read-only
value1
Event 2 not detected
#0
value2
Event 2 detected
#1
OMDS
One Match while Counting Down
1
read-only
value1
One match while counting down not detected
#0
value2
One match while counting down detected
#1
PMUS
Period Match while Counting Up
0
read-only
value1
Period match while counting up not detected
#0
value2
Period match while counting up detected
#1
TRPF
Trap Flag Status
11
read-only
PR
Timer Period Value
0x30
32
read-write
n
0x0
0x0
PR
Period Register
0
15
read-only
PRS
Timer Shadow Period Value
0x34
32
read-write
n
0x0
0x0
PRS
Period Register
0
15
read-write
PSC
Prescaler Control
0x24
32
read-write
n
0x0
0x0
PSIV
Prescaler Initial Value
0
3
read-write
PSL
Passive Level Config
0x18
32
read-write
n
0x0
0x0
PSL
Output Passive Level
0
read-write
value1
Passive Level is LOW
#0
value2
Passive Level is HIGH
#1
SRS
Service Request Selector
0xA8
32
read-write
n
0x0
0x0
CMSR
Compare match Service request selector
2
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
E0SR
Event 0 Service request selector
8
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
E1SR
Event 1 Service request selector
10
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
E2SR
Event 2 Service request selector
12
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
POSR
Period/One match Service request selector
0
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
SWR
Interrupt Status Clear
0xB0
32
read-write
n
0x0
0x0
RCMD
Compare match while counting down clear
3
write-only
RCMU
Compare match while counting up clear
2
write-only
RE0A
Event 0 detection clear
8
write-only
RE1A
Event 1 detection clear
9
write-only
RE2A
Event 2 detection clear
10
write-only
ROM
One match while counting down clear
1
write-only
RPM
Period match while counting up clear
0
write-only
RTRPF
Trap Flag status clear
11
write-only
SWS
Interrupt Status Set
0xAC
32
read-write
n
0x0
0x0
SCMD
Compare match while counting down set
3
write-only
SCMU
Compare match while counting up set
2
write-only
SE0A
Event 0 detection set
8
write-only
SE1A
Event 1 detection set
9
write-only
SE2A
Event 2 detection set
10
write-only
SOM
One match while counting down set
1
write-only
SPM
Period match while counting up set
0
write-only
STRPF
Trap Flag status set
11
write-only
TC
Slice Timer Control
0x14
32
read-write
n
0x0
0x0
CAPC
Clear on Capture Control
5
1
read-write
value1
Timer is never cleared on a capture event
#00
value2
Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event)
#01
value3
Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event)
#10
value4
Timer is always cleared in a capture event.
#11
CCS
Continuous Capture Enable
12
read-write
value1
The capture into a specific capture register is done with the rules linked with the full flags, described at .
#0
value2
The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back).
#1
CLST
Shadow Transfer on Clear
2
read-write
CMOD
Capture Compare Mode
3
read-only
value1
Compare Mode
#0
value2
Capture Mode
#1
DIM
Dither input selector
15
read-write
value1
Slice is using its own dither unit
#0
value2
Slice is connected to the dither unit of slice 0.
#1
DITHE
Dither Enable
13
1
read-write
value1
Dither is disabled
#00
value2
Dither is applied to the Period
#01
value3
Dither is applied to the Compare
#10
value4
Dither is applied to the Period and Compare
#11
ECM
Extended Capture Mode
4
read-write
value1
Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only.
#0
value2
Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the ECRD.VPTR is cleared.
#1
EMS
External Modulation Synchronization
23
read-write
value1
External Modulation functionality is not synchronized with the PWM signal
#0
value2
External Modulation functionality is synchronized with the PWM signal
#1
EMT
External Modulation Type
24
read-write
value1
External Modulation functionality is clearing the CC4yST bit.
#0
value2
External Modulation functionality is gating the outputs.
#1
ENDM
Extended Stop Function Control
8
1
read-write
value1
Clears the timer run bit only (default stop)
#00
value2
Clears the timer only (flush)
#01
value3
Clears the timer and run bit (flush/stop)
#10
FPE
Floating Prescaler enable
16
read-write
value1
Floating prescaler mode is disabled
#0
value2
Floating prescaler mode is enabled
#1
MCME
Multi Channel Mode Enable
25
read-write
value1
Multi Channel Mode is disabled
#0
value2
Multi Channel Mode is enabled
#1
SCE
Equal Capture Event enable
11
read-write
value1
Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1
#0
value2
Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. and CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1
#1
STRM
Extended Start Function Control
10
read-write
value1
Sets run bit only (default start)
#0
value2
Clears the timer and sets run bit (flush/start)
#1
TCM
Timer Counting Mode
0
read-write
value1
Edge aligned mode
#0
value2
Center aligned mode
#1
TRAPE
TRAP enable
17
read-write
value1
TRAP functionality has no effect on the output
#0
value2
TRAP functionality affects the output
#1
TRPSE
TRAP Synchronization Enable
21
read-write
value1
Exiting from TRAP state isn't synchronized with the PWM signal
#0
value2
Exiting from TRAP state is synchronized with the PWM signal
#1
TRPSW
TRAP State Clear Control
22
read-write
value1
The slice exits the TRAP state automatically when the TRAP condition is not present
#0
value2
The TRAP state can only be exited by a SW request.
#1
TSSM
Timer Single Shot Mode
1
read-write
value1
Single shot mode is disabled
#0
value2
Single shot mode is enabled
#1
TCCLR
Slice Timer Clear
0x10
32
read-write
n
0x0
0x0
DITC
Dither Counter Clear
2
write-only
TCC
Timer Clear
1
write-only
TRBC
Timer Run Bit Clear
0
write-only
TCSET
Slice Timer Run Set
0xC
32
read-write
n
0x0
0x0
TRBS
Timer Run Bit set
0
write-only
TCST
Slice Timer Status
0x8
32
read-write
n
0x0
0x0
CDIR
Timer Counting Direction
1
read-only
value1
Timer is counting up
#0
value2
Timer is counting down
#1
TRB
Timer Run Bit
0
read-only
value1
Timer is stopped
#0
value2
Timer is running
#1
TIMER
Timer Value
0x70
32
read-write
n
0x0
0x0
TVAL
Timer Value
0
15
read-write
CCU40_CC41
Capture Compare Unit 4 - Unit 0
CCU4
0x0
0x0
0x100
registers
n
C0V
Capture Register 0
0x74
32
read-write
n
0x0
0x0
modifyExternal
CAPTV
Capture Value
0
15
read-only
FFL
Full Flag
20
read-only
value1
No new value was captured into the specific capture register
#0
value2
A new value was captured into the specific register
#1
FPCV
Prescaler Value
16
3
read-only
C1V
Capture Register 1
0x78
32
read-write
n
0x0
0x0
modifyExternal
CAPTV
Capture Value
0
15
read-only
FFL
Full Flag
20
read-only
value1
No new value was captured into the specific capture register
#0
value2
A new value was captured into the specific register
#1
FPCV
Prescaler Value
16
3
read-only
C2V
Capture Register 2
0x7C
32
read-write
n
0x0
0x0
modifyExternal
CAPTV
Capture Value
0
15
read-only
FFL
Full Flag
20
read-only
value1
No new value was captured into the specific capture register
#0
value2
A new value was captured into the specific register
#1
FPCV
Prescaler Value
16
3
read-only
C3V
Capture Register 3
0x80
32
read-write
n
0x0
0x0
modifyExternal
CAPTV
Capture Value
0
15
read-only
FFL
Full Flag
20
read-only
value1
No new value was captured into the specific capture register
#0
value2
A new value was captured into the specific register
#1
FPCV
Prescaler Value
16
3
read-only
CMC
Connection Matrix Control
0x4
32
read-write
n
0x0
0x0
CAP0S
External Capture 0 Functionality Selector
4
1
read-write
value1
External Capture 0 Function deactivated
#00
value2
External Capture 0 Function triggered by Event 0
#01
value3
External Capture 0 Function triggered by Event 1
#10
value4
External Capture 0 Function triggered by Event 2
#11
CAP1S
External Capture 1 Functionality Selector
6
1
read-write
value1
External Capture 1 Function deactivated
#00
value2
External Capture 1 Function triggered by Event 0
#01
value3
External Capture 1 Function triggered by Event 1
#10
value4
External Capture 1 Function triggered by Event 2
#11
CNTS
External Count Selector
14
1
read-write
value1
External Count Function deactivated
#00
value2
External Count Function triggered by Event 0
#01
value3
External Count Function triggered by Event 1
#10
value4
External Count Function triggered by Event 2
#11
ENDS
External Stop Functionality Selector
2
1
read-write
value1
External Stop Function deactivated
#00
value2
External Stop Function triggered by Event 0
#01
value3
External Stop Function triggered by Event 1
#10
value4
External Stop Function triggered by Event 2
#11
GATES
External Gate Functionality Selector
8
1
read-write
value1
External Gating Function deactivated
#00
value2
External Gating Function triggered by Event 0
#01
value3
External Gating Function triggered by Event 1
#10
value4
External Gating Function triggered by Event 2
#11
LDS
External Timer Load Functionality Selector
12
1
read-write
MOS
External Modulation Functionality Selector
18
1
read-write
OFS
Override Function Selector
16
read-write
value1
Override functionality disabled
#0
value2
Status bit trigger override connected to Event 1; Status bit value override connected to Event 2
#1
STRTS
External Start Functionality Selector
0
1
read-write
value1
External Start Function deactivated
#00
value2
External Start Function triggered by Event 0
#01
value3
External Start Function triggered by Event 1
#10
value4
External Start Function triggered by Event 2
#11
TCE
Timer Concatenation Enable
20
read-write
value1
Timer concatenation is disabled
#0
value2
Timer concatenation is enabled
#1
TS
Trap Function Selector
17
read-write
value1
Trap function disabled
#0
value2
TRAP function connected to Event 2
#1
UDS
External Up/Down Functionality Selector
10
1
read-write
value1
External Up/Down Function deactivated
#00
value2
External Up/Down Function triggered by Event 0
#01
value3
External Up/Down Function triggered by Event 1
#10
value4
External Up/Down Function triggered by Event 2
#11
CR
Timer Compare Value
0x38
32
read-write
n
0x0
0x0
CR
Compare Register
0
15
read-only
CRS
Timer Shadow Compare Value
0x3C
32
read-write
n
0x0
0x0
CRS
Compare Register
0
15
read-write
DIT
Dither Config
0x1C
32
read-write
n
0x0
0x0
DCNT
Dither counter actual value
8
3
read-only
DCV
Dither compare Value
0
3
read-only
DITS
Dither Shadow Register
0x20
32
read-write
n
0x0
0x0
DCVS
Dither Shadow Compare Value
0
3
read-write
ECRD0
Extended Read Back 0
0xB8
32
read-write
n
0x0
0x0
modifyExternal
CAPV
Timer Capture Value
0
15
read-only
FFL
Full Flag
24
read-only
value1
No new value was captured into this register
#0
value2
A new value has been captured into this register
#1
FPCV
Prescaler Capture value
16
3
read-only
LCV
Lost Capture Value
25
read-only
value1
No capture was lost
#0
value2
A capture was lost
#1
SPTR
Slice pointer
20
1
read-only
value1
CC40
#00
value2
CC41
#01
value3
CC42
#10
value4
CC43
#11
VPTR
Capture register pointer
22
1
read-only
value1
Capture register 0
#00
value2
Capture register 1
#01
value3
Capture register 2
#10
value4
Capture register 3
#11
ECRD1
Extended Read Back 1
0xBC
32
read-write
n
0x0
0x0
modifyExternal
CAPV
Timer Capture Value
0
15
read-only
FFL
Full Flag
24
read-only
value1
No new value was captured into this register
#0
value2
A new value has been captured into this register
#1
FPCV
Prescaler Capture value
16
3
read-only
LCV
Lost Capture Value
25
read-only
value1
No capture was lost
#0
value2
A capture was lost
#1
SPTR
Slice pointer
20
1
read-only
value1
CC40
#00
value2
CC41
#01
value3
CC42
#10
value4
CC43
#11
VPTR
Capture register pointer
22
1
read-only
value1
Capture register 0
#00
value2
Capture register 1
#01
value3
Capture register 2
#10
value4
Capture register 3
#11
FPC
Floating Prescaler Control
0x28
32
read-write
n
0x0
0x0
PCMP
Floating Prescaler Compare Value
0
3
read-only
PVAL
Actual Prescaler Value
8
3
read-write
FPCS
Floating Prescaler Shadow
0x2C
32
read-write
n
0x0
0x0
PCMP
Floating Prescaler Shadow Compare Value
0
3
read-write
INS
Input Selector Configuration
0x0
32
read-write
n
0x0
0x0
EV0EM
Event 0 Edge Selection
16
1
read-write
value1
No action
#00
value2
Signal active on rising edge
#01
value3
Signal active on falling edge
#10
value4
Signal active on both edges
#11
EV0IS
Event 0 signal selection
0
3
read-write
value1
CCU4x.INyA
#0000
value2
CCU4x.INyB
#0001
value3
CCU4x.INyC
#0010
value4
CCU4x.INyD
#0011
value5
CCU4x.INyE
#0100
value6
CCU4x.INyF
#0101
value7
CCU4x.INyG
#0110
value8
CCU4x.INyH
#0111
value9
CCU4x.INyI
#1000
value10
CCU4x.INyJ
#1001
value11
CCU4x.INyK
#1010
value12
CCU4x.INyL
#1011
value13
CCU4x.INyM
#1100
value14
CCU4x.INyN
#1101
value15
CCU4x.INyO
#1110
value16
CCU4x.INyP
#1111
EV0LM
Event 0 Level Selection
22
read-write
value1
Active on HIGH level
#0
value2
Active on LOW level
#1
EV1EM
Event 1 Edge Selection
18
1
read-write
value1
No action
#00
value2
Signal active on rising edge
#01
value3
Signal active on falling edge
#10
value4
Signal active on both edges
#11
EV1IS
Event 1 signal selection
4
3
read-write
value1
CCU4x.INyA
#0000
value2
CCU4x.INyB
#0001
value3
CCU4x.INyC
#0010
value4
CCU4x.INyD
#0011
value5
CCU4x.INyE
#0100
value6
CCU4x.INyF
#0101
value7
CCU4x.INyG
#0110
value8
CCU4x.INyH
#0111
value9
CCU4x.INyI
#1000
value10
CCU4x.INyJ
#1001
value11
CCU4x.INyK
#1010
value12
CCU4x.INyL
#1011
value13
CCU4x.INyM
#1100
value14
CCU4x.INyN
#1101
value15
CCU4x.INyO
#1110
value16
CCU4x.INyP
#1111
EV1LM
Event 1 Level Selection
23
read-write
value1
Active on HIGH level
#0
value2
Active on LOW level
#1
EV2EM
Event 2 Edge Selection
20
1
read-write
value1
No action
#00
value2
Signal active on rising edge
#01
value3
Signal active on falling edge
#10
value4
Signal active on both edges
#11
EV2IS
Event 2 signal selection
8
3
read-write
value1
CCU4x.INyA
#0000
value2
CCU4x.INyB
#0001
value3
CCU4x.INyC
#0010
value4
CCU4x.INyD
#0011
value5
CCU4x.INyE
#0100
value6
CCU4x.INyF
#0101
value7
CCU4x.INyG
#0110
value8
CCU4x.INyH
#0111
value9
CCU4x.INyI
#1000
value10
CCU4x.INyJ
#1001
value11
CCU4x.INyK
#1010
value12
CCU4x.INyL
#1011
value13
CCU4x.INyM
#1100
value14
CCU4x.INyN
#1101
value15
CCU4x.INyO
#1110
value16
CCU4x.INyP
#1111
EV2LM
Event 2 Level Selection
24
read-write
value1
Active on HIGH level
#0
value2
Active on LOW level
#1
LPF0M
Event 0 Low Pass Filter Configuration
25
1
read-write
value1
LPF is disabled
#00
value2
3 clock cycles of fCCU4
#01
value3
5 clock cycles of fCCU4
#10
value4
7 clock cycles of fCCU4
#11
LPF1M
Event 1 Low Pass Filter Configuration
27
1
read-write
value1
LPF is disabled
#00
value2
3 clock cycles of fCCU4
#01
value3
5 clock cycles of fCCU4
#10
value4
7 clock cycles of fCCU4
#11
LPF2M
Event 2 Low Pass Filter Configuration
29
1
read-write
value1
LPF is disabled
#00
value2
3 clock cycles of fCCU4
#01
value3
5 clock cycles of fCCU4
#10
value4
7 clock cycles of fCCU4
#11
INTE
Interrupt Enable Control
0xA4
32
read-write
n
0x0
0x0
CMDE
Compare match while counting down enable
3
read-write
value1
Compare Match while counting down interrupt is disabled
#0
value2
Compare Match while counting down interrupt is enabled
#1
CMUE
Compare match while counting up enable
2
read-write
value1
Compare Match while counting up interrupt is disabled
#0
value2
Compare Match while counting up interrupt is enabled
#1
E0AE
Event 0 interrupt enable
8
read-write
value1
Event 0 detection interrupt is disabled
#0
value2
Event 0 detection interrupt is enabled
#1
E1AE
Event 1 interrupt enable
9
read-write
value1
Event 1 detection interrupt is disabled
#0
value2
Event 1 detection interrupt is enabled
#1
E2AE
Event 2 interrupt enable
10
read-write
value1
Event 2 detection interrupt is disabled
#0
value2
Event 2 detection interrupt is enabled
#1
OME
One match while counting down enable
1
read-write
value1
One Match interrupt is disabled
#0
value2
One Match interrupt is enabled
#1
PME
Period match while counting up enable
0
read-write
value1
Period Match interrupt is disabled
#0
value2
Period Match interrupt is enabled
#1
INTS
Interrupt Status
0xA0
32
read-write
n
0x0
0x0
CMDS
Compare Match while Counting Down
3
read-only
value1
Compare match while counting down not detected
#0
value2
Compare match while counting down detected
#1
CMUS
Compare Match while Counting Up
2
read-only
value1
Compare match while counting up not detected
#0
value2
Compare match while counting up detected
#1
E0AS
Event 0 Detection Status
8
read-only
value1
Event 0 not detected
#0
value2
Event 0 detected
#1
E1AS
Event 1 Detection Status
9
read-only
value1
Event 1 not detected
#0
value2
Event 1 detected
#1
E2AS
Event 2 Detection Status
10
read-only
value1
Event 2 not detected
#0
value2
Event 2 detected
#1
OMDS
One Match while Counting Down
1
read-only
value1
One match while counting down not detected
#0
value2
One match while counting down detected
#1
PMUS
Period Match while Counting Up
0
read-only
value1
Period match while counting up not detected
#0
value2
Period match while counting up detected
#1
TRPF
Trap Flag Status
11
read-only
PR
Timer Period Value
0x30
32
read-write
n
0x0
0x0
PR
Period Register
0
15
read-only
PRS
Timer Shadow Period Value
0x34
32
read-write
n
0x0
0x0
PRS
Period Register
0
15
read-write
PSC
Prescaler Control
0x24
32
read-write
n
0x0
0x0
PSIV
Prescaler Initial Value
0
3
read-write
PSL
Passive Level Config
0x18
32
read-write
n
0x0
0x0
PSL
Output Passive Level
0
read-write
value1
Passive Level is LOW
#0
value2
Passive Level is HIGH
#1
SRS
Service Request Selector
0xA8
32
read-write
n
0x0
0x0
CMSR
Compare match Service request selector
2
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
E0SR
Event 0 Service request selector
8
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
E1SR
Event 1 Service request selector
10
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
E2SR
Event 2 Service request selector
12
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
POSR
Period/One match Service request selector
0
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
SWR
Interrupt Status Clear
0xB0
32
read-write
n
0x0
0x0
RCMD
Compare match while counting down clear
3
write-only
RCMU
Compare match while counting up clear
2
write-only
RE0A
Event 0 detection clear
8
write-only
RE1A
Event 1 detection clear
9
write-only
RE2A
Event 2 detection clear
10
write-only
ROM
One match while counting down clear
1
write-only
RPM
Period match while counting up clear
0
write-only
RTRPF
Trap Flag status clear
11
write-only
SWS
Interrupt Status Set
0xAC
32
read-write
n
0x0
0x0
SCMD
Compare match while counting down set
3
write-only
SCMU
Compare match while counting up set
2
write-only
SE0A
Event 0 detection set
8
write-only
SE1A
Event 1 detection set
9
write-only
SE2A
Event 2 detection set
10
write-only
SOM
One match while counting down set
1
write-only
SPM
Period match while counting up set
0
write-only
STRPF
Trap Flag status set
11
write-only
TC
Slice Timer Control
0x14
32
read-write
n
0x0
0x0
CAPC
Clear on Capture Control
5
1
read-write
value1
Timer is never cleared on a capture event
#00
value2
Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event)
#01
value3
Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event)
#10
value4
Timer is always cleared in a capture event.
#11
CCS
Continuous Capture Enable
12
read-write
value1
The capture into a specific capture register is done with the rules linked with the full flags, described at .
#0
value2
The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back).
#1
CLST
Shadow Transfer on Clear
2
read-write
CMOD
Capture Compare Mode
3
read-only
value1
Compare Mode
#0
value2
Capture Mode
#1
DIM
Dither input selector
15
read-write
value1
Slice is using its own dither unit
#0
value2
Slice is connected to the dither unit of slice 0.
#1
DITHE
Dither Enable
13
1
read-write
value1
Dither is disabled
#00
value2
Dither is applied to the Period
#01
value3
Dither is applied to the Compare
#10
value4
Dither is applied to the Period and Compare
#11
ECM
Extended Capture Mode
4
read-write
value1
Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only.
#0
value2
Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the ECRD.VPTR is cleared.
#1
EMS
External Modulation Synchronization
23
read-write
value1
External Modulation functionality is not synchronized with the PWM signal
#0
value2
External Modulation functionality is synchronized with the PWM signal
#1
EMT
External Modulation Type
24
read-write
value1
External Modulation functionality is clearing the CC4yST bit.
#0
value2
External Modulation functionality is gating the outputs.
#1
ENDM
Extended Stop Function Control
8
1
read-write
value1
Clears the timer run bit only (default stop)
#00
value2
Clears the timer only (flush)
#01
value3
Clears the timer and run bit (flush/stop)
#10
FPE
Floating Prescaler enable
16
read-write
value1
Floating prescaler mode is disabled
#0
value2
Floating prescaler mode is enabled
#1
MCME
Multi Channel Mode Enable
25
read-write
value1
Multi Channel Mode is disabled
#0
value2
Multi Channel Mode is enabled
#1
SCE
Equal Capture Event enable
11
read-write
value1
Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1
#0
value2
Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. and CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1
#1
STRM
Extended Start Function Control
10
read-write
value1
Sets run bit only (default start)
#0
value2
Clears the timer and sets run bit (flush/start)
#1
TCM
Timer Counting Mode
0
read-write
value1
Edge aligned mode
#0
value2
Center aligned mode
#1
TRAPE
TRAP enable
17
read-write
value1
TRAP functionality has no effect on the output
#0
value2
TRAP functionality affects the output
#1
TRPSE
TRAP Synchronization Enable
21
read-write
value1
Exiting from TRAP state isn't synchronized with the PWM signal
#0
value2
Exiting from TRAP state is synchronized with the PWM signal
#1
TRPSW
TRAP State Clear Control
22
read-write
value1
The slice exits the TRAP state automatically when the TRAP condition is not present
#0
value2
The TRAP state can only be exited by a SW request.
#1
TSSM
Timer Single Shot Mode
1
read-write
value1
Single shot mode is disabled
#0
value2
Single shot mode is enabled
#1
TCCLR
Slice Timer Clear
0x10
32
read-write
n
0x0
0x0
DITC
Dither Counter Clear
2
write-only
TCC
Timer Clear
1
write-only
TRBC
Timer Run Bit Clear
0
write-only
TCSET
Slice Timer Run Set
0xC
32
read-write
n
0x0
0x0
TRBS
Timer Run Bit set
0
write-only
TCST
Slice Timer Status
0x8
32
read-write
n
0x0
0x0
CDIR
Timer Counting Direction
1
read-only
value1
Timer is counting up
#0
value2
Timer is counting down
#1
TRB
Timer Run Bit
0
read-only
value1
Timer is stopped
#0
value2
Timer is running
#1
TIMER
Timer Value
0x70
32
read-write
n
0x0
0x0
TVAL
Timer Value
0
15
read-write
CCU40_CC42
Capture Compare Unit 4 - Unit 0
CCU4
0x0
0x0
0x100
registers
n
C0V
Capture Register 0
0x74
32
read-write
n
0x0
0x0
modifyExternal
CAPTV
Capture Value
0
15
read-only
FFL
Full Flag
20
read-only
value1
No new value was captured into the specific capture register
#0
value2
A new value was captured into the specific register
#1
FPCV
Prescaler Value
16
3
read-only
C1V
Capture Register 1
0x78
32
read-write
n
0x0
0x0
modifyExternal
CAPTV
Capture Value
0
15
read-only
FFL
Full Flag
20
read-only
value1
No new value was captured into the specific capture register
#0
value2
A new value was captured into the specific register
#1
FPCV
Prescaler Value
16
3
read-only
C2V
Capture Register 2
0x7C
32
read-write
n
0x0
0x0
modifyExternal
CAPTV
Capture Value
0
15
read-only
FFL
Full Flag
20
read-only
value1
No new value was captured into the specific capture register
#0
value2
A new value was captured into the specific register
#1
FPCV
Prescaler Value
16
3
read-only
C3V
Capture Register 3
0x80
32
read-write
n
0x0
0x0
modifyExternal
CAPTV
Capture Value
0
15
read-only
FFL
Full Flag
20
read-only
value1
No new value was captured into the specific capture register
#0
value2
A new value was captured into the specific register
#1
FPCV
Prescaler Value
16
3
read-only
CMC
Connection Matrix Control
0x4
32
read-write
n
0x0
0x0
CAP0S
External Capture 0 Functionality Selector
4
1
read-write
value1
External Capture 0 Function deactivated
#00
value2
External Capture 0 Function triggered by Event 0
#01
value3
External Capture 0 Function triggered by Event 1
#10
value4
External Capture 0 Function triggered by Event 2
#11
CAP1S
External Capture 1 Functionality Selector
6
1
read-write
value1
External Capture 1 Function deactivated
#00
value2
External Capture 1 Function triggered by Event 0
#01
value3
External Capture 1 Function triggered by Event 1
#10
value4
External Capture 1 Function triggered by Event 2
#11
CNTS
External Count Selector
14
1
read-write
value1
External Count Function deactivated
#00
value2
External Count Function triggered by Event 0
#01
value3
External Count Function triggered by Event 1
#10
value4
External Count Function triggered by Event 2
#11
ENDS
External Stop Functionality Selector
2
1
read-write
value1
External Stop Function deactivated
#00
value2
External Stop Function triggered by Event 0
#01
value3
External Stop Function triggered by Event 1
#10
value4
External Stop Function triggered by Event 2
#11
GATES
External Gate Functionality Selector
8
1
read-write
value1
External Gating Function deactivated
#00
value2
External Gating Function triggered by Event 0
#01
value3
External Gating Function triggered by Event 1
#10
value4
External Gating Function triggered by Event 2
#11
LDS
External Timer Load Functionality Selector
12
1
read-write
MOS
External Modulation Functionality Selector
18
1
read-write
OFS
Override Function Selector
16
read-write
value1
Override functionality disabled
#0
value2
Status bit trigger override connected to Event 1; Status bit value override connected to Event 2
#1
STRTS
External Start Functionality Selector
0
1
read-write
value1
External Start Function deactivated
#00
value2
External Start Function triggered by Event 0
#01
value3
External Start Function triggered by Event 1
#10
value4
External Start Function triggered by Event 2
#11
TCE
Timer Concatenation Enable
20
read-write
value1
Timer concatenation is disabled
#0
value2
Timer concatenation is enabled
#1
TS
Trap Function Selector
17
read-write
value1
Trap function disabled
#0
value2
TRAP function connected to Event 2
#1
UDS
External Up/Down Functionality Selector
10
1
read-write
value1
External Up/Down Function deactivated
#00
value2
External Up/Down Function triggered by Event 0
#01
value3
External Up/Down Function triggered by Event 1
#10
value4
External Up/Down Function triggered by Event 2
#11
CR
Timer Compare Value
0x38
32
read-write
n
0x0
0x0
CR
Compare Register
0
15
read-only
CRS
Timer Shadow Compare Value
0x3C
32
read-write
n
0x0
0x0
CRS
Compare Register
0
15
read-write
DIT
Dither Config
0x1C
32
read-write
n
0x0
0x0
DCNT
Dither counter actual value
8
3
read-only
DCV
Dither compare Value
0
3
read-only
DITS
Dither Shadow Register
0x20
32
read-write
n
0x0
0x0
DCVS
Dither Shadow Compare Value
0
3
read-write
ECRD0
Extended Read Back 0
0xB8
32
read-write
n
0x0
0x0
modifyExternal
CAPV
Timer Capture Value
0
15
read-only
FFL
Full Flag
24
read-only
value1
No new value was captured into this register
#0
value2
A new value has been captured into this register
#1
FPCV
Prescaler Capture value
16
3
read-only
LCV
Lost Capture Value
25
read-only
value1
No capture was lost
#0
value2
A capture was lost
#1
SPTR
Slice pointer
20
1
read-only
value1
CC40
#00
value2
CC41
#01
value3
CC42
#10
value4
CC43
#11
VPTR
Capture register pointer
22
1
read-only
value1
Capture register 0
#00
value2
Capture register 1
#01
value3
Capture register 2
#10
value4
Capture register 3
#11
ECRD1
Extended Read Back 1
0xBC
32
read-write
n
0x0
0x0
modifyExternal
CAPV
Timer Capture Value
0
15
read-only
FFL
Full Flag
24
read-only
value1
No new value was captured into this register
#0
value2
A new value has been captured into this register
#1
FPCV
Prescaler Capture value
16
3
read-only
LCV
Lost Capture Value
25
read-only
value1
No capture was lost
#0
value2
A capture was lost
#1
SPTR
Slice pointer
20
1
read-only
value1
CC40
#00
value2
CC41
#01
value3
CC42
#10
value4
CC43
#11
VPTR
Capture register pointer
22
1
read-only
value1
Capture register 0
#00
value2
Capture register 1
#01
value3
Capture register 2
#10
value4
Capture register 3
#11
FPC
Floating Prescaler Control
0x28
32
read-write
n
0x0
0x0
PCMP
Floating Prescaler Compare Value
0
3
read-only
PVAL
Actual Prescaler Value
8
3
read-write
FPCS
Floating Prescaler Shadow
0x2C
32
read-write
n
0x0
0x0
PCMP
Floating Prescaler Shadow Compare Value
0
3
read-write
INS
Input Selector Configuration
0x0
32
read-write
n
0x0
0x0
EV0EM
Event 0 Edge Selection
16
1
read-write
value1
No action
#00
value2
Signal active on rising edge
#01
value3
Signal active on falling edge
#10
value4
Signal active on both edges
#11
EV0IS
Event 0 signal selection
0
3
read-write
value1
CCU4x.INyA
#0000
value2
CCU4x.INyB
#0001
value3
CCU4x.INyC
#0010
value4
CCU4x.INyD
#0011
value5
CCU4x.INyE
#0100
value6
CCU4x.INyF
#0101
value7
CCU4x.INyG
#0110
value8
CCU4x.INyH
#0111
value9
CCU4x.INyI
#1000
value10
CCU4x.INyJ
#1001
value11
CCU4x.INyK
#1010
value12
CCU4x.INyL
#1011
value13
CCU4x.INyM
#1100
value14
CCU4x.INyN
#1101
value15
CCU4x.INyO
#1110
value16
CCU4x.INyP
#1111
EV0LM
Event 0 Level Selection
22
read-write
value1
Active on HIGH level
#0
value2
Active on LOW level
#1
EV1EM
Event 1 Edge Selection
18
1
read-write
value1
No action
#00
value2
Signal active on rising edge
#01
value3
Signal active on falling edge
#10
value4
Signal active on both edges
#11
EV1IS
Event 1 signal selection
4
3
read-write
value1
CCU4x.INyA
#0000
value2
CCU4x.INyB
#0001
value3
CCU4x.INyC
#0010
value4
CCU4x.INyD
#0011
value5
CCU4x.INyE
#0100
value6
CCU4x.INyF
#0101
value7
CCU4x.INyG
#0110
value8
CCU4x.INyH
#0111
value9
CCU4x.INyI
#1000
value10
CCU4x.INyJ
#1001
value11
CCU4x.INyK
#1010
value12
CCU4x.INyL
#1011
value13
CCU4x.INyM
#1100
value14
CCU4x.INyN
#1101
value15
CCU4x.INyO
#1110
value16
CCU4x.INyP
#1111
EV1LM
Event 1 Level Selection
23
read-write
value1
Active on HIGH level
#0
value2
Active on LOW level
#1
EV2EM
Event 2 Edge Selection
20
1
read-write
value1
No action
#00
value2
Signal active on rising edge
#01
value3
Signal active on falling edge
#10
value4
Signal active on both edges
#11
EV2IS
Event 2 signal selection
8
3
read-write
value1
CCU4x.INyA
#0000
value2
CCU4x.INyB
#0001
value3
CCU4x.INyC
#0010
value4
CCU4x.INyD
#0011
value5
CCU4x.INyE
#0100
value6
CCU4x.INyF
#0101
value7
CCU4x.INyG
#0110
value8
CCU4x.INyH
#0111
value9
CCU4x.INyI
#1000
value10
CCU4x.INyJ
#1001
value11
CCU4x.INyK
#1010
value12
CCU4x.INyL
#1011
value13
CCU4x.INyM
#1100
value14
CCU4x.INyN
#1101
value15
CCU4x.INyO
#1110
value16
CCU4x.INyP
#1111
EV2LM
Event 2 Level Selection
24
read-write
value1
Active on HIGH level
#0
value2
Active on LOW level
#1
LPF0M
Event 0 Low Pass Filter Configuration
25
1
read-write
value1
LPF is disabled
#00
value2
3 clock cycles of fCCU4
#01
value3
5 clock cycles of fCCU4
#10
value4
7 clock cycles of fCCU4
#11
LPF1M
Event 1 Low Pass Filter Configuration
27
1
read-write
value1
LPF is disabled
#00
value2
3 clock cycles of fCCU4
#01
value3
5 clock cycles of fCCU4
#10
value4
7 clock cycles of fCCU4
#11
LPF2M
Event 2 Low Pass Filter Configuration
29
1
read-write
value1
LPF is disabled
#00
value2
3 clock cycles of fCCU4
#01
value3
5 clock cycles of fCCU4
#10
value4
7 clock cycles of fCCU4
#11
INTE
Interrupt Enable Control
0xA4
32
read-write
n
0x0
0x0
CMDE
Compare match while counting down enable
3
read-write
value1
Compare Match while counting down interrupt is disabled
#0
value2
Compare Match while counting down interrupt is enabled
#1
CMUE
Compare match while counting up enable
2
read-write
value1
Compare Match while counting up interrupt is disabled
#0
value2
Compare Match while counting up interrupt is enabled
#1
E0AE
Event 0 interrupt enable
8
read-write
value1
Event 0 detection interrupt is disabled
#0
value2
Event 0 detection interrupt is enabled
#1
E1AE
Event 1 interrupt enable
9
read-write
value1
Event 1 detection interrupt is disabled
#0
value2
Event 1 detection interrupt is enabled
#1
E2AE
Event 2 interrupt enable
10
read-write
value1
Event 2 detection interrupt is disabled
#0
value2
Event 2 detection interrupt is enabled
#1
OME
One match while counting down enable
1
read-write
value1
One Match interrupt is disabled
#0
value2
One Match interrupt is enabled
#1
PME
Period match while counting up enable
0
read-write
value1
Period Match interrupt is disabled
#0
value2
Period Match interrupt is enabled
#1
INTS
Interrupt Status
0xA0
32
read-write
n
0x0
0x0
CMDS
Compare Match while Counting Down
3
read-only
value1
Compare match while counting down not detected
#0
value2
Compare match while counting down detected
#1
CMUS
Compare Match while Counting Up
2
read-only
value1
Compare match while counting up not detected
#0
value2
Compare match while counting up detected
#1
E0AS
Event 0 Detection Status
8
read-only
value1
Event 0 not detected
#0
value2
Event 0 detected
#1
E1AS
Event 1 Detection Status
9
read-only
value1
Event 1 not detected
#0
value2
Event 1 detected
#1
E2AS
Event 2 Detection Status
10
read-only
value1
Event 2 not detected
#0
value2
Event 2 detected
#1
OMDS
One Match while Counting Down
1
read-only
value1
One match while counting down not detected
#0
value2
One match while counting down detected
#1
PMUS
Period Match while Counting Up
0
read-only
value1
Period match while counting up not detected
#0
value2
Period match while counting up detected
#1
TRPF
Trap Flag Status
11
read-only
PR
Timer Period Value
0x30
32
read-write
n
0x0
0x0
PR
Period Register
0
15
read-only
PRS
Timer Shadow Period Value
0x34
32
read-write
n
0x0
0x0
PRS
Period Register
0
15
read-write
PSC
Prescaler Control
0x24
32
read-write
n
0x0
0x0
PSIV
Prescaler Initial Value
0
3
read-write
PSL
Passive Level Config
0x18
32
read-write
n
0x0
0x0
PSL
Output Passive Level
0
read-write
value1
Passive Level is LOW
#0
value2
Passive Level is HIGH
#1
SRS
Service Request Selector
0xA8
32
read-write
n
0x0
0x0
CMSR
Compare match Service request selector
2
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
E0SR
Event 0 Service request selector
8
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
E1SR
Event 1 Service request selector
10
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
E2SR
Event 2 Service request selector
12
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
POSR
Period/One match Service request selector
0
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
SWR
Interrupt Status Clear
0xB0
32
read-write
n
0x0
0x0
RCMD
Compare match while counting down clear
3
write-only
RCMU
Compare match while counting up clear
2
write-only
RE0A
Event 0 detection clear
8
write-only
RE1A
Event 1 detection clear
9
write-only
RE2A
Event 2 detection clear
10
write-only
ROM
One match while counting down clear
1
write-only
RPM
Period match while counting up clear
0
write-only
RTRPF
Trap Flag status clear
11
write-only
SWS
Interrupt Status Set
0xAC
32
read-write
n
0x0
0x0
SCMD
Compare match while counting down set
3
write-only
SCMU
Compare match while counting up set
2
write-only
SE0A
Event 0 detection set
8
write-only
SE1A
Event 1 detection set
9
write-only
SE2A
Event 2 detection set
10
write-only
SOM
One match while counting down set
1
write-only
SPM
Period match while counting up set
0
write-only
STRPF
Trap Flag status set
11
write-only
TC
Slice Timer Control
0x14
32
read-write
n
0x0
0x0
CAPC
Clear on Capture Control
5
1
read-write
value1
Timer is never cleared on a capture event
#00
value2
Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event)
#01
value3
Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event)
#10
value4
Timer is always cleared in a capture event.
#11
CCS
Continuous Capture Enable
12
read-write
value1
The capture into a specific capture register is done with the rules linked with the full flags, described at .
#0
value2
The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back).
#1
CLST
Shadow Transfer on Clear
2
read-write
CMOD
Capture Compare Mode
3
read-only
value1
Compare Mode
#0
value2
Capture Mode
#1
DIM
Dither input selector
15
read-write
value1
Slice is using its own dither unit
#0
value2
Slice is connected to the dither unit of slice 0.
#1
DITHE
Dither Enable
13
1
read-write
value1
Dither is disabled
#00
value2
Dither is applied to the Period
#01
value3
Dither is applied to the Compare
#10
value4
Dither is applied to the Period and Compare
#11
ECM
Extended Capture Mode
4
read-write
value1
Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only.
#0
value2
Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the ECRD.VPTR is cleared.
#1
EMS
External Modulation Synchronization
23
read-write
value1
External Modulation functionality is not synchronized with the PWM signal
#0
value2
External Modulation functionality is synchronized with the PWM signal
#1
EMT
External Modulation Type
24
read-write
value1
External Modulation functionality is clearing the CC4yST bit.
#0
value2
External Modulation functionality is gating the outputs.
#1
ENDM
Extended Stop Function Control
8
1
read-write
value1
Clears the timer run bit only (default stop)
#00
value2
Clears the timer only (flush)
#01
value3
Clears the timer and run bit (flush/stop)
#10
FPE
Floating Prescaler enable
16
read-write
value1
Floating prescaler mode is disabled
#0
value2
Floating prescaler mode is enabled
#1
MCME
Multi Channel Mode Enable
25
read-write
value1
Multi Channel Mode is disabled
#0
value2
Multi Channel Mode is enabled
#1
SCE
Equal Capture Event enable
11
read-write
value1
Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1
#0
value2
Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. and CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1
#1
STRM
Extended Start Function Control
10
read-write
value1
Sets run bit only (default start)
#0
value2
Clears the timer and sets run bit (flush/start)
#1
TCM
Timer Counting Mode
0
read-write
value1
Edge aligned mode
#0
value2
Center aligned mode
#1
TRAPE
TRAP enable
17
read-write
value1
TRAP functionality has no effect on the output
#0
value2
TRAP functionality affects the output
#1
TRPSE
TRAP Synchronization Enable
21
read-write
value1
Exiting from TRAP state isn't synchronized with the PWM signal
#0
value2
Exiting from TRAP state is synchronized with the PWM signal
#1
TRPSW
TRAP State Clear Control
22
read-write
value1
The slice exits the TRAP state automatically when the TRAP condition is not present
#0
value2
The TRAP state can only be exited by a SW request.
#1
TSSM
Timer Single Shot Mode
1
read-write
value1
Single shot mode is disabled
#0
value2
Single shot mode is enabled
#1
TCCLR
Slice Timer Clear
0x10
32
read-write
n
0x0
0x0
DITC
Dither Counter Clear
2
write-only
TCC
Timer Clear
1
write-only
TRBC
Timer Run Bit Clear
0
write-only
TCSET
Slice Timer Run Set
0xC
32
read-write
n
0x0
0x0
TRBS
Timer Run Bit set
0
write-only
TCST
Slice Timer Status
0x8
32
read-write
n
0x0
0x0
CDIR
Timer Counting Direction
1
read-only
value1
Timer is counting up
#0
value2
Timer is counting down
#1
TRB
Timer Run Bit
0
read-only
value1
Timer is stopped
#0
value2
Timer is running
#1
TIMER
Timer Value
0x70
32
read-write
n
0x0
0x0
TVAL
Timer Value
0
15
read-write
CCU40_CC43
Capture Compare Unit 4 - Unit 0
CCU4
0x0
0x0
0x100
registers
n
C0V
Capture Register 0
0x74
32
read-write
n
0x0
0x0
modifyExternal
CAPTV
Capture Value
0
15
read-only
FFL
Full Flag
20
read-only
value1
No new value was captured into the specific capture register
#0
value2
A new value was captured into the specific register
#1
FPCV
Prescaler Value
16
3
read-only
C1V
Capture Register 1
0x78
32
read-write
n
0x0
0x0
modifyExternal
CAPTV
Capture Value
0
15
read-only
FFL
Full Flag
20
read-only
value1
No new value was captured into the specific capture register
#0
value2
A new value was captured into the specific register
#1
FPCV
Prescaler Value
16
3
read-only
C2V
Capture Register 2
0x7C
32
read-write
n
0x0
0x0
modifyExternal
CAPTV
Capture Value
0
15
read-only
FFL
Full Flag
20
read-only
value1
No new value was captured into the specific capture register
#0
value2
A new value was captured into the specific register
#1
FPCV
Prescaler Value
16
3
read-only
C3V
Capture Register 3
0x80
32
read-write
n
0x0
0x0
modifyExternal
CAPTV
Capture Value
0
15
read-only
FFL
Full Flag
20
read-only
value1
No new value was captured into the specific capture register
#0
value2
A new value was captured into the specific register
#1
FPCV
Prescaler Value
16
3
read-only
CMC
Connection Matrix Control
0x4
32
read-write
n
0x0
0x0
CAP0S
External Capture 0 Functionality Selector
4
1
read-write
value1
External Capture 0 Function deactivated
#00
value2
External Capture 0 Function triggered by Event 0
#01
value3
External Capture 0 Function triggered by Event 1
#10
value4
External Capture 0 Function triggered by Event 2
#11
CAP1S
External Capture 1 Functionality Selector
6
1
read-write
value1
External Capture 1 Function deactivated
#00
value2
External Capture 1 Function triggered by Event 0
#01
value3
External Capture 1 Function triggered by Event 1
#10
value4
External Capture 1 Function triggered by Event 2
#11
CNTS
External Count Selector
14
1
read-write
value1
External Count Function deactivated
#00
value2
External Count Function triggered by Event 0
#01
value3
External Count Function triggered by Event 1
#10
value4
External Count Function triggered by Event 2
#11
ENDS
External Stop Functionality Selector
2
1
read-write
value1
External Stop Function deactivated
#00
value2
External Stop Function triggered by Event 0
#01
value3
External Stop Function triggered by Event 1
#10
value4
External Stop Function triggered by Event 2
#11
GATES
External Gate Functionality Selector
8
1
read-write
value1
External Gating Function deactivated
#00
value2
External Gating Function triggered by Event 0
#01
value3
External Gating Function triggered by Event 1
#10
value4
External Gating Function triggered by Event 2
#11
LDS
External Timer Load Functionality Selector
12
1
read-write
MOS
External Modulation Functionality Selector
18
1
read-write
OFS
Override Function Selector
16
read-write
value1
Override functionality disabled
#0
value2
Status bit trigger override connected to Event 1; Status bit value override connected to Event 2
#1
STRTS
External Start Functionality Selector
0
1
read-write
value1
External Start Function deactivated
#00
value2
External Start Function triggered by Event 0
#01
value3
External Start Function triggered by Event 1
#10
value4
External Start Function triggered by Event 2
#11
TCE
Timer Concatenation Enable
20
read-write
value1
Timer concatenation is disabled
#0
value2
Timer concatenation is enabled
#1
TS
Trap Function Selector
17
read-write
value1
Trap function disabled
#0
value2
TRAP function connected to Event 2
#1
UDS
External Up/Down Functionality Selector
10
1
read-write
value1
External Up/Down Function deactivated
#00
value2
External Up/Down Function triggered by Event 0
#01
value3
External Up/Down Function triggered by Event 1
#10
value4
External Up/Down Function triggered by Event 2
#11
CR
Timer Compare Value
0x38
32
read-write
n
0x0
0x0
CR
Compare Register
0
15
read-only
CRS
Timer Shadow Compare Value
0x3C
32
read-write
n
0x0
0x0
CRS
Compare Register
0
15
read-write
DIT
Dither Config
0x1C
32
read-write
n
0x0
0x0
DCNT
Dither counter actual value
8
3
read-only
DCV
Dither compare Value
0
3
read-only
DITS
Dither Shadow Register
0x20
32
read-write
n
0x0
0x0
DCVS
Dither Shadow Compare Value
0
3
read-write
ECRD0
Extended Read Back 0
0xB8
32
read-write
n
0x0
0x0
modifyExternal
CAPV
Timer Capture Value
0
15
read-only
FFL
Full Flag
24
read-only
value1
No new value was captured into this register
#0
value2
A new value has been captured into this register
#1
FPCV
Prescaler Capture value
16
3
read-only
LCV
Lost Capture Value
25
read-only
value1
No capture was lost
#0
value2
A capture was lost
#1
SPTR
Slice pointer
20
1
read-only
value1
CC40
#00
value2
CC41
#01
value3
CC42
#10
value4
CC43
#11
VPTR
Capture register pointer
22
1
read-only
value1
Capture register 0
#00
value2
Capture register 1
#01
value3
Capture register 2
#10
value4
Capture register 3
#11
ECRD1
Extended Read Back 1
0xBC
32
read-write
n
0x0
0x0
modifyExternal
CAPV
Timer Capture Value
0
15
read-only
FFL
Full Flag
24
read-only
value1
No new value was captured into this register
#0
value2
A new value has been captured into this register
#1
FPCV
Prescaler Capture value
16
3
read-only
LCV
Lost Capture Value
25
read-only
value1
No capture was lost
#0
value2
A capture was lost
#1
SPTR
Slice pointer
20
1
read-only
value1
CC40
#00
value2
CC41
#01
value3
CC42
#10
value4
CC43
#11
VPTR
Capture register pointer
22
1
read-only
value1
Capture register 0
#00
value2
Capture register 1
#01
value3
Capture register 2
#10
value4
Capture register 3
#11
FPC
Floating Prescaler Control
0x28
32
read-write
n
0x0
0x0
PCMP
Floating Prescaler Compare Value
0
3
read-only
PVAL
Actual Prescaler Value
8
3
read-write
FPCS
Floating Prescaler Shadow
0x2C
32
read-write
n
0x0
0x0
PCMP
Floating Prescaler Shadow Compare Value
0
3
read-write
INS
Input Selector Configuration
0x0
32
read-write
n
0x0
0x0
EV0EM
Event 0 Edge Selection
16
1
read-write
value1
No action
#00
value2
Signal active on rising edge
#01
value3
Signal active on falling edge
#10
value4
Signal active on both edges
#11
EV0IS
Event 0 signal selection
0
3
read-write
value1
CCU4x.INyA
#0000
value2
CCU4x.INyB
#0001
value3
CCU4x.INyC
#0010
value4
CCU4x.INyD
#0011
value5
CCU4x.INyE
#0100
value6
CCU4x.INyF
#0101
value7
CCU4x.INyG
#0110
value8
CCU4x.INyH
#0111
value9
CCU4x.INyI
#1000
value10
CCU4x.INyJ
#1001
value11
CCU4x.INyK
#1010
value12
CCU4x.INyL
#1011
value13
CCU4x.INyM
#1100
value14
CCU4x.INyN
#1101
value15
CCU4x.INyO
#1110
value16
CCU4x.INyP
#1111
EV0LM
Event 0 Level Selection
22
read-write
value1
Active on HIGH level
#0
value2
Active on LOW level
#1
EV1EM
Event 1 Edge Selection
18
1
read-write
value1
No action
#00
value2
Signal active on rising edge
#01
value3
Signal active on falling edge
#10
value4
Signal active on both edges
#11
EV1IS
Event 1 signal selection
4
3
read-write
value1
CCU4x.INyA
#0000
value2
CCU4x.INyB
#0001
value3
CCU4x.INyC
#0010
value4
CCU4x.INyD
#0011
value5
CCU4x.INyE
#0100
value6
CCU4x.INyF
#0101
value7
CCU4x.INyG
#0110
value8
CCU4x.INyH
#0111
value9
CCU4x.INyI
#1000
value10
CCU4x.INyJ
#1001
value11
CCU4x.INyK
#1010
value12
CCU4x.INyL
#1011
value13
CCU4x.INyM
#1100
value14
CCU4x.INyN
#1101
value15
CCU4x.INyO
#1110
value16
CCU4x.INyP
#1111
EV1LM
Event 1 Level Selection
23
read-write
value1
Active on HIGH level
#0
value2
Active on LOW level
#1
EV2EM
Event 2 Edge Selection
20
1
read-write
value1
No action
#00
value2
Signal active on rising edge
#01
value3
Signal active on falling edge
#10
value4
Signal active on both edges
#11
EV2IS
Event 2 signal selection
8
3
read-write
value1
CCU4x.INyA
#0000
value2
CCU4x.INyB
#0001
value3
CCU4x.INyC
#0010
value4
CCU4x.INyD
#0011
value5
CCU4x.INyE
#0100
value6
CCU4x.INyF
#0101
value7
CCU4x.INyG
#0110
value8
CCU4x.INyH
#0111
value9
CCU4x.INyI
#1000
value10
CCU4x.INyJ
#1001
value11
CCU4x.INyK
#1010
value12
CCU4x.INyL
#1011
value13
CCU4x.INyM
#1100
value14
CCU4x.INyN
#1101
value15
CCU4x.INyO
#1110
value16
CCU4x.INyP
#1111
EV2LM
Event 2 Level Selection
24
read-write
value1
Active on HIGH level
#0
value2
Active on LOW level
#1
LPF0M
Event 0 Low Pass Filter Configuration
25
1
read-write
value1
LPF is disabled
#00
value2
3 clock cycles of fCCU4
#01
value3
5 clock cycles of fCCU4
#10
value4
7 clock cycles of fCCU4
#11
LPF1M
Event 1 Low Pass Filter Configuration
27
1
read-write
value1
LPF is disabled
#00
value2
3 clock cycles of fCCU4
#01
value3
5 clock cycles of fCCU4
#10
value4
7 clock cycles of fCCU4
#11
LPF2M
Event 2 Low Pass Filter Configuration
29
1
read-write
value1
LPF is disabled
#00
value2
3 clock cycles of fCCU4
#01
value3
5 clock cycles of fCCU4
#10
value4
7 clock cycles of fCCU4
#11
INTE
Interrupt Enable Control
0xA4
32
read-write
n
0x0
0x0
CMDE
Compare match while counting down enable
3
read-write
value1
Compare Match while counting down interrupt is disabled
#0
value2
Compare Match while counting down interrupt is enabled
#1
CMUE
Compare match while counting up enable
2
read-write
value1
Compare Match while counting up interrupt is disabled
#0
value2
Compare Match while counting up interrupt is enabled
#1
E0AE
Event 0 interrupt enable
8
read-write
value1
Event 0 detection interrupt is disabled
#0
value2
Event 0 detection interrupt is enabled
#1
E1AE
Event 1 interrupt enable
9
read-write
value1
Event 1 detection interrupt is disabled
#0
value2
Event 1 detection interrupt is enabled
#1
E2AE
Event 2 interrupt enable
10
read-write
value1
Event 2 detection interrupt is disabled
#0
value2
Event 2 detection interrupt is enabled
#1
OME
One match while counting down enable
1
read-write
value1
One Match interrupt is disabled
#0
value2
One Match interrupt is enabled
#1
PME
Period match while counting up enable
0
read-write
value1
Period Match interrupt is disabled
#0
value2
Period Match interrupt is enabled
#1
INTS
Interrupt Status
0xA0
32
read-write
n
0x0
0x0
CMDS
Compare Match while Counting Down
3
read-only
value1
Compare match while counting down not detected
#0
value2
Compare match while counting down detected
#1
CMUS
Compare Match while Counting Up
2
read-only
value1
Compare match while counting up not detected
#0
value2
Compare match while counting up detected
#1
E0AS
Event 0 Detection Status
8
read-only
value1
Event 0 not detected
#0
value2
Event 0 detected
#1
E1AS
Event 1 Detection Status
9
read-only
value1
Event 1 not detected
#0
value2
Event 1 detected
#1
E2AS
Event 2 Detection Status
10
read-only
value1
Event 2 not detected
#0
value2
Event 2 detected
#1
OMDS
One Match while Counting Down
1
read-only
value1
One match while counting down not detected
#0
value2
One match while counting down detected
#1
PMUS
Period Match while Counting Up
0
read-only
value1
Period match while counting up not detected
#0
value2
Period match while counting up detected
#1
TRPF
Trap Flag Status
11
read-only
PR
Timer Period Value
0x30
32
read-write
n
0x0
0x0
PR
Period Register
0
15
read-only
PRS
Timer Shadow Period Value
0x34
32
read-write
n
0x0
0x0
PRS
Period Register
0
15
read-write
PSC
Prescaler Control
0x24
32
read-write
n
0x0
0x0
PSIV
Prescaler Initial Value
0
3
read-write
PSL
Passive Level Config
0x18
32
read-write
n
0x0
0x0
PSL
Output Passive Level
0
read-write
value1
Passive Level is LOW
#0
value2
Passive Level is HIGH
#1
SRS
Service Request Selector
0xA8
32
read-write
n
0x0
0x0
CMSR
Compare match Service request selector
2
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
E0SR
Event 0 Service request selector
8
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
E1SR
Event 1 Service request selector
10
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
E2SR
Event 2 Service request selector
12
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
POSR
Period/One match Service request selector
0
1
read-write
value1
Forward to CC4ySR0
#00
value2
Forward to CC4ySR1
#01
value3
Forward to CC4ySR2
#10
value4
Forward to CC4ySR3
#11
SWR
Interrupt Status Clear
0xB0
32
read-write
n
0x0
0x0
RCMD
Compare match while counting down clear
3
write-only
RCMU
Compare match while counting up clear
2
write-only
RE0A
Event 0 detection clear
8
write-only
RE1A
Event 1 detection clear
9
write-only
RE2A
Event 2 detection clear
10
write-only
ROM
One match while counting down clear
1
write-only
RPM
Period match while counting up clear
0
write-only
RTRPF
Trap Flag status clear
11
write-only
SWS
Interrupt Status Set
0xAC
32
read-write
n
0x0
0x0
SCMD
Compare match while counting down set
3
write-only
SCMU
Compare match while counting up set
2
write-only
SE0A
Event 0 detection set
8
write-only
SE1A
Event 1 detection set
9
write-only
SE2A
Event 2 detection set
10
write-only
SOM
One match while counting down set
1
write-only
SPM
Period match while counting up set
0
write-only
STRPF
Trap Flag status set
11
write-only
TC
Slice Timer Control
0x14
32
read-write
n
0x0
0x0
CAPC
Clear on Capture Control
5
1
read-write
value1
Timer is never cleared on a capture event
#00
value2
Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event)
#01
value3
Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event)
#10
value4
Timer is always cleared in a capture event.
#11
CCS
Continuous Capture Enable
12
read-write
value1
The capture into a specific capture register is done with the rules linked with the full flags, described at .
#0
value2
The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back).
#1
CLST
Shadow Transfer on Clear
2
read-write
CMOD
Capture Compare Mode
3
read-only
value1
Compare Mode
#0
value2
Capture Mode
#1
DIM
Dither input selector
15
read-write
value1
Slice is using its own dither unit
#0
value2
Slice is connected to the dither unit of slice 0.
#1
DITHE
Dither Enable
13
1
read-write
value1
Dither is disabled
#00
value2
Dither is applied to the Period
#01
value3
Dither is applied to the Compare
#10
value4
Dither is applied to the Period and Compare
#11
ECM
Extended Capture Mode
4
read-write
value1
Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only.
#0
value2
Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the ECRD.VPTR is cleared.
#1
EMS
External Modulation Synchronization
23
read-write
value1
External Modulation functionality is not synchronized with the PWM signal
#0
value2
External Modulation functionality is synchronized with the PWM signal
#1
EMT
External Modulation Type
24
read-write
value1
External Modulation functionality is clearing the CC4yST bit.
#0
value2
External Modulation functionality is gating the outputs.
#1
ENDM
Extended Stop Function Control
8
1
read-write
value1
Clears the timer run bit only (default stop)
#00
value2
Clears the timer only (flush)
#01
value3
Clears the timer and run bit (flush/stop)
#10
FPE
Floating Prescaler enable
16
read-write
value1
Floating prescaler mode is disabled
#0
value2
Floating prescaler mode is enabled
#1
MCME
Multi Channel Mode Enable
25
read-write
value1
Multi Channel Mode is disabled
#0
value2
Multi Channel Mode is enabled
#1
SCE
Equal Capture Event enable
11
read-write
value1
Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1
#0
value2
Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. and CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1
#1
STRM
Extended Start Function Control
10
read-write
value1
Sets run bit only (default start)
#0
value2
Clears the timer and sets run bit (flush/start)
#1
TCM
Timer Counting Mode
0
read-write
value1
Edge aligned mode
#0
value2
Center aligned mode
#1
TRAPE
TRAP enable
17
read-write
value1
TRAP functionality has no effect on the output
#0
value2
TRAP functionality affects the output
#1
TRPSE
TRAP Synchronization Enable
21
read-write
value1
Exiting from TRAP state isn't synchronized with the PWM signal
#0
value2
Exiting from TRAP state is synchronized with the PWM signal
#1
TRPSW
TRAP State Clear Control
22
read-write
value1
The slice exits the TRAP state automatically when the TRAP condition is not present
#0
value2
The TRAP state can only be exited by a SW request.
#1
TSSM
Timer Single Shot Mode
1
read-write
value1
Single shot mode is disabled
#0
value2
Single shot mode is enabled
#1
TCCLR
Slice Timer Clear
0x10
32
read-write
n
0x0
0x0
DITC
Dither Counter Clear
2
write-only
TCC
Timer Clear
1
write-only
TRBC
Timer Run Bit Clear
0
write-only
TCSET
Slice Timer Run Set
0xC
32
read-write
n
0x0
0x0
TRBS
Timer Run Bit set
0
write-only
TCST
Slice Timer Status
0x8
32
read-write
n
0x0
0x0
CDIR
Timer Counting Direction
1
read-only
value1
Timer is counting up
#0
value2
Timer is counting down
#1
TRB
Timer Run Bit
0
read-only
value1
Timer is stopped
#0
value2
Timer is running
#1
TIMER
Timer Value
0x70
32
read-write
n
0x0
0x0
TVAL
Timer Value
0
15
read-write
ERU0
Event Request Unit 0
ERU0
0x0
0x0
0x100
registers
n
ERU0_0
External Request Unit 0
3
ERU0_1
External Request Unit 0
4
ERU0_2
External Request Unit 0
5
ERU0_3
External Request Unit 0
6
EXICON[0]
Event Input Control
0x20
32
read-write
n
0x0
0x0
FE
Falling Edge Detection Enable ETLx
3
read-write
value1
A falling edge is not considered as edge event
#0
value2
A falling edge is considered as edge event
#1
FL
Status Flag for ETLx
7
read-write
value1
The enabled edge event has not been detected
#0
value2
The enabled edge event has been detected
#1
LD
Rebuild Level Detection for Status Flag for ETLx
1
read-write
value1
The status flag FL is not cleared by hardware and is used as "sticky" bit. Once set, it is not influenced by any edge until it becomes cleared by software.
#0
value2
The status flag FL rebuilds a level detection of the desired event. It becomes automatically set with a rising edge if RE = 1 or with a falling edge if FE = 1. It becomes automatically cleared with a rising edge if RE = 0 or with a falling edge if FE = 0.
#1
NA
Input A Negation Select for ERSx
10
read-write
value1
Input A is used directly
#0
value2
Input A is inverted
#1
NB
Input B Negation Select for ERSx
11
read-write
value1
Input B is used directly
#0
value2
Input B is inverted
#1
OCS
Output Channel Select for ETLx Output Trigger Pulse
4
2
read-write
value1
Trigger pulses are sent to OGU0
#000
value2
Trigger pulses are sent to OGU1
#001
value3
Trigger pulses are sent to OGU2
#010
value4
Trigger pulses are sent to OGU3
#011
PE
Output Trigger Pulse Enable for ETLx
0
read-write
value1
The trigger pulse generation is disabled
#0
value2
The trigger pulse generation is enabled
#1
RE
Rising Edge Detection Enable ETLx
2
read-write
value1
A rising edge is not considered as edge event
#0
value2
A rising edge is considered as edge event
#1
SS
Input Source Select for ERSx
8
1
read-write
value1
Input A without additional combination
#00
value2
Input B without additional combination
#01
value3
Input A OR input B
#10
value4
Input A AND input B
#11
EXICON[1]
Event Input Control
0x34
32
read-write
n
0x0
0x0
FE
Falling Edge Detection Enable ETLx
3
read-write
value1
A falling edge is not considered as edge event
#0
value2
A falling edge is considered as edge event
#1
FL
Status Flag for ETLx
7
read-write
value1
The enabled edge event has not been detected
#0
value2
The enabled edge event has been detected
#1
LD
Rebuild Level Detection for Status Flag for ETLx
1
read-write
value1
The status flag FL is not cleared by hardware and is used as "sticky" bit. Once set, it is not influenced by any edge until it becomes cleared by software.
#0
value2
The status flag FL rebuilds a level detection of the desired event. It becomes automatically set with a rising edge if RE = 1 or with a falling edge if FE = 1. It becomes automatically cleared with a rising edge if RE = 0 or with a falling edge if FE = 0.
#1
NA
Input A Negation Select for ERSx
10
read-write
value1
Input A is used directly
#0
value2
Input A is inverted
#1
NB
Input B Negation Select for ERSx
11
read-write
value1
Input B is used directly
#0
value2
Input B is inverted
#1
OCS
Output Channel Select for ETLx Output Trigger Pulse
4
2
read-write
value1
Trigger pulses are sent to OGU0
#000
value2
Trigger pulses are sent to OGU1
#001
value3
Trigger pulses are sent to OGU2
#010
value4
Trigger pulses are sent to OGU3
#011
PE
Output Trigger Pulse Enable for ETLx
0
read-write
value1
The trigger pulse generation is disabled
#0
value2
The trigger pulse generation is enabled
#1
RE
Rising Edge Detection Enable ETLx
2
read-write
value1
A rising edge is not considered as edge event
#0
value2
A rising edge is considered as edge event
#1
SS
Input Source Select for ERSx
8
1
read-write
value1
Input A without additional combination
#00
value2
Input B without additional combination
#01
value3
Input A OR input B
#10
value4
Input A AND input B
#11
EXICON[2]
Event Input Control
0x4C
32
read-write
n
0x0
0x0
FE
Falling Edge Detection Enable ETLx
3
read-write
value1
A falling edge is not considered as edge event
#0
value2
A falling edge is considered as edge event
#1
FL
Status Flag for ETLx
7
read-write
value1
The enabled edge event has not been detected
#0
value2
The enabled edge event has been detected
#1
LD
Rebuild Level Detection for Status Flag for ETLx
1
read-write
value1
The status flag FL is not cleared by hardware and is used as "sticky" bit. Once set, it is not influenced by any edge until it becomes cleared by software.
#0
value2
The status flag FL rebuilds a level detection of the desired event. It becomes automatically set with a rising edge if RE = 1 or with a falling edge if FE = 1. It becomes automatically cleared with a rising edge if RE = 0 or with a falling edge if FE = 0.
#1
NA
Input A Negation Select for ERSx
10
read-write
value1
Input A is used directly
#0
value2
Input A is inverted
#1
NB
Input B Negation Select for ERSx
11
read-write
value1
Input B is used directly
#0
value2
Input B is inverted
#1
OCS
Output Channel Select for ETLx Output Trigger Pulse
4
2
read-write
value1
Trigger pulses are sent to OGU0
#000
value2
Trigger pulses are sent to OGU1
#001
value3
Trigger pulses are sent to OGU2
#010
value4
Trigger pulses are sent to OGU3
#011
PE
Output Trigger Pulse Enable for ETLx
0
read-write
value1
The trigger pulse generation is disabled
#0
value2
The trigger pulse generation is enabled
#1
RE
Rising Edge Detection Enable ETLx
2
read-write
value1
A rising edge is not considered as edge event
#0
value2
A rising edge is considered as edge event
#1
SS
Input Source Select for ERSx
8
1
read-write
value1
Input A without additional combination
#00
value2
Input B without additional combination
#01
value3
Input A OR input B
#10
value4
Input A AND input B
#11
EXICON[3]
Event Input Control
0x68
32
read-write
n
0x0
0x0
FE
Falling Edge Detection Enable ETLx
3
read-write
value1
A falling edge is not considered as edge event
#0
value2
A falling edge is considered as edge event
#1
FL
Status Flag for ETLx
7
read-write
value1
The enabled edge event has not been detected
#0
value2
The enabled edge event has been detected
#1
LD
Rebuild Level Detection for Status Flag for ETLx
1
read-write
value1
The status flag FL is not cleared by hardware and is used as "sticky" bit. Once set, it is not influenced by any edge until it becomes cleared by software.
#0
value2
The status flag FL rebuilds a level detection of the desired event. It becomes automatically set with a rising edge if RE = 1 or with a falling edge if FE = 1. It becomes automatically cleared with a rising edge if RE = 0 or with a falling edge if FE = 0.
#1
NA
Input A Negation Select for ERSx
10
read-write
value1
Input A is used directly
#0
value2
Input A is inverted
#1
NB
Input B Negation Select for ERSx
11
read-write
value1
Input B is used directly
#0
value2
Input B is inverted
#1
OCS
Output Channel Select for ETLx Output Trigger Pulse
4
2
read-write
value1
Trigger pulses are sent to OGU0
#000
value2
Trigger pulses are sent to OGU1
#001
value3
Trigger pulses are sent to OGU2
#010
value4
Trigger pulses are sent to OGU3
#011
PE
Output Trigger Pulse Enable for ETLx
0
read-write
value1
The trigger pulse generation is disabled
#0
value2
The trigger pulse generation is enabled
#1
RE
Rising Edge Detection Enable ETLx
2
read-write
value1
A rising edge is not considered as edge event
#0
value2
A rising edge is considered as edge event
#1
SS
Input Source Select for ERSx
8
1
read-write
value1
Input A without additional combination
#00
value2
Input B without additional combination
#01
value3
Input A OR input B
#10
value4
Input A AND input B
#11
EXISEL
Event Input Select
0x0
32
read-write
n
0x0
0x0
EXS0A
Event Source Select for A0 (ERS0)
0
1
read-write
value1
Input ERU_0A0 is selected
#00
value2
Input ERU_0A1 is selected
#01
value3
Input ERU_0A2 is selected
#10
value4
Input ERU_0A3 is selected
#11
EXS0B
Event Source Select for B0 (ERS0)
2
1
read-write
value1
Input ERU_0B0 is selected
#00
value2
Input ERU_0B1 is selected
#01
value3
Input ERU_0B2 is selected
#10
value4
Input ERU_0B3 is selected
#11
EXS1A
Event Source Select for A1 (ERS1)
4
1
read-write
value1
Input ERU_1A0 is selected
#00
value2
Input ERU_1A1 is selected
#01
value3
Input ERU_1A2 is selected
#10
value4
Input ERU_1A3 is selected
#11
EXS1B
Event Source Select for B1 (ERS1)
6
1
read-write
value1
Input ERU_1B0 is selected
#00
value2
Input ERU_1B1 is selected
#01
value3
Input ERU_1B2 is selected
#10
value4
Input ERU_1B3 is selected
#11
EXS2A
Event Source Select for A2 (ERS2)
8
1
read-write
value1
Input ERU_2A0 is selected
#00
value2
Input ERU_2A1 is selected
#01
value3
Input ERU_2A2 is selected
#10
value4
Input ERU_2A3 is selected
#11
EXS2B
Event Source Select for B2 (ERS2)
10
1
read-write
value1
Input ERU_2B0 is selected
#00
value2
Input ERU_2B1 is selected
#01
value3
Input ERU_2B2 is selected
#10
value4
Input ERU_2B3 is selected
#11
EXS3A
Event Source Select for A3 (ERS3)
12
1
read-write
value1
Input ERU_3A0 is selected
#00
value2
Input ERU_3A1 is selected
#01
value3
Input ERU_3A2 is selected
#10
value4
Input ERU_3A3 is selected
#11
EXS3B
Event Source Select for B3 (ERS3)
14
1
read-write
value1
Input ERU_3B0 is selected
#00
value2
Input ERU_3B1 is selected
#01
value3
Input ERU_3B2 is selected
#10
value4
Input ERU_3B3 is selected
#11
EXOCON[0]
Event Output Trigger Control
0x40
32
read-write
n
0x0
0x0
GEEN
Gating Event Enable
2
read-write
value1
The event detection is disabled
#0
value2
The event detection is enabled
#1
GP
Gating Selection for Pattern Detection Result
4
1
read-write
value1
ERU_GOUTy is always disabled and ERU_IOUTy can not be activated
#00
value2
ERU_GOUTy is always enabled and ERU_IOUTy becomes activated with each activation of ERU_TOUTy
#01
value3
ERU_GOUTy is equal to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is detected (pattern match PDR = 1)
#10
value4
ERU_GOUTy is inverted to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is not detected (pattern miss PDR = 0)
#11
IPEN0
Pattern Detection Enable for ETL0
12
read-write
value1
Flag EXICONx.FL is excluded from the pattern detection
#0
value2
Flag EXICONx.FL is included in the pattern detection
#1
IPEN1
Pattern Detection Enable for ETL1
13
read-write
value1
Flag EXICONx.FL is excluded from the pattern detection
#0
value2
Flag EXICONx.FL is included in the pattern detection
#1
IPEN2
Pattern Detection Enable for ETL2
14
read-write
value1
Flag EXICONx.FL is excluded from the pattern detection
#0
value2
Flag EXICONx.FL is included in the pattern detection
#1
IPEN3
Pattern Detection Enable for ETL3
15
read-write
value1
Flag EXICONx.FL is excluded from the pattern detection
#0
value2
Flag EXICONx.FL is included in the pattern detection
#1
ISS
Internal Trigger Source Selection
0
1
read-write
value1
The peripheral trigger function is disabled
#00
value2
Input ERU_OGUy1 is selected
#01
value3
Input ERU_OGUy2 is selected
#10
value4
Input ERU_OGUy3 is selected
#11
PDR
Pattern Detection Result Flag
3
read-only
value1
A pattern miss is detected
#0
value2
A pattern match is detected
#1
EXOCON[1]
Event Output Trigger Control
0x64
32
read-write
n
0x0
0x0
GEEN
Gating Event Enable
2
read-write
value1
The event detection is disabled
#0
value2
The event detection is enabled
#1
GP
Gating Selection for Pattern Detection Result
4
1
read-write
value1
ERU_GOUTy is always disabled and ERU_IOUTy can not be activated
#00
value2
ERU_GOUTy is always enabled and ERU_IOUTy becomes activated with each activation of ERU_TOUTy
#01
value3
ERU_GOUTy is equal to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is detected (pattern match PDR = 1)
#10
value4
ERU_GOUTy is inverted to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is not detected (pattern miss PDR = 0)
#11
IPEN0
Pattern Detection Enable for ETL0
12
read-write
value1
Flag EXICONx.FL is excluded from the pattern detection
#0
value2
Flag EXICONx.FL is included in the pattern detection
#1
IPEN1
Pattern Detection Enable for ETL1
13
read-write
value1
Flag EXICONx.FL is excluded from the pattern detection
#0
value2
Flag EXICONx.FL is included in the pattern detection
#1
IPEN2
Pattern Detection Enable for ETL2
14
read-write
value1
Flag EXICONx.FL is excluded from the pattern detection
#0
value2
Flag EXICONx.FL is included in the pattern detection
#1
IPEN3
Pattern Detection Enable for ETL3
15
read-write
value1
Flag EXICONx.FL is excluded from the pattern detection
#0
value2
Flag EXICONx.FL is included in the pattern detection
#1
ISS
Internal Trigger Source Selection
0
1
read-write
value1
The peripheral trigger function is disabled
#00
value2
Input ERU_OGUy1 is selected
#01
value3
Input ERU_OGUy2 is selected
#10
value4
Input ERU_OGUy3 is selected
#11
PDR
Pattern Detection Result Flag
3
read-only
value1
A pattern miss is detected
#0
value2
A pattern match is detected
#1
EXOCON[2]
Event Output Trigger Control
0x8C
32
read-write
n
0x0
0x0
GEEN
Gating Event Enable
2
read-write
value1
The event detection is disabled
#0
value2
The event detection is enabled
#1
GP
Gating Selection for Pattern Detection Result
4
1
read-write
value1
ERU_GOUTy is always disabled and ERU_IOUTy can not be activated
#00
value2
ERU_GOUTy is always enabled and ERU_IOUTy becomes activated with each activation of ERU_TOUTy
#01
value3
ERU_GOUTy is equal to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is detected (pattern match PDR = 1)
#10
value4
ERU_GOUTy is inverted to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is not detected (pattern miss PDR = 0)
#11
IPEN0
Pattern Detection Enable for ETL0
12
read-write
value1
Flag EXICONx.FL is excluded from the pattern detection
#0
value2
Flag EXICONx.FL is included in the pattern detection
#1
IPEN1
Pattern Detection Enable for ETL1
13
read-write
value1
Flag EXICONx.FL is excluded from the pattern detection
#0
value2
Flag EXICONx.FL is included in the pattern detection
#1
IPEN2
Pattern Detection Enable for ETL2
14
read-write
value1
Flag EXICONx.FL is excluded from the pattern detection
#0
value2
Flag EXICONx.FL is included in the pattern detection
#1
IPEN3
Pattern Detection Enable for ETL3
15
read-write
value1
Flag EXICONx.FL is excluded from the pattern detection
#0
value2
Flag EXICONx.FL is included in the pattern detection
#1
ISS
Internal Trigger Source Selection
0
1
read-write
value1
The peripheral trigger function is disabled
#00
value2
Input ERU_OGUy1 is selected
#01
value3
Input ERU_OGUy2 is selected
#10
value4
Input ERU_OGUy3 is selected
#11
PDR
Pattern Detection Result Flag
3
read-only
value1
A pattern miss is detected
#0
value2
A pattern match is detected
#1
EXOCON[3]
Event Output Trigger Control
0xB8
32
read-write
n
0x0
0x0
GEEN
Gating Event Enable
2
read-write
value1
The event detection is disabled
#0
value2
The event detection is enabled
#1
GP
Gating Selection for Pattern Detection Result
4
1
read-write
value1
ERU_GOUTy is always disabled and ERU_IOUTy can not be activated
#00
value2
ERU_GOUTy is always enabled and ERU_IOUTy becomes activated with each activation of ERU_TOUTy
#01
value3
ERU_GOUTy is equal to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is detected (pattern match PDR = 1)
#10
value4
ERU_GOUTy is inverted to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is not detected (pattern miss PDR = 0)
#11
IPEN0
Pattern Detection Enable for ETL0
12
read-write
value1
Flag EXICONx.FL is excluded from the pattern detection
#0
value2
Flag EXICONx.FL is included in the pattern detection
#1
IPEN1
Pattern Detection Enable for ETL1
13
read-write
value1
Flag EXICONx.FL is excluded from the pattern detection
#0
value2
Flag EXICONx.FL is included in the pattern detection
#1
IPEN2
Pattern Detection Enable for ETL2
14
read-write
value1
Flag EXICONx.FL is excluded from the pattern detection
#0
value2
Flag EXICONx.FL is included in the pattern detection
#1
IPEN3
Pattern Detection Enable for ETL3
15
read-write
value1
Flag EXICONx.FL is excluded from the pattern detection
#0
value2
Flag EXICONx.FL is included in the pattern detection
#1
ISS
Internal Trigger Source Selection
0
1
read-write
value1
The peripheral trigger function is disabled
#00
value2
Input ERU_OGUy1 is selected
#01
value3
Input ERU_OGUy2 is selected
#10
value4
Input ERU_OGUy3 is selected
#11
PDR
Pattern Detection Result Flag
3
read-only
value1
A pattern miss is detected
#0
value2
A pattern match is detected
#1
NVM
NVM Unit
NVM
0x0
0x0
0x100
registers
n
CONFIG1
Configuration 1 Register
0x48
16
read-write
n
0x0
0x0
FIXWS
Wait States Scheme
11
read-write
Const_0
adaptive wait states.
#0
Const_1
fixed wait states.
#1
NVMCONF
NVM Configuration Register
0x8
16
read-write
n
0x0
0x0
HRLEV
Hardread Level
1
1
read-write
value1
Normal read
#00
value2
Hardread written
#01
value3
Hardread erased
#10
INT_ON
Interrupt On
14
read-write
value1
No NVM ready interrupts are generated.
#0
value2
NVM ready interrupts are generated.
#1
NVM_ON
NVM On
15
read-write
value1
NVM is switched to or stays in sleep mode.
#0
value2
NVM is switched to or stays in normal mode.
#1
SECPROT
Sector Protection
4
7
read-write
WS
Number of fixed Wait States
12
read-write
value1
0 fixed wait states.
#0
value2
1 fixed wait state.
#1
NVMPROG
NVM Programming Control Register
0x4
16
read-write
n
0x0
0x0
ACTION
ACTION: [VERIFY, ONE_SHOT, OPTYPE]
0
7
read-write
value1
Idle state, no action triggered. Writing 0x00 exits current mode.
0x00
value2
Start one-shot write operation with automatic verify.
0x51
value4
Start continuous write operation with automatic verify of every write.
0x61
value3
Start one-shot write operation without verify.
0x91
value6
Start one-shot page erase operation.
0x92
value5
Start continuous write operation without verify.
0xA1
value7
Start continuous page erase operation.
0xA2
value8
Start one-shot verify-only: Written data is compared to array content.
0xD0
value9
Start continuous verify-only: Written data is compared to array content.
0xE0
RSTECC
Reset ECC
13
read-write
value1
No action.
#0
value2
Reset of .ECCxREAD and NVMSTATUS.WRPERR.
#1
RSTVERR
Reset Verify Error
12
read-write
value1
No action.
#0
value2
Reset of .VERR.
#1
NVMSTATUS
NVM Status Register
0x0
16
read-write
n
0x0
0x0
BUSY
Busy
0
read-only
value1
The NVM is not busy. Memory reads from the cell array and register write accesses are possible.
#0
value2
The NVM is busy. Memory reads and register write accesses are not possible.
#1
ECC1READ
ECC1 Read
4
read-only
value1
No ECC single bit failure occurred.
#0
value2
At least one ECC single bit failure was detected and corrected.
#1
ECC2READ
ECC2 Read
5
read-only
value1
No ECC two bit failure during memory read operations.
#0
value2
At least one ECC two bit failure was detected.
#1
SLEEP
Sleep Mode
1
read-only
value1
NVM not in sleep mode, and no sleep or wake up procedure in progress.
#0
value2
NVM in sleep mode, or busy due to a sleep or wake up procedure.
#1
VERR
Verify Error
2
1
read-only
value1
No fail bit.
#00
value2
One fail bit in one data block.
#01
value3
Two fail bits in two different data blocks.
#10
value4
Two or more fail bits in one data block, or three or more fail bits overall.
#11
WRPERR
Write Protocol Error
6
read-only
value1
No write protocol failure occurred.
#0
value2
At least one write protocol failure was detected.
#1
PAU
PAU Unit
PAU
0x0
0x0
0x10000
registers
n
AVAIL0
Peripheral Availability Register 0
0x40
32
read-write
n
0x0
0x0
AVAIL22
Port 0 Availability Flag
22
read-only
value1
Port 0 is not available.
#0
value2
Port 0 is available.
#1
AVAIL23
Port 1 Availability Flag
23
read-only
value1
Port 1 is not available.
#0
value2
Port 1 is available.
#1
AVAIL24
Port 0 Availability Flag
24
read-only
value1
Port 2 is not available.
#0
value2
Port 2 is available.
#1
AVAIL5
RAM Block 1 Availability Flag
5
read-only
value1
RAM block 1 is not available.
#0
value2
RAM block 1 is available.
#1
AVAIL6
RAM Block 2 Availability Flag
6
read-only
value1
RAM block 2 is not available.
#0
value2
RAM block 2 is available.
#1
AVAIL7
RAM Block 3 Availability Flag
7
read-only
value1
RAM block 3 is not available.
#0
value2
RAM block 3 is available.
#1
AVAIL1
Peripheral Availability Register 1
0x44
32
read-write
n
0x0
0x0
AVAIL0
USIC0 Channel 0 Availability Flag
0
read-only
value1
USIC0 Channel 0 is not available.
#0
value2
USIC0 Channel 0 is available.
#1
AVAIL1
USIC0 Channel 1 Availability Flag
1
read-only
value1
USIC0 Channel 1 is not available.
#0
value2
USIC0 Channel 1 is available.
#1
AVAIL10
CC41 Availability Flag
10
read-only
value1
CC41 is not available.
#0
value2
CC41 is available.
#1
AVAIL11
CC42 Availability Flag
11
read-only
value1
CC42 is not available.
#0
value2
CC42 is available.
#1
AVAIL12
CC43 Availability Flag
12
read-only
value1
CC43 is not available.
#0
value2
CC43 is available.
#1
AVAIL4
PRNG Availability Flag
4
read-only
value1
PRNG is not available.
#0
value2
PRNG is available.
#1
AVAIL5
VADC0 Basic SFRs Availability Flag
5
read-only
value1
VADC0 Basic SFRs are not available.
#0
value2
VADC0 Basic SFRs are available.
#1
AVAIL8
SHS0 Availability Flag
8
read-only
value1
SHS0 is not available.
#0
value2
SHS0 is available.
#1
AVAIL9
CC40 Availability Flag
9
read-only
value1
CC40 is not available.
#0
value2
CC40 is available.
#1
AVAIL2
Peripheral Availability Register 2
0x48
32
read-write
n
0x0
0x0
FLSIZE
Flash Size Register
0x404
32
read-write
n
0x0
0x0
ADDR
Flash Size
12
5
read-only
PRIVDIS0
Peripheral Privilege Access Register 0
0x80
32
read-write
n
0x0
0x0
PDIS19
WDT Privilege Disable Flag
19
read-write
value1
WDT is accessible.
#0
value2
WDT is not accessible.
#1
PDIS2
Flash SFRs Privilege Disable Flag
2
read-write
value1
Flash SFRs are accessible.
#0
value2
Flash SFRs are not accessible.
#1
PDIS22
Port 0 Privilege Disable Flag
22
read-write
value1
Port 0 is accessible.
#0
value2
Port 0 is not accessible.
#1
PDIS23
Port 1 Privilege Disable Flag
23
read-write
value1
Port 1 is accessible.
#0
value2
Port 1 is not accessible.
#1
PDIS24
Port 2 Privilege Disable Flag
24
read-write
value1
Port 2 is accessible.
#0
value2
Port 2 is not accessible.
#1
PDIS5
RAM Block 1 Privilege Disable Flag
5
read-write
value1
RAM Block 1 is accessible.
#0
value2
RAM Block 1 is not accessible.
#1
PDIS6
RAM Block 2 Privilege Disable Flag
6
read-write
value1
RAM Block 2 is accessible.
#0
value2
RAM Block 2 is not accessible.
#1
PDIS7
RAM Block 3 Privilege Disable Flag
7
read-write
value1
RAM Block 3 is accessible.
#0
value2
RAM Block 3 is not accessible.
#1
PRIVDIS1
Peripheral Privilege Access Register 1
0x84
32
read-write
n
0x0
0x0
PDIS0
USIC0 Channel 0 Privilege Disable Flag
0
read-write
value1
USIC0 Channel 0 is accessible.
#0
value2
USIC0 Channel 0 is not accessible.
#1
PDIS1
USIC0 Channel 1 Privilege Disable Flag
1
read-write
value1
USIC0 Channel 1 is accessible.
#0
value2
USIC0 Channel 1 is not accessible.
#1
PDIS10
CC41 Privilege Disable Flag
10
read-write
value1
CC41 is accessible.
#0
value2
CC41 is not accessible.
#1
PDIS11
CC42 Privilege Disable Flag
11
read-write
value1
CC42 is accessible.
#0
value2
CC42 is not accessible.
#1
PDIS12
CC43 Privilege Disable Flag
12
read-write
value1
CC43 is accessible.
#0
value2
CC43 is not accessible.
#1
PDIS5
VADC0 Basic SFRs Privilege Disable Flag
5
read-write
value1
VADC0 Basic SFRs are accessible.
#0
value2
VADC0 Basic SFRs are not accessible.
#1
PDIS8
SHS0 Privilege Disable Flag
8
read-write
value1
SHS is accessible.
#0
value2
SHS is not accessible.
#1
PDIS9
CC40 and CCU40 Kernel SFRs Privilege Disable Flag
9
read-write
value1
CC40 and CCU40 Kernel SFRs are accessible.
#0
value2
CC40 and CCU40 Kernel SFRs are not accessible.
#1
RAM0SIZE
RAM0 Size Register
0x410
32
read-write
n
0x0
0x0
ADDR
RAM0 Size
8
4
read-only
ROMSIZE
ROM Size Register
0x400
32
read-write
n
0x0
0x0
ADDR
ROM Size
8
5
read-only
PORT0
Port 0
PORTS
0x0
0x0
0x100
registers
n
HWSEL
Port 0 Pin Hardware Select Register
0x74
32
read-write
n
0x0
0x0
HW0
Port 0 Pin Hardware Select Bit 0
0
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW1
Port 0 Pin Hardware Select Bit 1
2
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW10
Port 0 Pin Hardware Select Bit 10
20
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW11
Port 0 Pin Hardware Select Bit 11
22
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW12
Port 0 Pin Hardware Select Bit 12
24
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW13
Port 0 Pin Hardware Select Bit 13
26
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW14
Port 0 Pin Hardware Select Bit 14
28
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW15
Port 0 Pin Hardware Select Bit 15
30
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW2
Port 0 Pin Hardware Select Bit 2
4
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW3
Port 0 Pin Hardware Select Bit 3
6
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW4
Port 0 Pin Hardware Select Bit 4
8
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW5
Port 0 Pin Hardware Select Bit 5
10
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW6
Port 0 Pin Hardware Select Bit 6
12
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW7
Port 0 Pin Hardware Select Bit 7
14
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW8
Port 0 Pin Hardware Select Bit 8
16
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW9
Port 0 Pin Hardware Select Bit 9
18
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
IN
Port 0 Input Register
0x24
32
read-write
n
0x0
0x0
P0
Port 0 Input Bit 0
0
read-only
value1
The input level of P0.x is 0.
#0
value2
The input level of P0.x is 1.
#1
P1
Port 0 Input Bit 1
1
read-only
value1
The input level of P0.x is 0.
#0
value2
The input level of P0.x is 1.
#1
P10
Port 0 Input Bit 10
10
read-only
value1
The input level of P0.x is 0.
#0
value2
The input level of P0.x is 1.
#1
P11
Port 0 Input Bit 11
11
read-only
value1
The input level of P0.x is 0.
#0
value2
The input level of P0.x is 1.
#1
P12
Port 0 Input Bit 12
12
read-only
value1
The input level of P0.x is 0.
#0
value2
The input level of P0.x is 1.
#1
P13
Port 0 Input Bit 13
13
read-only
value1
The input level of P0.x is 0.
#0
value2
The input level of P0.x is 1.
#1
P14
Port 0 Input Bit 14
14
read-only
value1
The input level of P0.x is 0.
#0
value2
The input level of P0.x is 1.
#1
P15
Port 0 Input Bit 15
15
read-only
value1
The input level of P0.x is 0.
#0
value2
The input level of P0.x is 1.
#1
P2
Port 0 Input Bit 2
2
read-only
value1
The input level of P0.x is 0.
#0
value2
The input level of P0.x is 1.
#1
P3
Port 0 Input Bit 3
3
read-only
value1
The input level of P0.x is 0.
#0
value2
The input level of P0.x is 1.
#1
P4
Port 0 Input Bit 4
4
read-only
value1
The input level of P0.x is 0.
#0
value2
The input level of P0.x is 1.
#1
P5
Port 0 Input Bit 5
5
read-only
value1
The input level of P0.x is 0.
#0
value2
The input level of P0.x is 1.
#1
P6
Port 0 Input Bit 6
6
read-only
value1
The input level of P0.x is 0.
#0
value2
The input level of P0.x is 1.
#1
P7
Port 0 Input Bit 7
7
read-only
value1
The input level of P0.x is 0.
#0
value2
The input level of P0.x is 1.
#1
P8
Port 0 Input Bit 8
8
read-only
value1
The input level of P0.x is 0.
#0
value2
The input level of P0.x is 1.
#1
P9
Port 0 Input Bit 9
9
read-only
value1
The input level of P0.x is 0.
#0
value2
The input level of P0.x is 1.
#1
IOCR0
Port 0 Input/Output Control Register 0
0x10
32
read-write
n
0x0
0x0
PC0
Port Control for Port n Pin 0 to 3
3
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC1
Port Control for Port n Pin 0 to 3
11
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC2
Port Control for Port n Pin 0 to 3
19
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC3
Port Control for Port n Pin 0 to 3
27
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
IOCR12
Port 0 Input/Output Control Register 12
0x1C
32
read-write
n
0x0
0x0
PC12
Port Control for Port n Pin 12 to 15
3
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC13
Port Control for Port n Pin 12 to 15
11
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC14
Port Control for Port n Pin 12 to 15
19
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC15
Port Control for Port n Pin 12 to 15
27
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
IOCR4
Port 0 Input/Output Control Register 4
0x14
32
read-write
n
0x0
0x0
PC4
Port Control for Port n Pin 4 to 7
3
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC5
Port Control for Port n Pin 4 to 7
11
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC6
Port Control for Port n Pin 4 to 7
19
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC7
Port Control for Port n Pin 4 to 7
27
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
IOCR8
Port 0 Input/Output Control Register 8
0x18
32
read-write
n
0x0
0x0
PC10
Port Control for Port n Pin 8 to 11
19
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC11
Port Control for Port n Pin 8 to 11
27
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC8
Port Control for Port n Pin 8 to 11
3
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC9
Port Control for Port n Pin 8 to 11
11
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
OMR
Port 0 Output Modification Register
0x4
32
read-write
n
0x0
0x0
PR0
Port 0 Reset Bit 0
16
write-only
PR1
Port 0 Reset Bit 1
17
write-only
PR10
Port 0 Reset Bit 10
26
write-only
PR11
Port 0 Reset Bit 11
27
write-only
PR12
Port 0 Reset Bit 12
28
write-only
PR13
Port 0 Reset Bit 13
29
write-only
PR14
Port 0 Reset Bit 14
30
write-only
PR15
Port 0 Reset Bit 15
31
write-only
PR2
Port 0 Reset Bit 2
18
write-only
PR3
Port 0 Reset Bit 3
19
write-only
PR4
Port 0 Reset Bit 4
20
write-only
PR5
Port 0 Reset Bit 5
21
write-only
PR6
Port 0 Reset Bit 6
22
write-only
PR7
Port 0 Reset Bit 7
23
write-only
PR8
Port 0 Reset Bit 8
24
write-only
PR9
Port 0 Reset Bit 9
25
write-only
PS0
Port 0 Set Bit 0
0
write-only
PS1
Port 0 Set Bit 1
1
write-only
PS10
Port 0 Set Bit 10
10
write-only
PS11
Port 0 Set Bit 11
11
write-only
PS12
Port 0 Set Bit 12
12
write-only
PS13
Port 0 Set Bit 13
13
write-only
PS14
Port 0 Set Bit 14
14
write-only
PS15
Port 0 Set Bit 15
15
write-only
PS2
Port 0 Set Bit 2
2
write-only
PS3
Port 0 Set Bit 3
3
write-only
PS4
Port 0 Set Bit 4
4
write-only
PS5
Port 0 Set Bit 5
5
write-only
PS6
Port 0 Set Bit 6
6
write-only
PS7
Port 0 Set Bit 7
7
write-only
PS8
Port 0 Set Bit 8
8
write-only
PS9
Port 0 Set Bit 9
9
write-only
OUT
Port 0 Output Register
0x0
32
read-write
n
0x0
0x0
P0
Port 0 Output Bit 0
0
read-write
value1
The output level of P0.x is 0.
#0
value2
The output level of P0.x is 1.
#1
P1
Port 0 Output Bit 1
1
read-write
value1
The output level of P0.x is 0.
#0
value2
The output level of P0.x is 1.
#1
P10
Port 0 Output Bit 10
10
read-write
value1
The output level of P0.x is 0.
#0
value2
The output level of P0.x is 1.
#1
P11
Port 0 Output Bit 11
11
read-write
value1
The output level of P0.x is 0.
#0
value2
The output level of P0.x is 1.
#1
P12
Port 0 Output Bit 12
12
read-write
value1
The output level of P0.x is 0.
#0
value2
The output level of P0.x is 1.
#1
P13
Port 0 Output Bit 13
13
read-write
value1
The output level of P0.x is 0.
#0
value2
The output level of P0.x is 1.
#1
P14
Port 0 Output Bit 14
14
read-write
value1
The output level of P0.x is 0.
#0
value2
The output level of P0.x is 1.
#1
P15
Port 0 Output Bit 15
15
read-write
value1
The output level of P0.x is 0.
#0
value2
The output level of P0.x is 1.
#1
P2
Port 0 Output Bit 2
2
read-write
value1
The output level of P0.x is 0.
#0
value2
The output level of P0.x is 1.
#1
P3
Port 0 Output Bit 3
3
read-write
value1
The output level of P0.x is 0.
#0
value2
The output level of P0.x is 1.
#1
P4
Port 0 Output Bit 4
4
read-write
value1
The output level of P0.x is 0.
#0
value2
The output level of P0.x is 1.
#1
P5
Port 0 Output Bit 5
5
read-write
value1
The output level of P0.x is 0.
#0
value2
The output level of P0.x is 1.
#1
P6
Port 0 Output Bit 6
6
read-write
value1
The output level of P0.x is 0.
#0
value2
The output level of P0.x is 1.
#1
P7
Port 0 Output Bit 7
7
read-write
value1
The output level of P0.x is 0.
#0
value2
The output level of P0.x is 1.
#1
P8
Port 0 Output Bit 8
8
read-write
value1
The output level of P0.x is 0.
#0
value2
The output level of P0.x is 1.
#1
P9
Port 0 Output Bit 9
9
read-write
value1
The output level of P0.x is 0.
#0
value2
The output level of P0.x is 1.
#1
PDISC
Port 0 Pin Function Decision Control Register
0x60
32
read-write
n
0x0
0x0
PDIS0
Pad Disable for Port 0 Pin 0
0
read-only
value1
Pad P0.x is enabled.
#0
value2
Pad P0.x is disabled.
#1
PDIS1
Pad Disable for Port 0 Pin 1
1
read-only
value1
Pad P0.x is enabled.
#0
value2
Pad P0.x is disabled.
#1
PDIS10
Pad Disable for Port 0 Pin 10
10
read-only
value1
Pad P0.x is enabled.
#0
value2
Pad P0.x is disabled.
#1
PDIS11
Pad Disable for Port 0 Pin 11
11
read-only
value1
Pad P0.x is enabled.
#0
value2
Pad P0.x is disabled.
#1
PDIS12
Pad Disable for Port 0 Pin 12
12
read-only
value1
Pad P0.x is enabled.
#0
value2
Pad P0.x is disabled.
#1
PDIS13
Pad Disable for Port 0 Pin 13
13
read-only
value1
Pad P0.x is enabled.
#0
value2
Pad P0.x is disabled.
#1
PDIS14
Pad Disable for Port 0 Pin 14
14
read-only
value1
Pad P0.x is enabled.
#0
value2
Pad P0.x is disabled.
#1
PDIS15
Pad Disable for Port 0 Pin 15
15
read-only
value1
Pad P0.x is enabled.
#0
value2
Pad P0.x is disabled.
#1
PDIS2
Pad Disable for Port 0 Pin 2
2
read-only
value1
Pad P0.x is enabled.
#0
value2
Pad P0.x is disabled.
#1
PDIS3
Pad Disable for Port 0 Pin 3
3
read-only
value1
Pad P0.x is enabled.
#0
value2
Pad P0.x is disabled.
#1
PDIS4
Pad Disable for Port 0 Pin 4
4
read-only
value1
Pad P0.x is enabled.
#0
value2
Pad P0.x is disabled.
#1
PDIS5
Pad Disable for Port 0 Pin 5
5
read-only
value1
Pad P0.x is enabled.
#0
value2
Pad P0.x is disabled.
#1
PDIS6
Pad Disable for Port 0 Pin 6
6
read-only
value1
Pad P0.x is enabled.
#0
value2
Pad P0.x is disabled.
#1
PDIS7
Pad Disable for Port 0 Pin 7
7
read-only
value1
Pad P0.x is enabled.
#0
value2
Pad P0.x is disabled.
#1
PDIS8
Pad Disable for Port 0 Pin 8
8
read-only
value1
Pad P0.x is enabled.
#0
value2
Pad P0.x is disabled.
#1
PDIS9
Pad Disable for Port 0 Pin 9
9
read-only
value1
Pad P0.x is enabled.
#0
value2
Pad P0.x is disabled.
#1
PHCR0
Port 0 Pad Hysteresis Control Register 0
0x40
32
read-write
n
0x0
0x0
PH0
Pad Hysteresis for Pn.0
2
read-write
PH1
Pad Hysteresis for Pn.1
6
read-write
PH2
Pad Hysteresis for Pn.2
10
read-write
PH3
Pad Hysteresis for Pn.3
14
read-write
PH4
Pad Hysteresis for Pn.4
18
read-write
PH5
Pad Hysteresis for Pn.5
22
read-write
PH6
Pad Hysteresis for Pn.6
26
read-write
PH7
Pad Hysteresis for Pn.7
30
read-write
PHCR1
Port 0 Pad Hysteresis Control Register 1
0x44
32
read-write
n
0x0
0x0
PH10
Pad Hysteresis for P0.10
10
read-write
PH11
Pad Hysteresis for P0.11
14
read-write
PH12
Pad Hysteresis for P0.12
18
read-write
PH13
Pad Hysteresis for P0.13
22
read-write
PH14
Pad Hysteresis for P0.14
26
read-write
PH15
Pad Hysteresis for P0.15
30
read-write
PH8
Pad Hysteresis for P0.8
2
read-write
PH9
Pad Hysteresis for P0.9
6
read-write
PPS
Port 0 Pin Power Save Register
0x70
32
read-write
n
0x0
0x0
PPS0
Port 0 Pin Power Save Bit 0
0
read-write
value1
Pin Power Save of P0.x is disabled.
#0
value2
Pin Power Save of P0.x is enabled.
#1
PPS1
Port 0 Pin Power Save Bit 1
1
read-write
value1
Pin Power Save of P0.x is disabled.
#0
value2
Pin Power Save of P0.x is enabled.
#1
PPS10
Port 0 Pin Power Save Bit 10
10
read-write
value1
Pin Power Save of P0.x is disabled.
#0
value2
Pin Power Save of P0.x is enabled.
#1
PPS11
Port 0 Pin Power Save Bit 11
11
read-write
value1
Pin Power Save of P0.x is disabled.
#0
value2
Pin Power Save of P0.x is enabled.
#1
PPS12
Port 0 Pin Power Save Bit 12
12
read-write
value1
Pin Power Save of P0.x is disabled.
#0
value2
Pin Power Save of P0.x is enabled.
#1
PPS13
Port 0 Pin Power Save Bit 13
13
read-write
value1
Pin Power Save of P0.x is disabled.
#0
value2
Pin Power Save of P0.x is enabled.
#1
PPS14
Port 0 Pin Power Save Bit 14
14
read-write
value1
Pin Power Save of P0.x is disabled.
#0
value2
Pin Power Save of P0.x is enabled.
#1
PPS15
Port 0 Pin Power Save Bit 15
15
read-write
value1
Pin Power Save of P0.x is disabled.
#0
value2
Pin Power Save of P0.x is enabled.
#1
PPS2
Port 0 Pin Power Save Bit 2
2
read-write
value1
Pin Power Save of P0.x is disabled.
#0
value2
Pin Power Save of P0.x is enabled.
#1
PPS3
Port 0 Pin Power Save Bit 3
3
read-write
value1
Pin Power Save of P0.x is disabled.
#0
value2
Pin Power Save of P0.x is enabled.
#1
PPS4
Port 0 Pin Power Save Bit 4
4
read-write
value1
Pin Power Save of P0.x is disabled.
#0
value2
Pin Power Save of P0.x is enabled.
#1
PPS5
Port 0 Pin Power Save Bit 5
5
read-write
value1
Pin Power Save of P0.x is disabled.
#0
value2
Pin Power Save of P0.x is enabled.
#1
PPS6
Port 0 Pin Power Save Bit 6
6
read-write
value1
Pin Power Save of P0.x is disabled.
#0
value2
Pin Power Save of P0.x is enabled.
#1
PPS7
Port 0 Pin Power Save Bit 7
7
read-write
value1
Pin Power Save of P0.x is disabled.
#0
value2
Pin Power Save of P0.x is enabled.
#1
PPS8
Port 0 Pin Power Save Bit 8
8
read-write
value1
Pin Power Save of P0.x is disabled.
#0
value2
Pin Power Save of P0.x is enabled.
#1
PPS9
Port 0 Pin Power Save Bit 9
9
read-write
value1
Pin Power Save of P0.x is disabled.
#0
value2
Pin Power Save of P0.x is enabled.
#1
PORT1
Port 1
PORTS
0x0
0x0
0x100
registers
n
HWSEL
Port 1 Pin Hardware Select Register
0x74
32
read-write
n
0x0
0x0
HW0
Port 1 Pin Hardware Select Bit 0
0
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW1
Port 1 Pin Hardware Select Bit 1
2
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW2
Port 1 Pin Hardware Select Bit 2
4
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW3
Port 1 Pin Hardware Select Bit 3
6
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW4
Port 1 Pin Hardware Select Bit 4
8
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW5
Port 1 Pin Hardware Select Bit 5
10
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW6
Port 1 Pin Hardware Select Bit 6
12
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
IN
Port 1 Input Register
0x24
32
read-write
n
0x0
0x0
P0
Port 1 Input Bit 0
0
read-only
value1
The input level of P1.x is 0.
#0
value2
The input level of P1.x is 1.
#1
P1
Port 1 Input Bit 1
1
read-only
value1
The input level of P1.x is 0.
#0
value2
The input level of P1.x is 1.
#1
P2
Port 1 Input Bit 2
2
read-only
value1
The input level of P1.x is 0.
#0
value2
The input level of P1.x is 1.
#1
P3
Port 1 Input Bit 3
3
read-only
value1
The input level of P1.x is 0.
#0
value2
The input level of P1.x is 1.
#1
P4
Port 1 Input Bit 4
4
read-only
value1
The input level of P1.x is 0.
#0
value2
The input level of P1.x is 1.
#1
P5
Port 1 Input Bit 5
5
read-only
value1
The input level of P1.x is 0.
#0
value2
The input level of P1.x is 1.
#1
P6
Port 1 Input Bit 6
6
read-only
value1
The input level of P1.x is 0.
#0
value2
The input level of P1.x is 1.
#1
IOCR0
Port 1 Input/Output Control Register 0
0x10
32
read-write
n
0x0
0x0
PC0
Port Control for Port n Pin 0 to 3
3
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC1
Port Control for Port n Pin 0 to 3
11
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC2
Port Control for Port n Pin 0 to 3
19
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC3
Port Control for Port n Pin 0 to 3
27
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
IOCR4
Port 1 Input/Output Control Register 4
0x14
32
read-write
n
0x0
0x0
PC4
Port Control for Port n Pin 4 to 6
3
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC5
Port Control for Port n Pin 4 to 6
11
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC6
Port Control for Port n Pin 4 to 6
19
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
OMR
Port 1 Output Modification Register
0x4
32
read-write
n
0x0
0x0
PR0
Port 1 Reset Bit 0
16
write-only
PR1
Port 1 Reset Bit 1
17
write-only
PR2
Port 1 Reset Bit 2
18
write-only
PR3
Port 1 Reset Bit 3
19
write-only
PR4
Port 1 Reset Bit 4
20
write-only
PR5
Port 1 Reset Bit 5
21
write-only
PR6
Port 1 Reset Bit 6
22
write-only
PS0
Port 1 Set Bit 0
0
write-only
PS1
Port 1 Set Bit 1
1
write-only
PS2
Port 1 Set Bit 2
2
write-only
PS3
Port 1 Set Bit 3
3
write-only
PS4
Port 1 Set Bit 4
4
write-only
PS5
Port 1 Set Bit 5
5
write-only
PS6
Port 1 Set Bit 6
6
write-only
OUT
Port 1 Output Register
0x0
32
read-write
n
0x0
0x0
P0
Port 1 Output Bit 0
0
read-write
value1
The output level of P1.x is 0.
#0
value2
The output level of P1.x is 1.
#1
P1
Port 1 Output Bit 1
1
read-write
value1
The output level of P1.x is 0.
#0
value2
The output level of P1.x is 1.
#1
P2
Port 1 Output Bit 2
2
read-write
value1
The output level of P1.x is 0.
#0
value2
The output level of P1.x is 1.
#1
P3
Port 1 Output Bit 3
3
read-write
value1
The output level of P1.x is 0.
#0
value2
The output level of P1.x is 1.
#1
P4
Port 1 Output Bit 4
4
read-write
value1
The output level of P1.x is 0.
#0
value2
The output level of P1.x is 1.
#1
P5
Port 1 Output Bit 5
5
read-write
value1
The output level of P1.x is 0.
#0
value2
The output level of P1.x is 1.
#1
P6
Port 1 Output Bit 6
6
read-write
value1
The output level of P1.x is 0.
#0
value2
The output level of P1.x is 1.
#1
PDISC
Port 1 Pin Function Decision Control Register
0x60
32
read-write
n
0x0
0x0
PDIS0
Pad Disable for Port 1 Pin 0
0
read-only
value1
Pad P1.x is enabled.
#0
value2
Pad P1.x is disabled.
#1
PDIS1
Pad Disable for Port 1 Pin 1
1
read-only
value1
Pad P1.x is enabled.
#0
value2
Pad P1.x is disabled.
#1
PDIS2
Pad Disable for Port 1 Pin 2
2
read-only
value1
Pad P1.x is enabled.
#0
value2
Pad P1.x is disabled.
#1
PDIS3
Pad Disable for Port 1 Pin 3
3
read-only
value1
Pad P1.x is enabled.
#0
value2
Pad P1.x is disabled.
#1
PDIS4
Pad Disable for Port 1 Pin 4
4
read-only
value1
Pad P1.x is enabled.
#0
value2
Pad P1.x is disabled.
#1
PDIS5
Pad Disable for Port 1 Pin 5
5
read-only
value1
Pad P1.x is enabled.
#0
value2
Pad P1.x is disabled.
#1
PDIS6
Pad Disable for Port 1 Pin 6
6
read-only
value1
Pad P1.x is enabled.
#0
value2
Pad P1.x is disabled.
#1
PHCR0
Port 1 Pad Hysteresis Control Register 0
0x40
32
read-write
n
0x0
0x0
PH0
Pad Hysteresis for P1.0
2
read-write
PH1
Pad Hysteresis for P1.1
6
read-write
PH2
Pad Hysteresis for P1.2
10
read-write
PH3
Pad Hysteresis for P1.3
14
read-write
PH4
Pad Hysteresis for P1.4
18
read-write
PH5
Pad Hysteresis for P1.5
22
read-write
PH6
Pad Hysteresis for P1.6
26
read-write
PPS
Port 1 Pin Power Save Register
0x70
32
read-write
n
0x0
0x0
PPS0
Port 1 Pin Power Save Bit 0
0
read-write
value1
Pin Power Save of P1.x is disabled.
#0
value2
Pin Power Save of P1.x is enabled.
#1
PPS1
Port 1 Pin Power Save Bit 1
1
read-write
value1
Pin Power Save of P1.x is disabled.
#0
value2
Pin Power Save of P1.x is enabled.
#1
PPS2
Port 1 Pin Power Save Bit 2
2
read-write
value1
Pin Power Save of P1.x is disabled.
#0
value2
Pin Power Save of P1.x is enabled.
#1
PPS3
Port 1 Pin Power Save Bit 3
3
read-write
value1
Pin Power Save of P1.x is disabled.
#0
value2
Pin Power Save of P1.x is enabled.
#1
PPS4
Port 1 Pin Power Save Bit 4
4
read-write
value1
Pin Power Save of P1.x is disabled.
#0
value2
Pin Power Save of P1.x is enabled.
#1
PPS5
Port 1 Pin Power Save Bit 5
5
read-write
value1
Pin Power Save of P1.x is disabled.
#0
value2
Pin Power Save of P1.x is enabled.
#1
PPS6
Port 1 Pin Power Save Bit 6
6
read-write
value1
Pin Power Save of P1.x is disabled.
#0
value2
Pin Power Save of P1.x is enabled.
#1
PORT2
Port 2
PORTS
0x0
0x0
0x100
registers
n
HWSEL
Port 2 Pin Hardware Select Register
0x74
32
read-write
n
0x0
0x0
HW0
Port 2 Pin Hardware Select Bit 0
0
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW1
Port 2 Pin Hardware Select Bit 1
2
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW10
Port 2 Pin Hardware Select Bit 10
20
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW11
Port 2 Pin Hardware Select Bit 11
22
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW2
Port 2 Pin Hardware Select Bit 2
4
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW3
Port 2 Pin Hardware Select Bit 3
6
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW4
Port 2 Pin Hardware Select Bit 4
8
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW5
Port 2 Pin Hardware Select Bit 5
10
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW6
Port 2 Pin Hardware Select Bit 6
12
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW7
Port 2 Pin Hardware Select Bit 7
14
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW8
Port 2 Pin Hardware Select Bit 8
16
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
HW9
Port 2 Pin Hardware Select Bit 9
18
1
read-write
value1
Software control only.
#00
value2
HW0 control path can override the software configuration.
#01
value3
HW1 control path can override the software configuration.
#10
IN
Port 2 Input Register
0x24
32
read-write
n
0x0
0x0
P0
Port 2 Input Bit 0
0
read-only
value1
The input level of P2.x is 0.
#0
value2
The input level of P2.x is 1.
#1
P1
Port 2 Input Bit 1
1
read-only
value1
The input level of P2.x is 0.
#0
value2
The input level of P2.x is 1.
#1
P10
Port 2 Input Bit 10
10
read-only
value1
The input level of P2.x is 0.
#0
value2
The input level of P2.x is 1.
#1
P11
Port 2 Input Bit 11
11
read-only
value1
The input level of P2.x is 0.
#0
value2
The input level of P2.x is 1.
#1
P2
Port 2 Input Bit 2
2
read-only
value1
The input level of P2.x is 0.
#0
value2
The input level of P2.x is 1.
#1
P3
Port 2 Input Bit 3
3
read-only
value1
The input level of P2.x is 0.
#0
value2
The input level of P2.x is 1.
#1
P4
Port 2 Input Bit 4
4
read-only
value1
The input level of P2.x is 0.
#0
value2
The input level of P2.x is 1.
#1
P5
Port 2 Input Bit 5
5
read-only
value1
The input level of P2.x is 0.
#0
value2
The input level of P2.x is 1.
#1
P6
Port 2 Input Bit 6
6
read-only
value1
The input level of P2.x is 0.
#0
value2
The input level of P2.x is 1.
#1
P7
Port 2 Input Bit 7
7
read-only
value1
The input level of P2.x is 0.
#0
value2
The input level of P2.x is 1.
#1
P8
Port 2 Input Bit 8
8
read-only
value1
The input level of P2.x is 0.
#0
value2
The input level of P2.x is 1.
#1
P9
Port 2 Input Bit 9
9
read-only
value1
The input level of P2.x is 0.
#0
value2
The input level of P2.x is 1.
#1
IOCR0
Port 2 Input/Output Control Register 0
0x10
32
read-write
n
0x0
0x0
PC0
Port Control for Port n Pin 0 to 3
3
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC1
Port Control for Port n Pin 0 to 3
11
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC2
Port Control for Port n Pin 0 to 3
19
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC3
Port Control for Port n Pin 0 to 3
27
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
IOCR4
Port 2 Input/Output Control Register 4
0x14
32
read-write
n
0x0
0x0
PC4
Port Control for Port n Pin 4 to 7
3
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC5
Port Control for Port n Pin 4 to 7
11
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC6
Port Control for Port n Pin 4 to 7
19
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC7
Port Control for Port n Pin 4 to 7
27
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
IOCR8
Port 2 Input/Output Control Register 8
0x18
32
read-write
n
0x0
0x0
PC10
Port Control for Port n Pin 8 to 11
19
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC11
Port Control for Port n Pin 8 to 11
27
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC8
Port Control for Port n Pin 8 to 11
3
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
PC9
Port Control for Port n Pin 8 to 11
11
4
read-write
value1
Input - No internal pull device active
#00000
value2
Input - Internal pull-down device active
#00001
value3
Input - Internal pull-up device active
#00010
value4
Input - No internal pull device, Pn_OUTx = input value
#00011
value5
Input inverted - No internal pull device active
#00100
value6
Input inverted - Internal pull-down device active
#00101
value7
Input inverted - Internal pull-up device active
#00110
value8
Input inverted - No internal pull device, Pn_OUTx = input value
#00111
value9
Output Push-Pull - General-purpose output
#10000
value10
Output Push-Pull - Alternate output function 1
#10001
value11
Output Push-Pull - Alternate output function 2
#10010
value12
Output Push-Pull - Alternate output function 3
#10011
value13
Output Push-Pull - Alternate output function 4
#10100
value14
Output Push-Pull - Alternate output function 5
#10101
value15
Output Push-Pull - Alternate output function 6
#10110
value16
Output Push-Pull - Alternate output function 7
#10111
value17
Output Open Drain - General-purpose output
#11000
value18
Output Open Drain - Alternate output function 1
#11001
value19
Output Open Drain - Alternate output function 2
#11010
value20
Output Open Drain - Alternate output function 3
#11011
value21
Output Open Drain - Alternate output function 4
#11100
value22
Output Open Drain - Alternate output function 5
#11101
value23
Output Open Drain - Alternate output function 6
#11110
value24
Output Open Drain - Alternate output function 7
#11111
OMR
Port 2 Output Modification Register
0x4
32
read-write
n
0x0
0x0
PR0
Port 2 Reset Bit 0
16
write-only
PR1
Port 2 Reset Bit 1
17
write-only
PR10
Port 2 Reset Bit 10
26
write-only
PR11
Port 2 Reset Bit 11
27
write-only
PR2
Port 2 Reset Bit 2
18
write-only
PR3
Port 2 Reset Bit 3
19
write-only
PR4
Port 2 Reset Bit 4
20
write-only
PR5
Port 2 Reset Bit 5
21
write-only
PR6
Port 2 Reset Bit 6
22
write-only
PR7
Port 2 Reset Bit 7
23
write-only
PR8
Port 2 Reset Bit 8
24
write-only
PR9
Port 2 Reset Bit 9
25
write-only
PS0
Port 2 Set Bit 0
0
write-only
PS1
Port 2 Set Bit 1
1
write-only
PS10
Port 2 Set Bit 10
10
write-only
PS11
Port 2 Set Bit 11
11
write-only
PS2
Port 2 Set Bit 2
2
write-only
PS3
Port 2 Set Bit 3
3
write-only
PS4
Port 2 Set Bit 4
4
write-only
PS5
Port 2 Set Bit 5
5
write-only
PS6
Port 2 Set Bit 6
6
write-only
PS7
Port 2 Set Bit 7
7
write-only
PS8
Port 2 Set Bit 8
8
write-only
PS9
Port 2 Set Bit 9
9
write-only
OUT
Port 2 Output Register
0x0
32
read-write
n
0x0
0x0
P0
Port 2 Output Bit 0
0
read-write
value1
The output level of P2.x is 0.
#0
value2
The output level of P2.x is 1.
#1
P1
Port 2 Output Bit 1
1
read-write
value1
The output level of P2.x is 0.
#0
value2
The output level of P2.x is 1.
#1
P10
Port 2 Output Bit 10
10
read-write
value1
The output level of P2.x is 0.
#0
value2
The output level of P2.x is 1.
#1
P11
Port 2 Output Bit 11
11
read-write
value1
The output level of P2.x is 0.
#0
value2
The output level of P2.x is 1.
#1
P2
Port 2 Output Bit 2
2
read-write
value1
The output level of P2.x is 0.
#0
value2
The output level of P2.x is 1.
#1
P3
Port 2 Output Bit 3
3
read-write
value1
The output level of P2.x is 0.
#0
value2
The output level of P2.x is 1.
#1
P4
Port 2 Output Bit 4
4
read-write
value1
The output level of P2.x is 0.
#0
value2
The output level of P2.x is 1.
#1
P5
Port 2 Output Bit 5
5
read-write
value1
The output level of P2.x is 0.
#0
value2
The output level of P2.x is 1.
#1
P6
Port 2 Output Bit 6
6
read-write
value1
The output level of P2.x is 0.
#0
value2
The output level of P2.x is 1.
#1
P7
Port 2 Output Bit 7
7
read-write
value1
The output level of P2.x is 0.
#0
value2
The output level of P2.x is 1.
#1
P8
Port 2 Output Bit 8
8
read-write
value1
The output level of P2.x is 0.
#0
value2
The output level of P2.x is 1.
#1
P9
Port 2 Output Bit 9
9
read-write
value1
The output level of P2.x is 0.
#0
value2
The output level of P2.x is 1.
#1
PDISC
Port 2 Pin Function Decision Control Register
0x60
32
read-write
n
0x0
0x0
PDIS0
Pad Disable for Port 2 Pin 0
0
read-write
value1
Digital Pad input is enabled. Analog and digital input/output path active.
#0
value2
Digital Pad input is disabled. Analog input path active. (default)
#1
PDIS1
Pad Disable for Port 2 Pin 1
1
read-write
value1
Digital Pad input is enabled. Analog and digital input/output path active.
#0
value2
Digital Pad input is disabled. Analog input path active. (default)
#1
PDIS10
Pad Disable for Port 2 Pin 10
10
read-write
value1
Digital Pad input is enabled. Analog and digital input/output path active.
#0
value2
Digital Pad input is disabled. Analog input path active. (default)
#1
PDIS11
Pad Disable for Port 2 Pin 11
11
read-write
value1
Digital Pad input is enabled. Analog and digital input/output path active.
#0
value2
Digital Pad input is disabled. Analog input path active. (default)
#1
PDIS2
Pad Disable for Port 2 Pin 2
2
read-write
value1
Digital Pad input is enabled. Analog and digital input path active.
#0
value2
Digital Pad input is disabled. Analog input path active. (default)
#1
PDIS3
Pad Disable for Port 2 Pin 3
3
read-write
value1
Digital Pad input is enabled. Analog and digital input path active.
#0
value2
Digital Pad input is disabled. Analog input path active. (default)
#1
PDIS4
Pad Disable for Port 2 Pin 4
4
read-write
value1
Digital Pad input is enabled. Analog and digital input path active.
#0
value2
Digital Pad input is disabled. Analog input path active. (default)
#1
PDIS5
Pad Disable for Port 2 Pin 5
5
read-write
value1
Digital Pad input is enabled. Analog and digital input path active.
#0
value2
Digital Pad input is disabled. Analog input path active. (default)
#1
PDIS6
Pad Disable for Port 2 Pin 6
6
read-write
value1
Digital Pad input is enabled. Analog and digital input path active.
#0
value2
Digital Pad input is disabled. Analog input path active. (default)
#1
PDIS7
Pad Disable for Port 2 Pin 7
7
read-write
value1
Digital Pad input is enabled. Analog and digital input path active.
#0
value2
Digital Pad input is disabled. Analog input path active. (default)
#1
PDIS8
Pad Disable for Port 2 Pin 8
8
read-write
value1
Digital Pad input is enabled. Analog and digital input path active.
#0
value2
Digital Pad input is disabled. Analog input path active. (default)
#1
PDIS9
Pad Disable for Port 2 Pin 9
9
read-write
value1
Digital Pad input is enabled. Analog and digital input path active.
#0
value2
Digital Pad input is disabled. Analog input path active. (default)
#1
PHCR0
Port 2 Pad Hysteresis Control Register 0
0x40
32
read-write
n
0x0
0x0
PH0
Pad Hysteresis for Pn.0
2
read-write
PH1
Pad Hysteresis for Pn.1
6
read-write
PH2
Pad Hysteresis for Pn.2
10
read-write
PH3
Pad Hysteresis for Pn.3
14
read-write
PH4
Pad Hysteresis for Pn.4
18
read-write
PH5
Pad Hysteresis for Pn.5
22
read-write
PH6
Pad Hysteresis for Pn.6
26
read-write
PH7
Pad Hysteresis for Pn.7
30
read-write
PHCR1
Port 2 Pad Hysteresis Control Register 1
0x44
32
read-write
n
0x0
0x0
PH10
Pad Hysteresis for P2.10
10
read-write
PH11
Pad Hysteresis for P2.11
14
read-write
PH8
Pad Hysteresis for P2.8
2
read-write
PH9
Pad Hysteresis for P2.9
6
read-write
PPS
Port 2 Pin Power Save Register
0x70
32
read-write
n
0x0
0x0
PPS0
Port 2 Pin Power Save Bit 0
0
read-write
value1
Pin Power Save of P2.x is disabled.
#0
value2
Pin Power Save of P2.x is enabled.
#1
PPS1
Port 2 Pin Power Save Bit 1
1
read-write
value1
Pin Power Save of P2.x is disabled.
#0
value2
Pin Power Save of P2.x is enabled.
#1
PPS10
Port 2 Pin Power Save Bit 10
10
read-write
value1
Pin Power Save of P2.x is disabled.
#0
value2
Pin Power Save of P2.x is enabled.
#1
PPS11
Port 2 Pin Power Save Bit 11
11
read-write
value1
Pin Power Save of P2.x is disabled.
#0
value2
Pin Power Save of P2.x is enabled.
#1
PPS2
Port 2 Pin Power Save Bit 2
2
read-write
value1
Pin Power Save of P2.x is disabled.
#0
value2
Pin Power Save of P2.x is enabled.
#1
PPS3
Port 2 Pin Power Save Bit 3
3
read-write
value1
Pin Power Save of P2.x is disabled.
#0
value2
Pin Power Save of P2.x is enabled.
#1
PPS4
Port 2 Pin Power Save Bit 4
4
read-write
value1
Pin Power Save of P2.x is disabled.
#0
value2
Pin Power Save of P2.x is enabled.
#1
PPS5
Port 2 Pin Power Save Bit 5
5
read-write
value1
Pin Power Save of P2.x is disabled.
#0
value2
Pin Power Save of P2.x is enabled.
#1
PPS6
Port 2 Pin Power Save Bit 6
6
read-write
value1
Pin Power Save of P2.x is disabled.
#0
value2
Pin Power Save of P2.x is enabled.
#1
PPS7
Port 2 Pin Power Save Bit 7
7
read-write
value1
Pin Power Save of P2.x is disabled.
#0
value2
Pin Power Save of P2.x is enabled.
#1
PPS8
Port 2 Pin Power Save Bit 8
8
read-write
value1
Pin Power Save of P2.x is disabled.
#0
value2
Pin Power Save of P2.x is enabled.
#1
PPS9
Port 2 Pin Power Save Bit 9
9
read-write
value1
Pin Power Save of P2.x is disabled.
#0
value2
Pin Power Save of P2.x is enabled.
#1
PPB
Cortex-M0 Private Peripheral Block
PPB
0x0
0x0
0x1000
registers
n
AIRCR
Application Interrupt and Reset Control Register
0xD0C
32
read-write
n
0x0
0x0
ENDIANNESS
Data Endianness
15
read-only
value1
Little-endian
#0
SYSRESETREQ
System Reset Request
2
write-only
value1
No effect.
#0
value2
Requests a system level reset.
#1
VECTKEY
Register Key
16
15
read-write
CCR
Configuration and Control Register
0xD14
32
read-write
n
0x0
0x0
STKALIGN
Stack Alignment
9
read-only
UNALIGN_TRP
Unaligned Access Traps
3
read-only
CPUID
CPUID Base Register
0xD00
32
read-write
n
0x0
0x0
Architecture
Architecture
16
3
read-only
value1
ARMv6-M
0xC
Implementer
Implementer Code
24
7
read-only
value1
ARM
0x41
PartNo
Part Number of the Processor
4
11
read-only
value1
Cortex-M0
0xC20
Revision
Revision Number
0
3
read-only
value1
Patch 0
0x0
Variant
Variant Number
20
3
read-only
value1
Revision 0
0x0
ICSR
Interrupt Control and State Register
0xD04
32
read-write
n
0x0
0x0
ISRPENDING
Interrupt Pending Flag
22
read-only
value1
Interrupt not pending
#0
value2
Interrupt pending.
#1
PENDSTCLR
SysTick Exception Clear-pending
25
write-only
value1
No effect
#0
value2
removes the pending state from the SysTick exception.
#1
PENDSTSET
SysTick Exception Set-pending
26
read-write
value1
SysTick exception is not pending
0
value2
SysTick exception is pending.
1
PENDSVCLR
PendSV Clear Pending
27
write-only
value1
Do not clear.
#0
value2
Removes pending state from PendSV exception.
#1
PENDSVSET
PendSV Set Pending
28
read-write
value1
PendSV exception is not pending.
#0
value2
PendSV excepton is pending.
#1
VECTACTIVE
Active Exception Number
0
5
read-only
value1
Thread mode
0x00
VECTPENDING
Pending Exception Number
12
5
read-only
value1
No pending exceptions
0x0
NVIC_ICER
IInterrupt Clear-enable Register
0x180
32
read-write
n
0x0
0x0
CLRENA
Interrupt Node Clear-enable
0
31
read-write
value1
Read: Interrupt node disabled. Write: No effect
#0
value2
Read: Interrupt node enabled. Write: Disable interrupt node.
#1
NVIC_ICPR
Interrupt Clear-pending Register
0x280
32
read-write
n
0x0
0x0
CLRPEND
Interrupt Node Clear-pending
0
31
read-write
value1
Read: Interrupt node is not pending. Write: No effect.
#0
value2
Read: Interrupt node is pending. Write: Remove interrupt state from pending.
#1
NVIC_IPR0
Interrupt Priority Register 0
0x400
32
read-write
n
0x0
0x0
PRI_0
Priority, Byte Offset 0
0
7
read-write
PRI_1
Priority, Byte Offset 1
8
7
read-write
PRI_2
Priority, Byte Offset 2
16
7
read-write
PRI_3
Priority, Byte Offset 3
24
7
read-write
NVIC_IPR1
Interrupt Priority Register 1
0x404
32
read-write
n
0x0
0x0
PRI_0
Priority, Byte Offset 0
0
7
read-write
PRI_1
Priority, Byte Offset 1
8
7
read-write
PRI_2
Priority, Byte Offset 2
16
7
read-write
PRI_3
Priority, Byte Offset 3
24
7
read-write
NVIC_IPR2
Interrupt Priority Register 2
0x408
32
read-write
n
0x0
0x0
PRI_0
Priority, Byte Offset 0
0
7
read-write
PRI_1
Priority, Byte Offset 1
8
7
read-write
PRI_2
Priority, Byte Offset 2
16
7
read-write
PRI_3
Priority, Byte Offset 3
24
7
read-write
NVIC_IPR3
Interrupt Priority Register 3
0x40C
32
read-write
n
0x0
0x0
PRI_0
Priority, Byte Offset 0
0
7
read-write
PRI_1
Priority, Byte Offset 1
8
7
read-write
PRI_2
Priority, Byte Offset 2
16
7
read-write
PRI_3
Priority, Byte Offset 3
24
7
read-write
NVIC_IPR4
Interrupt Priority Register 4
0x410
32
read-write
n
0x0
0x0
PRI_0
Priority, Byte Offset 0
0
7
read-write
PRI_1
Priority, Byte Offset 1
8
7
read-write
PRI_2
Priority, Byte Offset 2
16
7
read-write
PRI_3
Priority, Byte Offset 3
24
7
read-write
NVIC_IPR5
Interrupt Priority Register 5
0x414
32
read-write
n
0x0
0x0
PRI_0
Priority, Byte Offset 0
0
7
read-write
PRI_1
Priority, Byte Offset 1
8
7
read-write
PRI_2
Priority, Byte Offset 2
16
7
read-write
PRI_3
Priority, Byte Offset 3
24
7
read-write
NVIC_IPR6
Interrupt Priority Register 6
0x418
32
read-write
n
0x0
0x0
PRI_0
Priority, Byte Offset 0
0
7
read-write
PRI_1
Priority, Byte Offset 1
8
7
read-write
PRI_2
Priority, Byte Offset 2
16
7
read-write
PRI_3
Priority, Byte Offset 3
24
7
read-write
NVIC_IPR7
Interrupt Priority Register 7
0x41C
32
read-write
n
0x0
0x0
PRI_0
Priority, Byte Offset 0
0
7
read-write
PRI_1
Priority, Byte Offset 1
8
7
read-write
PRI_2
Priority, Byte Offset 2
16
7
read-write
PRI_3
Priority, Byte Offset 3
24
7
read-write
NVIC_ISER
Interrupt Set-enable Register
0x100
32
read-write
n
0x0
0x0
SETENA
Interrupt Node Set-enable
0
31
read-write
value1
Read: Interrupt node disabled. Write: No effect.
#0
value2
Read: Interrupt node enabled. Write: Enable interrupt node
#1
NVIC_ISPR
Interrupt Set-pending Register
0x200
32
read-write
n
0x0
0x0
SETPEND
Interrupt Node Set-pending
0
31
read-write
value1
Read: Interrupt node is not pending. Write: No effect
#0
value2
Read: Interrupt node is pending. Write: Change interrupt state to pending.
#1
SCR
System Control Register
0xD10
32
read-write
n
0x0
0x0
SEVONPEND
Send Event on Pending bit
4
read-write
value1
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
#0
value2
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
#1
SLEEPDEEP
Low Power Sleep Mode
2
read-write
value1
Sleep
#0
value2
Deep sleep
#1
SLEEPONEXIT
Sleep-on-exit
1
read-write
value1
Do not sleep when returning to Thread mode.
#0
value2
Enter sleep, or deep sleep, on return from an ISR to Thread mode.
#1
SHCSR
System Handler Control and State Register
0xD24
32
read-write
n
0x0
0x0
SVCALLPENDED
SVCall Pending bit
15
read-write
value1
SVCall is not pending.
#0
value2
SVCall is pending.
#1
SHPR2
System Handler Priority Register 2
0xD1C
32
read-write
n
0x0
0x0
PRI_11
Priority of System Handler 11
24
7
read-write
SHPR3
System Handler Priority Register 3
0xD20
32
read-write
n
0x0
0x0
PRI_14
Priority of System Handler 14
16
7
read-write
PRI_15
Priority of System Handler 15
24
7
read-write
SYST_CALIB
SysTick Calibration Value Register
0x1C
32
read-write
n
0x0
0x0
NOREF
Reference Clock
31
read-only
SKEW
Clock Skew
30
read-only
TENMS
10 Milliseconds
0
23
read-only
SYST_CSR
SysTick Control and Status Register
0x10
32
read-write
n
0x0
0x0
CLKSOURCE
Clock Source
2
read-write
value1
External clock.
#0
value2
Processor clock.
#1
COUNTFLAG
Counter Flag
16
read-write
ENABLE
Counter Enable
0
read-write
value1
Counter disabled.
#0
value2
Counter enabled.
#1
TICKINT
SysTick Exception Request
1
read-write
value1
Counting down to zero does not assert the SysTick exception request.
#0
value2
Counting down to zero to assert the SysTick exception request.
#1
SYST_CVR
SysTick Current Value Register
0x18
32
read-write
n
0x0
0x0
CURRENT
SysTick Counter Current Value
0
23
read-write
SYST_RVR
SysTick Reload Value Register
0x14
32
read-write
n
0x0
0x0
RELOAD
Reload Value
0
23
read-write
PRNG
PRNG Unit
PRNG
0x0
0x0
0x10
registers
n
CHK
PRNG Status Check Register
0x4
16
read-write
n
0x0
0x0
RDV
Random Data / Key Valid Flag
0
read-only
value1
New random data block is not yet ready to be read. In ) this flag is set to #0 while loading is in progress.
#0
value2
Random data block is valid. In key loading mode this value indicates that the next partial key word can be written to PRNG_WORD.
#1
CTRL
PRNG Control Register
0xC
16
read-write
n
0x0
0x0
KLD
Key Load Operation Mode
3
read-write
value1
Streaming mode (default)
#0
value2
Key loading mode
#1
RDBS
Random Data Block Size
1
1
read-write
value1
Reset state (no random data block size defined), value of PRNG_WORD is undefined.
#00
value2
8 bits in PRNG_WORD.RDATA[7:0]
#01
value3
16 bits in PRNG_WORD.RDATA[15:0]
#10
WORD
PRNG Word Register
0x0
16
read-write
n
0x0
0x0
RDATA
Random Data
0
15
read-write
RTC
Real Time Clock
RTC
0x0
0x0
0x100
registers
n
ATIM0
RTC Alarm Time Register 0
0x18
32
read-write
n
0x0
0x0
ADA
Alarm Days Compare Value
24
4
read-write
AHO
Alarm Hours Compare Value
16
4
read-write
AMI
Alarm Minutes Compare Value
8
5
read-write
ASE
Alarm Seconds Compare Value
0
5
read-write
ATIM1
RTC Alarm Time Register 1
0x1C
32
read-write
n
0x0
0x0
AMO
Alarm Month Compare Value
8
3
read-write
AYE
Alarm Year Compare Value
16
15
read-write
CLRSR
RTC Clear Service Request Register
0x14
32
read-write
n
0x0
0x0
RAI
Raw Alarm Interrupt Clear
8
write-only
RPDA
Raw Periodic Days Interrupt Clear
3
write-only
RPHO
Raw Periodic Hours Interrupt Clear
2
write-only
RPMI
Raw Periodic Minutes Interrupt Clear
1
write-only
RPMO
Raw Periodic Months Interrupt Clear
5
write-only
RPSE
Raw Periodic Seconds Interrupt Clear
0
write-only
RPYE
Raw Periodic Years Interrupt Clear
6
write-only
CTR
RTC Control Register
0x4
32
read-write
n
0x0
0x0
DIV
Divider Value
16
15
read-write
ENB
RTC Module Enable
0
read-write
SUS
Debug Suspend Control
1
read-write
ID
RTC Module ID Register
0x0
32
read-write
n
0x0
0x0
MOD_NUMBER
Module Number Value
16
15
read-only
MOD_REV
Module Revision Number
0
7
read-only
MOD_TYPE
Module Type
8
7
read-only
MSKSR
RTC Service Request Mask Register
0x10
32
read-write
n
0x0
0x0
MAI
Alarm Interrupt Mask
8
read-write
MPDA
Periodic Days Interrupt Mask
3
read-write
MPHO
Periodic Hours Interrupt Mask
2
read-write
MPMI
Periodic Minutes Interrupt Mask
1
read-write
MPMO
Periodic Months Interrupt Mask
5
read-write
MPSE
Periodic Seconds Interrupt Mask
0
read-write
MPYE
Periodic Years Interrupt Mask
6
read-write
RAWSTAT
RTC Raw Service Request Register
0x8
32
read-write
n
0x0
0x0
RAI
Alarm Service Request
8
read-only
RPDA
Raw Periodic Days Service Request
3
read-only
RPHO
Raw Periodic Hours Service Request
2
read-only
RPMI
Raw Periodic Minutes Service Request
1
read-only
RPMO
Raw Periodic Months Service Request
5
read-only
RPSE
Raw Periodic Seconds Service Request
0
read-only
RPYE
Raw Periodic Years Service Request
6
read-only
STSSR
RTC Service Request Status Register
0xC
32
read-write
n
0x0
0x0
SAI
Alarm Service Request Status after masking
8
read-only
SPDA
Periodic Days Service Request Status after masking
3
read-only
SPHO
Periodic Hours Service Request Status after masking
2
read-only
SPMI
Periodic Minutes Service Request Status after masking
1
read-only
SPMO
Periodic Months Service Request Status after masking
5
read-only
SPSE
Periodic Seconds Service Request Status after masking
0
read-only
SPYE
Periodic Years Service Request Status after masking
6
read-only
TIM0
RTC Time Register 0
0x20
32
read-write
n
0x0
0x0
DA
Days Time Value
24
4
read-write
HO
Hours Time Value
16
4
read-write
MI
Minutes Time Value
8
5
read-write
SE
Seconds Time Value
0
5
read-write
TIM1
RTC Time Register 1
0x24
32
read-write
n
0x0
0x0
DAWE
Days of Week Time Value
0
2
read-write
MO
Month Time Value
8
3
read-write
YE
Year Time Value
16
15
read-write
SCU_ANALOG
System Control Unit
SCU
0x0
0x0
0x100
registers
n
ANAOFFSET
DCO1 Offset Register
0x6C
16
read-write
n
0x0
0x0
ADJL_OFFSET
ADJL Offset register
0
3
read-write
value1
- 3.75%, typ.
0x0
value2
- 2.85%, typ.
0x1
value3
0, default
0x4
value4
+ 0.95%, typ.
0x5
value5
+ 3.75%, typ.
0x8
ANATSECTRL
Temperature Sensor Control Register
0x24
16
read-write
n
0x0
0x0
TSE_EN
Temperature sensor enable
0
read-write
value1
Temperature sensor is disabled
#0
value2
Temperature sensor is switched on
#1
ANATSEIH
Temperature Sensor High Temperature Interrupt Register
0x30
16
read-write
n
0x0
0x0
TSE_IH
Counter value for high temperature interrupt
0
15
read-write
ANATSEIL
Temperature Sensor Low Temperature Interrupt Register
0x34
16
read-write
n
0x0
0x0
TSE_IL
Counter value for low temperature interrupt
0
15
read-write
ANATSEMON
Temperature Sensor Counter2 Monitor Register
0x40
16
read-write
n
0x0
0x0
TSE_MON
Monitor Counter2 value; loaded by TSE_DONE
0
15
read-only
ANAVDEL
Voltage Detector Control Register
0x50
16
read-write
n
0x0
0x0
VDEL_EN
VDEL unit Enable
4
read-write
value1
VDEL is disabled
#0
value2
VDEL is active
#1
VDEL_SELECT
VDEL Range Select
0
1
read-write
value1
2.25V
#00
value2
3.0V
#01
value3
4.4V
#10
VDEL_TIM_ADJ
VDEL Timing Setting
2
1
read-write
value1
typ 1us - slowest response time
#00
value2
typ 500n
#01
value3
typ 250n
#10
value4
no delay - fastest response time.
#11
SCU_CLK
System Control Unit
SCU_CLK
0x0
0x0
0x100
registers
n
CGATCLR0
Peripheral 0 Clock Gating Clear
0x10
32
read-write
n
0x0
0x0
CCU40
CCU40 Gating Clear
2
write-only
value1
no effect
#0
value2
disable gating
#1
RTC
RTC Gating Clear
10
write-only
value1
no effect
#0
value2
disable gating
#1
USIC0
USIC0 Gating Clear
3
write-only
value1
no effect
#0
value2
disable gating
#1
VADC
VADC and SHS Gating Clear
0
write-only
value1
no effect
#0
value2
disable gating
#1
WDT
WDT Gating Clear
9
write-only
value1
no effect
#0
value2
disable gating
#1
CGATSET0
Peripheral 0 Clock Gating Set
0xC
32
read-write
n
0x0
0x0
CCU40
CCU40 Gating Set
2
write-only
value1
no effect
#0
value2
enable gating
#1
RTC
RTC Gating Set
10
write-only
value1
no effect
#0
value2
enable gating
#1
USIC0
USIC0 Gating Set
3
write-only
value1
no effect
#0
value2
enable gating
#1
VADC
VADC and SHS Gating Set
0
write-only
value1
no effect
#0
value2
enable gating
#1
WDT
WDT Gating Set
9
write-only
value1
no effect
#0
value2
enable gating
#1
CGATSTAT0
Peripheral 0 Clock Gating Status
0x8
32
read-write
n
0x0
0x0
CCU40
CCU40 Gating Status
2
read-only
value1
gating de-asserted
#0
value2
gating asserted
#1
RTC
RTC Gating Status
10
read-only
value1
gating de-asserted
#0
value2
gating asserted
#1
USIC0
USIC0 Gating Status
3
read-only
value1
gating de-asserted
#0
value2
gating asserted
#1
VADC
VADC and SHS Gating Status
0
read-only
value1
gating de-asserted
#0
value2
gating asserted
#1
WDT
WDT Gating Status
9
read-only
value1
gating de-asserted
#0
value2
gating asserted
#1
CLKCR
Clock Control Register
0x0
32
read-write
n
0x0
0x0
CNTADJ
Counter Adjustment
20
9
read-write
value1
1 clock cycles of the DCO1, 64MHz clock
0x000
value2
2 clock cycles of the DCO1, 64MHz clock
0x001
value3
3 clock cycles of the DCO1, 64MHz clock
0x002
value4
4 clock cycles of the DCO1, 64MHz clock
0x003
value5
5 clock cycles of the DCO1, 64MHz clock
0x004
value6
1023 clock cycles of the DCO1, 64MHz clock
0x3FE
value7
1024 clock cycles of the DCO1, 64MHz clock
0x3FF
FDIV
Fractional Divider Selection
0
7
read-write
IDIV
Divider Selection
8
7
read-write
value1
Divider is bypassed.
0x00
value2
1; MCLK = 32 MHz
0x01
value3
2; MCLK = 16 MHz
0x02
value4
3; MCLK = 10.67 MHz
0x03
value5
4; MCLK = 8 MHz
0x04
value6
254; MCLK = 126 kHz
0xFE
value7
255; MCLK = 125.5 kHz
0xFF
PCLKSEL
PCLK Clock Select
16
read-write
value1
PCLK = MCLK
#0
value2
PCLK = 2 x MCLK
#1
RTCCLKSEL
RTC Clock Select
17
2
read-write
VDDC2HIGH
VDDC too high
31
read-only
value1
VDDC is not too high
#0
value2
VDDC is too high
#1
VDDC2LOW
VDDC too low
30
read-only
value1
VDDC is not too low and the fractional divider input clock is running at the targeted frequency
#0
value2
VDDC is too low and the fractional divider input clock is not running at the targeted frequency
#1
OSCCSR
Oscillator Control and Status Register
0x14
32
read-write
n
0x0
0x0
OSC2H
Oscillator Valid High Status Bit
1
read-only
value1
The OSC frequency is usable
#0
value2
The OSC frequency is not usable. Frequency is too high.
#1
OSC2L
Oscillator Valid Low Status Bit
0
read-only
value1
The OSC frequency is usable
#0
value2
The OSC frequency is not usable. Frequency is too low.
#1
OWDEN
Oscillator Watchdog Enable
17
read-write
value1
The Oscillator Watchdog is disabled
#0
value2
The Oscillator Watchdog is enabled
#1
OWDRES
Oscillator Watchdog Reset
16
read-write
value1
The Oscillator Watchdog is not cleared and remains active
#0
value2
The Oscillator Watchdog is cleared and restarted. The OSC2L and OSC2H flag will be held in the last value until it is updated after 3 standby clock cycles.
#1
PWRSVCR
Power Save Control Register
0x4
32
read-write
n
0x0
0x0
FPD
Flash Power Down
0
read-write
value1
no effect
#0
value2
Flash power down when entering power save mode. Upon wake-up, CPU is able to fetch code from flash.
#1
SCU_GENERAL
System Control Unit
SCU_GENERAL
0x0
0x0
0x200
registers
n
CCUCON
CCU Control Register
0x30
32
read-write
n
0x0
0x0
GSC40
Global Start Control CCU40
0
read-write
DBGROMID
Debug System ROM ID Register
0x0
32
read-write
n
0x0
0x0
MANUFID
Manufactory Identity
1
10
read-only
PARTNO
Part Number
12
15
read-only
VERSION
Product version
28
3
read-only
ID
SCU Module ID Register
0x8
32
read-write
n
0x0
0x0
MOD_NUMBER
Module Number Value
16
15
read-only
MOD_REV
Module Revision Number
0
7
read-only
MOD_TYPE
Module Type
8
7
read-only
IDCHIP
Chip ID Register
0x4
32
read-write
n
0x0
0x0
IDCHIP
CHIP ID
0
31
read-only
MIRRSTS
Mirror Update Status Register
0x48
32
read-write
n
0x0
0x0
RTC_ATIM0
RTC ATIM0 Mirror Register Update Status
1
read-only
RTC_ATIM1
RTC ATIM1 Mirror Register Update Status
2
read-only
RTC_CTR
RTC CTR Mirror Register Update Status
0
read-only
RTC_TIM0
RTC TIM0 Mirror Register Update Status
3
read-only
RTC_TIM1
RTC TIM1 Mirror Register Update Status
4
read-only
PASSWD
Password Register
0x24
32
read-write
n
0x0
0x0
MODE
Bit Protection Scheme Control Bits
0
1
read-write
value1
Scheme disabled - direct access to the protected bits is allowed.
#00
value2
Scheme enabled - the bit field PASS has to be written with the passwords to open and close the access to the protected bits. (Default)
#11
PASS
Password Bits
3
4
write-only
value2
Opens access to writing of all protected bits.
#10011
value3
Closes access to writing of all protected bits.
#10101
value1
Enables writing of the bit field MODE.
#11000
PROTS
Bit Protection Signal Status Bit
2
read-only
value1
Software is able to write to all protected bits.
#0
value2
Software is unable to write to any of the protected bits.
#1
PMTSR
Parity Memory Test Select Register
0x54
32
read-write
n
0x0
0x0
MTENS
Parity Test Enable Control for 16kbytes SRAM
0
read-write
value1
standard operation
#0
value2
generate an inverted parity bit during a write operation
#1
SSW0
SSW Register 0
0x14
32
read-write
n
0x0
0x0
DAT
SSW Data
0
31
read-write
SCU_INTERRUPT
System Control Unit
SCU_INTERRUPT
0x0
0x0
0x10
registers
n
SCU_0
System Control
0
SCU_1
System Control
1
SCU_2
System Control
2
SRCLR
SCU Service Request Clear
0x8
32
read-write
n
0x0
0x0
AI
RTC Alarm Interrupt Clear
2
write-only
FLCMPLTI
Flash Operation Complete Interrupt Clear
20
write-only
FLECC2I
Flash Double Bit ECC Interrupt Clear
19
write-only
LOCI
Loss of Clock Interrupt Clear
16
write-only
PESRAMI
16kbytes SRAM Parity Error Interrupt Clear
17
write-only
PEU0I
USIC0 SRAM Parity Error Interrupt Clear
18
write-only
PI
RTC Periodic Interrupt Clear
1
write-only
PRWARN
WDT pre-warning Interrupt Clear
0
write-only
RTC_ATIM0
RTC ATIM0 Mirror Register Update Clear
25
write-only
RTC_ATIM1
RTC ATIM1 Mirror Register Update Clear
26
write-only
RTC_CTR
RTC CTR Mirror Register Update Clear
24
write-only
RTC_TIM0
RTC TIM0 Mirror Register Update Clear
27
write-only
RTC_TIM1
RTC TIM1 Mirror Register Update Clear
28
write-only
SBYCLKFI
Standby Clock Failure Interrupt Clear
22
write-only
TSE_DONE
TSE Measurement Done Interrupt Clear
29
write-only
TSE_HIGH
TSE Compare High Temperature Interrupt Clear
30
write-only
TSE_LOW
TSE Compare Low Temperature Interrupt Clear
31
write-only
VCLIPI
VCLIP Interrupt Clear
21
write-only
VDDPI
VDDP pre-warning Interrupt Clear
3
write-only
VDROPI
VDROP Interrupt Clear
7
write-only
SRMSK
SCU Service Request Mask
0x4
32
read-write
n
0x0
0x0
FLECC2I
Flash Double Bit ECC Interrupt Mask
19
read-write
LOCI
Loss of Clock Interrupt Mask
16
read-write
PESRAMI
16kbytes SRAM Parity Error Interrupt Mask
17
read-write
PEU0I
USIC0 SRAM Parity Error Interrupt Mask
18
read-write
PRWARN
WDT pre-warning Interrupt Mask
0
read-write
RTC_ATIM0
RTC ATIM0 Mirror Register Update Mask
25
read-write
RTC_ATIM1
RTC ATIM1 Mirror Register Update Mask
26
read-write
RTC_CTR
RTC CTR Mirror Register Update Mask
24
read-write
RTC_TIM0
RTC TIM0 Mirror Register Update Mask
27
read-write
RTC_TIM1
RTC TIM1 Mirror Register Update Mask
28
read-write
SBYCLKFI
Standby Clock Failure Interrupt Mask
22
read-write
TSE_DONE
TSE Measurement Done Interrupt Mask
29
read-write
TSE_HIGH
TSE Compare High Temperature Interrupt Mask
30
read-write
TSE_LOW
TSE Compare Low Temperature Interrupt Mask
31
read-write
VCLIPI
VCLIP Interrupt Mask
21
read-write
VDDPI
VDDP pre-warning Interrupt Mask
3
read-write
VDROPI
VDROP Interrupt Mask
7
read-write
SRRAW
SCU Raw Service Request Status
0x0
32
read-write
n
0x0
0x0
AI
RTC Raw Alarm Event Status Before Masking
2
read-only
FLCMPLTI
Flash Operation Complete Event Status Before Masking
20
read-only
FLECC2I
Flash Double Bit ECC Event Status Before Masking
19
read-only
LOCI
Loss of Clock Event Status Before Masking
16
read-only
PESRAMI
16kbytes SRAM Parity Error Event Status Before Masking
17
read-only
PEU0I
USIC0 SRAM Parity Error Event Status Before Masking
18
read-only
PI
RTC Raw Periodic Event Status Before Masking
1
read-only
PRWARN
WDT pre-warning Event Status Before Masking
0
read-only
RTC_ATIM0
RTC ATIM0 Mirror Register Update Status Before Masking
25
read-only
RTC_ATIM1
RTC ATIM1 Mirror Register Update Status Before Masking
26
read-only
RTC_CTR
RTC CTR Mirror Register Update Status Before Masking
24
read-only
RTC_TIM0
RTC TIM0 Mirror Register Update Before Masking
27
read-only
RTC_TIM1
RTC TIM1 Mirror Register Update Status Before Masking
28
read-only
SBYCLKFI
Standby Clock Failure Event Status Before Masking
22
read-only
TSE_DONE
TSE Measurement Done Event Status Before Masking
29
read-only
TSE_HIGH
TSE Compare High Temperature Event Status Before Masking
30
read-only
TSE_LOW
TSE Compare Low Temperature Event Status Before Masking
31
read-only
VCLIPI
VCLIP Event Status Before Masking
21
read-only
VDDPI
VDDP pre-warning Event Status Before Masking
3
read-only
VDROPI
VDROP Event Status Before Masking
7
read-only
SRSET
SCU Service Request Set
0xC
32
read-write
n
0x0
0x0
AI
RTC Alarm Interrupt Set
2
write-only
FLCMPLTI
Flash Operation Complete Interrupt Set
20
write-only
FLECC2I
Flash Double Bit ECC Interrupt Set
19
write-only
LOCI
Loss of Clock Interrupt Set
16
write-only
PESRAMI
16kbytes SRAM Parity Error Interrupt Set
17
write-only
PEU0I
USIC0 SRAM Parity Error Interrupt Set
18
write-only
PI
RTC Periodic Interrupt Set
1
write-only
PRWARN
WDT pre-warning Interrupt Set
0
write-only
RTC_ATIM0
RTC ATIM0 Mirror Register Update Set
25
write-only
RTC_ATIM1
RTC ATIM1 Mirror Register Update Set
26
write-only
RTC_CTR
RTC CTR Mirror Register Update Set
24
write-only
RTC_TIM0
RTC TIM0 Mirror Register Update Set
27
write-only
RTC_TIM1
RTC TIM1 Mirror Register Update Set
28
write-only
SBYCLKFI
Standby Clock Failure Interrupt Set
22
write-only
TSE_DONE
TSE Measurement Done Interrupt Set
29
write-only
TSE_HIGH
TSE Compare High Temperature Interrupt Set
30
write-only
TSE_LOW
TSE Compare Low Temperature Interrupt Set
31
write-only
VCLIPI
VCLIP Interrupt Set
21
write-only
VDDPI
VDDP pre-warning Interrupt Set
3
write-only
VDROPI
VDROP Interrupt Set
7
write-only
SCU_POWER
System Control Unit
SCU_POWER
0x0
0x0
0x100
registers
n
VDESR
Voltage Detector Status Register
0x0
32
read-write
n
0x0
0x0
VCLIP
VCLIP Indication
0
read-only
value1
VCLIP is not active
#0
value2
VCLIP is active
#1
VDDPPW
VDDPPW Indication
1
read-only
value1
VDDP is above pre-warning threshold
#0
value2
VDDP is below pre-warningthreshold
#1
SCU_RESET
System Control Unit
SCU_RESET
0x0
0x0
0x100
registers
n
RSTCLR
RCU Reset Clear Register
0x8
32
read-write
n
0x0
0x0
LCKEN
Enable Lockup Reset
10
write-only
value1
no effect
#0
value2
Disable reset when Lockup gets asserted
#1
RSCLR
Clear Reset Status
0
write-only
value1
no effect
#0
value2
Clears field RSTSTAT.RSTSTAT
#1
RSTCON
RCU Reset Control Register
0xC
32
read-write
n
0x0
0x0
ECCRSTEN
Enable ECC Error Reset
0
read-write
value1
No reset when ECC double bit error occur
#0
value2
Reset when ECC double bit error occur
#1
LOCRSTEN
Enable Loss of Clock Reset
1
read-write
value1
No reset when loss of clock occur
#0
value2
Reset when loss of clock occur
#1
MRSTEN
Enable Master Reset
16
write-only
value1
No effect
#0
value2
Triggered Master reset
#1
SPERSTEN
Enable 16kbytes SRAM Parity Error Reset
2
read-write
value1
No reset when SRAM parity error occur
#0
value2
Reset when SRAM parity error occur
#1
U0PERSTEN
Enable USIC0 SRAM Parity Error Reset
3
read-write
value1
No reset when USIC0 memory parity error occur
#0
value2
Reset when USIC0 memory parity error occur
#1
RSTSET
RCU Reset Set Register
0x4
32
read-write
n
0x0
0x0
LCKEN
Enable Lockup Reset
10
write-only
value1
no effect
#0
value2
Enable reset when Lockup gets asserted
#1
RSTSTAT
RCU Reset Status
0x0
32
read-write
n
0x0
0x0
LCKEN
Enable Lockup Status
10
read-only
value1
Reset by Lockup disabled
#0
value2
Reset by Lockup enabled
#1
RSTSTAT
Reset Status Information
0
9
read-only
SHS0
Sample and Hold ADC Sequencer
SHS0
0x0
0x0
0x200
registers
n
CALCTR
Calibration Control Register
0xBC
32
read-write
n
0x0
0x0
CALGNSTC
Gain Calibration Sample Time Control
8
5
read-write
CALMAX
Calibration Maximum Timing
24
5
read-write
CALORD
Calibration Order
0
read-write
value1
Do conversions then calibration
#0
value2
Do calibration then conversions
#1
SUCAL
Start-Up Calibration
31
write-only
value1
No action
#0
value2
Initiate the start-up calibration phase (indication in bitfield SHSCFG.STATE)
#1
SUCALVAL
Startup Calibration Cycles
16
6
read-write
CALGC0
Gain Calibration Control Register 0
0xC0
32
read-write
n
0x0
0x0
CALGNVALA
Gain Calibration Value, Alternate Reference
16
13
read-write
CALGNVALS
Gain Calibration Value, Standard Reference
0
13
read-write
GNAWC
Gain Calibration Write Control, Alternate
31
write-only
value1
No write access to gain calibration parameter
#0
value2
CALGNVALA can be written
#1
GNSWC
Gain Calibration Write Control, Standard
15
write-only
value1
No write access to gain calibration parameter
#0
value2
CALGNVALS can be written
#1
CALGC1
Gain Calibration Control Register 1
0xC4
32
read-write
n
0x0
0x0
CALGNVALA
Gain Calibration Value, Alternate Reference
16
13
read-write
CALGNVALS
Gain Calibration Value, Standard Reference
0
13
read-write
GNAWC
Gain Calibration Write Control, Alternate
31
write-only
value1
No write access to gain calibration parameter
#0
value2
CALGNVALA can be written
#1
GNSWC
Gain Calibration Write Control, Standard
15
write-only
value1
No write access to gain calibration parameter
#0
value2
CALGNVALS can be written
#1
GNCTR00
Gain Control Register 00
0x180
32
read-write
n
0x0
0x0
GAIN0
Gain Control 0
0
3
read-write
value1
Gain factor = 1
#0000
value2
Gain factor = 3
#0001
value3
Gain factor = 6
#0010
value4
Gain factor = 12
#0011
GAIN1
Gain Control 1
4
3
read-write
value1
Gain factor = 1
#0000
value2
Gain factor = 3
#0001
value3
Gain factor = 6
#0010
value4
Gain factor = 12
#0011
GAIN2
Gain Control 2
8
3
read-write
value1
Gain factor = 1
#0000
value2
Gain factor = 3
#0001
value3
Gain factor = 6
#0010
value4
Gain factor = 12
#0011
GAIN3
Gain Control 3
12
3
read-write
value1
Gain factor = 1
#0000
value2
Gain factor = 3
#0001
value3
Gain factor = 6
#0010
value4
Gain factor = 12
#0011
GAIN4
Gain Control 4
16
3
read-write
value1
Gain factor = 1
#0000
value2
Gain factor = 3
#0001
value3
Gain factor = 6
#0010
value4
Gain factor = 12
#0011
GAIN5
Gain Control 5
20
3
read-write
value1
Gain factor = 1
#0000
value2
Gain factor = 3
#0001
value3
Gain factor = 6
#0010
value4
Gain factor = 12
#0011
GAIN6
Gain Control 6
24
3
read-write
value1
Gain factor = 1
#0000
value2
Gain factor = 3
#0001
value3
Gain factor = 6
#0010
value4
Gain factor = 12
#0011
GAIN7
Gain Control 7
28
3
read-write
value1
Gain factor = 1
#0000
value2
Gain factor = 3
#0001
value3
Gain factor = 6
#0010
value4
Gain factor = 12
#0011
GNCTR10
Gain Control Register 10
0x190
32
read-write
n
0x0
0x0
GAIN0
Gain Control 0
0
3
read-write
value1
Gain factor = 1
#0000
value2
Gain factor = 3
#0001
value3
Gain factor = 6
#0010
value4
Gain factor = 12
#0011
GAIN1
Gain Control 1
4
3
read-write
value1
Gain factor = 1
#0000
value2
Gain factor = 3
#0001
value3
Gain factor = 6
#0010
value4
Gain factor = 12
#0011
GAIN2
Gain Control 2
8
3
read-write
value1
Gain factor = 1
#0000
value2
Gain factor = 3
#0001
value3
Gain factor = 6
#0010
value4
Gain factor = 12
#0011
GAIN3
Gain Control 3
12
3
read-write
value1
Gain factor = 1
#0000
value2
Gain factor = 3
#0001
value3
Gain factor = 6
#0010
value4
Gain factor = 12
#0011
GAIN4
Gain Control 4
16
3
read-write
value1
Gain factor = 1
#0000
value2
Gain factor = 3
#0001
value3
Gain factor = 6
#0010
value4
Gain factor = 12
#0011
GAIN5
Gain Control 5
20
3
read-write
value1
Gain factor = 1
#0000
value2
Gain factor = 3
#0001
value3
Gain factor = 6
#0010
value4
Gain factor = 12
#0011
GAIN6
Gain Control 6
24
3
read-write
value1
Gain factor = 1
#0000
value2
Gain factor = 3
#0001
value3
Gain factor = 6
#0010
value4
Gain factor = 12
#0011
GAIN7
Gain Control 7
28
3
read-write
value1
Gain factor = 1
#0000
value2
Gain factor = 3
#0001
value3
Gain factor = 6
#0010
value4
Gain factor = 12
#0011
ID
Module Identification Register
0x8
32
read-write
n
0x0
0x0
MOD_NUMBER
Module Number
16
15
read-only
MOD_REV
Module Revision
0
7
read-only
MOD_TYPE
Module Type
8
7
read-only
LOOP
Loop Control Register
0x50
32
read-write
n
0x0
0x0
LPCH0
Loop y Channel
0
4
read-write
LPCH1
Loop y Channel
16
4
read-write
LPEN0
Loop y Enable
15
read-write
value1
Off: standard operation
0x0
value2
ON: sigma-delta-loop is active
0x1
LPEN1
Loop y Enable
31
read-write
value1
Off: standard operation
0x0
value2
ON: sigma-delta-loop is active
0x1
LPSH0
Loop y Sample&Hold Unit
8
read-write
LPSH1
Loop y Sample&Hold Unit
24
read-write
SHSCFG
SHS Configuration Register
0x40
32
read-write
n
0x0
0x0
ANOFF
Analog Converter Power Down Force
12
read-write
value1
Converter is on
#0
value2
Converter is permanently off
#1
ANRDY
Analog Converter Ready
14
read-only
value1
Converter is in power-down mode
#0
value2
Converter is operable
#1
AREF
Analog Reference Voltage Selection
10
1
read-write
value1
External reference, upper supply range
#00
value3
Internal reference, upper supply range
#10
value4
Internal reference, lower supply range
#11
DIVS
Divider Factor for the SHS Clock
0
3
read-write
value1
fSH = fCONV / 1
#0000
value2
fSH = fCONV / 2
#0001
value3
fSH = fCONV / 16
#1111
SCWC
Write Control for SHS Configuration
15
write-only
value1
No write access to SHS configuration
#0
value2
Bitfields ANOFF, AREF, DIVS can be written
#1
SP0
Sample Pending on S&H Unit x
16
read-only
value1
No sample pending
#0
value2
S&H unit x has finished the sample phase
#1
SP1
Sample Pending on S&H Unit x
17
read-only
value1
No sample pending
#0
value2
S&H unit x has finished the sample phase
#1
STATE
Current State of Sequencer
28
3
read-only
value1
Idle
#0000
value2
Offset calibration active
#0001
value3
Gain calibration active
#0010
value4
Startup calibration active
#0011
value5
Stepper process active for S&H unit 0
#1000
value6
Stepper process active for S&H unit 1
#1001
TC
Test Control
24
3
read-write
value1
Internal test functions enabled
#1011
STEPCFG
Stepper Configuration Register
0x44
32
read-write
n
0x0
0x0
KSEL0
Kernel Select
0
2
read-write
KSEL1
Kernel Select
4
2
read-write
KSEL2
Kernel Select
8
2
read-write
KSEL3
Kernel Select
12
2
read-write
KSEL4
Kernel Select
16
2
read-write
KSEL5
Kernel Select
20
2
read-write
KSEL6
Kernel Select
24
2
read-write
KSEL7
Kernel Select
28
2
read-write
SEN0
Step x Enable
3
read-write
value1
Off: This step is not part of the stepper sequence
#0
value2
Active: This step is executed during the sequence
#1
SEN1
Step x Enable
7
read-write
value1
Off: This step is not part of the stepper sequence
#0
value2
Active: This step is executed during the sequence
#1
SEN2
Step x Enable
11
read-write
value1
Off: This step is not part of the stepper sequence
#0
value2
Active: This step is executed during the sequence
#1
SEN3
Step x Enable
15
read-write
value1
Off: This step is not part of the stepper sequence
#0
value2
Active: This step is executed during the sequence
#1
SEN4
Step x Enable
19
read-write
value1
Off: This step is not part of the stepper sequence
#0
value2
Active: This step is executed during the sequence
#1
SEN5
Step x Enable
23
read-write
value1
Off: This step is not part of the stepper sequence
#0
value2
Active: This step is executed during the sequence
#1
SEN6
Step x Enable
27
read-write
value1
Off: This step is not part of the stepper sequence
#0
value2
Active: This step is executed during the sequence
#1
SEN7
Step x Enable
31
read-write
value1
Off: This step is not part of the stepper sequence
#0
value2
Active: This step is executed during the sequence
#1
TIMCFG0
Timing Configuration Register 0
0x80
32
read-write
n
0x0
0x0
AT
Accelerated Timing
0
read-write
value1
Compatible timing: Result available after standard conversion time
#0
value2
Accelerated timing: Result available as soon as converted
#1
FCRT
Fast Compare Mode Response Time
4
3
read-write
value1
Result after tADCI o 2
0x0
value2
Result after tADCI o 32
0xF
SST
Short Sample Time
8
5
read-write
value1
Compatible timing: Sample time is defined by DIVA and STC.
0x00
value2
Sample time is tADC o 1
0x01
value3
Sample time is tADC o 63
0x3F
TGEN
Timing Generator
16
13
read-only
TIMCFG1
Timing Configuration Register 1
0x84
32
read-write
n
0x0
0x0
AT
Accelerated Timing
0
read-write
value1
Compatible timing: Result available after standard conversion time
#0
value2
Accelerated timing: Result available as soon as converted
#1
FCRT
Fast Compare Mode Response Time
4
3
read-write
value1
Result after tADCI o 2
0x0
value2
Result after tADCI o 32
0xF
SST
Short Sample Time
8
5
read-write
value1
Compatible timing: Sample time is defined by DIVA and STC.
0x00
value2
Sample time is tADC o 1
0x01
value3
Sample time is tADC o 63
0x3F
TGEN
Timing Generator
16
13
read-only
USIC0
Universal Serial Interface Controller 0
USIC
0x0
0x0
0x4
registers
n
USIC0_0
Universal Serial Interface Channel (Module 0)
9
USIC0_1
Universal Serial Interface Channel (Module 0)
10
USIC0_2
Universal Serial Interface Channel (Module 0)
11
USIC0_3
Universal Serial Interface Channel (Module 0)
12
USIC0_4
Universal Serial Interface Channel (Module 0)
13
USIC0_5
Universal Serial Interface Channel (Module 0)
14
ID
Module Identification Register
0x0
32
read-write
n
0x0
0x0
MOD_NUMBER
Module Number Value
16
15
read-only
MOD_REV
Module Revision Number
0
7
read-only
MOD_TYPE
Module Type
8
7
read-only
USIC0_CH0
Universal Serial Interface Controller 0
USIC
0x0
0x0
0x200
registers
n
BRG
Baud Rate Generator Register
0x14
32
read-write
n
0x0
0x0
CLKSEL
Clock Selection
0
1
read-write
value1
The fractional divider frequency fFD is selected.
#00
value3
The trigger signal DX1T defines fPIN. Signal MCLK toggles with fPIN.
#10
value4
Signal MCLK corresponds to the DX1S signal and the frequency fPIN is derived from the rising edges of DX1S.
#11
CTQSEL
Input Selection for CTQ
6
1
read-write
value1
fCTQIN = fPDIV
#00
value2
fCTQIN = fPPP
#01
value3
fCTQIN = fSCLK
#10
value4
fCTQIN = fMCLK
#11
DCTQ
Denominator for Time Quanta Counter
10
4
read-write
MCLKCFG
Master Clock Configuration
29
read-write
value1
The passive level is 0.
#0
value2
The passive level is 1.
#1
PCTQ
Pre-Divider for Time Quanta Counter
8
1
read-write
PDIV
Divider Mode: Divider Factor to Generate fPDIV
16
9
read-write
PPPEN
Enable 2:1 Divider for fPPP
4
read-write
value1
The 2:1 divider for fPPP is disabled. fPPP = fPIN
#0
value2
The 2:1 divider for fPPP is enabled. fPPP = fMCLK = fPIN / 2.
#1
SCLKCFG
Shift Clock Output Configuration
30
1
read-write
value1
The passive level is 0 and the delay is disabled.
#00
value2
The passive level is 1 and the delay is disabled.
#01
value3
The passive level is 0 and the delay is enabled.
#10
value4
The passive level is 1 and the delay is enabled.
#11
SCLKOSEL
Shift Clock Output Select
28
read-write
value1
SCLK from the baud rate generator is selected as the SCLKOUT input source.
#0
value2
The transmit shift clock from DX1 input stage is selected as the SCLKOUT input source.
#1
TMEN
Timing Measurement Enable
3
read-write
value1
Timing measurement is disabled: The trigger signals DX0T and DX1T are ignored.
#0
value2
Timing measurement is enabled: The 10-bit counter is incremented by 1 with fPPP and stops counting when reaching its maximum value. If one of the trigger signals DX0T or DX1T become active, the counter value is captured into bit field CTV, the counter is cleared and a transmit shift event is generated.
#1
BYP
Bypass Data Register
0x100
32
read-write
n
0x0
0x0
BDATA
Bypass Data
0
15
read-write
BYPCR
Bypass Control Register
0x104
32
read-write
n
0x0
0x0
BDEN
Bypass Data Enable
10
1
read-write
value1
The transfer of bypass data is disabled.
#00
value2
The transfer of bypass data to TBUF is possible. Bypass data will be transferred to TBUF according to its priority if BDV = 1.
#01
value3
Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 0.
#10
value4
Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 1.
#11
BDSSM
Bypass Data Single Shot Mode
8
read-write
value1
The bypass data is still considered as valid after it has been loaded into TBUF. The loading of the data into TBUF does not clear BDV.
#0
value2
The bypass data is considered as invalid after it has been loaded into TBUF. The loading of the data into TBUF clears BDV.
#1
BDV
Bypass Data Valid
15
read-only
value1
The bypass data is not valid.
#0
value2
The bypass data is valid.
#1
BDVTR
Bypass Data Valid Trigger
12
read-write
value1
Bit BDV is not influenced by DX2T.
#0
value2
Bit BDV is set if DX2T is active.
#1
BHPC
Bypass Hardware Port Control
21
2
read-write
BPRIO
Bypass Priority
13
read-write
value1
The transmit FIFO data has a higher priority than the bypass data.
#0
value2
The bypass data has a higher priority than the transmit FIFO data.
#1
BSELO
Bypass Select Outputs
16
4
read-write
BWLE
Bypass Word Length
0
3
read-write
CCFG
Channel Configuration Register
0x4
32
read-write
n
0x0
0x0
ASC
ASC Protocol Available
1
read-only
value1
The ASC protocol is not available.
#0
value2
The ASC protocol is available.
#1
IIC
IIC Protocol Available
2
read-only
value1
The IIC protocol is not available.
#0
value2
The IIC protocol is available.
#1
IIS
IIS Protocol Available
3
read-only
value1
The IIS protocol is not available.
#0
value2
The IIS protocol is available.
#1
RB
Receive FIFO Buffer Available
6
read-only
value1
A receive FIFO buffer is not available.
#0
value2
A receive FIFO buffer is available.
#1
SSC
SSC Protocol Available
0
read-only
value1
The SSC protocol is not available.
#0
value2
The SSC protocol is available.
#1
TB
Transmit FIFO Buffer Available
7
read-only
value1
A transmit FIFO buffer is not available.
#0
value2
A transmit FIFO buffer is available.
#1
CCR
Channel Control Register
0x40
32
read-write
n
0x0
0x0
AIEN
Alternative Receive Interrupt Enable
15
read-write
value1
The alternative receive interrupt is disabled.
#0
value2
The alternative receive interrupt is enabled. In case of an alternative receive event, the service request output SRx indicated by INPR.AINP is activated.
#1
BRGIEN
Baud Rate Generator Interrupt Enable
16
read-write
value1
The baud rate generator interrupt is disabled.
#0
value2
The baud rate generator interrupt is enabled. In case of a baud rate generator event, the service request output SRx indicated by INPR.PINP is activated.
#1
DLIEN
Data Lost Interrupt Enable
11
read-write
value1
The data lost interrupt is disabled.
#0
value2
The data lost interrupt is enabled. In case of a data lost event, the service request output SRx indicated by INPR.PINP is activated.
#1
HPCEN
Hardware Port Control Enable
6
1
read-write
value1
The hardware port control is disabled.
#00
value2
The hardware port control is enabled for DX0 and DOUT0.
#01
value3
The hardware port control is enabled for DX3, DX0 and DOUT[1:0].
#10
value4
The hardware port control is enabled for DX0, DX[5:3] and DOUT[3:0].
#11
MODE
Operating Mode
0
3
read-write
value1
The USIC channel is disabled. All protocol-related state machines are set to an idle state.
0x0
value2
The SSC (SPI) protocol is selected.
0x1
value3
The ASC (SCI, UART) protocol is selected.
0x2
value4
The IIS protocol is selected.
0x3
value5
The IIC protocol is selected.
0x4
PM
Parity Mode
8
1
read-write
value1
The parity generation is disabled.
#00
value3
Even parity is selected (parity bit = 1 on odd number of 1s in data, parity bit = 0 on even number of 1s in data).
#10
value4
Odd parity is selected (parity bit = 0 on odd number of 1s in data, parity bit = 1 on even number of 1s in data).
#11
RIEN
Receive Interrupt Enable
14
read-write
value1
The receive interrupt is disabled.
#0
value2
The receive interrupt is enabled. In case of a receive event, the service request output SRx indicated by INPR.RINP is activated.
#1
RSIEN
Receiver Start Interrupt Enable
10
read-write
value1
The receiver start interrupt is disabled.
#0
value2
The receiver start interrupt is enabled. In case of a receiver start event, the service request output SRx indicated by INPR.TBINP is activated.
#1
TBIEN
Transmit Buffer Interrupt Enable
13
read-write
value1
The transmit buffer interrupt is disabled.
#0
value2
The transmit buffer interrupt is enabled. In case of a transmit buffer event, the service request output SRx indicated by INPR.TBINP is activated.
#1
TSIEN
Transmit Shift Interrupt Enable
12
read-write
value1
The transmit shift interrupt is disabled.
#0
value2
The transmit shift interrupt is enabled. In case of a transmit shift interrupt event, the service request output SRx indicated by INPR.TSINP is activated.
#1
CMTR
Capture Mode Timer Register
0x44
32
read-write
n
0x0
0x0
CTV
Captured Timer Value
0
9
read-write
DX0CR
Input Control Register 0
0x1C
32
read-write
n
0x0
0x0
CM
Combination Mode
10
1
read-write
value1
The trigger activation is disabled.
#00
value2
A rising edge activates DXnT.
#01
value3
A falling edge activates DXnT.
#10
value4
Both edges activate DXnT.
#11
DFEN
Digital Filter Enable
5
read-write
value1
The input signal is not digitally filtered.
#0
value2
The input signal is digitally filtered.
#1
DPOL
Data Polarity for DXn
8
read-write
value1
The input signal is not inverted.
#0
value2
The input signal is inverted.
#1
DSEL
Data Selection for Input Signal
0
2
read-write
value1
The data input DXnA is selected.
#000
value2
The data input DXnB is selected.
#001
value3
The data input DXnC is selected.
#010
value4
The data input DXnD is selected.
#011
value5
The data input DXnE is selected.
#100
value6
The data input DXnF is selected.
#101
value7
The data input DXnG is selected.
#110
value8
The data input is always 1.
#111
DSEN
Data Synchronization Enable
6
read-write
value1
The un-synchronized signal can be taken as input for the data shift unit.
#0
value2
The synchronized signal can be taken as input for the data shift unit.
#1
DXS
Synchronized Data Value
15
read-only
value1
The current value of DXnS is 0.
#0
value2
The current value of DXnS is 1.
#1
INSW
Input Switch
4
read-write
value1
The input of the data shift unit is controlled by the protocol pre-processor.
#0
value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
#1
SFSEL
Sampling Frequency Selection
9
read-write
value1
The sampling frequency is fPERIPH.
#0
value2
The sampling frequency is fFD.
#1
DX1CR
Input Control Register 1
0x20
32
read-write
n
0x0
0x0
CM
Combination Mode
10
1
read-write
value1
The trigger activation is disabled.
#00
value2
A rising edge activates DX1T.
#01
value3
A falling edge activates DX1T.
#10
value4
Both edges activate DX1T.
#11
DCEN
Delay Compensation Enable
3
read-write
value1
The receive shift clock is dependent on INSW selection.
#0
value2
The receive shift clock is connected to the selected data input line. This setting is used if delay compensation is required in SSC and IIS protocols, else DCEN should always be 0.
#1
DFEN
Digital Filter Enable
5
read-write
value1
The input signal is not digitally filtered.
#0
value2
The input signal is digitally filtered.
#1
DPOL
Data Polarity for DXn
8
read-write
value1
The input signal is not inverted.
#0
value2
The input signal is inverted.
#1
DSEL
Data Selection for Input Signal
0
2
read-write
value1
The data input DX1A is selected.
#000
value2
The data input DX1B is selected.
#001
value3
The data input DX1C is selected.
#010
value4
The data input DX1D is selected.
#011
value5
The data input DX1E is selected.
#100
value6
The data input DX1F is selected.
#101
value7
The data input DX1G is selected.
#110
value8
The data input is always 1.
#111
DSEN
Data Synchronization Enable
6
read-write
value1
The un-synchronized signal can be taken as input for the data shift unit.
#0
value2
The synchronized signal can be taken as input for the data shift unit.
#1
DXS
Synchronized Data Value
15
read-only
value1
The current value of DX1S is 0.
#0
value2
The current value of DX1S is 1.
#1
INSW
Input Switch
4
read-write
value1
The input of the data shift unit is controlled by the protocol pre-processor.
#0
value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
#1
SFSEL
Sampling Frequency Selection
9
read-write
value1
The sampling frequency is fPERIPH.
#0
value2
The sampling frequency is fFD.
#1
DX2CR
Input Control Register 2
0x24
32
read-write
n
0x0
0x0
CM
Combination Mode
10
1
read-write
value1
The trigger activation is disabled.
#00
value2
A rising edge activates DXnT.
#01
value3
A falling edge activates DXnT.
#10
value4
Both edges activate DXnT.
#11
DFEN
Digital Filter Enable
5
read-write
value1
The input signal is not digitally filtered.
#0
value2
The input signal is digitally filtered.
#1
DPOL
Data Polarity for DXn
8
read-write
value1
The input signal is not inverted.
#0
value2
The input signal is inverted.
#1
DSEL
Data Selection for Input Signal
0
2
read-write
value1
The data input DXnA is selected.
#000
value2
The data input DXnB is selected.
#001
value3
The data input DXnC is selected.
#010
value4
The data input DXnD is selected.
#011
value5
The data input DXnE is selected.
#100
value6
The data input DXnF is selected.
#101
value7
The data input DXnG is selected.
#110
value8
The data input is always 1.
#111
DSEN
Data Synchronization Enable
6
read-write
value1
The un-synchronized signal can be taken as input for the data shift unit.
#0
value2
The synchronized signal can be taken as input for the data shift unit.
#1
DXS
Synchronized Data Value
15
read-only
value1
The current value of DXnS is 0.
#0
value2
The current value of DXnS is 1.
#1
INSW
Input Switch
4
read-write
value1
The input of the data shift unit is controlled by the protocol pre-processor.
#0
value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
#1
SFSEL
Sampling Frequency Selection
9
read-write
value1
The sampling frequency is fPERIPH.
#0
value2
The sampling frequency is fFD.
#1
DX3CR
Input Control Register 3
0x28
32
read-write
n
0x0
0x0
CM
Combination Mode
10
1
read-write
value1
The trigger activation is disabled.
#00
value2
A rising edge activates DXnT.
#01
value3
A falling edge activates DXnT.
#10
value4
Both edges activate DXnT.
#11
DFEN
Digital Filter Enable
5
read-write
value1
The input signal is not digitally filtered.
#0
value2
The input signal is digitally filtered.
#1
DPOL
Data Polarity for DXn
8
read-write
value1
The input signal is not inverted.
#0
value2
The input signal is inverted.
#1
DSEL
Data Selection for Input Signal
0
2
read-write
value1
The data input DXnA is selected.
#000
value2
The data input DXnB is selected.
#001
value3
The data input DXnC is selected.
#010
value4
The data input DXnD is selected.
#011
value5
The data input DXnE is selected.
#100
value6
The data input DXnF is selected.
#101
value7
The data input DXnG is selected.
#110
value8
The data input is always 1.
#111
DSEN
Data Synchronization Enable
6
read-write
value1
The un-synchronized signal can be taken as input for the data shift unit.
#0
value2
The synchronized signal can be taken as input for the data shift unit.
#1
DXS
Synchronized Data Value
15
read-only
value1
The current value of DXnS is 0.
#0
value2
The current value of DXnS is 1.
#1
INSW
Input Switch
4
read-write
value1
The input of the data shift unit is controlled by the protocol pre-processor.
#0
value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
#1
SFSEL
Sampling Frequency Selection
9
read-write
value1
The sampling frequency is fPERIPH.
#0
value2
The sampling frequency is fFD.
#1
DX4CR
Input Control Register 4
0x2C
32
read-write
n
0x0
0x0
CM
Combination Mode
10
1
read-write
value1
The trigger activation is disabled.
#00
value2
A rising edge activates DXnT.
#01
value3
A falling edge activates DXnT.
#10
value4
Both edges activate DXnT.
#11
DFEN
Digital Filter Enable
5
read-write
value1
The input signal is not digitally filtered.
#0
value2
The input signal is digitally filtered.
#1
DPOL
Data Polarity for DXn
8
read-write
value1
The input signal is not inverted.
#0
value2
The input signal is inverted.
#1
DSEL
Data Selection for Input Signal
0
2
read-write
value1
The data input DXnA is selected.
#000
value2
The data input DXnB is selected.
#001
value3
The data input DXnC is selected.
#010
value4
The data input DXnD is selected.
#011
value5
The data input DXnE is selected.
#100
value6
The data input DXnF is selected.
#101
value7
The data input DXnG is selected.
#110
value8
The data input is always 1.
#111
DSEN
Data Synchronization Enable
6
read-write
value1
The un-synchronized signal can be taken as input for the data shift unit.
#0
value2
The synchronized signal can be taken as input for the data shift unit.
#1
DXS
Synchronized Data Value
15
read-only
value1
The current value of DXnS is 0.
#0
value2
The current value of DXnS is 1.
#1
INSW
Input Switch
4
read-write
value1
The input of the data shift unit is controlled by the protocol pre-processor.
#0
value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
#1
SFSEL
Sampling Frequency Selection
9
read-write
value1
The sampling frequency is fPERIPH.
#0
value2
The sampling frequency is fFD.
#1
DX5CR
Input Control Register 5
0x30
32
read-write
n
0x0
0x0
CM
Combination Mode
10
1
read-write
value1
The trigger activation is disabled.
#00
value2
A rising edge activates DXnT.
#01
value3
A falling edge activates DXnT.
#10
value4
Both edges activate DXnT.
#11
DFEN
Digital Filter Enable
5
read-write
value1
The input signal is not digitally filtered.
#0
value2
The input signal is digitally filtered.
#1
DPOL
Data Polarity for DXn
8
read-write
value1
The input signal is not inverted.
#0
value2
The input signal is inverted.
#1
DSEL
Data Selection for Input Signal
0
2
read-write
value1
The data input DXnA is selected.
#000
value2
The data input DXnB is selected.
#001
value3
The data input DXnC is selected.
#010
value4
The data input DXnD is selected.
#011
value5
The data input DXnE is selected.
#100
value6
The data input DXnF is selected.
#101
value7
The data input DXnG is selected.
#110
value8
The data input is always 1.
#111
DSEN
Data Synchronization Enable
6
read-write
value1
The un-synchronized signal can be taken as input for the data shift unit.
#0
value2
The synchronized signal can be taken as input for the data shift unit.
#1
DXS
Synchronized Data Value
15
read-only
value1
The current value of DXnS is 0.
#0
value2
The current value of DXnS is 1.
#1
INSW
Input Switch
4
read-write
value1
The input of the data shift unit is controlled by the protocol pre-processor.
#0
value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
#1
SFSEL
Sampling Frequency Selection
9
read-write
value1
The sampling frequency is fPERIPH.
#0
value2
The sampling frequency is fFD.
#1
FDR
Fractional Divider Register
0x10
32
read-write
n
0x0
0x0
DM
Divider Mode
14
1
read-write
value1
The divider is switched off, fFD = 0.
#00
value2
Normal divider mode selected.
#01
value3
Fractional divider mode selected.
#10
value4
The divider is switched off, fFD = 0.
#11
RESULT
Result Value
16
9
read-only
STEP
Step Value
0
9
read-write
FMR
Flag Modification Register
0x68
32
read-write
n
0x0
0x0
ATVC
Activate Bit TVC
4
write-only
value1
No action.
#0
value2
Bit TCSR.TVC is set.
#1
CRDV0
Clear Bits RDV for RBUF0
14
write-only
value1
No action.
#0
value2
Bits RBUF01SR.RDV00 and RBUF01SR.RDV10 are cleared.
#1
CRDV1
Clear Bit RDV for RBUF1
15
write-only
value1
No action.
#0
value2
Bits RBUF01SR.RDV01 and RBUF01SR.RDV11 are cleared.
#1
MTDV
Modify Transmit Data Valid
0
1
write-only
value1
No action.
#00
value2
Bit TDV is set, TE is unchanged.
#01
value3
Bits TDV and TE are cleared.
#10
SIO0
Set Interrupt Output SRx
16
write-only
value1
No action.
#0
value2
The service request output SRx is activated.
#1
SIO1
Set Interrupt Output SRx
17
write-only
value1
No action.
#0
value2
The service request output SRx is activated.
#1
SIO2
Set Interrupt Output SRx
18
write-only
value1
No action.
#0
value2
The service request output SRx is activated.
#1
SIO3
Set Interrupt Output SRx
19
write-only
value1
No action.
#0
value2
The service request output SRx is activated.
#1
SIO4
Set Interrupt Output SRx
20
write-only
value1
No action.
#0
value2
The service request output SRx is activated.
#1
SIO5
Set Interrupt Output SRx
21
write-only
value1
No action.
#0
value2
The service request output SRx is activated.
#1
INPR
Interrupt Node Pointer Register
0x18
32
read-write
n
0x0
0x0
AINP
Alternative Receive Interrupt Node Pointer
12
2
read-write
PINP
Transmit Shift Interrupt Node Pointer
16
2
read-write
value1
Output SR0 becomes activated.
#000
value2
Output SR1 becomes activated.
#001
value3
Output SR2 becomes activated.
#010
value4
Output SR3 becomes activated.
#011
value5
Output SR4 becomes activated.
#100
value6
Output SR5 becomes activated.
#101
RINP
Receive Interrupt Node Pointer
8
2
read-write
TBINP
Transmit Buffer Interrupt Node Pointer
4
2
read-write
TSINP
Transmit Shift Interrupt Node Pointer
0
2
read-write
value1
Output SR0 becomes activated.
#000
value2
Output SR1 becomes activated.
#001
value3
Output SR2 becomes activated.
#010
value4
Output SR3 becomes activated.
#011
value5
Output SR4 becomes activated.
#100
value6
Output SR5 becomes activated.
#101
IN[0]
Transmit FIFO Buffer
0x300
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[10]
Transmit FIFO Buffer
0x12DC
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[11]
Transmit FIFO Buffer
0x1488
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[12]
Transmit FIFO Buffer
0x1638
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[13]
Transmit FIFO Buffer
0x17EC
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[14]
Transmit FIFO Buffer
0x19A4
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[15]
Transmit FIFO Buffer
0x1B60
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[16]
Transmit FIFO Buffer
0x1D20
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[17]
Transmit FIFO Buffer
0x1EE4
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[18]
Transmit FIFO Buffer
0x20AC
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[19]
Transmit FIFO Buffer
0x2278
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[1]
Transmit FIFO Buffer
0x484
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[20]
Transmit FIFO Buffer
0x2448
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[21]
Transmit FIFO Buffer
0x261C
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[22]
Transmit FIFO Buffer
0x27F4
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[23]
Transmit FIFO Buffer
0x29D0
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[24]
Transmit FIFO Buffer
0x2BB0
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[25]
Transmit FIFO Buffer
0x2D94
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[26]
Transmit FIFO Buffer
0x2F7C
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[27]
Transmit FIFO Buffer
0x3168
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[28]
Transmit FIFO Buffer
0x3358
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[29]
Transmit FIFO Buffer
0x354C
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[2]
Transmit FIFO Buffer
0x60C
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[30]
Transmit FIFO Buffer
0x3744
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[31]
Transmit FIFO Buffer
0x3940
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[3]
Transmit FIFO Buffer
0x798
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[4]
Transmit FIFO Buffer
0x928
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[5]
Transmit FIFO Buffer
0xABC
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[6]
Transmit FIFO Buffer
0xC54
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[7]
Transmit FIFO Buffer
0xDF0
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[8]
Transmit FIFO Buffer
0xF90
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[9]
Transmit FIFO Buffer
0x1134
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
KSCFG
Kernel State Configuration Register
0xC
32
read-write
n
0x0
0x0
BPMODEN
Bit Protection for MODEN
1
write-only
value1
MODEN is not changed.
#0
value2
MODEN is updated with the written value.
#1
BPNOM
Bit Protection for NOMCFG
7
write-only
value1
NOMCFG is not changed.
#0
value2
NOMCFG is updated with the written value.
#1
BPSUM
Bit Protection for SUMCFG
11
write-only
value1
SUMCFG is not changed.
#0
value2
SUMCFG is updated with the written value.
#1
MODEN
Module Enable
0
read-write
value1
The module is switched off immediately (without respecting a stop condition). It does not react on mode control actions and the module clock is switched off. The module does not react on read accesses and ignores write accesses (except to KSCFG).
#0
value2
The module is switched on and can operate. After writing 1 to MODEN, it is recommended to read register KSCFG to avoid pipeline effects in the control block before accessing other Service Request Processing registers.
#1
NOMCFG
Normal Operation Mode Configuration
4
1
read-write
value1
Run mode 0 is selected.
#00
value2
Run mode 1 is selected.
#01
value3
Stop mode 0 is selected.
#10
value4
Stop mode 1 is selected.
#11
SUMCFG
Suspend Mode Configuration
8
1
read-write
OUTDR
Receiver Buffer Output Register L for Debugger
0x120
32
read-write
n
0x0
0x0
DSR
Data from Shift Register
0
15
read-only
RCI
Receive Control Information from Shift Register
16
4
read-only
OUTR
Receiver Buffer Output Register
0x11C
32
read-write
n
0x0
0x0
modifyExternal
DSR
Received Data
0
15
read-only
RCI
Receiver Control Information
16
4
read-only
PCR
Protocol Control Register
0x3C
32
read-write
n
0x0
0x0
CTR0
Protocol Control Bit 0
0
read-write
CTR1
Protocol Control Bit 1
1
read-write
CTR10
Protocol Control Bit 10
10
read-write
CTR11
Protocol Control Bit 11
11
read-write
CTR12
Protocol Control Bit 12
12
read-write
CTR13
Protocol Control Bit 13
13
read-write
CTR14
Protocol Control Bit 14
14
read-write
CTR15
Protocol Control Bit 15
15
read-write
CTR16
Protocol Control Bit 16
16
read-write
CTR17
Protocol Control Bit 17
17
read-write
CTR18
Protocol Control Bit 18
18
read-write
CTR19
Protocol Control Bit 19
19
read-write
CTR2
Protocol Control Bit 2
2
read-write
CTR20
Protocol Control Bit 20
20
read-write
CTR21
Protocol Control Bit 21
21
read-write
CTR22
Protocol Control Bit 22
22
read-write
CTR23
Protocol Control Bit 23
23
read-write
CTR24
Protocol Control Bit 24
24
read-write
CTR25
Protocol Control Bit 25
25
read-write
CTR26
Protocol Control Bit 26
26
read-write
CTR27
Protocol Control Bit 27
27
read-write
CTR28
Protocol Control Bit 28
28
read-write
CTR29
Protocol Control Bit 29
29
read-write
CTR3
Protocol Control Bit 3
3
read-write
CTR30
Protocol Control Bit 30
30
read-write
CTR31
Protocol Control Bit 31
31
read-write
CTR4
Protocol Control Bit 4
4
read-write
CTR5
Protocol Control Bit 5
5
read-write
CTR6
Protocol Control Bit 6
6
read-write
CTR7
Protocol Control Bit 7
7
read-write
CTR8
Protocol Control Bit 8
8
read-write
CTR9
Protocol Control Bit 9
9
read-write
PCR_ASCMode
Protocol Control Register [ASC Mode]
PCR
0x3C
32
read-write
n
0x0
0x0
CDEN
Collision Detection Enable
4
read-write
value1
The collision detection is disabled.
#0
value2
If a collision is detected, the transmitter stops its data transmission, outputs a 1, sets bit PSR.COL and generates a protocol interrupt. In order to allow data transmission again, PSR.COL has to be cleared by software.
#1
FEIEN
Format Error Interrupt Enable
6
read-write
value1
The interrupt generation is disabled.
#0
value2
The interrupt generation is enabled.
#1
FFIEN
Frame Finished Interrupt Enable
7
read-write
value1
The interrupt generation is disabled.
#0
value2
The interrupt generation is enabled.
#1
IDM
Idle Detection Mode
2
read-write
value1
The bus idle detection is switched off and bits PSR.TXIDLE and PSR.RXIDLE are set automatically to enable data transfers without checking the inputs before.
#0
value2
The bus is considered as idle after a number of consecutive passive bit times defined by SCTR.FLE plus 2 (in the case without parity bit) or plus 3 (in the case with parity bit).
#1
MCLK
Master Clock Enable
31
read-write
value1
The MCLK generation is disabled and the MCLK signal is 0.
#0
value2
The MCLK generation is enabled.
#1
PL
Pulse Length
13
2
read-write
value1
The pulse length is equal to the bit length (no shortened 0).
#000
value2
The pulse length of a 0 bit is 2 time quanta.
#001
value3
The pulse length of a 0 bit is 3 time quanta.
#010
value4
The pulse length of a 0 bit is 8 time quanta.
#111
RNIEN
Receiver Noise Detection Interrupt Enable
5
read-write
value1
The interrupt generation is disabled.
#0
value2
The interrupt generation is enabled.
#1
RSTEN
Receiver Status Enable
16
read-write
value1
Flag PSR[9] is not modified depending on the receiver status.
#0
value2
Flag PSR[9] is set during the complete reception of a frame.
#1
SBIEN
Synchronization Break Interrupt Enable
3
read-write
value1
The interrupt generation is disabled.
#0
value2
The interrupt generation is enabled.
#1
SMD
Sample Mode
0
read-write
value1
Only one sample is taken per bit time. The current input value is sampled.
#0
value2
Three samples are taken per bit time and a majority decision is made.
#1
SP
Sample Point
8
4
read-write
STPB
Stop Bits
1
read-write
value1
The number of stop bits is 1.
#0
value2
The number of stop bits is 2.
#1
TSTEN
Transmitter Status Enable
17
read-write
value1
Flag PSR[9] is not modified depending on the transmitter status.
#0
value2
Flag PSR[9] is set during the complete transmission of a frame.
#1
PCR_IICMode
Protocol Control Register [IIC Mode]
PCR
0x3C
32
read-write
n
0x0
0x0
ACK00
Acknowledge 00H
16
read-write
value1
The slave device is not sensitive to this address.
#0
value2
The slave device is sensitive to this address.
#1
ACKIEN
Acknowledge Interrupt Enable
30
read-write
value1
The acknowledge interrupt is disabled.
#0
value2
The acknowledge interrupt is enabled.
#1
ARLIEN
Arbitration Lost Interrupt Enable
22
read-write
value1
The arbitration lost interrupt is disabled.
#0
value2
The arbitration lost interrupt is enabled.
#1
ERRIEN
Error Interrupt Enable
24
read-write
value1
The error interrupt is disabled.
#0
value2
The error interrupt is enabled.
#1
HDEL
Hardware Delay
26
3
read-write
MCLK
Master Clock Enable
31
read-write
value1
The MCLK generation is disabled and MCLK is 0.
#0
value2
The MCLK generation is enabled.
#1
NACKIEN
Non-Acknowledge Interrupt Enable
21
read-write
value1
The non-acknowledge interrupt is disabled.
#0
value2
The non-acknowledge interrupt is enabled.
#1
PCRIEN
Stop Condition Received Interrupt Enable
20
read-write
value1
The stop condition interrupt is disabled.
#0
value2
The stop condition interrupt is enabled.
#1
RSCRIEN
Repeated Start Condition Received Interrupt Enable
19
read-write
value1
The repeated start condition interrupt is disabled.
#0
value2
The repeated start condition interrupt is enabled.
#1
SACKDIS
Slave Acknowledge Disable
25
read-write
value1
The generation of an active slave acknowledge is enabled (slave acknowledge with 0 level = more bytes can be received).
#0
value2
The generation of an active slave acknowledge is disabled (slave acknowledge with 1 level = reception stopped).
#1
SCRIEN
Start Condition Received Interrupt Enable
18
read-write
value1
The start condition interrupt is disabled.
#0
value2
The start condition interrupt is enabled.
#1
SLAD
Slave Address
0
15
read-write
SRRIEN
Slave Read Request Interrupt Enable
23
read-write
value1
The slave read request interrupt is disabled.
#0
value2
The slave read request interrupt is enabled.
#1
STIM
Symbol Timing
17
read-write
value1
A symbol contains 10 time quanta. The timing is adapted for standard mode (100 kBaud).
#0
value2
A symbol contains 25 time quanta. The timing is adapted for fast mode (400 kBaud).
#1
PCR_IISMode
Protocol Control Register [IIS Mode]
PCR
0x3C
32
read-write
n
0x0
0x0
DTEN
Data Transfers Enable
1
read-write
value1
The changes of the WA input signal are ignored and no transfers take place.
#0
value2
Transfers are enabled.
#1
DX2TIEN
DX2T Interrupt Enable
15
read-write
value1
A protocol interrupt is not generated if DX2T is active.
#0
value2
A protocol interrupt is generated if DX2T is active.
#1
ENDIEN
END Interrupt Enable
6
read-write
value1
A protocol interrupt is not activated.
#0
value2
A protocol interrupt is activated.
#1
MCLK
Master Clock Enable
31
read-write
value1
The MCLK generation is disabled and MCLK is 0.
#0
value2
The MCLK generation is enabled.
#1
SELINV
Select Inversion
2
read-write
value1
The SELOx outputs have the same polarity as the WA signal.
#0
value2
The SELOx outputs have the inverted polarity to the WA signal.
#1
TDEL
Transfer Delay
16
5
read-write
WAFEIEN
WA Falling Edge Interrupt Enable
4
read-write
value1
A protocol interrupt is not activated if a falling edge of WA is generated.
#0
value2
A protocol interrupt is activated if a falling edge of WA is generated.
#1
WAGEN
WA Generation Enable
0
read-write
value1
The IIS can be used as slave. The generation of the word address signal is disabled. The output signal WA is 0. The MCLKO signal generation depends on PCR.MCLK.
#0
value2
The IIS can be used as master. The generation of the word address signal is enabled. The signal starts with a 0 after being enabled. The generation of MCLK is enabled, independent of PCR.MCLK. After clearing WAGEN, the USIC module stops the generation of the WA signal within the next 4 WA periods.
#1
WAREIEN
WA Rising Edge Interrupt Enable
5
read-write
value1
A protocol interrupt is not activated if a rising edge of WA is generated.
#0
value2
A protocol interrupt is activated if a rising edge of WA is generated.
#1
PCR_SSCMode
Protocol Control Register [SSC Mode]
PCR
0x3C
32
read-write
n
0x0
0x0
CTQSEL1
Input Frequency Selection
4
1
read-write
value1
fCTQIN = fPDIV
#00
value2
fCTQIN = fPPP
#01
value3
fCTQIN = fSCLK
#10
value4
fCTQIN = fMCLK
#11
DCTQ1
Divider Factor DCTQ1 for Tiw and Tnf
8
4
read-write
DX2TIEN
DX2T Interrupt Enable
15
read-write
value1
A protocol interrupt is not generated if DX2T is activated.
#0
value2
A protocol interrupt is generated if DX2T is activated.
#1
FEM
Frame End Mode
3
read-write
value1
The current data frame is considered as finished when the last bit of a data word has been sent out and the transmit buffer TBUF does not contain new data (TDV = 0).
#0
value2
The MSLS signal is kept active also while no new data is available and no other end of frame condition is reached. In this case, the software can accept delays in delivering the data without automatic deactivation of MSLS in multi-word data frames.
#1
MCLK
Master Clock Enable
31
read-write
value1
The MCLK generation is disabled and output MCLK = 0.
#0
value2
The MCLK generation is enabled.
#1
MSLSEN
MSLS Enable
0
read-write
value1
The MSLS generation is disabled (MSLS = 0). This is the setting for SSC slave mode.
#0
value2
The MSLS generation is enabled. This is the setting for SSC master mode.
#1
MSLSIEN
MSLS Interrupt Enable
14
read-write
value1
A protocol interrupt is not generated if a change of signal MSLS is detected.
#0
value2
A protocol interrupt is generated if a change of signal MSLS is detected.
#1
PARIEN
Parity Error Interrupt Enable
13
read-write
value1
A protocol interrupt is not generated with the detection of a parity error.
#0
value2
A protocol interrupt is generated with the detection of a parity error.
#1
PCTQ1
Divider Factor PCTQ1 for Tiw and Tnf
6
1
read-write
SELCTR
Select Control
1
read-write
value1
The coded select mode is enabled.
#0
value2
The direct select mode is enabled.
#1
SELINV
Select Inversion
2
read-write
value1
The SELO outputs have the same polarity as the MSLS signal (active high).
#0
value2
The SELO outputs have the inverted polarity to the MSLS signal (active low).
#1
SELO
Select Output
16
7
read-write
value1
The corresponding SELOx line cannot be activated.
#0
value2
The corresponding SELOx line can be activated (according to the mode selected by SELCTR).
#1
SLPHSEL
Slave Mode Clock Phase Select
25
read-write
value1
Data bits are shifted out with the leading edge of the shift clock signal and latched in with the trailing edge.
#0
value2
The first data bit is shifted out when the data shift unit receives a low to high transition from the DX2 stage. Subsequent bits are shifted out with the trailing edge of the shift clock signal. Data bits are always latched in with the leading edge.
#1
TIWEN
Enable Inter-Word Delay Tiw
24
read-write
value1
No delay between data words of the same frame.
#0
value2
The inter-word delay Tiw is enabled and introduced between data words of the same frame.
#1
PSCR
Protocol Status Clear Register
0x4C
32
read-write
n
0x0
0x0
CAIF
Clear Alternative Receive Indication Flag
15
write-only
value1
No action
#0
value2
Flag PSR.AIF is cleared.
#1
CBRGIF
Clear Baud Rate Generator Indication Flag
16
write-only
value1
No action
#0
value2
Flag PSR.BRGIF is cleared.
#1
CDLIF
Clear Data Lost Indication Flag
11
write-only
value1
No action
#0
value2
Flag PSR.DLIF is cleared.
#1
CRIF
Clear Receive Indication Flag
14
write-only
value1
No action
#0
value2
Flag PSR.RIF is cleared.
#1
CRSIF
Clear Receiver Start Indication Flag
10
write-only
value1
No action
#0
value2
Flag PSR.RSIF is cleared.
#1
CST0
Clear Status Flag 0 in PSR
0
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST1
Clear Status Flag 1 in PSR
1
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST2
Clear Status Flag 2 in PSR
2
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST3
Clear Status Flag 3 in PSR
3
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST4
Clear Status Flag 4 in PSR
4
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST5
Clear Status Flag 5 in PSR
5
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST6
Clear Status Flag 6 in PSR
6
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST7
Clear Status Flag 7 in PSR
7
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST8
Clear Status Flag 8 in PSR
8
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST9
Clear Status Flag 9 in PSR
9
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CTBIF
Clear Transmit Buffer Indication Flag
13
write-only
value1
No action
#0
value2
Flag PSR.TBIF is cleared.
#1
CTSIF
Clear Transmit Shift Indication Flag
12
write-only
value1
No action
#0
value2
Flag PSR.TSIF is cleared.
#1
PSR
Protocol Status Register
0x48
32
read-write
n
0x0
0x0
AIF
Alternative Receive Indication Flag
15
read-write
value1
An alternative receive event has not occurred.
#0
value2
An alternative receive event has occurred.
#1
BRGIF
Baud Rate Generator Indication Flag
16
read-write
value1
A baud rate generator event has not occurred.
#0
value2
A baud rate generator event has occurred.
#1
DLIF
Data Lost Indication Flag
11
read-write
value1
A data lost event has not occurred.
#0
value2
A data lost event has occurred.
#1
RIF
Receive Indication Flag
14
read-write
value1
A receive event has not occurred.
#0
value2
A receive event has occurred.
#1
RSIF
Receiver Start Indication Flag
10
read-write
value1
A receiver start event has not occurred.
#0
value2
A receiver start event has occurred.
#1
ST0
Protocol Status Flag 0
0
read-write
ST1
Protocol Status Flag 1
1
read-write
ST2
Protocol Status Flag 2
2
read-write
ST3
Protocol Status Flag 3
3
read-write
ST4
Protocol Status Flag 4
4
read-write
ST5
Protocol Status Flag 5
5
read-write
ST6
Protocol Status Flag 6
6
read-write
ST7
Protocol Status Flag 7
7
read-write
ST8
Protocol Status Flag 8
8
read-write
ST9
Protocol Status Flag 9
9
read-write
TBIF
Transmit Buffer Indication Flag
13
read-write
value1
A transmit buffer event has not occurred.
#0
value2
A transmit buffer event has occurred.
#1
TSIF
Transmit Shift Indication Flag
12
read-write
value1
A transmit shift event has not occurred.
#0
value2
A transmit shift event has occurred.
#1
PSR_ASCMode
Protocol Status Register [ASC Mode]
PSR
0x48
32
read-write
n
0x0
0x0
AIF
Alternative Receive Indication Flag
15
read-write
value1
An alternative receive event has not occurred.
#0
value2
An alternative receive event has occurred.
#1
BRGIF
Baud Rate Generator Indication Flag
16
read-write
value1
A baud rate generator event has not occurred.
#0
value2
A baud rate generator event has occurred.
#1
BUSY
Transfer Status BUSY
9
read-only
value1
A data transfer does not take place.
#0
value2
A data transfer currently takes place.
#1
COL
Collision Detected
3
read-write
value1
A collision has not yet been detected and frame transmission is possible.
#0
value2
A collision has been detected and frame transmission is not possible.
#1
DLIF
Data Lost Indication Flag
11
read-write
value1
A data lost event has not occurred.
#0
value2
A data lost event has occurred.
#1
FER0
Format Error in Stop Bit 0
5
read-write
value1
A format error 0 has not been detected.
#0
value2
A format error 0 has been detected.
#1
FER1
Format Error in Stop Bit 1
6
read-write
value1
A format error 1 has not been detected.
#0
value2
A format error 1 has been detected.
#1
RFF
Receive Frame Finished
7
read-write
value1
The received frame is not yet finished.
#0
value2
The received frame is finished.
#1
RIF
Receive Indication Flag
14
read-write
value1
A receive event has not occurred.
#0
value2
A receive event has occurred.
#1
RNS
Receiver Noise Detected
4
read-write
value1
Receiver noise has not been detected.
#0
value2
Receiver noise has been detected.
#1
RSIF
Receiver Start Indication Flag
10
read-write
value1
A receiver start event has not occurred.
#0
value2
A receiver start event has occurred.
#1
RXIDLE
Reception Idle
1
read-write
value1
The receiver line has not yet been idle.
#0
value2
The receiver line has been idle and frame reception is possible.
#1
SBD
Synchronization Break Detected
2
read-write
value1
A synchronization break has not yet been detected.
#0
value2
A synchronization break has been detected.
#1
TBIF
Transmit Buffer Indication Flag
13
read-write
value1
A transmit buffer event has not occurred.
#0
value2
A transmit buffer event has occurred.
#1
TFF
Transmitter Frame Finished
8
read-write
value1
The transmitter frame is not yet finished.
#0
value2
The transmitter frame is finished.
#1
TSIF
Transmit Shift Indication Flag
12
read-write
value1
A transmit shift event has not occurred.
#0
value2
A transmit shift event has occurred.
#1
TXIDLE
Transmission Idle
0
read-write
value1
The transmitter line has not yet been idle.
#0
value2
The transmitter line has been idle and frame transmission is possible.
#1
PSR_IICMode
Protocol Status Register [IIC Mode]
PSR
0x48
32
read-write
n
0x0
0x0
ACK
Acknowledge Received
9
read-write
value1
An acknowledge has not been received.
#0
value2
An acknowledge has been received.
#1
AIF
Alternative Receive Indication Flag
15
read-write
value1
An alternative receive event has not occurred.
#0
value2
An alternative receive event has occurred.
#1
ARL
Arbitration Lost
6
read-write
value1
An arbitration has not been lost.
#0
value2
An arbitration has been lost.
#1
BRGIF
Baud Rate Generator Indication Flag
16
read-write
value1
A baud rate generator event has not occurred.
#0
value2
A baud rate generator event has occurred.
#1
DLIF
Data Lost Indication Flag
11
read-write
value1
A data lost event has not occurred.
#0
value2
A data lost event has occurred.
#1
ERR
Error
8
read-write
value1
An IIC error has not been detected.
#0
value2
An IIC error has been detected.
#1
NACK
Non-Acknowledge Received
5
read-write
value1
A non-acknowledge has not been received.
#0
value2
A non-acknowledge has been received.
#1
PCR
Stop Condition Received
4
read-write
value1
A stop condition has not yet been detected.
#0
value2
A stop condition has been detected.
#1
RIF
Receive Indication Flag
14
read-write
value1
A receive event has not occurred.
#0
value2
A receive event has occurred.
#1
RSCR
Repeated Start Condition Received
3
read-write
value1
A repeated start condition has not yet been detected.
#0
value2
A repeated start condition has been detected.
#1
RSIF
Receiver Start Indication Flag
10
read-write
value1
A receiver start event has not occurred.
#0
value2
A receiver start event has occurred.
#1
SCR
Start Condition Received
2
read-write
value1
A start condition has not yet been detected.
#0
value2
A start condition has been detected.
#1
SLSEL
Slave Select
0
read-write
value1
The device is not selected as slave.
#0
value2
The device is selected as slave.
#1
SRR
Slave Read Request
7
read-write
value1
A slave read request has not been detected.
#0
value2
A slave read request has been detected.
#1
TBIF
Transmit Buffer Indication Flag
13
read-write
value1
A transmit buffer event has not occurred.
#0
value2
A transmit buffer event has occurred.
#1
TSIF
Transmit Shift Indication Flag
12
read-write
value1
A transmit shift event has not occurred.
#0
value2
A transmit shift event has occurred.
#1
WTDF
Wrong TDF Code Found
1
read-write
value1
A wrong TDF code has not been found.
#0
value2
A wrong TDF code has been found.
#1
PSR_IISMode
Protocol Status Register [IIS Mode]
PSR
0x48
32
read-write
n
0x0
0x0
AIF
Alternative Receive Indication Flag
15
read-write
value1
An alternative receive event has not occurred.
#0
value2
An alternative receive event has occurred.
#1
BRGIF
Baud Rate Generator Indication Flag
16
read-write
value1
A baud rate generator event has not occurred.
#0
value2
A baud rate generator event has occurred.
#1
DLIF
Data Lost Indication Flag
11
read-write
value1
A data lost event has not occurred.
#0
value2
A data lost event has occurred.
#1
DX2S
DX2S Status
1
read-write
value1
DX2S is 0.
#0
value2
DX2S is 1.
#1
DX2TEV
DX2T Event Detected
3
read-write
value1
The DX2T signal has not been activated.
#0
value2
The DX2T signal has been activated.
#1
END
WA Generation End
6
read-write
value1
The WA generation has not yet ended (if it is running and WAGEN has been cleared).
#0
value2
The WA generation has ended (if it has been running).
#1
RIF
Receive Indication Flag
14
read-write
value1
A receive event has not occurred.
#0
value2
A receive event has occurred.
#1
RSIF
Receiver Start Indication Flag
10
read-write
value1
A receiver start event has not occurred.
#0
value2
A receiver start event has occurred.
#1
TBIF
Transmit Buffer Indication Flag
13
read-write
value1
A transmit buffer event has not occurred.
#0
value2
A transmit buffer event has occurred.
#1
TSIF
Transmit Shift Indication Flag
12
read-write
value1
A transmit shift event has not occurred.
#0
value2
A transmit shift event has occurred.
#1
WA
Word Address
0
read-write
value1
WA has been sampled 0.
#0
value2
WA has been sampled 1.
#1
WAFE
WA Falling Edge Event
4
read-write
value1
A WA falling edge has not been generated.
#0
value2
A WA falling edge has been generated.
#1
WARE
WA Rising Edge Event
5
read-write
value1
A WA rising edge has not been generated.
#0
value2
A WA rising edge has been generated.
#1
PSR_SSCMode
Protocol Status Register [SSC Mode]
PSR
0x48
32
read-write
n
0x0
0x0
AIF
Alternative Receive Indication Flag
15
read-write
value1
An alternative receive event has not occurred.
#0
value2
An alternative receive event has occurred.
#1
BRGIF
Baud Rate Generator Indication Flag
16
read-write
value1
A baud rate generator event has not occurred.
#0
value2
A baud rate generator event has occurred.
#1
DLIF
Data Lost Indication Flag
11
read-write
value1
A data lost event has not occurred.
#0
value2
A data lost event has occurred.
#1
DX2S
DX2S Status
1
read-write
value1
DX2S is 0.
#0
value2
DX2S is 1.
#1
DX2TEV
DX2T Event Detected
3
read-write
value1
The DX2T signal has not been activated.
#0
value2
The DX2T signal has been activated.
#1
MSLS
MSLS Status
0
read-write
value1
The internal signal MSLS is inactive (0).
#0
value2
The internal signal MSLS is active (1).
#1
MSLSEV
MSLS Event Detected
2
read-write
value1
The MSLS signal has not changed its state.
#0
value2
The MSLS signal has changed its state.
#1
PARERR
Parity Error Event Detected
4
read-write
value1
A parity error event has not been activated.
#0
value2
A parity error event has been activated.
#1
RIF
Receive Indication Flag
14
read-write
value1
A receive event has not occurred.
#0
value2
A receive event has occurred.
#1
RSIF
Receiver Start Indication Flag
10
read-write
value1
A receiver start event has not occurred.
#0
value2
A receiver start event has occurred.
#1
TBIF
Transmit Buffer Indication Flag
13
read-write
value1
A transmit buffer event has not occurred.
#0
value2
A transmit buffer event has occurred.
#1
TSIF
Transmit Shift Indication Flag
12
read-write
value1
A transmit shift event has not occurred.
#0
value2
A transmit shift event has occurred.
#1
RBCTR
Receiver Buffer Control Register
0x10C
32
read-write
n
0x0
0x0
ARBIEN
Alternative Receive Buffer Interrupt Enable
29
read-write
value1
The alternative receive buffer interrupt generation is disabled.
#0
value2
The alternative receive buffer interrupt generation is enabled.
#1
ARBINP
Alternative Receive Buffer Interrupt Node Pointer
19
2
read-write
value1
Output SR0 becomes activated.
#000
value2
Output SR1 becomes activated.
#001
value3
Output SR2 becomes activated.
#010
value4
Output SR3 becomes activated.
#011
value5
Output SR4 becomes activated.
#100
value6
Output SR5 becomes activated.
#101
DPTR
Data Pointer
0
5
write-only
LIMIT
Limit For Interrupt Generation
8
5
read-write
LOF
Buffer Event on Limit Overflow
28
read-write
value1
A standard receive buffer event occurs when the filling level equals the limit value and gets lower due to a read access from OUTR.
#0
value2
A standard receive buffer event occurs when the filling level equals the limit value and gets bigger due to the reception of a new data word.
#1
RBERIEN
Receive Buffer Error Interrupt Enable
31
read-write
value1
The receive buffer error interrupt generation is disabled.
#0
value2
The receive buffer error interrupt generation is enabled.
#1
RCIM
Receiver Control Information Mode
22
1
read-write
value1
RCI[4] = PERR, RCI[3:0] = WLEN
#00
value2
RCI[4] = SOF, RCI[3:0] = WLEN
#01
value3
RCI[4] = 0, RCI[3:0] = WLEN
#10
value4
RCI[4] = PERR, RCI[3] = PAR, RCI[2:1] = 00B, RCI[0] = SOF
#11
RNM
Receiver Notification Mode
27
read-write
value1
Filling level mode: A standard receive buffer event occurs when the filling level equals the limit value and changes, either due to a read access from OUTR (LOF = 0) or due to a new received data word (LOF = 1).
#0
value2
RCI mode: A standard receive buffer event occurs when register OUTR is updated with a new value if the corresponding value in OUTR.RCI[4] = 0. If OUTR.RCI[4] = 1, an alternative receive buffer event occurs instead of the standard receive buffer event.
#1
SIZE
Buffer Size
24
2
read-write
value1
The FIFO mechanism is disabled. The buffer does not accept any request for data.
#000
value2
The FIFO buffer contains 2 entries.
#001
value3
The FIFO buffer contains 4 entries.
#010
value4
The FIFO buffer contains 8 entries.
#011
value5
The FIFO buffer contains 16 entries.
#100
value6
The FIFO buffer contains 32 entries.
#101
value7
The FIFO buffer contains 64 entries.
#110
SRBIEN
Standard Receive Buffer Interrupt Enable
30
read-write
value1
The standard receive buffer interrupt generation is disabled.
#0
value2
The standard receive buffer interrupt generation is enabled.
#1
SRBINP
Standard Receive Buffer Interrupt Node Pointer
16
2
read-write
value1
Output SR0 becomes activated.
#000
value2
Output SR1 becomes activated.
#001
value3
Output SR2 becomes activated.
#010
value4
Output SR3 becomes activated.
#011
value5
Output SR4 becomes activated.
#100
value6
Output SR5 becomes activated.
#101
SRBTEN
Standard Receive Buffer Trigger Enable
15
read-write
value1
The standard receive buffer event trigger through bit TRBSR.SRBT is disabled.
#0
value2
The standard receive buffer event trigger through bit TRBSR.SRBT is enabled.
#1
SRBTM
Standard Receive Buffer Trigger Mode
14
read-write
value1
Trigger mode 0: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=RBCTR.LIMIT.
#0
value2
Trigger mode 1: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=0.
#1
RBUF
Receiver Buffer Register
0x54
32
read-write
n
0x0
0x0
modifyExternal
DSR
Received Data
0
15
read-only
RBUF0
Receiver Buffer Register 0
0x5C
32
read-write
n
0x0
0x0
DSR0
Data of Shift Registers 0[3:0]
0
15
read-only
RBUF01SR
Receiver Buffer 01 Status Register
0x64
32
read-write
n
0x0
0x0
DS0
Data Source
15
read-only
value1
The register RBUF contains the data of RBUF0 (same for associated status information).
#0
value2
The register RBUF contains the data of RBUF1 (same for associated status information).
#1
DS1
Data Source
31
read-only
value1
The register RBUF contains the data of RBUF0 (same for associated status information).
#0
value2
The register RBUF contains the data of RBUF1 (same for associated status information).
#1
PAR0
Protocol-Related Argument in RBUF0
8
read-only
PAR1
Protocol-Related Argument in RBUF1
24
read-only
PERR0
Protocol-related Error in RBUF0
9
read-only
value1
The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt.
#0
value2
The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt.
#1
PERR1
Protocol-related Error in RBUF1
25
read-only
value1
The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt.
#0
value2
The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt.
#1
RDV00
Receive Data Valid in RBUF0
13
read-only
value1
Register RBUF0 does not contain data that has not yet been read out.
#0
value2
Register RBUF0 contains data that has not yet been read out.
#1
RDV01
Receive Data Valid in RBUF1
14
read-only
value1
Register RBUF1 does not contain data that has not yet been read out.
#0
value2
Register RBUF1 contains data that has not yet been read out.
#1
RDV10
Receive Data Valid in RBUF0
29
read-only
value1
Register RBUF0 does not contain data that has not yet been read out.
#0
value2
Register RBUF0 contains data that has not yet been read out.
#1
RDV11
Receive Data Valid in RBUF1
30
read-only
value1
Register RBUF1 does not contain data that has not yet been read out.
#0
value2
Register RBUF1 contains data that has not yet been read out.
#1
SOF0
Start of Frame in RBUF0
6
read-only
value1
The data in RBUF0 has not been the first data word of a data frame.
#0
value2
The data in RBUF0 has been the first data word of a data frame.
#1
SOF1
Start of Frame in RBUF1
22
read-only
value1
The data in RBUF1 has not been the first data word of a data frame.
#0
value2
The data in RBUF1 has been the first data word of a data frame.
#1
WLEN0
Received Data Word Length in RBUF0
0
3
read-only
WLEN1
Received Data Word Length in RBUF1
16
3
read-only
RBUF1
Receiver Buffer Register 1
0x60
32
read-write
n
0x0
0x0
DSR1
Data of Shift Registers 1[3:0]
0
15
read-only
RBUFD
Receiver Buffer Register for Debugger
0x58
32
read-write
n
0x0
0x0
DSR
Data from Shift Register
0
15
read-only
RBUFSR
Receiver Buffer Status Register
0x50
32
read-write
n
0x0
0x0
DS
Data Source of RBUF or RBUFD
15
read-only
PAR
Protocol-Related Argument in RBUF or RBUFD
8
read-only
PERR
Protocol-related Error in RBUF or RBUFD
9
read-only
RDV0
Receive Data Valid in RBUF or RBUFD
13
read-only
RDV1
Receive Data Valid in RBUF or RBUFD
14
read-only
SOF
Start of Frame in RBUF or RBUFD
6
read-only
WLEN
Received Data Word Length in RBUF or RBUFD
0
3
read-only
SCTR
Shift Control Register
0x34
32
read-write
n
0x0
0x0
DOCFG
Data Output Configuration
6
1
read-write
value1
DOUTx = shift data value
#00
value2
DOUTx = inverted shift data value
#01
DSM
Data Shift Mode
2
1
read-write
value1
Receive and transmit data is shifted in and out one bit at a time through DX0 and DOUT0.
#00
value3
Receive and transmit data is shifted in and out two bits at a time through two input stages (DX0 and DX3) and DOUT[1:0] respectively.
#10
value4
Receive and transmit data is shifted in and out four bits at a time through four input stages (DX0, DX[5:3]) and DOUT[3:0] respectively.
#11
FLE
Frame Length
16
5
read-write
HPCDIR
Port Control Direction
4
read-write
value1
The pin(s) with hardware pin control enabled are selected to be in input mode.
#0
value2
The pin(s) with hardware pin control enabled are selected to be in output mode.
#1
PDL
Passive Data Level
1
read-write
value1
The passive data level is 0.
#0
value2
The passive data level is 1.
#1
SDIR
Shift Direction
0
read-write
value1
Shift LSB first. The first data bit of a data word is located at bit position 0.
#0
value2
Shift MSB first. The first data bit of a data word is located at the bit position given by bit field SCTR.WLE.
#1
TRM
Transmission Mode
8
1
read-write
value1
The shift control signal is considered as inactive and data frame transfers are not possible.
#00
value2
The shift control signal is considered active if it is at 1-level. This is the setting to be programmed to allow data transfers.
#01
value3
The shift control signal is considered active if it is at 0-level. It is recommended to avoid this setting and to use the inversion in the DX2 stage in case of a low-active signal.
#10
value4
The shift control signal is considered active without referring to the actual signal level. Data frame transfer is possible after each edge of the signal.
#11
WLE
Word Length
24
3
read-write
value1
The data word contains 1 data bit located at bit position 0.
0x0
value2
The data word contains 2 data bits located at bit positions [1:0].
0x1
value3
The data word contains 15 data bits located at bit positions [14:0].
0xE
value4
The data word contains 16 data bits located at bit positions [15:0].
0xF
TBCTR
Transmitter Buffer Control Register
0x108
32
read-write
n
0x0
0x0
ATBINP
Alternative Transmit Buffer Interrupt Node Pointer
19
2
read-write
value1
Output SR0 becomes activated.
#000
value2
Output SR1 becomes activated.
#001
value3
Output SR2 becomes activated.
#010
value4
Output SR3 becomes activated.
#011
value5
Output SR4 becomes activated.
#100
value6
Output SR5 becomes activated.
#101
DPTR
Data Pointer
0
5
write-only
LIMIT
Limit For Interrupt Generation
8
5
read-write
LOF
Buffer Event on Limit Overflow
28
read-write
value1
A standard transmit buffer event occurs when the filling level equals the limit value and gets lower due to transmission of a data word.
#0
value2
A standard transmit buffer interrupt event occurs when the filling level equals the limit value and gets bigger due to a write access to a data input location INx.
#1
SIZE
Buffer Size
24
2
read-write
value1
The FIFO mechanism is disabled. The buffer does not accept any request for data.
#000
value2
The FIFO buffer contains 2 entries.
#001
value3
The FIFO buffer contains 4 entries.
#010
value4
The FIFO buffer contains 8 entries.
#011
value5
The FIFO buffer contains 16 entries.
#100
value6
The FIFO buffer contains 32 entries.
#101
value7
The FIFO buffer contains 64 entries.
#110
STBIEN
Standard Transmit Buffer Interrupt Enable
30
read-write
value1
The standard transmit buffer interrupt generation is disabled.
#0
value2
The standard transmit buffer interrupt generation is enabled.
#1
STBINP
Standard Transmit Buffer Interrupt Node Pointer
16
2
read-write
value1
Output SR0 becomes activated.
#000
value2
Output SR1 becomes activated.
#001
value3
Output SR2 becomes activated.
#010
value4
Output SR3 becomes activated.
#011
value5
Output SR4 becomes activated.
#100
value6
Output SR5 becomes activated.
#101
STBTEN
Standard Transmit Buffer Trigger Enable
15
read-write
value1
The standard transmit buffer event trigger through bit TRBSR.STBT is disabled.
#0
value2
The standard transmit buffer event trigger through bit TRBSR.STBT is enabled.
#1
STBTM
Standard Transmit Buffer Trigger Mode
14
read-write
value1
Trigger mode 0: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.LIMIT.
#0
value2
Trigger mode 1: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.SIZE.
#1
TBERIEN
Transmit Buffer Error Interrupt Enable
31
read-write
value1
The transmit buffer error interrupt generation is disabled.
#0
value2
The transmit buffer error interrupt generation is enabled.
#1
TBUF[0]
Transmit Buffer
0x100
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[10]
Transmit Buffer
0x6DC
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[11]
Transmit Buffer
0x788
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[12]
Transmit Buffer
0x838
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[13]
Transmit Buffer
0x8EC
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[14]
Transmit Buffer
0x9A4
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[15]
Transmit Buffer
0xA60
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[16]
Transmit Buffer
0xB20
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[17]
Transmit Buffer
0xBE4
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[18]
Transmit Buffer
0xCAC
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[19]
Transmit Buffer
0xD78
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[1]
Transmit Buffer
0x184
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[20]
Transmit Buffer
0xE48
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[21]
Transmit Buffer
0xF1C
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[22]
Transmit Buffer
0xFF4
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[23]
Transmit Buffer
0x10D0
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[24]
Transmit Buffer
0x11B0
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[25]
Transmit Buffer
0x1294
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[26]
Transmit Buffer
0x137C
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[27]
Transmit Buffer
0x1468
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[28]
Transmit Buffer
0x1558
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[29]
Transmit Buffer
0x164C
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[2]
Transmit Buffer
0x20C
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[30]
Transmit Buffer
0x1744
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[31]
Transmit Buffer
0x1840
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[3]
Transmit Buffer
0x298
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[4]
Transmit Buffer
0x328
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[5]
Transmit Buffer
0x3BC
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[6]
Transmit Buffer
0x454
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[7]
Transmit Buffer
0x4F0
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[8]
Transmit Buffer
0x590
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[9]
Transmit Buffer
0x634
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TCSR
Transmit Control/Status Register
0x38
32
read-write
n
0x0
0x0
EOF
End Of Frame
6
read-write
value1
The data word in TBUF is not considered as last word of an SSC frame.
#0
value2
The data word in TBUF is considered as last word of an SSC frame.
#1
FLEMD
FLE Mode
2
read-write
value1
The automatic update of FLE is disabled.
#0
value2
The automatic update of FLE is enabled.
#1
HPCMD
Hardware Port Control Mode
4
read-write
value1
The automatic update of bits SCTR.DSM and SCTR.HPCDIR is disabled.
#0
value2
The automatic update of bits SCTR.DSM and SCTR.HPCDIR is enabled.
#1
SELMD
Select Mode
1
read-write
value1
The automatic update of PCR.CTR[23:16] is disabled.
#0
value2
The automatic update of PCR.CTR[23:16] is disabled.
#1
SOF
Start Of Frame
5
read-write
value1
The data word in TBUF is not considered as first word of a frame.
#0
value2
The data word in TBUF is considered as first word of a frame. A currently running frame is finished and MSLS becomes deactivated (respecting the programmed delays).
#1
TDEN
TBUF Data Enable
10
1
read-write
value1
A transmission start of the data word in TBUF is disabled. If a transmission is started, the passive data level is sent out.
#00
value2
A transmission of the data word in TBUF can be started if TDV = 1.
#01
value3
A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 0.
#10
value4
A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 1.
#11
TDSSM
TBUF Data Single Shot Mode
8
read-write
value1
The data word in TBUF is not considered as invalid after it has been loaded into the transmit shift register. The loading of the TBUF data into the shift register does not clear TDV.
#0
value2
The data word in TBUF is considered as invalid after it has been loaded into the shift register. In ASC and IIC mode, TDV is cleared with the TBI event, whereas in SSC and IIS mode, it is cleared with the RSI event. TDSSM = 1 has to be programmed if an optional data buffer is used.
#1
TDV
Transmit Data Valid
7
read-only
value1
The data word in TBUF is not valid for transmission.
#0
value2
The data word in TBUF is valid for transmission and a transmission start is possible. New data should not be written to a TBUFx input location while TDV = 1.
#1
TDVTR
TBUF Data Valid Trigger
12
read-write
value1
Bit TCSR.TE is permanently set.
#0
value2
Bit TCSR.TE is set if DX2T becomes active while TDV = 1.
#1
TE
Trigger Event
28
read-only
value1
The trigger event has not yet been detected. A transmission of the data word in TBUF can not be started.
#0
value2
The trigger event has been detected (or the trigger mechanism is switched off) and a transmission of the data word in TBUF can be started.
#1
TSOF
Transmitted Start Of Frame
24
read-only
value1
The latest data word transmission has not been started for the first word of a data frame.
#0
value2
The latest data word transmission has been started for the first word of a data frame.
#1
TV
Transmission Valid
26
read-only
value1
The latest start of a data word transmission has taken place while no valid data was available. As a result, the transmission of a data words with passive level (SCTR.PDL) has been started.
#0
value2
The latest start of a data word transmission has taken place with valid data from TBUF.
#1
TVC
Transmission Valid Cumulated
27
read-only
value1
Since TVC has been set, at least one data buffer underflow condition has occurred.
#0
value2
Since TVC has been set, no data buffer underflow condition has occurred.
#1
WA
Word Address
13
read-write
value1
The data word in TBUF will be transmitted after a falling edge of WA has been detected (referring to PSR.WA).
#0
value2
The data word in TBUF will be transmitted after a rising edge of WA has been detected (referring to PSR.WA).
#1
WAMD
WA Mode
3
read-write
value1
The automatic update of bit WA is disabled.
#0
value2
The automatic update of bit WA is enabled.
#1
WLEMD
WLE Mode
0
read-write
value1
The automatic update of SCTR.WLE and TCSR.EOF is disabled.
#0
value2
The automatic update of SCTR.WLE and TCSR.EOF is enabled.
#1
TRBPTR
Transmit/Receive Buffer Pointer Register
0x110
32
read-write
n
0x0
0x0
RDIPTR
Receiver Data Input Pointer
16
5
read-only
RDOPTR
Receiver Data Output Pointer
24
5
read-only
TDIPTR
Transmitter Data Input Pointer
0
5
read-only
TDOPTR
Transmitter Data Output Pointer
8
5
read-only
TRBSCR
Transmit/Receive Buffer Status Clear Register
0x118
32
read-write
n
0x0
0x0
CARBI
Clear Alternative Receive Buffer Event
2
write-only
value1
No effect.
#0
value2
Clear TRBSR.ARBI.
#1
CBDV
Clear Bypass Data Valid
10
write-only
value1
No effect.
#0
value2
Clear BYPCR.BDV.
#1
CRBERI
Clear Receive Buffer Error Event
1
write-only
value1
No effect.
#0
value2
Clear TRBSR.RBERI.
#1
CSRBI
Clear Standard Receive Buffer Event
0
write-only
value1
No effect.
#0
value2
Clear TRBSR.SRBI.
#1
CSTBI
Clear Standard Transmit Buffer Event
8
write-only
value1
No effect.
#0
value2
Clear TRBSR.STBI.
#1
CTBERI
Clear Transmit Buffer Error Event
9
write-only
value1
No effect.
#0
value2
Clear TRBSR.TBERI.
#1
FLUSHRB
Flush Receive Buffer
14
write-only
value1
No effect.
#0
value2
The receive FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic.
#1
FLUSHTB
Flush Transmit Buffer
15
write-only
value1
No effect.
#0
value2
The transmit FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic.
#1
TRBSR
Transmit/Receive Buffer Status Register
0x114
32
read-write
n
0x0
0x0
ARBI
Alternative Receive Buffer Event
2
read-write
value1
An alternative receive buffer event has not been detected.
#0
value2
An alternative receive buffer event has been detected.
#1
RBERI
Receive Buffer Error Event
1
read-write
value1
A receive buffer error event has not been detected.
#0
value2
A receive buffer error event has been detected.
#1
RBFLVL
Receive Buffer Filling Level
16
6
read-only
RBUS
Receive Buffer Busy
5
read-only
value1
The receive buffer information has been completely updated.
#0
value2
The OUTR update from the FIFO memory is ongoing. A read from OUTR will be delayed. FIFO pointers from the previous read are not yet updated.
#1
REMPTY
Receive Buffer Empty
3
read-only
value1
The receive buffer is not empty.
#0
value2
The receive buffer is empty.
#1
RFULL
Receive Buffer Full
4
read-only
value1
The receive buffer is not full.
#0
value2
The receive buffer is full.
#1
SRBI
Standard Receive Buffer Event
0
read-write
value1
A standard receive buffer event has not been detected.
#0
value2
A standard receive buffer event has been detected.
#1
SRBT
Standard Receive Buffer Event Trigger
6
read-only
value1
A standard receive buffer event is not triggered using this bit.
#0
value2
A standard receive buffer event is triggered using this bit.
#1
STBI
Standard Transmit Buffer Event
8
read-write
value1
A standard transmit buffer event has not been detected.
#0
value2
A standard transmit buffer event has been detected.
#1
STBT
Standard Transmit Buffer Event Trigger
14
read-only
value1
A standard transmit buffer event is not triggered using this bit.
#0
value2
A standard transmit buffer event is triggered using this bit.
#1
TBERI
Transmit Buffer Error Event
9
read-write
value1
A transmit buffer error event has not been detected.
#0
value2
A transmit buffer error event has been detected.
#1
TBFLVL
Transmit Buffer Filling Level
24
6
read-only
TBUS
Transmit Buffer Busy
13
read-only
value1
The transmit buffer information has been completely updated.
#0
value2
The FIFO memory update after write to INx is ongoing. A write to INx will be delayed. FIFO pointers from the previous INx write are not yet updated.
#1
TEMPTY
Transmit Buffer Empty
11
read-only
value1
The transmit buffer is not empty.
#0
value2
The transmit buffer is empty.
#1
TFULL
Transmit Buffer Full
12
read-only
value1
The transmit buffer is not full.
#0
value2
The transmit buffer is full.
#1
USIC0_CH1
Universal Serial Interface Controller 0
USIC
0x0
0x0
0x200
registers
n
BRG
Baud Rate Generator Register
0x14
32
read-write
n
0x0
0x0
CLKSEL
Clock Selection
0
1
read-write
value1
The fractional divider frequency fFD is selected.
#00
value3
The trigger signal DX1T defines fPIN. Signal MCLK toggles with fPIN.
#10
value4
Signal MCLK corresponds to the DX1S signal and the frequency fPIN is derived from the rising edges of DX1S.
#11
CTQSEL
Input Selection for CTQ
6
1
read-write
value1
fCTQIN = fPDIV
#00
value2
fCTQIN = fPPP
#01
value3
fCTQIN = fSCLK
#10
value4
fCTQIN = fMCLK
#11
DCTQ
Denominator for Time Quanta Counter
10
4
read-write
MCLKCFG
Master Clock Configuration
29
read-write
value1
The passive level is 0.
#0
value2
The passive level is 1.
#1
PCTQ
Pre-Divider for Time Quanta Counter
8
1
read-write
PDIV
Divider Mode: Divider Factor to Generate fPDIV
16
9
read-write
PPPEN
Enable 2:1 Divider for fPPP
4
read-write
value1
The 2:1 divider for fPPP is disabled. fPPP = fPIN
#0
value2
The 2:1 divider for fPPP is enabled. fPPP = fMCLK = fPIN / 2.
#1
SCLKCFG
Shift Clock Output Configuration
30
1
read-write
value1
The passive level is 0 and the delay is disabled.
#00
value2
The passive level is 1 and the delay is disabled.
#01
value3
The passive level is 0 and the delay is enabled.
#10
value4
The passive level is 1 and the delay is enabled.
#11
SCLKOSEL
Shift Clock Output Select
28
read-write
value1
SCLK from the baud rate generator is selected as the SCLKOUT input source.
#0
value2
The transmit shift clock from DX1 input stage is selected as the SCLKOUT input source.
#1
TMEN
Timing Measurement Enable
3
read-write
value1
Timing measurement is disabled: The trigger signals DX0T and DX1T are ignored.
#0
value2
Timing measurement is enabled: The 10-bit counter is incremented by 1 with fPPP and stops counting when reaching its maximum value. If one of the trigger signals DX0T or DX1T become active, the counter value is captured into bit field CTV, the counter is cleared and a transmit shift event is generated.
#1
BYP
Bypass Data Register
0x100
32
read-write
n
0x0
0x0
BDATA
Bypass Data
0
15
read-write
BYPCR
Bypass Control Register
0x104
32
read-write
n
0x0
0x0
BDEN
Bypass Data Enable
10
1
read-write
value1
The transfer of bypass data is disabled.
#00
value2
The transfer of bypass data to TBUF is possible. Bypass data will be transferred to TBUF according to its priority if BDV = 1.
#01
value3
Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 0.
#10
value4
Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 1.
#11
BDSSM
Bypass Data Single Shot Mode
8
read-write
value1
The bypass data is still considered as valid after it has been loaded into TBUF. The loading of the data into TBUF does not clear BDV.
#0
value2
The bypass data is considered as invalid after it has been loaded into TBUF. The loading of the data into TBUF clears BDV.
#1
BDV
Bypass Data Valid
15
read-only
value1
The bypass data is not valid.
#0
value2
The bypass data is valid.
#1
BDVTR
Bypass Data Valid Trigger
12
read-write
value1
Bit BDV is not influenced by DX2T.
#0
value2
Bit BDV is set if DX2T is active.
#1
BHPC
Bypass Hardware Port Control
21
2
read-write
BPRIO
Bypass Priority
13
read-write
value1
The transmit FIFO data has a higher priority than the bypass data.
#0
value2
The bypass data has a higher priority than the transmit FIFO data.
#1
BSELO
Bypass Select Outputs
16
4
read-write
BWLE
Bypass Word Length
0
3
read-write
CCFG
Channel Configuration Register
0x4
32
read-write
n
0x0
0x0
ASC
ASC Protocol Available
1
read-only
value1
The ASC protocol is not available.
#0
value2
The ASC protocol is available.
#1
IIC
IIC Protocol Available
2
read-only
value1
The IIC protocol is not available.
#0
value2
The IIC protocol is available.
#1
IIS
IIS Protocol Available
3
read-only
value1
The IIS protocol is not available.
#0
value2
The IIS protocol is available.
#1
RB
Receive FIFO Buffer Available
6
read-only
value1
A receive FIFO buffer is not available.
#0
value2
A receive FIFO buffer is available.
#1
SSC
SSC Protocol Available
0
read-only
value1
The SSC protocol is not available.
#0
value2
The SSC protocol is available.
#1
TB
Transmit FIFO Buffer Available
7
read-only
value1
A transmit FIFO buffer is not available.
#0
value2
A transmit FIFO buffer is available.
#1
CCR
Channel Control Register
0x40
32
read-write
n
0x0
0x0
AIEN
Alternative Receive Interrupt Enable
15
read-write
value1
The alternative receive interrupt is disabled.
#0
value2
The alternative receive interrupt is enabled. In case of an alternative receive event, the service request output SRx indicated by INPR.AINP is activated.
#1
BRGIEN
Baud Rate Generator Interrupt Enable
16
read-write
value1
The baud rate generator interrupt is disabled.
#0
value2
The baud rate generator interrupt is enabled. In case of a baud rate generator event, the service request output SRx indicated by INPR.PINP is activated.
#1
DLIEN
Data Lost Interrupt Enable
11
read-write
value1
The data lost interrupt is disabled.
#0
value2
The data lost interrupt is enabled. In case of a data lost event, the service request output SRx indicated by INPR.PINP is activated.
#1
HPCEN
Hardware Port Control Enable
6
1
read-write
value1
The hardware port control is disabled.
#00
value2
The hardware port control is enabled for DX0 and DOUT0.
#01
value3
The hardware port control is enabled for DX3, DX0 and DOUT[1:0].
#10
value4
The hardware port control is enabled for DX0, DX[5:3] and DOUT[3:0].
#11
MODE
Operating Mode
0
3
read-write
value1
The USIC channel is disabled. All protocol-related state machines are set to an idle state.
0x0
value2
The SSC (SPI) protocol is selected.
0x1
value3
The ASC (SCI, UART) protocol is selected.
0x2
value4
The IIS protocol is selected.
0x3
value5
The IIC protocol is selected.
0x4
PM
Parity Mode
8
1
read-write
value1
The parity generation is disabled.
#00
value3
Even parity is selected (parity bit = 1 on odd number of 1s in data, parity bit = 0 on even number of 1s in data).
#10
value4
Odd parity is selected (parity bit = 0 on odd number of 1s in data, parity bit = 1 on even number of 1s in data).
#11
RIEN
Receive Interrupt Enable
14
read-write
value1
The receive interrupt is disabled.
#0
value2
The receive interrupt is enabled. In case of a receive event, the service request output SRx indicated by INPR.RINP is activated.
#1
RSIEN
Receiver Start Interrupt Enable
10
read-write
value1
The receiver start interrupt is disabled.
#0
value2
The receiver start interrupt is enabled. In case of a receiver start event, the service request output SRx indicated by INPR.TBINP is activated.
#1
TBIEN
Transmit Buffer Interrupt Enable
13
read-write
value1
The transmit buffer interrupt is disabled.
#0
value2
The transmit buffer interrupt is enabled. In case of a transmit buffer event, the service request output SRx indicated by INPR.TBINP is activated.
#1
TSIEN
Transmit Shift Interrupt Enable
12
read-write
value1
The transmit shift interrupt is disabled.
#0
value2
The transmit shift interrupt is enabled. In case of a transmit shift interrupt event, the service request output SRx indicated by INPR.TSINP is activated.
#1
CMTR
Capture Mode Timer Register
0x44
32
read-write
n
0x0
0x0
CTV
Captured Timer Value
0
9
read-write
DX0CR
Input Control Register 0
0x1C
32
read-write
n
0x0
0x0
CM
Combination Mode
10
1
read-write
value1
The trigger activation is disabled.
#00
value2
A rising edge activates DXnT.
#01
value3
A falling edge activates DXnT.
#10
value4
Both edges activate DXnT.
#11
DFEN
Digital Filter Enable
5
read-write
value1
The input signal is not digitally filtered.
#0
value2
The input signal is digitally filtered.
#1
DPOL
Data Polarity for DXn
8
read-write
value1
The input signal is not inverted.
#0
value2
The input signal is inverted.
#1
DSEL
Data Selection for Input Signal
0
2
read-write
value1
The data input DXnA is selected.
#000
value2
The data input DXnB is selected.
#001
value3
The data input DXnC is selected.
#010
value4
The data input DXnD is selected.
#011
value5
The data input DXnE is selected.
#100
value6
The data input DXnF is selected.
#101
value7
The data input DXnG is selected.
#110
value8
The data input is always 1.
#111
DSEN
Data Synchronization Enable
6
read-write
value1
The un-synchronized signal can be taken as input for the data shift unit.
#0
value2
The synchronized signal can be taken as input for the data shift unit.
#1
DXS
Synchronized Data Value
15
read-only
value1
The current value of DXnS is 0.
#0
value2
The current value of DXnS is 1.
#1
INSW
Input Switch
4
read-write
value1
The input of the data shift unit is controlled by the protocol pre-processor.
#0
value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
#1
SFSEL
Sampling Frequency Selection
9
read-write
value1
The sampling frequency is fPERIPH.
#0
value2
The sampling frequency is fFD.
#1
DX1CR
Input Control Register 1
0x20
32
read-write
n
0x0
0x0
CM
Combination Mode
10
1
read-write
value1
The trigger activation is disabled.
#00
value2
A rising edge activates DX1T.
#01
value3
A falling edge activates DX1T.
#10
value4
Both edges activate DX1T.
#11
DCEN
Delay Compensation Enable
3
read-write
value1
The receive shift clock is dependent on INSW selection.
#0
value2
The receive shift clock is connected to the selected data input line. This setting is used if delay compensation is required in SSC and IIS protocols, else DCEN should always be 0.
#1
DFEN
Digital Filter Enable
5
read-write
value1
The input signal is not digitally filtered.
#0
value2
The input signal is digitally filtered.
#1
DPOL
Data Polarity for DXn
8
read-write
value1
The input signal is not inverted.
#0
value2
The input signal is inverted.
#1
DSEL
Data Selection for Input Signal
0
2
read-write
value1
The data input DX1A is selected.
#000
value2
The data input DX1B is selected.
#001
value3
The data input DX1C is selected.
#010
value4
The data input DX1D is selected.
#011
value5
The data input DX1E is selected.
#100
value6
The data input DX1F is selected.
#101
value7
The data input DX1G is selected.
#110
value8
The data input is always 1.
#111
DSEN
Data Synchronization Enable
6
read-write
value1
The un-synchronized signal can be taken as input for the data shift unit.
#0
value2
The synchronized signal can be taken as input for the data shift unit.
#1
DXS
Synchronized Data Value
15
read-only
value1
The current value of DX1S is 0.
#0
value2
The current value of DX1S is 1.
#1
INSW
Input Switch
4
read-write
value1
The input of the data shift unit is controlled by the protocol pre-processor.
#0
value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
#1
SFSEL
Sampling Frequency Selection
9
read-write
value1
The sampling frequency is fPERIPH.
#0
value2
The sampling frequency is fFD.
#1
DX2CR
Input Control Register 2
0x24
32
read-write
n
0x0
0x0
CM
Combination Mode
10
1
read-write
value1
The trigger activation is disabled.
#00
value2
A rising edge activates DXnT.
#01
value3
A falling edge activates DXnT.
#10
value4
Both edges activate DXnT.
#11
DFEN
Digital Filter Enable
5
read-write
value1
The input signal is not digitally filtered.
#0
value2
The input signal is digitally filtered.
#1
DPOL
Data Polarity for DXn
8
read-write
value1
The input signal is not inverted.
#0
value2
The input signal is inverted.
#1
DSEL
Data Selection for Input Signal
0
2
read-write
value1
The data input DXnA is selected.
#000
value2
The data input DXnB is selected.
#001
value3
The data input DXnC is selected.
#010
value4
The data input DXnD is selected.
#011
value5
The data input DXnE is selected.
#100
value6
The data input DXnF is selected.
#101
value7
The data input DXnG is selected.
#110
value8
The data input is always 1.
#111
DSEN
Data Synchronization Enable
6
read-write
value1
The un-synchronized signal can be taken as input for the data shift unit.
#0
value2
The synchronized signal can be taken as input for the data shift unit.
#1
DXS
Synchronized Data Value
15
read-only
value1
The current value of DXnS is 0.
#0
value2
The current value of DXnS is 1.
#1
INSW
Input Switch
4
read-write
value1
The input of the data shift unit is controlled by the protocol pre-processor.
#0
value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
#1
SFSEL
Sampling Frequency Selection
9
read-write
value1
The sampling frequency is fPERIPH.
#0
value2
The sampling frequency is fFD.
#1
DX3CR
Input Control Register 3
0x28
32
read-write
n
0x0
0x0
CM
Combination Mode
10
1
read-write
value1
The trigger activation is disabled.
#00
value2
A rising edge activates DXnT.
#01
value3
A falling edge activates DXnT.
#10
value4
Both edges activate DXnT.
#11
DFEN
Digital Filter Enable
5
read-write
value1
The input signal is not digitally filtered.
#0
value2
The input signal is digitally filtered.
#1
DPOL
Data Polarity for DXn
8
read-write
value1
The input signal is not inverted.
#0
value2
The input signal is inverted.
#1
DSEL
Data Selection for Input Signal
0
2
read-write
value1
The data input DXnA is selected.
#000
value2
The data input DXnB is selected.
#001
value3
The data input DXnC is selected.
#010
value4
The data input DXnD is selected.
#011
value5
The data input DXnE is selected.
#100
value6
The data input DXnF is selected.
#101
value7
The data input DXnG is selected.
#110
value8
The data input is always 1.
#111
DSEN
Data Synchronization Enable
6
read-write
value1
The un-synchronized signal can be taken as input for the data shift unit.
#0
value2
The synchronized signal can be taken as input for the data shift unit.
#1
DXS
Synchronized Data Value
15
read-only
value1
The current value of DXnS is 0.
#0
value2
The current value of DXnS is 1.
#1
INSW
Input Switch
4
read-write
value1
The input of the data shift unit is controlled by the protocol pre-processor.
#0
value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
#1
SFSEL
Sampling Frequency Selection
9
read-write
value1
The sampling frequency is fPERIPH.
#0
value2
The sampling frequency is fFD.
#1
DX4CR
Input Control Register 4
0x2C
32
read-write
n
0x0
0x0
CM
Combination Mode
10
1
read-write
value1
The trigger activation is disabled.
#00
value2
A rising edge activates DXnT.
#01
value3
A falling edge activates DXnT.
#10
value4
Both edges activate DXnT.
#11
DFEN
Digital Filter Enable
5
read-write
value1
The input signal is not digitally filtered.
#0
value2
The input signal is digitally filtered.
#1
DPOL
Data Polarity for DXn
8
read-write
value1
The input signal is not inverted.
#0
value2
The input signal is inverted.
#1
DSEL
Data Selection for Input Signal
0
2
read-write
value1
The data input DXnA is selected.
#000
value2
The data input DXnB is selected.
#001
value3
The data input DXnC is selected.
#010
value4
The data input DXnD is selected.
#011
value5
The data input DXnE is selected.
#100
value6
The data input DXnF is selected.
#101
value7
The data input DXnG is selected.
#110
value8
The data input is always 1.
#111
DSEN
Data Synchronization Enable
6
read-write
value1
The un-synchronized signal can be taken as input for the data shift unit.
#0
value2
The synchronized signal can be taken as input for the data shift unit.
#1
DXS
Synchronized Data Value
15
read-only
value1
The current value of DXnS is 0.
#0
value2
The current value of DXnS is 1.
#1
INSW
Input Switch
4
read-write
value1
The input of the data shift unit is controlled by the protocol pre-processor.
#0
value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
#1
SFSEL
Sampling Frequency Selection
9
read-write
value1
The sampling frequency is fPERIPH.
#0
value2
The sampling frequency is fFD.
#1
DX5CR
Input Control Register 5
0x30
32
read-write
n
0x0
0x0
CM
Combination Mode
10
1
read-write
value1
The trigger activation is disabled.
#00
value2
A rising edge activates DXnT.
#01
value3
A falling edge activates DXnT.
#10
value4
Both edges activate DXnT.
#11
DFEN
Digital Filter Enable
5
read-write
value1
The input signal is not digitally filtered.
#0
value2
The input signal is digitally filtered.
#1
DPOL
Data Polarity for DXn
8
read-write
value1
The input signal is not inverted.
#0
value2
The input signal is inverted.
#1
DSEL
Data Selection for Input Signal
0
2
read-write
value1
The data input DXnA is selected.
#000
value2
The data input DXnB is selected.
#001
value3
The data input DXnC is selected.
#010
value4
The data input DXnD is selected.
#011
value5
The data input DXnE is selected.
#100
value6
The data input DXnF is selected.
#101
value7
The data input DXnG is selected.
#110
value8
The data input is always 1.
#111
DSEN
Data Synchronization Enable
6
read-write
value1
The un-synchronized signal can be taken as input for the data shift unit.
#0
value2
The synchronized signal can be taken as input for the data shift unit.
#1
DXS
Synchronized Data Value
15
read-only
value1
The current value of DXnS is 0.
#0
value2
The current value of DXnS is 1.
#1
INSW
Input Switch
4
read-write
value1
The input of the data shift unit is controlled by the protocol pre-processor.
#0
value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
#1
SFSEL
Sampling Frequency Selection
9
read-write
value1
The sampling frequency is fPERIPH.
#0
value2
The sampling frequency is fFD.
#1
FDR
Fractional Divider Register
0x10
32
read-write
n
0x0
0x0
DM
Divider Mode
14
1
read-write
value1
The divider is switched off, fFD = 0.
#00
value2
Normal divider mode selected.
#01
value3
Fractional divider mode selected.
#10
value4
The divider is switched off, fFD = 0.
#11
RESULT
Result Value
16
9
read-only
STEP
Step Value
0
9
read-write
FMR
Flag Modification Register
0x68
32
read-write
n
0x0
0x0
ATVC
Activate Bit TVC
4
write-only
value1
No action.
#0
value2
Bit TCSR.TVC is set.
#1
CRDV0
Clear Bits RDV for RBUF0
14
write-only
value1
No action.
#0
value2
Bits RBUF01SR.RDV00 and RBUF01SR.RDV10 are cleared.
#1
CRDV1
Clear Bit RDV for RBUF1
15
write-only
value1
No action.
#0
value2
Bits RBUF01SR.RDV01 and RBUF01SR.RDV11 are cleared.
#1
MTDV
Modify Transmit Data Valid
0
1
write-only
value1
No action.
#00
value2
Bit TDV is set, TE is unchanged.
#01
value3
Bits TDV and TE are cleared.
#10
SIO0
Set Interrupt Output SRx
16
write-only
value1
No action.
#0
value2
The service request output SRx is activated.
#1
SIO1
Set Interrupt Output SRx
17
write-only
value1
No action.
#0
value2
The service request output SRx is activated.
#1
SIO2
Set Interrupt Output SRx
18
write-only
value1
No action.
#0
value2
The service request output SRx is activated.
#1
SIO3
Set Interrupt Output SRx
19
write-only
value1
No action.
#0
value2
The service request output SRx is activated.
#1
SIO4
Set Interrupt Output SRx
20
write-only
value1
No action.
#0
value2
The service request output SRx is activated.
#1
SIO5
Set Interrupt Output SRx
21
write-only
value1
No action.
#0
value2
The service request output SRx is activated.
#1
INPR
Interrupt Node Pointer Register
0x18
32
read-write
n
0x0
0x0
AINP
Alternative Receive Interrupt Node Pointer
12
2
read-write
PINP
Transmit Shift Interrupt Node Pointer
16
2
read-write
value1
Output SR0 becomes activated.
#000
value2
Output SR1 becomes activated.
#001
value3
Output SR2 becomes activated.
#010
value4
Output SR3 becomes activated.
#011
value5
Output SR4 becomes activated.
#100
value6
Output SR5 becomes activated.
#101
RINP
Receive Interrupt Node Pointer
8
2
read-write
TBINP
Transmit Buffer Interrupt Node Pointer
4
2
read-write
TSINP
Transmit Shift Interrupt Node Pointer
0
2
read-write
value1
Output SR0 becomes activated.
#000
value2
Output SR1 becomes activated.
#001
value3
Output SR2 becomes activated.
#010
value4
Output SR3 becomes activated.
#011
value5
Output SR4 becomes activated.
#100
value6
Output SR5 becomes activated.
#101
IN[0]
Transmit FIFO Buffer
0x300
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[10]
Transmit FIFO Buffer
0x12DC
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[11]
Transmit FIFO Buffer
0x1488
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[12]
Transmit FIFO Buffer
0x1638
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[13]
Transmit FIFO Buffer
0x17EC
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[14]
Transmit FIFO Buffer
0x19A4
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[15]
Transmit FIFO Buffer
0x1B60
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[16]
Transmit FIFO Buffer
0x1D20
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[17]
Transmit FIFO Buffer
0x1EE4
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[18]
Transmit FIFO Buffer
0x20AC
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[19]
Transmit FIFO Buffer
0x2278
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[1]
Transmit FIFO Buffer
0x484
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[20]
Transmit FIFO Buffer
0x2448
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[21]
Transmit FIFO Buffer
0x261C
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[22]
Transmit FIFO Buffer
0x27F4
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[23]
Transmit FIFO Buffer
0x29D0
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[24]
Transmit FIFO Buffer
0x2BB0
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[25]
Transmit FIFO Buffer
0x2D94
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[26]
Transmit FIFO Buffer
0x2F7C
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[27]
Transmit FIFO Buffer
0x3168
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[28]
Transmit FIFO Buffer
0x3358
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[29]
Transmit FIFO Buffer
0x354C
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[2]
Transmit FIFO Buffer
0x60C
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[30]
Transmit FIFO Buffer
0x3744
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[31]
Transmit FIFO Buffer
0x3940
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[3]
Transmit FIFO Buffer
0x798
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[4]
Transmit FIFO Buffer
0x928
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[5]
Transmit FIFO Buffer
0xABC
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[6]
Transmit FIFO Buffer
0xC54
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[7]
Transmit FIFO Buffer
0xDF0
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[8]
Transmit FIFO Buffer
0xF90
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
IN[9]
Transmit FIFO Buffer
0x1134
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
write-only
KSCFG
Kernel State Configuration Register
0xC
32
read-write
n
0x0
0x0
BPMODEN
Bit Protection for MODEN
1
write-only
value1
MODEN is not changed.
#0
value2
MODEN is updated with the written value.
#1
BPNOM
Bit Protection for NOMCFG
7
write-only
value1
NOMCFG is not changed.
#0
value2
NOMCFG is updated with the written value.
#1
BPSUM
Bit Protection for SUMCFG
11
write-only
value1
SUMCFG is not changed.
#0
value2
SUMCFG is updated with the written value.
#1
MODEN
Module Enable
0
read-write
value1
The module is switched off immediately (without respecting a stop condition). It does not react on mode control actions and the module clock is switched off. The module does not react on read accesses and ignores write accesses (except to KSCFG).
#0
value2
The module is switched on and can operate. After writing 1 to MODEN, it is recommended to read register KSCFG to avoid pipeline effects in the control block before accessing other Service Request Processing registers.
#1
NOMCFG
Normal Operation Mode Configuration
4
1
read-write
value1
Run mode 0 is selected.
#00
value2
Run mode 1 is selected.
#01
value3
Stop mode 0 is selected.
#10
value4
Stop mode 1 is selected.
#11
SUMCFG
Suspend Mode Configuration
8
1
read-write
OUTDR
Receiver Buffer Output Register L for Debugger
0x120
32
read-write
n
0x0
0x0
DSR
Data from Shift Register
0
15
read-only
RCI
Receive Control Information from Shift Register
16
4
read-only
OUTR
Receiver Buffer Output Register
0x11C
32
read-write
n
0x0
0x0
modifyExternal
DSR
Received Data
0
15
read-only
RCI
Receiver Control Information
16
4
read-only
PCR
Protocol Control Register
0x3C
32
read-write
n
0x0
0x0
CTR0
Protocol Control Bit 0
0
read-write
CTR1
Protocol Control Bit 1
1
read-write
CTR10
Protocol Control Bit 10
10
read-write
CTR11
Protocol Control Bit 11
11
read-write
CTR12
Protocol Control Bit 12
12
read-write
CTR13
Protocol Control Bit 13
13
read-write
CTR14
Protocol Control Bit 14
14
read-write
CTR15
Protocol Control Bit 15
15
read-write
CTR16
Protocol Control Bit 16
16
read-write
CTR17
Protocol Control Bit 17
17
read-write
CTR18
Protocol Control Bit 18
18
read-write
CTR19
Protocol Control Bit 19
19
read-write
CTR2
Protocol Control Bit 2
2
read-write
CTR20
Protocol Control Bit 20
20
read-write
CTR21
Protocol Control Bit 21
21
read-write
CTR22
Protocol Control Bit 22
22
read-write
CTR23
Protocol Control Bit 23
23
read-write
CTR24
Protocol Control Bit 24
24
read-write
CTR25
Protocol Control Bit 25
25
read-write
CTR26
Protocol Control Bit 26
26
read-write
CTR27
Protocol Control Bit 27
27
read-write
CTR28
Protocol Control Bit 28
28
read-write
CTR29
Protocol Control Bit 29
29
read-write
CTR3
Protocol Control Bit 3
3
read-write
CTR30
Protocol Control Bit 30
30
read-write
CTR31
Protocol Control Bit 31
31
read-write
CTR4
Protocol Control Bit 4
4
read-write
CTR5
Protocol Control Bit 5
5
read-write
CTR6
Protocol Control Bit 6
6
read-write
CTR7
Protocol Control Bit 7
7
read-write
CTR8
Protocol Control Bit 8
8
read-write
CTR9
Protocol Control Bit 9
9
read-write
PCR_ASCMode
Protocol Control Register [ASC Mode]
PCR
0x3C
32
read-write
n
0x0
0x0
CDEN
Collision Detection Enable
4
read-write
value1
The collision detection is disabled.
#0
value2
If a collision is detected, the transmitter stops its data transmission, outputs a 1, sets bit PSR.COL and generates a protocol interrupt. In order to allow data transmission again, PSR.COL has to be cleared by software.
#1
FEIEN
Format Error Interrupt Enable
6
read-write
value1
The interrupt generation is disabled.
#0
value2
The interrupt generation is enabled.
#1
FFIEN
Frame Finished Interrupt Enable
7
read-write
value1
The interrupt generation is disabled.
#0
value2
The interrupt generation is enabled.
#1
IDM
Idle Detection Mode
2
read-write
value1
The bus idle detection is switched off and bits PSR.TXIDLE and PSR.RXIDLE are set automatically to enable data transfers without checking the inputs before.
#0
value2
The bus is considered as idle after a number of consecutive passive bit times defined by SCTR.FLE plus 2 (in the case without parity bit) or plus 3 (in the case with parity bit).
#1
MCLK
Master Clock Enable
31
read-write
value1
The MCLK generation is disabled and the MCLK signal is 0.
#0
value2
The MCLK generation is enabled.
#1
PL
Pulse Length
13
2
read-write
value1
The pulse length is equal to the bit length (no shortened 0).
#000
value2
The pulse length of a 0 bit is 2 time quanta.
#001
value3
The pulse length of a 0 bit is 3 time quanta.
#010
value4
The pulse length of a 0 bit is 8 time quanta.
#111
RNIEN
Receiver Noise Detection Interrupt Enable
5
read-write
value1
The interrupt generation is disabled.
#0
value2
The interrupt generation is enabled.
#1
RSTEN
Receiver Status Enable
16
read-write
value1
Flag PSR[9] is not modified depending on the receiver status.
#0
value2
Flag PSR[9] is set during the complete reception of a frame.
#1
SBIEN
Synchronization Break Interrupt Enable
3
read-write
value1
The interrupt generation is disabled.
#0
value2
The interrupt generation is enabled.
#1
SMD
Sample Mode
0
read-write
value1
Only one sample is taken per bit time. The current input value is sampled.
#0
value2
Three samples are taken per bit time and a majority decision is made.
#1
SP
Sample Point
8
4
read-write
STPB
Stop Bits
1
read-write
value1
The number of stop bits is 1.
#0
value2
The number of stop bits is 2.
#1
TSTEN
Transmitter Status Enable
17
read-write
value1
Flag PSR[9] is not modified depending on the transmitter status.
#0
value2
Flag PSR[9] is set during the complete transmission of a frame.
#1
PCR_IICMode
Protocol Control Register [IIC Mode]
PCR
0x3C
32
read-write
n
0x0
0x0
ACK00
Acknowledge 00H
16
read-write
value1
The slave device is not sensitive to this address.
#0
value2
The slave device is sensitive to this address.
#1
ACKIEN
Acknowledge Interrupt Enable
30
read-write
value1
The acknowledge interrupt is disabled.
#0
value2
The acknowledge interrupt is enabled.
#1
ARLIEN
Arbitration Lost Interrupt Enable
22
read-write
value1
The arbitration lost interrupt is disabled.
#0
value2
The arbitration lost interrupt is enabled.
#1
ERRIEN
Error Interrupt Enable
24
read-write
value1
The error interrupt is disabled.
#0
value2
The error interrupt is enabled.
#1
HDEL
Hardware Delay
26
3
read-write
MCLK
Master Clock Enable
31
read-write
value1
The MCLK generation is disabled and MCLK is 0.
#0
value2
The MCLK generation is enabled.
#1
NACKIEN
Non-Acknowledge Interrupt Enable
21
read-write
value1
The non-acknowledge interrupt is disabled.
#0
value2
The non-acknowledge interrupt is enabled.
#1
PCRIEN
Stop Condition Received Interrupt Enable
20
read-write
value1
The stop condition interrupt is disabled.
#0
value2
The stop condition interrupt is enabled.
#1
RSCRIEN
Repeated Start Condition Received Interrupt Enable
19
read-write
value1
The repeated start condition interrupt is disabled.
#0
value2
The repeated start condition interrupt is enabled.
#1
SACKDIS
Slave Acknowledge Disable
25
read-write
value1
The generation of an active slave acknowledge is enabled (slave acknowledge with 0 level = more bytes can be received).
#0
value2
The generation of an active slave acknowledge is disabled (slave acknowledge with 1 level = reception stopped).
#1
SCRIEN
Start Condition Received Interrupt Enable
18
read-write
value1
The start condition interrupt is disabled.
#0
value2
The start condition interrupt is enabled.
#1
SLAD
Slave Address
0
15
read-write
SRRIEN
Slave Read Request Interrupt Enable
23
read-write
value1
The slave read request interrupt is disabled.
#0
value2
The slave read request interrupt is enabled.
#1
STIM
Symbol Timing
17
read-write
value1
A symbol contains 10 time quanta. The timing is adapted for standard mode (100 kBaud).
#0
value2
A symbol contains 25 time quanta. The timing is adapted for fast mode (400 kBaud).
#1
PCR_IISMode
Protocol Control Register [IIS Mode]
PCR
0x3C
32
read-write
n
0x0
0x0
DTEN
Data Transfers Enable
1
read-write
value1
The changes of the WA input signal are ignored and no transfers take place.
#0
value2
Transfers are enabled.
#1
DX2TIEN
DX2T Interrupt Enable
15
read-write
value1
A protocol interrupt is not generated if DX2T is active.
#0
value2
A protocol interrupt is generated if DX2T is active.
#1
ENDIEN
END Interrupt Enable
6
read-write
value1
A protocol interrupt is not activated.
#0
value2
A protocol interrupt is activated.
#1
MCLK
Master Clock Enable
31
read-write
value1
The MCLK generation is disabled and MCLK is 0.
#0
value2
The MCLK generation is enabled.
#1
SELINV
Select Inversion
2
read-write
value1
The SELOx outputs have the same polarity as the WA signal.
#0
value2
The SELOx outputs have the inverted polarity to the WA signal.
#1
TDEL
Transfer Delay
16
5
read-write
WAFEIEN
WA Falling Edge Interrupt Enable
4
read-write
value1
A protocol interrupt is not activated if a falling edge of WA is generated.
#0
value2
A protocol interrupt is activated if a falling edge of WA is generated.
#1
WAGEN
WA Generation Enable
0
read-write
value1
The IIS can be used as slave. The generation of the word address signal is disabled. The output signal WA is 0. The MCLKO signal generation depends on PCR.MCLK.
#0
value2
The IIS can be used as master. The generation of the word address signal is enabled. The signal starts with a 0 after being enabled. The generation of MCLK is enabled, independent of PCR.MCLK. After clearing WAGEN, the USIC module stops the generation of the WA signal within the next 4 WA periods.
#1
WAREIEN
WA Rising Edge Interrupt Enable
5
read-write
value1
A protocol interrupt is not activated if a rising edge of WA is generated.
#0
value2
A protocol interrupt is activated if a rising edge of WA is generated.
#1
PCR_SSCMode
Protocol Control Register [SSC Mode]
PCR
0x3C
32
read-write
n
0x0
0x0
CTQSEL1
Input Frequency Selection
4
1
read-write
value1
fCTQIN = fPDIV
#00
value2
fCTQIN = fPPP
#01
value3
fCTQIN = fSCLK
#10
value4
fCTQIN = fMCLK
#11
DCTQ1
Divider Factor DCTQ1 for Tiw and Tnf
8
4
read-write
DX2TIEN
DX2T Interrupt Enable
15
read-write
value1
A protocol interrupt is not generated if DX2T is activated.
#0
value2
A protocol interrupt is generated if DX2T is activated.
#1
FEM
Frame End Mode
3
read-write
value1
The current data frame is considered as finished when the last bit of a data word has been sent out and the transmit buffer TBUF does not contain new data (TDV = 0).
#0
value2
The MSLS signal is kept active also while no new data is available and no other end of frame condition is reached. In this case, the software can accept delays in delivering the data without automatic deactivation of MSLS in multi-word data frames.
#1
MCLK
Master Clock Enable
31
read-write
value1
The MCLK generation is disabled and output MCLK = 0.
#0
value2
The MCLK generation is enabled.
#1
MSLSEN
MSLS Enable
0
read-write
value1
The MSLS generation is disabled (MSLS = 0). This is the setting for SSC slave mode.
#0
value2
The MSLS generation is enabled. This is the setting for SSC master mode.
#1
MSLSIEN
MSLS Interrupt Enable
14
read-write
value1
A protocol interrupt is not generated if a change of signal MSLS is detected.
#0
value2
A protocol interrupt is generated if a change of signal MSLS is detected.
#1
PARIEN
Parity Error Interrupt Enable
13
read-write
value1
A protocol interrupt is not generated with the detection of a parity error.
#0
value2
A protocol interrupt is generated with the detection of a parity error.
#1
PCTQ1
Divider Factor PCTQ1 for Tiw and Tnf
6
1
read-write
SELCTR
Select Control
1
read-write
value1
The coded select mode is enabled.
#0
value2
The direct select mode is enabled.
#1
SELINV
Select Inversion
2
read-write
value1
The SELO outputs have the same polarity as the MSLS signal (active high).
#0
value2
The SELO outputs have the inverted polarity to the MSLS signal (active low).
#1
SELO
Select Output
16
7
read-write
value1
The corresponding SELOx line cannot be activated.
#0
value2
The corresponding SELOx line can be activated (according to the mode selected by SELCTR).
#1
SLPHSEL
Slave Mode Clock Phase Select
25
read-write
value1
Data bits are shifted out with the leading edge of the shift clock signal and latched in with the trailing edge.
#0
value2
The first data bit is shifted out when the data shift unit receives a low to high transition from the DX2 stage. Subsequent bits are shifted out with the trailing edge of the shift clock signal. Data bits are always latched in with the leading edge.
#1
TIWEN
Enable Inter-Word Delay Tiw
24
read-write
value1
No delay between data words of the same frame.
#0
value2
The inter-word delay Tiw is enabled and introduced between data words of the same frame.
#1
PSCR
Protocol Status Clear Register
0x4C
32
read-write
n
0x0
0x0
CAIF
Clear Alternative Receive Indication Flag
15
write-only
value1
No action
#0
value2
Flag PSR.AIF is cleared.
#1
CBRGIF
Clear Baud Rate Generator Indication Flag
16
write-only
value1
No action
#0
value2
Flag PSR.BRGIF is cleared.
#1
CDLIF
Clear Data Lost Indication Flag
11
write-only
value1
No action
#0
value2
Flag PSR.DLIF is cleared.
#1
CRIF
Clear Receive Indication Flag
14
write-only
value1
No action
#0
value2
Flag PSR.RIF is cleared.
#1
CRSIF
Clear Receiver Start Indication Flag
10
write-only
value1
No action
#0
value2
Flag PSR.RSIF is cleared.
#1
CST0
Clear Status Flag 0 in PSR
0
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST1
Clear Status Flag 1 in PSR
1
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST2
Clear Status Flag 2 in PSR
2
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST3
Clear Status Flag 3 in PSR
3
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST4
Clear Status Flag 4 in PSR
4
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST5
Clear Status Flag 5 in PSR
5
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST6
Clear Status Flag 6 in PSR
6
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST7
Clear Status Flag 7 in PSR
7
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST8
Clear Status Flag 8 in PSR
8
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CST9
Clear Status Flag 9 in PSR
9
write-only
value1
No action
#0
value2
Flag PSR.STx is cleared.
#1
CTBIF
Clear Transmit Buffer Indication Flag
13
write-only
value1
No action
#0
value2
Flag PSR.TBIF is cleared.
#1
CTSIF
Clear Transmit Shift Indication Flag
12
write-only
value1
No action
#0
value2
Flag PSR.TSIF is cleared.
#1
PSR
Protocol Status Register
0x48
32
read-write
n
0x0
0x0
AIF
Alternative Receive Indication Flag
15
read-write
value1
An alternative receive event has not occurred.
#0
value2
An alternative receive event has occurred.
#1
BRGIF
Baud Rate Generator Indication Flag
16
read-write
value1
A baud rate generator event has not occurred.
#0
value2
A baud rate generator event has occurred.
#1
DLIF
Data Lost Indication Flag
11
read-write
value1
A data lost event has not occurred.
#0
value2
A data lost event has occurred.
#1
RIF
Receive Indication Flag
14
read-write
value1
A receive event has not occurred.
#0
value2
A receive event has occurred.
#1
RSIF
Receiver Start Indication Flag
10
read-write
value1
A receiver start event has not occurred.
#0
value2
A receiver start event has occurred.
#1
ST0
Protocol Status Flag 0
0
read-write
ST1
Protocol Status Flag 1
1
read-write
ST2
Protocol Status Flag 2
2
read-write
ST3
Protocol Status Flag 3
3
read-write
ST4
Protocol Status Flag 4
4
read-write
ST5
Protocol Status Flag 5
5
read-write
ST6
Protocol Status Flag 6
6
read-write
ST7
Protocol Status Flag 7
7
read-write
ST8
Protocol Status Flag 8
8
read-write
ST9
Protocol Status Flag 9
9
read-write
TBIF
Transmit Buffer Indication Flag
13
read-write
value1
A transmit buffer event has not occurred.
#0
value2
A transmit buffer event has occurred.
#1
TSIF
Transmit Shift Indication Flag
12
read-write
value1
A transmit shift event has not occurred.
#0
value2
A transmit shift event has occurred.
#1
PSR_ASCMode
Protocol Status Register [ASC Mode]
PSR
0x48
32
read-write
n
0x0
0x0
AIF
Alternative Receive Indication Flag
15
read-write
value1
An alternative receive event has not occurred.
#0
value2
An alternative receive event has occurred.
#1
BRGIF
Baud Rate Generator Indication Flag
16
read-write
value1
A baud rate generator event has not occurred.
#0
value2
A baud rate generator event has occurred.
#1
BUSY
Transfer Status BUSY
9
read-only
value1
A data transfer does not take place.
#0
value2
A data transfer currently takes place.
#1
COL
Collision Detected
3
read-write
value1
A collision has not yet been detected and frame transmission is possible.
#0
value2
A collision has been detected and frame transmission is not possible.
#1
DLIF
Data Lost Indication Flag
11
read-write
value1
A data lost event has not occurred.
#0
value2
A data lost event has occurred.
#1
FER0
Format Error in Stop Bit 0
5
read-write
value1
A format error 0 has not been detected.
#0
value2
A format error 0 has been detected.
#1
FER1
Format Error in Stop Bit 1
6
read-write
value1
A format error 1 has not been detected.
#0
value2
A format error 1 has been detected.
#1
RFF
Receive Frame Finished
7
read-write
value1
The received frame is not yet finished.
#0
value2
The received frame is finished.
#1
RIF
Receive Indication Flag
14
read-write
value1
A receive event has not occurred.
#0
value2
A receive event has occurred.
#1
RNS
Receiver Noise Detected
4
read-write
value1
Receiver noise has not been detected.
#0
value2
Receiver noise has been detected.
#1
RSIF
Receiver Start Indication Flag
10
read-write
value1
A receiver start event has not occurred.
#0
value2
A receiver start event has occurred.
#1
RXIDLE
Reception Idle
1
read-write
value1
The receiver line has not yet been idle.
#0
value2
The receiver line has been idle and frame reception is possible.
#1
SBD
Synchronization Break Detected
2
read-write
value1
A synchronization break has not yet been detected.
#0
value2
A synchronization break has been detected.
#1
TBIF
Transmit Buffer Indication Flag
13
read-write
value1
A transmit buffer event has not occurred.
#0
value2
A transmit buffer event has occurred.
#1
TFF
Transmitter Frame Finished
8
read-write
value1
The transmitter frame is not yet finished.
#0
value2
The transmitter frame is finished.
#1
TSIF
Transmit Shift Indication Flag
12
read-write
value1
A transmit shift event has not occurred.
#0
value2
A transmit shift event has occurred.
#1
TXIDLE
Transmission Idle
0
read-write
value1
The transmitter line has not yet been idle.
#0
value2
The transmitter line has been idle and frame transmission is possible.
#1
PSR_IICMode
Protocol Status Register [IIC Mode]
PSR
0x48
32
read-write
n
0x0
0x0
ACK
Acknowledge Received
9
read-write
value1
An acknowledge has not been received.
#0
value2
An acknowledge has been received.
#1
AIF
Alternative Receive Indication Flag
15
read-write
value1
An alternative receive event has not occurred.
#0
value2
An alternative receive event has occurred.
#1
ARL
Arbitration Lost
6
read-write
value1
An arbitration has not been lost.
#0
value2
An arbitration has been lost.
#1
BRGIF
Baud Rate Generator Indication Flag
16
read-write
value1
A baud rate generator event has not occurred.
#0
value2
A baud rate generator event has occurred.
#1
DLIF
Data Lost Indication Flag
11
read-write
value1
A data lost event has not occurred.
#0
value2
A data lost event has occurred.
#1
ERR
Error
8
read-write
value1
An IIC error has not been detected.
#0
value2
An IIC error has been detected.
#1
NACK
Non-Acknowledge Received
5
read-write
value1
A non-acknowledge has not been received.
#0
value2
A non-acknowledge has been received.
#1
PCR
Stop Condition Received
4
read-write
value1
A stop condition has not yet been detected.
#0
value2
A stop condition has been detected.
#1
RIF
Receive Indication Flag
14
read-write
value1
A receive event has not occurred.
#0
value2
A receive event has occurred.
#1
RSCR
Repeated Start Condition Received
3
read-write
value1
A repeated start condition has not yet been detected.
#0
value2
A repeated start condition has been detected.
#1
RSIF
Receiver Start Indication Flag
10
read-write
value1
A receiver start event has not occurred.
#0
value2
A receiver start event has occurred.
#1
SCR
Start Condition Received
2
read-write
value1
A start condition has not yet been detected.
#0
value2
A start condition has been detected.
#1
SLSEL
Slave Select
0
read-write
value1
The device is not selected as slave.
#0
value2
The device is selected as slave.
#1
SRR
Slave Read Request
7
read-write
value1
A slave read request has not been detected.
#0
value2
A slave read request has been detected.
#1
TBIF
Transmit Buffer Indication Flag
13
read-write
value1
A transmit buffer event has not occurred.
#0
value2
A transmit buffer event has occurred.
#1
TSIF
Transmit Shift Indication Flag
12
read-write
value1
A transmit shift event has not occurred.
#0
value2
A transmit shift event has occurred.
#1
WTDF
Wrong TDF Code Found
1
read-write
value1
A wrong TDF code has not been found.
#0
value2
A wrong TDF code has been found.
#1
PSR_IISMode
Protocol Status Register [IIS Mode]
PSR
0x48
32
read-write
n
0x0
0x0
AIF
Alternative Receive Indication Flag
15
read-write
value1
An alternative receive event has not occurred.
#0
value2
An alternative receive event has occurred.
#1
BRGIF
Baud Rate Generator Indication Flag
16
read-write
value1
A baud rate generator event has not occurred.
#0
value2
A baud rate generator event has occurred.
#1
DLIF
Data Lost Indication Flag
11
read-write
value1
A data lost event has not occurred.
#0
value2
A data lost event has occurred.
#1
DX2S
DX2S Status
1
read-write
value1
DX2S is 0.
#0
value2
DX2S is 1.
#1
DX2TEV
DX2T Event Detected
3
read-write
value1
The DX2T signal has not been activated.
#0
value2
The DX2T signal has been activated.
#1
END
WA Generation End
6
read-write
value1
The WA generation has not yet ended (if it is running and WAGEN has been cleared).
#0
value2
The WA generation has ended (if it has been running).
#1
RIF
Receive Indication Flag
14
read-write
value1
A receive event has not occurred.
#0
value2
A receive event has occurred.
#1
RSIF
Receiver Start Indication Flag
10
read-write
value1
A receiver start event has not occurred.
#0
value2
A receiver start event has occurred.
#1
TBIF
Transmit Buffer Indication Flag
13
read-write
value1
A transmit buffer event has not occurred.
#0
value2
A transmit buffer event has occurred.
#1
TSIF
Transmit Shift Indication Flag
12
read-write
value1
A transmit shift event has not occurred.
#0
value2
A transmit shift event has occurred.
#1
WA
Word Address
0
read-write
value1
WA has been sampled 0.
#0
value2
WA has been sampled 1.
#1
WAFE
WA Falling Edge Event
4
read-write
value1
A WA falling edge has not been generated.
#0
value2
A WA falling edge has been generated.
#1
WARE
WA Rising Edge Event
5
read-write
value1
A WA rising edge has not been generated.
#0
value2
A WA rising edge has been generated.
#1
PSR_SSCMode
Protocol Status Register [SSC Mode]
PSR
0x48
32
read-write
n
0x0
0x0
AIF
Alternative Receive Indication Flag
15
read-write
value1
An alternative receive event has not occurred.
#0
value2
An alternative receive event has occurred.
#1
BRGIF
Baud Rate Generator Indication Flag
16
read-write
value1
A baud rate generator event has not occurred.
#0
value2
A baud rate generator event has occurred.
#1
DLIF
Data Lost Indication Flag
11
read-write
value1
A data lost event has not occurred.
#0
value2
A data lost event has occurred.
#1
DX2S
DX2S Status
1
read-write
value1
DX2S is 0.
#0
value2
DX2S is 1.
#1
DX2TEV
DX2T Event Detected
3
read-write
value1
The DX2T signal has not been activated.
#0
value2
The DX2T signal has been activated.
#1
MSLS
MSLS Status
0
read-write
value1
The internal signal MSLS is inactive (0).
#0
value2
The internal signal MSLS is active (1).
#1
MSLSEV
MSLS Event Detected
2
read-write
value1
The MSLS signal has not changed its state.
#0
value2
The MSLS signal has changed its state.
#1
PARERR
Parity Error Event Detected
4
read-write
value1
A parity error event has not been activated.
#0
value2
A parity error event has been activated.
#1
RIF
Receive Indication Flag
14
read-write
value1
A receive event has not occurred.
#0
value2
A receive event has occurred.
#1
RSIF
Receiver Start Indication Flag
10
read-write
value1
A receiver start event has not occurred.
#0
value2
A receiver start event has occurred.
#1
TBIF
Transmit Buffer Indication Flag
13
read-write
value1
A transmit buffer event has not occurred.
#0
value2
A transmit buffer event has occurred.
#1
TSIF
Transmit Shift Indication Flag
12
read-write
value1
A transmit shift event has not occurred.
#0
value2
A transmit shift event has occurred.
#1
RBCTR
Receiver Buffer Control Register
0x10C
32
read-write
n
0x0
0x0
ARBIEN
Alternative Receive Buffer Interrupt Enable
29
read-write
value1
The alternative receive buffer interrupt generation is disabled.
#0
value2
The alternative receive buffer interrupt generation is enabled.
#1
ARBINP
Alternative Receive Buffer Interrupt Node Pointer
19
2
read-write
value1
Output SR0 becomes activated.
#000
value2
Output SR1 becomes activated.
#001
value3
Output SR2 becomes activated.
#010
value4
Output SR3 becomes activated.
#011
value5
Output SR4 becomes activated.
#100
value6
Output SR5 becomes activated.
#101
DPTR
Data Pointer
0
5
write-only
LIMIT
Limit For Interrupt Generation
8
5
read-write
LOF
Buffer Event on Limit Overflow
28
read-write
value1
A standard receive buffer event occurs when the filling level equals the limit value and gets lower due to a read access from OUTR.
#0
value2
A standard receive buffer event occurs when the filling level equals the limit value and gets bigger due to the reception of a new data word.
#1
RBERIEN
Receive Buffer Error Interrupt Enable
31
read-write
value1
The receive buffer error interrupt generation is disabled.
#0
value2
The receive buffer error interrupt generation is enabled.
#1
RCIM
Receiver Control Information Mode
22
1
read-write
value1
RCI[4] = PERR, RCI[3:0] = WLEN
#00
value2
RCI[4] = SOF, RCI[3:0] = WLEN
#01
value3
RCI[4] = 0, RCI[3:0] = WLEN
#10
value4
RCI[4] = PERR, RCI[3] = PAR, RCI[2:1] = 00B, RCI[0] = SOF
#11
RNM
Receiver Notification Mode
27
read-write
value1
Filling level mode: A standard receive buffer event occurs when the filling level equals the limit value and changes, either due to a read access from OUTR (LOF = 0) or due to a new received data word (LOF = 1).
#0
value2
RCI mode: A standard receive buffer event occurs when register OUTR is updated with a new value if the corresponding value in OUTR.RCI[4] = 0. If OUTR.RCI[4] = 1, an alternative receive buffer event occurs instead of the standard receive buffer event.
#1
SIZE
Buffer Size
24
2
read-write
value1
The FIFO mechanism is disabled. The buffer does not accept any request for data.
#000
value2
The FIFO buffer contains 2 entries.
#001
value3
The FIFO buffer contains 4 entries.
#010
value4
The FIFO buffer contains 8 entries.
#011
value5
The FIFO buffer contains 16 entries.
#100
value6
The FIFO buffer contains 32 entries.
#101
value7
The FIFO buffer contains 64 entries.
#110
SRBIEN
Standard Receive Buffer Interrupt Enable
30
read-write
value1
The standard receive buffer interrupt generation is disabled.
#0
value2
The standard receive buffer interrupt generation is enabled.
#1
SRBINP
Standard Receive Buffer Interrupt Node Pointer
16
2
read-write
value1
Output SR0 becomes activated.
#000
value2
Output SR1 becomes activated.
#001
value3
Output SR2 becomes activated.
#010
value4
Output SR3 becomes activated.
#011
value5
Output SR4 becomes activated.
#100
value6
Output SR5 becomes activated.
#101
SRBTEN
Standard Receive Buffer Trigger Enable
15
read-write
value1
The standard receive buffer event trigger through bit TRBSR.SRBT is disabled.
#0
value2
The standard receive buffer event trigger through bit TRBSR.SRBT is enabled.
#1
SRBTM
Standard Receive Buffer Trigger Mode
14
read-write
value1
Trigger mode 0: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=RBCTR.LIMIT.
#0
value2
Trigger mode 1: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=0.
#1
RBUF
Receiver Buffer Register
0x54
32
read-write
n
0x0
0x0
modifyExternal
DSR
Received Data
0
15
read-only
RBUF0
Receiver Buffer Register 0
0x5C
32
read-write
n
0x0
0x0
DSR0
Data of Shift Registers 0[3:0]
0
15
read-only
RBUF01SR
Receiver Buffer 01 Status Register
0x64
32
read-write
n
0x0
0x0
DS0
Data Source
15
read-only
value1
The register RBUF contains the data of RBUF0 (same for associated status information).
#0
value2
The register RBUF contains the data of RBUF1 (same for associated status information).
#1
DS1
Data Source
31
read-only
value1
The register RBUF contains the data of RBUF0 (same for associated status information).
#0
value2
The register RBUF contains the data of RBUF1 (same for associated status information).
#1
PAR0
Protocol-Related Argument in RBUF0
8
read-only
PAR1
Protocol-Related Argument in RBUF1
24
read-only
PERR0
Protocol-related Error in RBUF0
9
read-only
value1
The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt.
#0
value2
The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt.
#1
PERR1
Protocol-related Error in RBUF1
25
read-only
value1
The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt.
#0
value2
The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt.
#1
RDV00
Receive Data Valid in RBUF0
13
read-only
value1
Register RBUF0 does not contain data that has not yet been read out.
#0
value2
Register RBUF0 contains data that has not yet been read out.
#1
RDV01
Receive Data Valid in RBUF1
14
read-only
value1
Register RBUF1 does not contain data that has not yet been read out.
#0
value2
Register RBUF1 contains data that has not yet been read out.
#1
RDV10
Receive Data Valid in RBUF0
29
read-only
value1
Register RBUF0 does not contain data that has not yet been read out.
#0
value2
Register RBUF0 contains data that has not yet been read out.
#1
RDV11
Receive Data Valid in RBUF1
30
read-only
value1
Register RBUF1 does not contain data that has not yet been read out.
#0
value2
Register RBUF1 contains data that has not yet been read out.
#1
SOF0
Start of Frame in RBUF0
6
read-only
value1
The data in RBUF0 has not been the first data word of a data frame.
#0
value2
The data in RBUF0 has been the first data word of a data frame.
#1
SOF1
Start of Frame in RBUF1
22
read-only
value1
The data in RBUF1 has not been the first data word of a data frame.
#0
value2
The data in RBUF1 has been the first data word of a data frame.
#1
WLEN0
Received Data Word Length in RBUF0
0
3
read-only
WLEN1
Received Data Word Length in RBUF1
16
3
read-only
RBUF1
Receiver Buffer Register 1
0x60
32
read-write
n
0x0
0x0
DSR1
Data of Shift Registers 1[3:0]
0
15
read-only
RBUFD
Receiver Buffer Register for Debugger
0x58
32
read-write
n
0x0
0x0
DSR
Data from Shift Register
0
15
read-only
RBUFSR
Receiver Buffer Status Register
0x50
32
read-write
n
0x0
0x0
DS
Data Source of RBUF or RBUFD
15
read-only
PAR
Protocol-Related Argument in RBUF or RBUFD
8
read-only
PERR
Protocol-related Error in RBUF or RBUFD
9
read-only
RDV0
Receive Data Valid in RBUF or RBUFD
13
read-only
RDV1
Receive Data Valid in RBUF or RBUFD
14
read-only
SOF
Start of Frame in RBUF or RBUFD
6
read-only
WLEN
Received Data Word Length in RBUF or RBUFD
0
3
read-only
SCTR
Shift Control Register
0x34
32
read-write
n
0x0
0x0
DOCFG
Data Output Configuration
6
1
read-write
value1
DOUTx = shift data value
#00
value2
DOUTx = inverted shift data value
#01
DSM
Data Shift Mode
2
1
read-write
value1
Receive and transmit data is shifted in and out one bit at a time through DX0 and DOUT0.
#00
value3
Receive and transmit data is shifted in and out two bits at a time through two input stages (DX0 and DX3) and DOUT[1:0] respectively.
#10
value4
Receive and transmit data is shifted in and out four bits at a time through four input stages (DX0, DX[5:3]) and DOUT[3:0] respectively.
#11
FLE
Frame Length
16
5
read-write
HPCDIR
Port Control Direction
4
read-write
value1
The pin(s) with hardware pin control enabled are selected to be in input mode.
#0
value2
The pin(s) with hardware pin control enabled are selected to be in output mode.
#1
PDL
Passive Data Level
1
read-write
value1
The passive data level is 0.
#0
value2
The passive data level is 1.
#1
SDIR
Shift Direction
0
read-write
value1
Shift LSB first. The first data bit of a data word is located at bit position 0.
#0
value2
Shift MSB first. The first data bit of a data word is located at the bit position given by bit field SCTR.WLE.
#1
TRM
Transmission Mode
8
1
read-write
value1
The shift control signal is considered as inactive and data frame transfers are not possible.
#00
value2
The shift control signal is considered active if it is at 1-level. This is the setting to be programmed to allow data transfers.
#01
value3
The shift control signal is considered active if it is at 0-level. It is recommended to avoid this setting and to use the inversion in the DX2 stage in case of a low-active signal.
#10
value4
The shift control signal is considered active without referring to the actual signal level. Data frame transfer is possible after each edge of the signal.
#11
WLE
Word Length
24
3
read-write
value1
The data word contains 1 data bit located at bit position 0.
0x0
value2
The data word contains 2 data bits located at bit positions [1:0].
0x1
value3
The data word contains 15 data bits located at bit positions [14:0].
0xE
value4
The data word contains 16 data bits located at bit positions [15:0].
0xF
TBCTR
Transmitter Buffer Control Register
0x108
32
read-write
n
0x0
0x0
ATBINP
Alternative Transmit Buffer Interrupt Node Pointer
19
2
read-write
value1
Output SR0 becomes activated.
#000
value2
Output SR1 becomes activated.
#001
value3
Output SR2 becomes activated.
#010
value4
Output SR3 becomes activated.
#011
value5
Output SR4 becomes activated.
#100
value6
Output SR5 becomes activated.
#101
DPTR
Data Pointer
0
5
write-only
LIMIT
Limit For Interrupt Generation
8
5
read-write
LOF
Buffer Event on Limit Overflow
28
read-write
value1
A standard transmit buffer event occurs when the filling level equals the limit value and gets lower due to transmission of a data word.
#0
value2
A standard transmit buffer interrupt event occurs when the filling level equals the limit value and gets bigger due to a write access to a data input location INx.
#1
SIZE
Buffer Size
24
2
read-write
value1
The FIFO mechanism is disabled. The buffer does not accept any request for data.
#000
value2
The FIFO buffer contains 2 entries.
#001
value3
The FIFO buffer contains 4 entries.
#010
value4
The FIFO buffer contains 8 entries.
#011
value5
The FIFO buffer contains 16 entries.
#100
value6
The FIFO buffer contains 32 entries.
#101
value7
The FIFO buffer contains 64 entries.
#110
STBIEN
Standard Transmit Buffer Interrupt Enable
30
read-write
value1
The standard transmit buffer interrupt generation is disabled.
#0
value2
The standard transmit buffer interrupt generation is enabled.
#1
STBINP
Standard Transmit Buffer Interrupt Node Pointer
16
2
read-write
value1
Output SR0 becomes activated.
#000
value2
Output SR1 becomes activated.
#001
value3
Output SR2 becomes activated.
#010
value4
Output SR3 becomes activated.
#011
value5
Output SR4 becomes activated.
#100
value6
Output SR5 becomes activated.
#101
STBTEN
Standard Transmit Buffer Trigger Enable
15
read-write
value1
The standard transmit buffer event trigger through bit TRBSR.STBT is disabled.
#0
value2
The standard transmit buffer event trigger through bit TRBSR.STBT is enabled.
#1
STBTM
Standard Transmit Buffer Trigger Mode
14
read-write
value1
Trigger mode 0: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.LIMIT.
#0
value2
Trigger mode 1: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.SIZE.
#1
TBERIEN
Transmit Buffer Error Interrupt Enable
31
read-write
value1
The transmit buffer error interrupt generation is disabled.
#0
value2
The transmit buffer error interrupt generation is enabled.
#1
TBUF[0]
Transmit Buffer
0x100
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[10]
Transmit Buffer
0x6DC
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[11]
Transmit Buffer
0x788
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[12]
Transmit Buffer
0x838
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[13]
Transmit Buffer
0x8EC
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[14]
Transmit Buffer
0x9A4
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[15]
Transmit Buffer
0xA60
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[16]
Transmit Buffer
0xB20
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[17]
Transmit Buffer
0xBE4
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[18]
Transmit Buffer
0xCAC
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[19]
Transmit Buffer
0xD78
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[1]
Transmit Buffer
0x184
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[20]
Transmit Buffer
0xE48
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[21]
Transmit Buffer
0xF1C
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[22]
Transmit Buffer
0xFF4
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[23]
Transmit Buffer
0x10D0
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[24]
Transmit Buffer
0x11B0
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[25]
Transmit Buffer
0x1294
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[26]
Transmit Buffer
0x137C
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[27]
Transmit Buffer
0x1468
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[28]
Transmit Buffer
0x1558
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[29]
Transmit Buffer
0x164C
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[2]
Transmit Buffer
0x20C
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[30]
Transmit Buffer
0x1744
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[31]
Transmit Buffer
0x1840
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[3]
Transmit Buffer
0x298
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[4]
Transmit Buffer
0x328
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[5]
Transmit Buffer
0x3BC
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[6]
Transmit Buffer
0x454
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[7]
Transmit Buffer
0x4F0
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[8]
Transmit Buffer
0x590
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TBUF[9]
Transmit Buffer
0x634
32
read-write
n
0x0
0x0
TDATA
Transmit Data
0
15
read-write
TCSR
Transmit Control/Status Register
0x38
32
read-write
n
0x0
0x0
EOF
End Of Frame
6
read-write
value1
The data word in TBUF is not considered as last word of an SSC frame.
#0
value2
The data word in TBUF is considered as last word of an SSC frame.
#1
FLEMD
FLE Mode
2
read-write
value1
The automatic update of FLE is disabled.
#0
value2
The automatic update of FLE is enabled.
#1
HPCMD
Hardware Port Control Mode
4
read-write
value1
The automatic update of bits SCTR.DSM and SCTR.HPCDIR is disabled.
#0
value2
The automatic update of bits SCTR.DSM and SCTR.HPCDIR is enabled.
#1
SELMD
Select Mode
1
read-write
value1
The automatic update of PCR.CTR[23:16] is disabled.
#0
value2
The automatic update of PCR.CTR[23:16] is disabled.
#1
SOF
Start Of Frame
5
read-write
value1
The data word in TBUF is not considered as first word of a frame.
#0
value2
The data word in TBUF is considered as first word of a frame. A currently running frame is finished and MSLS becomes deactivated (respecting the programmed delays).
#1
TDEN
TBUF Data Enable
10
1
read-write
value1
A transmission start of the data word in TBUF is disabled. If a transmission is started, the passive data level is sent out.
#00
value2
A transmission of the data word in TBUF can be started if TDV = 1.
#01
value3
A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 0.
#10
value4
A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 1.
#11
TDSSM
TBUF Data Single Shot Mode
8
read-write
value1
The data word in TBUF is not considered as invalid after it has been loaded into the transmit shift register. The loading of the TBUF data into the shift register does not clear TDV.
#0
value2
The data word in TBUF is considered as invalid after it has been loaded into the shift register. In ASC and IIC mode, TDV is cleared with the TBI event, whereas in SSC and IIS mode, it is cleared with the RSI event. TDSSM = 1 has to be programmed if an optional data buffer is used.
#1
TDV
Transmit Data Valid
7
read-only
value1
The data word in TBUF is not valid for transmission.
#0
value2
The data word in TBUF is valid for transmission and a transmission start is possible. New data should not be written to a TBUFx input location while TDV = 1.
#1
TDVTR
TBUF Data Valid Trigger
12
read-write
value1
Bit TCSR.TE is permanently set.
#0
value2
Bit TCSR.TE is set if DX2T becomes active while TDV = 1.
#1
TE
Trigger Event
28
read-only
value1
The trigger event has not yet been detected. A transmission of the data word in TBUF can not be started.
#0
value2
The trigger event has been detected (or the trigger mechanism is switched off) and a transmission of the data word in TBUF can be started.
#1
TSOF
Transmitted Start Of Frame
24
read-only
value1
The latest data word transmission has not been started for the first word of a data frame.
#0
value2
The latest data word transmission has been started for the first word of a data frame.
#1
TV
Transmission Valid
26
read-only
value1
The latest start of a data word transmission has taken place while no valid data was available. As a result, the transmission of a data words with passive level (SCTR.PDL) has been started.
#0
value2
The latest start of a data word transmission has taken place with valid data from TBUF.
#1
TVC
Transmission Valid Cumulated
27
read-only
value1
Since TVC has been set, at least one data buffer underflow condition has occurred.
#0
value2
Since TVC has been set, no data buffer underflow condition has occurred.
#1
WA
Word Address
13
read-write
value1
The data word in TBUF will be transmitted after a falling edge of WA has been detected (referring to PSR.WA).
#0
value2
The data word in TBUF will be transmitted after a rising edge of WA has been detected (referring to PSR.WA).
#1
WAMD
WA Mode
3
read-write
value1
The automatic update of bit WA is disabled.
#0
value2
The automatic update of bit WA is enabled.
#1
WLEMD
WLE Mode
0
read-write
value1
The automatic update of SCTR.WLE and TCSR.EOF is disabled.
#0
value2
The automatic update of SCTR.WLE and TCSR.EOF is enabled.
#1
TRBPTR
Transmit/Receive Buffer Pointer Register
0x110
32
read-write
n
0x0
0x0
RDIPTR
Receiver Data Input Pointer
16
5
read-only
RDOPTR
Receiver Data Output Pointer
24
5
read-only
TDIPTR
Transmitter Data Input Pointer
0
5
read-only
TDOPTR
Transmitter Data Output Pointer
8
5
read-only
TRBSCR
Transmit/Receive Buffer Status Clear Register
0x118
32
read-write
n
0x0
0x0
CARBI
Clear Alternative Receive Buffer Event
2
write-only
value1
No effect.
#0
value2
Clear TRBSR.ARBI.
#1
CBDV
Clear Bypass Data Valid
10
write-only
value1
No effect.
#0
value2
Clear BYPCR.BDV.
#1
CRBERI
Clear Receive Buffer Error Event
1
write-only
value1
No effect.
#0
value2
Clear TRBSR.RBERI.
#1
CSRBI
Clear Standard Receive Buffer Event
0
write-only
value1
No effect.
#0
value2
Clear TRBSR.SRBI.
#1
CSTBI
Clear Standard Transmit Buffer Event
8
write-only
value1
No effect.
#0
value2
Clear TRBSR.STBI.
#1
CTBERI
Clear Transmit Buffer Error Event
9
write-only
value1
No effect.
#0
value2
Clear TRBSR.TBERI.
#1
FLUSHRB
Flush Receive Buffer
14
write-only
value1
No effect.
#0
value2
The receive FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic.
#1
FLUSHTB
Flush Transmit Buffer
15
write-only
value1
No effect.
#0
value2
The transmit FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic.
#1
TRBSR
Transmit/Receive Buffer Status Register
0x114
32
read-write
n
0x0
0x0
ARBI
Alternative Receive Buffer Event
2
read-write
value1
An alternative receive buffer event has not been detected.
#0
value2
An alternative receive buffer event has been detected.
#1
RBERI
Receive Buffer Error Event
1
read-write
value1
A receive buffer error event has not been detected.
#0
value2
A receive buffer error event has been detected.
#1
RBFLVL
Receive Buffer Filling Level
16
6
read-only
RBUS
Receive Buffer Busy
5
read-only
value1
The receive buffer information has been completely updated.
#0
value2
The OUTR update from the FIFO memory is ongoing. A read from OUTR will be delayed. FIFO pointers from the previous read are not yet updated.
#1
REMPTY
Receive Buffer Empty
3
read-only
value1
The receive buffer is not empty.
#0
value2
The receive buffer is empty.
#1
RFULL
Receive Buffer Full
4
read-only
value1
The receive buffer is not full.
#0
value2
The receive buffer is full.
#1
SRBI
Standard Receive Buffer Event
0
read-write
value1
A standard receive buffer event has not been detected.
#0
value2
A standard receive buffer event has been detected.
#1
SRBT
Standard Receive Buffer Event Trigger
6
read-only
value1
A standard receive buffer event is not triggered using this bit.
#0
value2
A standard receive buffer event is triggered using this bit.
#1
STBI
Standard Transmit Buffer Event
8
read-write
value1
A standard transmit buffer event has not been detected.
#0
value2
A standard transmit buffer event has been detected.
#1
STBT
Standard Transmit Buffer Event Trigger
14
read-only
value1
A standard transmit buffer event is not triggered using this bit.
#0
value2
A standard transmit buffer event is triggered using this bit.
#1
TBERI
Transmit Buffer Error Event
9
read-write
value1
A transmit buffer error event has not been detected.
#0
value2
A transmit buffer error event has been detected.
#1
TBFLVL
Transmit Buffer Filling Level
24
6
read-only
TBUS
Transmit Buffer Busy
13
read-only
value1
The transmit buffer information has been completely updated.
#0
value2
The FIFO memory update after write to INx is ongoing. A write to INx will be delayed. FIFO pointers from the previous INx write are not yet updated.
#1
TEMPTY
Transmit Buffer Empty
11
read-only
value1
The transmit buffer is not empty.
#0
value2
The transmit buffer is empty.
#1
TFULL
Transmit Buffer Full
12
read-only
value1
The transmit buffer is not full.
#0
value2
The transmit buffer is full.
#1
VADC
Analog to Digital Converter
VADC
0x0
0x0
0x400
registers
n
VADC0_C0_0
Analog to Digital Converter Common Block 0
15
VADC0_C0_1
Analog to Digital Converter Common Block 0
16
BRSCTRL
Background Request Source Control Register
0x200
32
read-write
n
0x0
0x0
GTLVL
Gate Input Level
20
read-only
GTSEL
Gate Input Selection
16
3
read-write
GTWC
Write Control for Gate Configuration
23
write-only
value1
No write access to gate configuration
#0
value2
Bitfield GTSEL can be written
#1
SRCRESREG
Source-specific Result Register
0
3
read-write
value1
Use GxCHCTRy.RESREG to select a group result register
#0000
value2
Store result in group result register GxRES1
#0001
value3
Store result in group result register GxRES15
#1111
XTLVL
External Trigger Level
12
read-only
XTMODE
Trigger Operating Mode
13
1
read-write
value1
No external trigger
#00
value2
Trigger event upon a falling edge
#01
value3
Trigger event upon a rising edge
#10
value4
Trigger event upon any edge
#11
XTSEL
External Trigger Input Selection
8
3
read-write
XTWC
Write Control for Trigger Configuration
15
write-only
value1
No write access to trigger configuration
#0
value2
Bitfields XTMODE and XTSEL can be written
#1
BRSMR
Background Request Source Mode Register
0x204
32
read-write
n
0x0
0x0
CLRPND
Clear Pending Bits
8
write-only
value1
No action
#0
value2
The bits in registers BRSPNDx are cleared
#1
ENGT
Enable Gate
0
1
read-write
value1
No conversion requests are issued
#00
value2
Conversion requests are issued if at least one pending bit is set
#01
value3
Conversion requests are issued if at least one pending bit is set and REQGTx = 1.
#10
value4
Conversion requests are issued if at least one pending bit is set and REQGTx = 0.
#11
ENSI
Enable Source Interrupt
3
read-write
value1
No request source interrupt
#0
value2
A request source interrupt is generated upon a request source event (last pending conversion is finished)
#1
ENTR
Enable External Trigger
2
read-write
value1
External trigger disabled
#0
value2
The selected edge at the selected trigger input signal REQTR generates the load event
#1
LDEV
Generate Load Event
9
write-only
value1
No action
#0
value2
A load event is generated
#1
LDM
Autoscan Source Load Event Mode
5
read-write
value1
Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event
#0
value2
Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR)
#1
REQGT
Request Gate Level
7
read-only
value1
The gate input is low
#0
value2
The gate input is high
#1
RPTDIS
Repeat Disable
16
read-write
value1
A cancelled conversion is repeated
#0
value2
A cancelled conversion is discarded
#1
SCAN
Autoscan Enable
4
read-write
value1
No autoscan
#0
value2
Autoscan functionality enabled: a request source event automatically generates a load event
#1
BRSPND[0]
Background Request Source Pending Register
0x380
32
read-write
n
0x0
0x0
CHPNDG0
Channels Pending Group x
0
read-write
value1
Ignore this channel
#0
value2
Request conversion of this channel
#1
CHPNDG1
Channels Pending Group x
1
read-write
value1
Ignore this channel
#0
value2
Request conversion of this channel
#1
CHPNDG2
Channels Pending Group x
2
read-write
value1
Ignore this channel
#0
value2
Request conversion of this channel
#1
CHPNDG3
Channels Pending Group x
3
read-write
value1
Ignore this channel
#0
value2
Request conversion of this channel
#1
CHPNDG4
Channels Pending Group x
4
read-write
value1
Ignore this channel
#0
value2
Request conversion of this channel
#1
CHPNDG5
Channels Pending Group x
5
read-write
value1
Ignore this channel
#0
value2
Request conversion of this channel
#1
CHPNDG6
Channels Pending Group x
6
read-write
value1
Ignore this channel
#0
value2
Request conversion of this channel
#1
CHPNDG7
Channels Pending Group x
7
read-write
value1
Ignore this channel
#0
value2
Request conversion of this channel
#1
BRSPND[1]
Background Request Source Pending Register
0x544
32
read-write
n
0x0
0x0
CHPNDG0
Channels Pending Group x
0
read-write
value1
Ignore this channel
#0
value2
Request conversion of this channel
#1
CHPNDG1
Channels Pending Group x
1
read-write
value1
Ignore this channel
#0
value2
Request conversion of this channel
#1
CHPNDG2
Channels Pending Group x
2
read-write
value1
Ignore this channel
#0
value2
Request conversion of this channel
#1
CHPNDG3
Channels Pending Group x
3
read-write
value1
Ignore this channel
#0
value2
Request conversion of this channel
#1
CHPNDG4
Channels Pending Group x
4
read-write
value1
Ignore this channel
#0
value2
Request conversion of this channel
#1
CHPNDG5
Channels Pending Group x
5
read-write
value1
Ignore this channel
#0
value2
Request conversion of this channel
#1
CHPNDG6
Channels Pending Group x
6
read-write
value1
Ignore this channel
#0
value2
Request conversion of this channel
#1
CHPNDG7
Channels Pending Group x
7
read-write
value1
Ignore this channel
#0
value2
Request conversion of this channel
#1
BRSSEL[0]
Background Request Source Channel Select Register
0x300
32
read-write
n
0x0
0x0
CHSELG0
Channel Selection Group x
0
read-write
value1
Ignore this channel
#0
value2
This channel is part of the scan sequence
#1
CHSELG1
Channel Selection Group x
1
read-write
value1
Ignore this channel
#0
value2
This channel is part of the scan sequence
#1
CHSELG2
Channel Selection Group x
2
read-write
value1
Ignore this channel
#0
value2
This channel is part of the scan sequence
#1
CHSELG3
Channel Selection Group x
3
read-write
value1
Ignore this channel
#0
value2
This channel is part of the scan sequence
#1
CHSELG4
Channel Selection Group x
4
read-write
value1
Ignore this channel
#0
value2
This channel is part of the scan sequence
#1
CHSELG5
Channel Selection Group x
5
read-write
value1
Ignore this channel
#0
value2
This channel is part of the scan sequence
#1
CHSELG6
Channel Selection Group x
6
read-write
value1
Ignore this channel
#0
value2
This channel is part of the scan sequence
#1
CHSELG7
Channel Selection Group x
7
read-write
value1
Ignore this channel
#0
value2
This channel is part of the scan sequence
#1
BRSSEL[1]
Background Request Source Channel Select Register
0x484
32
read-write
n
0x0
0x0
CHSELG0
Channel Selection Group x
0
read-write
value1
Ignore this channel
#0
value2
This channel is part of the scan sequence
#1
CHSELG1
Channel Selection Group x
1
read-write
value1
Ignore this channel
#0
value2
This channel is part of the scan sequence
#1
CHSELG2
Channel Selection Group x
2
read-write
value1
Ignore this channel
#0
value2
This channel is part of the scan sequence
#1
CHSELG3
Channel Selection Group x
3
read-write
value1
Ignore this channel
#0
value2
This channel is part of the scan sequence
#1
CHSELG4
Channel Selection Group x
4
read-write
value1
Ignore this channel
#0
value2
This channel is part of the scan sequence
#1
CHSELG5
Channel Selection Group x
5
read-write
value1
Ignore this channel
#0
value2
This channel is part of the scan sequence
#1
CHSELG6
Channel Selection Group x
6
read-write
value1
Ignore this channel
#0
value2
This channel is part of the scan sequence
#1
CHSELG7
Channel Selection Group x
7
read-write
value1
Ignore this channel
#0
value2
This channel is part of the scan sequence
#1
CLC
Clock Control Register
0x0
32
read-write
n
0x0
0x0
DISR
Module Disable Request Bit
0
read-write
value1
On request: enable the module clock
#0
value2
Off request: stop the module clock
#1
DISS
Module Disable Status Bit
1
read-only
value1
Module clock is enabled
#0
value2
Off: module is not clocked
#1
EDIS
Sleep Mode Enable Control
3
read-write
value1
Sleep mode request is enabled and functional
#0
value2
Module disregards the sleep mode control signal
#1
GLOBCFG
Global Configuration Register
0x80
32
read-write
n
0x0
0x0
DCMSB
Double Clock for the MSB Conversion
7
read-write
value1
1 clock cycles for the MSB (standard)
#0
value2
2 clock cycles for the MSB (fADCI > 20 MHz)
#1
DIVA
Divider Factor for the Analog Internal Clock
0
4
read-write
value1
fADCI = fADC
0x00
value2
fADCI = fADC / 2
0x01
value3
fADCI = fADC / 3
0x02
value4
fADCI = fADC / 32
0x1F
DIVD
Divider Factor for the Arbiter Clock
8
1
read-write
value1
fADCD = fADC
#00
value2
fADCD = fADC / 2
#01
value3
fADCD = fADC / 3
#10
value4
fADCD = fADC / 4
#11
DIVWC
Write Control for Divider Parameters
15
write-only
value1
No write access to divider parameters
#0
value2
Bitfields DIVA, DCMSB, DIVD can be written
#1
DPCAL0
Disable Post-Calibration
16
read-write
value1
Automatic post-calibration after each conversion of group x
#0
value2
No post-calibration
#1
DPCAL1
Disable Post-Calibration
17
read-write
value1
Automatic post-calibration after each conversion of group x
#0
value2
No post-calibration
#1
SUCAL
Start-Up Calibration
31
write-only
value1
No action
#0
value2
Initiate the start-up calibration phase (indication in bit GxARBCFG.CAL)
#1
GLOBEFLAG
Global Event Flag Register
0xE0
32
read-write
n
0x0
0x0
REVGLB
Global Result Event
8
read-write
value1
No result event
#0
value2
New result was stored in register GLOBRES
#1
REVGLBCLR
Clear Global Result Event
24
write-only
value1
No action
#0
value2
Clear the result event flag REVGLB
#1
SEVGLB
Source Event (Background)
0
read-write
value1
No source event
#0
value2
A source event has occurred
#1
SEVGLBCLR
Clear Source Event (Background)
16
write-only
value1
No action
#0
value2
Clear the source event flag SEVGLB
#1
GLOBEVNP
Global Event Node Pointer Register
0x140
32
read-write
n
0x0
0x0
REV0NP
Service Request Node Pointer Global Result
16
3
read-write
value1
Select shared service request line 0 of common service request group 0
#0000
value2
Select shared service request line 3 of common service request group 0
#0011
value3
Select shared service request line 0 of common service request group 1
#0100
value4
Select shared service request line 3 of common service request group 1
#0111
SEV0NP
Service Request Node Pointer Backgr. Source
0
3
read-write
value1
Select shared service request line 0 of common service request group 0
#0000
value2
Select shared service request line 3 of common service request group 0
#0011
GLOBICLASS[0]
Input Class Register, Global
0x140
32
read-write
n
0x0
0x0
CMS
Conversion Mode for Standard Conversions
8
2
read-write
value1
12-bit conversion
#000
value2
10-bit conversion
#001
value3
8-bit conversion
#010
value6
10-bit fast compare mode
#101
STCS
Sample Time Control for Standard Conversions
0
4
read-write
GLOBICLASS[1]
Input Class Register, Global
0x1E4
32
read-write
n
0x0
0x0
CMS
Conversion Mode for Standard Conversions
8
2
read-write
value1
12-bit conversion
#000
value2
10-bit conversion
#001
value3
8-bit conversion
#010
value6
10-bit fast compare mode
#101
STCS
Sample Time Control for Standard Conversions
0
4
read-write
GLOBRCR
Global Result Control Register
0x280
32
read-write
n
0x0
0x0
DRCTR
Data Reduction Control
16
3
read-write
value1
Data reduction disabled
#0000
value2
Accumulate 2 result values
#0001
value3
Accumulate 3 result values
#0010
value4
Accumulate 4 result values
#0011
SRGEN
Service Request Generation Enable
31
read-write
value1
No service request
#0
value2
Service request after a result event
#1
WFR
Wait-for-Read Mode Enable
24
read-write
value1
Overwrite mode
#0
value2
Wait-for-read mode enabled for this register
#1
GLOBRES
Global Result Register
0x300
32
read-write
n
0x0
0x0
modifyExternal
CHNR
Channel Number
20
4
read-only
CRS
Converted Request Source
28
1
read-only
EMUX
External Multiplexer Setting
25
2
read-only
FCR
Fast Compare Result
30
read-only
value1
Signal level was below compare value
#0
value2
Signal level was above compare value
#1
GNR
Group Number
16
3
read-only
RESULT
Result of most recent conversion
0
15
read-write
VF
Valid Flag
31
read-write
value1
Read access: No new valid data available Write access: No effect
#0
value2
Read access: Bitfield RESULT contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and the data reduction counter (overrides a hardware set action)
#1
GLOBRESD
Global Result Register, Debug
0x380
32
read-write
n
0x0
0x0
CHNR
Channel Number
20
4
read-only
CRS
Converted Request Source
28
1
read-only
EMUX
External Multiplexer Setting
25
2
read-only
FCR
Fast Compare Result
30
read-only
value1
Signal level was below compare value
#0
value2
Signal level was above compare value
#1
GNR
Group Number
16
3
read-only
RESULT
Result of most recent conversion
0
15
read-write
VF
Valid Flag
31
read-write
value1
Read access: No new valid data available Write access: No effect
#0
value2
Read access: Bitfield RESULT contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and the data reduction counter (overrides a hardware set action)
#1
ID
Module Identification Register
0x8
32
read-write
n
0x0
0x0
MOD_NUMBER
Module Number
16
15
read-only
MOD_REV
Module Revision
0
7
read-only
MOD_TYPE
Module Type
8
7
read-only
OCS
OCDS Control and Status Register
0x28
32
read-write
n
0x0
0x0
SUS
OCDS Suspend Control
24
3
read-write
value1
Will not suspend
#0000
value2
Hard suspend: Clock is switched off immediately.
#0001
value3
Soft suspend mode 0: Stop conversions after the currently running one is completed and its result has been stored. No change for the arbiter.
#0010
value4
Soft suspend mode 1: Stop conversions after the currently running one is completed and its result has been stored. Stop arbiter after the current arbitration round.
#0011
SUSSTA
Suspend State
29
read-only
value1
Module is not (yet) suspended
#0
value2
Module is suspended
#1
SUS_P
SUS Write Protection
28
write-only
TGB
OTGB0/1 Bus Select
2
read-write
value1
Trigger Set is output on OTGB0
#0
value2
Trigger Set is output on OTGB1
#1
TGS
Trigger Set for OTGB0/1
0
1
read-write
value1
No Trigger Set output
#00
value2
Trigger Set 1: TS16_SSIG, input sample signals
#01
TG_P
TGS, TGB Write Protection
3
write-only
WDT
Watch Dog Timer
WDT
0x0
0x0
0x10000
registers
n
CTR
WDT Control Register
0x4
32
read-write
n
0x0
0x0
DSP
Debug Suspend
4
read-write
ENB
Enable
0
read-write
PRE
Pre-warning
1
read-write
SPW
Service Indication Pulse Width
8
7
read-write
ID
WDT Module ID Register
0x0
32
read-write
n
0x0
0x0
MOD_NUMBER
Module Number Value
16
15
read-only
MOD_REV
Module Revision Number
0
7
read-only
MOD_TYPE
Module Type
8
7
read-only
SRV
WDT Service Register
0x8
32
read-write
n
0x0
0x0
SRV
Service
0
31
write-only
TIM
WDT Timer Register
0xC
32
read-write
n
0x0
0x0
TIM
Timer Value
0
31
read-only
WDTCLR
WDT Clear Register
0x1C
32
read-write
n
0x0
0x0
ALMC
Pre-warning Alarm
0
write-only
WDTSTS
WDT Status Register
0x18
32
read-write
n
0x0
0x0
ALMS
Pre-warning Alarm
0
read-only
WLB
WDT Window Lower Bound Register
0x10
32
read-write
n
0x0
0x0
WLB
Window Lower Bound
0
31
read-write
WUB
WDT Window Upper Bound Register
0x14
32
read-write
n
0x0
0x0
WUB
Window Upper Bound
0
31
read-write