Infineon psoc4100smax 2024.04.27 PSoC4100Smax CM0PLUS r0p1 little 2 false 8 32 CPUSS CPU Subsystem CPUSS 0x0 0x0 0x1000 registers n ioss_interrupts_gpio_0 GPIO P0 0 ioss_interrupts_gpio_1 GPIO P1 1 ioss_interrupts_gpio_2 GPIO P2 2 ioss_interrupts_gpio_3 GPIO P3 3 ioss_interrupt_gpio GPIO All Ports 4 lpcomp_interrupt LPCOMP trigger interrupt 5 srss_interrupt_wdt WDT 6 scb_0_interrupt SCB #0 7 scb_1_interrupt SCB #1 8 scb_2_interrupt SCB #2 9 scb_3_interrupt SCB #3 10 scb_4_interrupt SCB #4 11 pass_interrupt_ctbs CTBm Interrupt (all CTBms) 12 wco_interrupt WCO WDT Interrupt 13 cpuss_interrupt_dma DMA Interrupt 14 cpuss_interrupt_spcif SPCIF interrupt 15 msc_0_interrupt CSD #0 (Primarily Capsense) 16 tcpwm_interrupts_0 TCPWM #0, Counter #0 17 tcpwm_interrupts_1 TCPWM #0, Counter #1 18 tcpwm_interrupts_2 TCPWM #0, Counter #2 19 tcpwm_interrupts_3 TCPWM #0, Counter #3 20 tcpwm_interrupts_4 TCPWM #0, Counter #4 21 tcpwm_interrupts_5 TCPWM #0, Counter #5 22 tcpwm_interrupts_6 TCPWM #0, Counter #6 23 tcpwm_interrupts_7 TCPWM #0, Counter #7 24 pass_interrupt_sar SAR 25 canfd_interrupts0_0 CAN Interrupt 26 canfd_interrupts1_0 CAN Interrupt 27 crypto_interrupt Crypto Interrupt 28 msc_1_interrupt CSD #0 (Primarily Capsense) 29 exco_interrupt EXCO 30 audioss_interrupt_i2s I2S Interrupt 31 CONFIG Configuration register 0x0 32 read-write n 0x0 0x0 VECT_IN_RAM 0': Vector Table is located at 0x0000:0000 in flash '1': Vector Table is located at 0x2000:0000 in SRAM Note that vectors for RESET and FAULT are always fetched from ROM. Value in flash/RAM is ignored for these vectors. 0 1 read-write DMAC_CTL DMA controller register 0x3C 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write FLASH_CTL FLASH control register 0x30 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write FLASH_INVALIDATE 1': Invalidates the content of the flash controller's buffers. 8 9 read-write FLASH_WS Amount of ROM wait states: '0': 0 wait states (fast flash: [0, 24] MHz system frequency, slow flash: [0, 16] MHz system frequency) '1': 1 wait state (fast flash: [24, 48] MHz system frequency, slow flash: [16, 32] MHz system frequency) '2': 2 wait states (slow flash: [32, 48] MHz system frequency) '3': 3 wait states (can be used to give more time for flash access if 2 wait states are not sufficient) 0 2 read-write PREF_EN Prefetch enable: '0': disabled. This is a desirable seeting when FLASH_WS is '0' or when predictable execution behavior is required. '1': enabled. 4 5 read-write INT_MODE DSI interrupt pulse mode register 0x24 32 read-write n 0x0 0x0 DSI_INT_PULSE Specifies DSI interrupt format: '0': level sensitive i.e. no pulse generator. '1': pulse generator on rising edge. 0 32 read-write INT_SEL Interrupt multiplexer select register 0x20 32 read-write n 0x0 0x0 DSI Specifies interrupt source: '0': Fixed Function. '1': DSI. When changing the source of a specific interrupt, it is advised to temporarily disable the interrupt using the CM0 NVIC's CLRENA and SETENA interrupt enable clear and set registers to prevent a spurious interrupt activation. In addition, the CM0 NVIC's CLRPEND interrupt pending clear register should be used clear a pending interrupt before re-enabling the interrupt. 0 32 read-write MTB_CTL MTB control register 0xB0 32 read-write n 0x0 0x0 CPU_HALT_TSTOP_EN 1': Enable CPU Halt to stop MTB trace. ('HALTED' output of CM0+ can stop the trace when high/'1') '0': 'HALTED' output of CM0+ can not strop trace. 0 1 read-write NMI_MODE DSI NMI pulse mode register 0x28 32 read-write n 0x0 0x0 DSI_NMI_PULSE Specifies DSI NMI format: '0': level sensitive i.e. no pulse generator. '1': pulse generator on rising edge. 0 1 read-write PRIV_FLASH Flash privilege register 0x18 32 read-write n 0x0 0x0 FLASH_PROT_LIMIT Indicates the limit where the privileged area of flash starts in increments of 256 Bytes. '0': Entire flash is Privileged. '1': First 256 Bytes are User accessable. Any number larger than the size of the flash indicates that the entire flash is user mode accessible. Note that SuperVisory rows are always User accessable. If FLASH_PROT_LIMIT defines a non-empty privileged area, the boot ROM will assume that a system call table exists at the beginning of the Flash privileged area and use it for all SystemCalls made using SYSREQ. 0 12 read-write PRIV_RAM RAM privilege register 0x14 32 read-write n 0x0 0x0 RAM_PROT_LIMIT Indicates the limit where the privileged area of SRAM starts in increments of 256 Bytes. '0': Entire SRAM is Privileged. '1': First 256 Bytes are User accessable. Any number larger than the size of the SRAM indicates that the entire SRAM is user mode accessible. 0 9 read-write PRIV_RAM1 RAM 1 privilege register 0xA0 32 read-write n 0x0 0x0 RAM_PROT_LIMIT See description of PRIV_RAM.RAM_PROT_LIMIT. Note that the reset value is 0x1ff, indicating that the complete RAM 1 memory capacity is User accessable. 0 9 read-write PRIV_ROM ROM privilege register 0x10 32 read-write n 0x0 0x0 BROM_PROT_LIMIT Indicates the limit where the privileged area of the Boot ROM partition starts in increments of 256 Bytes. '0': Entire Boot ROM is Privileged. '1': First 256 Bytes are User accessable. ... BROM_PROT_LIMIT >= 'Boot ROM partition capacity': Entire Boot ROM partition is user mode accessible. 0 8 read-write SROM_PROT_LIMIT Indicates the limit where the privileged area of System ROM partition starts in increments of 256 Bytes. The limit is wrt. the start of the ROM memory (start of the Boot ROM partition). SROM_PROT_LIMIT * 256 Byte <= 'Boot ROM partition capacity': Entire System ROM is Privileged. SROM_PROT_LIMIT * 256 Byte > 'Boot ROM partition capacity': First SROM_PROT_LIMIT * 256 - 'Boot ROM partition capacity' Bytes are User accessable. ... SROM_PROT_LIMIT >= 'ROM capacity': Entire System ROM is user mode accessible. 16 26 read-write PROTECTION Protection control register 0xC 32 read-write n 0x0 0x0 FLASH_LOCK Setting this bit will force SPCIF.ADDRESS.AXA to be ignored, which prevents SM Flash from being erased or overwritten. It is used to indicate the DEAD protection mode. Writes to this field are ignored when PROTECTION_LOCK is '1' 30 31 read-write PROTECTION_LOCK Setting this field will block (ignore) any further writes to the PROTECTION_MODE field in this register. Once '1', this field cannot be cleared. 31 32 read-write PROTECTION_MODE Current protection mode this field is available as a global signal everywhere in the system. Writes to this field are ignored when PROTECTION_LOCK is '1': 0b1xxx: BOOT 0b01xx: KILL 0b001x: PROTECTED 0b0001: OPEN 0b0000: VIRGIN (also used for DEAD mode, but then FLASH_LOCK is also set) 0 4 read-write RAM1_CTL RAM 1 control register 0xA4 32 read-write n 0x0 0x0 ARB Arbitration policy (for RAM controller 1): '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write RAM_CTL RAM control register 0x38 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write ROM_CTL ROM control register 0x34 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write ROM_WS Amount of ROM wait states: '0': 0 wait states. Use this setting for newer, faster ROM design. Use this setting for older, slower ROM design and frequencies in the range [0, 24] MHz. '1': 1 wait state. Use this setting for older, slower ROM design and frequencies in the range <24, 48] MHz. CPUSSv2 supports two types of ROM memory: an older, slower design (operating at up to 24 MHz) and a newer, faster design (operating at up to 48 MHz). The older design requires 1 wait state for frequencies above 24 MHz. The newer design never requires wait states. All chips after Street Fighter will use the newer design. As a result, all chips after Street Fighter can always use 0 wait states. 0 1 read-write SL_CTL0 Slave control register 0x100 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL1 Slave control register 0x104 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL10 Slave control register 0x128 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL11 Slave control register 0x12C 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL12 Slave control register 0x130 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL13 Slave control register 0x134 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL14 Slave control register 0x138 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL15 Slave control register 0x13C 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL16 Slave control register 0x140 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL17 Slave control register 0x144 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL18 Slave control register 0x148 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL19 Slave control register 0x14C 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL2 Slave control register 0x108 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL20 Slave control register 0x150 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL21 Slave control register 0x154 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL22 Slave control register 0x158 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL23 Slave control register 0x15C 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL3 Slave control register 0x10C 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL4 Slave control register 0x110 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL5 Slave control register 0x114 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL6 Slave control register 0x118 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL7 Slave control register 0x11C 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL8 Slave control register 0x120 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SL_CTL9 Slave control register 0x124 32 read-write n 0x0 0x0 ARB Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky 16 18 read-write SYSARG SYSARG control register 0x8 32 read-write n 0x0 0x0 SYSCALL_ARG Argument to System Call specified in SYSREQ. Semantics of argument depends on system call made. Typically a pointer to a parameter block. 0 32 read-write SYSREQ SYSCALL control register 0x4 32 read-write n 0x0 0x0 DIS_RESET_VECT_REL Disable Reset Vector fetch relocation: '0': CPU accesses to locations 0x0000:0000 - 0x0000:0007 are redirected to ROM. '1': CPU accesses to locations 0x0000:0000 - 0x0000:0007 are made to flash. Note that this field defaults to '0' on reset, ensuring actual reset vector fetches are always made to ROM. Note that this field does not affect DAP accesses. Flash DfT routines may set this bit to '1' to enable uninhibited read-back of programmed data in the first flash page. 27 28 read-write HMASTER_0 Indicates the source of the write access to the SYSREQ register. '0': CPU write access. '1': DAP write access. HW sets this field when the SYSREQ register is written to and SYSCALL_REQ is '0' (the last time it is set is when SW sets SYSCALL_REQ from '0' to '1'). 30 31 read-only PRIVILEGED Indicates whether the system is in privileged ('1') or user mode ('0'). Only CPU SW executing from ROM can set this field to '1' when ROM_ACCESS_EN is '1' (the CPU is executing a SystemCall NMI interrupt handler). Any other write to this field sets is to '0'. This field is used as the AHB-Lite hprot[1] signal to implement Cypress proprietary user/privileged modes. These modes are used to enable/disable access to specific MMIO registers and memory regions. 28 29 read-write ROM_ACCESS_EN Indicates that executing from Boot ROM is enabled. HW sets this field to '1', on reset or when the SystemCall NMI vector is fetched from Boot ROM. HW sets this field to '0', when the CPU is NOT executing from either Boot or System ROM. This bit is used for debug purposes only. 29 30 read-only SYSCALL_COMMAND Opcode of the system call being requested. 0 16 read-write SYSCALL_REQ CPU/DAP writes a '1' to this field to request a SystemCall. The HMASTER_0 field indicates the source of the write access. Setting this field to '1' immediate results in a NMI. The SystemCall NMI interrupt handler sets this field to '0' after servicing the request. 31 32 read-write WOUNDING Wounding register 0x1C 32 read-write n 0x0 0x0 FLASH_WOUND Indicates the amount of accessible flash in this part. The value in this field is effectively write-once (it is only possible to set bits, not clear them). The remainder portion of flash is not accessible and will return an AHB-Lite bus error. '0': entire memory accessible '1': first 1/2 of the memory accessible '2': first 1/4 of the memory accessible '3': first 1/8 of the memory accessible '4': first 1/16 of the memory accessible '5': first 1/32 of the memory accessible '6': first 1/64 of the memory accessible '7': first 1/128 of the memory accessible (used for the DEAD protection mode) 20 23 read-write RAM1_WOUND Wounding of RAM 1 (see description of RAM_WOUND). 24 27 read-write RAM_WOUND Indicates the amount of accessible RAM 0 memory capacitty in this part. The value in this field is effectively write-once (it is only possible to set bits, not clear them). The remainder portion of SRAM is not accessible and will return an AHB-Lite bus error. '0': entire memory accessible '1': first 1/2 of the memory accessible '2': first 1/4 of the memory accessible '3': first 1/8 of the memory accessible '4': first 1/16 of the memory accessible '5': first 1/32 of the memory accessible '6': first 1/64 of the memory accessible '7': first 1/128 of the memory accessible 16 19 read-write DMAC DataWire/DMA Controller DMAC 0x0 0x0 0x1000 registers n CH_CTL0 Channel control register 0x80 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL1 Channel control register 0x84 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL10 Channel control register 0xA8 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL11 Channel control register 0xAC 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL12 Channel control register 0xB0 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL13 Channel control register 0xB4 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL14 Channel control register 0xB8 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL15 Channel control register 0xBC 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL16 Channel control register 0xC0 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL17 Channel control register 0xC4 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL18 Channel control register 0xC8 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL19 Channel control register 0xCC 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL2 Channel control register 0x88 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL20 Channel control register 0xD0 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL21 Channel control register 0xD4 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL22 Channel control register 0xD8 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL23 Channel control register 0xDC 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL24 Channel control register 0xE0 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL25 Channel control register 0xE4 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL26 Channel control register 0xE8 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL27 Channel control register 0xEC 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL28 Channel control register 0xF0 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL29 Channel control register 0xF4 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL3 Channel control register 0x8C 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL30 Channel control register 0xF8 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL31 Channel control register 0xFC 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL4 Channel control register 0x90 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL5 Channel control register 0x94 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL6 Channel control register 0x98 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL7 Channel control register 0x9C 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL8 Channel control register 0xA0 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CH_CTL9 Channel control register 0xA4 32 read-write n 0x0 0x0 ENABLED '0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled, the data transfer(s) are aborted. '1': channel enabled. Software sets this field to '1' to enable a specific channel. Hardware sets this field to '0' on erroneous channel behavior (the specific error is specified by STATUS.RESP in the channel's descriptor structure). 31 32 read-write PING_PONG Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. Software sets this field to the desired descriptor structure. Hardware inverts the field value on the completion of a descriptor structure when CONTROL.FLIPPING of the current descriptor structure is set to '1'. Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure, the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This field identifies the descriptor structure that is currently in use by the controller. 30 31 read-write PRIO Channel priority, with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same highest priority, the channel with the lowest index i, is considered the highest priority activated channel. 28 30 read-write CTL Control register 0x0 32 read-write n 0x0 0x0 ENABLED 0': IP is disabled. Non-retainable MMIO registers and logic functionality are reset (retainable MMIO registers are NOT reset): - INTR register is set to '0'. - DW/DMA functionality is aborted. - DW/DMA controller input/pending triggers are de-activated. - DW/DMA controller output triggers are de-activated. Disabling the IP has the same effect as an active 'rst_sys_act_n' reset in DeepSleep power mode. To prevent a loss of active (pending) DW/DMA triggers when disabling the IP or when transitioning from Active to DeepSleep power mode, the STATUS.ACTIVE and STATUS_CH_ACTIVE.CH fields can be used. Note that most MMIO registers are retainable, and a transition from DeepSleep to Active/Sleep power modes makes the DW/DMA controller operational, and ready to react to DW/DMA input triggers that are activated after the transition. Triggers are Active/Sleep functionality. '1': IP is enabled. 31 32 read-write INTR Interrupt register 0x7F0 32 read-write n 0x0 0x0 CH Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit. 0 32 read-write INTR_MASK Interrupt mask register 0x7F8 32 read-write n 0x0 0x0 CH Mask for corresponding field in INTR register. 0 32 read-write INTR_MASKED Interrupt masked register 0x7FC 32 read-only n 0x0 0x0 CH Logical and of corresponding request and mask fields. 0 32 read-only INTR_SET Interrupt set register 0x7F4 32 read-write n 0x0 0x0 CH Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). 0 32 read-write PING_CTL Ping control word 0x8 32 read-write n 0x0 0x0 DATA_NR Number of data elements that are transferred by a single descriptor. In DW mode (OPCODE is '0') each trigger initiates the transfer of a single data element. This field specifies the source and/or destination buffer size in data elements: buffer size = DATA_NR+1. The buffer is typically associated to a memory structure. In DMA mode (OPCODE is '1' or '2') each trigger initiates the transfer of DATA_NR+1 data elements. 0 16 read-write DATA_SIZE Specifies the data element size: '0': Byte (8 bits). '1': Halfword (16 bits). '2': Word (32 bits). DATA_SIZE, SRC_TRANSFER_SIZE and DST_TRANSFER_SIZE together determine how data elements are transferred. The following are the 9 legal settings: - DATA is 8 bit, SRC is 8 bit, DST is 8 bit - DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 8 bit - DATA is 8 bit, SRC is 8 bit, DST is 32 bit (higher 24 bits are made '0') - DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 32 bit (higher 24 bits are made '0') - DATA is 16 bit, SRC is 16 bit, DST is 16 bit - DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 16 bit - DATA is 16 bit, SRC is 16 bit, DST is 32 bit (higher 16 bits are made '0') - DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 32 bit (higher 16 bits are made '0') - DATA is 32 bit, SRC is 32 bit, DST is 32 bit 16 18 read-write DST_ADDR_INCR Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not. '0' : No increment, typically used for transmit (TX) FIFO structures. '1': Increment, typically used for memory structures. 21 22 read-write DST_TRANSFER_SIZE Specifies the bus transfer size to the destination location: '0': As specified by DATA_SIZE. '1': Word (32 bits). Distinguishing bus transfer size from data element size allows for destination components with data elements that are smaller than their 32-bit bus interface width. E.g., a DAC destination has a 32-bit bus transfer size, but only requires a 16-bit data element. 20 21 read-write FLIPPING '1': On completion of the current descriptor structure, the current descriptor identifier CHi_CTL.PING_PONG is flipped/inverted. In DMA mode, descriptor list transfer, flipping of the current descriptor identifier can be used to construct a linked list of descriptor structures. 29 30 read-write INV_DESCR '1': On completion of the current descriptor structure, the VALID bit of the descriptor's STATUS word is set to '0'. 26 27 read-write OPCODE Specifies the specific data transfer (only when the VALID bit of the descriptor's STATUS word is '1'): '0': A single trigger initiates a single data element transfer (DW mode). This opcode specifies a transfer of a single data element. The current descriptor is completed when the amount of transferred single data elements equals the programmed buffer size (DATA_NR+1). '1': A single trigger initiates a single descriptor transfer (DMA mode). This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure. The current descriptor is completed when its data transfer is completed. '2': A single trigger initiates a descriptor list transfer (DMA mode). This opcode specifies a transfer of DATA_NR+1 data elements as specified by the current descriptor structure and by successive valid descriptors. The current descriptor is completed when its data transfer is completed. This OPCODE relies on FLIPPING to be set to '1', such that the CHi_CTL.PING_PONG field is flipped/inverted and the successive descriptor is used. This continues for as long as the successive descriptor is valid. Note that as the HW is using the PING/PONG descriptor, the SW can prepare the alternate PONG/PING descriptor. The interrupt mechanism is used by HW to convey to the SW that the current descriptor is completed (and can be prepared for a successive transfer). After completerion of the opcode (and waiting for de-activation, the channel's output trigger is activated). 30 32 read-write PREEMPTABLE '1': Transfer is preemptable. In DMA mode (OPCODE is '1' or '2'), multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field allows higher priority activated channels to preempt the current transfer in between these atomic (load, store) sequences. Preemption will NOT deactivate the current channel. As a result, after completion of a higher priority activated channel, the current channel is rescheduled. 28 29 read-write SET_CAUSE '1': On completion of the current descriptor structure, the interrupt cause field of the channel is set to '1' (INTR.CH[i]). 27 28 read-write SRC_ADDR_INCR Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not. '0': No increment, typically used for receive (RX) FIFO structures. '1': Increment, typically used for memory structures. 23 24 read-write SRC_TRANSFER_SIZE Specifies the bus transfer size to the source location: '0': As specified by DATA_SIZE. '1': Word (32 bits). Distinguishing bus transfer size from data element size allows for source components with data elements that are smaller than their 32-bit bus interface width. E.g., an ADC source has a 32-bit bus transfer size, but only provides a 16-bit data element. 22 23 read-write WAIT_FOR_DEACT Specifies whether the data transfer engine should wait for the channel to be deactivated i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the trigger. This field is ONLY used at the completion of an opcode. E.g., a FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the transfer engine AND received by the agent. Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the DW/DMA controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW/DMA controller performance. '0': Do not wait for de-activation (for pulse sensitive triggers). '1': Wait for up to 4 cycles. '2': Wait for up to 8 cycles. '3': Wait indefinitely. This option may result in DW/DMA controller lockup if the system trigger is not de-activated by the source agent. 24 26 read-write PING_DST Ping destination address 0x4 32 read-write n 0x0 0x0 ADDR Base address of destination location. The effective destination location is calculated by adding on offset (derived from PING.STATUS.CURR_DATA_NR) to this base address. 0 32 read-write PING_SRC Ping source address 0x0 32 read-write n 0x0 0x0 ADDR Base address of source location. The effective source location is calculated by adding on offset (derived from PING.STATUS.CURR_DATA_NR) to this base address. 0 32 read-write PING_STATUS Ping status word 0xC 32 read-write n 0x0 0x0 CURR_DATA_NR Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field: - When a descriptor is done (RESPONSE is DONE), the field is set to '0' when PING_CTL.INV_DESCR is '0' and the field is set to PING_CTL.DATA_NR when PING_CTL.INV_DESCR is '1'. - When a descriptor is not done (RESPONSE is NO_ERROR), the field reflects the progress of a data transfer. - In case of erroneous behavior (RESPONSE is neither DONE or NO_ERROR), the field is not updated, but keeps its value to ease debugging. HW only modifies this field for an active descriptor (STATUS.VALID to be '1'). At descriptor initialization, SW should set this field to '0'. This field allows software to read the progress of the data transfer. Note that SRC.ADDR and DST.ADDR represent base addresses and are not modified during data transfer. However, STATUS.CURR_DATA_NR is modified during data transfer and provides an offset wrt. the base addresses. 0 16 read-write RESPONSE Response code (the first two codes NO_ERROR and DONE are the result of normal behavior, the other codes are the result of erroneous behavior). '0'/NO_ERROR: No error. Setting this response does NOT set the interrupt cause bit to '1'. STATUS.VALID is NOT affected. CHi_CTL.ENABLED is NOT affected. CHi_CTL.PING_PONG is not updated. This response is used for an unused or not completed descriptor. Software should set the RESPONSE field to '0'/NO_ERROR during descriptor initialization. '1'/DONE: Descriptor is done (without errors). Setting this response sets the interrupt cause bit to '1' if CONTROL.SET_CAUSE is '1'. STATUS.VALID is set to '0' if CONTROL.INV_DESCR is '1'. CHi_CTL.ENABLED is NOT affected. CHi_CTL.PING_PONG is updated if CONTROL.FLIPPING is '1'. '2'/SRC_BUS_ERROR: Bus error while loading data from the source location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHi_CTL.ENABLED is set to '0'. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). '3'/DST_BUS_ERROR: Bus error while storing data to the destination location. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHi_CTL.ENABLED is set to '0'. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). '4'/SRC_MISAL: Misalignment of source address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHi_CTL.ENABLED is set to '0'. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). '5'/DST_MISAL: Misalignment of destination address. This occurs on a 16-bit bus transfer that is not 2-byte aligned or on a 32-bit bus transfer that is not 4-byte aligned. Setting this response sets the interrupt cause bit to '1'. STATUS.VALID is set '0'. CHi_CTL.ENABLED is set to '0'. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). '6'/INVALID_DESCR: Invalid descriptor (STATUS.VALID is '0'). This occurs when an activated channel has an invalid descriptor. CHi_CTL.ENABLED is set to '0'. CHi_CTL.PING_PONG is not updated (it identifies the descriptor that caused the error). 16 19 read-write VALID '0': Invalid, cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code (and the interrupt cause bit is set to '1'). '1': Valid. Hardware set this field to '0' when a descriptor is done, but only if CONTROL.INV_DESCR is '1'. Software sets this field to '1' when a descriptor is initialized. 31 32 read-write PONG_CTL Pong control word 0x18 32 read-write n 0x0 0x0 DATA_NR See description of PING_CTL. 0 16 read-write DATA_SIZE See description of PING_CTL. 16 18 read-write DST_ADDR_INCR See description of PING_CTL. 21 22 read-write DST_TRANSFER_SIZE See description of PING_CTL. 20 21 read-write FLIPPING See description of PING_CTL. 29 30 read-write INV_DESCR See description of PING_CTL. 26 27 read-write OPCODE See description of PING_CTL. 30 32 read-write PREEMPTABLE See description of PING_CTL. 28 29 read-write SET_CAUSE See description of PING_CTL. 27 28 read-write SRC_ADDR_INCR See description of PING_CTL. 23 24 read-write SRC_TRANSFER_SIZE See description of PING_CTL. 22 23 read-write WAIT_FOR_DEACT See description of PING_CTL. 24 26 read-write PONG_DST Pong destination address 0x14 32 read-write n 0x0 0x0 ADDR See description of PING_DST. 0 32 read-write PONG_SRC Pong source address 0x10 32 read-write n 0x0 0x0 ADDR See description of PING_SRC. 0 32 read-write PONG_STATUS Pong status word 0x1C 32 read-write n 0x0 0x0 CURR_DATA_NR See description of PING_STATUS. 0 16 read-write RESPONSE See description of PING_STATUS. 16 19 read-write VALID See description of PING_STATUS. 31 32 read-write STATUS Status register 0x10 32 read-only n 0x0 0x0 ACTIVE Specifies if there is a currently active (pending) channel in the data transfer engine: '0': no currently active channel. '1': currently active channel. 31 32 read-only CH_ADDR Specifies the channel number of the currently active channel. E.g. if we have 32 channels, the channel number address with CH_ADDR_WIDTH is LOG2 (32) = 5, and this field is a 5-bit field. If channel 7 is active, STATUS.ACTIVE is '1' and STATUS.CH_ADDR is '7'. 16 21 read-only DATA_NR Specifies the index of the currently active data transfer. This value increases from '0' to CONTROL.DATA_NR. 0 16 read-only PING_PONG Specifies whether the PING descriptor ('0') or PONG descriptor ('1') of the channel is currently in use. 30 31 read-only PRIO Specifies the priority of the currently active channel. 28 30 read-only STATE State of the data transfer engine. '0': DEFAULT state. '1': Loading descriptor (SRC, DST, CONTROL and STATUS words). '2': Loading data element from source location. '3': Storing data element to destination location. '4': Storing descriptor (STATUS word). '5': Wait for trigger de-activation. '6': Storing descriptor with error response (STATUS word). 24 27 read-only STATUS_CH_ACT Channel activation status register 0x1C 32 read-only n 0x0 0x0 CH Channel activation status. Bit i is associated to channel i, with i = 0, ..., CH_NR-1. Software reads this field to get information on all actively pending channels (either in pending or in the data transfer engine). 0 32 read-only STATUS_DST_ADDR Destination address register 0x18 32 read-only n 0x0 0x0 ADDR Base address or current address of destination location of currently active channel. The specific address information is cycle dependent. This is field is provided for debug purposes. Functionally, no assumption should be made on whether the base or current address is provided. The specifics of the currently active channel are available through STATUS. Note while reading the STATUS, STATUS_SRC and STATUS_DST registers, the transfer engine may have moved from one active channel to another. 0 32 read-only STATUS_SRC_ADDR Source address status register 0x14 32 read-only n 0x0 0x0 ADDR Base address or current address of source location of currently active channel. The specific address information is cycle dependent. This is field is provided for debug purposes. Functionally, no assumption should be made on whether the base or current address is provided. The specifics of the currently active channel are available through STATUS. Note while reading the STATUS, STATUS_SRC and STATUS_DST registers, the transfer engine may have moved from one active channel to another. 0 32 read-only GPIO GPIO port control/configuration GPIO 0x0 0x0 0x4000 registers n DR Port output data register 0x0 32 read-write n 0x0 0x0 DATA0 IO pad 0 output data. 0 1 read-write DATA1 IO pad 1 output data. 1 2 read-write DATA2 IO pad 2 output data. 2 3 read-write DATA3 IO pad 3 output data. 3 4 read-write DATA4 IO pad 4 output data. 4 5 read-write DATA5 IO pad 5 output data. 5 6 read-write DATA6 IO pad 6 output data. 6 7 read-write DATA7 IO pad 7 output data. 7 8 read-write DR_CLR Port output data clear register 0x44 32 read-write n 0x0 0x0 DATA IO pad i: '0': Output state DR.DATA[i] not affected. '1': Output state DR.DATA[i] set to '0'. 0 8 read-write DR_INV Port output data invert register 0x48 32 read-write n 0x0 0x0 DATA IO pad i: '0': Output state DR.DATA[i] not affected. '1': Output state DR.DATA[i] inverted ('0' => '1', '1' => '0'). 0 8 read-write DR_SET Port output data set register 0x40 32 read-write n 0x0 0x0 DATA IO pad i: '0': Output state DR.DATA[i] not affected. '1': Output state DR.DATA[i] set to '1'. 0 8 read-write DS Port drive strength register 0x4C 32 read-write n 0x0 0x0 DS0 The GPIO drive strength for IO pad 0. 0 2 read-write 0 Refer to s8iom0s8v1p2 BROS Table11. 0 1 Refer to s8iom0s8v1p2 BROS Table11. 1 2 Refer to s8iom0s8v1p2 BROS Table11. 2 3 Refer to s8iom0s8v1p2 BROS Table11. 3 DS1 The GPIO drive strength for IO pad 1. 2 4 read-write DS2 The GPIO drive strength for IO pad 2. 4 6 read-write DS3 The GPIO drive strength for IO pad 3. 6 8 read-write DS4 The GPIO drive strength for IO pad 4. 8 10 read-write DS5 The GPIO drive strength for IO pad 5. 10 12 read-write DS6 The GPIO drive strength for IO pad 6. 12 14 read-write DS7 The GPIO drive strength for IO pad 7. 14 16 read-write PORT_V1P2_IB_MODE_SEL For GPIOV1P2 cell, 0: vtrip_sel register controls the vtrip_sel of the IO cells 1: vddio detect cell output controls the vtrip_sel of the IO cells For GPIOV1P2_I2C cells, refer to PORT_VTRIP_SEL description for usage. 17 18 read-write PORT_V1P2_VTRIP_SEL For GPIOV1P2: 0: 1.2V VDDIO 1: 1.8V VDDIO For GPIOV1P_I2C cells: Used in conjunction with PORT_V1P2_IB_MODE_SEL PORT_V1P2_VTRIP_SEL,PORT_V1P2_IB_MODE_SEL 0,0 - VDDIO 1.2V and VDDI2C 1.2V 1,1 - VDDIO 1.2V and VDDI2C 1.8V 0,0 - VDDIO 1.8V and VDDI2C 1.8V All other combinations are illegal 16 17 read-write FILT_CONFIG IO filter config register 0x50 32 read-write n 0x0 0x0 FILT0_EN Filter selection for IO pad 0 16 17 read-write FILT1_EN Filter selection for IO pad 1 17 18 read-write FILT2_EN Filter selection for IO pad 2 18 19 read-write FILT3_EN Filter selection for IO pad 3 19 20 read-write FILT4_EN Filter selection for IO pad 4 20 21 read-write FILT5_EN Filter selection for IO pad 5 21 22 read-write FILT6_EN Filter selection for IO pad 6 22 23 read-write FILT7_EN Filter selection for IO pad 7 23 24 read-write TRIM0 trim bits for 50ns filter on IO pad 0 0 2 read-write TRIM1 trim bits for 50ns filter on IO pad 1 2 4 read-write TRIM2 trim bits for 50ns filter on IO pad 2 4 6 read-write TRIM3 trim bits for 50ns filter on IO pad 3 6 8 read-write TRIM4 trim bits for 50ns filter on IO pad 4 8 10 read-write TRIM5 trim bits for 50ns filter on IO pad 5 10 12 read-write TRIM6 trim bits for 50ns filter on IO pad 6 12 14 read-write TRIM7 trim bits for 50ns filter on IO pad 7 14 16 read-write GPIOV1P2_DET GPIOV1P2 Detect output 0x1020 32 read-only n 0x0 0x0 DET Indicates HI when VDDIO is in 1.8V range, and LOW when VDDIO is in 1.2V range. 0 1 read-only INTR Port interrupt status register 0x10 32 read-write n 0x0 0x0 DATA0 Interrupt pending on IO pad 0. Firmware writes 1 to clear the interrupt. 0 1 read-write DATA1 Interrupt pending on IO pad 1. Firmware writes 1 to clear the interrupt. 1 2 read-write DATA2 Interrupt pending on IO pad 2. Firmware writes 1 to clear the interrupt. 2 3 read-write DATA3 Interrupt pending on IO pad 3. Firmware writes 1 to clear the interrupt. 3 4 read-write DATA4 Interrupt pending on IO pad 4. Firmware writes 1 to clear the interrupt. 4 5 read-write DATA5 Interrupt pending on IO pad 5. Firmware writes 1 to clear the interrupt. 5 6 read-write DATA6 Interrupt pending on IO pad 6. Firmware writes 1 to clear the interrupt. 6 7 read-write DATA7 Interrupt pending on IO pad 7. Firmware writes 1 to clear the interrupt. 7 8 read-write FLT_DATA Deglitched interrupt pending (selected by FLT_SELECT). 8 9 read-write PS_DATA0 ` 16 17 read-only PS_DATA1 N/A 17 18 read-only PS_DATA2 N/A 18 19 read-only PS_DATA3 N/A 19 20 read-only PS_DATA4 N/A 20 21 read-only PS_DATA5 N/A 21 22 read-only PS_DATA6 N/A 22 23 read-only PS_DATA7 N/A 23 24 read-only PS_FLT_DATA This is a duplicate of the contents of the PS register, provided here to allow reading of both pin state and interrupt state of the port in a single read operation. 24 25 read-only INTR_CAUSE Interrupt port cause register 0x1000 32 read-only n 0x0 0x0 PORT_INT Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a shared/combined interrupt line 'gpio_interrupt'. The SW ISR reads the register to deternine which IO port(s) is responsible for the shared/combined interrupt line 'gpio_interrupt'. Once, the IO port(s) is determined, the IO port's INTR register is read to determine the IO pad(s) in the IO port that caused the interrupt. 0 32 read-only INTR_CFG Port interrupt configuration register 0xC 32 read-write n 0x0 0x0 EDGE0_SEL Sets which edge will trigger an IRQ for IO pad 0. 0 2 read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 EDGE1_SEL Sets which edge will trigger an IRQ for IO pad 1. 2 4 read-write EDGE2_SEL Sets which edge will trigger an IRQ for IO pad 2. 4 6 read-write EDGE3_SEL Sets which edge will trigger an IRQ for IO pad 3. 6 8 read-write EDGE4_SEL Sets which edge will trigger an IRQ for IO pad 4. 8 10 read-write EDGE5_SEL Sets which edge will trigger an IRQ for IO pad 5. 10 12 read-write EDGE6_SEL Sets which edge will trigger an IRQ for IO pad 6. 12 14 read-write EDGE7_SEL Sets which edge will trigger an IRQ for IO pad 7. 14 16 read-write FLT_EDGE_SEL Same for the glitch filtered pin (selected by FLT_SELECT). 16 18 read-write DISABLE Disabled 0 RISING Rising edge 1 FALLING Falling edge 2 BOTH Both rising and falling edges 3 FLT_SEL Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt. 18 21 read-write PC Port configuration register 0x8 32 read-write n 0x0 0x0 DM0 The GPIO drive mode for IO pad 0. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the HSIOM is properly configured (HSIOM_PRT_SELx) before turning the IO on here to avoid producing glitches on the bus. 0 3 read-write OFF Mode 0 (analog mode): Output buffer off (high Z). Input buffer off. 0 INPUT Mode 1: Output buffer off (high Z). Input buffer on. 1 0_PU Mode 2: Strong pull down ('0'), weak/resistive pull up (PU). Input buffer on. For GPIOV1P2_I2C, Strong pull down only. 2 PD_1 Mode 3: Weak/resistive pull down (PD), strong pull up ('1'). Input buffer on. For GPIOV1P2_I2C: Weak pull down only. 3 0_Z Mode 4: Strong pull down ('0'), open drain (pull up off). Input buffer on. For GPIOV1P2_I2C, Strong pull down only. 4 Z_1 Mode 5: Open drain (pull down off), strong pull up ('1'). Input buffer on. Illegal for GPIOV1P2_I2C 5 0_1 Mode 6: Strong pull down ('0'), strong pull up ('1'). Input buffer on. For GPIOV1P2_I2C, Strong pull down only. 6 PD_PU Mode 7: Weak/resistive pull down (PD), weak/resistive pull up (PU). Input buffer on. For GPIOV1P2_I2C: Weak pull down only. 7 DM1 The GPIO drive mode for IO pad 1. 3 6 read-write DM2 The GPIO drive mode for IO pad 2. 6 9 read-write DM3 The GPIO drive mode for IO pad 3. 9 12 read-write DM4 The GPIO drive mode for IO pad 4. 12 15 read-write DM5 The GPIO drive mode for IO pad 5. 15 18 read-write DM6 The GPIO drive mode for IO pad 6. 18 21 read-write DM7 The GPIO drive mode for IO pad 7. 21 24 read-write PORT_HYST_TRIM This field is used to improve the hysteresis (to 10 percent of vddio) of the selectable trip point input buffer. The voltage reference comes from the VREFGEN block and is only available when using the VREFGEN block: '0': <= 2.2 V input signaling Voltage. '1': > 2.2 V input signaling Voltage. 27 28 read-write PORT_IB_MODE_SEL This field selects the input buffer reference. The size (1 or 2 bits) and functionality is dependent on the IO cell. For GPIOv2 IO cells, bit PORT_IB_MODE_SEL[1] is not used (GPIOv2 IO cell replaces GPIO IO cell): '0'/'2': CMOS input buffer (PORT_VTRIP_SEL is '0'), LVTTL input buffer (PORT_VTRIP_SEL is '1') '1'/'3': vcchib. For GPIO_OVTv2 and SIOv2 IO cells: '0': CMOS input buffer (PORT_VTRIP_SEL is '0'), LVTTL input buffer (PORT_VTRIP_SEL is '1') '1': vcchib. '2': OVT. '3': Reference (possibly from reference generator cell). For SIO IO cell, this field is present but not used as the SIO IO cell does not provide input buffer mode select functionality (SIOv2 IO cell will replace SIO IO cell, as soon as it is available). For GPIOV1P2 and GPIOV1P2_I2C cells, PC.PORT_IB_MODE_SEL unused. Refer to DS register. 30 32 read-write PORT_SLEW_CTL Slew control. Only used in the O_Z drive mode (mode 4: strong pull down, open drain): This field is intended for I2C functionality. See BROS 001-70428 for more details. 28 30 read-write PORT_SLEW_CTL_0 HS mode (100pf < Cb < 400pF, 1.713.0) FS mode (10pf 0 PORT_SLEW_CTL_1 HS mode (Cb<100pf,1.712.8,F=1.7MHz) (10-80ns) FS+ Mode (Vext>2.8,1.71 1 PORT_SLEW_CTL_2 HS mode (100pf 2 PORT_SLEW_CTL_3 HS mode (Cb<100pf,1.71 3 PORT_SLOW This field controls the output edge rate of all pins on the port: '0': fast. '1': slow. 25 26 read-write PORT_VTRIP_SEL The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage. Note: this bit is ignored for SIO ports, the VTRIP_SEL settings in the SIO register are used instead (a separate VTRIP_SEL is provided for each pin pair). 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. For GPIOV1P2 and GPIOV1P_I2C cells, PC.PORT_VTRIP_SEL is unused. Refer to DS register 24 25 read-write PC2 Port configuration register 2 0x18 32 read-write n 0x0 0x0 INP_DIS0 Disables the input buffer for IO pad 0 independent of the port control drive mode (PC.DM). This bit should be set when analog signals are present on the pin and PC.DM != 0 is required to use the output driver. 0 1 read-write INP_DIS1 Disables the input buffer for IO pad 1. 1 2 read-write INP_DIS2 Disables the input buffer for IO pad 2. 2 3 read-write INP_DIS3 Disables the input buffer for IO pad 3. 3 4 read-write INP_DIS4 Disables the input buffer for IO pad 4. 4 5 read-write INP_DIS5 Disables the input buffer for IO pad 5. 5 6 read-write INP_DIS6 Disables the input buffer for IO pad 6. 6 7 read-write INP_DIS7 Disables the input buffer for IO pad 7. 7 8 read-write PS Port IO pad state register 0x4 32 read-only n 0x0 0x0 DATA0 IO pad 0 state: 1: Logic high, if the pin voltage is above the input buffer threshold, logic high. 0: Logic low, if the pin voltage is below that threshold, logic low. If the drive mode for the pin is set to high Z Analog, the pin state will read 0 independent of the voltage on the pin. 0 1 read-only DATA1 IO pad 1 state. 1 2 read-only DATA2 IO pad 2 state. 2 3 read-only DATA3 IO pad 3 state. 3 4 read-only DATA4 IO pad 4 state. 4 5 read-only DATA5 IO pad 5 state. 5 6 read-only DATA6 IO pad 6 state. 6 7 read-only DATA7 IO pad 7 state. 7 8 read-only FLT_DATA Reads of this register return the logical state of the filtered pin. 8 9 read-only SIO Port SIO configuration register 0x14 32 read-write n 0x0 0x0 PAIR_IBUF01_SEL Selects input buffer mode: 0: singled ended input buffer 1: differential input buffer 1 2 read-write PAIR_IBUF23_SEL See corresponding definition for IO pads 2 and 3. 9 10 read-write PAIR_IBUF45_SEL See corresponding definition for IO pads 4 and 5. 17 18 read-write PAIR_IBUF67_SEL See corresponding definition for IO pads 6 and 7. 25 26 read-write PAIR_VOH01_SEL Selects regulated Voh output level and trip point of input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL). 0: Voh = 1*reference e.g. reference at 1.2V -> Voh = 1.2V 1: Voh = 1.25*reference e.g. reference at 1.2V -> Voh = 1.5V 2: Voh = 1.49*reference e.g. reference at 1.2V -> Voh = ~1.8V 3: Voh = 1.67*reference e.g. reference at 1.2V -> Voh = 2V 4: Voh = 2.08*reference e.g. reference at 1.2V -> Voh = 2.5V 5: Voh = 2.5*reference e.g. reference at 1.2V -> Voh = 3V 6: Voh = 2.78*reference e.g. reference at 1.2V -> Voh = ~3.3V 7: Voh = 4.16*reference e.g. reference at 1.2V -> Voh = 5.0V Note: The upper value on VOH is limited to Vddio - 400mV 5 8 read-write PAIR_VOH23_SEL See corresponding definition for IO pads 2 and 3. 13 16 read-write PAIR_VOH45_SEL See corresponding definition for IO pads 4 and 5. 21 24 read-write PAIR_VOH67_SEL See corresponding definition for IO pads 6 and 7. 29 32 read-write PAIR_VREF01_SEL Selects reference voltage Vref for trip-point of input buffer: 0: trip-point reference of SRSS internal referece Vref (1.2V) 1: trip-point reference of SRSS internal referece Vref (1.2V) 2: trip-point reference of AMUXBUS_A 3: trip-point reference of AMUXBUS_B Please refer to s8iom0s8 BROS 001-70428, section 4.2.7 for more details. 3 5 read-write PAIR_VREF23_SEL See corresponding definition for IO pads 2 and 3. 11 13 read-write PAIR_VREF45_SEL See corresponding definition for IO pads 4 and 5. 19 21 read-write PAIR_VREF67_SEL See corresponding definition for IO pads 6 and 7. 27 29 read-write PAIR_VREG01_EN Selects output buffer mode: 0: unregulated output buffer 1: regulated output buffer 0 1 read-write PAIR_VREG23_EN See corresponding definition for IO pads 2 and 3. 8 9 read-write PAIR_VREG45_EN See corresponding definition for IO pads 4 and 5. 16 17 read-write PAIR_VREG67_EN See corresponding definition for IO pads 6 and 7. 24 25 read-write PAIR_VTRIP01_SEL Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'): 0: input buffer functions as a CMOS input buffer. 1: input buffer functions as a LVTTL input buffer. In differential input buffer mode (IBUF01_SEL = '1') '0': trip-point is 0.5*Vddio or 0.5*Voh (depends on VREF_SEL/VOH_SEL) '1': trip-point is 0.4*Vddio or 1.0*Vref (depends on VREF_SEL) Please refer to s8iom0s8 BROS 001-70428, section 4.2.7 for more details. 2 3 read-write PAIR_VTRIP23_SEL See corresponding definition for IO pads 2 and 3. 10 11 read-write PAIR_VTRIP45_SEL See corresponding definition for IO pads 4 and 5. 18 19 read-write PAIR_VTRIP67_SEL See corresponding definition for IO pads 6 and 7. 26 27 read-write VREFGEN Reference generator configuration register 0x80 32 read-write n 0x0 0x0 REF_SEL Reference selection. A reference Voltage vinref is created using a Voltage vddio: '0': vinref = (0 * 13 + 184)/600 * vddio = 184/600 * vddio. '1': vinref = (1 * 13 + 184)/600 * vddio = 197/600 * vddio. '2': vinref = (2 * 13 + 184)/600 * vddio = 210/600 * vddio. ... '31': vinref = (31 * 13 + 184)/600 * vddio = 587/600 * vddio. 0 5 read-write VREFGEN_EN Reference generator enable: '0': Disabled. '1': Enabled. 8 9 read-write HSIOM High Speed IO Matrix (HSIOM) HSIOM 0x0 0x0 0x4000 registers n AMUX_SPLIT_CTL0 AMUX splitter cell control 0x2100 32 read-write n 0x0 0x0 SWITCH_AA_S0 T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed. 2 3 read-write SWITCH_AA_SL T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed. 0 1 read-write SWITCH_AA_SR T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed. 1 2 read-write SWITCH_BB_S0 T-switch control for AMUXBUSB vssa/ground switch. 6 7 read-write SWITCH_BB_SL T-switch control for Left AMUXBUSB switch. 4 5 read-write SWITCH_BB_SR T-switch control for Right AMUXBUSB switch. 5 6 read-write AMUX_SPLIT_CTL1 AMUX splitter cell control 0x2104 32 read-write n 0x0 0x0 SWITCH_AA_S0 T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed. 2 3 read-write SWITCH_AA_SL T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed. 0 1 read-write SWITCH_AA_SR T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed. 1 2 read-write SWITCH_BB_S0 T-switch control for AMUXBUSB vssa/ground switch. 6 7 read-write SWITCH_BB_SL T-switch control for Left AMUXBUSB switch. 4 5 read-write SWITCH_BB_SR T-switch control for Right AMUXBUSB switch. 5 6 read-write AMUX_SPLIT_CTL2 AMUX splitter cell control 0x2108 32 read-write n 0x0 0x0 SWITCH_AA_S0 T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed. 2 3 read-write SWITCH_AA_SL T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed. 0 1 read-write SWITCH_AA_SR T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed. 1 2 read-write SWITCH_BB_S0 T-switch control for AMUXBUSB vssa/ground switch. 6 7 read-write SWITCH_BB_SL T-switch control for Left AMUXBUSB switch. 4 5 read-write SWITCH_BB_SR T-switch control for Right AMUXBUSB switch. 5 6 read-write AMUX_SPLIT_CTL3 AMUX splitter cell control 0x210C 32 read-write n 0x0 0x0 SWITCH_AA_S0 T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed. 2 3 read-write SWITCH_AA_SL T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed. 0 1 read-write SWITCH_AA_SR T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed. 1 2 read-write SWITCH_BB_S0 T-switch control for AMUXBUSB vssa/ground switch. 6 7 read-write SWITCH_BB_SL T-switch control for Left AMUXBUSB switch. 4 5 read-write SWITCH_BB_SR T-switch control for Right AMUXBUSB switch. 5 6 read-write AMUX_SPLIT_CTL4 AMUX splitter cell control 0x2110 32 read-write n 0x0 0x0 SWITCH_AA_S0 T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed. 2 3 read-write SWITCH_AA_SL T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed. 0 1 read-write SWITCH_AA_SR T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed. 1 2 read-write SWITCH_BB_S0 T-switch control for AMUXBUSB vssa/ground switch. 6 7 read-write SWITCH_BB_SL T-switch control for Left AMUXBUSB switch. 4 5 read-write SWITCH_BB_SR T-switch control for Right AMUXBUSB switch. 5 6 read-write AMUX_SPLIT_CTL5 AMUX splitter cell control 0x2114 32 read-write n 0x0 0x0 SWITCH_AA_S0 T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed. 2 3 read-write SWITCH_AA_SL T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed. 0 1 read-write SWITCH_AA_SR T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed. 1 2 read-write SWITCH_BB_S0 T-switch control for AMUXBUSB vssa/ground switch. 6 7 read-write SWITCH_BB_SL T-switch control for Left AMUXBUSB switch. 4 5 read-write SWITCH_BB_SR T-switch control for Right AMUXBUSB switch. 5 6 read-write AMUX_SPLIT_CTL6 AMUX splitter cell control 0x2118 32 read-write n 0x0 0x0 SWITCH_AA_S0 T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed. 2 3 read-write SWITCH_AA_SL T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed. 0 1 read-write SWITCH_AA_SR T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed. 1 2 read-write SWITCH_BB_S0 T-switch control for AMUXBUSB vssa/ground switch. 6 7 read-write SWITCH_BB_SL T-switch control for Left AMUXBUSB switch. 4 5 read-write SWITCH_BB_SR T-switch control for Right AMUXBUSB switch. 5 6 read-write AMUX_SPLIT_CTL7 AMUX splitter cell control 0x211C 32 read-write n 0x0 0x0 SWITCH_AA_S0 T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed. 2 3 read-write SWITCH_AA_SL T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed. 0 1 read-write SWITCH_AA_SR T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed. 1 2 read-write SWITCH_BB_S0 T-switch control for AMUXBUSB vssa/ground switch. 6 7 read-write SWITCH_BB_SL T-switch control for Left AMUXBUSB switch. 4 5 read-write SWITCH_BB_SR T-switch control for Right AMUXBUSB switch. 5 6 read-write PORT_SEL Port selection register 0x0 32 read-write n 0x0 0x0 IO0_SEL Selects connection for IO pad 0 route. 0 4 read-write GPIO SW controlled GPIO. 0 GPIO_DSI SW controlled 'out', DSI controlled 'oe_n'. 1 ACT_2 Chip specific Active source 2 connection. 10 ACT_3 Chip specific Active source 3 connection. 11 LCD_COM LCD common connection. This mode provides DeepSleep functionality (provided that the LCD block is enabled and properly configured). 12 LCD_SEG LCD segment connection. This mode provides DeepSleep functionality (provided that the LCD block is enabled and properly configured). 13 DS_2 Chip specific DeepSleep source 2 connection. 14 DS_3 Chip specific DeepSleep source 3 connection. 15 DSI_DSI DSI controlled 'out' and 'oe_n'. 2 DSI_GPIO DSI controlled 'out', SW controlled 'oe_n'. 3 CSD_SENSE CSD sense connection (analog mode) 4 CSD_SHIELD CSD shield connection (analog mode) 5 AMUXA AMUXBUS A connection. 6 AMUXB AMUXBUS B connection. This mode is also used for CSD GPIO charging. When CSD GPIO charging is enabled in CSD_CONTROL, 'oe_n' is connected to '!csd_charge' signal (and IO pad is also still connected to AMUXBUS B). 7 ACT_0 Chip specific Active source 0 connection. 8 ACT_1 Chip specific Active source 1 connection. 9 IO1_SEL Selects connection for IO pad 1 route. 4 8 read-write IO2_SEL Selects connection for IO pad 2 route. 8 12 read-write IO3_SEL Selects connection for IO pad 3 route. 12 16 read-write IO4_SEL Selects connection for IO pad 4 route. 16 20 read-write IO5_SEL Selects connection for IO pad 5 route. 20 24 read-write IO6_SEL Selects connection for IO pad 6 route. 24 28 read-write IO7_SEL Selects connection for IO pad 7 route. 28 32 read-write PUMP_CTL Pump control 0x2000 32 read-write n 0x0 0x0 CLOCK_SEL Clock select: '0': External clock. '1': Internal clock (deprecated). 0 1 read-write ENABLED Pump enabled: '0': Disabled. '1': Enabled. 31 32 read-write LCD LCD Controller Block LCD 0x0 0x0 0x10000 registers n CONTROL LCD Configuration Register 0x8 32 read-write n 0x0 0x0 BIAS PWM bias selection 5 7 read-write HALF 1/2 Bias 0 THIRD 1/3 Bias 1 FOURTH 1/4 Bias (not supported by LS generator) 2 FIFTH 1/5 Bias (not supported by LS generator) 3 COM_NUM The number of COM connections minus 2. So: 0: 2 COM's 1: 3 COM's ... 13: 15 COM's 14: 16 COM's 15: undefined 8 12 read-write HS_EN High speed (HS) generator enable 1: enable 0: disable 1 2 read-write LCD_MODE HS/LS Mode selection 2 3 read-write LS Select Low Speed (32kHz) Generator (Works in Active, Sleep and DeepSleep power modes). 0 HS Select High Speed (system clock) Generator (Works in Active and Sleep power modes only). 1 LS_EN Low speed (LS) generator enable 1: enable 0: disable 0 1 read-write LS_EN_STAT LS enable status bit. This bit is a copy of LS_EN that is synchronized to the low speed clock domain and back to the system clock domain. Firmware can use this bit to observe whether LS_EN has taken effect in the low speed clock domain. Firmware should never change the configuration for the LS generator without ensuring this bit is 0. The following procedure should be followed to disable the LS generator: 1. If LS_EN=0 we are done. Exit the procedure. 2. Check that LS_EN_STAT=1. If not, wait until it is. This will catch the case of a recent enable (LS_EN=1) that has not taken effect yet. 3. Set LS_EN=0. 4. Wait until LS_EN_STAT=0. 31 32 read-only OP_MODE Driving mode configuration 4 5 read-write PWM PWM Mode 0 CORRELATION Digital Correlation Mode 1 TYPE LCD driving waveform type configuration. 3 4 read-write TYPE_A Type A - Each frame addresses each COM pin only once with a balanced (DC=0) waveform. 0 TYPE_B Type B - Each frame addresses each COM pin twice in sequence with a positive and negative waveform that together are balanced (DC=0). 1 DATA00 LCD Pin Data Registers 0x100 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb). 0 32 read-write DATA01 LCD Pin Data Registers 0x104 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb). 0 32 read-write DATA02 LCD Pin Data Registers 0x108 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb). 0 32 read-write DATA03 LCD Pin Data Registers 0x10C 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb). 0 32 read-write DATA04 LCD Pin Data Registers 0x110 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb). 0 32 read-write DATA05 LCD Pin Data Registers 0x114 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb). 0 32 read-write DATA06 LCD Pin Data Registers 0x118 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb). 0 32 read-write DATA07 LCD Pin Data Registers 0x11C 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb). 0 32 read-write DATA10 LCD Pin Data Registers 0x200 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb). 0 32 read-write DATA11 LCD Pin Data Registers 0x204 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb). 0 32 read-write DATA12 LCD Pin Data Registers 0x208 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb). 0 32 read-write DATA13 LCD Pin Data Registers 0x20C 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb). 0 32 read-write DATA14 LCD Pin Data Registers 0x210 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb). 0 32 read-write DATA15 LCD Pin Data Registers 0x214 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb). 0 32 read-write DATA16 LCD Pin Data Registers 0x218 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb). 0 32 read-write DATA17 LCD Pin Data Registers 0x21C 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb). 0 32 read-write DATA20 LCD Pin Data Registers 0x300 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb). 0 32 read-write DATA21 LCD Pin Data Registers 0x304 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb). 0 32 read-write DATA22 LCD Pin Data Registers 0x308 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb). 0 32 read-write DATA23 LCD Pin Data Registers 0x30C 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb). 0 32 read-write DATA24 LCD Pin Data Registers 0x310 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb). 0 32 read-write DATA25 LCD Pin Data Registers 0x314 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb). 0 32 read-write DATA26 LCD Pin Data Registers 0x318 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb). 0 32 read-write DATA27 LCD Pin Data Registers 0x31C 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb). 0 32 read-write DATA30 LCD Pin Data Registers 0x400 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb). 0 32 read-write DATA31 LCD Pin Data Registers 0x404 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb). 0 32 read-write DATA32 LCD Pin Data Registers 0x408 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb). 0 32 read-write DATA33 LCD Pin Data Registers 0x40C 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb). 0 32 read-write DATA34 LCD Pin Data Registers 0x410 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb). 0 32 read-write DATA35 LCD Pin Data Registers 0x414 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb). 0 32 read-write DATA36 LCD Pin Data Registers 0x418 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb). 0 32 read-write DATA37 LCD Pin Data Registers 0x41C 32 read-write n 0x0 0x0 DATA Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb). 0 32 read-write DIVIDER LCD Divider Register 0x4 32 read-write n 0x0 0x0 DEAD_DIV Length of the dead time period in cycles. When set to zero, no dead time period exists. 16 32 read-write SUBFR_DIV Input clock frequency divide value, to generate the 1/4 sub-frame period. The sub-frame period is 4*(SUBFR_DIV+1) cycles long. 0 16 read-write ID ID and Revision 0x0 32 read-only n 0x0 0x0 ID the ID of LCD controller peripheral is 0xF0F0 0 16 read-only REVISION the version number is 0x0001 16 32 read-only PERI Peripheral Interconnect PERI 0x0 0x0 0x10000 registers n DIV_16_5_CTL0 Divider control register (for 16.5 divider) 0x400 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL1 Divider control register (for 16.5 divider) 0x404 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL10 Divider control register (for 16.5 divider) 0x428 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL11 Divider control register (for 16.5 divider) 0x42C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL12 Divider control register (for 16.5 divider) 0x430 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL13 Divider control register (for 16.5 divider) 0x434 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL14 Divider control register (for 16.5 divider) 0x438 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL15 Divider control register (for 16.5 divider) 0x43C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL16 Divider control register (for 16.5 divider) 0x440 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL17 Divider control register (for 16.5 divider) 0x444 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL18 Divider control register (for 16.5 divider) 0x448 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL19 Divider control register (for 16.5 divider) 0x44C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL2 Divider control register (for 16.5 divider) 0x408 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL20 Divider control register (for 16.5 divider) 0x450 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL21 Divider control register (for 16.5 divider) 0x454 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL22 Divider control register (for 16.5 divider) 0x458 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL23 Divider control register (for 16.5 divider) 0x45C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL24 Divider control register (for 16.5 divider) 0x460 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL25 Divider control register (for 16.5 divider) 0x464 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL26 Divider control register (for 16.5 divider) 0x468 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL27 Divider control register (for 16.5 divider) 0x46C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL28 Divider control register (for 16.5 divider) 0x470 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL29 Divider control register (for 16.5 divider) 0x474 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL3 Divider control register (for 16.5 divider) 0x40C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL30 Divider control register (for 16.5 divider) 0x478 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL31 Divider control register (for 16.5 divider) 0x47C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL32 Divider control register (for 16.5 divider) 0x480 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL33 Divider control register (for 16.5 divider) 0x484 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL34 Divider control register (for 16.5 divider) 0x488 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL35 Divider control register (for 16.5 divider) 0x48C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL36 Divider control register (for 16.5 divider) 0x490 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL37 Divider control register (for 16.5 divider) 0x494 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL38 Divider control register (for 16.5 divider) 0x498 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL39 Divider control register (for 16.5 divider) 0x49C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL4 Divider control register (for 16.5 divider) 0x410 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL40 Divider control register (for 16.5 divider) 0x4A0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL41 Divider control register (for 16.5 divider) 0x4A4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL42 Divider control register (for 16.5 divider) 0x4A8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL43 Divider control register (for 16.5 divider) 0x4AC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL44 Divider control register (for 16.5 divider) 0x4B0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL45 Divider control register (for 16.5 divider) 0x4B4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL46 Divider control register (for 16.5 divider) 0x4B8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL47 Divider control register (for 16.5 divider) 0x4BC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL48 Divider control register (for 16.5 divider) 0x4C0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL49 Divider control register (for 16.5 divider) 0x4C4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL5 Divider control register (for 16.5 divider) 0x414 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL50 Divider control register (for 16.5 divider) 0x4C8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL51 Divider control register (for 16.5 divider) 0x4CC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL52 Divider control register (for 16.5 divider) 0x4D0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL53 Divider control register (for 16.5 divider) 0x4D4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL54 Divider control register (for 16.5 divider) 0x4D8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL55 Divider control register (for 16.5 divider) 0x4DC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL56 Divider control register (for 16.5 divider) 0x4E0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL57 Divider control register (for 16.5 divider) 0x4E4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL58 Divider control register (for 16.5 divider) 0x4E8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL59 Divider control register (for 16.5 divider) 0x4EC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL6 Divider control register (for 16.5 divider) 0x418 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL60 Divider control register (for 16.5 divider) 0x4F0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL61 Divider control register (for 16.5 divider) 0x4F4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL62 Divider control register (for 16.5 divider) 0x4F8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL63 Divider control register (for 16.5 divider) 0x4FC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL7 Divider control register (for 16.5 divider) 0x41C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL8 Divider control register (for 16.5 divider) 0x420 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_5_CTL9 Divider control register (for 16.5 divider) 0x424 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL0 Divider control register (for 16.0 divider) 0x300 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL1 Divider control register (for 16.0 divider) 0x304 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL10 Divider control register (for 16.0 divider) 0x328 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL11 Divider control register (for 16.0 divider) 0x32C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL12 Divider control register (for 16.0 divider) 0x330 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL13 Divider control register (for 16.0 divider) 0x334 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL14 Divider control register (for 16.0 divider) 0x338 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL15 Divider control register (for 16.0 divider) 0x33C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL16 Divider control register (for 16.0 divider) 0x340 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL17 Divider control register (for 16.0 divider) 0x344 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL18 Divider control register (for 16.0 divider) 0x348 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL19 Divider control register (for 16.0 divider) 0x34C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL2 Divider control register (for 16.0 divider) 0x308 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL20 Divider control register (for 16.0 divider) 0x350 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL21 Divider control register (for 16.0 divider) 0x354 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL22 Divider control register (for 16.0 divider) 0x358 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL23 Divider control register (for 16.0 divider) 0x35C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL24 Divider control register (for 16.0 divider) 0x360 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL25 Divider control register (for 16.0 divider) 0x364 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL26 Divider control register (for 16.0 divider) 0x368 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL27 Divider control register (for 16.0 divider) 0x36C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL28 Divider control register (for 16.0 divider) 0x370 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL29 Divider control register (for 16.0 divider) 0x374 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL3 Divider control register (for 16.0 divider) 0x30C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL30 Divider control register (for 16.0 divider) 0x378 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL31 Divider control register (for 16.0 divider) 0x37C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL32 Divider control register (for 16.0 divider) 0x380 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL33 Divider control register (for 16.0 divider) 0x384 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL34 Divider control register (for 16.0 divider) 0x388 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL35 Divider control register (for 16.0 divider) 0x38C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL36 Divider control register (for 16.0 divider) 0x390 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL37 Divider control register (for 16.0 divider) 0x394 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL38 Divider control register (for 16.0 divider) 0x398 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL39 Divider control register (for 16.0 divider) 0x39C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL4 Divider control register (for 16.0 divider) 0x310 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL40 Divider control register (for 16.0 divider) 0x3A0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL41 Divider control register (for 16.0 divider) 0x3A4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL42 Divider control register (for 16.0 divider) 0x3A8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL43 Divider control register (for 16.0 divider) 0x3AC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL44 Divider control register (for 16.0 divider) 0x3B0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL45 Divider control register (for 16.0 divider) 0x3B4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL46 Divider control register (for 16.0 divider) 0x3B8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL47 Divider control register (for 16.0 divider) 0x3BC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL48 Divider control register (for 16.0 divider) 0x3C0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL49 Divider control register (for 16.0 divider) 0x3C4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL5 Divider control register (for 16.0 divider) 0x314 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL50 Divider control register (for 16.0 divider) 0x3C8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL51 Divider control register (for 16.0 divider) 0x3CC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL52 Divider control register (for 16.0 divider) 0x3D0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL53 Divider control register (for 16.0 divider) 0x3D4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL54 Divider control register (for 16.0 divider) 0x3D8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL55 Divider control register (for 16.0 divider) 0x3DC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL56 Divider control register (for 16.0 divider) 0x3E0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL57 Divider control register (for 16.0 divider) 0x3E4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL58 Divider control register (for 16.0 divider) 0x3E8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL59 Divider control register (for 16.0 divider) 0x3EC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL6 Divider control register (for 16.0 divider) 0x318 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL60 Divider control register (for 16.0 divider) 0x3F0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL61 Divider control register (for 16.0 divider) 0x3F4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL62 Divider control register (for 16.0 divider) 0x3F8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL63 Divider control register (for 16.0 divider) 0x3FC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL7 Divider control register (for 16.0 divider) 0x31C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL8 Divider control register (for 16.0 divider) 0x320 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_16_CTL9 Divider control register (for 16.0 divider) 0x324 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT16_DIV Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 24 read-write DIV_24_5_CTL0 Divider control register (for 24.5 divider) 0x500 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL1 Divider control register (for 24.5 divider) 0x504 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL10 Divider control register (for 24.5 divider) 0x528 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL11 Divider control register (for 24.5 divider) 0x52C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL12 Divider control register (for 24.5 divider) 0x530 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL13 Divider control register (for 24.5 divider) 0x534 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL14 Divider control register (for 24.5 divider) 0x538 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL15 Divider control register (for 24.5 divider) 0x53C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL16 Divider control register (for 24.5 divider) 0x540 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL17 Divider control register (for 24.5 divider) 0x544 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL18 Divider control register (for 24.5 divider) 0x548 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL19 Divider control register (for 24.5 divider) 0x54C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL2 Divider control register (for 24.5 divider) 0x508 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL20 Divider control register (for 24.5 divider) 0x550 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL21 Divider control register (for 24.5 divider) 0x554 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL22 Divider control register (for 24.5 divider) 0x558 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL23 Divider control register (for 24.5 divider) 0x55C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL24 Divider control register (for 24.5 divider) 0x560 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL25 Divider control register (for 24.5 divider) 0x564 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL26 Divider control register (for 24.5 divider) 0x568 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL27 Divider control register (for 24.5 divider) 0x56C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL28 Divider control register (for 24.5 divider) 0x570 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL29 Divider control register (for 24.5 divider) 0x574 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL3 Divider control register (for 24.5 divider) 0x50C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL30 Divider control register (for 24.5 divider) 0x578 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL31 Divider control register (for 24.5 divider) 0x57C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL32 Divider control register (for 24.5 divider) 0x580 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL33 Divider control register (for 24.5 divider) 0x584 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL34 Divider control register (for 24.5 divider) 0x588 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL35 Divider control register (for 24.5 divider) 0x58C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL36 Divider control register (for 24.5 divider) 0x590 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL37 Divider control register (for 24.5 divider) 0x594 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL38 Divider control register (for 24.5 divider) 0x598 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL39 Divider control register (for 24.5 divider) 0x59C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL4 Divider control register (for 24.5 divider) 0x510 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL40 Divider control register (for 24.5 divider) 0x5A0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL41 Divider control register (for 24.5 divider) 0x5A4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL42 Divider control register (for 24.5 divider) 0x5A8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL43 Divider control register (for 24.5 divider) 0x5AC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL44 Divider control register (for 24.5 divider) 0x5B0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL45 Divider control register (for 24.5 divider) 0x5B4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL46 Divider control register (for 24.5 divider) 0x5B8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL47 Divider control register (for 24.5 divider) 0x5BC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL48 Divider control register (for 24.5 divider) 0x5C0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL49 Divider control register (for 24.5 divider) 0x5C4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL5 Divider control register (for 24.5 divider) 0x514 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL50 Divider control register (for 24.5 divider) 0x5C8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL51 Divider control register (for 24.5 divider) 0x5CC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL52 Divider control register (for 24.5 divider) 0x5D0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL53 Divider control register (for 24.5 divider) 0x5D4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL54 Divider control register (for 24.5 divider) 0x5D8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL55 Divider control register (for 24.5 divider) 0x5DC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL56 Divider control register (for 24.5 divider) 0x5E0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL57 Divider control register (for 24.5 divider) 0x5E4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL58 Divider control register (for 24.5 divider) 0x5E8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL59 Divider control register (for 24.5 divider) 0x5EC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL6 Divider control register (for 24.5 divider) 0x518 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL60 Divider control register (for 24.5 divider) 0x5F0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL61 Divider control register (for 24.5 divider) 0x5F4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL62 Divider control register (for 24.5 divider) 0x5F8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL7 Divider control register (for 24.5 divider) 0x51C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL8 Divider control register (for 24.5 divider) 0x520 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_24_5_CTL9 Divider control register (for 24.5 divider) 0x524 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only FRAC5_DIV Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 3 8 read-write INT24_DIV Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 32 read-write DIV_8_CTL0 Divider control register (for 8.0 divider) 0x200 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL1 Divider control register (for 8.0 divider) 0x204 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL10 Divider control register (for 8.0 divider) 0x228 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL11 Divider control register (for 8.0 divider) 0x22C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL12 Divider control register (for 8.0 divider) 0x230 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL13 Divider control register (for 8.0 divider) 0x234 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL14 Divider control register (for 8.0 divider) 0x238 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL15 Divider control register (for 8.0 divider) 0x23C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL16 Divider control register (for 8.0 divider) 0x240 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL17 Divider control register (for 8.0 divider) 0x244 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL18 Divider control register (for 8.0 divider) 0x248 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL19 Divider control register (for 8.0 divider) 0x24C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL2 Divider control register (for 8.0 divider) 0x208 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL20 Divider control register (for 8.0 divider) 0x250 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL21 Divider control register (for 8.0 divider) 0x254 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL22 Divider control register (for 8.0 divider) 0x258 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL23 Divider control register (for 8.0 divider) 0x25C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL24 Divider control register (for 8.0 divider) 0x260 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL25 Divider control register (for 8.0 divider) 0x264 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL26 Divider control register (for 8.0 divider) 0x268 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL27 Divider control register (for 8.0 divider) 0x26C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL28 Divider control register (for 8.0 divider) 0x270 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL29 Divider control register (for 8.0 divider) 0x274 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL3 Divider control register (for 8.0 divider) 0x20C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL30 Divider control register (for 8.0 divider) 0x278 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL31 Divider control register (for 8.0 divider) 0x27C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL32 Divider control register (for 8.0 divider) 0x280 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL33 Divider control register (for 8.0 divider) 0x284 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL34 Divider control register (for 8.0 divider) 0x288 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL35 Divider control register (for 8.0 divider) 0x28C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL36 Divider control register (for 8.0 divider) 0x290 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL37 Divider control register (for 8.0 divider) 0x294 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL38 Divider control register (for 8.0 divider) 0x298 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL39 Divider control register (for 8.0 divider) 0x29C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL4 Divider control register (for 8.0 divider) 0x210 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL40 Divider control register (for 8.0 divider) 0x2A0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL41 Divider control register (for 8.0 divider) 0x2A4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL42 Divider control register (for 8.0 divider) 0x2A8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL43 Divider control register (for 8.0 divider) 0x2AC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL44 Divider control register (for 8.0 divider) 0x2B0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL45 Divider control register (for 8.0 divider) 0x2B4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL46 Divider control register (for 8.0 divider) 0x2B8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL47 Divider control register (for 8.0 divider) 0x2BC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL48 Divider control register (for 8.0 divider) 0x2C0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL49 Divider control register (for 8.0 divider) 0x2C4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL5 Divider control register (for 8.0 divider) 0x214 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL50 Divider control register (for 8.0 divider) 0x2C8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL51 Divider control register (for 8.0 divider) 0x2CC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL52 Divider control register (for 8.0 divider) 0x2D0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL53 Divider control register (for 8.0 divider) 0x2D4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL54 Divider control register (for 8.0 divider) 0x2D8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL55 Divider control register (for 8.0 divider) 0x2DC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL56 Divider control register (for 8.0 divider) 0x2E0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL57 Divider control register (for 8.0 divider) 0x2E4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL58 Divider control register (for 8.0 divider) 0x2E8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL59 Divider control register (for 8.0 divider) 0x2EC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL6 Divider control register (for 8.0 divider) 0x218 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL60 Divider control register (for 8.0 divider) 0x2F0 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL61 Divider control register (for 8.0 divider) 0x2F4 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL62 Divider control register (for 8.0 divider) 0x2F8 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL63 Divider control register (for 8.0 divider) 0x2FC 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL7 Divider control register (for 8.0 divider) 0x21C 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL8 Divider control register (for 8.0 divider) 0x220 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_8_CTL9 Divider control register (for 8.0 divider) 0x224 32 read-write n 0x0 0x0 EN Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. 0 1 read-only INT8_DIV Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. 8 16 read-write DIV_CMD Divider command register 0x0 32 read-write n 0x0 0x0 DISABLE Clock divider disable command (mutually exlusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. The SEL_DIV and SEL_TYPE fields specify which divider is to be disabled. The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately. 30 31 read-write ENABLE Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: 0: Disable the divider using the DIV_CMD.DISABLE field. 1: Configure the divider's DIV_XXX_CTL register. 2: Enable the divider using the DIV_CMD_ENABLE field. The SEL_DIV and SEL_TYPE fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_hf' (typical usage) or to ANY enabled divider. The PA_SEL_DIV and P_SEL_TYPE fields specify the reference divider. The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_hf'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_hf' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process. 31 32 read-write PA_SEL_DIV (PA_SEL_TYPE, PA_SEL_DIV) pecifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. If PA_SEL_DIV is '63' and 'PA_SEL_TYPE' is '3', 'clk_hf' is used as reference. 8 14 read-write PA_SEL_TYPE Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 14 16 read-write SEL_DIV (SEL_TYPE, SEL_DIV) specifies the divider on which the command (DISABLE/ENABLE) is performed. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock signal(s) are generated. 0 6 read-write SEL_TYPE Specifies the divider type of the divider on which the command is performed: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL0 Programmable clock control register 0x100 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL1 Programmable clock control register 0x104 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL10 Programmable clock control register 0x128 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL11 Programmable clock control register 0x12C 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL12 Programmable clock control register 0x130 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL13 Programmable clock control register 0x134 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL14 Programmable clock control register 0x138 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL15 Programmable clock control register 0x13C 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL16 Programmable clock control register 0x140 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL17 Programmable clock control register 0x144 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL18 Programmable clock control register 0x148 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL19 Programmable clock control register 0x14C 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL2 Programmable clock control register 0x108 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL20 Programmable clock control register 0x150 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL21 Programmable clock control register 0x154 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL22 Programmable clock control register 0x158 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL23 Programmable clock control register 0x15C 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL24 Programmable clock control register 0x160 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL25 Programmable clock control register 0x164 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL26 Programmable clock control register 0x168 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL27 Programmable clock control register 0x16C 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL28 Programmable clock control register 0x170 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL29 Programmable clock control register 0x174 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL3 Programmable clock control register 0x10C 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL30 Programmable clock control register 0x178 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL31 Programmable clock control register 0x17C 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL32 Programmable clock control register 0x180 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL33 Programmable clock control register 0x184 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL34 Programmable clock control register 0x188 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL35 Programmable clock control register 0x18C 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL36 Programmable clock control register 0x190 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL37 Programmable clock control register 0x194 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL38 Programmable clock control register 0x198 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL39 Programmable clock control register 0x19C 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL4 Programmable clock control register 0x110 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL40 Programmable clock control register 0x1A0 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL41 Programmable clock control register 0x1A4 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL42 Programmable clock control register 0x1A8 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL43 Programmable clock control register 0x1AC 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL44 Programmable clock control register 0x1B0 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL45 Programmable clock control register 0x1B4 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL46 Programmable clock control register 0x1B8 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL47 Programmable clock control register 0x1BC 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL48 Programmable clock control register 0x1C0 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL49 Programmable clock control register 0x1C4 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL5 Programmable clock control register 0x114 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL50 Programmable clock control register 0x1C8 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL51 Programmable clock control register 0x1CC 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL52 Programmable clock control register 0x1D0 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL53 Programmable clock control register 0x1D4 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL54 Programmable clock control register 0x1D8 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL55 Programmable clock control register 0x1DC 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL56 Programmable clock control register 0x1E0 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL57 Programmable clock control register 0x1E4 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL58 Programmable clock control register 0x1E8 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL59 Programmable clock control register 0x1EC 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL6 Programmable clock control register 0x118 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL60 Programmable clock control register 0x1F0 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL61 Programmable clock control register 0x1F4 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL62 Programmable clock control register 0x1F8 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL63 Programmable clock control register 0x1FC 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL7 Programmable clock control register 0x11C 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL8 Programmable clock control register 0x120 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write PCLK_CTL9 Programmable clock control register 0x124 32 read-write n 0x0 0x0 SEL_DIV Specifies one of the dividers of the divider type specified by SEL_TYPE. If SEL_DIV is '63' and 'SEL_TYPE' is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out of phase dividers, spurious clock control signals may be generated for one 'clk_hf' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (SEL_DIV is '63' and 'SEL_TYPE' is '3') for a transition time that is larger than the smaller of the two divider periods. 0 6 read-write SEL_TYPE Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. 6 8 read-write TR_CTL Trigger control register 0x600 32 read-write n 0x0 0x0 TR_ACT SW sets this field to '1' by to activate (set to '1') a trigger as identified by TR_SEL and TR_OUT for TR_COUNT cycles. HW sets this field to '0' when the cycle counter is decremented to '0'. Note: a TR_COUNT value of 255 is a special case and trigger activation is under direct control of the TR_ACT field (the counter is not decremented). 31 32 read-write TR_COUNT Amount of cycles a specific trigger is activated. During activation (TR_ACT is '1'), HW decrements this field to '0' using a cycle counter. During activation, SW should not modify this register field. A value of 255 is a special case: HW does NOT decrement this field to '0' and trigger activation is under direct control of TR_ACT: when TR_ACT is '1' the trigger is activated and when TR_ACT is '0' the trigger is deactivated. 16 24 read-write TR_GROUP Specifies the trigger group. 8 12 read-write TR_OUT Specifies whether trigger activation is for a specific input or ouput trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only. '0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer. '1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer. 30 31 read-write TR_SEL Specifies the activated trigger when TR_ACT is '1'. TR_OUT specifies whether the activated trigger is an input trigger or output trigger to the trigger multiplexer. During activation (TR_ACT is '1'), SW should not modify this register field. If the specified trigger is not present, the trigger activation has no effect. 0 7 read-write TR_OUT_CTL0 Trigger control register 0x0 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL1 Trigger control register 0x4 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL10 Trigger control register 0x28 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL100 Trigger control register 0x190 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL101 Trigger control register 0x194 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL102 Trigger control register 0x198 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL103 Trigger control register 0x19C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL104 Trigger control register 0x1A0 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL105 Trigger control register 0x1A4 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL106 Trigger control register 0x1A8 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL107 Trigger control register 0x1AC 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL108 Trigger control register 0x1B0 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL109 Trigger control register 0x1B4 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL11 Trigger control register 0x2C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL110 Trigger control register 0x1B8 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL111 Trigger control register 0x1BC 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL112 Trigger control register 0x1C0 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL113 Trigger control register 0x1C4 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL114 Trigger control register 0x1C8 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL115 Trigger control register 0x1CC 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL116 Trigger control register 0x1D0 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL117 Trigger control register 0x1D4 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL118 Trigger control register 0x1D8 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL119 Trigger control register 0x1DC 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL12 Trigger control register 0x30 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL120 Trigger control register 0x1E0 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL121 Trigger control register 0x1E4 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL122 Trigger control register 0x1E8 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL123 Trigger control register 0x1EC 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL124 Trigger control register 0x1F0 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL125 Trigger control register 0x1F4 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL126 Trigger control register 0x1F8 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL127 Trigger control register 0x1FC 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL13 Trigger control register 0x34 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL14 Trigger control register 0x38 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL15 Trigger control register 0x3C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL16 Trigger control register 0x40 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL17 Trigger control register 0x44 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL18 Trigger control register 0x48 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL19 Trigger control register 0x4C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL2 Trigger control register 0x8 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL20 Trigger control register 0x50 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL21 Trigger control register 0x54 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL22 Trigger control register 0x58 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL23 Trigger control register 0x5C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL24 Trigger control register 0x60 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL25 Trigger control register 0x64 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL26 Trigger control register 0x68 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL27 Trigger control register 0x6C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL28 Trigger control register 0x70 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL29 Trigger control register 0x74 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL3 Trigger control register 0xC 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL30 Trigger control register 0x78 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL31 Trigger control register 0x7C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL32 Trigger control register 0x80 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL33 Trigger control register 0x84 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL34 Trigger control register 0x88 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL35 Trigger control register 0x8C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL36 Trigger control register 0x90 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL37 Trigger control register 0x94 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL38 Trigger control register 0x98 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL39 Trigger control register 0x9C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL4 Trigger control register 0x10 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL40 Trigger control register 0xA0 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL41 Trigger control register 0xA4 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL42 Trigger control register 0xA8 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL43 Trigger control register 0xAC 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL44 Trigger control register 0xB0 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL45 Trigger control register 0xB4 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL46 Trigger control register 0xB8 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL47 Trigger control register 0xBC 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL48 Trigger control register 0xC0 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL49 Trigger control register 0xC4 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL5 Trigger control register 0x14 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL50 Trigger control register 0xC8 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL51 Trigger control register 0xCC 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL52 Trigger control register 0xD0 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL53 Trigger control register 0xD4 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL54 Trigger control register 0xD8 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL55 Trigger control register 0xDC 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL56 Trigger control register 0xE0 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL57 Trigger control register 0xE4 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL58 Trigger control register 0xE8 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL59 Trigger control register 0xEC 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL6 Trigger control register 0x18 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL60 Trigger control register 0xF0 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL61 Trigger control register 0xF4 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL62 Trigger control register 0xF8 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL63 Trigger control register 0xFC 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL64 Trigger control register 0x100 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL65 Trigger control register 0x104 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL66 Trigger control register 0x108 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL67 Trigger control register 0x10C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL68 Trigger control register 0x110 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL69 Trigger control register 0x114 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL7 Trigger control register 0x1C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL70 Trigger control register 0x118 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL71 Trigger control register 0x11C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL72 Trigger control register 0x120 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL73 Trigger control register 0x124 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL74 Trigger control register 0x128 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL75 Trigger control register 0x12C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL76 Trigger control register 0x130 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL77 Trigger control register 0x134 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL78 Trigger control register 0x138 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL79 Trigger control register 0x13C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL8 Trigger control register 0x20 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL80 Trigger control register 0x140 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL81 Trigger control register 0x144 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL82 Trigger control register 0x148 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL83 Trigger control register 0x14C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL84 Trigger control register 0x150 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL85 Trigger control register 0x154 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL86 Trigger control register 0x158 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL87 Trigger control register 0x15C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL88 Trigger control register 0x160 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL89 Trigger control register 0x164 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL9 Trigger control register 0x24 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL90 Trigger control register 0x168 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL91 Trigger control register 0x16C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL92 Trigger control register 0x170 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL93 Trigger control register 0x174 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL94 Trigger control register 0x178 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL95 Trigger control register 0x17C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL96 Trigger control register 0x180 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL97 Trigger control register 0x184 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL98 Trigger control register 0x188 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write TR_OUT_CTL99 Trigger control register 0x18C 32 read-write n 0x0 0x0 SEL Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typicallu connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. 0 7 read-write PRGIO Programmable IO configuration PRGIO 0x0 0x0 0x1000 registers n CTL Control register 0x0 32 read-write n 0x0 0x0 BYPASS Bypass of the programmable IO, one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1', this field is used. When ENABLED is '0', this field is NOT used and PRGIO is always bypassed. '0': No bypass (programmable IO fabric is exposed). '1': Bypass (programmable IO fabric is hidden). 0 8 read-write CLOCK_SRC Clock ('clk_fabric') and reset ('rst_fabric_n') source selection: '0': io_data_in[0]/'1'. ... '7': io_data_in[7]/'1'. '8': chip_data[0]/'1'. ... '15': chip_data[7]/'1'. '16': clk_prgio/rst_sys_act_n. Used for both Active functionality synchronous logic on 'clk_prgio'. This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_prgio_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. '17': clk_prgio/rst_sys_dpslp_n. Used for both DeepSleep functionality synchronous logic on 'clk_prgio' (note that 'clk_prgio' is NOT available in DeepSleep and Hibernate power modes). This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_prgio_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. '18': clk_prgio/rst_sys_hib_n. Used for both Hibernate functionality synchronous logic on 'clk_prgio' (note that 'clk_prgio' is NOT available in DeepSleep and Hibernate power modes). This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_prgio_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'. '19': clk_lf/rst_lf_dpslp_n (note that 'clk_lf' is only available in DeepSleep power mode). This selection is intended for synchronous operation on'clk_lf'. Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to other 'clk_lf' clocked elements. '20'-'30': Clock source is constant '0'. Any of these clock sources should be selected when the IP is disabled to ensure low power consumption. '31': clk_sys/'1'. This selection is NOT intended for 'clk_sys' operation, but for asynchronous operation: three 'clk_sys' cycles after enabling the IP, the IP is fully functional (reset is de-activated). To be used for asynchronous (clockless) fabric functionality. 8 13 read-write ENABLED Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured: '0': Disabled (signals are bypassed behavior as if BYPASS is 0xFF). When disabled, the fabric (data unit and LUTs) reset is activated. If the IP is disabled: - The PIPELINE_EN register field should be set to '1', to ensure low power consumption by preventing combinatorial loops. - The CLOCK_SRC register field should be set to '20'-'30' (clock is constant '0'), to ensure low power consumption. '1': Enabled. Once enabled, it takes 3 'clk_fabric' clock cycles till the fabric reset is de-activated and the fabric becomes fully functional. This ensures that the IO pins' input synchronizer states are flushed when the fabric is fully functional. 31 32 read-write HLD_OVR IO cell hold override functionality. In DeepSleep and Hibernate power modes, the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the PRGIO is supposed to deliver DeepSleep or Hibernate output functionality on these IO pads. This field is used to control the hold override functionality from the PRGIO: '0': The HSIOM controls the IO cell hold override functionality ('hsiom_hld_ovr'). '1': The PRGIO controls the IO cel hold override functionality: - In bypass mode (ENABLED is '0' or BYPASS[i] is '1'), the HSIOM control is used. - In NON bypass mode (ENABLED is '1' and BYPASS[i] is '0'), the PRGIO sets hold override to 'pwr_hld_ovr_hib' to enable PRGIO functionality in DeepSleep and Hibernate power modes (but disables it in Stop power mode). Note that in Hibernate power mode, the PRGIO should not rely on the state of Active or DeepSleep functionality signals from the HSIOM: these signals are clamped to '0' in Hibernate' 24 25 read-write PIPELINE_EN Enable for pipeline register: '0': Disabled (register is bypassed). '1': Enabled. 25 26 read-write DATA Data register 0xF0 32 read-write n 0x0 0x0 DATA Data unit input data source. 0 8 read-write DU_CTL Data unit component control register 0xC4 32 read-write n 0x0 0x0 DU_OPC Data unit opcode specifies the data unit operation: '1': INCR '2': DECR '3': INCR_WRAP '4': DECR_WRAP '5': INCR_DECR '6': INCR_DECR_WRAP '7': ROR '8': SHR '9': AND_OR '10': SHR_MAJ3 '11': SHR_EQL. Otherwise: Undefined. 8 12 read-write DU_SIZE Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is 7, the width is 8 bits. 0 3 read-write DU_SEL Data unit component input selection 0xC0 32 read-write n 0x0 0x0 DU_DATA0_SEL Data unit input data 'data0_in' source selection: '0': Constant '0'. '1': chip_data[7:0]. '2': io_data_in[7:0]. '3': DATA.DATA MMIO register field. 24 26 read-write DU_DATA1_SEL Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL. 28 30 read-write DU_TR0_SEL Data unit input signal 'tr0_in' source selection: '0': Constant '0'. '1': Constant '1'. '2': Data unit output. '10-3': LUT 7 - 0 outputs. Otherwise: Undefined. 0 4 read-write DU_TR1_SEL Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL. 8 12 read-write DU_TR2_SEL Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL. 16 20 read-write LUT_CTL0 LUT component control register 0x40 32 read-write n 0x0 0x0 LUT LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). 0 8 read-write LUT_OPC LUT opcode specifies the LUT operation: '0': Combinatoral output, no feedback. tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. '1': Combinatorial output, feedback. tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. On clock: lut_reg <= tr_in2. '2': Sequential output, no feedback. temp = LUT[{tr2_in, tr1_in, tr0_in}]. tr_out = lut_reg. On clock: lut_reg <= temp. '3': Register with asynchronous set and reset. tr_out = lut_reg. enable = (tr2_in ^ LUT[4]) | LUT[5]. set = enable and (tr1_in ^ LUT[2]) and LUT[3]. clr = enable and (tr0_in ^ LUT[0]) and LUT[1]. Asynchronously (no clock required): lut_reg <= if (clr) '0' else if (set) '1' 8 10 read-write LUT_CTL1 LUT component control register 0x44 32 read-write n 0x0 0x0 LUT LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). 0 8 read-write LUT_OPC LUT opcode specifies the LUT operation: '0': Combinatoral output, no feedback. tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. '1': Combinatorial output, feedback. tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. On clock: lut_reg <= tr_in2. '2': Sequential output, no feedback. temp = LUT[{tr2_in, tr1_in, tr0_in}]. tr_out = lut_reg. On clock: lut_reg <= temp. '3': Register with asynchronous set and reset. tr_out = lut_reg. enable = (tr2_in ^ LUT[4]) | LUT[5]. set = enable and (tr1_in ^ LUT[2]) and LUT[3]. clr = enable and (tr0_in ^ LUT[0]) and LUT[1]. Asynchronously (no clock required): lut_reg <= if (clr) '0' else if (set) '1' 8 10 read-write LUT_CTL2 LUT component control register 0x48 32 read-write n 0x0 0x0 LUT LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). 0 8 read-write LUT_OPC LUT opcode specifies the LUT operation: '0': Combinatoral output, no feedback. tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. '1': Combinatorial output, feedback. tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. On clock: lut_reg <= tr_in2. '2': Sequential output, no feedback. temp = LUT[{tr2_in, tr1_in, tr0_in}]. tr_out = lut_reg. On clock: lut_reg <= temp. '3': Register with asynchronous set and reset. tr_out = lut_reg. enable = (tr2_in ^ LUT[4]) | LUT[5]. set = enable and (tr1_in ^ LUT[2]) and LUT[3]. clr = enable and (tr0_in ^ LUT[0]) and LUT[1]. Asynchronously (no clock required): lut_reg <= if (clr) '0' else if (set) '1' 8 10 read-write LUT_CTL3 LUT component control register 0x4C 32 read-write n 0x0 0x0 LUT LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). 0 8 read-write LUT_OPC LUT opcode specifies the LUT operation: '0': Combinatoral output, no feedback. tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. '1': Combinatorial output, feedback. tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. On clock: lut_reg <= tr_in2. '2': Sequential output, no feedback. temp = LUT[{tr2_in, tr1_in, tr0_in}]. tr_out = lut_reg. On clock: lut_reg <= temp. '3': Register with asynchronous set and reset. tr_out = lut_reg. enable = (tr2_in ^ LUT[4]) | LUT[5]. set = enable and (tr1_in ^ LUT[2]) and LUT[3]. clr = enable and (tr0_in ^ LUT[0]) and LUT[1]. Asynchronously (no clock required): lut_reg <= if (clr) '0' else if (set) '1' 8 10 read-write LUT_CTL4 LUT component control register 0x50 32 read-write n 0x0 0x0 LUT LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). 0 8 read-write LUT_OPC LUT opcode specifies the LUT operation: '0': Combinatoral output, no feedback. tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. '1': Combinatorial output, feedback. tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. On clock: lut_reg <= tr_in2. '2': Sequential output, no feedback. temp = LUT[{tr2_in, tr1_in, tr0_in}]. tr_out = lut_reg. On clock: lut_reg <= temp. '3': Register with asynchronous set and reset. tr_out = lut_reg. enable = (tr2_in ^ LUT[4]) | LUT[5]. set = enable and (tr1_in ^ LUT[2]) and LUT[3]. clr = enable and (tr0_in ^ LUT[0]) and LUT[1]. Asynchronously (no clock required): lut_reg <= if (clr) '0' else if (set) '1' 8 10 read-write LUT_CTL5 LUT component control register 0x54 32 read-write n 0x0 0x0 LUT LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). 0 8 read-write LUT_OPC LUT opcode specifies the LUT operation: '0': Combinatoral output, no feedback. tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. '1': Combinatorial output, feedback. tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. On clock: lut_reg <= tr_in2. '2': Sequential output, no feedback. temp = LUT[{tr2_in, tr1_in, tr0_in}]. tr_out = lut_reg. On clock: lut_reg <= temp. '3': Register with asynchronous set and reset. tr_out = lut_reg. enable = (tr2_in ^ LUT[4]) | LUT[5]. set = enable and (tr1_in ^ LUT[2]) and LUT[3]. clr = enable and (tr0_in ^ LUT[0]) and LUT[1]. Asynchronously (no clock required): lut_reg <= if (clr) '0' else if (set) '1' 8 10 read-write LUT_CTL6 LUT component control register 0x58 32 read-write n 0x0 0x0 LUT LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). 0 8 read-write LUT_OPC LUT opcode specifies the LUT operation: '0': Combinatoral output, no feedback. tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. '1': Combinatorial output, feedback. tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. On clock: lut_reg <= tr_in2. '2': Sequential output, no feedback. temp = LUT[{tr2_in, tr1_in, tr0_in}]. tr_out = lut_reg. On clock: lut_reg <= temp. '3': Register with asynchronous set and reset. tr_out = lut_reg. enable = (tr2_in ^ LUT[4]) | LUT[5]. set = enable and (tr1_in ^ LUT[2]) and LUT[3]. clr = enable and (tr0_in ^ LUT[0]) and LUT[1]. Asynchronously (no clock required): lut_reg <= if (clr) '0' else if (set) '1' 8 10 read-write LUT_CTL7 LUT component control register 0x5C 32 read-write n 0x0 0x0 LUT LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg). 0 8 read-write LUT_OPC LUT opcode specifies the LUT operation: '0': Combinatoral output, no feedback. tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. '1': Combinatorial output, feedback. tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. On clock: lut_reg <= tr_in2. '2': Sequential output, no feedback. temp = LUT[{tr2_in, tr1_in, tr0_in}]. tr_out = lut_reg. On clock: lut_reg <= temp. '3': Register with asynchronous set and reset. tr_out = lut_reg. enable = (tr2_in ^ LUT[4]) | LUT[5]. set = enable and (tr1_in ^ LUT[2]) and LUT[3]. clr = enable and (tr0_in ^ LUT[0]) and LUT[1]. Asynchronously (no clock required): lut_reg <= if (clr) '0' else if (set) '1' 8 10 read-write LUT_SEL0 LUT component input selection 0x20 32 read-write n 0x0 0x0 LUT_TR0_SEL LUT input signal 'tr0_in' source selection: '0': Data unit output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3) chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3) chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3) chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3) chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3) io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3) io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3) io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3) io_data_in[7] (for LUTs 4, 5, 6, 7). 0 4 read-write LUT_TR1_SEL LUT input signal 'tr1_in' source selection: '0': LUT 0 output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3) chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3) chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3) chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3) chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3) io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3) io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3) io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3) io_data_in[7] (for LUTs 4, 5, 6, 7). 8 12 read-write LUT_TR2_SEL LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. 16 20 read-write LUT_SEL1 LUT component input selection 0x24 32 read-write n 0x0 0x0 LUT_TR0_SEL LUT input signal 'tr0_in' source selection: '0': Data unit output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3) chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3) chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3) chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3) chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3) io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3) io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3) io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3) io_data_in[7] (for LUTs 4, 5, 6, 7). 0 4 read-write LUT_TR1_SEL LUT input signal 'tr1_in' source selection: '0': LUT 0 output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3) chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3) chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3) chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3) chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3) io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3) io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3) io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3) io_data_in[7] (for LUTs 4, 5, 6, 7). 8 12 read-write LUT_TR2_SEL LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. 16 20 read-write LUT_SEL2 LUT component input selection 0x28 32 read-write n 0x0 0x0 LUT_TR0_SEL LUT input signal 'tr0_in' source selection: '0': Data unit output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3) chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3) chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3) chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3) chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3) io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3) io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3) io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3) io_data_in[7] (for LUTs 4, 5, 6, 7). 0 4 read-write LUT_TR1_SEL LUT input signal 'tr1_in' source selection: '0': LUT 0 output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3) chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3) chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3) chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3) chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3) io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3) io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3) io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3) io_data_in[7] (for LUTs 4, 5, 6, 7). 8 12 read-write LUT_TR2_SEL LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. 16 20 read-write LUT_SEL3 LUT component input selection 0x2C 32 read-write n 0x0 0x0 LUT_TR0_SEL LUT input signal 'tr0_in' source selection: '0': Data unit output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3) chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3) chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3) chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3) chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3) io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3) io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3) io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3) io_data_in[7] (for LUTs 4, 5, 6, 7). 0 4 read-write LUT_TR1_SEL LUT input signal 'tr1_in' source selection: '0': LUT 0 output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3) chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3) chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3) chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3) chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3) io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3) io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3) io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3) io_data_in[7] (for LUTs 4, 5, 6, 7). 8 12 read-write LUT_TR2_SEL LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. 16 20 read-write LUT_SEL4 LUT component input selection 0x30 32 read-write n 0x0 0x0 LUT_TR0_SEL LUT input signal 'tr0_in' source selection: '0': Data unit output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3) chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3) chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3) chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3) chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3) io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3) io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3) io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3) io_data_in[7] (for LUTs 4, 5, 6, 7). 0 4 read-write LUT_TR1_SEL LUT input signal 'tr1_in' source selection: '0': LUT 0 output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3) chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3) chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3) chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3) chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3) io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3) io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3) io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3) io_data_in[7] (for LUTs 4, 5, 6, 7). 8 12 read-write LUT_TR2_SEL LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. 16 20 read-write LUT_SEL5 LUT component input selection 0x34 32 read-write n 0x0 0x0 LUT_TR0_SEL LUT input signal 'tr0_in' source selection: '0': Data unit output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3) chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3) chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3) chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3) chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3) io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3) io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3) io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3) io_data_in[7] (for LUTs 4, 5, 6, 7). 0 4 read-write LUT_TR1_SEL LUT input signal 'tr1_in' source selection: '0': LUT 0 output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3) chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3) chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3) chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3) chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3) io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3) io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3) io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3) io_data_in[7] (for LUTs 4, 5, 6, 7). 8 12 read-write LUT_TR2_SEL LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. 16 20 read-write LUT_SEL6 LUT component input selection 0x38 32 read-write n 0x0 0x0 LUT_TR0_SEL LUT input signal 'tr0_in' source selection: '0': Data unit output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3) chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3) chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3) chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3) chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3) io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3) io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3) io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3) io_data_in[7] (for LUTs 4, 5, 6, 7). 0 4 read-write LUT_TR1_SEL LUT input signal 'tr1_in' source selection: '0': LUT 0 output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3) chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3) chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3) chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3) chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3) io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3) io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3) io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3) io_data_in[7] (for LUTs 4, 5, 6, 7). 8 12 read-write LUT_TR2_SEL LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. 16 20 read-write LUT_SEL7 LUT component input selection 0x3C 32 read-write n 0x0 0x0 LUT_TR0_SEL LUT input signal 'tr0_in' source selection: '0': Data unit output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3) chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3) chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3) chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3) chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3) io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3) io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3) io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3) io_data_in[7] (for LUTs 4, 5, 6, 7). 0 4 read-write LUT_TR1_SEL LUT input signal 'tr1_in' source selection: '0': LUT 0 output. '1': LUT 1 output. '2': LUT 2 output. '3': LUT 3 output. '4': LUT 4 output. '5': LUT 5 output. '6': LUT 6 output. '7': LUT 7 output. '8': chip_data[0] (for LUTs 0, 1, 2, 3) chip_data[4] (for LUTs 4, 5, 6, 7). '9': chip_data[1] (for LUTs 0, 1, 2, 3) chip_data[5] (for LUTs 4, 5, 6, 7). '10': chip_data[2] (for LUTs 0, 1, 2, 3) chip_data[6] (for LUTs 4, 5, 6, 7). '11': chip_data[3] (for LUTs 0, 1, 2, 3) chip_data[7] (for LUTs 4, 5, 6, 7). '12': io_data_in[0] (for LUTs 0, 1, 2, 3) io_data_in[4] (for LUTs 4, 5, 6, 7). '13': io_data_in[1] (for LUTs 0, 1, 2, 3) io_data_in[5] (for LUTs 4, 5, 6, 7). '14': io_data_in[2] (for LUTs 0, 1, 2, 3) io_data_in[6] (for LUTs 4, 5, 6, 7). '15': io_data_in[3] (for LUTs 0, 1, 2, 3) io_data_in[7] (for LUTs 4, 5, 6, 7). 8 12 read-write LUT_TR2_SEL LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL. 16 20 read-write SYNC_CTL Synchronization control register 0x10 32 read-write n 0x0 0x0 CHIP_SYNC_EN Synchronization of the chip input signals to 'clk_fabric', one bit for each input: CHIP_SYNC_EN[i] is for input i. '0': No synchronization. '1': Synchronization. 8 16 read-write IO_SYNC_EN Synchronization of the IO pin input signals to 'clk_fabric', one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i. '0': No synchronization. '1': Synchronization. 0 8 read-write SPCIF Flash Control Interface SPCIF 0x0 0x0 0x10000 registers n GEOMETRY Flash/NVL geometry information 0x0 32 read-write n 0x0 0x0 DE_CPD_LP 0': SRAM busy wait loop has not been copied. '1': Busy wait loop has been written into SRAM. 31 32 read-write FLASH Regular flash capacity in 256 Byte multiples (chip dependent). If multiple flash macros are present, this field provides the flash capacity of all flash macros together: '0': 256 Bytes. '1': 2*256 Bytes. ... '16383': 16384*256 Bytes. 0 14 read-only FLASH_ROW Page size in 64 Byte multiples (chip dependent): '0': 64 byte '1': 128 byte '2': 192 byte '3': 256 byte The page size is used to detemine the number of Bytes in a page for Flash page based operations (e.g. PGM_PAGE). Note: the field name FLASH_ROW is misleading, as this field specifies the number of Bytes in a page, rather than the number of Bytes in a row. In a single plane flash macro architecture, a page consists of a single row. However, in a multi plane flash macro architecture, a page consists of multiple rows from different planes. 22 24 read-only NUM_FLASH Number of flash macros (chip dependent): '0': 1 flash macro '1': 2 flash macros '2': 3 flash macros '3': 4 flash macros 20 22 read-only NVL NVLatch size in Byte multiples (chip dependent): '0': 0 Bytes '1': 1 Byte ... '127': 127 Bytes 24 31 read-only SFLASH Supervisory flash capacity in 256 Byte multiples (chip dependent). If multiple flash macros are present, this field provides the supervisory flash capacity of all flash macros together: '0': 256 Bytes. '1': 2*256 Bytes. ... '63': 64*256 Bytes. 14 20 read-only INTR SPCIF interrupt request register 0x7F0 32 read-write n 0x0 0x0 TIMER Timer counter value reaches '0'. Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit. 0 1 read-write INTR_MASK SPCIF interrupt mask register 0x7F8 32 read-write n 0x0 0x0 TIMER Mask for corresponding field in INTR register. 0 1 read-write INTR_MASKED SPCIF interrupt masked request register 0x7FC 32 read-only n 0x0 0x0 TIMER Logical and of corresponding request and mask fields. 0 1 read-only INTR_SET SPCIF interrupt set request register 0x7F4 32 read-write n 0x0 0x0 TIMER Write INTR_SET field with '1' to set corresponding INTR field. 0 1 read-write NVL_WR_DATA NVL write data register 0x1C 32 read-write n 0x0 0x0 DATA Data to be written to NVLatch array 0 8 read-write SRSSLT System Resources Lite Subsystem SRSSLT 0x0 0x0 0x10000 registers n CLK_DFT_SELECT Clock DFT Mode Selection Register 0x34 32 read-write n 0x0 0x0 DFT_DIV0 DFT Output Divide Down. 4 6 read-write NO_DIV Direct Output 0 DIV_BY_2 Divide by 2 1 DIV_BY_4 Divide by 4 2 DIV_BY_8 Divide by 8 3 DFT_DIV1 DFT Output Divide Down. 12 14 read-write NO_DIV Direct Output 0 DIV_BY_2 Divide by 2 1 DIV_BY_4 Divide by 4 2 DIV_BY_8 Divide by 8 3 DFT_EDGE0 Edge sensitivity for in-line divider on output #0 (only relevant when DIV0>0). 6 7 read-write POSEDGE Use posedge for divider 0 NEGEDGE Use negedge for divider 1 DFT_EDGE1 Edge sensitivity for in-line divider on output #1 (only relevant when DIV1>0). 14 15 read-write POSEDGE Use posedge for divider 0 NEGEDGE Use negedge for divider 1 DFT_SEL0 Select signal for DFT output #0 0 4 read-write NC Disabled - output is 0 0 ILO clk_ilo: ILO output 1 IMO clk_imo: IMO primary output 2 ECO clk_eco: ECO output 3 EXTCLK clk_ext: external clock input 4 HFCLK clk_hf: root of the high-speed clock tree 5 LFCLK clk_lf: root of the low-speed clock tree 6 SYSCLK clk_sys: root of the CPU/AHB clock tree (gated version of clk_hf) 7 PUMPCLK clk_pump: clock provided to charge pumps in FLASH and PA 8 SLPCTRLCLK clk_slpctrl: clock provided to SleepController 9 DFT_SEL1 Select signal for DFT output #1 8 12 read-write NC Disabled - output is 0 0 ILO clk_ilo: ILO output 1 IMO clk_imo: IMO primary output 2 ECO clk_eco: ECO output 3 EXTCLK clk_ext: external clock input 4 HFCLK clk_hf: root of the high-speed clock tree 5 LFCLK clk_lf: root of the low-speed clock tree 6 SYSCLK clk_sys: root of the CPU/AHB clock tree (gated version of clk_hf) 7 PUMPCLK clk_pump: clock provided to charge pumps in FLASH and PA 8 SLPCTRLCLK clk_slpctrl: clock provided to SleepController 9 CLK_ILO_CONFIG ILO Configuration 0x2C 32 read-write n 0x0 0x0 ENABLE Master enable for ILO oscillator. This bit is hardware set whenever the WD_DISABLE_KEY is not set to the magic value. 31 32 read-write CLK_IMO_CONFIG IMO Configuration 0x30 32 read-write n 0x0 0x0 ENABLE Master enable for IMO oscillator. Clearing this bit will disable the IMO. Don't do this if the system is running off it. 31 32 read-write CLK_IMO_SELECT IMO Frequency Select Register 0xF08 32 read-write n 0x0 0x0 FREQ Select operating frequency 0 3 read-write 24_MHZ IMO runs at 24 MHz 0 28_MHZ IMO runs at 28 MHz 1 32_MHZ IMO runs at 32 MHz 2 36_MHZ IMO runs at 36 MHz 3 40_MHZ IMO runs at 40 MHz 4 44_MHZ IMO runs at 44 MHz 5 48_MHZ IMO runs at 48 MHz 6 CLK_IMO_TRIM1 IMO Trim Register 0xF0C 32 read-write n 0x0 0x0 OFFSET Frequency trim bits. These bits are determined at manufacturing time for each FREQ setting (IMO_TRIM2) and stored in SFLASH. This field is hardware updated during USB osclock mode. This field is mapped to the most significant bits of the IMO trim imo_clk_trim[10:3]. The step size of 1 LSB on this field is approximately 120 kHz. 0 8 read-write CLK_IMO_TRIM2 IMO Trim Register 0xF10 32 read-write n 0x0 0x0 FSOFFSET Frequency trim bits. These bits are not trimmed during manufacturing and kept at 0 under normal operation. This field is hardware updated during USB osclock mode. This field is mapped to the least significant bits of the IMO trim imo_clk_trim[2:0]. The step size of 1 LSB on this field is approximately 15 kHz. 0 3 read-write CLK_IMO_TRIM3 IMO Trim Register 0xF18 32 read-write n 0x0 0x0 STEPSIZE IMO trim stepsize bits. These bits are determined at manufacturing time to adjust for process variation. They are used to tune the stepsize of the FSOFFSET and OFFSET trims. 0 5 read-write TCTRIM IMO temperature compesation trim. These bits are determined at manufacturing time to adjust for temperature dependence. This bits are dependent on frequency and need to be changed using the Cypress provided frequency change algorithm. 5 7 read-write CLK_SELECT Clock Select Register 0x28 32 read-write n 0x0 0x0 HFCLK_DIV Selects clk_hf predivider value. 2 4 read-write NO_DIV Transparent mode, feed through selected clock source w/o dividing. 0 DIV_BY_2 Divide selected clock source by 2 1 DIV_BY_4 Divide selected clock source by 4 2 DIV_BY_8 Divide selected clock source by 8 3 HFCLK_SEL Selects a source for clk_hf and dsi_in[0]. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. 0 2 read-write IMO IMO - Internal R/C Oscillator 0 EXTCLK EXTCLK - External Clock Pin 1 ECO ECO - External-Crystal Oscillator or PLL subsystem output 2 PUMP_SEL Selects clock source for charge pump clock. This clock is not guaranteed to be glitch free when changing any of its sources or settings. 4 6 read-write GND No clock, connect to gnd 0 IMO Use main IMO output 1 HFCLK Use clk_hf (using selected source after predivider but before prescaler) 2 SYSCLK_DIV Select clk_sys prescaler value. 6 8 read-write NO_DIV clk_sys= clk_hf/1 0 DIV_BY_2 clk_sys= clk_hf/2 1 DIV_BY_4 clk_sys= clk_hf/4 2 DIV_BY_8 clk_sys= clk_hf/8 3 PWR_BG_TRIM1 Bandgap Trim Register 0xF00 32 read-write n 0x0 0x0 REF_VTRIM Trims the bandgap reference voltage output. Used to trim the VBG to the voltage where its temperature curvature is minimal. Bit [5] is unused within the bandgap block. 0 6 read-write PWR_BG_TRIM2 Bandgap Trim Register 0xF04 32 read-write n 0x0 0x0 REF_ITRIM Trims the bandgap reference current output. Used to trim the IBG to the voltage where its temperature curvature is minimal. 0 6 read-write PWR_CONTROL Power Mode Control 0x0 32 read-write n 0x0 0x0 DEBUG_SESSION Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1) 4 5 read-only NO_SESSION No debug session active 0 SESSION_ACTIVE Debug session is active 1 EXT_VCCD Always write 0 except as noted below. PSoC4-S0 and Streetfighter CapSense products may set this bit if Vccd is provided externally (on Vccd pin). Setting this bit turns off the active regulator and will lead to system reset (BOD) unless both Vddd and Vccd pins are supplied externally. This register bit only resets for XRES, POR, or a detected BOD. 23 24 read-write LPM_READY Indicates whether the low power mode regulator is ready to enter DEEPSLEEP mode. 0: If DEEPSLEEP mode is requested, device will enter SLEEP mode. When low power regulators are ready, device will automatically enter the originally requested mode. 1: Normal operation. DEEPSLEEP works as described. 5 6 read-only OVER_TEMP_EN Enables the die over temperature sensor. Must be enabled when using the TEMP_HIGH interrupt. 16 17 read-write OVER_TEMP_THRESH Over-temperature threshold. 0: TEMP_HIGH condition occurs between 120C and 125C. 1: TEMP_HIGH condition occurs between 60C and 75C (used for testing). 17 18 read-write POWER_MODE Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon. 0 4 read-only RESET RESET state 0 ACTIVE ACTIVE state 1 SLEEP SLEEP state 2 DEEP_SLEEP DEEP_SLEEP state 3 SPARE Spare AHB readback bits that are hooked to PWR_PWRSYS_TRIM1.SPARE_TRIM[1:0] through spare logic equivalent to bitwise inversion. Engineering only. 18 20 read-only PWR_DDFT_SELECT Power DDFT Mode Selection Register 0xC 32 read-write n 0x0 0x0 DDFT0_SEL Select signal for power DDFT output #0 0 4 read-write WAKEUP wakeup 0 AWAKE awake 1 OVER_TEMP_EN pwr_control_over_temp_en 10 SLEEPHOLDREQ_N sleepholdreq_n 11 ADFT_BUF_EN adft_buf_en 12 ATPG_OBSERVE ATPG observe point (no functional purpose) 13 GND 1'b0 14 PWR 1'b1 15 ACT_POWER_EN act_power_en 2 ACT_POWER_UP act_power_up 3 ACT_POWER_GOOD act_power_good 4 ACT_REF_EN srss_adft_control_act_ref_en 5 ACT_COMP_EN srss_adft_control_act_comp_en 6 DPSLP_REF_EN srss_adft_control_dpslp_ref_en 7 DPSLP_REG_EN srss_adft_control_dpslp_reg_en 8 DPSLP_COMP_EN srss_adft_control_dpslp_comp_en 9 DDFT1_SEL Select signal for power DDFT output #1 4 8 read-write WAKEUP wakeup 0 AWAKE awake 1 DPSLP_POWER_UP dpslp_power_up 10 AWAKE_DELAYED awake_delayed 11 LPM_READY lpm_ready 12 SLEEPHOLDACK_N sleepholdack_n 13 GND 1'b0 14 PWR 1'b1 15 ACT_POWER_EN act_power_en 2 ACT_POWER_UP act_power_up 3 ACT_POWER_GOOD act_power_good 4 ACT_REF_VALID act_ref_valid 5 ACT_REG_VALID act_reg_valid 6 ACT_COMP_OUT act_comp_out 7 ACT_TEMP_HIGH act_temp_high 8 DPSLP_COMP_OUT dpslp_comp_out 9 PWR_KEY_DELAY Power System Key and Delay Register 0x4 32 read-write n 0x0 0x0 WAKEUP_HOLDOFF Delay to wait for references to settle on wakeup from deepsleep. BOD is ignored and system does not resume until this delay expires. Note that the same delay on POR is hard-coded. The default assumes the output of the predivider is 48MHz + 3 percent. Firmware may scale this setting according to the fastest actual clock frequency that can occur when waking from DEEPSLEEP. 0 10 read-write PWR_PWRSYS_TRIM1 Power System Trim Register 0xF14 32 read-write n 0x0 0x0 DPSLP_REF_TRIM Trims the DeepSleep reference that is used by the DeepSleep regulator and DeepSleep power comparator. 0 4 read-write SPARE_TRIM Active-Reference temperature compensation trim (repurposed from spare bits). Bits [7:6] - trim the Active-Reference IREF temperature coefficient (TC). 00: TC = 0 (unchanged) 01: TC = +80ppm/C 10: TC = -80ppm/C 11: TC = -150ppm/C Bits [5:4] - trim the Active-Reference VREF temperature coefficient (TC). 00: TC = 0 (unchanged) 01: TC = -50ppm/C 10: TC = -80ppm/C 11: TC = +150ppm/C 4 8 read-write RES_CAUSE Reset Cause Observation Register 0x54 32 read-write n 0x0 0x0 RESET_PROT_FAULT A protection violation occurred that requires a RESET. This includes, but is not limited to, hitting a debug breakpoint while in Privileged Mode. 3 4 read-write RESET_SOFT Cortex-M0 requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. 4 5 read-write RESET_WDT A WatchDog Timer reset has occurred since last power cycle. 0 1 read-write SRSS_INTR SRSS Interrupt Register 0x44 32 read-write n 0x0 0x0 TEMP_HIGH Regulator over-temp interrupt. This interrupt can occur when a short circuit exists on the vccd pin or when extreme loads are applied on IO-cells causing the die to overheat. Firmware is encourage to shutdown all IO cells and then go to DeepSleep mode when this interrupt occurs if protection against such conditions is desired. 1 2 read-write WDT_MATCH WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. Clearing this bit also feeds the watch dog. Missing 2 interrupts in a row will generate brown-out reset. Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C. 0 1 read-write SRSS_INTR_MASK SRSS Interrupt Mask Register 0x4C 32 read-write n 0x0 0x0 TEMP_HIGH Masks REG_OVERTEMP interrupt 1 2 read-write WDT_MATCH Clearing this bit will not forward the interrupt to the CPU. It will not, however, disable the WDT reset generation on 2 missed interrupts. 0 1 read-write SRSS_INTR_SET SRSS Interrupt Set Register 0x48 32 read-write n 0x0 0x0 TEMP_HIGH Writing 1 to this bit internally sets the overtemp interrupt. This can be observed by reading SRSS_INTR.TEMP_HIGH. This bit always reads back as zero. 1 2 read-write TST_MODE Test Mode Control Register 0x14 32 read-write n 0x0 0x0 BLOCK_ALT_XRES Relevant only for parts that have the alternate XRES mechanism of overloading a GPIO pin temporarily as alternate XRES during test. When set, this bit blocks the alternate XRES function, such that the pin can be used for normal I/O or for ddft/adft observation. See SAS Part-V and Part-IX for details. This register bit only resets for XRES, POR, or a detected BOD. 28 29 read-write SWD_CONNECTED 0: SWD not active 1: SWD activated (Line Reset and Connect sequence passed) (Note: this bit replaces TST_CTRL.SWD_CONNECTED and is present in all M0S8 products except TSG4) 2 3 read-only TEST_KEY_DFT_EN This bit is set when a XRES test mode key is shifted in. It is the value of the test_key_dft_en signal. When this bit is set, the BootROM will not yield execution to the FLASH image (same function as setting TEST_MODE bit below). 30 31 read-only TEST_MODE 0: Normal operation mode 1: Test mode (any test mode) Setting this bit will prevent BootROM from yielding execution to Flash image. 31 32 read-write WDT_COUNTER Watchdog Counter Register 0x3C 32 read-only n 0x0 0x0 COUNTER Current value of WDT Counter 0 16 read-only WDT_DISABLE_KEY Watchdog Disable Key Register 0x38 32 read-write n 0x0 0x0 KEY Disables WDT reset when equal to 0xACED8865. The WDT reset functions normally for any other setting. 0 32 read-write WDT_MATCH Watchdog Match Register 0x40 32 read-write n 0x0 0x0 IGNORE_BITS The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Note that certain products may enforce a minimum value for this register through design time configuration. 16 20 read-write MATCH Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match). 0 16 read-write TCPWM Timer/Counter/PWM TCPWM 0x0 0x0 0x10000 registers n CC Counter compare/capture register 0xC 32 read-write n 0x0 0x0 CC In CAPTURE mode, captures the counter value. In other modes, compared to counter value. 0 16 read-write CC_BUFF Counter buffered compare/capture register 0x10 32 read-write n 0x0 0x0 CC Additional buffer for counter CC register. 0 16 read-write CMD TCPWM command register. 0x8 32 read-write n 0x0 0x0 COUNTER_CAPTURE Counters SW capture trigger. When written with '1', a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.COUNTER_ENABLED, the field is immediately set to '0'. 0 8 read-write COUNTER_RELOAD Counters SW reload trigger. For HW behavior, see COUNTER_CAPTURE field. 8 16 read-write COUNTER_START Counters SW start trigger. For HW behavior, see COUNTER_CAPTURE field. 24 32 read-write COUNTER_STOP Counters SW stop trigger. For HW behavior, see COUNTER_CAPTURE field. 16 24 read-write COUNTER Counter count register 0x8 32 read-write n 0x0 0x0 COUNTER 16-bit counter value. It is advised to not write to this field when the counter is running. 0 16 read-write CTRL Counter control register 0x0 32 read-write n 0x0 0x0 AUTO_RELOAD_CC Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: '0': never switch. '1': switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. '1': switch on a terminal count event with an actively pending switch event. 0 1 read-write AUTO_RELOAD_PERIOD Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. '0': never switch. '1': switch on a terminal count event with and actively pending siwtch event. 1 2 read-write COUNTER_ENABLED Counter enables for counters 0 up to CNT_NR-1. '0': counter disabled. '1': counter enabled. Counter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes: - the associated counter triggers in the CMD register are set to '0'. - the counter's interrupt cause fields in counter's INTR register. - the counter's status fields in counter's STATUS register.. - the counter's trigger outputs ('tr_overflow', 'tr_underflow' and 'tr_compare_match'). - the counter's line outputs ('line_out' and 'line_compl_out'). 0 8 read-write GENERIC Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock. 8 16 read-write MODE Counter mode. 24 27 read-write TIMER Timer mode 0 CAPTURE Capture mode 2 QUAD Quadrature encoding mode 3 PWM Pulse width modulation (PWM) mode 4 PWM_DT PWM with deadtime insertion mode 5 PWM_PR Pseudo random pulse width modulation 6 ONE_SHOT When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated. 18 19 read-write PWM_STOP_ON_KILL Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only. 3 4 read-write PWM_SYNC_KILL Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. '0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET. This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'. 2 3 read-write QUADRATURE_MODE In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'. Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out' i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1]. 20 22 read-write X1 X1 encoding (QUAD mode) 0 X2 X2 encoding (QUAD mode) 1 X4 X4 encoding (QUAD mode) 2 UP_DOWN_MODE Determines counter direction. 16 18 read-write COUNT_UP Count up (to PERIOD). An overflow event is generated when the counter reaches PERIOD. A terminal count event is generated when the counter reaches PERIOD. 0 COUNT_DOWN Count down (to '0'). An underflow event is generated when the counter reaches '0'. A terminal count event is generated when the counter reaches '0'. 1 COUNT_UPDN1 Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter reaches PERIOD. An underflow event is generated when the counter reaches '0'. A terminal count event is generated when the counter reaches '0'. 2 COUNT_UPDN2 Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter reaches PERIOD. An underflow event is generated when the counter reaches '0'. A terminal count event is generated when the counter reaches '0' AND when the counter reaches PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates). 3 INTR Interrupt request register. 0x30 32 read-write n 0x0 0x0 CC_MATCH Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit. 1 2 read-write TC Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit. 0 1 read-write INTR_CAUSE TCPWM Counter interrupt cause register. 0xC 32 read-only n 0x0 0x0 COUNTER_INT Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED, the associated interrupt field is immediately set to '0'. 0 8 read-only INTR_MASK Interrupt mask register. 0x38 32 read-write n 0x0 0x0 CC_MATCH Mask bit for corresponding bit in interrupt request register. 1 2 read-write TC Mask bit for corresponding bit in interrupt request register. 0 1 read-write INTR_MASKED Interrupt masked request register 0x3C 32 read-only n 0x0 0x0 CC_MATCH Logical and of corresponding request and mask bits. 1 2 read-only TC Logical and of corresponding request and mask bits. 0 1 read-only INTR_SET Interrupt set request register. 0x34 32 read-write n 0x0 0x0 CC_MATCH Write with '1' to set corresponding bit in interrupt request register. 1 2 read-write TC Write with '1' to set corresponding bit in interrupt request register. 0 1 read-write PERIOD Counter period register 0x14 32 read-write n 0x0 0x0 PERIOD Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1. 0 16 read-write PERIOD_BUFF Counter buffered period register 0x18 32 read-write n 0x0 0x0 PERIOD Additional buffer for counter PERIOD register. 0 16 read-write STATUS Counter status register 0x4 32 read-only n 0x0 0x0 DOWN When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented. 0 1 read-only GENERIC Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality. 8 16 read-only RUNNING When '0', the counter is NOT running. When '1', the counter is running. 31 32 read-only TR_CTRL0 Counter trigger control register 0 0x20 32 read-write n 0x0 0x0 CAPTURE_SEL Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. Input trigger 2 is the first external trigger line (tcpwm.tr_in[0]). In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts. 0 4 read-write COUNT_SEL Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'. 4 8 read-write RELOAD_SEL Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with the value in the TCPWM_CNTn_PERIOD register. 8 12 read-write START_SEL Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B). 16 20 read-write STOP_SEL Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event. 12 16 read-write TR_CTRL1 Counter trigger control register 1 0x24 32 read-write n 0x0 0x0 CAPTURE_EDGE A capture event will copy the counter value into the CC register. 0 2 read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 BOTH_EDGES Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 COUNT_EDGE A counter event will increase or decrease the counter by '1'. 2 4 read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 BOTH_EDGES Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 RELOAD_EDGE A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD. 4 6 read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 BOTH_EDGES Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 START_EDGE A start event will start the counter i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does. 8 10 read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 BOTH_EDGES Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 STOP_EDGE A stop event, will stop the counter i.e. it will no longer be running. Stopping will NOT disable the counter. 6 8 read-write RISING_EDGE Rising edge. Any rising edge generates an event. 0 FALLING_EDGE Falling edge. Any falling edge generates an event. 1 BOTH_EDGES Rising AND falling edge. Any odd amount of edges generates an event. 2 NO_EDGE_DET No edge detection, use trigger as is. 3 TR_CTRL2 Counter trigger control register 2 0x28 32 read-write n 0x0 0x0 CC_MATCH_MODE Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register. 0 2 read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 OVERFLOW_MODE Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals. 2 4 read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 UNDERFLOW_MODE Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals. 4 6 read-write SET Set to '1' 0 CLEAR Set to '0' 1 INVERT Invert 2 NO_CHANGE No Change 3 WCO 32KHz Oscillator WCO 0x0 0x0 0x10000 registers n CONFIG WCO Configuration Register 0x0 32 read-write n 0x0 0x0 DPLL_ENABLE Enable DPLL operation. The Oscillator is specified to be stable after 500 ms thus the DPLL should be asserted no sooner than that after IP_ENABLE is set. 30 31 read-write ENBUS Test Mode Control bits enbus[7] - N/A enbus[6] - 1=enable both primary Beta Multipliers enbus[5] - N/A enbus[4] - N/A enbus[3] - Load Resistor Control enbus[2] - Load Resistor Control enbus[1] - Load Resistor Control enbus[0] - Load Resistor Control 16 24 read-write EXT_INPUT_EN Disables the load resistor and allows external clock input for pad_xin 2 3 read-write IP_ENABLE Master enable for IP - disables both WCO and DPLL 31 32 read-write LPM_AUTO Automatically control low power mode (only relevant when LPM_EN=0): 0: Do not enter low power mode (LPM) in DeepSleep 1: Enter low power mode (LPM) in DeepSleep. The logic monitors !act_power_en to determine the device has entered DeepSleep. 1 2 read-write LPM_EN Force block into Low Power Mode: 0: Do not force low power mode (LPM) on 1: Force low power mode (LPM) on 0 1 read-write DPLL WCO DPLL Register 0x8 32 read-write n 0x0 0x0 DPLL_LF_IGAIN DPLL Loop Filter Integral Gain Setting 0x0 - 0.0625 0x1 - 0.125 0x2 - 0.25 0x3 - 0.5 0x4 - 1.0 0x5 - 2.0 0x6 - 4.0 0x7 - 8.0 16 19 read-write DPLL_LF_LIMIT Maximum IMO offset allowed (used to prevent DPLL dynamics from selecting an IMO frequency that the logic cannot support) 22 30 read-write DPLL_LF_PGAIN DPLL Loop Filter Proportionial Gain Setting 0x0 - 0.0625 0x1 - 0.125 0x2 - 0.25 0x3 - 0.5 0x4 - 1.0 0x5 - 2.0 0x6 - 4.0 0x7 - 8.0 19 22 read-write DPLL_MULT Multiplier to determine IMO frequency in multiples of the WCO frequency Fimo = (DPLL_MULT + 1) * Fwco 0 11 read-write STATUS WCO Status Register 0x4 32 read-only n 0x0 0x0 OUT_BLNK_A Indicates that output has transitioned - This bit is intended for Test Mode Only and is not a reliable indicator. 0 1 read-only TRIM WCO Trim Register 0xF00 32 read-write n 0x0 0x0 LPM_GM GM setting for LPM (bandwidth = DC/ms) - Used when WCO.LPM_AUTO=0 or when LPM_AUTO=1 and not in DeepSleep mode. 4 6 read-write XGM Amplifier GM setting - Used when WCO.LPM_AUTO=0 or when LPM_AUTO=1 and not in DeepSleep mode. 0x0 - 3370 nA 0x1 - 2620 nA 0x2 - 2250 nA 0x3 - 1500 nA 0x4 - 1870 nA 0x5 - 1120 nA 0x6 - 750 nA 0x7 - 0 nA 0 3 read-write WDT_CLKEN Watchdog Counters Clock Enable 0x214 32 read-write n 0x0 0x0 CLK_ILO_EN_FOR_WDT Enables the ILO clock for use by the WDT logic. Wait at least 4 ILO clock cycles for a change to take effect. Must be 0 when switching WDT_CONFIG.LFCLK_SEL. Should be 0 if CLK_WCO_EN_FOR_WDT=1. 1 2 read-write CLK_WCO_EN_FOR_WDT Enables the WCO clock for use by the WDT logic. Wait at least 4 WCO clock cycles for a change to take effect. Must be 0 when switching WDT_CONFIG.LFCLK_SEL. Should be 0 if CLK_ILO_EN_FOR_WDT=1 0 1 read-write WDT_CONFIG Watchdog Counters Configuration 0x20C 32 read-write n 0x0 0x0 LFCLK_SEL N/A 30 32 read-write WDT_BITS2 Bit to observe for WDT_INT2: 0: Assert when bit0 of WDT_CTR2 toggles (one int every tick) .. 31: Assert when bit31 of WDT_CTR2 toggles (one int every 2^31 ticks) 24 29 read-write WDT_CASCADE0_1 Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0. 0: Independent counters 1: Cascaded counters 3 4 read-write WDT_CASCADE1_2 Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters. 0: Independent counters 1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1 11 12 read-write WDT_CLEAR0 Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1). 0: Free running counter 1: Clear on match 2 3 read-write WDT_CLEAR1 Clear Watchdog Counter when WDT_CTR1=WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1). 0: Free running counter 1: Clear on match 10 11 read-write WDT_MODE0 Watchdog Counter Action on Match (WDT_CTR0=WDT_MATCH0). 0 2 read-write NOTHING Do nothing 0 INT Assert WDT_INTx 1 RESET Assert WDT Reset - Not Supported - here for backwards compatibility 2 INT_THEN_RESET Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt. Not supported - here for Backwards compatibility. 3 WDT_MODE1 Watchdog Counter Action on Match (WDT_CTR1=WDT_MATCH1). 8 10 read-write NOTHING Do nothing 0 INT Assert WDT_INTx 1 RESET Assert WDT Reset - Not Supported - here for backwards compatibility 2 INT_THEN_RESET Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt - Not supported - here for backwards compatibility. 3 WDT_MODE2 Watchdog Counter 2 Mode. 16 17 read-write NOTHING Free running counter with no interrupt requests 0 INT Free running counter with interrupt request when a specified bit in CTR2 toggles (see WDT_BITS2) 1 WDT_CONTROL Watchdog Counters Control 0x210 32 read-write n 0x0 0x0 WDT_ENABLE0 Enable Counter 0 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) Note: This field takes considerable time (up to 3 LFCLK cycles) to take effect. It must not be changed more than once in that period. 0 1 read-write WDT_ENABLE1 Enable Counter 1 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) Note: This field takes considerable time (up to 3 LFCLK cycles) to take effect. It must not be changed more than once in that period. 8 9 read-write WDT_ENABLE2 Enable Counter 2 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) Note: This field takes considerable time (up to 3 LFCLK cycles) to take effect. It must not be changed more than once in that period. 16 17 read-write WDT_ENABLED0 Indicates actual state of counter. May lag WDT_ENABLE0 by up to 3 LFCLK cycles. After changing WDT_ENABLE0, do not enter DEEPSLEEP mode until this field acknowledges the change. 1 2 read-only WDT_ENABLED1 Indicates actual state of counter. May lag WDT_ENABLE1 by up to 3 LFCLK cycles. After changing WDT_ENABLE1, do not enter DEEPSLEEP mode until this field acknowledges the change. 9 10 read-only WDT_ENABLED2 Indicates actual state of counter. May lag WDT_ENABLE2 by up to 3 LFCLK cycles. After changing WDT_ENABLE2, do not enter DEEPSLEEP mode until this field acknowledges the change. 17 18 read-only WDT_INT0 WDT Interrupt Request. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODEx=3. After W1C, WDT_CONTROL must be read for the hardware to internally remove the clear flag. Failure to do this may result in missing the next interrupt. 2 3 read-write WDT_INT1 WDT Interrupt Request. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. After W1C, WDT_CONTROL must be read for the hardware to internally remove the clear flag. Failure to do this may result in missing the next interrupt. 10 11 read-write WDT_INT2 WDT Interrupt Request. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. After W1C, WDT_CONTROL must be read for the hardware to internally remove the clear flag. Failure to do this may result in missing the next interrupt. 18 19 read-write WDT_RESET0 Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take several LFCLK cycles to take effect. Wait until the reset completes before enabling the WDT. 3 4 read-write WDT_RESET1 Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take several LFCLK cycles to take effect. Wait until the reset completes before enabling the WDT. 11 12 read-write WDT_RESET2 Resets counter 2 back to 0000_0000. Hardware will reset this bit after counter was reset. This will take several LFCLK cycles to take effect. Wait until the reset completes before enabling the WDT. 19 20 read-write WDT_CTRHIGH Watchdog Counter 2 0x204 32 read-only n 0x0 0x0 WDT_CTR2 Current value of WDT Counter 2 0 32 read-only WDT_CTRLOW Watchdog Counters 0/1 0x200 32 read-only n 0x0 0x0 WDT_CTR0 Current value of WDT Counter 0 0 16 read-only WDT_CTR1 Current value of WDT Counter 1 16 32 read-only WDT_MATCH Watchdog counter match values 0x208 32 read-write n 0x0 0x0 WDT_MATCH0 Match value for Watchdog Counter 0 0 16 read-write WDT_MATCH1 Match value for Watchdog Counter 1 16 32 read-write