Infineon
psoc6_01
2024.05.04
PSoC6_01
CM4
r0p1
little
true
true
3
false
8
32
BACKUP
SRSS Backup Domain
BACKUP
0x0
0x0
0x10000
registers
n
ALM1_DATE
Alarm 1 Day of Month, Month
0x20
32
read-write
n
0x0
0x0
ALM_DATE
Alarm Day of the Month in BCD, 1-31 Leap Year corrected
0
6
read-write
ALM_DATE_EN
Alarm Day of the Month enable: 0=ignore, 1=match
7
8
read-write
ALM_EN
Master enable for alarm 1. 0: Alarm 1 is disabled. Fields for date and time are ignored. 1: Alarm 1 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second.
31
32
read-write
ALM_MON
Alarm Month in BCD, 1-12
8
13
read-write
ALM_MON_EN
Alarm Month enable: 0=ignore, 1=match
15
16
read-write
ALM1_TIME
Alarm 1 Seconds, Minute, Hours, Day of Week
0x1C
32
read-write
n
0x0
0x0
ALM_DAY
Alarm Day of the week in BCD, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended
24
27
read-write
ALM_DAY_EN
Alarm Day of the Week enable: 0=ignore, 1=match
31
32
read-write
ALM_HOUR
Alarm hours in BCD, value depending on 12/24HR mode 12HR: [5]:0=AM, 1=PM, [4:0]=1-12 24HR: [5:0]=0-23
16
22
read-write
ALM_HOUR_EN
Alarm hour enable: 0=ignore, 1=match
23
24
read-write
ALM_MIN
Alarm minutes in BCD, 0-59
8
15
read-write
ALM_MIN_EN
Alarm minutes enable: 0=ignore, 1=match
15
16
read-write
ALM_SEC
Alarm seconds in BCD, 0-59
0
7
read-write
ALM_SEC_EN
Alarm second enable: 0=ignore, 1=match
7
8
read-write
ALM2_DATE
Alarm 2 Day of Month, Month
0x28
32
read-write
n
0x0
0x0
ALM_DATE
Alarm Day of the Month in BCD, 1-31 Leap Year corrected
0
6
read-write
ALM_DATE_EN
Alarm Day of the Month enable: 0=ignore, 1=match
7
8
read-write
ALM_EN
Master enable for alarm 2. 0: Alarm 2 is disabled. Fields for date and time are ignored. 1: Alarm 2 is enabled. Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration. If none of the date and time fields are enabled, then this alarm triggers once every second.
31
32
read-write
ALM_MON
Alarm Month in BCD, 1-12
8
13
read-write
ALM_MON_EN
Alarm Month enable: 0=ignore, 1=match
15
16
read-write
ALM2_TIME
Alarm 2 Seconds, Minute, Hours, Day of Week
0x24
32
read-write
n
0x0
0x0
ALM_DAY
Alarm Day of the week in BCD, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended
24
27
read-write
ALM_DAY_EN
Alarm Day of the Week enable: 0=ignore, 1=match
31
32
read-write
ALM_HOUR
Alarm hours in BCD, value depending on 12/24HR mode 12HR: [5]:0=AM, 1=PM, [4:0]=1-12 24HR: [5:0]=0-23
16
22
read-write
ALM_HOUR_EN
Alarm hour enable: 0=ignore, 1=match
23
24
read-write
ALM_MIN
Alarm minutes in BCD, 0-59
8
15
read-write
ALM_MIN_EN
Alarm minutes enable: 0=ignore, 1=match
15
16
read-write
ALM_SEC
Alarm seconds in BCD, 0-59
0
7
read-write
ALM_SEC_EN
Alarm second enable: 0=ignore, 1=match
7
8
read-write
BREG0
Backup register region
0x1000
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG1
Backup register region
0x1004
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG10
Backup register region
0x1028
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG11
Backup register region
0x102C
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG12
Backup register region
0x1030
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG13
Backup register region
0x1034
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG14
Backup register region
0x1038
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG15
Backup register region
0x103C
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG16
Backup register region
0x1040
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG17
Backup register region
0x1044
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG18
Backup register region
0x1048
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG19
Backup register region
0x104C
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG2
Backup register region
0x1008
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG20
Backup register region
0x1050
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG21
Backup register region
0x1054
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG22
Backup register region
0x1058
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG23
Backup register region
0x105C
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG24
Backup register region
0x1060
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG25
Backup register region
0x1064
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG26
Backup register region
0x1068
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG27
Backup register region
0x106C
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG28
Backup register region
0x1070
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG29
Backup register region
0x1074
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG3
Backup register region
0x100C
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG30
Backup register region
0x1078
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG31
Backup register region
0x107C
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG32
Backup register region
0x1080
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG33
Backup register region
0x1084
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG34
Backup register region
0x1088
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG35
Backup register region
0x108C
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG36
Backup register region
0x1090
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG37
Backup register region
0x1094
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG38
Backup register region
0x1098
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG39
Backup register region
0x109C
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG4
Backup register region
0x1010
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG40
Backup register region
0x10A0
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG41
Backup register region
0x10A4
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG42
Backup register region
0x10A8
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG43
Backup register region
0x10AC
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG44
Backup register region
0x10B0
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG45
Backup register region
0x10B4
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG46
Backup register region
0x10B8
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG47
Backup register region
0x10BC
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG48
Backup register region
0x10C0
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG49
Backup register region
0x10C4
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG5
Backup register region
0x1014
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG50
Backup register region
0x10C8
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG51
Backup register region
0x10CC
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG52
Backup register region
0x10D0
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG53
Backup register region
0x10D4
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG54
Backup register region
0x10D8
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG55
Backup register region
0x10DC
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG56
Backup register region
0x10E0
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG57
Backup register region
0x10E4
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG58
Backup register region
0x10E8
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG59
Backup register region
0x10EC
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG6
Backup register region
0x1018
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG60
Backup register region
0x10F0
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG61
Backup register region
0x10F4
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG62
Backup register region
0x10F8
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG63
Backup register region
0x10FC
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG7
Backup register region
0x101C
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG8
Backup register region
0x1020
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
BREG9
Backup register region
0x1024
32
read-write
n
0x0
0x0
BREG
Backup memory that contains application-specific data. Memory is retained on vbackup supply.
0
32
read-write
CAL_CTL
Oscillator calibration for absolute frequency
0xC
32
read-write
n
0x0
0x0
CALIB_SIGN
Calibration sign: 0= Negative sign: remove pulses (it takes more clock ticks to count one second) 1= Positive sign: add pulses (it takes less clock ticks to count one second)
6
7
read-write
CALIB_VAL
Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/(60*60*32,768)). Positive values 0x01-0x3c (1..60) add pulses, negative values remove pulses, thus giving a range of +/-65.1 ppm (limited by 60 minutes per hour, not the range of this field) Calibration is performed hourly, starting at 59 minutes and 59 seconds, and applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments.
0
6
read-write
CAL_OUT
Output enable for 512Hz signal for calibration and allow CALIB_VAL to be written. Note that calibration does not affect the 512Hz output signal.
31
32
read-write
CTL
Control
0x0
32
read-write
n
0x0
0x0
CLK_SEL
Clock select for BAK clock
8
10
read-write
WCO
Watch-crystal oscillator input.
0
ALTBAK
This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is not available in all power modes, and clock glitches can propagate into the backup logic when the clock is stopped. For this reason, if the WCO is intended as the clock source then choose it directly instead of routing through LFCLK.
1
EN_CHARGE_KEY
When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY.
24
32
read-write
PRESCALER
N/A
12
14
read-write
VBACKUP_MEAS
Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC.
19
20
read-write
VDDBAK_CTL
Controls the behavior of the switch that generates vddbak from vbackup or vddd. 0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup. 1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage.
17
19
read-write
WCO_BYPASS
Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. 0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins. 1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information.
16
17
read-write
WCO_EN
Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes. After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs. Follow the procedure in BACKUP_RTC_RW to access this bit.
3
4
read-write
INTR
Interrupt request register
0x2C
32
read-write
n
0x0
0x0
ALARM1
Alarm 1 Interrupt
0
1
read-write
ALARM2
Alarm 2 Interrupt
1
2
read-write
CENTURY
Century overflow interrupt
2
3
read-write
INTR_MASK
Interrupt mask register
0x34
32
read-write
n
0x0
0x0
ALARM1
Mask bit for corresponding bit in interrupt request register.
0
1
read-write
ALARM2
Mask bit for corresponding bit in interrupt request register.
1
2
read-write
CENTURY
Mask bit for corresponding bit in interrupt request register.
2
3
read-write
INTR_MASKED
Interrupt masked request register
0x38
32
read-only
n
0x0
0x0
ALARM1
Logical and of corresponding request and mask bits.
0
1
read-only
ALARM2
Logical and of corresponding request and mask bits.
1
2
read-only
CENTURY
Logical and of corresponding request and mask bits.
2
3
read-only
INTR_SET
Interrupt set request register
0x30
32
read-write
n
0x0
0x0
ALARM1
Write with '1' to set corresponding bit in interrupt request register.
0
1
read-write
ALARM2
Write with '1' to set corresponding bit in interrupt request register.
1
2
read-write
CENTURY
Write with '1' to set corresponding bit in interrupt request register.
2
3
read-write
OSCCNT
32kHz oscillator counter
0x3C
32
read-only
n
0x0
0x0
CNT32KHZ
32kHz oscillator count (msb=128Hz), calibration can cause bit 6 to skip. Reset when RTC_TIME.RTC_SEC fields is written.
0
8
read-only
PMIC_CTL
PMIC control register
0x44
32
read-write
n
0x0
0x0
PMIC_ALWAYSEN
Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware. 0: Normal operation, PMIC_EN and PMIC_OUTEN work as described 1: PMIC_EN and PMIC_OUTEN are ignored and the output pad is forced enabled. Note: This bit is a write-once bit until the next backup reset.
30
31
read-write
PMIC_EN
Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0, the system functions normally until vddd is no longer present (OFF w/Backup mode). Firmware can set this bit, if it does so before vddd is actually removed. This bit is also set by any RTC alarm or PMIC pin wakeup event regardless of UNLOCK setting.
31
32
read-write
PMIC_EN_OUTEN
Output enable for the output driver in the PMIC_EN pad. 0: Output pad is tristate for PMIC_EN pin. This can allow this pin to be used for another purpose. Tristate condition is kept only if the UNLOCK key (0x3A) is present 1: Output pad is enabled for PMIC_EN pin.
29
30
read-write
POLARITY
N/A
16
17
read-write
UNLOCK
This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the UNLOCK code do these in separate write cycles.
8
16
read-write
RESET
Backup reset register
0x48
32
read-write
n
0x0
0x0
RESET
Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register, firmware should confirm it reads as 0 before attempting to write other backup registers.
31
32
read-write
RTC_DATE
Calendar Day of Month, Month, Year
0x18
32
read-write
n
0x0
0x0
RTC_DATE
Calendar Day of the Month in BCD, 1-31 Automatic Leap Year Correction
0
6
read-write
RTC_MON
Calendar Month in BCD, 1-12
8
13
read-write
RTC_YEAR
Calendar year in BCD, 0-99
16
24
read-write
RTC_RW
RTC Read Write register
0x8
32
read-write
n
0x0
0x0
READ
Read bit When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be read. The RTC will keep on running. Do not set the read bit if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Write bit is set. Do not set the Read bit at the same time that the Write bit is cleared.
0
1
read-write
WRITE
Write bit Only when this bit is set can the RTC registers be written to (otherwise writes are ignored). This bit cannot be set if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Read bit is set or getting set. The user writes to the RTC user registers, when the Write bit is cleared by the user then the user registers content is copied to the actual RTC registers. Only user RTC registers that were written to will get copied, others will not be affected. When the SECONDS field is updated then TICKS will also be reset (WDT is not affected). When the Write bit is cleared by a reset (brown out/DeepSleep) then the RTC update will be ignored/lost. Do not set the Write bit if the RTC if the RTC is still busy with a previous update (see RTC_BUSY). Do not set the Write bit at the same time that the Read bit is cleared.
1
2
read-write
RTC_TIME
Calendar Seconds, Minutes, Hours, Day of Week
0x14
32
read-write
n
0x0
0x0
CTRL_12HR
Select 12/24HR mode: 1=12HR, 0=24HR
22
23
read-write
RTC_DAY
Calendar Day of the week in BCD, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended
24
27
read-write
RTC_HOUR
Calendar hours in BCD, value depending on 12/24HR mode 0=24HR: [21:16]=0-23 1=12HR: [21]:0=AM, 1=PM, [20:16]=1-12
16
22
read-write
RTC_MIN
Calendar minutes in BCD, 0-59
8
15
read-write
RTC_SEC
Calendar seconds in BCD, 0-59
0
7
read-write
STATUS
Status
0x10
32
read-only
n
0x0
0x0
RTC_BUSY
pending RTC write
0
1
read-only
WCO_OK
Indicates that output has transitioned.
2
3
read-only
TICKS
128Hz tick counter
0x40
32
read-only
n
0x0
0x0
CNT128HZ
128Hz counter (msb=2Hz) When SECONDS is written this field will be reset.
0
6
read-only
TRIM
Trim Register
0xFF00
32
read-write
n
0x0
0x0
TRIM
WCO trim
0
6
read-write
CPUSS
CPU subsystem (CPUSS)
CPUSS
0x0
0x0
0x10000
registers
n
ioss_interrupts_gpio_0
GPIO Port Interrupt #0
0
ioss_interrupts_gpio_1
GPIO Port Interrupt #1
1
ioss_interrupts_gpio_2
GPIO Port Interrupt #2
2
ioss_interrupts_gpio_3
GPIO Port Interrupt #3
3
ioss_interrupts_gpio_4
GPIO Port Interrupt #4
4
ioss_interrupts_gpio_5
GPIO Port Interrupt #5
5
ioss_interrupts_gpio_6
GPIO Port Interrupt #6
6
ioss_interrupts_gpio_7
GPIO Port Interrupt #7
7
ioss_interrupts_gpio_8
GPIO Port Interrupt #8
8
ioss_interrupts_gpio_9
GPIO Port Interrupt #9
9
ioss_interrupts_gpio_10
GPIO Port Interrupt #10
10
ioss_interrupts_gpio_11
GPIO Port Interrupt #11
11
ioss_interrupts_gpio_12
GPIO Port Interrupt #12
12
ioss_interrupts_gpio_13
GPIO Port Interrupt #13
13
ioss_interrupts_gpio_14
GPIO Port Interrupt #14
14
ioss_interrupt_gpio
GPIO All Ports
15
ioss_interrupt_vdd
GPIO Supply Detect Interrupt
16
lpcomp_interrupt
Low Power Comparator Interrupt
17
scb_8_interrupt
Serial Communication Block #8 (DeepSleep capable)
18
srss_interrupt_mcwdt_0
Multi Counter Watchdog Timer interrupt
19
srss_interrupt_mcwdt_1
Multi Counter Watchdog Timer interrupt
20
srss_interrupt_backup
Backup domain interrupt
21
srss_interrupt
Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)
22
pass_interrupt_ctbs
CTBm Interrupt (all CTBms)
23
bless_interrupt
Bluetooth Radio interrupt
24
cpuss_interrupts_ipc_0
CPUSS Inter Process Communication Interrupt #0
25
cpuss_interrupts_ipc_1
CPUSS Inter Process Communication Interrupt #1
26
cpuss_interrupts_ipc_2
CPUSS Inter Process Communication Interrupt #2
27
cpuss_interrupts_ipc_3
CPUSS Inter Process Communication Interrupt #3
28
cpuss_interrupts_ipc_4
CPUSS Inter Process Communication Interrupt #4
29
cpuss_interrupts_ipc_5
CPUSS Inter Process Communication Interrupt #5
30
cpuss_interrupts_ipc_6
CPUSS Inter Process Communication Interrupt #6
31
cpuss_interrupts_ipc_7
CPUSS Inter Process Communication Interrupt #7
32
cpuss_interrupts_ipc_8
CPUSS Inter Process Communication Interrupt #8
33
cpuss_interrupts_ipc_9
CPUSS Inter Process Communication Interrupt #9
34
cpuss_interrupts_ipc_10
CPUSS Inter Process Communication Interrupt #10
35
cpuss_interrupts_ipc_11
CPUSS Inter Process Communication Interrupt #11
36
cpuss_interrupts_ipc_12
CPUSS Inter Process Communication Interrupt #12
37
cpuss_interrupts_ipc_13
CPUSS Inter Process Communication Interrupt #13
38
cpuss_interrupts_ipc_14
CPUSS Inter Process Communication Interrupt #14
39
cpuss_interrupts_ipc_15
CPUSS Inter Process Communication Interrupt #15
40
scb_0_interrupt
Serial Communication Block #0
41
scb_1_interrupt
Serial Communication Block #1
42
scb_2_interrupt
Serial Communication Block #2
43
scb_3_interrupt
Serial Communication Block #3
44
scb_4_interrupt
Serial Communication Block #4
45
scb_5_interrupt
Serial Communication Block #5
46
scb_6_interrupt
Serial Communication Block #6
47
scb_7_interrupt
Serial Communication Block #7
48
csd_interrupt
CSD (Capsense) interrupt
49
cpuss_interrupts_dw0_0
CPUSS DataWire #0, Channel #0
50
cpuss_interrupts_dw0_1
CPUSS DataWire #0, Channel #1
51
cpuss_interrupts_dw0_2
CPUSS DataWire #0, Channel #2
52
cpuss_interrupts_dw0_3
CPUSS DataWire #0, Channel #3
53
cpuss_interrupts_dw0_4
CPUSS DataWire #0, Channel #4
54
cpuss_interrupts_dw0_5
CPUSS DataWire #0, Channel #5
55
cpuss_interrupts_dw0_6
CPUSS DataWire #0, Channel #6
56
cpuss_interrupts_dw0_7
CPUSS DataWire #0, Channel #7
57
cpuss_interrupts_dw0_8
CPUSS DataWire #0, Channel #8
58
cpuss_interrupts_dw0_9
CPUSS DataWire #0, Channel #9
59
cpuss_interrupts_dw0_10
CPUSS DataWire #0, Channel #10
60
cpuss_interrupts_dw0_11
CPUSS DataWire #0, Channel #11
61
cpuss_interrupts_dw0_12
CPUSS DataWire #0, Channel #12
62
cpuss_interrupts_dw0_13
CPUSS DataWire #0, Channel #13
63
cpuss_interrupts_dw0_14
CPUSS DataWire #0, Channel #14
64
cpuss_interrupts_dw0_15
CPUSS DataWire #0, Channel #15
65
cpuss_interrupts_dw1_0
CPUSS DataWire #1, Channel #0
66
cpuss_interrupts_dw1_1
CPUSS DataWire #1, Channel #1
67
cpuss_interrupts_dw1_2
CPUSS DataWire #1, Channel #2
68
cpuss_interrupts_dw1_3
CPUSS DataWire #1, Channel #3
69
cpuss_interrupts_dw1_4
CPUSS DataWire #1, Channel #4
70
cpuss_interrupts_dw1_5
CPUSS DataWire #1, Channel #5
71
cpuss_interrupts_dw1_6
CPUSS DataWire #1, Channel #6
72
cpuss_interrupts_dw1_7
CPUSS DataWire #1, Channel #7
73
cpuss_interrupts_dw1_8
CPUSS DataWire #1, Channel #8
74
cpuss_interrupts_dw1_9
CPUSS DataWire #1, Channel #9
75
cpuss_interrupts_dw1_10
CPUSS DataWire #1, Channel #10
76
cpuss_interrupts_dw1_11
CPUSS DataWire #1, Channel #11
77
cpuss_interrupts_dw1_12
CPUSS DataWire #1, Channel #12
78
cpuss_interrupts_dw1_13
CPUSS DataWire #1, Channel #13
79
cpuss_interrupts_dw1_14
CPUSS DataWire #1, Channel #14
80
cpuss_interrupts_dw1_15
CPUSS DataWire #1, Channel #15
81
cpuss_interrupts_fault_0
CPUSS Fault Structure Interrupt #0
82
cpuss_interrupts_fault_1
CPUSS Fault Structure Interrupt #1
83
cpuss_interrupt_crypto
CRYPTO Accelerator Interrupt
84
cpuss_interrupt_fm
FLASH Macro Interrupt
85
cpuss_interrupts_cm0_cti_0
CM0+ CTI #0
86
cpuss_interrupts_cm0_cti_1
CM0+ CTI #1
87
cpuss_interrupts_cm4_cti_0
CM4 CTI #0
88
cpuss_interrupts_cm4_cti_1
CM4 CTI #1
89
tcpwm_0_interrupts_0
TCPWM #0, Counter #0
90
tcpwm_0_interrupts_1
TCPWM #0, Counter #1
91
tcpwm_0_interrupts_2
TCPWM #0, Counter #2
92
tcpwm_0_interrupts_3
TCPWM #0, Counter #3
93
tcpwm_0_interrupts_4
TCPWM #0, Counter #4
94
tcpwm_0_interrupts_5
TCPWM #0, Counter #5
95
tcpwm_0_interrupts_6
TCPWM #0, Counter #6
96
tcpwm_0_interrupts_7
TCPWM #0, Counter #7
97
tcpwm_1_interrupts_0
TCPWM #1, Counter #0
98
tcpwm_1_interrupts_1
TCPWM #1, Counter #1
99
tcpwm_1_interrupts_2
TCPWM #1, Counter #2
100
tcpwm_1_interrupts_3
TCPWM #1, Counter #3
101
tcpwm_1_interrupts_4
TCPWM #1, Counter #4
102
tcpwm_1_interrupts_5
TCPWM #1, Counter #5
103
tcpwm_1_interrupts_6
TCPWM #1, Counter #6
104
tcpwm_1_interrupts_7
TCPWM #1, Counter #7
105
tcpwm_1_interrupts_8
TCPWM #1, Counter #8
106
tcpwm_1_interrupts_9
TCPWM #1, Counter #9
107
tcpwm_1_interrupts_10
TCPWM #1, Counter #10
108
tcpwm_1_interrupts_11
TCPWM #1, Counter #11
109
tcpwm_1_interrupts_12
TCPWM #1, Counter #12
110
tcpwm_1_interrupts_13
TCPWM #1, Counter #13
111
tcpwm_1_interrupts_14
TCPWM #1, Counter #14
112
tcpwm_1_interrupts_15
TCPWM #1, Counter #15
113
tcpwm_1_interrupts_16
TCPWM #1, Counter #16
114
tcpwm_1_interrupts_17
TCPWM #1, Counter #17
115
tcpwm_1_interrupts_18
TCPWM #1, Counter #18
116
tcpwm_1_interrupts_19
TCPWM #1, Counter #19
117
tcpwm_1_interrupts_20
TCPWM #1, Counter #20
118
tcpwm_1_interrupts_21
TCPWM #1, Counter #21
119
tcpwm_1_interrupts_22
TCPWM #1, Counter #22
120
tcpwm_1_interrupts_23
TCPWM #1, Counter #23
121
udb_interrupts_0
UDB Interrupt #0
122
udb_interrupts_1
UDB Interrupt #1
123
udb_interrupts_2
UDB Interrupt #2
124
udb_interrupts_3
UDB Interrupt #3
125
udb_interrupts_4
UDB Interrupt #4
126
udb_interrupts_5
UDB Interrupt #5
127
udb_interrupts_6
UDB Interrupt #6
128
udb_interrupts_7
UDB Interrupt #7
129
udb_interrupts_8
UDB Interrupt #8
130
udb_interrupts_9
UDB Interrupt #9
131
udb_interrupts_10
UDB Interrupt #10
132
udb_interrupts_11
UDB Interrupt #11
133
udb_interrupts_12
UDB Interrupt #12
134
udb_interrupts_13
UDB Interrupt #13
135
udb_interrupts_14
UDB Interrupt #14
136
udb_interrupts_15
UDB Interrupt #15
137
pass_interrupt_sar
SAR ADC interrupt
138
audioss_interrupt_i2s
I2S Audio interrupt
139
audioss_interrupt_pdm
PDM/PCM Audio interrupt
140
profile_interrupt
Energy Profiler interrupt
141
smif_interrupt
Serial Memory Interface interrupt
142
usb_interrupt_hi
USB Interrupt
143
usb_interrupt_med
USB Interrupt
144
usb_interrupt_lo
USB Interrupt
145
pass_interrupt_dacs
Consolidated interrrupt for all DACs
146
AP_CTL
Access port control
0x540
32
read-write
n
0x0
0x0
CM0_DISABLE
Disables the CM0 AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'.
16
17
read-write
CM0_ENABLE
Enables the CM0 AP interface: '0': Disabled. '1': Enabled.
0
1
read-write
CM4_DISABLE
Disables the CM4 AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM4_DISABLE is '0' and CM4_ENABLE is '1'.
17
18
read-write
CM4_ENABLE
Enables the CM4 AP interface: '0': Disabled. '1': Enabled.
1
2
read-write
SYS_DISABLE
Disables the system AP interface: '0': Enabled. '1': Disabled. Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'.
18
19
read-write
SYS_ENABLE
Enables the system AP interface: '0': Disabled. '1': Enabled.
2
3
read-write
BUFF_CTL
Buffer control
0x220
32
read-write
n
0x0
0x0
WRITE_BUFF
Specifies if write transfer can be buffered in the bus infrastructure bridges: '0': Write transfers are not buffered, independent of the transfer's bufferable attribute. '1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write.
0
1
read-write
CM0_CLOCK_CTL
CM0+ clock control
0x10
32
read-write
n
0x0
0x0
PERI_INT_DIV
Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode. Note that Fperi <= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'.
24
32
read-write
SLOW_INT_DIV
Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
CM0_CTL
CM0+ control
0x0
32
read-write
n
0x0
0x0
ENABLED
Processor enable: '0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. '1': Enabled. Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented). Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value see CPU user manual for more details).
1
2
read-write
SLV_STALL
Processor debug access control: '0': Access. '1': Stall access. This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses.
0
1
read-write
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
CM0_INT_CTL0
CM0+ interrupt control 0
0x20
32
read-write
n
0x0
0x0
MUX0_SEL
System interrupt select for CPU interrupt source 0. If the field value is 240, no system interrupt is connected and the CPU interrupt source is always '0'/de-activated.
0
8
read-write
MUX1_SEL
System interrupt select for CPU interrupt source 1.
8
16
read-write
MUX2_SEL
System interrupt select for CPU interrupt source 2.
16
24
read-write
MUX3_SEL
System interrupt select for CPU interrupt source 3.
24
32
read-write
CM0_INT_CTL1
CM0+ interrupt control 1
0x24
32
read-write
n
0x0
0x0
MUX0_SEL
System interrupt select for CPU interrupt source 4.
0
8
read-write
MUX1_SEL
System interrupt select for CPU interrupt source 5.
8
16
read-write
MUX2_SEL
System interrupt select for CPU interrupt source 6.
16
24
read-write
MUX3_SEL
System interrupt select for CPU interrupt source 7.
24
32
read-write
CM0_INT_CTL2
CM0+ interrupt control 2
0x28
32
read-write
n
0x0
0x0
MUX0_SEL
System interrupt select for CPU interrupt source 8.
0
8
read-write
MUX1_SEL
System interrupt select for CPU interrupt source 9.
8
16
read-write
MUX2_SEL
System interrupt select for CPU interrupt source 10.
16
24
read-write
MUX3_SEL
System interrupt select for CPU interrupt source 11.
24
32
read-write
CM0_INT_CTL3
CM0+ interrupt control 3
0x2C
32
read-write
n
0x0
0x0
MUX0_SEL
System interrupt select for CPU interrupt source 12.
0
8
read-write
MUX1_SEL
System interrupt select for CPU interrupt source 13.
8
16
read-write
MUX2_SEL
System interrupt select for CPU interrupt source 14.
16
24
read-write
MUX3_SEL
System interrupt select for CPU interrupt source 15.
24
32
read-write
CM0_INT_CTL4
CM0+ interrupt control 4
0x30
32
read-write
n
0x0
0x0
MUX0_SEL
System interrupt select for CPU interrupt source 16.
0
8
read-write
MUX1_SEL
System interrupt select for CPU interrupt source 17.
8
16
read-write
MUX2_SEL
System interrupt select for CPU interrupt source 18.
16
24
read-write
MUX3_SEL
System interrupt select for CPU interrupt source 19.
24
32
read-write
CM0_INT_CTL5
CM0+ interrupt control 5
0x34
32
read-write
n
0x0
0x0
MUX0_SEL
System interrupt select for CPU interrupt source 20.
0
8
read-write
MUX1_SEL
System interrupt select for CPU interrupt source 21.
8
16
read-write
MUX2_SEL
System interrupt select for CPU interrupt source 22.
16
24
read-write
MUX3_SEL
System interrupt select for CPU interrupt source 23.
24
32
read-write
CM0_INT_CTL6
CM0+ interrupt control 6
0x38
32
read-write
n
0x0
0x0
MUX0_SEL
System interrupt select for CPU interrupt source 24.
0
8
read-write
MUX1_SEL
System interrupt select for CPU interrupt source 25.
8
16
read-write
MUX2_SEL
System interrupt select for CPU interrupt source 26.
16
24
read-write
MUX3_SEL
System interrupt select for CPU interrupt source 27.
24
32
read-write
CM0_INT_CTL7
CM0+ interrupt control 7
0x3C
32
read-write
n
0x0
0x0
MUX0_SEL
System interrupt select for CPU interrupt source 28.
0
8
read-write
MUX1_SEL
System interrupt select for CPU interrupt source 29.
8
16
read-write
MUX2_SEL
System interrupt select for CPU interrupt source 30.
16
24
read-write
MUX3_SEL
System interrupt select for CPU interrupt source 31.
24
32
read-write
CM0_NMI_CTL
CM0+ NMI control
0x520
32
read-write
n
0x0
0x0
MUX0_SEL
System interrupt select for CPU NMI. The reset value ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.
0
8
read-write
CM0_PC0_HANDLER
CM0+ protection context 0 handler
0x320
32
read-write
n
0x0
0x0
ADDR
Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt.
0
32
read-write
CM0_STATUS
CM0+ status
0x8
32
read-only
n
0x0
0x0
SLEEPDEEP
Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field.
1
2
read-only
SLEEPING
Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'.
0
1
read-only
CM0_VECTOR_TABLE_BASE
CM0+ vector table base
0x2B0
32
read-write
n
0x0
0x0
ADDR24
Address of CM0+ vector table. Note: the CM0+ vector table is at an address that is a 256 B multiple.
8
32
read-write
CM4_CLOCK_CTL
CM4 clock control
0x90
32
read-write
n
0x0
0x0
FAST_INT_DIV
Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]). Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
CM4_NMI_CTL
CM4 NMI control
0xA0
32
read-write
n
0x0
0x0
MUX0_SEL
System interrupt select for CPU NMI. The reset value ensure that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.
0
8
read-write
CM4_PWR_CTL
CM4 power control
0x80
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for CM4
0
2
read-write
OFF
Switch CM4 off Power off, clock off, isolate, reset and no retain.
0
RESET
Reset CM4 Clock off, no isolated, no retain and reset. Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot.
1
RETAINED
Put CM4 in Retained mode This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached. Power off, clock off, isolate, no reset and retain.
2
ENABLED
Switch CM4 on. Power on, clock on, no isolate, no reset and no retain.
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
CM4_PWR_DELAY_CTL
CM4 power control
0x84
32
read-write
n
0x0
0x0
UP
Number clock cycles delay needed after power domain power up
0
10
read-write
CM4_STATUS
CM4 status
0x88
32
read-only
n
0x0
0x0
PWR_DONE
After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. Note: this flag can also change as a result of a change in debug power up req
4
5
read-only
SLEEPDEEP
Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field.
1
2
read-only
SLEEPING
Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'.
0
1
read-only
CM4_VECTOR_TABLE_BASE
CM4 vector table base
0x2C0
32
read-write
n
0x0
0x0
ADDR22
Address of CM4 vector table. Note: the CM4 vector table is at an address that is a 1024 B multiple.
10
32
read-write
DDFT_CTL
DDFT control
0x230
32
read-write
n
0x0
0x0
DDFT_OUT0_SEL
Select signal for CPUSS DDFT[0] 0: clk_r of the Main flash (which is clk_hf for SONOS Flash) 1: Flash data output bit '0' (r_q[0]) 2: Flash data output bit '32' (r_q[32]) 3: Flash data output bit '64' (r_q[64]) 4: Flash data output bit '127' (r_q[127]) 5: bist_fm_enabled 6: bist_fail 7: cm0_sleeping 8: cm0_sleepdeep 9: cm0_sleep_hold_ack_n 10: cm4_sleeping 11: cm4_sleepdeep 12: cm4_sleep_hold_ack_n 13: cm4_power 14: cm4_act_retain_n 15: cm4_act_isolate_n 16: cm4_enabled 17: cm4_reset_n 18: cm4_pwr_done 19: mmio_ram0_ctl1_power[0] (Power control for SRAM0 macro0) 20: mmio_ram0_ctl1_retain_n[0] (Retention control for SRAM0 macro0) 21: mmio_ram0_ctl1_isolate_n[0] (Isolation control for SRAM0 macro0)
0
5
read-write
DDFT_OUT1_SEL
Select signal for CPUSS DDFT[0] 0: clk_r of the Main flash (which is clk_hf for SONOS Flash) 1: Flash data output bit '0' (r_q[0]) 2: Flash data output bit '32' (r_q[32]) 3: Flash data output bit '64' (r_q[64]) 4: Flash data output bit '127' (r_q[127]) 5: bist_fm_enabled 6: bist_fail 7: cm0_sleeping 8: cm0_sleepdeep 9: cm0_sleep_hold_ack_n 10: cm4_sleeping 11: cm4_sleepdeep 12: cm4_sleep_hold_ack_n 13: cm4_power 14: cm4_act_retain_n 15: cm4_act_isolate_n 16: cm4_enabled 17: cm4_reset_n 18: cm4_pwr_done 19: mmio_ram0_ctl1_power[0] (Power control for SRAM0 macro0) 20: mmio_ram0_ctl1_retain_n[0] (Retention control for SRAM0 macro0) 21: mmio_ram0_ctl1_isolate_n[0] (Isolation control for SRAM0 macro0)
8
13
read-write
DP_STATUS
Debug port status
0x208
32
read-only
n
0x0
0x0
SWJ_CONNECTED
Specifies if the SWJ debug port is connected i.e. debug host interface is active: '0': Not connected/not active. '1': Connected/active.
0
1
read-only
SWJ_DEBUG_EN
Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on: '0': Disabled. '1': Enabled.
1
2
read-only
SWJ_JTAG_SEL
Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected). '0': SWD selected. '1': JTAG selected.
2
3
read-only
IDENTITY
Identity
0x400
32
read-only
n
0x0
0x0
MS
This field specifies the bus master identifier of the transfer that reads the register.
8
12
read-only
NS
This field specifies the security setting ('0': secure mode '1': non-secure mode) of the transfer that reads the register.
1
2
read-only
P
This field specifies the privileged setting ('0': user mode '1': privileged mode) of the transfer that reads the register.
0
1
read-only
PC
This field specifies the protection context of the transfer that reads the register.
4
8
read-only
MBIST_STAT
Memory BIST status
0x5A0
32
read-only
n
0x0
0x0
SFP_FAIL
Report status of the BIST run, only valid if SFP_READY=1
1
2
read-only
SFP_READY
Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0.
0
1
read-only
PROTECTION
Protection status
0x500
32
read-write
n
0x0
0x0
STATE
Protection state: '0': UNKNOWN. '1': VIRGIN. '2': NORMAL. '3': SECURE. '4': DEAD. The following state transitions are allowed (and enforced by HW): - UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD - NORMAL => DEAD - SECURE => DEAD An attempt to make a NOT allowed state transition will NOT affect this register field.
0
3
read-write
RAM0_CTL0
RAM 0 control 0
0x100
32
read-write
n
0x0
0x0
FAST_WS
Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
8
10
read-write
SLOW_WS
Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
0
2
read-write
RAM0_PWR_MACRO_CTL0
RAM 0 power control
0x140
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for 1 SRAM0 Macro
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM0_PWR_MACRO_CTL1
RAM 0 power control
0x144
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for 1 SRAM0 Macro
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM0_PWR_MACRO_CTL10
RAM 0 power control
0x168
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for 1 SRAM0 Macro
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM0_PWR_MACRO_CTL11
RAM 0 power control
0x16C
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for 1 SRAM0 Macro
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM0_PWR_MACRO_CTL12
RAM 0 power control
0x170
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for 1 SRAM0 Macro
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM0_PWR_MACRO_CTL13
RAM 0 power control
0x174
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for 1 SRAM0 Macro
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM0_PWR_MACRO_CTL14
RAM 0 power control
0x178
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for 1 SRAM0 Macro
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM0_PWR_MACRO_CTL15
RAM 0 power control
0x17C
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for 1 SRAM0 Macro
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM0_PWR_MACRO_CTL2
RAM 0 power control
0x148
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for 1 SRAM0 Macro
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM0_PWR_MACRO_CTL3
RAM 0 power control
0x14C
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for 1 SRAM0 Macro
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM0_PWR_MACRO_CTL4
RAM 0 power control
0x150
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for 1 SRAM0 Macro
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM0_PWR_MACRO_CTL5
RAM 0 power control
0x154
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for 1 SRAM0 Macro
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM0_PWR_MACRO_CTL6
RAM 0 power control
0x158
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for 1 SRAM0 Macro
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM0_PWR_MACRO_CTL7
RAM 0 power control
0x15C
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for 1 SRAM0 Macro
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM0_PWR_MACRO_CTL8
RAM 0 power control
0x160
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for 1 SRAM0 Macro
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM0_PWR_MACRO_CTL9
RAM 0 power control
0x164
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for 1 SRAM0 Macro
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM1_CTL0
RAM 1 control 0
0x180
32
read-write
n
0x0
0x0
FAST_WS
Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
8
10
read-write
SLOW_WS
Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
0
2
read-write
RAM1_PWR_CTL
RAM1 power control
0x190
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for SRAM1
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM2_CTL0
RAM 2 control 0
0x1A0
32
read-write
n
0x0
0x0
FAST_WS
Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
8
10
read-write
SLOW_WS
Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
0
2
read-write
RAM2_PWR_CTL
RAM2 power control
0x1B0
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for SRAM2
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
RAM_PWR_DELAY_CTL
Power up delay used for all SRAM power domains
0x1C0
32
read-write
n
0x0
0x0
UP
Number clock cycles delay needed after power domain power up
0
10
read-write
ROM_CTL
ROM control
0x1D0
32
read-write
n
0x0
0x0
FAST_WS
Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
8
10
read-write
SLOW_WS
Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles. Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met. A table/formula will be provided for this field's values for different 'clk_hf' frequencies.
0
2
read-write
SYSTICK_CTL
SysTick timer control
0x240
32
read-write
n
0x0
0x0
CLOCK_SOURCE
Specifies an external clock source: '0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise). '1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock. o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected. '3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo'). Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used. Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source.
24
26
read-write
NOREF
Specifies if an external clock source is provided: '0': An external clock source is provided. '1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source.
31
32
read-write
SKEW
Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock: '0': Precise. '1': Imprecise.
30
31
read-write
TENMS
Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327.
0
24
read-write
TRIM_RAM_CTL
RAM trim control
0xF004
32
read-write
n
0x0
0x0
RA
Read Assist control for WL under-drive.
8
10
read-write
RM
N/A
0
4
read-write
RME
Read-Write margin enable control. This selects between the default Read-Write margin setting, and the external RM[3:0] Read-Write margin setting.
4
5
read-write
WA
Write assist enable control (Active High). - WA[1:0] Write Assist pins to control negative voltage on SRAM bitline.
12
15
read-write
WPULSE
Write Assist Pulse to control pulse width of negative voltage on SRAM bitline.
5
8
read-write
TRIM_ROM_CTL
ROM trim control
0xF000
32
read-write
n
0x0
0x0
RM
N/A
0
4
read-write
RME
Read-Write margin enable control. This selects between the default Read-Write margin setting, and the external pin Read-Write margin setting.
4
5
read-write
UDB_PWR_CTL
UDB power control
0x1F0
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for UDBs
0
2
read-write
OFF
See CM4_PWR_CTL
0
RESET
See CM4_PWR_CTL
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
UDB_PWR_DELAY_CTL
UDB power control
0x1F4
32
read-write
n
0x0
0x0
UP
Number clock cycles delay needed after power domain power up
0
10
read-write
FAULT
Fault structures
FAULT
0x0
0x0
0x10000
registers
n
CTL
Fault control
0x0
32
read-write
n
0x0
0x0
OUT_EN
IO output signal enable: '0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'. '1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'.
1
2
read-write
RESET_REQ_EN
Reset request enable: '0': Disabled. '1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis). The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal.
2
3
read-write
TR_EN
Trigger output enable: '0': Disabled. The trigger output 'tr_fault' is '0'. '1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3).
0
1
read-write
DATA0
Fault data
0x10
32
read-only
n
0x0
0x0
DATA
Captured fault source data. Note: the fault source index STATUS.IDX specifies the format of the DATA registers.
0
32
read-only
DATA1
Fault data
0x14
32
read-only
n
0x0
0x0
DATA
Captured fault source data. Note: the fault source index STATUS.IDX specifies the format of the DATA registers.
0
32
read-only
DATA2
Fault data
0x18
32
read-only
n
0x0
0x0
DATA
Captured fault source data. Note: the fault source index STATUS.IDX specifies the format of the DATA registers.
0
32
read-only
DATA3
Fault data
0x1C
32
read-only
n
0x0
0x0
DATA
Captured fault source data. Note: the fault source index STATUS.IDX specifies the format of the DATA registers.
0
32
read-only
INTR
Interrupt
0xC0
32
read-write
n
0x0
0x0
FAULT
This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured: - STATUS.VALID is set to '1'. - STATUS.IDX specifies the fault source index. - DATA0 through DATA3 captures the fault source data. SW writes a '1' to these field to clear the interrupt cause to '0'.
0
1
read-write
INTR_MASK
Interrupt mask
0xC8
32
read-write
n
0x0
0x0
FAULT
Mask bit for corresponding field in the INTR register.
0
1
read-write
INTR_MASKED
Interrupt masked
0xCC
32
read-only
n
0x0
0x0
FAULT
Logical and of corresponding INTR and INTR_MASK fields.
0
1
read-only
INTR_SET
Interrupt set
0xC4
32
read-write
n
0x0
0x0
FAULT
SW writes a '1' to this field to set the corresponding field in the INTR register.
0
1
read-write
MASK0
Fault mask 0
0x50
32
read-write
n
0x0
0x0
SOURCE
Fault source enables: Bits 31-0: Fault sources 31 to 0.
0
32
read-write
MASK1
Fault mask 1
0x54
32
read-write
n
0x0
0x0
SOURCE
Fault source enables: Bits 31-0: Fault sources 63 to 32.
0
32
read-write
MASK2
Fault mask 2
0x58
32
read-write
n
0x0
0x0
SOURCE
Fault source enables: Bits 31-0: Fault sources 95 to 64.
0
32
read-write
PENDING0
Fault pending 0
0x40
32
read-only
n
0x0
0x0
SOURCE
This field specifies the following sources: Bit 0: CM0 MPU. Bit 1: CRYPTO MPU. Bit 2: DW 0 MPU. Bit 3: DW 1 MPU. ... Bit 14: CM4 code bus MPU. Bit 15: DAP MPU. Bit 16: CM4 s+G92ystem bus MPU. Bit 28: Peripheral master interface 0 PPU. Bit 29: Peripheral master interface 1 PPU. Bit 30: Peripheral master interface 2 PPU. Bit 31: Peripheral master interface 3 PPU.
0
32
read-only
PENDING1
Fault pending 1
0x44
32
read-only
n
0x0
0x0
SOURCE
This field specifies the following sources: Bit 0: Peripheral group 0 PPU. Bit 1: Peripheral group 1 PPU. Bit 2: Peripheral group 2 PPU. Bit 3: Peripheral group 3 PPU. Bit 4: Peripheral group 4 PPU. Bit 5: Peripheral group 5 PPU. Bit 6: Peripheral group 6 PPU. Bit 7: Peripheral group 7 PPU. ... Bit 15: Peripheral group 15 PPU. Bit 18: Flash controller, main interface, bus error.
0
32
read-only
PENDING2
Fault pending 2
0x48
32
read-only
n
0x0
0x0
SOURCE
This field specifies the following sources: Bit 0 - 31: TBD.
0
32
read-only
STATUS
Fault status
0xC
32
read-write
n
0x0
0x0
IDX
The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below. Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'.
0
7
read-only
VALID
Valid indication: '0': Invalid. '1': Valid. HW sets this field to '1' when new fault source data is captured. New fault source data is ONLY captured when VALID is '0'. SW can clear this field to '0' when the fault is handled (by SW).
31
32
read-write
FLASHC
Flash controller
FLASHC
0x0
0x0
0x10000
registers
n
ACLK_CTL
Aclk control
0x38
32
write-only
n
0x0
0x0
ACLK_GEN
A write to this register generates a ACLK pulse for the flash macro (also requires FM_CTL.IF_SEL to be '1').
0
1
write-only
ANA_CTL0
Analog control 0
0x18
32
read-write
n
0x0
0x0
CSLDAC
Trimming of common source line DAC.
8
11
read-write
FLIP_AMUXBUS_AB
Flips amuxbusa and amuxbusb '0': amuxbusa, amuxbusb '1': amuxbusb, amuxbusb
27
28
read-write
VCC_SEL
Vcc select: '0': 1.2 V : LP reset value '1': 0.95 V: ULP reset value Note: the flash macro compiler has a configuration option that specifies the default/reset value of this field.
24
25
read-write
ANA_CTL1
Analog control 1
0x1C
32
read-write
n
0x0
0x0
MDAC
Trimming of the output margin Voltage as a function of Vpos and Vneg.
0
8
read-write
NDAC
Trimming of negative pump output Voltage:
24
28
read-write
PDAC
Trimming of positive pump output Voltage:
16
20
read-write
RST_SFT_HVPL
'1': Page Latches Soft Reset
30
31
read-write
R_GRANT_CTL
r_grant control: '0': r_grant normal functionality '1': forces r_grant LO synchronized on clk_r
29
30
read-write
VPROT_OVERRIDE
'0': vprot = BG.vprot. '1': vprot = vcc
28
29
read-write
BIST_ADDR
BIST address register
0x16C
32
read-only
n
0x0
0x0
COL_ADDR
Current column address.
0
16
read-only
ROW_ADDR
Current row address.
16
32
read-only
BIST_ADDR_START
BIST address start register
0x108
32
read-write
n
0x0
0x0
COL_ADDR_START
Column start address. Useful to apply BIST to a part of an Flash. The value of this field should be in a legal range (a value outside of the legal range has an undefined result, and may lock up the BIST state machine). This legal range is dependent on the number of columns of the SRAM the BIST is applied to (as specified by BIST_CTL.SRAMS_ENABLED). E.g. for a Flash with n columns, the legal range is [0, n-1].
0
16
read-write
ROW_ADDR_START
Row start address. Useful to apply BIST to a part of an Flash. The value of this field should be in a legal range (a value outside of the legal range has an undefined result, and may lock up the BIST state machine). This legal range is dependent on the number of rows of the SRAM the BIST is applied to (as specified by BIST_CTL.SRAMS_ENABLED). E.g. for a Flash with m columns, the legal range is [0, m-1].
16
32
read-write
BIST_CMD
BIST command
0x104
32
read-write
n
0x0
0x0
START
1: Start FLASH BIST. Hardware set this field to '0' when BIST is completed.
0
1
read-write
BIST_CTL
BIST control
0x100
32
read-write
n
0x0
0x0
ADDR_COMPLIMENT_ENABLED
Specifies to generate address compliment patterns. 0: Generate normal increment/decrement patterns. 1: Generate address patterns which interleaves compliment of previous address in between. Example: The following is an example pattern, With UP=1 and ROW_FIRST =0 00_00 11_11 00_01 11_10 00_10 11_01 ...
5
6
read-write
ADDR_START_ENABLED
Specifies Flash BIST start addresses: '0': Row and column addresses start with their maximum/minimum values. '1': Row and column addresses start with their values as specified by BIST_ADDR_START. This feature is supported only for simple increment/decrement patterns. It is not supported with address compliment pattern (BIST_CTL.ADDR_COMPLIMENT_ENABLED) or address pattern which increments/decrements both row address and column address (BIST_CTL.INCR_DECR_BOTH) for every read.
4
5
read-write
INCR_DECR_BOTH
Specifies to generate patterns where both column address and row address are incremented/decremented simultaneously. 0: Generate normal increment/decrement patterns. 1: Generate address patterns with both row and column address changing. Example: With UP = 1 and ROW_FIRST = 0 00_00 01_01 10_10 11_11 00_01 01_10 10_11 11_00 00_10 ...
6
7
read-write
OPCODE
This field specifies how the data check should be performed after reading the data from Flash memory. 0: Read the Flash and compare the output to BIST_DATA (R0). 1: Read the Flash and compare the output to the binary complement of BIST_DATA (R1). 3: Read the Flash and compare with BIST_DATA[] and compliment of BIST_DATA alternately (R01). The expected data of the first read is BIST_DATA, expected data of the second read is binary compliment of BIST_DATA, third read expected data is BIST_DATA, fourth read expected data is binary compliment of BIST_DATA and so on.
0
2
read-write
ROW_FIRST
Specifies how the Flash BIST addresses are generated: '0': Column address is incremented/decremented till it reaches its maximum/minimum value. Once it reach its maximum/minimum value, it is set to its minimum/maximum value and only then is the row address incremented/decremented. '1': Row address is incremented/decremented till it reaches its maximum/minimum value. Once it reach its maximum/minimum value, it is set to its minimum/maximum value and only then is the column address incremented/decremented.
3
4
read-write
STOP_ON_ERROR
Specifies the BIST to continue indefinitely, regardless of occurrence of errors or not. 0: BIST controller doesn't stop on the data failures, it continues regardless of the errors. 1: BIST controller stops on when the first data failure is encountered.
7
8
read-write
UP
Specifies direction in which Flash BIST steps through addresses: 0: BIST steps through the Flash from the maximum row and column addresses (as specified by a design time configuration parameter when ADDR_START_ENABLED is '0' and as specified by BIST_ADDR_START when ADDR_START_ENABLED is '1') to the minimum row and column addresses. 1: BIST steps through the Flash from the minimum row and column addresses ('0' when ADDR_START_ENABLED is '0' and as specified by BIST_ADDR_START when ADDR_START_ENABLED is '1'' to the maximum row and column addresses.
2
3
read-write
BIST_DATA0
BIST data register(s)
0x10C
32
read-write
n
0x0
0x0
DATA
BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.
0
32
read-write
BIST_DATA1
BIST data register(s)
0x110
32
read-write
n
0x0
0x0
DATA
BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.
0
32
read-write
BIST_DATA2
BIST data register(s)
0x114
32
read-write
n
0x0
0x0
DATA
BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.
0
32
read-write
BIST_DATA3
BIST data register(s)
0x118
32
read-write
n
0x0
0x0
DATA
BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.
0
32
read-write
BIST_DATA4
BIST data register(s)
0x11C
32
read-write
n
0x0
0x0
DATA
BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.
0
32
read-write
BIST_DATA5
BIST data register(s)
0x120
32
read-write
n
0x0
0x0
DATA
BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.
0
32
read-write
BIST_DATA6
BIST data register(s)
0x124
32
read-write
n
0x0
0x0
DATA
BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.
0
32
read-write
BIST_DATA7
BIST data register(s)
0x128
32
read-write
n
0x0
0x0
DATA
BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.
0
32
read-write
BIST_DATA_ACT0
BIST data actual register(s)
0x12C
32
read-only
n
0x0
0x0
DATA
This field specified the actual Flash data output that caused the BIST failure.
0
32
read-only
BIST_DATA_ACT1
BIST data actual register(s)
0x130
32
read-only
n
0x0
0x0
DATA
This field specified the actual Flash data output that caused the BIST failure.
0
32
read-only
BIST_DATA_ACT2
BIST data actual register(s)
0x134
32
read-only
n
0x0
0x0
DATA
This field specified the actual Flash data output that caused the BIST failure.
0
32
read-only
BIST_DATA_ACT3
BIST data actual register(s)
0x138
32
read-only
n
0x0
0x0
DATA
This field specified the actual Flash data output that caused the BIST failure.
0
32
read-only
BIST_DATA_ACT4
BIST data actual register(s)
0x13C
32
read-only
n
0x0
0x0
DATA
This field specified the actual Flash data output that caused the BIST failure.
0
32
read-only
BIST_DATA_ACT5
BIST data actual register(s)
0x140
32
read-only
n
0x0
0x0
DATA
This field specified the actual Flash data output that caused the BIST failure.
0
32
read-only
BIST_DATA_ACT6
BIST data actual register(s)
0x144
32
read-only
n
0x0
0x0
DATA
This field specified the actual Flash data output that caused the BIST failure.
0
32
read-only
BIST_DATA_ACT7
BIST data actual register(s)
0x148
32
read-only
n
0x0
0x0
DATA
This field specified the actual Flash data output that caused the BIST failure.
0
32
read-only
BIST_DATA_EXP0
BIST data expected register(s)
0x14C
32
read-only
n
0x0
0x0
DATA
This field specified the expected Flash data output.
0
32
read-only
BIST_DATA_EXP1
BIST data expected register(s)
0x150
32
read-only
n
0x0
0x0
DATA
This field specified the expected Flash data output.
0
32
read-only
BIST_DATA_EXP2
BIST data expected register(s)
0x154
32
read-only
n
0x0
0x0
DATA
This field specified the expected Flash data output.
0
32
read-only
BIST_DATA_EXP3
BIST data expected register(s)
0x158
32
read-only
n
0x0
0x0
DATA
This field specified the expected Flash data output.
0
32
read-only
BIST_DATA_EXP4
BIST data expected register(s)
0x15C
32
read-only
n
0x0
0x0
DATA
This field specified the expected Flash data output.
0
32
read-only
BIST_DATA_EXP5
BIST data expected register(s)
0x160
32
read-only
n
0x0
0x0
DATA
This field specified the expected Flash data output.
0
32
read-only
BIST_DATA_EXP6
BIST data expected register(s)
0x164
32
read-only
n
0x0
0x0
DATA
This field specified the expected Flash data output.
0
32
read-only
BIST_DATA_EXP7
BIST data expected register(s)
0x168
32
read-only
n
0x0
0x0
DATA
This field specified the expected Flash data output.
0
32
read-only
BIST_STATUS
BIST status register
0x170
32
read-write
n
0x0
0x0
FAIL
0: BIST passed. 1: BIST failed.
0
1
read-write
BOOKMARK
Bookmark register - keeps the current FW HV seq
0x60
32
write-only
n
0x0
0x0
BOOKMARK
Used by FW. Keeps the Current HV cycle sequence
0
32
write-only
CAL_CTL0
Cal control BG LO trim bits
0x50
32
read-write
n
0x0
0x0
CDAC_LO_HV
LO Temperature compensated trim DAC. To control Vcstat slope for Vpos.
5
8
read-write
IPREF_TRIM_LO_HV
LO Bandgap IPTAT trim control.
16
20
read-write
VBG_TC_TRIM_LO_HV
LO Bandgap Voltage Temperature Compensation trim control
13
16
read-write
VBG_TRIM_LO_HV
LO Bandgap Voltage trim control.
8
13
read-write
VCT_TRIM_LO_HV
LO Bandgap Voltage Temperature Compensation trim control.
0
5
read-write
CAL_CTL1
Cal control BG HI trim bits
0x54
32
read-write
n
0x0
0x0
CDAC_HI_HV
HI Temperature compensated trim DAC. To control Vcstat slope for Vpos.
5
8
read-write
IPREF_TRIM_HI_HV
HI Bandgap IPTAT trim control.
16
20
read-write
VBG_TC_TRIM_HI_HV
HI Bandgap Voltage Temperature Compensation trim control.
13
16
read-write
VBG_TRIM_HI_HV
HI Bandgap Voltage trim control.
8
13
read-write
VCT_TRIM_HI_HV
HI Bandgap Voltage Temperature Compensation trim control.
0
5
read-write
CAL_CTL2
Cal control BG LO and HI ipref trim, ref sel, fm_active, turbo_ext
0x58
32
read-write
n
0x0
0x0
FM_ACTIVE_HV
0: No Action 1: Forces FM SYS in active mode
18
19
read-write
ICREF_TC_TRIM_HI_HV
HI Bandgap Current Temperature Compensation trim control.
13
16
read-write
ICREF_TC_TRIM_LO_HV
LO Bandgap Current Temperature Compensation trim control
5
8
read-write
ICREF_TRIM_HI_HV
HI Bandgap Current trim control.
8
13
read-write
ICREF_TRIM_LO_HV
LO Bandgap Current trim control.
0
5
read-write
IREF_SEL_HV
Current reference: '0': internal current reference '1': external current reference
17
18
read-write
TURBO_EXT_HV
0: turbo signal generated internally 1: turbo cleared by clk_pump_ext HI
19
20
read-write
VREF_SEL_HV
Voltage reference: '0': internal bandgap reference '1': external voltage reference
16
17
read-write
CAL_CTL3
Cal control osc trim bits, idac, sdac, itim, bdac.
0x5C
32
read-write
n
0x0
0x0
BGHI_EN_HV
HI Bandgap Enable
19
20
read-write
BGLO_EN_HV
LO Bandgap Enable
18
19
read-write
IDAC_HV
N/A
5
9
read-write
ITIM_HV
Trimming of timing current
11
15
read-write
OSC_RANGE_TRIM_HV
0: Oscillator High Frequency Range 1: Oscillator Low Frequency range
4
5
read-write
OSC_TRIM_HV
Flash macro pump clock trim control.
0
4
read-write
SDAC_HV
N/A
9
11
read-write
TURBO_PULSEW_HV
Turbo pulse width trim
16
18
read-write
VDDHI_HV
0': vdd<2.3V '1': vdd>=2.3V
15
16
read-write
CM0_CA_CMD
CM0+ cache command
0x40C
32
read-write
n
0x0
0x0
INV
FLASH cache invalidation. SW writes a '1' to clear the cache. W sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The cache's LRU structure is also reset to its default state.
0
1
read-write
CM0_CA_CTL0
CM0+ cache control
0x400
32
read-write
n
0x0
0x0
ENABLED
Cache enable: 0: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way). 1: Enabled.
31
32
read-write
PREF_EN
Prefetch enable: 0: Disabled. 1: Enabled. Prefetching requires the cache to be enabled i.e. ENABLED is '1'.
30
31
read-write
SET_ADDR
Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2.
24
27
read-write
WAY
Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2.
16
18
read-write
CM0_CA_CTL1
CM0+ cache control
0x404
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for CM0 cache
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
CM0_CA_CTL2
CM0+ cache control
0x408
32
read-write
n
0x0
0x0
PWRUP_DELAY
Number clock cycles delay needed after power domain power up
0
10
read-write
CM0_CA_STATUS0
CM0+ cache status 0
0x440
32
read-only
n
0x0
0x0
VALID16
Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR.
0
16
read-only
CM0_CA_STATUS1
CM0+ cache status 1
0x444
32
read-only
n
0x0
0x0
TAG
Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR.
0
32
read-only
CM0_CA_STATUS2
CM0+ cache status 2
0x448
32
read-only
n
0x0
0x0
LRU
Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y): Bit 5: 0_LRU_1: way 0 less recently used than way 1. Bit 4: 0_LRU_2. Bit 3: 0_LRU_3. Bit 2: 1_LRU_2. Bit 1: 1_LRU_3. Bit 0: 2_LRU_3.
0
6
read-only
CM4_CA_CMD
CM4 cache command
0x48C
32
read-write
n
0x0
0x0
INV
See CM0_CA_CMD.
0
1
read-write
CM4_CA_CTL0
CM4 cache control
0x480
32
read-write
n
0x0
0x0
ENABLED
See CM0_CA_CTL.
31
32
read-write
PREF_EN
See CM0_CA_CTL.
30
31
read-write
SET_ADDR
See CM0_CA_CTL.
24
27
read-write
WAY
See CM0_CA_CTL.
16
18
read-write
CM4_CA_CTL1
CM4 cache control
0x484
32
read-write
n
0x0
0x0
PWR_MODE
Set Power mode for CM4 cache
0
2
read-write
OFF
See CM4_PWR_CTL
0
RSVD
undefined
1
RETAINED
See CM4_PWR_CTL
2
ENABLED
See CM4_PWR_CTL
3
VECTKEYSTAT
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05.
16
32
read-only
CM4_CA_CTL2
CM4 cache control
0x488
32
read-write
n
0x0
0x0
PWRUP_DELAY
Number clock cycles delay needed after power domain power up
0
10
read-write
CM4_CA_STATUS0
CM4 cache status 0
0x4C0
32
read-only
n
0x0
0x0
VALID16
See CM0_CA_STATUS0.
0
16
read-only
CM4_CA_STATUS1
CM4 cache status 1
0x4C4
32
read-only
n
0x0
0x0
TAG
See CM0_CA_STATUS1.
0
32
read-only
CM4_CA_STATUS2
CM4 cache status 2
0x4C8
32
read-only
n
0x0
0x0
LRU
See CM0_CA_STATUS2.
0
6
read-only
CRYPTO_BUFF_CMD
Cryptography buffer command
0x508
32
read-write
n
0x0
0x0
INV
FLASH buffer invalidation. SW writes a '1' to clear the buffer. HW sets this field to '0' when the operation is completed.
0
1
read-write
CRYPTO_BUFF_CTL
Cryptography buffer control
0x500
32
read-write
n
0x0
0x0
ENABLED
Cache enable: 0: Disabled. 1: Enabled.
31
32
read-write
PREF_EN
Prefetch enable: 0: Disabled. 1: Enabled. Prefetching requires the buffer to be enabled i.e. ENABLED is '1'.
30
31
read-write
DAP_BUFF_CMD
Debug access port buffer command
0x688
32
read-write
n
0x0
0x0
INV
See CRYPTO_BUFF_CMD.
0
1
read-write
DAP_BUFF_CTL
Debug access port buffer control
0x680
32
read-write
n
0x0
0x0
ENABLED
See CRYPTO_BUFF_CTL.
31
32
read-write
PREF_EN
See CRYPTO_BUFF_CTL.
30
31
read-write
DW0_BUFF_CMD
Datawire 0 buffer command
0x588
32
read-write
n
0x0
0x0
INV
See CRYPTO_BUFF_CMD.
0
1
read-write
DW0_BUFF_CTL
Datawire 0 buffer control
0x580
32
read-write
n
0x0
0x0
ENABLED
See CRYPTO_BUFF_CTL.
31
32
read-write
PREF_EN
See CRYPTO_BUFF_CTL.
30
31
read-write
DW1_BUFF_CMD
Datawire 1 buffer command
0x608
32
read-write
n
0x0
0x0
INV
See CRYPTO_BUFF_CMD.
0
1
read-write
DW1_BUFF_CTL
Datawire 1 buffer control
0x600
32
read-write
n
0x0
0x0
ENABLED
See CRYPTO_BUFF_CTL.
31
32
read-write
PREF_EN
See CRYPTO_BUFF_CTL.
30
31
read-write
EXT_MS0_BUFF_CMD
External master 0 buffer command
0x708
32
read-write
n
0x0
0x0
INV
See CRYPTO_BUFF_CMD.
0
1
read-write
EXT_MS0_BUFF_CTL
External master 0 buffer control
0x700
32
read-write
n
0x0
0x0
ENABLED
See CRYPTO_BUFF_CTL.
31
32
read-write
PREF_EN
See CRYPTO_BUFF_CTL.
30
31
read-write
EXT_MS1_BUFF_CMD
External master 1 buffer command
0x788
32
read-write
n
0x0
0x0
INV
See CRYPTO_BUFF_CMD.
0
1
read-write
EXT_MS1_BUFF_CTL
External master 1 buffer control
0x780
32
read-write
n
0x0
0x0
ENABLED
See CRYPTO_BUFF_CTL.
31
32
read-write
PREF_EN
See CRYPTO_BUFF_CTL.
30
31
read-write
FLASH_CMD
Command
0x8
32
read-write
n
0x0
0x0
INV
FLASH cache and buffer invalidation for ALL cache and buffers. SW writes a '1' to clear the cache and buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state.
0
1
read-write
FLASH_CTL
Control
0x0
32
read-write
n
0x0
0x0
MAIN_WS
FLASH macro main interface wait states: 0: 0 wait states. ... 15: 15 wait states
0
4
read-write
REMAP
Specifies remapping of FLASH macro main region. 0: No remapping. 1: Remapping. The highest address bit of the FLASH main region is inverted. This effectively remaps the location of FLASH main region physical sectors in the logical address space. In other words, the higher half physical sectors are swapped with the lower half physical sectors. Note: remapping only affects reading of the FLASH main region (over the R interface). It does NOT affect programming/erasing of the FLASH memory region (over the C interface). E.g., for a 512 KB / 4 Mb main region, the logical address space ranges from [0x1000:0000, 0x1007:ffff] (the highest bit if the FLASH main region is bit 18). The memory has four physical sectors: sectors 0, 1, 2 and 3. If REMAP is '0', the physical regions logical addresses are as follows: - The physical region 0: [0x1000:0000, 0x1001:ffff]. - The physical region 1: [0x1002:0000, 0x1003:ffff]. - The physical region 2: [0x1004:0000, 0x1005:ffff]. - The physical region 3: [0x1006:0000, 0x1007:ffff]. If REMAP is '1', the physical regions logical addresses are as follows: - The physical region 0: [0x1004:0000, 0x1005:ffff]. - The physical region 1: [0x1006:0000, 0x1007:ffff]. - The physical region 2: [0x1000:0000, 0x1001:ffff]. - The physical region 3: [0x1002:0000, 0x1003:ffff]. Note: when the REMAP is changed, SW should invalidate the caches and buffers.
8
9
read-write
FLASH_PWR_CTL
Flash power control
0x4
32
read-write
n
0x0
0x0
ENABLE
Controls 'enable' pin of the Flash memory.
0
1
read-write
ENABLE_HV
Controls 'enable_hv' pin of the Flash memory.
1
2
read-write
FM_ADDR
Flash macro address
0x8
32
read-write
n
0x0
0x0
AXA
Auxiliary address field: '0': regular flash memory. '1': supervisory flash memory.
24
25
read-write
BA
Bank address.
16
24
read-write
RA
Row address.
0
16
read-write
FM_CTL
Flash macro control
0x0
32
read-write
n
0x0
0x0
DAA_MUX_SEL
Direct memory cell access address.
16
23
read-write
FM_MODE
Flash macro mode selection: '0': Normal functional mode. '1': Sets 'pre-program control bit' for soft pre-program operation of all selected SONOS cells. the control bit is cleared by the HW after any program operation. '2': Sets ... '15': TBD
0
4
read-write
FM_SEQ
Flash macro sequence select: '0': TBD '1': TBD '2': TBD '3': TBD
8
10
read-write
IF_SEL
Interface selection. Specifies the interface that is used for flash memory read operations: '0': R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface. '1': C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure.
24
25
read-write
WR_EN
'0': normal mode '1': Fm Write Enable
25
26
read-write
FM_HV_DATA0
Flash macro high Voltage page latches data
0x800
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA1
Flash macro high Voltage page latches data
0x804
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA10
Flash macro high Voltage page latches data
0x828
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA100
Flash macro high Voltage page latches data
0x990
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA101
Flash macro high Voltage page latches data
0x994
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA102
Flash macro high Voltage page latches data
0x998
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA103
Flash macro high Voltage page latches data
0x99C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA104
Flash macro high Voltage page latches data
0x9A0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA105
Flash macro high Voltage page latches data
0x9A4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA106
Flash macro high Voltage page latches data
0x9A8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA107
Flash macro high Voltage page latches data
0x9AC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA108
Flash macro high Voltage page latches data
0x9B0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA109
Flash macro high Voltage page latches data
0x9B4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA11
Flash macro high Voltage page latches data
0x82C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA110
Flash macro high Voltage page latches data
0x9B8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA111
Flash macro high Voltage page latches data
0x9BC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA112
Flash macro high Voltage page latches data
0x9C0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA113
Flash macro high Voltage page latches data
0x9C4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA114
Flash macro high Voltage page latches data
0x9C8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA115
Flash macro high Voltage page latches data
0x9CC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA116
Flash macro high Voltage page latches data
0x9D0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA117
Flash macro high Voltage page latches data
0x9D4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA118
Flash macro high Voltage page latches data
0x9D8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA119
Flash macro high Voltage page latches data
0x9DC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA12
Flash macro high Voltage page latches data
0x830
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA120
Flash macro high Voltage page latches data
0x9E0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA121
Flash macro high Voltage page latches data
0x9E4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA122
Flash macro high Voltage page latches data
0x9E8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA123
Flash macro high Voltage page latches data
0x9EC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA124
Flash macro high Voltage page latches data
0x9F0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA125
Flash macro high Voltage page latches data
0x9F4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA126
Flash macro high Voltage page latches data
0x9F8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA127
Flash macro high Voltage page latches data
0x9FC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA128
Flash macro high Voltage page latches data
0xA00
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA129
Flash macro high Voltage page latches data
0xA04
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA13
Flash macro high Voltage page latches data
0x834
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA130
Flash macro high Voltage page latches data
0xA08
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA131
Flash macro high Voltage page latches data
0xA0C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA132
Flash macro high Voltage page latches data
0xA10
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA133
Flash macro high Voltage page latches data
0xA14
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA134
Flash macro high Voltage page latches data
0xA18
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA135
Flash macro high Voltage page latches data
0xA1C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA136
Flash macro high Voltage page latches data
0xA20
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA137
Flash macro high Voltage page latches data
0xA24
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA138
Flash macro high Voltage page latches data
0xA28
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA139
Flash macro high Voltage page latches data
0xA2C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA14
Flash macro high Voltage page latches data
0x838
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA140
Flash macro high Voltage page latches data
0xA30
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA141
Flash macro high Voltage page latches data
0xA34
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA142
Flash macro high Voltage page latches data
0xA38
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA143
Flash macro high Voltage page latches data
0xA3C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA144
Flash macro high Voltage page latches data
0xA40
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA145
Flash macro high Voltage page latches data
0xA44
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA146
Flash macro high Voltage page latches data
0xA48
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA147
Flash macro high Voltage page latches data
0xA4C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA148
Flash macro high Voltage page latches data
0xA50
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA149
Flash macro high Voltage page latches data
0xA54
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA15
Flash macro high Voltage page latches data
0x83C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA150
Flash macro high Voltage page latches data
0xA58
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA151
Flash macro high Voltage page latches data
0xA5C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA152
Flash macro high Voltage page latches data
0xA60
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA153
Flash macro high Voltage page latches data
0xA64
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA154
Flash macro high Voltage page latches data
0xA68
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA155
Flash macro high Voltage page latches data
0xA6C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA156
Flash macro high Voltage page latches data
0xA70
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA157
Flash macro high Voltage page latches data
0xA74
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA158
Flash macro high Voltage page latches data
0xA78
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA159
Flash macro high Voltage page latches data
0xA7C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA16
Flash macro high Voltage page latches data
0x840
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA160
Flash macro high Voltage page latches data
0xA80
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA161
Flash macro high Voltage page latches data
0xA84
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA162
Flash macro high Voltage page latches data
0xA88
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA163
Flash macro high Voltage page latches data
0xA8C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA164
Flash macro high Voltage page latches data
0xA90
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA165
Flash macro high Voltage page latches data
0xA94
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA166
Flash macro high Voltage page latches data
0xA98
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA167
Flash macro high Voltage page latches data
0xA9C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA168
Flash macro high Voltage page latches data
0xAA0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA169
Flash macro high Voltage page latches data
0xAA4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA17
Flash macro high Voltage page latches data
0x844
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA170
Flash macro high Voltage page latches data
0xAA8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA171
Flash macro high Voltage page latches data
0xAAC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA172
Flash macro high Voltage page latches data
0xAB0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA173
Flash macro high Voltage page latches data
0xAB4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA174
Flash macro high Voltage page latches data
0xAB8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA175
Flash macro high Voltage page latches data
0xABC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA176
Flash macro high Voltage page latches data
0xAC0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA177
Flash macro high Voltage page latches data
0xAC4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA178
Flash macro high Voltage page latches data
0xAC8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA179
Flash macro high Voltage page latches data
0xACC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA18
Flash macro high Voltage page latches data
0x848
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA180
Flash macro high Voltage page latches data
0xAD0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA181
Flash macro high Voltage page latches data
0xAD4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA182
Flash macro high Voltage page latches data
0xAD8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA183
Flash macro high Voltage page latches data
0xADC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA184
Flash macro high Voltage page latches data
0xAE0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA185
Flash macro high Voltage page latches data
0xAE4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA186
Flash macro high Voltage page latches data
0xAE8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA187
Flash macro high Voltage page latches data
0xAEC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA188
Flash macro high Voltage page latches data
0xAF0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA189
Flash macro high Voltage page latches data
0xAF4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA19
Flash macro high Voltage page latches data
0x84C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA190
Flash macro high Voltage page latches data
0xAF8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA191
Flash macro high Voltage page latches data
0xAFC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA192
Flash macro high Voltage page latches data
0xB00
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA193
Flash macro high Voltage page latches data
0xB04
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA194
Flash macro high Voltage page latches data
0xB08
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA195
Flash macro high Voltage page latches data
0xB0C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA196
Flash macro high Voltage page latches data
0xB10
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA197
Flash macro high Voltage page latches data
0xB14
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA198
Flash macro high Voltage page latches data
0xB18
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA199
Flash macro high Voltage page latches data
0xB1C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA2
Flash macro high Voltage page latches data
0x808
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA20
Flash macro high Voltage page latches data
0x850
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA200
Flash macro high Voltage page latches data
0xB20
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA201
Flash macro high Voltage page latches data
0xB24
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA202
Flash macro high Voltage page latches data
0xB28
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA203
Flash macro high Voltage page latches data
0xB2C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA204
Flash macro high Voltage page latches data
0xB30
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA205
Flash macro high Voltage page latches data
0xB34
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA206
Flash macro high Voltage page latches data
0xB38
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA207
Flash macro high Voltage page latches data
0xB3C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA208
Flash macro high Voltage page latches data
0xB40
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA209
Flash macro high Voltage page latches data
0xB44
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA21
Flash macro high Voltage page latches data
0x854
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA210
Flash macro high Voltage page latches data
0xB48
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA211
Flash macro high Voltage page latches data
0xB4C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA212
Flash macro high Voltage page latches data
0xB50
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA213
Flash macro high Voltage page latches data
0xB54
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA214
Flash macro high Voltage page latches data
0xB58
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA215
Flash macro high Voltage page latches data
0xB5C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA216
Flash macro high Voltage page latches data
0xB60
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA217
Flash macro high Voltage page latches data
0xB64
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA218
Flash macro high Voltage page latches data
0xB68
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA219
Flash macro high Voltage page latches data
0xB6C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA22
Flash macro high Voltage page latches data
0x858
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA220
Flash macro high Voltage page latches data
0xB70
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA221
Flash macro high Voltage page latches data
0xB74
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA222
Flash macro high Voltage page latches data
0xB78
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA223
Flash macro high Voltage page latches data
0xB7C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA224
Flash macro high Voltage page latches data
0xB80
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA225
Flash macro high Voltage page latches data
0xB84
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA226
Flash macro high Voltage page latches data
0xB88
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA227
Flash macro high Voltage page latches data
0xB8C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA228
Flash macro high Voltage page latches data
0xB90
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA229
Flash macro high Voltage page latches data
0xB94
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA23
Flash macro high Voltage page latches data
0x85C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA230
Flash macro high Voltage page latches data
0xB98
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA231
Flash macro high Voltage page latches data
0xB9C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA232
Flash macro high Voltage page latches data
0xBA0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA233
Flash macro high Voltage page latches data
0xBA4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA234
Flash macro high Voltage page latches data
0xBA8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA235
Flash macro high Voltage page latches data
0xBAC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA236
Flash macro high Voltage page latches data
0xBB0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA237
Flash macro high Voltage page latches data
0xBB4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA238
Flash macro high Voltage page latches data
0xBB8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA239
Flash macro high Voltage page latches data
0xBBC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA24
Flash macro high Voltage page latches data
0x860
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA240
Flash macro high Voltage page latches data
0xBC0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA241
Flash macro high Voltage page latches data
0xBC4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA242
Flash macro high Voltage page latches data
0xBC8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA243
Flash macro high Voltage page latches data
0xBCC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA244
Flash macro high Voltage page latches data
0xBD0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA245
Flash macro high Voltage page latches data
0xBD4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA246
Flash macro high Voltage page latches data
0xBD8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA247
Flash macro high Voltage page latches data
0xBDC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA248
Flash macro high Voltage page latches data
0xBE0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA249
Flash macro high Voltage page latches data
0xBE4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA25
Flash macro high Voltage page latches data
0x864
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA250
Flash macro high Voltage page latches data
0xBE8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA251
Flash macro high Voltage page latches data
0xBEC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA252
Flash macro high Voltage page latches data
0xBF0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA253
Flash macro high Voltage page latches data
0xBF4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA254
Flash macro high Voltage page latches data
0xBF8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA255
Flash macro high Voltage page latches data
0xBFC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA26
Flash macro high Voltage page latches data
0x868
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA27
Flash macro high Voltage page latches data
0x86C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA28
Flash macro high Voltage page latches data
0x870
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA29
Flash macro high Voltage page latches data
0x874
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA3
Flash macro high Voltage page latches data
0x80C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA30
Flash macro high Voltage page latches data
0x878
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA31
Flash macro high Voltage page latches data
0x87C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA32
Flash macro high Voltage page latches data
0x880
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA33
Flash macro high Voltage page latches data
0x884
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA34
Flash macro high Voltage page latches data
0x888
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA35
Flash macro high Voltage page latches data
0x88C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA36
Flash macro high Voltage page latches data
0x890
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA37
Flash macro high Voltage page latches data
0x894
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA38
Flash macro high Voltage page latches data
0x898
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA39
Flash macro high Voltage page latches data
0x89C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA4
Flash macro high Voltage page latches data
0x810
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA40
Flash macro high Voltage page latches data
0x8A0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA41
Flash macro high Voltage page latches data
0x8A4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA42
Flash macro high Voltage page latches data
0x8A8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA43
Flash macro high Voltage page latches data
0x8AC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA44
Flash macro high Voltage page latches data
0x8B0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA45
Flash macro high Voltage page latches data
0x8B4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA46
Flash macro high Voltage page latches data
0x8B8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA47
Flash macro high Voltage page latches data
0x8BC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA48
Flash macro high Voltage page latches data
0x8C0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA49
Flash macro high Voltage page latches data
0x8C4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA5
Flash macro high Voltage page latches data
0x814
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA50
Flash macro high Voltage page latches data
0x8C8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA51
Flash macro high Voltage page latches data
0x8CC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA52
Flash macro high Voltage page latches data
0x8D0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA53
Flash macro high Voltage page latches data
0x8D4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA54
Flash macro high Voltage page latches data
0x8D8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA55
Flash macro high Voltage page latches data
0x8DC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA56
Flash macro high Voltage page latches data
0x8E0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA57
Flash macro high Voltage page latches data
0x8E4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA58
Flash macro high Voltage page latches data
0x8E8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA59
Flash macro high Voltage page latches data
0x8EC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA6
Flash macro high Voltage page latches data
0x818
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA60
Flash macro high Voltage page latches data
0x8F0
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA61
Flash macro high Voltage page latches data
0x8F4
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA62
Flash macro high Voltage page latches data
0x8F8
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA63
Flash macro high Voltage page latches data
0x8FC
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA64
Flash macro high Voltage page latches data
0x900
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA65
Flash macro high Voltage page latches data
0x904
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA66
Flash macro high Voltage page latches data
0x908
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA67
Flash macro high Voltage page latches data
0x90C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA68
Flash macro high Voltage page latches data
0x910
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA69
Flash macro high Voltage page latches data
0x914
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA7
Flash macro high Voltage page latches data
0x81C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA70
Flash macro high Voltage page latches data
0x918
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA71
Flash macro high Voltage page latches data
0x91C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA72
Flash macro high Voltage page latches data
0x920
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA73
Flash macro high Voltage page latches data
0x924
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA74
Flash macro high Voltage page latches data
0x928
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA75
Flash macro high Voltage page latches data
0x92C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA76
Flash macro high Voltage page latches data
0x930
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA77
Flash macro high Voltage page latches data
0x934
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA78
Flash macro high Voltage page latches data
0x938
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA79
Flash macro high Voltage page latches data
0x93C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA8
Flash macro high Voltage page latches data
0x820
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA80
Flash macro high Voltage page latches data
0x940
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA81
Flash macro high Voltage page latches data
0x944
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA82
Flash macro high Voltage page latches data
0x948
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA83
Flash macro high Voltage page latches data
0x94C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA84
Flash macro high Voltage page latches data
0x950
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA85
Flash macro high Voltage page latches data
0x954
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA86
Flash macro high Voltage page latches data
0x958
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA87
Flash macro high Voltage page latches data
0x95C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA88
Flash macro high Voltage page latches data
0x960
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA89
Flash macro high Voltage page latches data
0x964
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA9
Flash macro high Voltage page latches data
0x824
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA90
Flash macro high Voltage page latches data
0x968
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA91
Flash macro high Voltage page latches data
0x96C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA92
Flash macro high Voltage page latches data
0x970
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA93
Flash macro high Voltage page latches data
0x974
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA94
Flash macro high Voltage page latches data
0x978
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA95
Flash macro high Voltage page latches data
0x97C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA96
Flash macro high Voltage page latches data
0x980
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA97
Flash macro high Voltage page latches data
0x984
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA98
Flash macro high Voltage page latches data
0x988
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA99
Flash macro high Voltage page latches data
0x98C
32
read-write
n
0x0
0x0
DATA32
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality.
0
32
read-write
FM_HV_DATA_ALL
Flash macro high Voltage page latches data (for all page latches)
0x4C
32
write-only
n
0x0
0x0
DATA32
Write all high Voltage page latches with the same 32-bit data in a single write cycle
0
32
write-only
FM_MEM_DATA0
Flash macro memory sense amplifier and column decoder data
0xC00
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA1
Flash macro memory sense amplifier and column decoder data
0xC04
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA10
Flash macro memory sense amplifier and column decoder data
0xC28
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA100
Flash macro memory sense amplifier and column decoder data
0xD90
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA101
Flash macro memory sense amplifier and column decoder data
0xD94
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA102
Flash macro memory sense amplifier and column decoder data
0xD98
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA103
Flash macro memory sense amplifier and column decoder data
0xD9C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA104
Flash macro memory sense amplifier and column decoder data
0xDA0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA105
Flash macro memory sense amplifier and column decoder data
0xDA4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA106
Flash macro memory sense amplifier and column decoder data
0xDA8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA107
Flash macro memory sense amplifier and column decoder data
0xDAC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA108
Flash macro memory sense amplifier and column decoder data
0xDB0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA109
Flash macro memory sense amplifier and column decoder data
0xDB4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA11
Flash macro memory sense amplifier and column decoder data
0xC2C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA110
Flash macro memory sense amplifier and column decoder data
0xDB8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA111
Flash macro memory sense amplifier and column decoder data
0xDBC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA112
Flash macro memory sense amplifier and column decoder data
0xDC0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA113
Flash macro memory sense amplifier and column decoder data
0xDC4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA114
Flash macro memory sense amplifier and column decoder data
0xDC8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA115
Flash macro memory sense amplifier and column decoder data
0xDCC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA116
Flash macro memory sense amplifier and column decoder data
0xDD0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA117
Flash macro memory sense amplifier and column decoder data
0xDD4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA118
Flash macro memory sense amplifier and column decoder data
0xDD8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA119
Flash macro memory sense amplifier and column decoder data
0xDDC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA12
Flash macro memory sense amplifier and column decoder data
0xC30
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA120
Flash macro memory sense amplifier and column decoder data
0xDE0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA121
Flash macro memory sense amplifier and column decoder data
0xDE4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA122
Flash macro memory sense amplifier and column decoder data
0xDE8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA123
Flash macro memory sense amplifier and column decoder data
0xDEC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA124
Flash macro memory sense amplifier and column decoder data
0xDF0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA125
Flash macro memory sense amplifier and column decoder data
0xDF4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA126
Flash macro memory sense amplifier and column decoder data
0xDF8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA127
Flash macro memory sense amplifier and column decoder data
0xDFC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA128
Flash macro memory sense amplifier and column decoder data
0xE00
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA129
Flash macro memory sense amplifier and column decoder data
0xE04
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA13
Flash macro memory sense amplifier and column decoder data
0xC34
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA130
Flash macro memory sense amplifier and column decoder data
0xE08
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA131
Flash macro memory sense amplifier and column decoder data
0xE0C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA132
Flash macro memory sense amplifier and column decoder data
0xE10
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA133
Flash macro memory sense amplifier and column decoder data
0xE14
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA134
Flash macro memory sense amplifier and column decoder data
0xE18
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA135
Flash macro memory sense amplifier and column decoder data
0xE1C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA136
Flash macro memory sense amplifier and column decoder data
0xE20
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA137
Flash macro memory sense amplifier and column decoder data
0xE24
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA138
Flash macro memory sense amplifier and column decoder data
0xE28
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA139
Flash macro memory sense amplifier and column decoder data
0xE2C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA14
Flash macro memory sense amplifier and column decoder data
0xC38
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA140
Flash macro memory sense amplifier and column decoder data
0xE30
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA141
Flash macro memory sense amplifier and column decoder data
0xE34
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA142
Flash macro memory sense amplifier and column decoder data
0xE38
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA143
Flash macro memory sense amplifier and column decoder data
0xE3C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA144
Flash macro memory sense amplifier and column decoder data
0xE40
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA145
Flash macro memory sense amplifier and column decoder data
0xE44
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA146
Flash macro memory sense amplifier and column decoder data
0xE48
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA147
Flash macro memory sense amplifier and column decoder data
0xE4C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA148
Flash macro memory sense amplifier and column decoder data
0xE50
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA149
Flash macro memory sense amplifier and column decoder data
0xE54
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA15
Flash macro memory sense amplifier and column decoder data
0xC3C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA150
Flash macro memory sense amplifier and column decoder data
0xE58
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA151
Flash macro memory sense amplifier and column decoder data
0xE5C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA152
Flash macro memory sense amplifier and column decoder data
0xE60
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA153
Flash macro memory sense amplifier and column decoder data
0xE64
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA154
Flash macro memory sense amplifier and column decoder data
0xE68
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA155
Flash macro memory sense amplifier and column decoder data
0xE6C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA156
Flash macro memory sense amplifier and column decoder data
0xE70
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA157
Flash macro memory sense amplifier and column decoder data
0xE74
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA158
Flash macro memory sense amplifier and column decoder data
0xE78
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA159
Flash macro memory sense amplifier and column decoder data
0xE7C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA16
Flash macro memory sense amplifier and column decoder data
0xC40
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA160
Flash macro memory sense amplifier and column decoder data
0xE80
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA161
Flash macro memory sense amplifier and column decoder data
0xE84
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA162
Flash macro memory sense amplifier and column decoder data
0xE88
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA163
Flash macro memory sense amplifier and column decoder data
0xE8C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA164
Flash macro memory sense amplifier and column decoder data
0xE90
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA165
Flash macro memory sense amplifier and column decoder data
0xE94
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA166
Flash macro memory sense amplifier and column decoder data
0xE98
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA167
Flash macro memory sense amplifier and column decoder data
0xE9C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA168
Flash macro memory sense amplifier and column decoder data
0xEA0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA169
Flash macro memory sense amplifier and column decoder data
0xEA4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA17
Flash macro memory sense amplifier and column decoder data
0xC44
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA170
Flash macro memory sense amplifier and column decoder data
0xEA8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA171
Flash macro memory sense amplifier and column decoder data
0xEAC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA172
Flash macro memory sense amplifier and column decoder data
0xEB0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA173
Flash macro memory sense amplifier and column decoder data
0xEB4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA174
Flash macro memory sense amplifier and column decoder data
0xEB8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA175
Flash macro memory sense amplifier and column decoder data
0xEBC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA176
Flash macro memory sense amplifier and column decoder data
0xEC0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA177
Flash macro memory sense amplifier and column decoder data
0xEC4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA178
Flash macro memory sense amplifier and column decoder data
0xEC8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA179
Flash macro memory sense amplifier and column decoder data
0xECC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA18
Flash macro memory sense amplifier and column decoder data
0xC48
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA180
Flash macro memory sense amplifier and column decoder data
0xED0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA181
Flash macro memory sense amplifier and column decoder data
0xED4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA182
Flash macro memory sense amplifier and column decoder data
0xED8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA183
Flash macro memory sense amplifier and column decoder data
0xEDC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA184
Flash macro memory sense amplifier and column decoder data
0xEE0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA185
Flash macro memory sense amplifier and column decoder data
0xEE4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA186
Flash macro memory sense amplifier and column decoder data
0xEE8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA187
Flash macro memory sense amplifier and column decoder data
0xEEC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA188
Flash macro memory sense amplifier and column decoder data
0xEF0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA189
Flash macro memory sense amplifier and column decoder data
0xEF4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA19
Flash macro memory sense amplifier and column decoder data
0xC4C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA190
Flash macro memory sense amplifier and column decoder data
0xEF8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA191
Flash macro memory sense amplifier and column decoder data
0xEFC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA192
Flash macro memory sense amplifier and column decoder data
0xF00
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA193
Flash macro memory sense amplifier and column decoder data
0xF04
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA194
Flash macro memory sense amplifier and column decoder data
0xF08
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA195
Flash macro memory sense amplifier and column decoder data
0xF0C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA196
Flash macro memory sense amplifier and column decoder data
0xF10
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA197
Flash macro memory sense amplifier and column decoder data
0xF14
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA198
Flash macro memory sense amplifier and column decoder data
0xF18
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA199
Flash macro memory sense amplifier and column decoder data
0xF1C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA2
Flash macro memory sense amplifier and column decoder data
0xC08
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA20
Flash macro memory sense amplifier and column decoder data
0xC50
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA200
Flash macro memory sense amplifier and column decoder data
0xF20
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA201
Flash macro memory sense amplifier and column decoder data
0xF24
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA202
Flash macro memory sense amplifier and column decoder data
0xF28
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA203
Flash macro memory sense amplifier and column decoder data
0xF2C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA204
Flash macro memory sense amplifier and column decoder data
0xF30
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA205
Flash macro memory sense amplifier and column decoder data
0xF34
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA206
Flash macro memory sense amplifier and column decoder data
0xF38
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA207
Flash macro memory sense amplifier and column decoder data
0xF3C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA208
Flash macro memory sense amplifier and column decoder data
0xF40
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA209
Flash macro memory sense amplifier and column decoder data
0xF44
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA21
Flash macro memory sense amplifier and column decoder data
0xC54
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA210
Flash macro memory sense amplifier and column decoder data
0xF48
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA211
Flash macro memory sense amplifier and column decoder data
0xF4C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA212
Flash macro memory sense amplifier and column decoder data
0xF50
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA213
Flash macro memory sense amplifier and column decoder data
0xF54
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA214
Flash macro memory sense amplifier and column decoder data
0xF58
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA215
Flash macro memory sense amplifier and column decoder data
0xF5C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA216
Flash macro memory sense amplifier and column decoder data
0xF60
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA217
Flash macro memory sense amplifier and column decoder data
0xF64
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA218
Flash macro memory sense amplifier and column decoder data
0xF68
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA219
Flash macro memory sense amplifier and column decoder data
0xF6C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA22
Flash macro memory sense amplifier and column decoder data
0xC58
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA220
Flash macro memory sense amplifier and column decoder data
0xF70
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA221
Flash macro memory sense amplifier and column decoder data
0xF74
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA222
Flash macro memory sense amplifier and column decoder data
0xF78
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA223
Flash macro memory sense amplifier and column decoder data
0xF7C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA224
Flash macro memory sense amplifier and column decoder data
0xF80
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA225
Flash macro memory sense amplifier and column decoder data
0xF84
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA226
Flash macro memory sense amplifier and column decoder data
0xF88
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA227
Flash macro memory sense amplifier and column decoder data
0xF8C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA228
Flash macro memory sense amplifier and column decoder data
0xF90
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA229
Flash macro memory sense amplifier and column decoder data
0xF94
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA23
Flash macro memory sense amplifier and column decoder data
0xC5C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA230
Flash macro memory sense amplifier and column decoder data
0xF98
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA231
Flash macro memory sense amplifier and column decoder data
0xF9C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA232
Flash macro memory sense amplifier and column decoder data
0xFA0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA233
Flash macro memory sense amplifier and column decoder data
0xFA4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA234
Flash macro memory sense amplifier and column decoder data
0xFA8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA235
Flash macro memory sense amplifier and column decoder data
0xFAC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA236
Flash macro memory sense amplifier and column decoder data
0xFB0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA237
Flash macro memory sense amplifier and column decoder data
0xFB4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA238
Flash macro memory sense amplifier and column decoder data
0xFB8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA239
Flash macro memory sense amplifier and column decoder data
0xFBC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA24
Flash macro memory sense amplifier and column decoder data
0xC60
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA240
Flash macro memory sense amplifier and column decoder data
0xFC0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA241
Flash macro memory sense amplifier and column decoder data
0xFC4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA242
Flash macro memory sense amplifier and column decoder data
0xFC8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA243
Flash macro memory sense amplifier and column decoder data
0xFCC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA244
Flash macro memory sense amplifier and column decoder data
0xFD0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA245
Flash macro memory sense amplifier and column decoder data
0xFD4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA246
Flash macro memory sense amplifier and column decoder data
0xFD8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA247
Flash macro memory sense amplifier and column decoder data
0xFDC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA248
Flash macro memory sense amplifier and column decoder data
0xFE0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA249
Flash macro memory sense amplifier and column decoder data
0xFE4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA25
Flash macro memory sense amplifier and column decoder data
0xC64
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA250
Flash macro memory sense amplifier and column decoder data
0xFE8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA251
Flash macro memory sense amplifier and column decoder data
0xFEC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA252
Flash macro memory sense amplifier and column decoder data
0xFF0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA253
Flash macro memory sense amplifier and column decoder data
0xFF4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA254
Flash macro memory sense amplifier and column decoder data
0xFF8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA255
Flash macro memory sense amplifier and column decoder data
0xFFC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA26
Flash macro memory sense amplifier and column decoder data
0xC68
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA27
Flash macro memory sense amplifier and column decoder data
0xC6C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA28
Flash macro memory sense amplifier and column decoder data
0xC70
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA29
Flash macro memory sense amplifier and column decoder data
0xC74
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA3
Flash macro memory sense amplifier and column decoder data
0xC0C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA30
Flash macro memory sense amplifier and column decoder data
0xC78
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA31
Flash macro memory sense amplifier and column decoder data
0xC7C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA32
Flash macro memory sense amplifier and column decoder data
0xC80
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA33
Flash macro memory sense amplifier and column decoder data
0xC84
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA34
Flash macro memory sense amplifier and column decoder data
0xC88
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA35
Flash macro memory sense amplifier and column decoder data
0xC8C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA36
Flash macro memory sense amplifier and column decoder data
0xC90
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA37
Flash macro memory sense amplifier and column decoder data
0xC94
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA38
Flash macro memory sense amplifier and column decoder data
0xC98
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA39
Flash macro memory sense amplifier and column decoder data
0xC9C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA4
Flash macro memory sense amplifier and column decoder data
0xC10
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA40
Flash macro memory sense amplifier and column decoder data
0xCA0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA41
Flash macro memory sense amplifier and column decoder data
0xCA4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA42
Flash macro memory sense amplifier and column decoder data
0xCA8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA43
Flash macro memory sense amplifier and column decoder data
0xCAC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA44
Flash macro memory sense amplifier and column decoder data
0xCB0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA45
Flash macro memory sense amplifier and column decoder data
0xCB4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA46
Flash macro memory sense amplifier and column decoder data
0xCB8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA47
Flash macro memory sense amplifier and column decoder data
0xCBC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA48
Flash macro memory sense amplifier and column decoder data
0xCC0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA49
Flash macro memory sense amplifier and column decoder data
0xCC4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA5
Flash macro memory sense amplifier and column decoder data
0xC14
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA50
Flash macro memory sense amplifier and column decoder data
0xCC8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA51
Flash macro memory sense amplifier and column decoder data
0xCCC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA52
Flash macro memory sense amplifier and column decoder data
0xCD0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA53
Flash macro memory sense amplifier and column decoder data
0xCD4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA54
Flash macro memory sense amplifier and column decoder data
0xCD8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA55
Flash macro memory sense amplifier and column decoder data
0xCDC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA56
Flash macro memory sense amplifier and column decoder data
0xCE0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA57
Flash macro memory sense amplifier and column decoder data
0xCE4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA58
Flash macro memory sense amplifier and column decoder data
0xCE8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA59
Flash macro memory sense amplifier and column decoder data
0xCEC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA6
Flash macro memory sense amplifier and column decoder data
0xC18
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA60
Flash macro memory sense amplifier and column decoder data
0xCF0
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA61
Flash macro memory sense amplifier and column decoder data
0xCF4
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA62
Flash macro memory sense amplifier and column decoder data
0xCF8
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA63
Flash macro memory sense amplifier and column decoder data
0xCFC
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA64
Flash macro memory sense amplifier and column decoder data
0xD00
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA65
Flash macro memory sense amplifier and column decoder data
0xD04
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA66
Flash macro memory sense amplifier and column decoder data
0xD08
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA67
Flash macro memory sense amplifier and column decoder data
0xD0C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA68
Flash macro memory sense amplifier and column decoder data
0xD10
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA69
Flash macro memory sense amplifier and column decoder data
0xD14
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA7
Flash macro memory sense amplifier and column decoder data
0xC1C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA70
Flash macro memory sense amplifier and column decoder data
0xD18
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA71
Flash macro memory sense amplifier and column decoder data
0xD1C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA72
Flash macro memory sense amplifier and column decoder data
0xD20
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA73
Flash macro memory sense amplifier and column decoder data
0xD24
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA74
Flash macro memory sense amplifier and column decoder data
0xD28
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA75
Flash macro memory sense amplifier and column decoder data
0xD2C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA76
Flash macro memory sense amplifier and column decoder data
0xD30
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA77
Flash macro memory sense amplifier and column decoder data
0xD34
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA78
Flash macro memory sense amplifier and column decoder data
0xD38
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA79
Flash macro memory sense amplifier and column decoder data
0xD3C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA8
Flash macro memory sense amplifier and column decoder data
0xC20
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA80
Flash macro memory sense amplifier and column decoder data
0xD40
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA81
Flash macro memory sense amplifier and column decoder data
0xD44
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA82
Flash macro memory sense amplifier and column decoder data
0xD48
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA83
Flash macro memory sense amplifier and column decoder data
0xD4C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA84
Flash macro memory sense amplifier and column decoder data
0xD50
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA85
Flash macro memory sense amplifier and column decoder data
0xD54
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA86
Flash macro memory sense amplifier and column decoder data
0xD58
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA87
Flash macro memory sense amplifier and column decoder data
0xD5C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA88
Flash macro memory sense amplifier and column decoder data
0xD60
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA89
Flash macro memory sense amplifier and column decoder data
0xD64
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA9
Flash macro memory sense amplifier and column decoder data
0xC24
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA90
Flash macro memory sense amplifier and column decoder data
0xD68
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA91
Flash macro memory sense amplifier and column decoder data
0xD6C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA92
Flash macro memory sense amplifier and column decoder data
0xD70
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA93
Flash macro memory sense amplifier and column decoder data
0xD74
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA94
Flash macro memory sense amplifier and column decoder data
0xD78
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA95
Flash macro memory sense amplifier and column decoder data
0xD7C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA96
Flash macro memory sense amplifier and column decoder data
0xD80
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA97
Flash macro memory sense amplifier and column decoder data
0xD84
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA98
Flash macro memory sense amplifier and column decoder data
0xD88
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
FM_MEM_DATA99
Flash macro memory sense amplifier and column decoder data
0xD8C
32
read-only
n
0x0
0x0
DATA32
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is '0': data as specified by the R interface address - IF_SEL is '1': data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.
0
32
read-only
GEOMETRY
Regular flash geometry
0xC
32
read-only
n
0x0
0x0
BANK_COUNT
Number of banks (minus 1): '0': 1 bank '1': 2 banks ... '255': 256 banks
24
32
read-only
PAGE_SIZE_LOG2
Number of Bytes per page (log 2): '0': 1 Byte '1': 2 Bytes '2': 4 Bytes ... '15': 32768 Bytes The currently planned flash macros have a page size of either 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively.
4
8
read-only
ROW_COUNT
Number of rows (minus 1): '0': 1 row '1': 2 rows '2': 3 rows ... '65535': 65536 rows
8
24
read-only
WORD_SIZE_LOG2
Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access: '0': 1 Byte '1': 2 Bytes '2': 4 Bytes ... '7': 128 Bytes The currently planned flash macros have a word size of either 32-bit, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively.
0
4
read-only
GEOMETRY_GEN
N/A, DNU
0x20
32
read-only
n
0x0
0x0
DNU_0X20_1
N/A
1
2
read-only
DNU_0X20_2
N/A
2
3
read-only
DNU_0X20_3
N/A
3
4
read-only
GEOMETRY_SUPERVISORY
Supervisory flash geometry
0x10
32
read-only
n
0x0
0x0
BANK_COUNT
Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT.
24
32
read-only
PAGE_SIZE_LOG2
Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2.
4
8
read-only
ROW_COUNT
Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT
8
24
read-only
WORD_SIZE_LOG2
Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2.
0
4
read-only
HV_CTL
High voltage control
0x34
32
read-write
n
0x0
0x0
TIMER_CLOCK_FREQ
Specifies the frequency in MHz of the timer clock 'clk_t' as provide to the flash macro. E.g., if '4', the timer clock 'clk_t' has a frequency of 4 MHz.
0
8
read-write
INTR
Interrupt
0x3C
32
read-write
n
0x0
0x0
TIMER_EXPIRED
Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit.
0
1
read-write
INTR_MASK
Interrupt mask
0x44
32
read-write
n
0x0
0x0
TIMER_EXPIRED
Mask for corresponding field in INTR register.
0
1
read-write
INTR_MASKED
Interrupt masked
0x48
32
read-only
n
0x0
0x0
TIMER_EXPIRED
Logical and of corresponding request and mask fields.
0
1
read-only
INTR_SET
Interrupt set
0x40
32
read-write
n
0x0
0x0
TIMER_EXPIRED
Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).
0
1
read-write
MONITOR_STATUS
Monitor Status
0x2C
32
read-only
n
0x0
0x0
NEG_PUMP_VHI
NEG pump VHI
2
3
read-only
POS_PUMP_VLO
POS pump VLO
1
2
read-only
RED_CTL01
Redundancy Control normal sectors 0,1
0x80
32
read-write
n
0x0
0x0
RED_ADDR_0
Bad Row Pair Address for Sector 0
0
8
read-write
RED_ADDR_1
Bad Row Pair Address for Sector 1
16
24
read-write
RED_EN_0
'1': Redundancy Enable for Sector 0
8
9
read-write
RED_EN_1
'1': Redundancy Enable for Sector 1
24
25
read-write
RED_CTL23
Redundancy Controll normal sectors 2,3
0x84
32
read-write
n
0x0
0x0
RED_ADDR_2
Bad Row Pair Address for Sector 2
0
8
read-write
RED_ADDR_3
Bad Row Pair Address for Sector 3
16
24
read-write
RED_EN_2
1': Redundancy Enable for Sector 2
8
9
read-write
RED_EN_3
1': Redundancy Enable for Sector 3
24
25
read-write
RED_CTL45
Redundancy Controll normal sectors 4,5
0x88
32
read-write
n
0x0
0x0
DNU_45_1
Not Used
0
1
read-write
DNU_45_23_16
Not Used
16
24
read-write
DNU_45_3
Not Used
2
3
read-write
DNU_45_5
Not Used
4
5
read-write
DNU_45_6
Not Used
6
7
read-write
DNU_45_8
Not Used
8
9
read-write
FDIV_TRIM_HV_0
'2b00' F = 1MHz see fdiv_trim_hv<1> value as well '2b01' F = 0.5MHz '2b10' F = 2MHz '2b11' F = 4Mhz
3
4
read-write
FDIV_TRIM_HV_1
'2b00' F = 1MHz see fdiv_trim_hv<0> value as well '2b01' F = 0.5MHz '2b10' F = 2MHz '2b11' F = 4Mhz
5
6
read-write
REG_ACT_HV
Forces the VBST regulator in active mode all the time
1
2
read-write
VLIM_TRIM_HV_0
'2b00' V2 = 650mV see vlim_trim_hv<1> value as well '2b01' V2 = 600mV '2b10' V2 = 750mV '2b11' V2 = 700mV
7
8
read-write
RED_CTL67
Redundancy Controll normal sectors 6,7
0x8C
32
read-write
n
0x0
0x0
DNU_67_1
Not Used
1
2
read-write
DNU_67_23_16
Not Used
16
24
read-write
DNU_67_3
Not Used
3
4
read-write
DNU_67_5
Not Used
5
6
read-write
DNU_67_7
Not Used
7
8
read-write
IPREF_TC_HV
Reduces the IPREF Tempco by not subtracting ICREF form IPREF - IPREF will be 1uA
4
5
read-write
IPREF_TRIMA_HI_HV
Adds 200-300nA boost on IPREF_HI
6
7
read-write
IPREF_TRIMA_LO_HV
Adds 200-300nA boost on IPREF_LO
8
9
read-write
VLIM_TRIM_HV_1
'2b00' V2 = 650mV see vlim_trim_hv<0> value as well '2b01' V2 = 600mV '2b10' V2 = 750mV '2b11' V2 = 700mV
0
1
read-write
VPROT_ACT_HV
Forces VPROT in active mode all the time
2
3
read-write
RED_CTL_SM01
Redundancy Controll special sectors 0,1
0x90
32
read-write
n
0x0
0x0
RED_ADDR_SM0
Bad Row Pair Address for Special Sector 0
0
8
read-write
RED_ADDR_SM1
Bad Row Pair Address for Special Sector 1
16
24
read-write
RED_EN_SM0
Redundancy Enable for Special Sector 0
8
9
read-write
RED_EN_SM1
Redundancy Enable for Special Sector 1
24
25
read-write
R_GRANT_EN
'0': r_grant handshake disabled, r_grant always 1. '1': r_grand handshake enabled
31
32
read-write
TRKD
Sense Amp Control tracking delay
30
31
read-write
SCRATCH_CTL
Scratch Control
0x30
32
read-write
n
0x0
0x0
DUMMY32
Scratchpad register fields. Provided for test purposes.
0
32
read-write
STATUS
Status
0x4
32
read-only
n
0x0
0x0
HV_REGS_ISOLATED
Indicates the isolation status at HV trim and redundancy registers inputs '0' - Not isolated, writing permitted '1' - isolated writing disabled
1
2
read-only
HV_TIMER_RUNNING
Indicates if the high voltage timer is running: '0': not running '1': running
0
1
read-only
IF_SEL_MON
FM_CTL.IF_SEL bit after being synchronized in clk_r domain
5
6
read-only
ILLEGAL_HVOP
Indicates a bulk, sector erase, program has been requested when axa=1 '0' - no error '1' - illegal HV operation error
2
3
read-only
TURBO_N
After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.. Used in the testchip boot only as an 'FM READY' flag. '0' - turbo mode '1' - normal mode
3
4
read-only
WR_EN_MON
FM_CTL.WR_EN bit after being synchronized in clk_r domain
4
5
read-only
TEST_CTL
Test mode control
0x24
32
read-write
n
0x0
0x0
CSL_DEBUG
Engineering Debug Register
17
18
read-write
ENABLE_OSC
0': the oscillator enable logic has control over the internal oscillator '1': forces oscillator enable HI
18
19
read-write
EN_CLK_MON
1: enables the oscillator output monitor
16
17
read-write
PN_CTL
Positive/negative margin mode control: '0': negative margin control '1': positive margin control
8
9
read-write
TEST_MODE
Test mode control: '0'-'31': TBD
0
5
read-write
TM_DISNEG
Test mode negative pump disable
11
12
read-write
TM_DISPOS
Test mode positive pump disable
10
11
read-write
TM_PE
PUMP_EN override: Pump Enable =PUMP_EN | PE_TM
9
10
read-write
UNSCRAMBLE_WA
See BSN-242 memo '0': normal '1': disables the Word Address scrambling
31
32
read-write
TIMER_CTL
Timer control
0x14
32
read-write
n
0x0
0x0
ACLK_EN
ACLK enable (generates a single cycle pulse for the FM): '0': disabled '1': enabled. SW set this field to '1' to generate a single cycle pulse. HW sets this field to '0' when the pulse is generated.
30
31
read-write
PERIOD
Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples.
0
16
read-write
PRE_PROG
'1' during pre-program operation
25
26
read-write
PRE_PROG_CSL
'0' CSL lines driven by CSL_DAC '1' CSL lines driven by VNEG_G
26
27
read-write
PUMP_CLOCK_SEL
Pump clock select: '0': internal clock. '1': external clock.
24
25
read-write
PUMP_EN
Pump enable: '0': disabled '1': enabled (also requires FM_CTL.IF_SEL to be '1', this additional restriction is required to prevent non intentional clearing of the FM). SW sets this field to '1' to generate a single PE pulse. HW clears this field when timer is expired.
29
30
read-write
SCALE
Timer tick scale: '0': 1 microsecond. '1': 100 microseconds.
16
17
read-write
TIMER_EN
Timer enable: '0': disabled '1': enabled. SW sets this field to '1' to start the timer. HW sets this field to '0' when the timer is expired.
31
32
read-write
TM_CMPR0
Do Not Use
0x100
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR1
Do Not Use
0x104
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR10
Do Not Use
0x128
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR11
Do Not Use
0x12C
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR12
Do Not Use
0x130
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR13
Do Not Use
0x134
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR14
Do Not Use
0x138
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR15
Do Not Use
0x13C
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR16
Do Not Use
0x140
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR17
Do Not Use
0x144
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR18
Do Not Use
0x148
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR19
Do Not Use
0x14C
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR2
Do Not Use
0x108
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR20
Do Not Use
0x150
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR21
Do Not Use
0x154
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR22
Do Not Use
0x158
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR23
Do Not Use
0x15C
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR24
Do Not Use
0x160
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR25
Do Not Use
0x164
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR26
Do Not Use
0x168
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR27
Do Not Use
0x16C
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR28
Do Not Use
0x170
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR29
Do Not Use
0x174
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR3
Do Not Use
0x10C
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR30
Do Not Use
0x178
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR31
Do Not Use
0x17C
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR4
Do Not Use
0x110
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR5
Do Not Use
0x114
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR6
Do Not Use
0x118
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR7
Do Not Use
0x11C
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR8
Do Not Use
0x120
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
TM_CMPR9
Do Not Use
0x124
32
read-only
n
0x0
0x0
DATA_COMP_RESULT
The result of a comparison between the flash macro data output and the content of the high voltage page latches. The comparison result for a given column 'Column_Number' is updated in this register field on a read to address: 0x100+4*Column_Number. The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD. '0': FALSE (not equal) '1': TRUE (equal)
0
1
read-only
WAIT_CTL
Wiat State control
0x28
32
read-write
n
0x0
0x0
WAIT_FM_HV_RD
Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches. Common for reading HV Page Latches and the DATA_COMP_RESULT bit
8
12
read-write
WAIT_FM_HV_WR
Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches.
16
19
read-write
WAIT_FM_MEM_RD
Number of C interface wait cycles (on 'clk_c') for a read from the memory
0
4
read-write
IPC
IPC
IPC
0x0
0x0
0x10000
registers
n
ACQUIRE
IPC acquire
0x0
32
read-only
n
0x0
0x0
MS
This field specifies the bus master identifier that successfully acquired the lock.
8
12
read-only
NS
Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the access that successfully acquired the lock.
1
2
read-only
P
User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the access that successfully acquired the lock.
0
1
read-only
PC
This field specifies the protection context that successfully acquired the lock.
4
8
read-only
SUCCESS
Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).
31
32
read-only
DATA
IPC data
0xC
32
read-write
n
0x0
0x0
DATA
This field holds a 32-bit data element that is associated with the IPC structure.
0
32
read-write
INTR
Interrupt
0x0
32
read-write
n
0x0
0x0
NOTIFY
These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
16
32
read-write
RELEASE
These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.
0
16
read-write
INTR_MASK
Interrupt mask
0x8
32
read-write
n
0x0
0x0
NOTIFY
Mask bit for corresponding field in the INTR register.
16
32
read-write
RELEASE
Mask bit for corresponding field in the INTR register.
0
16
read-write
INTR_MASKED
Interrupt masked
0xC
32
read-only
n
0x0
0x0
NOTIFY
Logical and of corresponding INTR and INTR_MASK fields.
16
32
read-only
RELEASE
Logical and of corresponding request and mask bits.
0
16
read-only
INTR_SET
Interrupt set
0x4
32
read-write
n
0x0
0x0
NOTIFY
SW writes a '1' to this field to set the corresponding field in the INTR register.
16
32
read-write
RELEASE
SW writes a '1' to this field to set the corresponding field in the INTR register.
0
16
read-write
LOCK_STATUS
IPC lock status
0x10
32
read-only
n
0x0
0x0
ACQUIRED
Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1').
31
32
read-only
MS
This field specifies the bus master identifier that successfully acquired the lock.
8
12
read-only
NS
This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure.
1
2
read-only
P
This field specifies the user/privileged access control: '0': user mode. '1': privileged mode.
0
1
read-only
PC
This field specifies the protection context that successfully acquired the lock.
4
8
read-only
NOTIFY
IPC notification
0x8
32
write-only
n
0x0
0x0
INTR_NOTIFY
This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.
0
16
write-only
RELEASE
IPC release
0x4
32
write-only
n
0x0
0x0
INTR_RELEASE
This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field. As a side effect, a write to this register will always set LOCK_STATUS.ACQUIRED to '0' (even when no release event is generated i.e. the written data is '0').
0
16
write-only
PERI
Peripheral interconnect
PERI
0x0
0x0
0x10000
registers
n
ADDR0
PPU region address 0 (slave structure)
0x0
32
read-only
n
0x0
0x0
ADDR24
See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': address of protected region. Note: this field is read-only. Its value is chip specific.
8
32
read-only
SUBREGION_DISABLE
See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
0
8
read-only
ADDR1
PPU region address 1 (master structure)
0x20
32
read-only
n
0x0
0x0
ADDR24
See corresponding field for PPU structure with programmable address. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
8
32
read-only
SUBREGION_DISABLE
See corresponding field for PPU structure with programmable address. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
0
8
read-only
ATT0
PPU region attributes 0 (slave structure)
0x4
32
read-write
n
0x0
0x0
ENABLED
See corresponding field for PPU structure with programmable address.
31
32
read-write
NS
See corresponding field for PPU structure with programmable address.
6
7
read-write
PC_MASK_0
See corresponding field for PPU structure with programmable address.
8
9
read-only
PC_MASK_15_TO_1
See corresponding field for PPU structure with programmable address.
9
24
read-write
PC_MATCH
See corresponding field for PPU structure with programmable address.
30
31
read-write
PR
See corresponding field for PPU structure with programmable address.
3
4
read-write
PW
See corresponding field for PPU structure with programmable address.
4
5
read-write
PX
See corresponding field for PPU structure with programmable address. Note that this register is constant '1' i.e. user execute accesses are ALWAYS allowed.
5
6
read-only
REGION_SIZE
See corresponding field for PPU structure with programmable address. Note: this field is read-only. Its value is chip specific.
24
29
read-only
UR
See corresponding field for PPU structure with programmable address.
0
1
read-write
UW
See corresponding field for PPU structure with programmable address.
1
2
read-write
UX
See corresponding field for PPU structure with programmable address. Note that this register is constant '1' i.e. user execute accesses are ALWAYS allowed.
2
3
read-only
ATT1
PPU region attributes 1 (master structure)
0x24
32
read-write
n
0x0
0x0
ENABLED
See corresponding field for PPU structure with programmable address.
31
32
read-write
NS
See corresponding field for PPU structure with programmable address.
6
7
read-write
PC_MASK_0
See corresponding field for PPU structure with programmable address.
8
9
read-only
PC_MASK_15_TO_1
See corresponding field for PPU structure with programmable address.
9
24
read-write
PC_MATCH
See corresponding field for PPU structure with programmable address.
30
31
read-write
PR
See corresponding field for PPU structure with programmable address. Note that this register is constant '1' i.e. privileged read accesses are ALWAYS allowed.
3
4
read-only
PW
See corresponding field for PPU structure with programmable address.
4
5
read-write
PX
See corresponding field for PPU structure with programmable address. Note that this register is constant '0' i.e. privileged execute accesses are NEVER allowed.
5
6
read-only
REGION_SIZE
See corresponding field for PPU structure with programmable address. '7': 256 B region
24
29
read-only
UR
See corresponding field for PPU structure with programmable address. Note that this register is constant '1' i.e. user read accesses are ALWAYS allowed.
0
1
read-only
UW
See corresponding field for PPU structure with programmable address.
1
2
read-write
UX
See corresponding field for PPU structure with programmable address. Note that this register is constant '0' i.e. user execute accesses are NEVER allowed.
2
3
read-only
CLOCK_CTL
Clock control
0x0
32
read-write
n
0x0
0x0
INT8_DIV
Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
CLOCK_CTL0
Clock control register
0xC00
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL1
Clock control register
0xC04
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL10
Clock control register
0xC28
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL100
Clock control register
0xD90
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL101
Clock control register
0xD94
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL102
Clock control register
0xD98
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL103
Clock control register
0xD9C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL104
Clock control register
0xDA0
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL105
Clock control register
0xDA4
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL106
Clock control register
0xDA8
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL107
Clock control register
0xDAC
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL108
Clock control register
0xDB0
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL109
Clock control register
0xDB4
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL11
Clock control register
0xC2C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL110
Clock control register
0xDB8
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL111
Clock control register
0xDBC
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL112
Clock control register
0xDC0
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL113
Clock control register
0xDC4
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL114
Clock control register
0xDC8
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL115
Clock control register
0xDCC
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL116
Clock control register
0xDD0
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL117
Clock control register
0xDD4
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL118
Clock control register
0xDD8
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL119
Clock control register
0xDDC
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL12
Clock control register
0xC30
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL120
Clock control register
0xDE0
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL121
Clock control register
0xDE4
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL122
Clock control register
0xDE8
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL123
Clock control register
0xDEC
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL124
Clock control register
0xDF0
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL125
Clock control register
0xDF4
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL126
Clock control register
0xDF8
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL127
Clock control register
0xDFC
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL13
Clock control register
0xC34
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL14
Clock control register
0xC38
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL15
Clock control register
0xC3C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL16
Clock control register
0xC40
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL17
Clock control register
0xC44
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL18
Clock control register
0xC48
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL19
Clock control register
0xC4C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL2
Clock control register
0xC08
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL20
Clock control register
0xC50
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL21
Clock control register
0xC54
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL22
Clock control register
0xC58
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL23
Clock control register
0xC5C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL24
Clock control register
0xC60
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL25
Clock control register
0xC64
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL26
Clock control register
0xC68
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL27
Clock control register
0xC6C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL28
Clock control register
0xC70
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL29
Clock control register
0xC74
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL3
Clock control register
0xC0C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL30
Clock control register
0xC78
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL31
Clock control register
0xC7C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL32
Clock control register
0xC80
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL33
Clock control register
0xC84
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL34
Clock control register
0xC88
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL35
Clock control register
0xC8C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL36
Clock control register
0xC90
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL37
Clock control register
0xC94
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL38
Clock control register
0xC98
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL39
Clock control register
0xC9C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL4
Clock control register
0xC10
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL40
Clock control register
0xCA0
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL41
Clock control register
0xCA4
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL42
Clock control register
0xCA8
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL43
Clock control register
0xCAC
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL44
Clock control register
0xCB0
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL45
Clock control register
0xCB4
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL46
Clock control register
0xCB8
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL47
Clock control register
0xCBC
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL48
Clock control register
0xCC0
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL49
Clock control register
0xCC4
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL5
Clock control register
0xC14
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL50
Clock control register
0xCC8
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL51
Clock control register
0xCCC
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL52
Clock control register
0xCD0
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL53
Clock control register
0xCD4
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL54
Clock control register
0xCD8
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL55
Clock control register
0xCDC
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL56
Clock control register
0xCE0
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL57
Clock control register
0xCE4
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL58
Clock control register
0xCE8
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL59
Clock control register
0xCEC
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL6
Clock control register
0xC18
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL60
Clock control register
0xCF0
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL61
Clock control register
0xCF4
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL62
Clock control register
0xCF8
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL63
Clock control register
0xCFC
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL64
Clock control register
0xD00
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL65
Clock control register
0xD04
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL66
Clock control register
0xD08
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL67
Clock control register
0xD0C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL68
Clock control register
0xD10
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL69
Clock control register
0xD14
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL7
Clock control register
0xC1C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL70
Clock control register
0xD18
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL71
Clock control register
0xD1C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL72
Clock control register
0xD20
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL73
Clock control register
0xD24
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL74
Clock control register
0xD28
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL75
Clock control register
0xD2C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL76
Clock control register
0xD30
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL77
Clock control register
0xD34
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL78
Clock control register
0xD38
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL79
Clock control register
0xD3C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL8
Clock control register
0xC20
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL80
Clock control register
0xD40
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL81
Clock control register
0xD44
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL82
Clock control register
0xD48
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL83
Clock control register
0xD4C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL84
Clock control register
0xD50
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL85
Clock control register
0xD54
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL86
Clock control register
0xD58
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL87
Clock control register
0xD5C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL88
Clock control register
0xD60
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL89
Clock control register
0xD64
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL9
Clock control register
0xC24
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL90
Clock control register
0xD68
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL91
Clock control register
0xD6C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL92
Clock control register
0xD70
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL93
Clock control register
0xD74
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL94
Clock control register
0xD78
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL95
Clock control register
0xD7C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL96
Clock control register
0xD80
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL97
Clock control register
0xD84
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL98
Clock control register
0xD88
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
CLOCK_CTL99
Clock control register
0xD8C
32
read-write
n
0x0
0x0
DIV_SEL
Specifies one of the dividers of the divider type specified by TYPE_SEL. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated. When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '63' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.
0
6
read-write
TYPE_SEL
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
DIV_16_5_CTL0
Divider control register (for 16.5 divider)
0xA00
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL1
Divider control register (for 16.5 divider)
0xA04
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL10
Divider control register (for 16.5 divider)
0xA28
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL11
Divider control register (for 16.5 divider)
0xA2C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL12
Divider control register (for 16.5 divider)
0xA30
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL13
Divider control register (for 16.5 divider)
0xA34
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL14
Divider control register (for 16.5 divider)
0xA38
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL15
Divider control register (for 16.5 divider)
0xA3C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL16
Divider control register (for 16.5 divider)
0xA40
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL17
Divider control register (for 16.5 divider)
0xA44
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL18
Divider control register (for 16.5 divider)
0xA48
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL19
Divider control register (for 16.5 divider)
0xA4C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL2
Divider control register (for 16.5 divider)
0xA08
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL20
Divider control register (for 16.5 divider)
0xA50
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL21
Divider control register (for 16.5 divider)
0xA54
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL22
Divider control register (for 16.5 divider)
0xA58
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL23
Divider control register (for 16.5 divider)
0xA5C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL24
Divider control register (for 16.5 divider)
0xA60
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL25
Divider control register (for 16.5 divider)
0xA64
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL26
Divider control register (for 16.5 divider)
0xA68
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL27
Divider control register (for 16.5 divider)
0xA6C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL28
Divider control register (for 16.5 divider)
0xA70
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL29
Divider control register (for 16.5 divider)
0xA74
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL3
Divider control register (for 16.5 divider)
0xA0C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL30
Divider control register (for 16.5 divider)
0xA78
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL31
Divider control register (for 16.5 divider)
0xA7C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL32
Divider control register (for 16.5 divider)
0xA80
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL33
Divider control register (for 16.5 divider)
0xA84
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL34
Divider control register (for 16.5 divider)
0xA88
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL35
Divider control register (for 16.5 divider)
0xA8C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL36
Divider control register (for 16.5 divider)
0xA90
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL37
Divider control register (for 16.5 divider)
0xA94
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL38
Divider control register (for 16.5 divider)
0xA98
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL39
Divider control register (for 16.5 divider)
0xA9C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL4
Divider control register (for 16.5 divider)
0xA10
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL40
Divider control register (for 16.5 divider)
0xAA0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL41
Divider control register (for 16.5 divider)
0xAA4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL42
Divider control register (for 16.5 divider)
0xAA8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL43
Divider control register (for 16.5 divider)
0xAAC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL44
Divider control register (for 16.5 divider)
0xAB0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL45
Divider control register (for 16.5 divider)
0xAB4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL46
Divider control register (for 16.5 divider)
0xAB8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL47
Divider control register (for 16.5 divider)
0xABC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL48
Divider control register (for 16.5 divider)
0xAC0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL49
Divider control register (for 16.5 divider)
0xAC4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL5
Divider control register (for 16.5 divider)
0xA14
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL50
Divider control register (for 16.5 divider)
0xAC8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL51
Divider control register (for 16.5 divider)
0xACC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL52
Divider control register (for 16.5 divider)
0xAD0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL53
Divider control register (for 16.5 divider)
0xAD4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL54
Divider control register (for 16.5 divider)
0xAD8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL55
Divider control register (for 16.5 divider)
0xADC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL56
Divider control register (for 16.5 divider)
0xAE0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL57
Divider control register (for 16.5 divider)
0xAE4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL58
Divider control register (for 16.5 divider)
0xAE8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL59
Divider control register (for 16.5 divider)
0xAEC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL6
Divider control register (for 16.5 divider)
0xA18
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL60
Divider control register (for 16.5 divider)
0xAF0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL61
Divider control register (for 16.5 divider)
0xAF4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL62
Divider control register (for 16.5 divider)
0xAF8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL63
Divider control register (for 16.5 divider)
0xAFC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL7
Divider control register (for 16.5 divider)
0xA1C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL8
Divider control register (for 16.5 divider)
0xA20
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_5_CTL9
Divider control register (for 16.5 divider)
0xA24
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments. For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 65,536]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL0
Divider control register (for 16.0 divider)
0x900
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL1
Divider control register (for 16.0 divider)
0x904
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL10
Divider control register (for 16.0 divider)
0x928
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL11
Divider control register (for 16.0 divider)
0x92C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL12
Divider control register (for 16.0 divider)
0x930
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL13
Divider control register (for 16.0 divider)
0x934
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL14
Divider control register (for 16.0 divider)
0x938
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL15
Divider control register (for 16.0 divider)
0x93C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL16
Divider control register (for 16.0 divider)
0x940
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL17
Divider control register (for 16.0 divider)
0x944
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL18
Divider control register (for 16.0 divider)
0x948
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL19
Divider control register (for 16.0 divider)
0x94C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL2
Divider control register (for 16.0 divider)
0x908
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL20
Divider control register (for 16.0 divider)
0x950
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL21
Divider control register (for 16.0 divider)
0x954
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL22
Divider control register (for 16.0 divider)
0x958
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL23
Divider control register (for 16.0 divider)
0x95C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL24
Divider control register (for 16.0 divider)
0x960
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL25
Divider control register (for 16.0 divider)
0x964
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL26
Divider control register (for 16.0 divider)
0x968
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL27
Divider control register (for 16.0 divider)
0x96C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL28
Divider control register (for 16.0 divider)
0x970
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL29
Divider control register (for 16.0 divider)
0x974
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL3
Divider control register (for 16.0 divider)
0x90C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL30
Divider control register (for 16.0 divider)
0x978
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL31
Divider control register (for 16.0 divider)
0x97C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL32
Divider control register (for 16.0 divider)
0x980
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL33
Divider control register (for 16.0 divider)
0x984
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL34
Divider control register (for 16.0 divider)
0x988
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL35
Divider control register (for 16.0 divider)
0x98C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL36
Divider control register (for 16.0 divider)
0x990
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL37
Divider control register (for 16.0 divider)
0x994
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL38
Divider control register (for 16.0 divider)
0x998
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL39
Divider control register (for 16.0 divider)
0x99C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL4
Divider control register (for 16.0 divider)
0x910
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL40
Divider control register (for 16.0 divider)
0x9A0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL41
Divider control register (for 16.0 divider)
0x9A4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL42
Divider control register (for 16.0 divider)
0x9A8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL43
Divider control register (for 16.0 divider)
0x9AC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL44
Divider control register (for 16.0 divider)
0x9B0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL45
Divider control register (for 16.0 divider)
0x9B4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL46
Divider control register (for 16.0 divider)
0x9B8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL47
Divider control register (for 16.0 divider)
0x9BC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL48
Divider control register (for 16.0 divider)
0x9C0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL49
Divider control register (for 16.0 divider)
0x9C4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL5
Divider control register (for 16.0 divider)
0x914
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL50
Divider control register (for 16.0 divider)
0x9C8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL51
Divider control register (for 16.0 divider)
0x9CC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL52
Divider control register (for 16.0 divider)
0x9D0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL53
Divider control register (for 16.0 divider)
0x9D4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL54
Divider control register (for 16.0 divider)
0x9D8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL55
Divider control register (for 16.0 divider)
0x9DC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL56
Divider control register (for 16.0 divider)
0x9E0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL57
Divider control register (for 16.0 divider)
0x9E4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL58
Divider control register (for 16.0 divider)
0x9E8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL59
Divider control register (for 16.0 divider)
0x9EC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL6
Divider control register (for 16.0 divider)
0x918
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL60
Divider control register (for 16.0 divider)
0x9F0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL61
Divider control register (for 16.0 divider)
0x9F4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL62
Divider control register (for 16.0 divider)
0x9F8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL63
Divider control register (for 16.0 divider)
0x9FC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL7
Divider control register (for 16.0 divider)
0x91C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL8
Divider control register (for 16.0 divider)
0x920
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_16_CTL9
Divider control register (for 16.0 divider)
0x924
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT16_DIV
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 65,536]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
24
read-write
DIV_24_5_CTL0
Divider control register (for 24.5 divider)
0xB00
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL1
Divider control register (for 24.5 divider)
0xB04
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL10
Divider control register (for 24.5 divider)
0xB28
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL11
Divider control register (for 24.5 divider)
0xB2C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL12
Divider control register (for 24.5 divider)
0xB30
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL13
Divider control register (for 24.5 divider)
0xB34
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL14
Divider control register (for 24.5 divider)
0xB38
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL15
Divider control register (for 24.5 divider)
0xB3C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL16
Divider control register (for 24.5 divider)
0xB40
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL17
Divider control register (for 24.5 divider)
0xB44
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL18
Divider control register (for 24.5 divider)
0xB48
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL19
Divider control register (for 24.5 divider)
0xB4C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL2
Divider control register (for 24.5 divider)
0xB08
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL20
Divider control register (for 24.5 divider)
0xB50
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL21
Divider control register (for 24.5 divider)
0xB54
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL22
Divider control register (for 24.5 divider)
0xB58
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL23
Divider control register (for 24.5 divider)
0xB5C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL24
Divider control register (for 24.5 divider)
0xB60
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL25
Divider control register (for 24.5 divider)
0xB64
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL26
Divider control register (for 24.5 divider)
0xB68
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL27
Divider control register (for 24.5 divider)
0xB6C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL28
Divider control register (for 24.5 divider)
0xB70
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL29
Divider control register (for 24.5 divider)
0xB74
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL3
Divider control register (for 24.5 divider)
0xB0C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL30
Divider control register (for 24.5 divider)
0xB78
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL31
Divider control register (for 24.5 divider)
0xB7C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL32
Divider control register (for 24.5 divider)
0xB80
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL33
Divider control register (for 24.5 divider)
0xB84
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL34
Divider control register (for 24.5 divider)
0xB88
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL35
Divider control register (for 24.5 divider)
0xB8C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL36
Divider control register (for 24.5 divider)
0xB90
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL37
Divider control register (for 24.5 divider)
0xB94
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL38
Divider control register (for 24.5 divider)
0xB98
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL39
Divider control register (for 24.5 divider)
0xB9C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL4
Divider control register (for 24.5 divider)
0xB10
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL40
Divider control register (for 24.5 divider)
0xBA0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL41
Divider control register (for 24.5 divider)
0xBA4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL42
Divider control register (for 24.5 divider)
0xBA8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL43
Divider control register (for 24.5 divider)
0xBAC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL44
Divider control register (for 24.5 divider)
0xBB0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL45
Divider control register (for 24.5 divider)
0xBB4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL46
Divider control register (for 24.5 divider)
0xBB8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL47
Divider control register (for 24.5 divider)
0xBBC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL48
Divider control register (for 24.5 divider)
0xBC0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL49
Divider control register (for 24.5 divider)
0xBC4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL5
Divider control register (for 24.5 divider)
0xB14
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL50
Divider control register (for 24.5 divider)
0xBC8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL51
Divider control register (for 24.5 divider)
0xBCC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL52
Divider control register (for 24.5 divider)
0xBD0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL53
Divider control register (for 24.5 divider)
0xBD4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL54
Divider control register (for 24.5 divider)
0xBD8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL55
Divider control register (for 24.5 divider)
0xBDC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL56
Divider control register (for 24.5 divider)
0xBE0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL57
Divider control register (for 24.5 divider)
0xBE4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL58
Divider control register (for 24.5 divider)
0xBE8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL59
Divider control register (for 24.5 divider)
0xBEC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL6
Divider control register (for 24.5 divider)
0xB18
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL60
Divider control register (for 24.5 divider)
0xBF0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL61
Divider control register (for 24.5 divider)
0xBF4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL62
Divider control register (for 24.5 divider)
0xBF8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL7
Divider control register (for 24.5 divider)
0xB1C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL8
Divider control register (for 24.5 divider)
0xB20
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_24_5_CTL9
Divider control register (for 24.5 divider)
0xB24
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
FRAC5_DIV
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
3
8
read-write
INT24_DIV
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments. For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32]. For the generation of a 50/50 percent duty cycle divided clock, the division range is restricted to [2, 16,777,216]. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
32
read-write
DIV_8_CTL0
Divider control register (for 8.0 divider)
0x800
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL1
Divider control register (for 8.0 divider)
0x804
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL10
Divider control register (for 8.0 divider)
0x828
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL11
Divider control register (for 8.0 divider)
0x82C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL12
Divider control register (for 8.0 divider)
0x830
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL13
Divider control register (for 8.0 divider)
0x834
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL14
Divider control register (for 8.0 divider)
0x838
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL15
Divider control register (for 8.0 divider)
0x83C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL16
Divider control register (for 8.0 divider)
0x840
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL17
Divider control register (for 8.0 divider)
0x844
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL18
Divider control register (for 8.0 divider)
0x848
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL19
Divider control register (for 8.0 divider)
0x84C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL2
Divider control register (for 8.0 divider)
0x808
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL20
Divider control register (for 8.0 divider)
0x850
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL21
Divider control register (for 8.0 divider)
0x854
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL22
Divider control register (for 8.0 divider)
0x858
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL23
Divider control register (for 8.0 divider)
0x85C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL24
Divider control register (for 8.0 divider)
0x860
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL25
Divider control register (for 8.0 divider)
0x864
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL26
Divider control register (for 8.0 divider)
0x868
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL27
Divider control register (for 8.0 divider)
0x86C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL28
Divider control register (for 8.0 divider)
0x870
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL29
Divider control register (for 8.0 divider)
0x874
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL3
Divider control register (for 8.0 divider)
0x80C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL30
Divider control register (for 8.0 divider)
0x878
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL31
Divider control register (for 8.0 divider)
0x87C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL32
Divider control register (for 8.0 divider)
0x880
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL33
Divider control register (for 8.0 divider)
0x884
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL34
Divider control register (for 8.0 divider)
0x888
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL35
Divider control register (for 8.0 divider)
0x88C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL36
Divider control register (for 8.0 divider)
0x890
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL37
Divider control register (for 8.0 divider)
0x894
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL38
Divider control register (for 8.0 divider)
0x898
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL39
Divider control register (for 8.0 divider)
0x89C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL4
Divider control register (for 8.0 divider)
0x810
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL40
Divider control register (for 8.0 divider)
0x8A0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL41
Divider control register (for 8.0 divider)
0x8A4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL42
Divider control register (for 8.0 divider)
0x8A8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL43
Divider control register (for 8.0 divider)
0x8AC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL44
Divider control register (for 8.0 divider)
0x8B0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL45
Divider control register (for 8.0 divider)
0x8B4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL46
Divider control register (for 8.0 divider)
0x8B8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL47
Divider control register (for 8.0 divider)
0x8BC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL48
Divider control register (for 8.0 divider)
0x8C0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL49
Divider control register (for 8.0 divider)
0x8C4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL5
Divider control register (for 8.0 divider)
0x814
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL50
Divider control register (for 8.0 divider)
0x8C8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL51
Divider control register (for 8.0 divider)
0x8CC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL52
Divider control register (for 8.0 divider)
0x8D0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL53
Divider control register (for 8.0 divider)
0x8D4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL54
Divider control register (for 8.0 divider)
0x8D8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL55
Divider control register (for 8.0 divider)
0x8DC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL56
Divider control register (for 8.0 divider)
0x8E0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL57
Divider control register (for 8.0 divider)
0x8E4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL58
Divider control register (for 8.0 divider)
0x8E8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL59
Divider control register (for 8.0 divider)
0x8EC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL6
Divider control register (for 8.0 divider)
0x818
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL60
Divider control register (for 8.0 divider)
0x8F0
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL61
Divider control register (for 8.0 divider)
0x8F4
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL62
Divider control register (for 8.0 divider)
0x8F8
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL63
Divider control register (for 8.0 divider)
0x8FC
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL7
Divider control register (for 8.0 divider)
0x81C
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL8
Divider control register (for 8.0 divider)
0x820
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_8_CTL9
Divider control register (for 8.0 divider)
0x824
32
read-write
n
0x0
0x0
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command. Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.
0
1
read-only
INT8_DIV
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division. For the generation of a divided clock, the integer division range is restricted to [2, 256]. For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 percent duty cycle analog divided clock has no restrictions. Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
8
16
read-write
DIV_CMD
Divider command register
0x400
32
read-write
n
0x0
0x0
DISABLE
Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled. The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately.
30
31
read-write
DIV_SEL
(TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed. If DIV_SEL is '63' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated.
0
6
read-write
ENABLE
Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: 0: Disable the divider using the DIV_CMD.DISABLE field. 1: Configure the divider's DIV_XXX_CTL register. 2: Enable the divider using the DIV_CMD_ENABLE field. The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_peri' (typical usage) or to ANY enabled divider. The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider. The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_peri'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_peri' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process.
31
32
read-write
PA_DIV_SEL
(PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times. If PA_DIV_SEL is '63' and PA_TYPE_SEL is '3', 'clk_peri' is used as reference.
8
14
read-write
PA_TYPE_SEL
Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
14
16
read-write
TYPE_SEL
Specifies the divider type of the divider on which the command is performed: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.
6
8
read-write
SL_CTL
Slave control
0x20
32
read-write
n
0x0
0x0
ENABLED_0
Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled.
0
1
read-only
ENABLED_1
Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
1
2
read-write
ENABLED_10
N/A
10
11
read-write
ENABLED_11
N/A
11
12
read-write
ENABLED_12
N/A
12
13
read-write
ENABLED_13
N/A
13
14
read-write
ENABLED_14
N/A
14
15
read-write
ENABLED_15
N/A
15
16
read-write
ENABLED_2
Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated. Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.
2
3
read-write
ENABLED_3
N/A
3
4
read-write
ENABLED_4
N/A
4
5
read-write
ENABLED_5
N/A
5
6
read-write
ENABLED_6
N/A
6
7
read-write
ENABLED_7
N/A
7
8
read-write
ENABLED_8
N/A
8
9
read-write
ENABLED_9
N/A
9
10
read-write
TIMEOUT_CTL
Timeout control
0x24
32
read-write
n
0x0
0x0
TIMEOUT
This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). '0x0000'-'0xfffe': Number of peripheral group clock cycles. '0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated.
0
16
read-write
TR_CMD
Trigger command register
0x1000
32
read-write
n
0x0
0x0
ACTIVATE
SW sets this field to '1' by to activate (set to '1') a trigger as identified by TR_SEL and OUT_SEL for COUNT cycles. HW sets this field to '0' when the cycle counter is decremented to '0'. Note: a COUNT value of 255 is a special case and trigger activation is under direct control of the ACTIVATE field (the counter is not decremented).
31
32
read-write
COUNT
Amount of 'clk_peri' cycles a specific trigger is activated. During activation (ACTIVATE is '1'), HW decrements this field to '0' using a cycle counter. During activation, SW should not modify this register field. A value of 255 is a special case: HW does NOT decrement this field to '0' and trigger activation is under direct control of ACTIVATE when ACTIVATE is '1' the trigger is activated and when ACTIVATE is '0' the trigger is deactivated.
16
24
read-write
GROUP_SEL
Specifies the trigger group.
8
12
read-write
OUT_SEL
Specifies whether trigger activation is for a specific input or ouput trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only. '0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer. '1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer.
30
31
read-write
TR_SEL
Specifies the activated trigger when ACTIVATE is '1'. OUT_SEL specifies whether the activated trigger is an input trigger or output trigger to the trigger multiplexer. During activation (ACTIVATE is '1'), SW should not modify this register field. If the specified trigger is not present, the trigger activation has no effect.
0
8
read-write
TR_OUT_CTL0
Trigger control register
0x0
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL1
Trigger control register
0x4
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL10
Trigger control register
0x28
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL100
Trigger control register
0x190
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL101
Trigger control register
0x194
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL102
Trigger control register
0x198
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL103
Trigger control register
0x19C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL104
Trigger control register
0x1A0
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL105
Trigger control register
0x1A4
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL106
Trigger control register
0x1A8
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL107
Trigger control register
0x1AC
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL108
Trigger control register
0x1B0
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL109
Trigger control register
0x1B4
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL11
Trigger control register
0x2C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL110
Trigger control register
0x1B8
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL111
Trigger control register
0x1BC
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL112
Trigger control register
0x1C0
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL113
Trigger control register
0x1C4
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL114
Trigger control register
0x1C8
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL115
Trigger control register
0x1CC
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL116
Trigger control register
0x1D0
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL117
Trigger control register
0x1D4
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL118
Trigger control register
0x1D8
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL119
Trigger control register
0x1DC
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL12
Trigger control register
0x30
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL120
Trigger control register
0x1E0
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL121
Trigger control register
0x1E4
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL122
Trigger control register
0x1E8
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL123
Trigger control register
0x1EC
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL124
Trigger control register
0x1F0
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL125
Trigger control register
0x1F4
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL126
Trigger control register
0x1F8
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL127
Trigger control register
0x1FC
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL13
Trigger control register
0x34
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL14
Trigger control register
0x38
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL15
Trigger control register
0x3C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL16
Trigger control register
0x40
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL17
Trigger control register
0x44
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL18
Trigger control register
0x48
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL19
Trigger control register
0x4C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL2
Trigger control register
0x8
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL20
Trigger control register
0x50
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL21
Trigger control register
0x54
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL22
Trigger control register
0x58
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL23
Trigger control register
0x5C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL24
Trigger control register
0x60
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL25
Trigger control register
0x64
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL26
Trigger control register
0x68
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL27
Trigger control register
0x6C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL28
Trigger control register
0x70
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL29
Trigger control register
0x74
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL3
Trigger control register
0xC
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL30
Trigger control register
0x78
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL31
Trigger control register
0x7C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL32
Trigger control register
0x80
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL33
Trigger control register
0x84
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL34
Trigger control register
0x88
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL35
Trigger control register
0x8C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL36
Trigger control register
0x90
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL37
Trigger control register
0x94
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL38
Trigger control register
0x98
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL39
Trigger control register
0x9C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL4
Trigger control register
0x10
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL40
Trigger control register
0xA0
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL41
Trigger control register
0xA4
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL42
Trigger control register
0xA8
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL43
Trigger control register
0xAC
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL44
Trigger control register
0xB0
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL45
Trigger control register
0xB4
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL46
Trigger control register
0xB8
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL47
Trigger control register
0xBC
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL48
Trigger control register
0xC0
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL49
Trigger control register
0xC4
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL5
Trigger control register
0x14
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL50
Trigger control register
0xC8
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL51
Trigger control register
0xCC
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL52
Trigger control register
0xD0
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL53
Trigger control register
0xD4
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL54
Trigger control register
0xD8
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL55
Trigger control register
0xDC
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL56
Trigger control register
0xE0
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL57
Trigger control register
0xE4
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL58
Trigger control register
0xE8
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL59
Trigger control register
0xEC
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL6
Trigger control register
0x18
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL60
Trigger control register
0xF0
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL61
Trigger control register
0xF4
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL62
Trigger control register
0xF8
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL63
Trigger control register
0xFC
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL64
Trigger control register
0x100
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL65
Trigger control register
0x104
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL66
Trigger control register
0x108
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL67
Trigger control register
0x10C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL68
Trigger control register
0x110
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL69
Trigger control register
0x114
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL7
Trigger control register
0x1C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL70
Trigger control register
0x118
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL71
Trigger control register
0x11C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL72
Trigger control register
0x120
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL73
Trigger control register
0x124
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL74
Trigger control register
0x128
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL75
Trigger control register
0x12C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL76
Trigger control register
0x130
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL77
Trigger control register
0x134
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL78
Trigger control register
0x138
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL79
Trigger control register
0x13C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL8
Trigger control register
0x20
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL80
Trigger control register
0x140
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL81
Trigger control register
0x144
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL82
Trigger control register
0x148
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL83
Trigger control register
0x14C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL84
Trigger control register
0x150
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL85
Trigger control register
0x154
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL86
Trigger control register
0x158
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL87
Trigger control register
0x15C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL88
Trigger control register
0x160
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL89
Trigger control register
0x164
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL9
Trigger control register
0x24
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL90
Trigger control register
0x168
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL91
Trigger control register
0x16C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL92
Trigger control register
0x170
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL93
Trigger control register
0x174
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL94
Trigger control register
0x178
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL95
Trigger control register
0x17C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL96
Trigger control register
0x180
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL97
Trigger control register
0x184
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL98
Trigger control register
0x188
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
TR_OUT_CTL99
Trigger control register
0x18C
32
read-write
n
0x0
0x0
TR_EDGE
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.
9
10
read-write
TR_INV
Specifies if the output trigger is inverted.
8
9
read-write
TR_SEL
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.
0
8
read-write
PROT
Protection
PROT
0x0
0x0
0x10000
registers
n
ADDR
MPU region address
0x0
32
read-write
n
0x0
0x0
ADDR24
This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
8
32
read-write
SUBREGION_DISABLE
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
0
8
read-write
ADDR0
SMPU region address 0 (slave structure)
0x0
32
read-write
n
0x0
0x0
ADDR24
This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.
8
32
read-write
SUBREGION_DISABLE
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.
0
8
read-write
ADDR1
SMPU region address 1 (master structure)
0x20
32
read-only
n
0x0
0x0
ADDR24
This field specifies the most significant bits of the 32-bit address of an address region. 'ADDR_DEF1': base address of structure. Note: this field is read-only.
8
32
read-only
SUBREGION_DISABLE
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only.
0
8
read-only
ATT
MPU region attrributes
0x4
32
read-write
n
0x0
0x0
ENABLED
Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
31
32
read-write
NS
Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
6
7
read-write
PR
Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed).
3
4
read-write
PW
Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed).
4
5
read-write
PX
Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed).
5
6
read-write
REGION_SIZE
This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
24
29
read-write
UR
User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed).
0
1
read-write
UW
User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed).
1
2
read-write
UX
User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed).
2
3
read-write
ATT0
SMPU region attributes 0 (slave structure)
0x4
32
read-write
n
0x0
0x0
ENABLED
Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption.
31
32
read-write
NS
Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
6
7
read-write
PC_MASK_0
This field specifies protection context identifier based access control for protection context '0'.
8
9
read-only
PC_MASK_15_TO_1
This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled i.e. not allowed. If '1', protection context i+1 access is enabled i.e. allowed.
9
24
read-write
PC_MATCH
This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'. '1': PC field participates in 'matching'. 'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. 'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
30
31
read-write
PR
Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed).
3
4
read-write
PW
Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed).
4
5
read-write
PX
Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed).
5
6
read-write
REGION_SIZE
This field specifies the region size: '0'-'6': Undefined. '7': 256 B region '8': 512 B region '9': 1 KB region '10': 2 KB region '11': 4 KB region '12': 8 KB region '13': 16 KB region '14': 32 KB region '15': 64 KB region '16': 128 KB region '17': 256 KB region '18': 512 KB region '19': 1 MB region '20': 2 MB region '21': 4 MB region '22': 8 MB region '23': 16 MB region '24': 32 MB region '25': 64 MB region '26': 128 MB region '27': 256 MB region '28': 512 MB region '39': 1 GB region '30': 2 GB region '31': 4 GB region
24
29
read-write
UR
User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed).
0
1
read-write
UW
User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed).
1
2
read-write
UX
User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed).
2
3
read-write
ATT1
SMPU region attributes 1 (master structure)
0x24
32
read-write
n
0x0
0x0
ENABLED
Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled.
31
32
read-write
NS
Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed).
6
7
read-write
PC_MASK_0
This field specifies protection context identifier based access control for protection context '0'.
8
9
read-only
PC_MASK_15_TO_1
This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled i.e. not allowed. If '1', protection context i+1 access is enabled i.e. allowed.
9
24
read-write
PC_MATCH
This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process: '0': PC field participates in 'access evaluation'. '1': PC field participates in 'matching'. 'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions. 'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes. Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.
30
31
read-write
PR
Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). Note that this register is constant '1' i.e. privileged read accesses are ALWAYS allowed.
3
4
read-only
PW
Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed).
4
5
read-write
PX
Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). Note that this register is constant '0' i.e. privileged execute accesses are NEVER allowed.
5
6
read-only
REGION_SIZE
This field specifies the region size: '7': 256 B region (8 32 B subregions) Note: this field is read-only.
24
29
read-only
UR
User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). Note that this register is constant '1' i.e. user read accesses are ALWAYS allowed.
0
1
read-only
UW
User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed).
1
2
read-write
UX
User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). Note that this register is constant '0' i.e. user execute accesses are NEVER allowed.
2
3
read-only
MS0_CTL
Master 0 protection context control
0x0
32
read-write
n
0x0
0x0
NS
Security setting ('0': secure mode '1': non-secure mode). Notes: This field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute. Note that the default/reset field value provides non-secure mode access capabilities to all masters.
1
2
read-write
P
Privileged setting ('0': user mode '1': privileged mode). Notes: This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute. The default/reset field value provides privileged mode access capabilities.
0
1
read-write
PC_MASK_0
Protection context mask for protection context '0'. This field is a constant '0': - PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed.
16
17
read-only
PC_MASK_15_TO_1
Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1': - PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed. - PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'. Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]).
17
32
read-write
PRIO
Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority). Notes: The AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth). The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency). Masters with the same priority setting form a 'priority group'. Within a 'priority group', round robin arbitration is performed.
8
10
read-write
MS10_CTL
Master 10 protection context control
0x28
32
read-write
n
0x0
0x0
NS
See MS0_CTL.NS.
1
2
read-write
P
See MS0_CTL.P.
0
1
read-write
PC_MASK_0
See MS0_CTL.PC_MASK_0.
16
17
read-only
PC_MASK_15_TO_1
See MS0_CTL.PC_MASK_15_TO_1.
17
32
read-write
PRIO
See MS0_CTL.PRIO
8
10
read-write
MS11_CTL
Master 11 protection context control
0x2C
32
read-write
n
0x0
0x0
NS
See MS0_CTL.NS.
1
2
read-write
P
See MS0_CTL.P.
0
1
read-write
PC_MASK_0
See MS0_CTL.PC_MASK_0.
16
17
read-only
PC_MASK_15_TO_1
See MS0_CTL.PC_MASK_15_TO_1.
17
32
read-write
PRIO
See MS0_CTL.PRIO
8
10
read-write
MS12_CTL
Master 12 protection context control
0x30
32
read-write
n
0x0
0x0
NS
See MS0_CTL.NS.
1
2
read-write
P
See MS0_CTL.P.
0
1
read-write
PC_MASK_0
See MS0_CTL.PC_MASK_0.
16
17
read-only
PC_MASK_15_TO_1
See MS0_CTL.PC_MASK_15_TO_1.
17
32
read-write
PRIO
See MS0_CTL.PRIO
8
10
read-write
MS13_CTL
Master 13 protection context control
0x34
32
read-write
n
0x0
0x0
NS
See MS0_CTL.NS.
1
2
read-write
P
See MS0_CTL.P.
0
1
read-write
PC_MASK_0
See MS0_CTL.PC_MASK_0.
16
17
read-only
PC_MASK_15_TO_1
See MS0_CTL.PC_MASK_15_TO_1.
17
32
read-write
PRIO
See MS0_CTL.PRIO
8
10
read-write
MS14_CTL
Master 14 protection context control
0x38
32
read-write
n
0x0
0x0
NS
See MS0_CTL.NS.
1
2
read-write
P
See MS0_CTL.P.
0
1
read-write
PC_MASK_0
See MS0_CTL.PC_MASK_0.
16
17
read-only
PC_MASK_15_TO_1
See MS0_CTL.PC_MASK_15_TO_1.
17
32
read-write
PRIO
See MS0_CTL.PRIO
8
10
read-write
MS15_CTL
Master 15 protection context control
0x3C
32
read-write
n
0x0
0x0
NS
See MS0_CTL.NS.
1
2
read-write
P
See MS0_CTL.P.
0
1
read-write
PC_MASK_0
See MS0_CTL.PC_MASK_0.
16
17
read-only
PC_MASK_15_TO_1
See MS0_CTL.PC_MASK_15_TO_1.
17
32
read-write
PRIO
See MS0_CTL.PRIO
8
10
read-write
MS1_CTL
Master 1 protection context control
0x4
32
read-write
n
0x0
0x0
NS
See MS0_CTL.NS.
1
2
read-write
P
See MS0_CTL.P.
0
1
read-write
PC_MASK_0
See MS0_CTL.PC_MASK_0.
16
17
read-only
PC_MASK_15_TO_1
See MS0_CTL.PC_MASK_15_TO_1.
17
32
read-write
PRIO
See MS0_CTL.PRIO
8
10
read-write
MS2_CTL
Master 2 protection context control
0x8
32
read-write
n
0x0
0x0
NS
See MS0_CTL.NS.
1
2
read-write
P
See MS0_CTL.P.
0
1
read-write
PC_MASK_0
See MS0_CTL.PC_MASK_0.
16
17
read-only
PC_MASK_15_TO_1
See MS0_CTL.PC_MASK_15_TO_1.
17
32
read-write
PRIO
See MS0_CTL.PRIO
8
10
read-write
MS3_CTL
Master 3 protection context control
0xC
32
read-write
n
0x0
0x0
NS
See MS0_CTL.NS.
1
2
read-write
P
See MS0_CTL.P.
0
1
read-write
PC_MASK_0
See MS0_CTL.PC_MASK_0.
16
17
read-only
PC_MASK_15_TO_1
See MS0_CTL.PC_MASK_15_TO_1.
17
32
read-write
PRIO
See MS0_CTL.PRIO
8
10
read-write
MS4_CTL
Master 4 protection context control
0x10
32
read-write
n
0x0
0x0
NS
See MS0_CTL.NS.
1
2
read-write
P
See MS0_CTL.P.
0
1
read-write
PC_MASK_0
See MS0_CTL.PC_MASK_0.
16
17
read-only
PC_MASK_15_TO_1
See MS0_CTL.PC_MASK_15_TO_1.
17
32
read-write
PRIO
See MS0_CTL.PRIO
8
10
read-write
MS5_CTL
Master 5 protection context control
0x14
32
read-write
n
0x0
0x0
NS
See MS0_CTL.NS.
1
2
read-write
P
See MS0_CTL.P.
0
1
read-write
PC_MASK_0
See MS0_CTL.PC_MASK_0.
16
17
read-only
PC_MASK_15_TO_1
See MS0_CTL.PC_MASK_15_TO_1.
17
32
read-write
PRIO
See MS0_CTL.PRIO
8
10
read-write
MS6_CTL
Master 6 protection context control
0x18
32
read-write
n
0x0
0x0
NS
See MS0_CTL.NS.
1
2
read-write
P
See MS0_CTL.P.
0
1
read-write
PC_MASK_0
See MS0_CTL.PC_MASK_0.
16
17
read-only
PC_MASK_15_TO_1
See MS0_CTL.PC_MASK_15_TO_1.
17
32
read-write
PRIO
See MS0_CTL.PRIO
8
10
read-write
MS7_CTL
Master 7 protection context control
0x1C
32
read-write
n
0x0
0x0
NS
See MS0_CTL.NS.
1
2
read-write
P
See MS0_CTL.P.
0
1
read-write
PC_MASK_0
See MS0_CTL.PC_MASK_0.
16
17
read-only
PC_MASK_15_TO_1
See MS0_CTL.PC_MASK_15_TO_1.
17
32
read-write
PRIO
See MS0_CTL.PRIO
8
10
read-write
MS8_CTL
Master 8 protection context control
0x20
32
read-write
n
0x0
0x0
NS
See MS0_CTL.NS.
1
2
read-write
P
See MS0_CTL.P.
0
1
read-write
PC_MASK_0
See MS0_CTL.PC_MASK_0.
16
17
read-only
PC_MASK_15_TO_1
See MS0_CTL.PC_MASK_15_TO_1.
17
32
read-write
PRIO
See MS0_CTL.PRIO
8
10
read-write
MS9_CTL
Master 9 protection context control
0x24
32
read-write
n
0x0
0x0
NS
See MS0_CTL.NS.
1
2
read-write
P
See MS0_CTL.P.
0
1
read-write
PC_MASK_0
See MS0_CTL.PC_MASK_0.
16
17
read-only
PC_MASK_15_TO_1
See MS0_CTL.PC_MASK_15_TO_1.
17
32
read-write
PRIO
See MS0_CTL.PRIO
8
10
read-write
MS_CTL
Master control
0x0
32
read-write
n
0x0
0x0
PC
N/A
0
4
read-write
PC_SAVED
Saved protection context. Modifications to this field are constrained by the associated MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields.
16
20
read-write
MS_CTL_READ_MIR0
Master control read mirror
0x4
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR1
Master control read mirror
0x8
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR10
Master control read mirror
0x2C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR100
Master control read mirror
0x194
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR101
Master control read mirror
0x198
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR102
Master control read mirror
0x19C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR103
Master control read mirror
0x1A0
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR104
Master control read mirror
0x1A4
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR105
Master control read mirror
0x1A8
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR106
Master control read mirror
0x1AC
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR107
Master control read mirror
0x1B0
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR108
Master control read mirror
0x1B4
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR109
Master control read mirror
0x1B8
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR11
Master control read mirror
0x30
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR110
Master control read mirror
0x1BC
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR111
Master control read mirror
0x1C0
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR112
Master control read mirror
0x1C4
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR113
Master control read mirror
0x1C8
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR114
Master control read mirror
0x1CC
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR115
Master control read mirror
0x1D0
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR116
Master control read mirror
0x1D4
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR117
Master control read mirror
0x1D8
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR118
Master control read mirror
0x1DC
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR119
Master control read mirror
0x1E0
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR12
Master control read mirror
0x34
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR120
Master control read mirror
0x1E4
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR121
Master control read mirror
0x1E8
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR122
Master control read mirror
0x1EC
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR123
Master control read mirror
0x1F0
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR124
Master control read mirror
0x1F4
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR125
Master control read mirror
0x1F8
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR126
Master control read mirror
0x1FC
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR13
Master control read mirror
0x38
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR14
Master control read mirror
0x3C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR15
Master control read mirror
0x40
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR16
Master control read mirror
0x44
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR17
Master control read mirror
0x48
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR18
Master control read mirror
0x4C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR19
Master control read mirror
0x50
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR2
Master control read mirror
0xC
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR20
Master control read mirror
0x54
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR21
Master control read mirror
0x58
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR22
Master control read mirror
0x5C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR23
Master control read mirror
0x60
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR24
Master control read mirror
0x64
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR25
Master control read mirror
0x68
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR26
Master control read mirror
0x6C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR27
Master control read mirror
0x70
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR28
Master control read mirror
0x74
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR29
Master control read mirror
0x78
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR3
Master control read mirror
0x10
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR30
Master control read mirror
0x7C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR31
Master control read mirror
0x80
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR32
Master control read mirror
0x84
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR33
Master control read mirror
0x88
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR34
Master control read mirror
0x8C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR35
Master control read mirror
0x90
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR36
Master control read mirror
0x94
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR37
Master control read mirror
0x98
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR38
Master control read mirror
0x9C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR39
Master control read mirror
0xA0
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR4
Master control read mirror
0x14
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR40
Master control read mirror
0xA4
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR41
Master control read mirror
0xA8
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR42
Master control read mirror
0xAC
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR43
Master control read mirror
0xB0
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR44
Master control read mirror
0xB4
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR45
Master control read mirror
0xB8
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR46
Master control read mirror
0xBC
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR47
Master control read mirror
0xC0
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR48
Master control read mirror
0xC4
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR49
Master control read mirror
0xC8
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR5
Master control read mirror
0x18
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR50
Master control read mirror
0xCC
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR51
Master control read mirror
0xD0
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR52
Master control read mirror
0xD4
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR53
Master control read mirror
0xD8
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR54
Master control read mirror
0xDC
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR55
Master control read mirror
0xE0
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR56
Master control read mirror
0xE4
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR57
Master control read mirror
0xE8
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR58
Master control read mirror
0xEC
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR59
Master control read mirror
0xF0
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR6
Master control read mirror
0x1C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR60
Master control read mirror
0xF4
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR61
Master control read mirror
0xF8
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR62
Master control read mirror
0xFC
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR63
Master control read mirror
0x100
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR64
Master control read mirror
0x104
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR65
Master control read mirror
0x108
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR66
Master control read mirror
0x10C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR67
Master control read mirror
0x110
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR68
Master control read mirror
0x114
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR69
Master control read mirror
0x118
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR7
Master control read mirror
0x20
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR70
Master control read mirror
0x11C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR71
Master control read mirror
0x120
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR72
Master control read mirror
0x124
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR73
Master control read mirror
0x128
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR74
Master control read mirror
0x12C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR75
Master control read mirror
0x130
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR76
Master control read mirror
0x134
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR77
Master control read mirror
0x138
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR78
Master control read mirror
0x13C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR79
Master control read mirror
0x140
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR8
Master control read mirror
0x24
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR80
Master control read mirror
0x144
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR81
Master control read mirror
0x148
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR82
Master control read mirror
0x14C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR83
Master control read mirror
0x150
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR84
Master control read mirror
0x154
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR85
Master control read mirror
0x158
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR86
Master control read mirror
0x15C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR87
Master control read mirror
0x160
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR88
Master control read mirror
0x164
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR89
Master control read mirror
0x168
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR9
Master control read mirror
0x28
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR90
Master control read mirror
0x16C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR91
Master control read mirror
0x170
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR92
Master control read mirror
0x174
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR93
Master control read mirror
0x178
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR94
Master control read mirror
0x17C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR95
Master control read mirror
0x180
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR96
Master control read mirror
0x184
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR97
Master control read mirror
0x188
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR98
Master control read mirror
0x18C
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
MS_CTL_READ_MIR99
Master control read mirror
0x190
32
read-only
n
0x0
0x0
PC
Read-only mirror of MS_CTL.PC
0
4
read-only
PC_SAVED
Read-only mirror of MS_CTL.PC_SAVED
16
20
read-only
SRSS
SRSS Core Registers
SRSS
0x0
0x0
0x10000
registers
n
CLK_CAL_CNT1
Clock Calibration Counter 1
0x51C
32
read-write
n
0x0
0x0
CAL_COUNTER1
Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done. Do not write this field unless CAL_COUNTER_DONE==1. Both clocks must be running or the measurement will not complete. A stalled counter can be recovered by selecting valid clocks, waiting until the measurement completes, and discarding the first result.
0
24
read-write
CAL_COUNTER_DONE
Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up
31
32
read-only
CLK_CAL_CNT2
Clock Calibration Counter 2
0x520
32
read-only
n
0x0
0x0
CAL_COUNTER2
Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER)
0
24
read-only
CLK_DSI_SELECT0
Clock DSI Select Register
0x300
32
read-write
n
0x0
0x0
DSI_MUX
Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
0
5
read-write
DSI_OUT0
DSI0 - dsi_out[0]
0
DSI_OUT1
DSI1 - dsi_out[1]
1
DSI_OUT10
DSI10 - dsi_out[10]
10
DSI_OUT11
DSI11 - dsi_out[11]
11
DSI_OUT12
DSI12 - dsi_out[12]
12
DSI_OUT13
DSI13 - dsi_out[13]
13
DSI_OUT14
DSI14 - dsi_out[14]
14
DSI_OUT15
DSI15 - dsi_out[15]
15
ILO
ILO - Internal Low-speed Oscillator
16
WCO
WCO - Watch-Crystal Oscillator
17
ALTLF
ALTLF - Alternate Low-Frequency Clock
18
PILO
PILO - Precision Internal Low-speed Oscillator
19
DSI_OUT2
DSI2 - dsi_out[2]
2
DSI_OUT3
DSI3 - dsi_out[3]
3
DSI_OUT4
DSI4 - dsi_out[4]
4
DSI_OUT5
DSI5 - dsi_out[5]
5
DSI_OUT6
DSI6 - dsi_out[6]
6
DSI_OUT7
DSI7 - dsi_out[7]
7
DSI_OUT8
DSI8 - dsi_out[8]
8
DSI_OUT9
DSI9 - dsi_out[9]
9
CLK_DSI_SELECT1
Clock DSI Select Register
0x304
32
read-write
n
0x0
0x0
DSI_MUX
Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
0
5
read-write
DSI_OUT0
DSI0 - dsi_out[0]
0
DSI_OUT1
DSI1 - dsi_out[1]
1
DSI_OUT10
DSI10 - dsi_out[10]
10
DSI_OUT11
DSI11 - dsi_out[11]
11
DSI_OUT12
DSI12 - dsi_out[12]
12
DSI_OUT13
DSI13 - dsi_out[13]
13
DSI_OUT14
DSI14 - dsi_out[14]
14
DSI_OUT15
DSI15 - dsi_out[15]
15
ILO
ILO - Internal Low-speed Oscillator
16
WCO
WCO - Watch-Crystal Oscillator
17
ALTLF
ALTLF - Alternate Low-Frequency Clock
18
PILO
PILO - Precision Internal Low-speed Oscillator
19
DSI_OUT2
DSI2 - dsi_out[2]
2
DSI_OUT3
DSI3 - dsi_out[3]
3
DSI_OUT4
DSI4 - dsi_out[4]
4
DSI_OUT5
DSI5 - dsi_out[5]
5
DSI_OUT6
DSI6 - dsi_out[6]
6
DSI_OUT7
DSI7 - dsi_out[7]
7
DSI_OUT8
DSI8 - dsi_out[8]
8
DSI_OUT9
DSI9 - dsi_out[9]
9
CLK_DSI_SELECT10
Clock DSI Select Register
0x328
32
read-write
n
0x0
0x0
DSI_MUX
Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
0
5
read-write
DSI_OUT0
DSI0 - dsi_out[0]
0
DSI_OUT1
DSI1 - dsi_out[1]
1
DSI_OUT10
DSI10 - dsi_out[10]
10
DSI_OUT11
DSI11 - dsi_out[11]
11
DSI_OUT12
DSI12 - dsi_out[12]
12
DSI_OUT13
DSI13 - dsi_out[13]
13
DSI_OUT14
DSI14 - dsi_out[14]
14
DSI_OUT15
DSI15 - dsi_out[15]
15
ILO
ILO - Internal Low-speed Oscillator
16
WCO
WCO - Watch-Crystal Oscillator
17
ALTLF
ALTLF - Alternate Low-Frequency Clock
18
PILO
PILO - Precision Internal Low-speed Oscillator
19
DSI_OUT2
DSI2 - dsi_out[2]
2
DSI_OUT3
DSI3 - dsi_out[3]
3
DSI_OUT4
DSI4 - dsi_out[4]
4
DSI_OUT5
DSI5 - dsi_out[5]
5
DSI_OUT6
DSI6 - dsi_out[6]
6
DSI_OUT7
DSI7 - dsi_out[7]
7
DSI_OUT8
DSI8 - dsi_out[8]
8
DSI_OUT9
DSI9 - dsi_out[9]
9
CLK_DSI_SELECT11
Clock DSI Select Register
0x32C
32
read-write
n
0x0
0x0
DSI_MUX
Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
0
5
read-write
DSI_OUT0
DSI0 - dsi_out[0]
0
DSI_OUT1
DSI1 - dsi_out[1]
1
DSI_OUT10
DSI10 - dsi_out[10]
10
DSI_OUT11
DSI11 - dsi_out[11]
11
DSI_OUT12
DSI12 - dsi_out[12]
12
DSI_OUT13
DSI13 - dsi_out[13]
13
DSI_OUT14
DSI14 - dsi_out[14]
14
DSI_OUT15
DSI15 - dsi_out[15]
15
ILO
ILO - Internal Low-speed Oscillator
16
WCO
WCO - Watch-Crystal Oscillator
17
ALTLF
ALTLF - Alternate Low-Frequency Clock
18
PILO
PILO - Precision Internal Low-speed Oscillator
19
DSI_OUT2
DSI2 - dsi_out[2]
2
DSI_OUT3
DSI3 - dsi_out[3]
3
DSI_OUT4
DSI4 - dsi_out[4]
4
DSI_OUT5
DSI5 - dsi_out[5]
5
DSI_OUT6
DSI6 - dsi_out[6]
6
DSI_OUT7
DSI7 - dsi_out[7]
7
DSI_OUT8
DSI8 - dsi_out[8]
8
DSI_OUT9
DSI9 - dsi_out[9]
9
CLK_DSI_SELECT12
Clock DSI Select Register
0x330
32
read-write
n
0x0
0x0
DSI_MUX
Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
0
5
read-write
DSI_OUT0
DSI0 - dsi_out[0]
0
DSI_OUT1
DSI1 - dsi_out[1]
1
DSI_OUT10
DSI10 - dsi_out[10]
10
DSI_OUT11
DSI11 - dsi_out[11]
11
DSI_OUT12
DSI12 - dsi_out[12]
12
DSI_OUT13
DSI13 - dsi_out[13]
13
DSI_OUT14
DSI14 - dsi_out[14]
14
DSI_OUT15
DSI15 - dsi_out[15]
15
ILO
ILO - Internal Low-speed Oscillator
16
WCO
WCO - Watch-Crystal Oscillator
17
ALTLF
ALTLF - Alternate Low-Frequency Clock
18
PILO
PILO - Precision Internal Low-speed Oscillator
19
DSI_OUT2
DSI2 - dsi_out[2]
2
DSI_OUT3
DSI3 - dsi_out[3]
3
DSI_OUT4
DSI4 - dsi_out[4]
4
DSI_OUT5
DSI5 - dsi_out[5]
5
DSI_OUT6
DSI6 - dsi_out[6]
6
DSI_OUT7
DSI7 - dsi_out[7]
7
DSI_OUT8
DSI8 - dsi_out[8]
8
DSI_OUT9
DSI9 - dsi_out[9]
9
CLK_DSI_SELECT13
Clock DSI Select Register
0x334
32
read-write
n
0x0
0x0
DSI_MUX
Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
0
5
read-write
DSI_OUT0
DSI0 - dsi_out[0]
0
DSI_OUT1
DSI1 - dsi_out[1]
1
DSI_OUT10
DSI10 - dsi_out[10]
10
DSI_OUT11
DSI11 - dsi_out[11]
11
DSI_OUT12
DSI12 - dsi_out[12]
12
DSI_OUT13
DSI13 - dsi_out[13]
13
DSI_OUT14
DSI14 - dsi_out[14]
14
DSI_OUT15
DSI15 - dsi_out[15]
15
ILO
ILO - Internal Low-speed Oscillator
16
WCO
WCO - Watch-Crystal Oscillator
17
ALTLF
ALTLF - Alternate Low-Frequency Clock
18
PILO
PILO - Precision Internal Low-speed Oscillator
19
DSI_OUT2
DSI2 - dsi_out[2]
2
DSI_OUT3
DSI3 - dsi_out[3]
3
DSI_OUT4
DSI4 - dsi_out[4]
4
DSI_OUT5
DSI5 - dsi_out[5]
5
DSI_OUT6
DSI6 - dsi_out[6]
6
DSI_OUT7
DSI7 - dsi_out[7]
7
DSI_OUT8
DSI8 - dsi_out[8]
8
DSI_OUT9
DSI9 - dsi_out[9]
9
CLK_DSI_SELECT14
Clock DSI Select Register
0x338
32
read-write
n
0x0
0x0
DSI_MUX
Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
0
5
read-write
DSI_OUT0
DSI0 - dsi_out[0]
0
DSI_OUT1
DSI1 - dsi_out[1]
1
DSI_OUT10
DSI10 - dsi_out[10]
10
DSI_OUT11
DSI11 - dsi_out[11]
11
DSI_OUT12
DSI12 - dsi_out[12]
12
DSI_OUT13
DSI13 - dsi_out[13]
13
DSI_OUT14
DSI14 - dsi_out[14]
14
DSI_OUT15
DSI15 - dsi_out[15]
15
ILO
ILO - Internal Low-speed Oscillator
16
WCO
WCO - Watch-Crystal Oscillator
17
ALTLF
ALTLF - Alternate Low-Frequency Clock
18
PILO
PILO - Precision Internal Low-speed Oscillator
19
DSI_OUT2
DSI2 - dsi_out[2]
2
DSI_OUT3
DSI3 - dsi_out[3]
3
DSI_OUT4
DSI4 - dsi_out[4]
4
DSI_OUT5
DSI5 - dsi_out[5]
5
DSI_OUT6
DSI6 - dsi_out[6]
6
DSI_OUT7
DSI7 - dsi_out[7]
7
DSI_OUT8
DSI8 - dsi_out[8]
8
DSI_OUT9
DSI9 - dsi_out[9]
9
CLK_DSI_SELECT15
Clock DSI Select Register
0x33C
32
read-write
n
0x0
0x0
DSI_MUX
Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
0
5
read-write
DSI_OUT0
DSI0 - dsi_out[0]
0
DSI_OUT1
DSI1 - dsi_out[1]
1
DSI_OUT10
DSI10 - dsi_out[10]
10
DSI_OUT11
DSI11 - dsi_out[11]
11
DSI_OUT12
DSI12 - dsi_out[12]
12
DSI_OUT13
DSI13 - dsi_out[13]
13
DSI_OUT14
DSI14 - dsi_out[14]
14
DSI_OUT15
DSI15 - dsi_out[15]
15
ILO
ILO - Internal Low-speed Oscillator
16
WCO
WCO - Watch-Crystal Oscillator
17
ALTLF
ALTLF - Alternate Low-Frequency Clock
18
PILO
PILO - Precision Internal Low-speed Oscillator
19
DSI_OUT2
DSI2 - dsi_out[2]
2
DSI_OUT3
DSI3 - dsi_out[3]
3
DSI_OUT4
DSI4 - dsi_out[4]
4
DSI_OUT5
DSI5 - dsi_out[5]
5
DSI_OUT6
DSI6 - dsi_out[6]
6
DSI_OUT7
DSI7 - dsi_out[7]
7
DSI_OUT8
DSI8 - dsi_out[8]
8
DSI_OUT9
DSI9 - dsi_out[9]
9
CLK_DSI_SELECT2
Clock DSI Select Register
0x308
32
read-write
n
0x0
0x0
DSI_MUX
Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
0
5
read-write
DSI_OUT0
DSI0 - dsi_out[0]
0
DSI_OUT1
DSI1 - dsi_out[1]
1
DSI_OUT10
DSI10 - dsi_out[10]
10
DSI_OUT11
DSI11 - dsi_out[11]
11
DSI_OUT12
DSI12 - dsi_out[12]
12
DSI_OUT13
DSI13 - dsi_out[13]
13
DSI_OUT14
DSI14 - dsi_out[14]
14
DSI_OUT15
DSI15 - dsi_out[15]
15
ILO
ILO - Internal Low-speed Oscillator
16
WCO
WCO - Watch-Crystal Oscillator
17
ALTLF
ALTLF - Alternate Low-Frequency Clock
18
PILO
PILO - Precision Internal Low-speed Oscillator
19
DSI_OUT2
DSI2 - dsi_out[2]
2
DSI_OUT3
DSI3 - dsi_out[3]
3
DSI_OUT4
DSI4 - dsi_out[4]
4
DSI_OUT5
DSI5 - dsi_out[5]
5
DSI_OUT6
DSI6 - dsi_out[6]
6
DSI_OUT7
DSI7 - dsi_out[7]
7
DSI_OUT8
DSI8 - dsi_out[8]
8
DSI_OUT9
DSI9 - dsi_out[9]
9
CLK_DSI_SELECT3
Clock DSI Select Register
0x30C
32
read-write
n
0x0
0x0
DSI_MUX
Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
0
5
read-write
DSI_OUT0
DSI0 - dsi_out[0]
0
DSI_OUT1
DSI1 - dsi_out[1]
1
DSI_OUT10
DSI10 - dsi_out[10]
10
DSI_OUT11
DSI11 - dsi_out[11]
11
DSI_OUT12
DSI12 - dsi_out[12]
12
DSI_OUT13
DSI13 - dsi_out[13]
13
DSI_OUT14
DSI14 - dsi_out[14]
14
DSI_OUT15
DSI15 - dsi_out[15]
15
ILO
ILO - Internal Low-speed Oscillator
16
WCO
WCO - Watch-Crystal Oscillator
17
ALTLF
ALTLF - Alternate Low-Frequency Clock
18
PILO
PILO - Precision Internal Low-speed Oscillator
19
DSI_OUT2
DSI2 - dsi_out[2]
2
DSI_OUT3
DSI3 - dsi_out[3]
3
DSI_OUT4
DSI4 - dsi_out[4]
4
DSI_OUT5
DSI5 - dsi_out[5]
5
DSI_OUT6
DSI6 - dsi_out[6]
6
DSI_OUT7
DSI7 - dsi_out[7]
7
DSI_OUT8
DSI8 - dsi_out[8]
8
DSI_OUT9
DSI9 - dsi_out[9]
9
CLK_DSI_SELECT4
Clock DSI Select Register
0x310
32
read-write
n
0x0
0x0
DSI_MUX
Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
0
5
read-write
DSI_OUT0
DSI0 - dsi_out[0]
0
DSI_OUT1
DSI1 - dsi_out[1]
1
DSI_OUT10
DSI10 - dsi_out[10]
10
DSI_OUT11
DSI11 - dsi_out[11]
11
DSI_OUT12
DSI12 - dsi_out[12]
12
DSI_OUT13
DSI13 - dsi_out[13]
13
DSI_OUT14
DSI14 - dsi_out[14]
14
DSI_OUT15
DSI15 - dsi_out[15]
15
ILO
ILO - Internal Low-speed Oscillator
16
WCO
WCO - Watch-Crystal Oscillator
17
ALTLF
ALTLF - Alternate Low-Frequency Clock
18
PILO
PILO - Precision Internal Low-speed Oscillator
19
DSI_OUT2
DSI2 - dsi_out[2]
2
DSI_OUT3
DSI3 - dsi_out[3]
3
DSI_OUT4
DSI4 - dsi_out[4]
4
DSI_OUT5
DSI5 - dsi_out[5]
5
DSI_OUT6
DSI6 - dsi_out[6]
6
DSI_OUT7
DSI7 - dsi_out[7]
7
DSI_OUT8
DSI8 - dsi_out[8]
8
DSI_OUT9
DSI9 - dsi_out[9]
9
CLK_DSI_SELECT5
Clock DSI Select Register
0x314
32
read-write
n
0x0
0x0
DSI_MUX
Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
0
5
read-write
DSI_OUT0
DSI0 - dsi_out[0]
0
DSI_OUT1
DSI1 - dsi_out[1]
1
DSI_OUT10
DSI10 - dsi_out[10]
10
DSI_OUT11
DSI11 - dsi_out[11]
11
DSI_OUT12
DSI12 - dsi_out[12]
12
DSI_OUT13
DSI13 - dsi_out[13]
13
DSI_OUT14
DSI14 - dsi_out[14]
14
DSI_OUT15
DSI15 - dsi_out[15]
15
ILO
ILO - Internal Low-speed Oscillator
16
WCO
WCO - Watch-Crystal Oscillator
17
ALTLF
ALTLF - Alternate Low-Frequency Clock
18
PILO
PILO - Precision Internal Low-speed Oscillator
19
DSI_OUT2
DSI2 - dsi_out[2]
2
DSI_OUT3
DSI3 - dsi_out[3]
3
DSI_OUT4
DSI4 - dsi_out[4]
4
DSI_OUT5
DSI5 - dsi_out[5]
5
DSI_OUT6
DSI6 - dsi_out[6]
6
DSI_OUT7
DSI7 - dsi_out[7]
7
DSI_OUT8
DSI8 - dsi_out[8]
8
DSI_OUT9
DSI9 - dsi_out[9]
9
CLK_DSI_SELECT6
Clock DSI Select Register
0x318
32
read-write
n
0x0
0x0
DSI_MUX
Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
0
5
read-write
DSI_OUT0
DSI0 - dsi_out[0]
0
DSI_OUT1
DSI1 - dsi_out[1]
1
DSI_OUT10
DSI10 - dsi_out[10]
10
DSI_OUT11
DSI11 - dsi_out[11]
11
DSI_OUT12
DSI12 - dsi_out[12]
12
DSI_OUT13
DSI13 - dsi_out[13]
13
DSI_OUT14
DSI14 - dsi_out[14]
14
DSI_OUT15
DSI15 - dsi_out[15]
15
ILO
ILO - Internal Low-speed Oscillator
16
WCO
WCO - Watch-Crystal Oscillator
17
ALTLF
ALTLF - Alternate Low-Frequency Clock
18
PILO
PILO - Precision Internal Low-speed Oscillator
19
DSI_OUT2
DSI2 - dsi_out[2]
2
DSI_OUT3
DSI3 - dsi_out[3]
3
DSI_OUT4
DSI4 - dsi_out[4]
4
DSI_OUT5
DSI5 - dsi_out[5]
5
DSI_OUT6
DSI6 - dsi_out[6]
6
DSI_OUT7
DSI7 - dsi_out[7]
7
DSI_OUT8
DSI8 - dsi_out[8]
8
DSI_OUT9
DSI9 - dsi_out[9]
9
CLK_DSI_SELECT7
Clock DSI Select Register
0x31C
32
read-write
n
0x0
0x0
DSI_MUX
Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
0
5
read-write
DSI_OUT0
DSI0 - dsi_out[0]
0
DSI_OUT1
DSI1 - dsi_out[1]
1
DSI_OUT10
DSI10 - dsi_out[10]
10
DSI_OUT11
DSI11 - dsi_out[11]
11
DSI_OUT12
DSI12 - dsi_out[12]
12
DSI_OUT13
DSI13 - dsi_out[13]
13
DSI_OUT14
DSI14 - dsi_out[14]
14
DSI_OUT15
DSI15 - dsi_out[15]
15
ILO
ILO - Internal Low-speed Oscillator
16
WCO
WCO - Watch-Crystal Oscillator
17
ALTLF
ALTLF - Alternate Low-Frequency Clock
18
PILO
PILO - Precision Internal Low-speed Oscillator
19
DSI_OUT2
DSI2 - dsi_out[2]
2
DSI_OUT3
DSI3 - dsi_out[3]
3
DSI_OUT4
DSI4 - dsi_out[4]
4
DSI_OUT5
DSI5 - dsi_out[5]
5
DSI_OUT6
DSI6 - dsi_out[6]
6
DSI_OUT7
DSI7 - dsi_out[7]
7
DSI_OUT8
DSI8 - dsi_out[8]
8
DSI_OUT9
DSI9 - dsi_out[9]
9
CLK_DSI_SELECT8
Clock DSI Select Register
0x320
32
read-write
n
0x0
0x0
DSI_MUX
Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
0
5
read-write
DSI_OUT0
DSI0 - dsi_out[0]
0
DSI_OUT1
DSI1 - dsi_out[1]
1
DSI_OUT10
DSI10 - dsi_out[10]
10
DSI_OUT11
DSI11 - dsi_out[11]
11
DSI_OUT12
DSI12 - dsi_out[12]
12
DSI_OUT13
DSI13 - dsi_out[13]
13
DSI_OUT14
DSI14 - dsi_out[14]
14
DSI_OUT15
DSI15 - dsi_out[15]
15
ILO
ILO - Internal Low-speed Oscillator
16
WCO
WCO - Watch-Crystal Oscillator
17
ALTLF
ALTLF - Alternate Low-Frequency Clock
18
PILO
PILO - Precision Internal Low-speed Oscillator
19
DSI_OUT2
DSI2 - dsi_out[2]
2
DSI_OUT3
DSI3 - dsi_out[3]
3
DSI_OUT4
DSI4 - dsi_out[4]
4
DSI_OUT5
DSI5 - dsi_out[5]
5
DSI_OUT6
DSI6 - dsi_out[6]
6
DSI_OUT7
DSI7 - dsi_out[7]
7
DSI_OUT8
DSI8 - dsi_out[8]
8
DSI_OUT9
DSI9 - dsi_out[9]
9
CLK_DSI_SELECT9
Clock DSI Select Register
0x324
32
read-write
n
0x0
0x0
DSI_MUX
Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_PATH_SELECT register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock.
0
5
read-write
DSI_OUT0
DSI0 - dsi_out[0]
0
DSI_OUT1
DSI1 - dsi_out[1]
1
DSI_OUT10
DSI10 - dsi_out[10]
10
DSI_OUT11
DSI11 - dsi_out[11]
11
DSI_OUT12
DSI12 - dsi_out[12]
12
DSI_OUT13
DSI13 - dsi_out[13]
13
DSI_OUT14
DSI14 - dsi_out[14]
14
DSI_OUT15
DSI15 - dsi_out[15]
15
ILO
ILO - Internal Low-speed Oscillator
16
WCO
WCO - Watch-Crystal Oscillator
17
ALTLF
ALTLF - Alternate Low-Frequency Clock
18
PILO
PILO - Precision Internal Low-speed Oscillator
19
DSI_OUT2
DSI2 - dsi_out[2]
2
DSI_OUT3
DSI3 - dsi_out[3]
3
DSI_OUT4
DSI4 - dsi_out[4]
4
DSI_OUT5
DSI5 - dsi_out[5]
5
DSI_OUT6
DSI6 - dsi_out[6]
6
DSI_OUT7
DSI7 - dsi_out[7]
7
DSI_OUT8
DSI8 - dsi_out[8]
8
DSI_OUT9
DSI9 - dsi_out[9]
9
CLK_ECO_CONFIG
ECO Configuration Register
0x52C
32
read-write
n
0x0
0x0
AGC_EN
Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM. When low, the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal.
1
2
read-write
ECO_EN
Master enable for ECO oscillator.
31
32
read-write
CLK_ECO_STATUS
ECO Status Register
0x530
32
read-only
n
0x0
0x0
ECO_OK
Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec.
0
1
read-only
ECO_READY
Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled, and it does not check the ECO output. It is recommended to also confirm ECO_OK==1.
1
2
read-only
CLK_FLL_CONFIG
FLL Configuration Register
0x580
32
read-write
n
0x0
0x0
FLL_ENABLE
Master enable for FLL. The FLL requires firmware sequencing when enabling, disabling, and entering/exiting DEEPSLEEP. To enable the FLL, first enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1 and wait until CLK_FLL_STATUS.CCO_READY==1. Next, ensure the reference clock has stabilized and CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF. Next, write FLL_ENABLE=1 and wait until CLK_FLL_STATUS.LOCKED==1. Finally, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. It takes seven reference clock cycles plus four FLL output cycles to switch to the FLL output. Do not disable the FLL before this time completes. To disable the FLL, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF and (optionally) read the same register to ensure the write completes. Then, wait at least seven FLL reference clock cycles before disabling it with FLL_ENABLE=0. Lastly, disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0. Before entering DEEPSLEEP, either disable the FLL using above sequence or use the following procedure to deselect/select it before/after DEEPSLEEP. Before entering DEEPSLEEP, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF to change the FLL to use its reference clock. After DEEPSLEEP wakeup, wait until CLK_FLL_STATUS.LOCKED==1 and then write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. 0: Block is powered off 1: Block is powered on
31
32
read-write
FLL_MULT
Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref). Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1)
0
18
read-write
FLL_OUTPUT_DIV
Control bits for Output divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: no division 1: divide by 2
24
25
read-write
CLK_FLL_CONFIG2
FLL Configuration Register 2
0x584
32
read-write
n
0x0
0x0
FLL_REF_DIV
Control bits for reference divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 8191: divide by 8191
0
13
read-write
LOCK_TOL
Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or to track a less accurate source. The tolerance should be set so that the FLL does not unlock under normal conditions. The tolerance is the allowed difference between the count value for the ideal formula and the measured value. 0: tolerate error of 1 count value 1: tolerate error of 2 count values ... 511: tolerate error of 512 count values
16
25
read-write
CLK_FLL_CONFIG3
FLL Configuration Register 3
0x588
32
read-write
n
0x0
0x0
BYPASS_SEL
Bypass mux located just after FLL output. See FLL_ENABLE description for instructions on how to use this field when enabling/disabling the FLL.
28
30
read-write
AUTO
N/A
0
AUTO1
N/A
1
FLL_REF
Select FLL reference input (bypass mode). Ignores lock indicator
2
FLL_OUT
Select FLL output. Ignores lock indicator.
3
FLL_LF_IGAIN
FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal
0
4
read-write
FLL_LF_PGAIN
FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal
4
8
read-write
SETTLING_COUNT
Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case. 0: no settling time 1: wait one reference clock cycle ... 8191: wait 8191 reference clock cycles
8
21
read-write
CLK_FLL_CONFIG4
FLL Configuration Register 4
0x58C
32
read-write
n
0x0
0x0
CCO_ENABLE
Enable the CCO. It is required to enable the CCO before using the FLL. 0: Block is powered off 1: Block is powered on
31
32
read-write
CCO_FREQ
CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range.
16
25
read-write
CCO_HW_UPDATE_DIS
Disable CCO frequency update by FLL hardware 0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation. 1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation.
30
31
read-write
CCO_LIMIT
Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support)
0
8
read-write
CCO_RANGE
Frequency range of CCO
8
11
read-write
RANGE0
Target frequency is in range [48, 64) MHz
0
RANGE1
Target frequency is in range [64, 85) MHz
1
RANGE2
Target frequency is in range [85, 113) MHz
2
RANGE3
Target frequency is in range [113, 150) MHz
3
RANGE4
Target frequency is in range [150, 200] MHz
4
CLK_FLL_STATUS
FLL Status Register
0x590
32
read-write
n
0x0
0x0
CCO_READY
This indicates that the CCO is internally settled and ready to use.
2
3
read-only
LOCKED
FLL Lock Indicator. LOCKED is high when FLL is within CLK_FLL_CONFIG2.LOCK_TOL. If FLL is outside LOCK_TOL, LOCKED goes low. Note that this can happen during normal operation, if FLL needs to recalculate due to a change in the reference clock, change in voltage, or change in temperature.
0
1
read-only
UNLOCK_OCCURRED
N/A
1
2
read-write
CLK_ILO_CONFIG
ILO Configuration
0x50C
32
read-write
n
0x0
0x0
ENABLE
Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. After enabling, it takes at most two cycles to reach the accuracy spec.
31
32
read-write
ILO_BACKUP
If backup domain is present on this product, this register indicates that ILO should stay enabled for use by backup domain during XRES, HIBERNATE mode, and through power-related resets like BOD on VDDD/VCCD. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. 0: ILO turns off at XRES/BOD event or HIBERNATE entry. 1: ILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry.
0
1
read-write
CLK_IMO_CONFIG
IMO Configuration
0x510
32
read-write
n
0x0
0x0
ENABLE
Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during HIBERNATE and XRES. It will automatically disable during DEEPSLEEP if DPSLP_ENABLE==0.
31
32
read-write
CLK_OUTPUT_FAST
Fast Clock Output Select Register
0x514
32
read-write
n
0x0
0x0
FAST_SEL0
Select signal for fast clock output #0
0
4
read-write
NC
Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0.
0
ECO
External Crystal Oscillator (ECO)
1
EXTCLK
External clock input (EXTCLK)
2
ALTHF
Alternate High-Frequency (ALTHF) clock input to SRSS
3
TIMERCLK
Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse.
4
PATH_SEL0
Selects the clock path chosen by PATH_SEL0 field
5
HFCLK_SEL0
Selects the output of the HFCLK_SEL0 mux
6
SLOW_SEL0
Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0
7
FAST_SEL1
Select signal for fast clock output #1
16
20
read-write
NC
Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1.
0
ECO
External Crystal Oscillator (ECO)
1
EXTCLK
External clock input (EXTCLK)
2
ALTHF
Alternate High-Frequency (ALTHF) clock input to SRSS
3
TIMERCLK
Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse.
4
PATH_SEL1
Selects the clock path chosen by PATH_SEL1 field
5
HFCLK_SEL1
Selects the output of the HFCLK_SEL1 mux
6
SLOW_SEL1
Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1
7
HFCLK_SEL0
Selects a HFCLK tree for use in fast clock output #0
8
12
read-write
HFCLK_SEL1
Selects a HFCLK tree for use in fast clock output #1 logic
24
28
read-write
PATH_SEL0
Selects a clock path to use in fast clock output #0 logic. 0: FLL output 1-15: PLL output on path1-path15 (if available)
4
8
read-write
PATH_SEL1
Selects a clock path to use in fast clock output #1 logic. 0: FLL output 1-15: PLL output on path1-path15 (if available)
20
24
read-write
CLK_OUTPUT_SLOW
Slow Clock Output Select Register
0x518
32
read-write
n
0x0
0x0
SLOW_SEL0
Select signal for slow clock output #0
0
4
read-write
NC
Disabled - output is 0. For power savings, clocks are blocked before entering any muxes.
0
ILO
Internal Low Speed Oscillator (ILO)
1
WCO
Watch-Crystal Oscillator (WCO)
2
BAK
Root of the Backup domain clock tree (BAK)
3
ALTLF
Alternate low-frequency clock input to SRSS (ALTLF)
4
LFCLK
Root of the low-speed clock tree (LFCLK)
5
IMO
Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.
6
SLPCTRL
Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.
7
PILO
Precision Internal Low Speed Oscillator (PILO)
8
SLOW_SEL1
Select signal for slow clock output #1
4
8
read-write
NC
Disabled - output is 0. For power savings, clocks are blocked before entering any muxes.
0
ILO
Internal Low Speed Oscillator (ILO)
1
WCO
Watch-Crystal Oscillator (WCO)
2
BAK
Root of the Backup domain clock tree (BAK)
3
ALTLF
Alternate low-frequency clock input to SRSS (ALTLF)
4
LFCLK
Root of the low-speed clock tree (LFCLK)
5
IMO
Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.
6
SLPCTRL
Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.
7
PILO
Precision Internal Low Speed Oscillator (PILO)
8
CLK_PATH_SELECT0
Clock Path Select Register
0x340
32
read-write
n
0x0
0x0
PATH_MUX
Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
3
read-write
IMO
IMO - Internal R/C Oscillator
0
EXTCLK
EXTCLK - External Clock Pin
1
ECO
ECO - External-Crystal Oscillator
2
ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
3
DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
4
CLK_PATH_SELECT1
Clock Path Select Register
0x344
32
read-write
n
0x0
0x0
PATH_MUX
Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
3
read-write
IMO
IMO - Internal R/C Oscillator
0
EXTCLK
EXTCLK - External Clock Pin
1
ECO
ECO - External-Crystal Oscillator
2
ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
3
DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
4
CLK_PATH_SELECT10
Clock Path Select Register
0x368
32
read-write
n
0x0
0x0
PATH_MUX
Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
3
read-write
IMO
IMO - Internal R/C Oscillator
0
EXTCLK
EXTCLK - External Clock Pin
1
ECO
ECO - External-Crystal Oscillator
2
ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
3
DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
4
CLK_PATH_SELECT11
Clock Path Select Register
0x36C
32
read-write
n
0x0
0x0
PATH_MUX
Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
3
read-write
IMO
IMO - Internal R/C Oscillator
0
EXTCLK
EXTCLK - External Clock Pin
1
ECO
ECO - External-Crystal Oscillator
2
ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
3
DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
4
CLK_PATH_SELECT12
Clock Path Select Register
0x370
32
read-write
n
0x0
0x0
PATH_MUX
Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
3
read-write
IMO
IMO - Internal R/C Oscillator
0
EXTCLK
EXTCLK - External Clock Pin
1
ECO
ECO - External-Crystal Oscillator
2
ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
3
DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
4
CLK_PATH_SELECT13
Clock Path Select Register
0x374
32
read-write
n
0x0
0x0
PATH_MUX
Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
3
read-write
IMO
IMO - Internal R/C Oscillator
0
EXTCLK
EXTCLK - External Clock Pin
1
ECO
ECO - External-Crystal Oscillator
2
ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
3
DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
4
CLK_PATH_SELECT14
Clock Path Select Register
0x378
32
read-write
n
0x0
0x0
PATH_MUX
Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
3
read-write
IMO
IMO - Internal R/C Oscillator
0
EXTCLK
EXTCLK - External Clock Pin
1
ECO
ECO - External-Crystal Oscillator
2
ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
3
DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
4
CLK_PATH_SELECT15
Clock Path Select Register
0x37C
32
read-write
n
0x0
0x0
PATH_MUX
Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
3
read-write
IMO
IMO - Internal R/C Oscillator
0
EXTCLK
EXTCLK - External Clock Pin
1
ECO
ECO - External-Crystal Oscillator
2
ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
3
DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
4
CLK_PATH_SELECT2
Clock Path Select Register
0x348
32
read-write
n
0x0
0x0
PATH_MUX
Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
3
read-write
IMO
IMO - Internal R/C Oscillator
0
EXTCLK
EXTCLK - External Clock Pin
1
ECO
ECO - External-Crystal Oscillator
2
ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
3
DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
4
CLK_PATH_SELECT3
Clock Path Select Register
0x34C
32
read-write
n
0x0
0x0
PATH_MUX
Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
3
read-write
IMO
IMO - Internal R/C Oscillator
0
EXTCLK
EXTCLK - External Clock Pin
1
ECO
ECO - External-Crystal Oscillator
2
ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
3
DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
4
CLK_PATH_SELECT4
Clock Path Select Register
0x350
32
read-write
n
0x0
0x0
PATH_MUX
Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
3
read-write
IMO
IMO - Internal R/C Oscillator
0
EXTCLK
EXTCLK - External Clock Pin
1
ECO
ECO - External-Crystal Oscillator
2
ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
3
DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
4
CLK_PATH_SELECT5
Clock Path Select Register
0x354
32
read-write
n
0x0
0x0
PATH_MUX
Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
3
read-write
IMO
IMO - Internal R/C Oscillator
0
EXTCLK
EXTCLK - External Clock Pin
1
ECO
ECO - External-Crystal Oscillator
2
ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
3
DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
4
CLK_PATH_SELECT6
Clock Path Select Register
0x358
32
read-write
n
0x0
0x0
PATH_MUX
Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
3
read-write
IMO
IMO - Internal R/C Oscillator
0
EXTCLK
EXTCLK - External Clock Pin
1
ECO
ECO - External-Crystal Oscillator
2
ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
3
DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
4
CLK_PATH_SELECT7
Clock Path Select Register
0x35C
32
read-write
n
0x0
0x0
PATH_MUX
Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
3
read-write
IMO
IMO - Internal R/C Oscillator
0
EXTCLK
EXTCLK - External Clock Pin
1
ECO
ECO - External-Crystal Oscillator
2
ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
3
DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
4
CLK_PATH_SELECT8
Clock Path Select Register
0x360
32
read-write
n
0x0
0x0
PATH_MUX
Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
3
read-write
IMO
IMO - Internal R/C Oscillator
0
EXTCLK
EXTCLK - External Clock Pin
1
ECO
ECO - External-Crystal Oscillator
2
ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
3
DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
4
CLK_PATH_SELECT9
Clock Path Select Register
0x364
32
read-write
n
0x0
0x0
PATH_MUX
Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
3
read-write
IMO
IMO - Internal R/C Oscillator
0
EXTCLK
EXTCLK - External Clock Pin
1
ECO
ECO - External-Crystal Oscillator
2
ALTHF
ALTHF - Alternate High-Frequency clock input (product-specific clock)
3
DSI_MUX
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
4
CLK_PILO_CONFIG
Precision ILO Configuration Register
0x53C
32
read-write
n
0x0
0x0
PILO_CLK_EN
Enable the PILO clock output. See PILO_EN field for required sequencing.
29
30
read-write
PILO_EN
Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle.
31
32
read-write
PILO_FFREQ
Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz.
0
10
read-write
PILO_RESET_N
Reset the PILO. See PILO_EN field for required sequencing.
30
31
read-write
CLK_PLL_CONFIG0
PLL Configuration Register
0x600
32
read-write
n
0x0
0x0
BYPASS_SEL
Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
28
30
read-write
AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
0
AUTO1
Same as AUTO
1
PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
2
PLL_OUT
Select PLL output. Ignores lock indicator.
3
ENABLE
Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
31
32
read-write
FEEDBACK_DIV
Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
0
7
read-write
OUTPUT_DIV
Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
16
21
read-write
PLL_LF_MODE
VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
27
28
read-write
REFERENCE_DIV
Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
8
13
read-write
CLK_PLL_CONFIG1
PLL Configuration Register
0x604
32
read-write
n
0x0
0x0
BYPASS_SEL
Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
28
30
read-write
AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
0
AUTO1
Same as AUTO
1
PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
2
PLL_OUT
Select PLL output. Ignores lock indicator.
3
ENABLE
Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
31
32
read-write
FEEDBACK_DIV
Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
0
7
read-write
OUTPUT_DIV
Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
16
21
read-write
PLL_LF_MODE
VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
27
28
read-write
REFERENCE_DIV
Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
8
13
read-write
CLK_PLL_CONFIG10
PLL Configuration Register
0x628
32
read-write
n
0x0
0x0
BYPASS_SEL
Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
28
30
read-write
AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
0
AUTO1
Same as AUTO
1
PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
2
PLL_OUT
Select PLL output. Ignores lock indicator.
3
ENABLE
Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
31
32
read-write
FEEDBACK_DIV
Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
0
7
read-write
OUTPUT_DIV
Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
16
21
read-write
PLL_LF_MODE
VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
27
28
read-write
REFERENCE_DIV
Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
8
13
read-write
CLK_PLL_CONFIG11
PLL Configuration Register
0x62C
32
read-write
n
0x0
0x0
BYPASS_SEL
Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
28
30
read-write
AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
0
AUTO1
Same as AUTO
1
PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
2
PLL_OUT
Select PLL output. Ignores lock indicator.
3
ENABLE
Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
31
32
read-write
FEEDBACK_DIV
Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
0
7
read-write
OUTPUT_DIV
Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
16
21
read-write
PLL_LF_MODE
VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
27
28
read-write
REFERENCE_DIV
Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
8
13
read-write
CLK_PLL_CONFIG12
PLL Configuration Register
0x630
32
read-write
n
0x0
0x0
BYPASS_SEL
Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
28
30
read-write
AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
0
AUTO1
Same as AUTO
1
PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
2
PLL_OUT
Select PLL output. Ignores lock indicator.
3
ENABLE
Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
31
32
read-write
FEEDBACK_DIV
Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
0
7
read-write
OUTPUT_DIV
Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
16
21
read-write
PLL_LF_MODE
VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
27
28
read-write
REFERENCE_DIV
Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
8
13
read-write
CLK_PLL_CONFIG13
PLL Configuration Register
0x634
32
read-write
n
0x0
0x0
BYPASS_SEL
Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
28
30
read-write
AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
0
AUTO1
Same as AUTO
1
PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
2
PLL_OUT
Select PLL output. Ignores lock indicator.
3
ENABLE
Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
31
32
read-write
FEEDBACK_DIV
Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
0
7
read-write
OUTPUT_DIV
Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
16
21
read-write
PLL_LF_MODE
VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
27
28
read-write
REFERENCE_DIV
Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
8
13
read-write
CLK_PLL_CONFIG14
PLL Configuration Register
0x638
32
read-write
n
0x0
0x0
BYPASS_SEL
Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
28
30
read-write
AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
0
AUTO1
Same as AUTO
1
PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
2
PLL_OUT
Select PLL output. Ignores lock indicator.
3
ENABLE
Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
31
32
read-write
FEEDBACK_DIV
Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
0
7
read-write
OUTPUT_DIV
Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
16
21
read-write
PLL_LF_MODE
VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
27
28
read-write
REFERENCE_DIV
Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
8
13
read-write
CLK_PLL_CONFIG2
PLL Configuration Register
0x608
32
read-write
n
0x0
0x0
BYPASS_SEL
Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
28
30
read-write
AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
0
AUTO1
Same as AUTO
1
PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
2
PLL_OUT
Select PLL output. Ignores lock indicator.
3
ENABLE
Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
31
32
read-write
FEEDBACK_DIV
Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
0
7
read-write
OUTPUT_DIV
Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
16
21
read-write
PLL_LF_MODE
VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
27
28
read-write
REFERENCE_DIV
Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
8
13
read-write
CLK_PLL_CONFIG3
PLL Configuration Register
0x60C
32
read-write
n
0x0
0x0
BYPASS_SEL
Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
28
30
read-write
AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
0
AUTO1
Same as AUTO
1
PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
2
PLL_OUT
Select PLL output. Ignores lock indicator.
3
ENABLE
Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
31
32
read-write
FEEDBACK_DIV
Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
0
7
read-write
OUTPUT_DIV
Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
16
21
read-write
PLL_LF_MODE
VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
27
28
read-write
REFERENCE_DIV
Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
8
13
read-write
CLK_PLL_CONFIG4
PLL Configuration Register
0x610
32
read-write
n
0x0
0x0
BYPASS_SEL
Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
28
30
read-write
AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
0
AUTO1
Same as AUTO
1
PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
2
PLL_OUT
Select PLL output. Ignores lock indicator.
3
ENABLE
Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
31
32
read-write
FEEDBACK_DIV
Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
0
7
read-write
OUTPUT_DIV
Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
16
21
read-write
PLL_LF_MODE
VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
27
28
read-write
REFERENCE_DIV
Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
8
13
read-write
CLK_PLL_CONFIG5
PLL Configuration Register
0x614
32
read-write
n
0x0
0x0
BYPASS_SEL
Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
28
30
read-write
AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
0
AUTO1
Same as AUTO
1
PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
2
PLL_OUT
Select PLL output. Ignores lock indicator.
3
ENABLE
Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
31
32
read-write
FEEDBACK_DIV
Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
0
7
read-write
OUTPUT_DIV
Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
16
21
read-write
PLL_LF_MODE
VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
27
28
read-write
REFERENCE_DIV
Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
8
13
read-write
CLK_PLL_CONFIG6
PLL Configuration Register
0x618
32
read-write
n
0x0
0x0
BYPASS_SEL
Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
28
30
read-write
AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
0
AUTO1
Same as AUTO
1
PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
2
PLL_OUT
Select PLL output. Ignores lock indicator.
3
ENABLE
Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
31
32
read-write
FEEDBACK_DIV
Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
0
7
read-write
OUTPUT_DIV
Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
16
21
read-write
PLL_LF_MODE
VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
27
28
read-write
REFERENCE_DIV
Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
8
13
read-write
CLK_PLL_CONFIG7
PLL Configuration Register
0x61C
32
read-write
n
0x0
0x0
BYPASS_SEL
Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
28
30
read-write
AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
0
AUTO1
Same as AUTO
1
PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
2
PLL_OUT
Select PLL output. Ignores lock indicator.
3
ENABLE
Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
31
32
read-write
FEEDBACK_DIV
Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
0
7
read-write
OUTPUT_DIV
Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
16
21
read-write
PLL_LF_MODE
VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
27
28
read-write
REFERENCE_DIV
Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
8
13
read-write
CLK_PLL_CONFIG8
PLL Configuration Register
0x620
32
read-write
n
0x0
0x0
BYPASS_SEL
Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
28
30
read-write
AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
0
AUTO1
Same as AUTO
1
PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
2
PLL_OUT
Select PLL output. Ignores lock indicator.
3
ENABLE
Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
31
32
read-write
FEEDBACK_DIV
Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
0
7
read-write
OUTPUT_DIV
Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
16
21
read-write
PLL_LF_MODE
VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
27
28
read-write
REFERENCE_DIV
Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
8
13
read-write
CLK_PLL_CONFIG9
PLL Configuration Register
0x624
32
read-write
n
0x0
0x0
BYPASS_SEL
Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running.
28
30
read-write
AUTO
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
0
AUTO1
Same as AUTO
1
PLL_REF
Select PLL reference input (bypass mode). Ignores lock indicator
2
PLL_OUT
Select PLL output. Ignores lock indicator.
3
ENABLE
Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled
31
32
read-write
FEEDBACK_DIV
Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior)
0
7
read-write
OUTPUT_DIV
Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior)
16
21
read-write
PLL_LF_MODE
VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz)
27
28
read-write
REFERENCE_DIV
Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior)
8
13
read-write
CLK_PLL_STATUS0
PLL Status Register
0x640
32
read-write
n
0x0
0x0
LOCKED
PLL Lock Indicator
0
1
read-only
UNLOCK_OCCURRED
This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
1
2
read-write
CLK_PLL_STATUS1
PLL Status Register
0x644
32
read-write
n
0x0
0x0
LOCKED
PLL Lock Indicator
0
1
read-only
UNLOCK_OCCURRED
This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
1
2
read-write
CLK_PLL_STATUS10
PLL Status Register
0x668
32
read-write
n
0x0
0x0
LOCKED
PLL Lock Indicator
0
1
read-only
UNLOCK_OCCURRED
This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
1
2
read-write
CLK_PLL_STATUS11
PLL Status Register
0x66C
32
read-write
n
0x0
0x0
LOCKED
PLL Lock Indicator
0
1
read-only
UNLOCK_OCCURRED
This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
1
2
read-write
CLK_PLL_STATUS12
PLL Status Register
0x670
32
read-write
n
0x0
0x0
LOCKED
PLL Lock Indicator
0
1
read-only
UNLOCK_OCCURRED
This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
1
2
read-write
CLK_PLL_STATUS13
PLL Status Register
0x674
32
read-write
n
0x0
0x0
LOCKED
PLL Lock Indicator
0
1
read-only
UNLOCK_OCCURRED
This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
1
2
read-write
CLK_PLL_STATUS14
PLL Status Register
0x678
32
read-write
n
0x0
0x0
LOCKED
PLL Lock Indicator
0
1
read-only
UNLOCK_OCCURRED
This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
1
2
read-write
CLK_PLL_STATUS2
PLL Status Register
0x648
32
read-write
n
0x0
0x0
LOCKED
PLL Lock Indicator
0
1
read-only
UNLOCK_OCCURRED
This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
1
2
read-write
CLK_PLL_STATUS3
PLL Status Register
0x64C
32
read-write
n
0x0
0x0
LOCKED
PLL Lock Indicator
0
1
read-only
UNLOCK_OCCURRED
This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
1
2
read-write
CLK_PLL_STATUS4
PLL Status Register
0x650
32
read-write
n
0x0
0x0
LOCKED
PLL Lock Indicator
0
1
read-only
UNLOCK_OCCURRED
This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
1
2
read-write
CLK_PLL_STATUS5
PLL Status Register
0x654
32
read-write
n
0x0
0x0
LOCKED
PLL Lock Indicator
0
1
read-only
UNLOCK_OCCURRED
This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
1
2
read-write
CLK_PLL_STATUS6
PLL Status Register
0x658
32
read-write
n
0x0
0x0
LOCKED
PLL Lock Indicator
0
1
read-only
UNLOCK_OCCURRED
This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
1
2
read-write
CLK_PLL_STATUS7
PLL Status Register
0x65C
32
read-write
n
0x0
0x0
LOCKED
PLL Lock Indicator
0
1
read-only
UNLOCK_OCCURRED
This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
1
2
read-write
CLK_PLL_STATUS8
PLL Status Register
0x660
32
read-write
n
0x0
0x0
LOCKED
PLL Lock Indicator
0
1
read-only
UNLOCK_OCCURRED
This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
1
2
read-write
CLK_PLL_STATUS9
PLL Status Register
0x664
32
read-write
n
0x0
0x0
LOCKED
PLL Lock Indicator
0
1
read-only
UNLOCK_OCCURRED
This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
1
2
read-write
CLK_ROOT_SELECT0
Clock Root Select Register
0x380
32
read-write
n
0x0
0x0
ENABLE
Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
31
32
read-write
ROOT_DIV
Selects predivider value for this clock root and DSI input.
4
6
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
0
DIV_BY_2
Divide selected clock source by 2
1
DIV_BY_4
Divide selected clock source by 4
2
DIV_BY_8
Divide selected clock source by 8
3
ROOT_MUX
Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
4
read-write
PATH0
Select PATH0 (can be configured for FLL)
0
PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
1
PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
10
PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
11
PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
12
PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
13
PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
14
PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
15
PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
2
PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
3
PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
4
PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
5
PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
6
PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
7
PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
8
PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
9
CLK_ROOT_SELECT1
Clock Root Select Register
0x384
32
read-write
n
0x0
0x0
ENABLE
Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
31
32
read-write
ROOT_DIV
Selects predivider value for this clock root and DSI input.
4
6
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
0
DIV_BY_2
Divide selected clock source by 2
1
DIV_BY_4
Divide selected clock source by 4
2
DIV_BY_8
Divide selected clock source by 8
3
ROOT_MUX
Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
4
read-write
PATH0
Select PATH0 (can be configured for FLL)
0
PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
1
PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
10
PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
11
PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
12
PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
13
PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
14
PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
15
PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
2
PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
3
PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
4
PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
5
PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
6
PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
7
PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
8
PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
9
CLK_ROOT_SELECT10
Clock Root Select Register
0x3A8
32
read-write
n
0x0
0x0
ENABLE
Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
31
32
read-write
ROOT_DIV
Selects predivider value for this clock root and DSI input.
4
6
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
0
DIV_BY_2
Divide selected clock source by 2
1
DIV_BY_4
Divide selected clock source by 4
2
DIV_BY_8
Divide selected clock source by 8
3
ROOT_MUX
Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
4
read-write
PATH0
Select PATH0 (can be configured for FLL)
0
PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
1
PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
10
PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
11
PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
12
PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
13
PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
14
PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
15
PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
2
PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
3
PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
4
PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
5
PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
6
PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
7
PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
8
PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
9
CLK_ROOT_SELECT11
Clock Root Select Register
0x3AC
32
read-write
n
0x0
0x0
ENABLE
Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
31
32
read-write
ROOT_DIV
Selects predivider value for this clock root and DSI input.
4
6
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
0
DIV_BY_2
Divide selected clock source by 2
1
DIV_BY_4
Divide selected clock source by 4
2
DIV_BY_8
Divide selected clock source by 8
3
ROOT_MUX
Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
4
read-write
PATH0
Select PATH0 (can be configured for FLL)
0
PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
1
PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
10
PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
11
PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
12
PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
13
PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
14
PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
15
PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
2
PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
3
PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
4
PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
5
PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
6
PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
7
PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
8
PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
9
CLK_ROOT_SELECT12
Clock Root Select Register
0x3B0
32
read-write
n
0x0
0x0
ENABLE
Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
31
32
read-write
ROOT_DIV
Selects predivider value for this clock root and DSI input.
4
6
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
0
DIV_BY_2
Divide selected clock source by 2
1
DIV_BY_4
Divide selected clock source by 4
2
DIV_BY_8
Divide selected clock source by 8
3
ROOT_MUX
Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
4
read-write
PATH0
Select PATH0 (can be configured for FLL)
0
PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
1
PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
10
PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
11
PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
12
PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
13
PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
14
PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
15
PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
2
PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
3
PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
4
PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
5
PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
6
PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
7
PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
8
PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
9
CLK_ROOT_SELECT13
Clock Root Select Register
0x3B4
32
read-write
n
0x0
0x0
ENABLE
Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
31
32
read-write
ROOT_DIV
Selects predivider value for this clock root and DSI input.
4
6
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
0
DIV_BY_2
Divide selected clock source by 2
1
DIV_BY_4
Divide selected clock source by 4
2
DIV_BY_8
Divide selected clock source by 8
3
ROOT_MUX
Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
4
read-write
PATH0
Select PATH0 (can be configured for FLL)
0
PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
1
PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
10
PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
11
PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
12
PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
13
PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
14
PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
15
PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
2
PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
3
PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
4
PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
5
PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
6
PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
7
PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
8
PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
9
CLK_ROOT_SELECT14
Clock Root Select Register
0x3B8
32
read-write
n
0x0
0x0
ENABLE
Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
31
32
read-write
ROOT_DIV
Selects predivider value for this clock root and DSI input.
4
6
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
0
DIV_BY_2
Divide selected clock source by 2
1
DIV_BY_4
Divide selected clock source by 4
2
DIV_BY_8
Divide selected clock source by 8
3
ROOT_MUX
Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
4
read-write
PATH0
Select PATH0 (can be configured for FLL)
0
PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
1
PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
10
PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
11
PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
12
PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
13
PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
14
PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
15
PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
2
PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
3
PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
4
PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
5
PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
6
PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
7
PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
8
PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
9
CLK_ROOT_SELECT15
Clock Root Select Register
0x3BC
32
read-write
n
0x0
0x0
ENABLE
Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
31
32
read-write
ROOT_DIV
Selects predivider value for this clock root and DSI input.
4
6
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
0
DIV_BY_2
Divide selected clock source by 2
1
DIV_BY_4
Divide selected clock source by 4
2
DIV_BY_8
Divide selected clock source by 8
3
ROOT_MUX
Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
4
read-write
PATH0
Select PATH0 (can be configured for FLL)
0
PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
1
PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
10
PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
11
PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
12
PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
13
PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
14
PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
15
PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
2
PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
3
PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
4
PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
5
PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
6
PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
7
PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
8
PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
9
CLK_ROOT_SELECT2
Clock Root Select Register
0x388
32
read-write
n
0x0
0x0
ENABLE
Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
31
32
read-write
ROOT_DIV
Selects predivider value for this clock root and DSI input.
4
6
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
0
DIV_BY_2
Divide selected clock source by 2
1
DIV_BY_4
Divide selected clock source by 4
2
DIV_BY_8
Divide selected clock source by 8
3
ROOT_MUX
Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
4
read-write
PATH0
Select PATH0 (can be configured for FLL)
0
PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
1
PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
10
PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
11
PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
12
PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
13
PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
14
PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
15
PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
2
PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
3
PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
4
PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
5
PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
6
PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
7
PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
8
PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
9
CLK_ROOT_SELECT3
Clock Root Select Register
0x38C
32
read-write
n
0x0
0x0
ENABLE
Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
31
32
read-write
ROOT_DIV
Selects predivider value for this clock root and DSI input.
4
6
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
0
DIV_BY_2
Divide selected clock source by 2
1
DIV_BY_4
Divide selected clock source by 4
2
DIV_BY_8
Divide selected clock source by 8
3
ROOT_MUX
Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
4
read-write
PATH0
Select PATH0 (can be configured for FLL)
0
PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
1
PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
10
PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
11
PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
12
PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
13
PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
14
PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
15
PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
2
PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
3
PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
4
PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
5
PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
6
PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
7
PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
8
PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
9
CLK_ROOT_SELECT4
Clock Root Select Register
0x390
32
read-write
n
0x0
0x0
ENABLE
Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
31
32
read-write
ROOT_DIV
Selects predivider value for this clock root and DSI input.
4
6
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
0
DIV_BY_2
Divide selected clock source by 2
1
DIV_BY_4
Divide selected clock source by 4
2
DIV_BY_8
Divide selected clock source by 8
3
ROOT_MUX
Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
4
read-write
PATH0
Select PATH0 (can be configured for FLL)
0
PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
1
PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
10
PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
11
PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
12
PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
13
PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
14
PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
15
PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
2
PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
3
PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
4
PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
5
PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
6
PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
7
PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
8
PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
9
CLK_ROOT_SELECT5
Clock Root Select Register
0x394
32
read-write
n
0x0
0x0
ENABLE
Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
31
32
read-write
ROOT_DIV
Selects predivider value for this clock root and DSI input.
4
6
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
0
DIV_BY_2
Divide selected clock source by 2
1
DIV_BY_4
Divide selected clock source by 4
2
DIV_BY_8
Divide selected clock source by 8
3
ROOT_MUX
Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
4
read-write
PATH0
Select PATH0 (can be configured for FLL)
0
PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
1
PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
10
PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
11
PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
12
PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
13
PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
14
PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
15
PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
2
PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
3
PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
4
PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
5
PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
6
PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
7
PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
8
PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
9
CLK_ROOT_SELECT6
Clock Root Select Register
0x398
32
read-write
n
0x0
0x0
ENABLE
Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
31
32
read-write
ROOT_DIV
Selects predivider value for this clock root and DSI input.
4
6
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
0
DIV_BY_2
Divide selected clock source by 2
1
DIV_BY_4
Divide selected clock source by 4
2
DIV_BY_8
Divide selected clock source by 8
3
ROOT_MUX
Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
4
read-write
PATH0
Select PATH0 (can be configured for FLL)
0
PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
1
PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
10
PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
11
PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
12
PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
13
PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
14
PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
15
PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
2
PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
3
PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
4
PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
5
PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
6
PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
7
PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
8
PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
9
CLK_ROOT_SELECT7
Clock Root Select Register
0x39C
32
read-write
n
0x0
0x0
ENABLE
Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
31
32
read-write
ROOT_DIV
Selects predivider value for this clock root and DSI input.
4
6
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
0
DIV_BY_2
Divide selected clock source by 2
1
DIV_BY_4
Divide selected clock source by 4
2
DIV_BY_8
Divide selected clock source by 8
3
ROOT_MUX
Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
4
read-write
PATH0
Select PATH0 (can be configured for FLL)
0
PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
1
PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
10
PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
11
PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
12
PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
13
PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
14
PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
15
PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
2
PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
3
PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
4
PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
5
PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
6
PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
7
PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
8
PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
9
CLK_ROOT_SELECT8
Clock Root Select Register
0x3A0
32
read-write
n
0x0
0x0
ENABLE
Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
31
32
read-write
ROOT_DIV
Selects predivider value for this clock root and DSI input.
4
6
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
0
DIV_BY_2
Divide selected clock source by 2
1
DIV_BY_4
Divide selected clock source by 4
2
DIV_BY_8
Divide selected clock source by 8
3
ROOT_MUX
Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
4
read-write
PATH0
Select PATH0 (can be configured for FLL)
0
PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
1
PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
10
PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
11
PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
12
PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
13
PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
14
PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
15
PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
2
PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
3
PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
4
PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
5
PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
6
PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
7
PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
8
PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
9
CLK_ROOT_SELECT9
Clock Root Select Register
0x3A4
32
read-write
n
0x0
0x0
ENABLE
Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.
31
32
read-write
ROOT_DIV
Selects predivider value for this clock root and DSI input.
4
6
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
0
DIV_BY_2
Divide selected clock source by 2
1
DIV_BY_4
Divide selected clock source by 4
2
DIV_BY_8
Divide selected clock source by 8
3
ROOT_MUX
Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_PATH_SELECT[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior.
0
4
read-write
PATH0
Select PATH0 (can be configured for FLL)
0
PATH1
Select PATH1 (can be configured for PLL0, if available in the product)
1
PATH10
Select PATH10 (can be configured for PLL9, if available in the product)
10
PATH11
Select PATH11 (can be configured for PLL10, if available in the product)
11
PATH12
Select PATH12 (can be configured for PLL11, if available in the product)
12
PATH13
Select PATH13 (can be configured for PLL12, if available in the product)
13
PATH14
Select PATH14 (can be configured for PLL13, if available in the product)
14
PATH15
Select PATH15 (can be configured for PLL14, if available in the product)
15
PATH2
Select PATH2 (can be configured for PLL1, if available in the product)
2
PATH3
Select PATH3 (can be configured for PLL2, if available in the product)
3
PATH4
Select PATH4 (can be configured for PLL3, if available in the product)
4
PATH5
Select PATH5 (can be configured for PLL4, if available in the product)
5
PATH6
Select PATH6 (can be configured for PLL5, if available in the product)
6
PATH7
Select PATH7 (can be configured for PLL6, if available in the product)
7
PATH8
Select PATH8 (can be configured for PLL7, if available in the product)
8
PATH9
Select PATH9 (can be configured for PLL8, if available in the product)
9
CLK_SELECT
Clock selection register
0x500
32
read-write
n
0x0
0x0
LFCLK_SEL
Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.
0
2
read-write
ILO
ILO - Internal Low-speed Oscillator
0
WCO
WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly configured (including external watch crystal, if used).
1
ALTLF
ALTLF - Alternate Low-Frequency Clock. Capability is product-specific
2
PILO
PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not work in HIBERNATE mode.
3
PUMP_DIV
Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source.
12
15
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing.
0
DIV_BY_2
Divide selected clock source by 2
1
DIV_BY_4
Divide selected clock source by 4
2
DIV_BY_8
Divide selected clock source by 8
3
DIV_BY_16
Divide selected clock source by 16
4
PUMP_ENABLE
Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects, avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE. To change the settings, do the following: 1) If the pump clock is enabled, write PUMP_ENABLE=0 without changing PUMP_SEL and PUMP_DIV. 2) Change PUMP_SEL and PUMP_DIV to desired settings with PUMP_ENABLE=0. 3) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV.
15
16
read-write
PUMP_SEL
Selects clock PATH, where k=PUMP_SEL. The output of this mux goes to the PUMP_DIV to make PUMPCLK Each product has a specific number of available clock paths. Selecting a path that is not implemented on a product will result in undefined behavior. Note that this is not a glitch free mux.
8
12
read-write
CLK_TIMER_CTL
Timer Clock Control Register
0x504
32
read-write
n
0x0
0x0
ENABLE
Enable for TIMERCLK. 0: TIMERCLK is off 1: TIMERCLK is enabled
31
32
read-write
TIMER_DIV
Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TIMERCLK Allows for integer divisions in the range [1, 256]. Do not change this setting while the timer is enabled.
16
24
read-write
TIMER_HF0_DIV
Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV). Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock.
8
10
read-write
NO_DIV
Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle.
0
DIV_BY_2
Divide HFCLK0 by 2.
1
DIV_BY_4
Divide HFCLK0 by 4.
2
DIV_BY_8
Divide HFCLK0 by 8.
3
TIMER_SEL
Select source for TIMERCLK. The output of this mux can be further divided using TIMER_DIV.
0
1
read-write
IMO
IMO - Internal Main Oscillator
0
HF0_DIV
Select the output of the predivider configured by TIMER_HF0_DIV.
1
CLK_TRIM_CCO_CTL
CCO Trim Register
0x7F08
32
read-write
n
0x0
0x0
CCO_RCSTRIM
CCO reference current source trim.
0
6
read-write
CCO_STABLE_CNT
Terminal count for the stabilization counter from CCO_ENABLE until stable.
24
30
read-write
ENABLE_CNT
Enables the automatic stabilization counter.
31
32
read-write
CLK_TRIM_CCO_CTL2
CCO Trim Register 2
0x7F0C
32
read-write
n
0x0
0x0
CCO_FCTRIM1
CCO frequency 1st range calibration
0
5
read-write
CCO_FCTRIM2
CCO frequency 2nd range calibration
5
10
read-write
CCO_FCTRIM3
CCO frequency 3rd range calibration
10
15
read-write
CCO_FCTRIM4
CCO frequency 4th range calibration
15
20
read-write
CCO_FCTRIM5
CCO frequency 5th range calibration
20
25
read-write
CLK_TRIM_ECO_CTL
ECO Trim Register
0xFF20
32
read-write
n
0x0
0x0
ATRIM
Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal. 0x0 - 150mV 0x1 - 175mV 0x2 - 200mV 0x3 - 225mV 0x4 - 250mV 0x5 - 275mV 0x6 - 300mV 0x7 - 325mV 0x8 - 350mV 0x9 - 375mV 0xA - 400mV 0xB - 425mV 0xC - 450mV 0xD - 475mV 0xE - 500mV 0xF - 525mV
4
8
read-write
FTRIM
Filter Trim - 3rd harmonic oscillation
8
10
read-write
GTRIM
Gain Trim - Startup time
12
14
read-write
ITRIM
Current Trim
16
22
read-write
RTRIM
Feedback resistor Trim
10
12
read-write
WDTRIM
Watch Dog Trim - Delta voltage below steady state level 0x0 - 50mV 0x1 - 75mV 0x2 - 100mV 0x3 - 125mV 0x4 - 150mV 0x5 - 175mV 0x6 - 200mV 0x7 - 225mV
0
3
read-write
CLK_TRIM_ILO_CTL
ILO Trim Register
0xFF18
32
read-write
n
0x0
0x0
ILO_FTRIM
ILO frequency trims. LSB step size is 1.5 percent (typical) of the frequency.
0
6
read-write
CLK_TRIM_PILO_CTL
PILO Trim Register
0xFF24
32
read-write
n
0x0
0x0
PILO_CFREQ
Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. The nominal step size of the LSB is 1kHz.
0
6
read-write
PILO_COMP_TRIM
Trim for comparator bias current.
16
18
read-write
PILO_ISLOPE_TRIM
Trim for beta-multiplier current slope
26
28
read-write
PILO_NBIAS_TRIM
Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier
18
20
read-write
PILO_OSC_TRIM
Trim for current in oscillator block.
12
15
read-write
PILO_RES_TRIM
Trim for beta-multiplier branch current
20
25
read-write
PILO_VTDIFF_TRIM
Trim for VT-DIFF output (internal power supply)
28
31
read-write
CLK_TRIM_PILO_CTL2
PILO Trim Register 2
0xFF28
32
read-write
n
0x0
0x0
PILO_IREFBM_TRIM
Trim for beta-multiplier current reference
8
13
read-write
PILO_IREF_TRIM
Trim for current reference
16
24
read-write
PILO_VREF_TRIM
Trim for voltage reference
0
8
read-write
CLK_TRIM_PILO_CTL3
PILO Trim Register 3
0xFF2C
32
read-write
n
0x0
0x0
PILO_ENGOPT
Engineering options for PILO circuits 0: Short vdda to vpwr 1: Beta:mult current change 2: Iref generation Ptat current addition 3: Disable current path in secondary Beta:mult startup circuit 4: Double oscillator current 5: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block 6: Spare 7: Ptat component increase in Iref 8: vpwr_rc and vpwr_dig_rc shorting testmode 9: Switch b/w psub connection for cascode nfet for vref generation 10: Switch between sub:threshold and deep:sub:threshold stacks in comparator. 15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy.
0
16
read-write
INTR
SRSS Interrupt Register
0x700
32
read-write
n
0x0
0x0
CLK_CAL
Clock calibration counter is done. This field is reset during DEEPSLEEP mode.
5
6
read-write
HVLVD1
Interrupt for low voltage detector HVLVD1
1
2
read-write
WDT_MATCH
WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. W1C also feeds the watch dog. Missing 2 interrupts in a row will generate a reset. Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C.
0
1
read-write
INTR_CFG
SRSS Interrupt Configuration Register
0x710
32
read-write
n
0x0
0x0
HVLVD1_EDGE_SEL
Sets which edge(s) will trigger an IRQ for HVLVD1
0
2
read-write
DISABLE
Disabled
0
RISING
Rising edge
1
FALLING
Falling edge
2
BOTH
Both rising and falling edges
3
INTR_MASK
SRSS Interrupt Mask Register
0x708
32
read-write
n
0x0
0x0
CLK_CAL
Mask for clock calibration done
5
6
read-write
HVLVD1
Mask for low voltage detector HVLVD1
1
2
read-write
WDT_MATCH
Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. It will not, however, disable the WDT reset generation on 2 missed interrupts. When WDT resets the chip, it also internally pends an interrupt that survives the reset. To prevent unintended ISR execution, clear SRSS_INTR.WDT_MATCH before setting this bit.
0
1
read-write
INTR_MASKED
SRSS Interrupt Masked Register
0x70C
32
read-only
n
0x0
0x0
CLK_CAL
Logical and of corresponding request and mask bits.
5
6
read-only
HVLVD1
Logical and of corresponding request and mask bits.
1
2
read-only
WDT_MATCH
Logical and of corresponding request and mask bits.
0
1
read-only
INTR_SET
SRSS Interrupt Set Register
0x704
32
read-write
n
0x0
0x0
CLK_CAL
Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode.
5
6
read-write
HVLVD1
Set interrupt for low voltage detector HVLVD1
1
2
read-write
WDT_MATCH
Set interrupt for low voltage detector WDT_MATCH
0
1
read-write
MCWDT_CNTHIGH
Multi-Counter Watchdog Sub-counter 2
0x8
32
read-write
n
0x0
0x0
WDT_CTR2
Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled
0
32
read-write
MCWDT_CNTLOW
Multi-Counter Watchdog Sub-counters 0/1
0x4
32
read-write
n
0x0
0x0
WDT_CTR0
Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled.
0
16
read-write
WDT_CTR1
Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled
16
32
read-write
MCWDT_CONFIG
Multi-Counter Watchdog Counter Configuration
0x10
32
read-write
n
0x0
0x0
WDT_BITS2
Bit to observe for WDT_INT2: 0: Assert after bit0 of WDT_CTR2 toggles (one int every tick) ... 31: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks)
24
29
read-write
WDT_CASCADE0_1
Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0. 0: Independent counters 1: Cascaded counters
3
4
read-write
WDT_CASCADE1_2
Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters. 0: Independent counters 1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1.
11
12
read-write
WDT_CLEAR0
Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH0 is 1.
2
3
read-write
WDT_CLEAR1
Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH1 is 1.
10
11
read-write
WDT_MODE0
Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0).
0
2
read-write
NOTHING
Do nothing
0
INT
Assert WDT_INTx
1
RESET
Assert WDT Reset
2
INT_THEN_RESET
Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt
3
WDT_MODE1
Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1).
8
10
read-write
NOTHING
Do nothing
0
INT
Assert WDT_INTx
1
RESET
Assert WDT Reset
2
INT_THEN_RESET
Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt
3
WDT_MODE2
Watchdog Counter 2 Mode.
16
17
read-write
NOTHING
Free running counter with no interrupt requests
0
INT
Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2).
1
MCWDT_CTL
Multi-Counter Watchdog Counter Control
0x14
32
read-write
n
0x0
0x0
WDT_ENABLE0
Enable subcounter 0. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up)
0
1
read-write
WDT_ENABLE1
Enable subcounter 1. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up)
8
9
read-write
WDT_ENABLE2
Enable subcounter 2. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up)
16
17
read-write
WDT_ENABLED0
Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles.
1
2
read-only
WDT_ENABLED1
Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles.
9
10
read-only
WDT_ENABLED2
Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles.
17
18
read-only
WDT_RESET0
Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect.
3
4
read-write
WDT_RESET1
Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect.
11
12
read-write
WDT_RESET2
Resets counter 2 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect.
19
20
read-write
MCWDT_INTR
Multi-Counter Watchdog Counter Interrupt Register
0x18
32
read-write
n
0x0
0x0
MCWDT_INT0
MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3.
0
1
read-write
MCWDT_INT1
MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3.
1
2
read-write
MCWDT_INT2
MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3.
2
3
read-write
MCWDT_INTR_MASK
Multi-Counter Watchdog Counter Interrupt Mask Register
0x20
32
read-write
n
0x0
0x0
MCWDT_INT0
Mask for sub-counter 0
0
1
read-write
MCWDT_INT1
Mask for sub-counter 1
1
2
read-write
MCWDT_INT2
Mask for sub-counter 2
2
3
read-write
MCWDT_INTR_MASKED
Multi-Counter Watchdog Counter Interrupt Masked Register
0x24
32
read-only
n
0x0
0x0
MCWDT_INT0
Logical and of corresponding request and mask bits.
0
1
read-only
MCWDT_INT1
Logical and of corresponding request and mask bits.
1
2
read-only
MCWDT_INT2
Logical and of corresponding request and mask bits.
2
3
read-only
MCWDT_INTR_SET
Multi-Counter Watchdog Counter Interrupt Set Register
0x1C
32
read-write
n
0x0
0x0
MCWDT_INT0
Set interrupt for MCWDT_INT0
0
1
read-write
MCWDT_INT1
Set interrupt for MCWDT_INT1
1
2
read-write
MCWDT_INT2
Set interrupt for MCWDT_INT2
2
3
read-write
MCWDT_LOCK
Multi-Counter Watchdog Counter Lock Register
0x28
32
read-write
n
0x0
0x0
MCWDT_LOCK
Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. Note that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that.
30
32
read-write
NO_CHG
No effect
0
CLR0
Clears bit 0
1
CLR1
Clears bit 1
2
SET01
Sets both bits 0 and 1
3
MCWDT_MATCH
Multi-Counter Watchdog Counter Match Register
0xC
32
read-write
n
0x0
0x0
WDT_MATCH0
Match value for sub-counter 0 of this MCWDT
0
16
read-write
WDT_MATCH1
Match value for sub-counter 1 of this MCWDT
16
32
read-write
PWR_BUCK_CTL
Buck Control Register
0x14
32
read-write
n
0x0
0x0
BUCK_EN
Master enable for buck converter. This register is only reset by XRES/POR/BOD/HIBERNATE.
30
31
read-write
BUCK_OUT1_EN
Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES/POR/BOD/HIBERNATE. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1. TRM must follow the SAS.
31
32
read-write
BUCK_OUT1_SEL
Voltage output selection for vccbuck1 output. This register is only reset by XRES/POR/BOD/HIBERNATE. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 0.85V 1: 0.875V 2: 0.90V 3: 0.95V 4: 1.05V 5: 1.10V 6: 1.15V 7: 1.20V
0
3
read-write
PWR_BUCK_CTL2
Buck Control Register 2
0x18
32
read-write
n
0x0
0x0
BUCK_OUT2_EN
Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time.
31
32
read-write
BUCK_OUT2_HW_SEL
Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead. If the product has supporting hardware, it can directly control the enable signal for vccbuck2. The same charging time in BUCK_OUT2_EN applies.
30
31
read-write
BUCK_OUT2_SEL
Voltage output selection for vccbuck2 output. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 1.15V 1: 1.20V 2: 1.25V 3: 1.30V 4: 1.35V 5: 1.40V 6: 1.45V 7: 1.50V
0
3
read-write
PWR_CTL
Power Mode Control
0x0
32
read-write
n
0x0
0x0
ACT_REF_DIS
Disables the Active Reference. Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference. When enabling the Active Reference, use ACT_REF_OK indicator to know when it is ready. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Active Reference is enabled 1: Active Reference is disabled
30
31
read-write
ACT_REF_OK
Indicates that the normal mode of the Active Reference is ready.
31
32
read-only
BGREF_LPMODE
Control the power mode of the Bandgap Voltage and Current References. This applies to voltage and current generation and is different than the reference voltage buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. When lower power mode is used, the Active Reference circuit can be disabled to reduce current. Firmware is responsible to ensure ACT_REF_OK==1 before changing back to normal mode. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Active Bandgap Voltage and Current Reference operates in normal mode. They work for vddd ramp rates of 100mV/us or less. 1: Active Bandgap Voltage and Current Reference operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. The Active Reference may be disabled using ACT_REF_DIS=0.
26
27
read-write
DEBUG_SESSION
Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)
4
5
read-only
NO_SESSION
No debug session active
0
SESSION_ACTIVE
Debug session is active. Power modes behave differently to keep the debug session active.
1
DPSLP_REG_DIS
Disable the DeepSleep regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: DeepSleep Regulator is on. 1: DeepSleep Regulator is off.
20
21
read-write
IREF_LPMODE
Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Current reference generator operates in normal mode. It works for vddd ramp rates of 100mV/us or less. 1: Current reference generator operates in low power mode. Response time is reduced to save current, and it works for vddd ramp rates of 10mV/us or less.
18
19
read-write
LINREG_DIS
Disable the linear Core Regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Linear regulator is on. 1: Linear regulator is off.
23
24
read-write
LINREG_LPMODE
Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Linear Regulator operates in normal mode. Internal current consumption is 50uA and load current capability is 50mA to 300mA, depending on the number of regulator modules present in the product. 1: Linear Regulator operates in low power mode. Internal current consumption is 5uA and load current capability is 25mA. Firmware must ensure the current is kept within the limit.
24
25
read-write
LPM_READY
Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES/POR/BOD/HIBERNATE wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode. 1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers.
5
6
read-only
NWELL_REG_DIS
Disable the Nwell regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Nwell Regulator is on. 1: Nwell Regulator is off.
22
23
read-write
PLL_LS_BYPASS
Bypass level shifter inside the PLL. 0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage. 1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current.
27
28
read-write
PORBOD_LPMODE
Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: POR/BOD circuits operate in normal mode. They work for vddd ramp rates of 100mV/us or less. 1: POR/BOD circuits operate in low power mode. Response time is reduced to save current, and they work for vddd ramp rates of 10mV/us or less.
25
26
read-write
POWER_MODE
Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon.
0
2
read-only
RESET
System is resetting.
0
ACTIVE
At least one CPU is running.
1
SLEEP
No CPUs are running. Peripherals may be running.
2
DEEPSLEEP
Main high-frequency clock is off low speed clocks are available. Communication interface clocks may be present.
3
RET_REG_DIS
Disable the Retention regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Retention Regulator is on. 1: Retention Regulator is off.
21
22
read-write
VREFBUF_DIS
Disable the 800mV voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES/POR/BOD/HIBERNATE.
29
30
read-write
VREFBUF_LPMODE
Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. 0: Voltage Reference Buffer operates in normal mode. They work for vddd ramp rates of 100mV/us or less. This register is only reset by XRES/POR/BOD/HIBERNATE. 1: Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less.
28
29
read-write
VREFBUF_OK
Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1.
19
20
read-only
PWR_HIBERNATE
HIBERNATE Mode Register
0x4
32
read-write
n
0x0
0x0
FREEZE
Firmware sets this bit to freeze the configuration, mode and state of all GPIOs and SIOs in the system. When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This occurs even in the illegal condition where UNLOCK is not set. If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write.
17
18
read-write
HIBERNATE
Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a previous write operations. Otherwise, it will not enter HIBERNATE. External supplies must have been stable for 250us before entering HIBERNATE mode.
31
32
read-write
HIBERNATE_DISABLE
Hibernate disable bit. 0: Normal operation, HIBERNATE works as described 1: Further writes to this register are ignored Note: This bit is a write-once bit until the next reset. Avoid changing any other bits in this register while disabling HIBERNATE mode. Also, it is recommended to clear the UNLOCK code, if it was previously written..
30
31
read-write
MASK_HIBALARM
When set, HIBERNATE will wakeup for a RTC interrupt
18
19
read-write
MASK_HIBPIN
When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the wakeup pins.
24
28
read-write
MASK_HIBWDT
When set, HIBERNATE will wakeup if WDT matches
19
20
read-write
POLARITY_HIBPIN
Each bit sets the active polarity of the corresponding wakeup pin. 0: Pin input of 0 will wakeup the part from HIBERNATE 1: Pin input of 1 will wakeup the part from HIBERNATE
20
24
read-write
TOKEN
Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register.
0
8
read-write
UNLOCK
This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description.
8
16
read-write
PWR_HIB_DATA0
HIBERNATE Data Register
0x80
32
read-write
n
0x0
0x0
HIB_DATA
Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
0
32
read-write
PWR_HIB_DATA1
HIBERNATE Data Register
0x84
32
read-write
n
0x0
0x0
HIB_DATA
Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
0
32
read-write
PWR_HIB_DATA10
HIBERNATE Data Register
0xA8
32
read-write
n
0x0
0x0
HIB_DATA
Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
0
32
read-write
PWR_HIB_DATA11
HIBERNATE Data Register
0xAC
32
read-write
n
0x0
0x0
HIB_DATA
Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
0
32
read-write
PWR_HIB_DATA12
HIBERNATE Data Register
0xB0
32
read-write
n
0x0
0x0
HIB_DATA
Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
0
32
read-write
PWR_HIB_DATA13
HIBERNATE Data Register
0xB4
32
read-write
n
0x0
0x0
HIB_DATA
Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
0
32
read-write
PWR_HIB_DATA14
HIBERNATE Data Register
0xB8
32
read-write
n
0x0
0x0
HIB_DATA
Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
0
32
read-write
PWR_HIB_DATA15
HIBERNATE Data Register
0xBC
32
read-write
n
0x0
0x0
HIB_DATA
Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
0
32
read-write
PWR_HIB_DATA2
HIBERNATE Data Register
0x88
32
read-write
n
0x0
0x0
HIB_DATA
Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
0
32
read-write
PWR_HIB_DATA3
HIBERNATE Data Register
0x8C
32
read-write
n
0x0
0x0
HIB_DATA
Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
0
32
read-write
PWR_HIB_DATA4
HIBERNATE Data Register
0x90
32
read-write
n
0x0
0x0
HIB_DATA
Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
0
32
read-write
PWR_HIB_DATA5
HIBERNATE Data Register
0x94
32
read-write
n
0x0
0x0
HIB_DATA
Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
0
32
read-write
PWR_HIB_DATA6
HIBERNATE Data Register
0x98
32
read-write
n
0x0
0x0
HIB_DATA
Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
0
32
read-write
PWR_HIB_DATA7
HIBERNATE Data Register
0x9C
32
read-write
n
0x0
0x0
HIB_DATA
Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
0
32
read-write
PWR_HIB_DATA8
HIBERNATE Data Register
0xA0
32
read-write
n
0x0
0x0
HIB_DATA
Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
0
32
read-write
PWR_HIB_DATA9
HIBERNATE Data Register
0xA4
32
read-write
n
0x0
0x0
HIB_DATA
Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register.
0
32
read-write
PWR_LVD_CTL
Low Voltage Detector (LVD) Configuration Register
0x8
32
read-write
n
0x0
0x0
HVLVD1_EN
Enable HVLVD1 voltage monitor. When the LVD is enabled, it takes 20us for it to settle. There is no hardware stabilization counter, and it may falsely trigger during settling. It is recommended that firmware keep the interrupt masked for at least 8us, write a 1'b1 to the corresponding SRSS_INTR field to any falsely pended interrupt, and then optionally unmask the interrupt. After enabling, it is further recommended to read the related PWR_LVD_STATUS field, since the interrupt only triggers on edges. This bit is cleared (LVD is disabled) when entering DEEPSLEEP to prevent false interrupts during wakeup.
7
8
read-write
HVLVD1_SRCSEL
Source selection for HVLVD1
4
7
read-write
VDDD
Select VDDD
0
AMUXBUSA
Select AMUXBUSA (VDDD branch)
1
RSVD
N/A
2
VDDIO
N/A
3
AMUXBUSB
Select AMUXBUSB (VDDD branch)
4
HVLVD1_TRIPSEL
Threshold selection for HVLVD1. Disable the LVD (HVLVD1_EN=0) before changing the threshold. 0: rise=1.225V (nom), fall=1.2V (nom) 1: rise=1.425V (nom), fall=1.4V (nom) 2: rise=1.625V (nom), fall=1.6V (nom) 3: rise=1.825V (nom), fall=1.8V (nom) 4: rise=2.025V (nom), fall=2V (nom) 5: rise=2.125V (nom), fall=2.1V (nom) 6: rise=2.225V (nom), fall=2.2V (nom) 7: rise=2.325V (nom), fall=2.3V (nom) 8: rise=2.425V (nom), fall=2.4V (nom) 9: rise=2.525V (nom), fall=2.5V (nom) 10: rise=2.625V (nom), fall=2.6V (nom) 11: rise=2.725V (nom), fall=2.7V (nom) 12: rise=2.825V (nom), fall=2.8V (nom) 13: rise=2.925V (nom), fall=2.9V (nom) 14: rise=3.025V (nom), fall=3.0V (nom) 15: rise=3.125V (nom), fall=3.1V (nom)
0
4
read-write
PWR_LVD_STATUS
Low Voltage Detector (LVD) Status Register
0x1C
32
read-only
n
0x0
0x0
HVLVD1_OK
HVLVD1 output. 0: below voltage threshold 1: above voltage threshold
0
1
read-only
PWR_TRIM_BODOVP_CTL
BOD/OVP Trim Register
0x7F04
32
read-write
n
0x0
0x0
HVPORBOD_ITRIM
HVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE.
7
10
read-write
HVPORBOD_OFSTRIM
HVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE.
4
7
read-write
HVPORBOD_TRIPSEL
HVPORBOD trip point selection. Monitors vddd. This register is only reset by XRES/POR/BOD/HIBERNATE.
0
3
read-write
LVPORBOD_ITRIM
LVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE.
17
20
read-write
LVPORBOD_OFSTRIM
LVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE.
14
17
read-write
LVPORBOD_TRIPSEL
LVPORBOD trip point selection. Monitors vccd. This register is only reset by XRES/POR/BOD/HIBERNATE.
10
13
read-write
PWR_TRIM_LVD_CTL
LVD Trim Register
0xFF10
32
read-write
n
0x0
0x0
HVLVD1_ITRIM
HVLVD1 current trim
4
7
read-write
HVLVD1_OFSTRIM
HVLVD1 offset trim
0
3
read-write
PWR_TRIM_PWRSYS_CTL
Power System Trim Register
0xFF1C
32
read-write
n
0x0
0x0
ACT_REG_BOOST
Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting: 2'b00: 50uA 2'b01: 100uA 2'b10: 150uA 2'b11: 200uA The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip. 50mA chip: 2'b00 (default) 100mA chip: 2'b00 (default) 150mA chip: 50..100mA app => 2'b00, 150mA app => 2'b01 (default) 200mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200mA app => 2'b10 (default) 250mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10 (default) 300mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10, 300mA app => 2'b11 (default) This register is only reset by XRES/POR/BOD/HIBERNATE.
30
32
read-write
ACT_REG_TRIM
Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES/POR/BOD/HIBERNATE. Two voltages are supported: 0.9V and 1.1V. The codes for these are stored in SFLASH_LDO_0P9V_TRIM and SFLASH_LDO_1P1V_TRIM, respectively.
0
5
read-write
PWR_TRIM_REF_CTL
Reference Trim Register
0x7F00
32
read-write
n
0x0
0x0
ACT_REF_ABSTRIM
Active-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR not for trimming use others -> normal trim range
8
13
read-write
ACT_REF_IBOOST
Active-Reference current boost. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: normal operation others: risk mitigation
14
15
read-write
ACT_REF_ITRIM
Active-Reference current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR not for trimming use others -> normal trim range
4
8
read-write
ACT_REF_TCTRIM
Active-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR not for trimming use others -> normal trim range
0
4
read-write
DPSLP_REF_ABSTRIM
DeepSleep-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE.
20
25
read-write
DPSLP_REF_ITRIM
DeepSleep current reference trim. This register is only reset by XRES/POR/BOD/HIBERNATE.
28
32
read-write
DPSLP_REF_TCTRIM
DeepSleep-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR not for trimming use others -> normal trim range
16
20
read-write
PWR_TRIM_WAKE_CTL
Wakeup Trim Register
0x7F30
32
read-write
n
0x0
0x0
WAKE_DELAY
Wakeup holdoff. Spec (fastest) wake time is achieved with a setting of 0. Additional delay can be added for debugging or workaround. The delay is counted by the IMO.
0
8
read-write
RES_CAUSE
Reset Cause Observation Register
0x800
32
read-write
n
0x0
0x0
RESET_ACT_FAULT
Fault logging system requested a reset from its Active logic.
1
2
read-write
RESET_CSV_WCO_LOSS
Clock supervision logic requested a reset due to loss of a watch-crystal clock.
3
4
read-write
RESET_DPSLP_FAULT
Fault logging system requested a reset from its DeepSleep logic.
2
3
read-write
RESET_MCWDT0
Multi-Counter Watchdog timer reset #0 has occurred since last power cycle.
5
6
read-write
RESET_MCWDT1
Multi-Counter Watchdog timer reset #1 has occurred since last power cycle.
6
7
read-write
RESET_MCWDT2
Multi-Counter Watchdog timer reset #2 has occurred since last power cycle.
7
8
read-write
RESET_MCWDT3
Multi-Counter Watchdog timer reset #3 has occurred since last power cycle.
8
9
read-write
RESET_SOFT
A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware.
4
5
read-write
RESET_WDT
A basic WatchDog Timer (WDT) reset has occurred since last power cycle.
0
1
read-write
RES_CAUSE2
Reset Cause Observation Register 2
0x804
32
read-write
n
0x0
0x0
RESET_CSV_HF_FREQ
Clock supervision logic requested a reset due to frequency error of high-frequency clock. Each bit index K corresponds to a HFCLK. Unimplemented clock bits return zero.
16
32
read-write
RESET_CSV_HF_LOSS
Clock supervision logic requested a reset due to loss of a high-frequency clock. Each bit index K corresponds to a HFCLK. Unimplemented clock bits return zero.
0
16
read-write
WDT_CNT
Watchdog Counter Count Register
0x184
32
read-write
n
0x0
0x0
COUNTER
Current value of WDT Counter. The write feature of this register is for engineering use (DfV), have no synchronization, and can only be applied when the WDT is fully off. When writing, the value is updated immediately in the WDT counter, but it will read back as the old value until this register resynchronizes just after the negedge of ILO. Writes will be ignored if they occur when the WDT is enabled.
0
16
read-write
WDT_CTL
Watchdog Counter Control Register
0x180
32
read-write
n
0x0
0x0
WDT_EN
Enable this watchdog timer. This field is retained during DEEPSLEEP and HIBERNATE modes.
0
1
read-write
WDT_LOCK
Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers when not equal 0. Requires at least two different writes to unlock. A change in WDT_LOCK takes effect beginning with the next write cycle. Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all those registers at the same time. WDT will lock on any reset. This field is not retained during DEEPSLEEP or HIBERNATE mode, so the WDT will be locked after wakeup from these modes.
30
32
read-write
NO_CHG
No effect
0
CLR0
Clears bit 0
1
CLR1
Clears bit 1
2
SET01
Sets both bits 0 and 1
3
WDT_MATCH
Watchdog Counter Match Register
0x188
32
read-write
n
0x0
0x0
IGNORE_BITS
The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Up to 12 MSB can be ignored. Settings >12 behave like a setting of 12.
16
20
read-write
MATCH
Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match).
0
16
read-write